Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.34 97.82 93.72 97.44 73.44 96.21 98.17 96.58


Total test records in report: 2853
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T2763 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.948317780 Jul 23 05:01:00 PM PDT 24 Jul 23 05:01:15 PM PDT 24 55110735 ps
T284 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2685400762 Jul 23 05:00:54 PM PDT 24 Jul 23 05:01:09 PM PDT 24 708490349 ps
T232 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3185026126 Jul 23 05:00:22 PM PDT 24 Jul 23 05:00:27 PM PDT 24 118313839 ps
T254 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.4026071779 Jul 23 05:00:37 PM PDT 24 Jul 23 05:00:43 PM PDT 24 148295854 ps
T2764 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2192969203 Jul 23 05:00:40 PM PDT 24 Jul 23 05:00:49 PM PDT 24 126284638 ps
T255 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3495505003 Jul 23 05:00:37 PM PDT 24 Jul 23 05:00:43 PM PDT 24 91559770 ps
T282 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2525708769 Jul 23 05:01:02 PM PDT 24 Jul 23 05:01:17 PM PDT 24 60536855 ps
T256 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.59035833 Jul 23 05:00:36 PM PDT 24 Jul 23 05:00:40 PM PDT 24 52979023 ps
T2765 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2079219198 Jul 23 05:00:57 PM PDT 24 Jul 23 05:01:12 PM PDT 24 229900066 ps
T2766 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.266394012 Jul 23 05:00:40 PM PDT 24 Jul 23 05:00:48 PM PDT 24 43682518 ps
T2767 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2551931960 Jul 23 05:00:37 PM PDT 24 Jul 23 05:00:42 PM PDT 24 164850556 ps
T2768 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2461494893 Jul 23 05:00:51 PM PDT 24 Jul 23 05:00:56 PM PDT 24 67031235 ps
T288 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2579279789 Jul 23 05:00:26 PM PDT 24 Jul 23 05:00:32 PM PDT 24 858583132 ps
T2769 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1568400060 Jul 23 05:00:57 PM PDT 24 Jul 23 05:01:11 PM PDT 24 51097320 ps
T2770 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.464070382 Jul 23 05:00:53 PM PDT 24 Jul 23 05:01:02 PM PDT 24 67196420 ps
T2771 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3557772290 Jul 23 05:00:37 PM PDT 24 Jul 23 05:00:43 PM PDT 24 104125040 ps
T2772 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.540933896 Jul 23 05:00:52 PM PDT 24 Jul 23 05:00:59 PM PDT 24 58359194 ps
T2773 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1583145480 Jul 23 05:00:37 PM PDT 24 Jul 23 05:00:44 PM PDT 24 78616504 ps
T2774 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3628650922 Jul 23 05:00:56 PM PDT 24 Jul 23 05:01:09 PM PDT 24 116301991 ps
T2775 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.958600803 Jul 23 05:00:35 PM PDT 24 Jul 23 05:00:37 PM PDT 24 41890067 ps
T2776 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.409351962 Jul 23 05:00:35 PM PDT 24 Jul 23 05:00:39 PM PDT 24 284634365 ps
T2777 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1317812552 Jul 23 05:00:36 PM PDT 24 Jul 23 05:00:41 PM PDT 24 162784423 ps
T2778 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2959046645 Jul 23 05:00:37 PM PDT 24 Jul 23 05:00:44 PM PDT 24 108686273 ps
T2779 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1164143349 Jul 23 05:01:07 PM PDT 24 Jul 23 05:01:25 PM PDT 24 60208272 ps
T257 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.4243090783 Jul 23 05:00:38 PM PDT 24 Jul 23 05:00:46 PM PDT 24 124724733 ps
T259 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.740350775 Jul 23 05:00:40 PM PDT 24 Jul 23 05:00:51 PM PDT 24 335134850 ps
T2780 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2914787704 Jul 23 05:00:53 PM PDT 24 Jul 23 05:01:04 PM PDT 24 1047874745 ps
T2781 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3510620780 Jul 23 05:00:54 PM PDT 24 Jul 23 05:01:05 PM PDT 24 170770217 ps
T2782 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3660920242 Jul 23 05:00:53 PM PDT 24 Jul 23 05:01:02 PM PDT 24 60691989 ps
T2783 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3748091692 Jul 23 05:00:54 PM PDT 24 Jul 23 05:01:06 PM PDT 24 123602454 ps
T2784 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1331373239 Jul 23 05:00:58 PM PDT 24 Jul 23 05:01:13 PM PDT 24 183254670 ps
T2785 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.260373167 Jul 23 05:00:40 PM PDT 24 Jul 23 05:00:48 PM PDT 24 49009031 ps
T2786 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3089448732 Jul 23 05:00:36 PM PDT 24 Jul 23 05:00:41 PM PDT 24 57130487 ps
T2787 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2654274871 Jul 23 05:00:57 PM PDT 24 Jul 23 05:01:11 PM PDT 24 36939527 ps
T2788 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1715343247 Jul 23 05:00:37 PM PDT 24 Jul 23 05:00:45 PM PDT 24 735748986 ps
T2789 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.1254653401 Jul 23 05:01:04 PM PDT 24 Jul 23 05:01:20 PM PDT 24 40621540 ps
T260 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.733923856 Jul 23 05:00:56 PM PDT 24 Jul 23 05:01:08 PM PDT 24 60160069 ps
T2790 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1723563632 Jul 23 05:00:39 PM PDT 24 Jul 23 05:00:48 PM PDT 24 247575592 ps
T261 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1043564668 Jul 23 05:00:37 PM PDT 24 Jul 23 05:00:43 PM PDT 24 194441785 ps
T2791 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.802605868 Jul 23 05:00:36 PM PDT 24 Jul 23 05:00:45 PM PDT 24 826637136 ps
T2792 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.94689082 Jul 23 05:00:57 PM PDT 24 Jul 23 05:01:12 PM PDT 24 86346306 ps
T2793 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.4275674674 Jul 23 05:00:40 PM PDT 24 Jul 23 05:00:50 PM PDT 24 180357546 ps
T2794 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.288722797 Jul 23 05:00:37 PM PDT 24 Jul 23 05:00:43 PM PDT 24 61263033 ps
T2795 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.108465881 Jul 23 05:01:05 PM PDT 24 Jul 23 05:01:21 PM PDT 24 79516473 ps
T2796 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2043563430 Jul 23 05:00:52 PM PDT 24 Jul 23 05:01:02 PM PDT 24 711796491 ps
T2797 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1203983037 Jul 23 05:00:53 PM PDT 24 Jul 23 05:01:01 PM PDT 24 98086970 ps
T2798 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.4218194850 Jul 23 05:00:52 PM PDT 24 Jul 23 05:00:58 PM PDT 24 163875800 ps
T2799 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1093771693 Jul 23 05:01:07 PM PDT 24 Jul 23 05:01:25 PM PDT 24 36781024 ps
T2800 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3825484061 Jul 23 05:01:07 PM PDT 24 Jul 23 05:01:25 PM PDT 24 98531026 ps
T2801 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1872768647 Jul 23 05:01:03 PM PDT 24 Jul 23 05:01:19 PM PDT 24 52342152 ps
T2802 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.676189439 Jul 23 05:00:57 PM PDT 24 Jul 23 05:01:10 PM PDT 24 92440002 ps
T2803 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.662601120 Jul 23 05:01:03 PM PDT 24 Jul 23 05:01:19 PM PDT 24 55383273 ps
T2804 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.213407506 Jul 23 05:00:56 PM PDT 24 Jul 23 05:01:13 PM PDT 24 493210912 ps
T2805 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.300336179 Jul 23 05:00:57 PM PDT 24 Jul 23 05:01:11 PM PDT 24 118956609 ps
T2806 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2701574721 Jul 23 05:00:40 PM PDT 24 Jul 23 05:00:49 PM PDT 24 132166993 ps
T2807 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.136986473 Jul 23 05:00:39 PM PDT 24 Jul 23 05:00:49 PM PDT 24 124906642 ps
T2808 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2220699830 Jul 23 05:00:51 PM PDT 24 Jul 23 05:00:58 PM PDT 24 101788425 ps
T2809 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.639906501 Jul 23 05:00:57 PM PDT 24 Jul 23 05:01:10 PM PDT 24 60662123 ps
T2810 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.229385759 Jul 23 05:00:37 PM PDT 24 Jul 23 05:00:41 PM PDT 24 45850711 ps
T2811 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3029474770 Jul 23 05:00:40 PM PDT 24 Jul 23 05:00:49 PM PDT 24 90056438 ps
T2812 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2584894335 Jul 23 05:00:38 PM PDT 24 Jul 23 05:00:46 PM PDT 24 260185969 ps
T2813 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2539119519 Jul 23 05:00:53 PM PDT 24 Jul 23 05:01:04 PM PDT 24 156582010 ps
T2814 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3418639670 Jul 23 05:00:52 PM PDT 24 Jul 23 05:00:58 PM PDT 24 150911755 ps
T2815 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2099669590 Jul 23 05:00:36 PM PDT 24 Jul 23 05:00:42 PM PDT 24 171877341 ps
T2816 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.4118512889 Jul 23 05:01:09 PM PDT 24 Jul 23 05:01:28 PM PDT 24 45397524 ps
T2817 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1984829649 Jul 23 05:00:53 PM PDT 24 Jul 23 05:01:02 PM PDT 24 80824837 ps
T2818 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3020085346 Jul 23 05:00:59 PM PDT 24 Jul 23 05:01:14 PM PDT 24 54899218 ps
T2819 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3017159178 Jul 23 05:00:40 PM PDT 24 Jul 23 05:00:50 PM PDT 24 489294538 ps
T2820 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.51074810 Jul 23 05:00:56 PM PDT 24 Jul 23 05:01:10 PM PDT 24 97123457 ps
T2821 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3564964027 Jul 23 05:00:55 PM PDT 24 Jul 23 05:01:07 PM PDT 24 50925964 ps
T2822 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1068324872 Jul 23 05:00:38 PM PDT 24 Jul 23 05:00:44 PM PDT 24 90268842 ps
T2823 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.512343568 Jul 23 05:00:40 PM PDT 24 Jul 23 05:00:49 PM PDT 24 504453068 ps
T2824 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1407374575 Jul 23 05:00:50 PM PDT 24 Jul 23 05:00:55 PM PDT 24 79234525 ps
T2825 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2075514814 Jul 23 05:00:38 PM PDT 24 Jul 23 05:00:46 PM PDT 24 337915624 ps
T2826 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3899776531 Jul 23 05:00:37 PM PDT 24 Jul 23 05:00:44 PM PDT 24 136932148 ps
T2827 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3857397712 Jul 23 05:00:52 PM PDT 24 Jul 23 05:01:03 PM PDT 24 505906495 ps
T2828 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2457296007 Jul 23 05:00:57 PM PDT 24 Jul 23 05:01:12 PM PDT 24 128273247 ps
T2829 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.876015387 Jul 23 05:01:03 PM PDT 24 Jul 23 05:01:19 PM PDT 24 57123468 ps
T289 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.816201324 Jul 23 05:00:35 PM PDT 24 Jul 23 05:00:43 PM PDT 24 1151435919 ps
T2830 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1653954312 Jul 23 05:01:07 PM PDT 24 Jul 23 05:01:25 PM PDT 24 45113897 ps
T2831 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2828122932 Jul 23 05:00:37 PM PDT 24 Jul 23 05:00:44 PM PDT 24 146006416 ps
T2832 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2398560869 Jul 23 05:00:40 PM PDT 24 Jul 23 05:00:51 PM PDT 24 230892839 ps
T2833 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1922811026 Jul 23 05:00:22 PM PDT 24 Jul 23 05:00:26 PM PDT 24 80288676 ps
T2834 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2040960157 Jul 23 05:00:39 PM PDT 24 Jul 23 05:00:46 PM PDT 24 126043615 ps
T2835 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.437394693 Jul 23 05:00:51 PM PDT 24 Jul 23 05:00:56 PM PDT 24 97829525 ps
T2836 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1322095136 Jul 23 05:00:57 PM PDT 24 Jul 23 05:01:13 PM PDT 24 104474085 ps
T2837 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.4041669014 Jul 23 05:00:34 PM PDT 24 Jul 23 05:00:36 PM PDT 24 76217826 ps
T2838 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1908936227 Jul 23 05:00:39 PM PDT 24 Jul 23 05:00:47 PM PDT 24 55963103 ps
T2839 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1075420029 Jul 23 05:00:35 PM PDT 24 Jul 23 05:00:37 PM PDT 24 88385310 ps
T2840 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.916948688 Jul 23 05:00:38 PM PDT 24 Jul 23 05:00:46 PM PDT 24 108844432 ps
T2841 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2643929498 Jul 23 05:00:39 PM PDT 24 Jul 23 05:00:46 PM PDT 24 35055424 ps
T2842 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3798621346 Jul 23 05:00:23 PM PDT 24 Jul 23 05:00:28 PM PDT 24 152272800 ps
T2843 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2145390323 Jul 23 05:00:38 PM PDT 24 Jul 23 05:00:46 PM PDT 24 916710880 ps
T2844 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.4177784424 Jul 23 05:00:39 PM PDT 24 Jul 23 05:00:52 PM PDT 24 1649478951 ps
T2845 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.4191346193 Jul 23 05:00:38 PM PDT 24 Jul 23 05:00:47 PM PDT 24 219515679 ps
T2846 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3730627713 Jul 23 05:00:37 PM PDT 24 Jul 23 05:00:42 PM PDT 24 151671166 ps
T2847 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2218070394 Jul 23 05:00:52 PM PDT 24 Jul 23 05:00:58 PM PDT 24 68437300 ps
T2848 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.48147305 Jul 23 05:00:38 PM PDT 24 Jul 23 05:00:44 PM PDT 24 71870411 ps
T2849 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.270173627 Jul 23 05:01:01 PM PDT 24 Jul 23 05:01:16 PM PDT 24 95047626 ps
T2850 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2768619813 Jul 23 05:01:09 PM PDT 24 Jul 23 05:01:27 PM PDT 24 66035324 ps
T2851 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1485971608 Jul 23 05:00:37 PM PDT 24 Jul 23 05:00:44 PM PDT 24 243724306 ps
T2852 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.558587496 Jul 23 05:00:40 PM PDT 24 Jul 23 05:00:51 PM PDT 24 281319793 ps
T2853 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2620441302 Jul 23 05:00:55 PM PDT 24 Jul 23 05:01:08 PM PDT 24 214525842 ps

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.397290556
Short name T8
Test name
Test status
Simulation time 23374373800 ps
CPU time 22.57 seconds
Started Jul 23 06:44:53 PM PDT 24
Finished Jul 23 06:45:21 PM PDT 24
Peak memory 206960 kb
Host smart-c7daa2ce-2612-4804-a398-74d36b00f8d3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=397290556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.397290556
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_device_address.2758058272
Short name T29
Test name
Test status
Simulation time 13690744977 ps
CPU time 28.78 seconds
Started Jul 23 06:38:50 PM PDT 24
Finished Jul 23 06:39:21 PM PDT 24
Peak memory 206984 kb
Host smart-40a8e261-662e-42aa-998f-b49779cef425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27580
58272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.2758058272
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2674770439
Short name T202
Test name
Test status
Simulation time 129302446 ps
CPU time 0.76 seconds
Started Jul 23 05:01:03 PM PDT 24
Finished Jul 23 05:01:19 PM PDT 24
Peak memory 206460 kb
Host smart-727b37d5-6856-4407-b3e3-e746b9e61525
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2674770439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.2674770439
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2262766775
Short name T191
Test name
Test status
Simulation time 823761551 ps
CPU time 4.49 seconds
Started Jul 23 05:00:43 PM PDT 24
Finished Jul 23 05:00:54 PM PDT 24
Peak memory 206852 kb
Host smart-85a52b20-0249-4fc1-a874-1bea59ce4266
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2262766775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.2262766775
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.2898348384
Short name T102
Test name
Test status
Simulation time 173990135 ps
CPU time 0.81 seconds
Started Jul 23 06:46:37 PM PDT 24
Finished Jul 23 06:46:44 PM PDT 24
Peak memory 206712 kb
Host smart-7e1eaec7-da36-494c-8199-a78be96aea30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28983
48384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.2898348384
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.106256427
Short name T275
Test name
Test status
Simulation time 41196108 ps
CPU time 0.68 seconds
Started Jul 23 05:00:59 PM PDT 24
Finished Jul 23 05:01:13 PM PDT 24
Peak memory 206476 kb
Host smart-87b493d2-ea38-4045-99bd-595ca069fbfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=106256427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.106256427
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/default/14.usbdev_iso_retraction.1872273665
Short name T4
Test name
Test status
Simulation time 8394468083 ps
CPU time 27.21 seconds
Started Jul 23 06:40:47 PM PDT 24
Finished Jul 23 06:41:15 PM PDT 24
Peak memory 206952 kb
Host smart-c2efdd89-815e-43ec-a083-92700b8fb2b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18722
73665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.1872273665
Directory /workspace/14.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.2566556690
Short name T1
Test name
Test status
Simulation time 204987424 ps
CPU time 0.85 seconds
Started Jul 23 06:40:24 PM PDT 24
Finished Jul 23 06:40:27 PM PDT 24
Peak memory 206764 kb
Host smart-d39f5214-5c0b-4301-949d-0deaf4f8e0f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25665
56690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.2566556690
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.3723376976
Short name T39
Test name
Test status
Simulation time 141238321 ps
CPU time 0.74 seconds
Started Jul 23 06:42:48 PM PDT 24
Finished Jul 23 06:42:53 PM PDT 24
Peak memory 206772 kb
Host smart-44ad089a-8af9-40b9-b021-eb747c37c336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37233
76976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.3723376976
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.801328489
Short name T226
Test name
Test status
Simulation time 339117924 ps
CPU time 3.35 seconds
Started Jul 23 05:00:37 PM PDT 24
Finished Jul 23 05:00:45 PM PDT 24
Peak memory 216080 kb
Host smart-39bd3e22-4f6b-4900-a0ef-e914608306fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=801328489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.801328489
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.2173354426
Short name T188
Test name
Test status
Simulation time 1545341781 ps
CPU time 2.45 seconds
Started Jul 23 06:36:50 PM PDT 24
Finished Jul 23 06:36:55 PM PDT 24
Peak memory 225532 kb
Host smart-74205661-e4f7-46ee-b029-4b21d86b1c3d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2173354426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.2173354426
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.4273202022
Short name T484
Test name
Test status
Simulation time 13348088000 ps
CPU time 14.45 seconds
Started Jul 23 06:41:23 PM PDT 24
Finished Jul 23 06:41:43 PM PDT 24
Peak memory 206968 kb
Host smart-e876a5d4-65c0-4df0-a177-a2bf83ea814d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4273202022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.4273202022
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.3239730342
Short name T42
Test name
Test status
Simulation time 1394510037 ps
CPU time 3.18 seconds
Started Jul 23 06:41:17 PM PDT 24
Finished Jul 23 06:41:29 PM PDT 24
Peak memory 206900 kb
Host smart-5fd8e6c3-be1c-485e-994c-810a40e46bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32397
30342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.3239730342
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.1930436560
Short name T27
Test name
Test status
Simulation time 38916470 ps
CPU time 0.66 seconds
Started Jul 23 06:40:10 PM PDT 24
Finished Jul 23 06:40:13 PM PDT 24
Peak memory 206716 kb
Host smart-ecdf0185-7636-4ce4-8b1f-3cf07e08fbaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19304
36560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.1930436560
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.2398411875
Short name T294
Test name
Test status
Simulation time 171876633 ps
CPU time 0.9 seconds
Started Jul 23 06:40:23 PM PDT 24
Finished Jul 23 06:40:26 PM PDT 24
Peak memory 206752 kb
Host smart-a8e747d8-1d48-4782-8868-7e233f0aab6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23984
11875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.2398411875
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3523927761
Short name T204
Test name
Test status
Simulation time 64642057 ps
CPU time 0.71 seconds
Started Jul 23 05:00:53 PM PDT 24
Finished Jul 23 05:01:01 PM PDT 24
Peak memory 206532 kb
Host smart-93e99e08-4645-41e9-a1e7-9fd2e5d32d4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3523927761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.3523927761
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.3764574135
Short name T80
Test name
Test status
Simulation time 311777305 ps
CPU time 1.01 seconds
Started Jul 23 06:36:37 PM PDT 24
Finished Jul 23 06:36:40 PM PDT 24
Peak memory 206764 kb
Host smart-0288f0e9-3b71-4efb-b696-e0afe434b7e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37645
74135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.3764574135
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.2667977617
Short name T44
Test name
Test status
Simulation time 11205752674 ps
CPU time 73.21 seconds
Started Jul 23 06:38:26 PM PDT 24
Finished Jul 23 06:39:41 PM PDT 24
Peak memory 207012 kb
Host smart-77ac24a2-492e-480f-813e-f1ee31994e3a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2667977617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.2667977617
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.3967099117
Short name T47
Test name
Test status
Simulation time 20176304655 ps
CPU time 19.78 seconds
Started Jul 23 06:36:37 PM PDT 24
Finished Jul 23 06:36:58 PM PDT 24
Peak memory 206792 kb
Host smart-1066a406-2f37-4203-a154-54e306e88f31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39670
99117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.3967099117
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.378915210
Short name T956
Test name
Test status
Simulation time 270643945 ps
CPU time 1 seconds
Started Jul 23 06:40:05 PM PDT 24
Finished Jul 23 06:40:09 PM PDT 24
Peak memory 206772 kb
Host smart-ff7b9be4-1fb3-4704-b55d-a3400d080736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37891
5210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.378915210
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2917621197
Short name T249
Test name
Test status
Simulation time 47239198 ps
CPU time 0.84 seconds
Started Jul 23 05:00:36 PM PDT 24
Finished Jul 23 05:00:41 PM PDT 24
Peak memory 206604 kb
Host smart-a9e03952-c303-41eb-93c9-bbe491fdce20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2917621197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.2917621197
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.969169739
Short name T278
Test name
Test status
Simulation time 202236500 ps
CPU time 0.88 seconds
Started Jul 23 06:42:34 PM PDT 24
Finished Jul 23 06:42:36 PM PDT 24
Peak memory 206756 kb
Host smart-c5f266b5-3d40-4313-a1ba-a7b33f36d805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96916
9739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.969169739
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.452211164
Short name T279
Test name
Test status
Simulation time 64604411 ps
CPU time 0.78 seconds
Started Jul 23 05:00:36 PM PDT 24
Finished Jul 23 05:00:41 PM PDT 24
Peak memory 206508 kb
Host smart-78a22d4d-cc8d-48d6-ae7b-37c04a5973e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=452211164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.452211164
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.87251495
Short name T46
Test name
Test status
Simulation time 3720287453 ps
CPU time 4.58 seconds
Started Jul 23 06:39:35 PM PDT 24
Finished Jul 23 06:39:42 PM PDT 24
Peak memory 206848 kb
Host smart-2a7ea845-a16d-4128-9a07-f6eac31aa467
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=87251495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.87251495
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.110236981
Short name T75
Test name
Test status
Simulation time 161315394 ps
CPU time 0.84 seconds
Started Jul 23 06:45:37 PM PDT 24
Finished Jul 23 06:45:43 PM PDT 24
Peak memory 206784 kb
Host smart-87ff29d9-612f-413d-b3c4-31c002825cf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11023
6981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.110236981
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.2450610227
Short name T70
Test name
Test status
Simulation time 468331715 ps
CPU time 1.25 seconds
Started Jul 23 06:36:20 PM PDT 24
Finished Jul 23 06:36:23 PM PDT 24
Peak memory 206752 kb
Host smart-d55d32f4-b957-415e-b9d4-e79513a1616c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24506
10227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.2450610227
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.2421215297
Short name T162
Test name
Test status
Simulation time 4762745165 ps
CPU time 32.69 seconds
Started Jul 23 06:38:25 PM PDT 24
Finished Jul 23 06:38:59 PM PDT 24
Peak memory 206908 kb
Host smart-b8fdb640-c38d-41b8-a036-b1d476aa972e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2421215297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.2421215297
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.58610352
Short name T276
Test name
Test status
Simulation time 41169061 ps
CPU time 0.68 seconds
Started Jul 23 05:00:26 PM PDT 24
Finished Jul 23 05:00:29 PM PDT 24
Peak memory 206412 kb
Host smart-cfc63f96-b205-45bf-a4de-8c26f89613c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=58610352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.58610352
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2579279789
Short name T288
Test name
Test status
Simulation time 858583132 ps
CPU time 4.51 seconds
Started Jul 23 05:00:26 PM PDT 24
Finished Jul 23 05:00:32 PM PDT 24
Peak memory 206760 kb
Host smart-c80fedc9-7921-4d1b-8592-7e7fa2052144
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2579279789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.2579279789
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1419103130
Short name T285
Test name
Test status
Simulation time 553470361 ps
CPU time 4.22 seconds
Started Jul 23 05:00:56 PM PDT 24
Finished Jul 23 05:01:12 PM PDT 24
Peak memory 206848 kb
Host smart-cd486921-9f53-40e2-91ac-4e099ff9a41b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1419103130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.1419103130
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.4193449470
Short name T280
Test name
Test status
Simulation time 101707136 ps
CPU time 0.79 seconds
Started Jul 23 05:01:04 PM PDT 24
Finished Jul 23 05:01:20 PM PDT 24
Peak memory 206520 kb
Host smart-158189c9-d084-49c6-ad3f-9f24faabe564
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4193449470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.4193449470
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.388302156
Short name T472
Test name
Test status
Simulation time 36572917 ps
CPU time 0.68 seconds
Started Jul 23 06:36:49 PM PDT 24
Finished Jul 23 06:36:53 PM PDT 24
Peak memory 206764 kb
Host smart-30c2cb79-ed24-4357-8cf6-12dd674d0c6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=388302156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.388302156
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.3620200015
Short name T105
Test name
Test status
Simulation time 11439727413 ps
CPU time 323.36 seconds
Started Jul 23 06:47:16 PM PDT 24
Finished Jul 23 06:52:43 PM PDT 24
Peak memory 206904 kb
Host smart-fb453214-ea6d-4101-a518-9a9c1090a6ec
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3620200015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.3620200015
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.3448253206
Short name T58
Test name
Test status
Simulation time 244304283 ps
CPU time 0.95 seconds
Started Jul 23 06:36:38 PM PDT 24
Finished Jul 23 06:36:40 PM PDT 24
Peak memory 206672 kb
Host smart-5a48b1cf-a0de-4fa7-96e2-1691a4756226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34482
53206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.3448253206
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.3201894231
Short name T65
Test name
Test status
Simulation time 143330680 ps
CPU time 0.79 seconds
Started Jul 23 06:36:11 PM PDT 24
Finished Jul 23 06:36:13 PM PDT 24
Peak memory 206736 kb
Host smart-0154cb8c-f164-4817-9094-18d932023172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32018
94231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.3201894231
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.1122207234
Short name T94
Test name
Test status
Simulation time 8672903299 ps
CPU time 230.39 seconds
Started Jul 23 06:44:59 PM PDT 24
Finished Jul 23 06:48:55 PM PDT 24
Peak memory 206880 kb
Host smart-d07f0233-0c56-41a2-9cdc-34735176d3df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11222
07234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.1122207234
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_device_address.3238047154
Short name T176
Test name
Test status
Simulation time 8645222661 ps
CPU time 16.71 seconds
Started Jul 23 06:46:26 PM PDT 24
Finished Jul 23 06:46:46 PM PDT 24
Peak memory 206892 kb
Host smart-998560ce-f4bb-4f73-a5d8-e5b35393e670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32380
47154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.3238047154
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.2469188682
Short name T567
Test name
Test status
Simulation time 148627817 ps
CPU time 0.77 seconds
Started Jul 23 06:39:55 PM PDT 24
Finished Jul 23 06:39:58 PM PDT 24
Peak memory 206756 kb
Host smart-6be58ac1-41fb-4d7a-bae8-d24d70da3293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24691
88682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.2469188682
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.2344350837
Short name T184
Test name
Test status
Simulation time 23322681385 ps
CPU time 23.59 seconds
Started Jul 23 06:44:17 PM PDT 24
Finished Jul 23 06:44:43 PM PDT 24
Peak memory 206832 kb
Host smart-f91301c6-133f-44ef-a43c-3b7aaf6b361c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23443
50837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.2344350837
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.1712976516
Short name T74
Test name
Test status
Simulation time 171259819 ps
CPU time 0.79 seconds
Started Jul 23 06:37:07 PM PDT 24
Finished Jul 23 06:37:09 PM PDT 24
Peak memory 206744 kb
Host smart-0392a17a-a92d-440f-be66-a737028edeaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17129
76516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.1712976516
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.4128860629
Short name T586
Test name
Test status
Simulation time 188338883 ps
CPU time 1.58 seconds
Started Jul 23 06:39:52 PM PDT 24
Finished Jul 23 06:39:55 PM PDT 24
Peak memory 206852 kb
Host smart-0a9a9a34-e534-44d0-86cd-a36f4232897b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41288
60629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.4128860629
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.3773625445
Short name T54
Test name
Test status
Simulation time 183359172 ps
CPU time 0.8 seconds
Started Jul 23 06:36:10 PM PDT 24
Finished Jul 23 06:36:12 PM PDT 24
Peak memory 206652 kb
Host smart-297e75c6-b6b3-46b2-a26a-8e0cfd5e1f6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37736
25445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.3773625445
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.2490878493
Short name T68
Test name
Test status
Simulation time 4167148835 ps
CPU time 8.56 seconds
Started Jul 23 06:36:18 PM PDT 24
Finished Jul 23 06:36:28 PM PDT 24
Peak memory 206976 kb
Host smart-fe7f2859-c3e8-4e8e-b2ca-fe188666c6b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24908
78493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.2490878493
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.415849690
Short name T69
Test name
Test status
Simulation time 167887464 ps
CPU time 0.74 seconds
Started Jul 23 06:36:26 PM PDT 24
Finished Jul 23 06:36:28 PM PDT 24
Peak memory 206744 kb
Host smart-89f35a71-d0d8-4ed0-befc-695218d7c73b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41584
9690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.415849690
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.3505850710
Short name T59
Test name
Test status
Simulation time 176624262 ps
CPU time 0.82 seconds
Started Jul 23 06:36:50 PM PDT 24
Finished Jul 23 06:36:53 PM PDT 24
Peak memory 206780 kb
Host smart-28a4f734-f0e5-49f8-b234-1b23f4f700e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35058
50710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.3505850710
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.4062267458
Short name T984
Test name
Test status
Simulation time 73573760 ps
CPU time 0.68 seconds
Started Jul 23 06:40:39 PM PDT 24
Finished Jul 23 06:40:42 PM PDT 24
Peak memory 206748 kb
Host smart-5079e411-b8e6-4f88-850d-cd5915b981ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40622
67458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.4062267458
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3185026126
Short name T232
Test name
Test status
Simulation time 118313839 ps
CPU time 1.73 seconds
Started Jul 23 05:00:22 PM PDT 24
Finished Jul 23 05:00:27 PM PDT 24
Peak memory 222696 kb
Host smart-a9a8f02e-cfce-4986-a7b0-ff26b452a330
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3185026126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.3185026126
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2521423100
Short name T272
Test name
Test status
Simulation time 928942769 ps
CPU time 3.16 seconds
Started Jul 23 05:00:52 PM PDT 24
Finished Jul 23 05:01:01 PM PDT 24
Peak memory 206860 kb
Host smart-ce3f15d8-5ef2-4584-b6cc-8034d5afd241
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2521423100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.2521423100
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_device_address.2662467898
Short name T22
Test name
Test status
Simulation time 10548738153 ps
CPU time 19.35 seconds
Started Jul 23 06:36:09 PM PDT 24
Finished Jul 23 06:36:29 PM PDT 24
Peak memory 206952 kb
Host smart-7a7daa75-c640-4dd6-8e88-b65f1b5c8551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26624
67898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.2662467898
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.2080274751
Short name T133
Test name
Test status
Simulation time 219988882 ps
CPU time 0.9 seconds
Started Jul 23 06:36:30 PM PDT 24
Finished Jul 23 06:36:33 PM PDT 24
Peak memory 206768 kb
Host smart-d76a6d50-d9eb-40dd-81d0-c231535a1ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20802
74751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.2080274751
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.1632371370
Short name T55
Test name
Test status
Simulation time 415464060 ps
CPU time 1.29 seconds
Started Jul 23 06:36:36 PM PDT 24
Finished Jul 23 06:36:39 PM PDT 24
Peak memory 206760 kb
Host smart-bc19d1c5-f589-4aaa-b24b-51e44da95cc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16323
71370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.1632371370
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.2111904285
Short name T2432
Test name
Test status
Simulation time 200149234 ps
CPU time 0.96 seconds
Started Jul 23 06:37:01 PM PDT 24
Finished Jul 23 06:37:03 PM PDT 24
Peak memory 206696 kb
Host smart-8600b2a0-982a-49ce-8cff-2cb919b96643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21119
04285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.2111904285
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.958911025
Short name T2705
Test name
Test status
Simulation time 15837069510 ps
CPU time 135.92 seconds
Started Jul 23 06:37:20 PM PDT 24
Finished Jul 23 06:39:38 PM PDT 24
Peak memory 207048 kb
Host smart-860112ba-712a-4c2a-805f-daea6392daf0
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=958911025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.958911025
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.4268512917
Short name T2479
Test name
Test status
Simulation time 223917821 ps
CPU time 0.87 seconds
Started Jul 23 06:39:56 PM PDT 24
Finished Jul 23 06:40:00 PM PDT 24
Peak memory 206748 kb
Host smart-75ad3246-089c-4602-9117-f46643f7c202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42685
12917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.4268512917
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.96571983
Short name T618
Test name
Test status
Simulation time 13329311525 ps
CPU time 128.12 seconds
Started Jul 23 06:40:29 PM PDT 24
Finished Jul 23 06:42:38 PM PDT 24
Peak memory 207148 kb
Host smart-48624802-fa16-4e5f-8ef9-27e762a2026e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96571
983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.96571983
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.2286892569
Short name T1409
Test name
Test status
Simulation time 175187777 ps
CPU time 0.86 seconds
Started Jul 23 06:40:35 PM PDT 24
Finished Jul 23 06:40:37 PM PDT 24
Peak memory 206760 kb
Host smart-340cb9c6-ac9e-4e1b-a68b-094345b33508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22868
92569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.2286892569
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.550881874
Short name T140
Test name
Test status
Simulation time 220582478 ps
CPU time 0.86 seconds
Started Jul 23 06:41:15 PM PDT 24
Finished Jul 23 06:41:24 PM PDT 24
Peak memory 206744 kb
Host smart-d5337ccc-1c78-44ae-a1ad-389fdd168c30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55088
1874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.550881874
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.393272374
Short name T122
Test name
Test status
Simulation time 202205777 ps
CPU time 0.86 seconds
Started Jul 23 06:41:27 PM PDT 24
Finished Jul 23 06:41:34 PM PDT 24
Peak memory 206664 kb
Host smart-bb9a81d4-11d0-4d52-bd60-3a66319cdabc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39327
2374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.393272374
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.2183323582
Short name T125
Test name
Test status
Simulation time 221399206 ps
CPU time 0.84 seconds
Started Jul 23 06:37:34 PM PDT 24
Finished Jul 23 06:37:36 PM PDT 24
Peak memory 206756 kb
Host smart-0602e8ae-b4e0-4276-b70f-0254eff0a335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21833
23582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.2183323582
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.1134306726
Short name T1529
Test name
Test status
Simulation time 178111936 ps
CPU time 0.87 seconds
Started Jul 23 06:42:37 PM PDT 24
Finished Jul 23 06:42:41 PM PDT 24
Peak memory 206768 kb
Host smart-8139382f-544f-4f05-96e7-7ee6cd131ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11343
06726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.1134306726
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.2411240447
Short name T148
Test name
Test status
Simulation time 232232767 ps
CPU time 0.87 seconds
Started Jul 23 06:38:01 PM PDT 24
Finished Jul 23 06:38:03 PM PDT 24
Peak memory 206756 kb
Host smart-3cba035f-a1a0-4c72-bf84-b75e1f520cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24112
40447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.2411240447
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_invalid_sync.3392823121
Short name T116
Test name
Test status
Simulation time 5857466570 ps
CPU time 162.93 seconds
Started Jul 23 06:46:26 PM PDT 24
Finished Jul 23 06:49:12 PM PDT 24
Peak memory 206864 kb
Host smart-84bbcf9e-e6c5-4116-98a1-86bb82a4b17d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3392823121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.3392823121
Directory /workspace/41.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.712631288
Short name T134
Test name
Test status
Simulation time 218833899 ps
CPU time 0.88 seconds
Started Jul 23 06:47:18 PM PDT 24
Finished Jul 23 06:47:22 PM PDT 24
Peak memory 206712 kb
Host smart-ca84f2b0-58e7-44e6-8100-450895ce8b2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71263
1288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.712631288
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.740350775
Short name T259
Test name
Test status
Simulation time 335134850 ps
CPU time 3.73 seconds
Started Jul 23 05:00:40 PM PDT 24
Finished Jul 23 05:00:51 PM PDT 24
Peak memory 206380 kb
Host smart-f4960152-44aa-4d27-942c-cc44bec43af3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=740350775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.740350775
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1715343247
Short name T2788
Test name
Test status
Simulation time 735748986 ps
CPU time 4.55 seconds
Started Jul 23 05:00:37 PM PDT 24
Finished Jul 23 05:00:45 PM PDT 24
Peak memory 206436 kb
Host smart-6d5975b2-f63c-4dfd-8f71-6c80fce4bb61
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1715343247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1715343247
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1922811026
Short name T2833
Test name
Test status
Simulation time 80288676 ps
CPU time 0.92 seconds
Started Jul 23 05:00:22 PM PDT 24
Finished Jul 23 05:00:26 PM PDT 24
Peak memory 206636 kb
Host smart-2dd3aa1e-5834-4c89-8fe0-1726980d9b47
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1922811026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1922811026
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3557772290
Short name T2771
Test name
Test status
Simulation time 104125040 ps
CPU time 1.32 seconds
Started Jul 23 05:00:37 PM PDT 24
Finished Jul 23 05:00:43 PM PDT 24
Peak memory 215036 kb
Host smart-077d5913-69e4-4c2d-b5e1-ade310054214
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557772290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.3557772290
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1958973340
Short name T265
Test name
Test status
Simulation time 73945679 ps
CPU time 0.86 seconds
Started Jul 23 05:00:22 PM PDT 24
Finished Jul 23 05:00:26 PM PDT 24
Peak memory 206636 kb
Host smart-47c7e0bb-9597-47ba-a465-dd6904eb8f0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1958973340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1958973340
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3798621346
Short name T2842
Test name
Test status
Simulation time 152272800 ps
CPU time 2.21 seconds
Started Jul 23 05:00:23 PM PDT 24
Finished Jul 23 05:00:28 PM PDT 24
Peak memory 214996 kb
Host smart-4aa1349e-249b-4561-bf75-94105a92b44a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3798621346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.3798621346
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3665559740
Short name T2759
Test name
Test status
Simulation time 159108825 ps
CPU time 2.44 seconds
Started Jul 23 05:00:26 PM PDT 24
Finished Jul 23 05:00:31 PM PDT 24
Peak memory 206724 kb
Host smart-ee8c3075-c0c3-4881-9f3f-90fdc5bd6fad
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3665559740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.3665559740
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3730627713
Short name T2846
Test name
Test status
Simulation time 151671166 ps
CPU time 1.25 seconds
Started Jul 23 05:00:37 PM PDT 24
Finished Jul 23 05:00:42 PM PDT 24
Peak memory 206828 kb
Host smart-f3f63eca-2ea3-41d9-89d2-d5cd62dd46e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3730627713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.3730627713
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.977770019
Short name T248
Test name
Test status
Simulation time 299945782 ps
CPU time 3.73 seconds
Started Jul 23 05:00:36 PM PDT 24
Finished Jul 23 05:00:43 PM PDT 24
Peak memory 206888 kb
Host smart-50a6ccf0-269a-46be-8ea7-f5dc63b44a94
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=977770019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.977770019
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1307306146
Short name T2747
Test name
Test status
Simulation time 543191834 ps
CPU time 4.39 seconds
Started Jul 23 05:00:35 PM PDT 24
Finished Jul 23 05:00:41 PM PDT 24
Peak memory 206868 kb
Host smart-d4f9003a-e7d2-4045-bb1f-1b327ae0e2af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1307306146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.1307306146
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1317812552
Short name T2777
Test name
Test status
Simulation time 162784423 ps
CPU time 0.9 seconds
Started Jul 23 05:00:36 PM PDT 24
Finished Jul 23 05:00:41 PM PDT 24
Peak memory 206524 kb
Host smart-703150ce-4a04-4386-86f5-4ff518e00b43
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1317812552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.1317812552
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.4271607941
Short name T237
Test name
Test status
Simulation time 80840700 ps
CPU time 1.2 seconds
Started Jul 23 05:00:38 PM PDT 24
Finished Jul 23 05:00:45 PM PDT 24
Peak memory 215072 kb
Host smart-1610ef4c-7544-40e1-a6cd-7d9fb3f0a0a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271607941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.4271607941
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.4041669014
Short name T2837
Test name
Test status
Simulation time 76217826 ps
CPU time 1.04 seconds
Started Jul 23 05:00:34 PM PDT 24
Finished Jul 23 05:00:36 PM PDT 24
Peak memory 206860 kb
Host smart-8ade5b71-efb6-434b-8df2-e0d00cbb37b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4041669014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.4041669014
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1043564668
Short name T261
Test name
Test status
Simulation time 194441785 ps
CPU time 2.47 seconds
Started Jul 23 05:00:37 PM PDT 24
Finished Jul 23 05:00:43 PM PDT 24
Peak memory 214660 kb
Host smart-0bc107e3-ba6e-44c4-acd5-058a48b2bcba
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1043564668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.1043564668
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.136986473
Short name T2807
Test name
Test status
Simulation time 124906642 ps
CPU time 2.42 seconds
Started Jul 23 05:00:39 PM PDT 24
Finished Jul 23 05:00:49 PM PDT 24
Peak memory 206816 kb
Host smart-170392c7-93fb-4fa6-bc5b-c93f70d70d89
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=136986473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.136986473
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2652541175
Short name T262
Test name
Test status
Simulation time 69579107 ps
CPU time 1.07 seconds
Started Jul 23 05:00:38 PM PDT 24
Finished Jul 23 05:00:44 PM PDT 24
Peak memory 206836 kb
Host smart-cd5544f1-4b19-46a4-8a29-088c13733008
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2652541175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.2652541175
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2100949026
Short name T228
Test name
Test status
Simulation time 62061040 ps
CPU time 1.79 seconds
Started Jul 23 05:00:40 PM PDT 24
Finished Jul 23 05:00:49 PM PDT 24
Peak memory 206288 kb
Host smart-ac2175d2-951e-4524-b152-29a3c591d63b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2100949026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.2100949026
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3990582935
Short name T287
Test name
Test status
Simulation time 1361887241 ps
CPU time 4.99 seconds
Started Jul 23 05:00:39 PM PDT 24
Finished Jul 23 05:00:51 PM PDT 24
Peak memory 206768 kb
Host smart-6058a248-c6de-42bf-8a1c-91ab0c8b3ad6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3990582935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3990582935
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.4191232089
Short name T235
Test name
Test status
Simulation time 100442275 ps
CPU time 1.38 seconds
Started Jul 23 05:00:52 PM PDT 24
Finished Jul 23 05:00:57 PM PDT 24
Peak memory 215060 kb
Host smart-18ef7b8d-a653-450a-91fd-fe6207f94925
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191232089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.4191232089
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2917107998
Short name T221
Test name
Test status
Simulation time 40553901 ps
CPU time 0.86 seconds
Started Jul 23 05:00:54 PM PDT 24
Finished Jul 23 05:01:05 PM PDT 24
Peak memory 206568 kb
Host smart-9bc3194b-0a76-44a5-a45e-aa36c70c4b50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2917107998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.2917107998
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3793686868
Short name T194
Test name
Test status
Simulation time 140327305 ps
CPU time 1.48 seconds
Started Jul 23 05:00:54 PM PDT 24
Finished Jul 23 05:01:05 PM PDT 24
Peak memory 206696 kb
Host smart-8ee1e4bf-77c2-40bc-9847-3e09cbca3d89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3793686868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.3793686868
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1407374575
Short name T2824
Test name
Test status
Simulation time 79234525 ps
CPU time 1.65 seconds
Started Jul 23 05:00:50 PM PDT 24
Finished Jul 23 05:00:55 PM PDT 24
Peak memory 206856 kb
Host smart-f09eef81-05b6-4319-a25f-95106c3fd90a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1407374575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1407374575
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2654236465
Short name T238
Test name
Test status
Simulation time 273227625 ps
CPU time 2.48 seconds
Started Jul 23 05:00:50 PM PDT 24
Finished Jul 23 05:00:56 PM PDT 24
Peak memory 206836 kb
Host smart-f8d06672-ba92-4ed0-bb6b-f6136fed9e37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2654236465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.2654236465
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2883685464
Short name T2755
Test name
Test status
Simulation time 96445704 ps
CPU time 1.79 seconds
Started Jul 23 05:00:50 PM PDT 24
Finished Jul 23 05:00:55 PM PDT 24
Peak memory 215080 kb
Host smart-0fc2cfc1-b2d8-43db-b4c2-75600b83dc7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883685464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.2883685464
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.733923856
Short name T260
Test name
Test status
Simulation time 60160069 ps
CPU time 0.89 seconds
Started Jul 23 05:00:56 PM PDT 24
Finished Jul 23 05:01:08 PM PDT 24
Peak memory 206572 kb
Host smart-1c69c06b-a6da-43ba-b33c-40d9bcc1472e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=733923856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.733923856
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.4033773840
Short name T2752
Test name
Test status
Simulation time 36544160 ps
CPU time 0.68 seconds
Started Jul 23 05:00:53 PM PDT 24
Finished Jul 23 05:01:01 PM PDT 24
Peak memory 206436 kb
Host smart-62805253-7ca9-40a8-bffb-148795b86b34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4033773840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.4033773840
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3660920242
Short name T2782
Test name
Test status
Simulation time 60691989 ps
CPU time 1.07 seconds
Started Jul 23 05:00:53 PM PDT 24
Finished Jul 23 05:01:02 PM PDT 24
Peak memory 206716 kb
Host smart-e7db3888-3d92-4c07-955c-e4db6e06af13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3660920242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.3660920242
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2187482973
Short name T225
Test name
Test status
Simulation time 48891345 ps
CPU time 1.16 seconds
Started Jul 23 05:00:51 PM PDT 24
Finished Jul 23 05:00:57 PM PDT 24
Peak memory 206804 kb
Host smart-4565bdfc-e54b-4512-b84b-103ed4fd9744
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2187482973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.2187482973
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.676189439
Short name T2802
Test name
Test status
Simulation time 92440002 ps
CPU time 1.29 seconds
Started Jul 23 05:00:57 PM PDT 24
Finished Jul 23 05:01:10 PM PDT 24
Peak memory 215016 kb
Host smart-5bdac407-44dc-4227-a685-2a7808c54de5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676189439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbde
v_csr_mem_rw_with_rand_reset.676189439
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.464070382
Short name T2770
Test name
Test status
Simulation time 67196420 ps
CPU time 0.96 seconds
Started Jul 23 05:00:53 PM PDT 24
Finished Jul 23 05:01:02 PM PDT 24
Peak memory 206772 kb
Host smart-d5714195-c7b2-4fa2-ad50-e81e0c2dcd47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=464070382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.464070382
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.3805022305
Short name T273
Test name
Test status
Simulation time 74950208 ps
CPU time 0.73 seconds
Started Jul 23 05:00:53 PM PDT 24
Finished Jul 23 05:01:02 PM PDT 24
Peak memory 206516 kb
Host smart-f74d7cbc-c933-477e-b99c-9157b94e4bab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3805022305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.3805022305
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3564964027
Short name T2821
Test name
Test status
Simulation time 50925964 ps
CPU time 1.02 seconds
Started Jul 23 05:00:55 PM PDT 24
Finished Jul 23 05:01:07 PM PDT 24
Peak memory 206824 kb
Host smart-ba5c35c2-b26d-4453-9e10-a2fe058e5465
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3564964027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3564964027
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2220699830
Short name T2808
Test name
Test status
Simulation time 101788425 ps
CPU time 2.69 seconds
Started Jul 23 05:00:51 PM PDT 24
Finished Jul 23 05:00:58 PM PDT 24
Peak memory 215040 kb
Host smart-2ac786de-8bcf-49d2-a61a-e81eb5363a58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2220699830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2220699830
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2685400762
Short name T284
Test name
Test status
Simulation time 708490349 ps
CPU time 4.51 seconds
Started Jul 23 05:00:54 PM PDT 24
Finished Jul 23 05:01:09 PM PDT 24
Peak memory 206872 kb
Host smart-e16315dc-94d7-4031-9a52-352278ab1a40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2685400762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.2685400762
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1331373239
Short name T2784
Test name
Test status
Simulation time 183254670 ps
CPU time 1.95 seconds
Started Jul 23 05:00:58 PM PDT 24
Finished Jul 23 05:01:13 PM PDT 24
Peak memory 215008 kb
Host smart-762d7ef2-dc6e-4d60-80ca-45f4a9ef16b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331373239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.1331373239
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2218070394
Short name T2847
Test name
Test status
Simulation time 68437300 ps
CPU time 0.98 seconds
Started Jul 23 05:00:52 PM PDT 24
Finished Jul 23 05:00:58 PM PDT 24
Peak memory 206864 kb
Host smart-3f36ee75-fb7b-4213-9677-dbad68ef1d3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2218070394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.2218070394
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2732650418
Short name T2761
Test name
Test status
Simulation time 60726678 ps
CPU time 0.71 seconds
Started Jul 23 05:00:53 PM PDT 24
Finished Jul 23 05:01:02 PM PDT 24
Peak memory 206512 kb
Host smart-f17fa84b-15da-4e1a-b79b-c9f02d6f4815
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2732650418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.2732650418
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3408731633
Short name T2758
Test name
Test status
Simulation time 154943194 ps
CPU time 1.14 seconds
Started Jul 23 05:00:52 PM PDT 24
Finished Jul 23 05:00:59 PM PDT 24
Peak memory 206796 kb
Host smart-187622ef-28f3-4813-81a2-ecfe04e98de6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3408731633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.3408731633
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3573459372
Short name T218
Test name
Test status
Simulation time 148885035 ps
CPU time 1.89 seconds
Started Jul 23 05:00:58 PM PDT 24
Finished Jul 23 05:01:13 PM PDT 24
Peak memory 214964 kb
Host smart-7b7ca447-34aa-4cde-be11-c284554748dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3573459372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3573459372
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.621050641
Short name T286
Test name
Test status
Simulation time 2399778933 ps
CPU time 5.6 seconds
Started Jul 23 05:00:54 PM PDT 24
Finished Jul 23 05:01:09 PM PDT 24
Peak memory 206872 kb
Host smart-071a1c6b-2b50-46b7-b7bc-cf1ad0e97e93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=621050641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.621050641
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2620441302
Short name T2853
Test name
Test status
Simulation time 214525842 ps
CPU time 2.02 seconds
Started Jul 23 05:00:55 PM PDT 24
Finished Jul 23 05:01:08 PM PDT 24
Peak memory 215052 kb
Host smart-c22ed3e9-de65-4a9b-a9e2-8664611d45ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620441302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.2620441302
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3628650922
Short name T2774
Test name
Test status
Simulation time 116301991 ps
CPU time 0.91 seconds
Started Jul 23 05:00:56 PM PDT 24
Finished Jul 23 05:01:09 PM PDT 24
Peak memory 206596 kb
Host smart-d46c2adb-a688-4db7-a999-065e30f09946
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3628650922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.3628650922
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2079219198
Short name T2765
Test name
Test status
Simulation time 229900066 ps
CPU time 1.93 seconds
Started Jul 23 05:00:57 PM PDT 24
Finished Jul 23 05:01:12 PM PDT 24
Peak memory 206724 kb
Host smart-2cec433a-1704-41dc-b5a5-b1f0610cb6a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2079219198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.2079219198
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3748091692
Short name T2783
Test name
Test status
Simulation time 123602454 ps
CPU time 1.79 seconds
Started Jul 23 05:00:54 PM PDT 24
Finished Jul 23 05:01:06 PM PDT 24
Peak memory 206756 kb
Host smart-5e904873-42eb-4c93-ae95-c790d823b12e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3748091692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3748091692
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.213407506
Short name T2804
Test name
Test status
Simulation time 493210912 ps
CPU time 4.16 seconds
Started Jul 23 05:00:56 PM PDT 24
Finished Jul 23 05:01:13 PM PDT 24
Peak memory 206684 kb
Host smart-f77dd906-6780-42ea-a626-813bf1b39a15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=213407506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.213407506
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2965260073
Short name T231
Test name
Test status
Simulation time 93159856 ps
CPU time 1.24 seconds
Started Jul 23 05:00:57 PM PDT 24
Finished Jul 23 05:01:11 PM PDT 24
Peak memory 215100 kb
Host smart-55288c88-53bc-46f6-93d6-7c8d76d5f267
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965260073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.2965260073
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.639906501
Short name T2809
Test name
Test status
Simulation time 60662123 ps
CPU time 1.03 seconds
Started Jul 23 05:00:57 PM PDT 24
Finished Jul 23 05:01:10 PM PDT 24
Peak memory 206816 kb
Host smart-e3d6bf88-5253-4396-9779-b9598439e5d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=639906501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.639906501
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2654274871
Short name T2787
Test name
Test status
Simulation time 36939527 ps
CPU time 0.64 seconds
Started Jul 23 05:00:57 PM PDT 24
Finished Jul 23 05:01:11 PM PDT 24
Peak memory 206448 kb
Host smart-6a1c4353-dad0-4ab4-8e44-1b8b970637d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2654274871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.2654274871
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.51074810
Short name T2820
Test name
Test status
Simulation time 97123457 ps
CPU time 1.21 seconds
Started Jul 23 05:00:56 PM PDT 24
Finished Jul 23 05:01:10 PM PDT 24
Peak memory 206864 kb
Host smart-5a6d3c45-15a7-47f2-b072-3a410bfb2204
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=51074810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.51074810
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3667084722
Short name T230
Test name
Test status
Simulation time 68729596 ps
CPU time 1.54 seconds
Started Jul 23 05:00:56 PM PDT 24
Finished Jul 23 05:01:10 PM PDT 24
Peak memory 206828 kb
Host smart-c40b270d-549b-4b66-9e57-af62a6daadf2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3667084722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.3667084722
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3323347506
Short name T193
Test name
Test status
Simulation time 254313969 ps
CPU time 2.54 seconds
Started Jul 23 05:00:54 PM PDT 24
Finished Jul 23 05:01:06 PM PDT 24
Peak memory 206808 kb
Host smart-2ba7e45d-833b-4f23-b1be-44d4c0f07a73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3323347506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.3323347506
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.599091991
Short name T2757
Test name
Test status
Simulation time 105169800 ps
CPU time 1.69 seconds
Started Jul 23 05:00:55 PM PDT 24
Finished Jul 23 05:01:08 PM PDT 24
Peak memory 215028 kb
Host smart-adbc3fba-c993-4d37-a8ff-ca8fe1220d74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599091991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbde
v_csr_mem_rw_with_rand_reset.599091991
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3020085346
Short name T2818
Test name
Test status
Simulation time 54899218 ps
CPU time 0.82 seconds
Started Jul 23 05:00:59 PM PDT 24
Finished Jul 23 05:01:14 PM PDT 24
Peak memory 206596 kb
Host smart-d7f59279-3247-4df3-af7b-2bb8c2a9591e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3020085346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.3020085346
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.4236441467
Short name T270
Test name
Test status
Simulation time 80889170 ps
CPU time 0.73 seconds
Started Jul 23 05:00:55 PM PDT 24
Finished Jul 23 05:01:07 PM PDT 24
Peak memory 206488 kb
Host smart-0f845243-7e4a-4254-b11a-7b8197c64ac9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4236441467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.4236441467
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.300336179
Short name T2805
Test name
Test status
Simulation time 118956609 ps
CPU time 1.1 seconds
Started Jul 23 05:00:57 PM PDT 24
Finished Jul 23 05:01:11 PM PDT 24
Peak memory 206696 kb
Host smart-a3f89025-7380-41c6-89e6-b9f30e787f2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=300336179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.300336179
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.94689082
Short name T2792
Test name
Test status
Simulation time 86346306 ps
CPU time 2.01 seconds
Started Jul 23 05:00:57 PM PDT 24
Finished Jul 23 05:01:12 PM PDT 24
Peak memory 223056 kb
Host smart-8f991c40-a5a2-419d-9aa5-82155d3cbc12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=94689082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.94689082
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3303278518
Short name T192
Test name
Test status
Simulation time 254509544 ps
CPU time 2.5 seconds
Started Jul 23 05:00:56 PM PDT 24
Finished Jul 23 05:01:11 PM PDT 24
Peak memory 206828 kb
Host smart-93b25052-9897-44c8-a712-0887675a9a4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3303278518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.3303278518
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1047624658
Short name T220
Test name
Test status
Simulation time 140474654 ps
CPU time 1.4 seconds
Started Jul 23 05:00:54 PM PDT 24
Finished Jul 23 05:01:06 PM PDT 24
Peak memory 215044 kb
Host smart-bb9fa026-0b10-42d3-b70e-7f34f3b7d771
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047624658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.1047624658
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1984829649
Short name T2817
Test name
Test status
Simulation time 80824837 ps
CPU time 0.83 seconds
Started Jul 23 05:00:53 PM PDT 24
Finished Jul 23 05:01:02 PM PDT 24
Peak memory 206580 kb
Host smart-516b4ff0-4c90-42db-b64d-1e606b73437f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1984829649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.1984829649
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1568400060
Short name T2769
Test name
Test status
Simulation time 51097320 ps
CPU time 0.71 seconds
Started Jul 23 05:00:57 PM PDT 24
Finished Jul 23 05:01:11 PM PDT 24
Peak memory 206528 kb
Host smart-9348a5d4-0849-4405-992b-078f754b0c58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1568400060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.1568400060
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1203983037
Short name T2797
Test name
Test status
Simulation time 98086970 ps
CPU time 1.02 seconds
Started Jul 23 05:00:53 PM PDT 24
Finished Jul 23 05:01:01 PM PDT 24
Peak memory 206704 kb
Host smart-563da2c0-e5c3-454e-8ac6-2b5373303e21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1203983037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.1203983037
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1322095136
Short name T2836
Test name
Test status
Simulation time 104474085 ps
CPU time 2.89 seconds
Started Jul 23 05:00:57 PM PDT 24
Finished Jul 23 05:01:13 PM PDT 24
Peak memory 215040 kb
Host smart-b103cd95-3076-4761-9d54-d2bc4e3a7032
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1322095136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.1322095136
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2534534120
Short name T236
Test name
Test status
Simulation time 64826013 ps
CPU time 1.46 seconds
Started Jul 23 05:00:50 PM PDT 24
Finished Jul 23 05:00:55 PM PDT 24
Peak memory 215028 kb
Host smart-d0c80016-653e-4ec8-a07a-e2097f425bd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534534120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.2534534120
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2461494893
Short name T2768
Test name
Test status
Simulation time 67031235 ps
CPU time 0.98 seconds
Started Jul 23 05:00:51 PM PDT 24
Finished Jul 23 05:00:56 PM PDT 24
Peak memory 206796 kb
Host smart-b67eced0-d0c6-4d7e-9f92-74a1fbd72e35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2461494893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.2461494893
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.540933896
Short name T2772
Test name
Test status
Simulation time 58359194 ps
CPU time 0.69 seconds
Started Jul 23 05:00:52 PM PDT 24
Finished Jul 23 05:00:59 PM PDT 24
Peak memory 206532 kb
Host smart-b0b9d4f3-05fd-48d1-ba51-d6b3430e2ab5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=540933896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.540933896
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1116362514
Short name T266
Test name
Test status
Simulation time 94107629 ps
CPU time 1.46 seconds
Started Jul 23 05:00:51 PM PDT 24
Finished Jul 23 05:00:57 PM PDT 24
Peak memory 206824 kb
Host smart-b230b1ea-0f25-460a-848a-5734c1ebc311
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1116362514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.1116362514
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3510620780
Short name T2781
Test name
Test status
Simulation time 170770217 ps
CPU time 2.21 seconds
Started Jul 23 05:00:54 PM PDT 24
Finished Jul 23 05:01:05 PM PDT 24
Peak memory 206716 kb
Host smart-c7bcef27-c94a-49fc-ba1c-e2e50fb3b438
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3510620780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3510620780
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2043563430
Short name T2796
Test name
Test status
Simulation time 711796491 ps
CPU time 4.47 seconds
Started Jul 23 05:00:52 PM PDT 24
Finished Jul 23 05:01:02 PM PDT 24
Peak memory 206776 kb
Host smart-1e926044-5780-457b-9174-d3c1146eabaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2043563430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.2043563430
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.948317780
Short name T2763
Test name
Test status
Simulation time 55110735 ps
CPU time 1.36 seconds
Started Jul 23 05:01:00 PM PDT 24
Finished Jul 23 05:01:15 PM PDT 24
Peak memory 215048 kb
Host smart-d132af15-0303-4271-8eae-11ee2927ecad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948317780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbde
v_csr_mem_rw_with_rand_reset.948317780
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1204725172
Short name T264
Test name
Test status
Simulation time 53750246 ps
CPU time 0.87 seconds
Started Jul 23 05:00:57 PM PDT 24
Finished Jul 23 05:01:10 PM PDT 24
Peak memory 206644 kb
Host smart-0f9cda00-4750-41c0-8d9e-a812c6e5e7c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1204725172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.1204725172
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.1390159181
Short name T2749
Test name
Test status
Simulation time 39266804 ps
CPU time 0.7 seconds
Started Jul 23 05:00:57 PM PDT 24
Finished Jul 23 05:01:09 PM PDT 24
Peak memory 206396 kb
Host smart-202fd928-49f9-49cd-a603-318c4b55e389
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1390159181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.1390159181
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2457296007
Short name T2828
Test name
Test status
Simulation time 128273247 ps
CPU time 1.76 seconds
Started Jul 23 05:00:57 PM PDT 24
Finished Jul 23 05:01:12 PM PDT 24
Peak memory 206724 kb
Host smart-9fddb36a-db8d-4220-bf33-986e0cbf4e6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2457296007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.2457296007
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.4218194850
Short name T2798
Test name
Test status
Simulation time 163875800 ps
CPU time 1.65 seconds
Started Jul 23 05:00:52 PM PDT 24
Finished Jul 23 05:00:58 PM PDT 24
Peak memory 215084 kb
Host smart-b7db2f14-f7f8-4640-9aa7-2267e2f9b08b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4218194850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.4218194850
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2914787704
Short name T2780
Test name
Test status
Simulation time 1047874745 ps
CPU time 3.35 seconds
Started Jul 23 05:00:53 PM PDT 24
Finished Jul 23 05:01:04 PM PDT 24
Peak memory 206844 kb
Host smart-a027e381-2126-420d-9e49-0de1e4ff804d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2914787704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.2914787704
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1963073050
Short name T250
Test name
Test status
Simulation time 354155991 ps
CPU time 3.62 seconds
Started Jul 23 05:00:36 PM PDT 24
Finished Jul 23 05:00:43 PM PDT 24
Peak memory 206804 kb
Host smart-be49e9b7-c7ba-4faf-bb3a-660b7bdd1185
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1963073050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.1963073050
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2260673378
Short name T2744
Test name
Test status
Simulation time 750048627 ps
CPU time 4.24 seconds
Started Jul 23 05:00:36 PM PDT 24
Finished Jul 23 05:00:44 PM PDT 24
Peak memory 206784 kb
Host smart-fbc0dd15-75eb-49ab-8760-f4cd273b8f68
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2260673378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.2260673378
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.288722797
Short name T2794
Test name
Test status
Simulation time 61263033 ps
CPU time 0.81 seconds
Started Jul 23 05:00:37 PM PDT 24
Finished Jul 23 05:00:43 PM PDT 24
Peak memory 206596 kb
Host smart-78ed3d92-5212-4006-9b16-a415c7fe9798
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=288722797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.288722797
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2551931960
Short name T2767
Test name
Test status
Simulation time 164850556 ps
CPU time 1.83 seconds
Started Jul 23 05:00:37 PM PDT 24
Finished Jul 23 05:00:42 PM PDT 24
Peak memory 215032 kb
Host smart-37e08841-42a5-42b1-8a86-05017393468c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551931960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.2551931960
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1908936227
Short name T2838
Test name
Test status
Simulation time 55963103 ps
CPU time 0.96 seconds
Started Jul 23 05:00:39 PM PDT 24
Finished Jul 23 05:00:47 PM PDT 24
Peak memory 206792 kb
Host smart-5b3ff173-6092-4c8a-9e59-22c30adff859
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1908936227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.1908936227
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.48147305
Short name T2848
Test name
Test status
Simulation time 71870411 ps
CPU time 0.72 seconds
Started Jul 23 05:00:38 PM PDT 24
Finished Jul 23 05:00:44 PM PDT 24
Peak memory 206528 kb
Host smart-9fcbc3c6-563d-4537-a8cd-7037d6a3101c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=48147305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.48147305
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1431658263
Short name T253
Test name
Test status
Simulation time 122195158 ps
CPU time 1.49 seconds
Started Jul 23 05:00:38 PM PDT 24
Finished Jul 23 05:00:45 PM PDT 24
Peak memory 223100 kb
Host smart-9a8c8e61-556a-46ba-aa25-fde8e83f84c0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1431658263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.1431658263
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3721167355
Short name T2756
Test name
Test status
Simulation time 486085056 ps
CPU time 4.37 seconds
Started Jul 23 05:00:40 PM PDT 24
Finished Jul 23 05:00:52 PM PDT 24
Peak memory 206792 kb
Host smart-ddefe776-7728-40ac-8a8a-80815963b204
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3721167355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3721167355
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.465491915
Short name T267
Test name
Test status
Simulation time 195060802 ps
CPU time 1.63 seconds
Started Jul 23 05:00:35 PM PDT 24
Finished Jul 23 05:00:39 PM PDT 24
Peak memory 206816 kb
Host smart-5c07b516-e40c-4031-9e5d-ba1199576b25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=465491915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.465491915
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3825484061
Short name T2800
Test name
Test status
Simulation time 98531026 ps
CPU time 0.76 seconds
Started Jul 23 05:01:07 PM PDT 24
Finished Jul 23 05:01:25 PM PDT 24
Peak memory 206444 kb
Host smart-0b48b6e4-0507-4aef-a58a-a97694cc1a09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3825484061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.3825484061
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1872768647
Short name T2801
Test name
Test status
Simulation time 52342152 ps
CPU time 0.74 seconds
Started Jul 23 05:01:03 PM PDT 24
Finished Jul 23 05:01:19 PM PDT 24
Peak memory 206536 kb
Host smart-2e40f77b-f8b0-4f58-8827-5e0b10f10fe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1872768647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.1872768647
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1779795145
Short name T2754
Test name
Test status
Simulation time 49867649 ps
CPU time 0.71 seconds
Started Jul 23 05:01:04 PM PDT 24
Finished Jul 23 05:01:20 PM PDT 24
Peak memory 206524 kb
Host smart-b2bc6b1f-198f-4c1c-9fc4-9f0b5476b92d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1779795145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.1779795145
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2150252422
Short name T281
Test name
Test status
Simulation time 60454381 ps
CPU time 0.67 seconds
Started Jul 23 05:00:59 PM PDT 24
Finished Jul 23 05:01:14 PM PDT 24
Peak memory 206512 kb
Host smart-8aa30c52-326e-4111-a407-35ccf87de1c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2150252422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.2150252422
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.270173627
Short name T2849
Test name
Test status
Simulation time 95047626 ps
CPU time 0.76 seconds
Started Jul 23 05:01:01 PM PDT 24
Finished Jul 23 05:01:16 PM PDT 24
Peak memory 206488 kb
Host smart-89e18c71-d92a-4230-ad6a-e731e5260bc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=270173627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.270173627
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2525708769
Short name T282
Test name
Test status
Simulation time 60536855 ps
CPU time 0.72 seconds
Started Jul 23 05:01:02 PM PDT 24
Finished Jul 23 05:01:17 PM PDT 24
Peak memory 206488 kb
Host smart-d469c687-b7f4-48fd-bbd7-d7211fe561d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2525708769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.2525708769
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.876015387
Short name T2829
Test name
Test status
Simulation time 57123468 ps
CPU time 0.7 seconds
Started Jul 23 05:01:03 PM PDT 24
Finished Jul 23 05:01:19 PM PDT 24
Peak memory 206532 kb
Host smart-beb2e6c1-2aa6-4fa6-b9bb-53db1e28cd21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=876015387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.876015387
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3045338403
Short name T2760
Test name
Test status
Simulation time 45207448 ps
CPU time 0.68 seconds
Started Jul 23 05:01:04 PM PDT 24
Finished Jul 23 05:01:20 PM PDT 24
Peak memory 206516 kb
Host smart-00676d15-6bd6-4abc-b81b-60532560e896
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3045338403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.3045338403
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.4118512889
Short name T2816
Test name
Test status
Simulation time 45397524 ps
CPU time 0.69 seconds
Started Jul 23 05:01:09 PM PDT 24
Finished Jul 23 05:01:28 PM PDT 24
Peak memory 206512 kb
Host smart-5aeebb8c-df67-446d-8db7-92b01e3d8f98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4118512889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.4118512889
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3739589444
Short name T251
Test name
Test status
Simulation time 371608983 ps
CPU time 3.7 seconds
Started Jul 23 05:00:40 PM PDT 24
Finished Jul 23 05:00:51 PM PDT 24
Peak memory 206832 kb
Host smart-505fae12-b825-4bc1-9605-6adaf0ebf037
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3739589444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3739589444
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3645071476
Short name T2746
Test name
Test status
Simulation time 738805722 ps
CPU time 8.37 seconds
Started Jul 23 05:00:38 PM PDT 24
Finished Jul 23 05:00:53 PM PDT 24
Peak memory 206760 kb
Host smart-4f9e8e23-5169-4da8-afd8-d6cf497e2f21
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3645071476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3645071476
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.4026071779
Short name T254
Test name
Test status
Simulation time 148295854 ps
CPU time 0.91 seconds
Started Jul 23 05:00:37 PM PDT 24
Finished Jul 23 05:00:43 PM PDT 24
Peak memory 206536 kb
Host smart-fb6244f9-4d4e-4ea2-96b5-f4e453014866
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4026071779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.4026071779
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2099669590
Short name T2815
Test name
Test status
Simulation time 171877341 ps
CPU time 1.91 seconds
Started Jul 23 05:00:36 PM PDT 24
Finished Jul 23 05:00:42 PM PDT 24
Peak memory 215012 kb
Host smart-9061b0ed-50cc-4bfc-bb41-d83bc826658a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099669590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.2099669590
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.59035833
Short name T256
Test name
Test status
Simulation time 52979023 ps
CPU time 1.05 seconds
Started Jul 23 05:00:36 PM PDT 24
Finished Jul 23 05:00:40 PM PDT 24
Peak memory 206792 kb
Host smart-b023ba0a-c7aa-47fe-986b-1e69192d737d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=59035833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.59035833
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.229385759
Short name T2810
Test name
Test status
Simulation time 45850711 ps
CPU time 0.66 seconds
Started Jul 23 05:00:37 PM PDT 24
Finished Jul 23 05:00:41 PM PDT 24
Peak memory 206512 kb
Host smart-d60513c5-bd89-4ed6-a767-4ffc9c90047d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=229385759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.229385759
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.4191346193
Short name T2845
Test name
Test status
Simulation time 219515679 ps
CPU time 2.44 seconds
Started Jul 23 05:00:38 PM PDT 24
Finished Jul 23 05:00:47 PM PDT 24
Peak memory 216228 kb
Host smart-0bee5543-e24d-4d31-bf74-3b53d6a6aca1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4191346193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.4191346193
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3183488205
Short name T2762
Test name
Test status
Simulation time 291755398 ps
CPU time 2.62 seconds
Started Jul 23 05:00:41 PM PDT 24
Finished Jul 23 05:00:51 PM PDT 24
Peak memory 206780 kb
Host smart-34f04d6c-df92-41c2-a910-53a20a236623
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3183488205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.3183488205
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2040960157
Short name T2834
Test name
Test status
Simulation time 126043615 ps
CPU time 1.13 seconds
Started Jul 23 05:00:39 PM PDT 24
Finished Jul 23 05:00:46 PM PDT 24
Peak memory 206756 kb
Host smart-4bb4ce3d-9f82-4d78-95a8-f8fb882893cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2040960157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.2040960157
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2701574721
Short name T2806
Test name
Test status
Simulation time 132166993 ps
CPU time 1.58 seconds
Started Jul 23 05:00:40 PM PDT 24
Finished Jul 23 05:00:49 PM PDT 24
Peak memory 215076 kb
Host smart-661ba1b4-4f0d-42b2-b685-d12364353137
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2701574721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2701574721
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1820781168
Short name T233
Test name
Test status
Simulation time 827820334 ps
CPU time 5.46 seconds
Started Jul 23 05:00:39 PM PDT 24
Finished Jul 23 05:00:51 PM PDT 24
Peak memory 206800 kb
Host smart-2654f53c-fe9e-43aa-8936-30fe3fba9eb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1820781168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.1820781168
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1653954312
Short name T2830
Test name
Test status
Simulation time 45113897 ps
CPU time 0.63 seconds
Started Jul 23 05:01:07 PM PDT 24
Finished Jul 23 05:01:25 PM PDT 24
Peak memory 206512 kb
Host smart-cb170962-7079-431f-8354-38c3585058ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1653954312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.1653954312
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3594708553
Short name T283
Test name
Test status
Simulation time 109450808 ps
CPU time 0.74 seconds
Started Jul 23 05:01:02 PM PDT 24
Finished Jul 23 05:01:18 PM PDT 24
Peak memory 206532 kb
Host smart-33bd5b9d-2443-4b6b-8110-b3ac6c079c8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3594708553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.3594708553
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1093771693
Short name T2799
Test name
Test status
Simulation time 36781024 ps
CPU time 0.73 seconds
Started Jul 23 05:01:07 PM PDT 24
Finished Jul 23 05:01:25 PM PDT 24
Peak memory 206516 kb
Host smart-e69c1386-32ad-4832-bd7a-eb136f946868
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1093771693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.1093771693
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1026592010
Short name T2751
Test name
Test status
Simulation time 82970802 ps
CPU time 0.7 seconds
Started Jul 23 05:01:07 PM PDT 24
Finished Jul 23 05:01:25 PM PDT 24
Peak memory 206480 kb
Host smart-913fc4fb-4906-4a42-bfc4-17fb244ba0c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1026592010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.1026592010
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.4291550920
Short name T271
Test name
Test status
Simulation time 46962009 ps
CPU time 0.77 seconds
Started Jul 23 05:01:03 PM PDT 24
Finished Jul 23 05:01:19 PM PDT 24
Peak memory 206532 kb
Host smart-291bbeca-f748-4635-bd62-1efceec710ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4291550920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.4291550920
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.257752855
Short name T2748
Test name
Test status
Simulation time 37446018 ps
CPU time 0.65 seconds
Started Jul 23 05:01:09 PM PDT 24
Finished Jul 23 05:01:28 PM PDT 24
Peak memory 206540 kb
Host smart-a1e67336-d0c1-418a-ad9d-217ab2627e65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=257752855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.257752855
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.172382565
Short name T201
Test name
Test status
Simulation time 39988107 ps
CPU time 0.67 seconds
Started Jul 23 05:01:07 PM PDT 24
Finished Jul 23 05:01:25 PM PDT 24
Peak memory 206476 kb
Host smart-28d4f15e-37f1-461a-992e-17f6218eb016
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=172382565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.172382565
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.1254653401
Short name T2789
Test name
Test status
Simulation time 40621540 ps
CPU time 0.76 seconds
Started Jul 23 05:01:04 PM PDT 24
Finished Jul 23 05:01:20 PM PDT 24
Peak memory 206456 kb
Host smart-541a5624-0422-4e32-a3ba-d6f848e2ebfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1254653401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.1254653401
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.108465881
Short name T2795
Test name
Test status
Simulation time 79516473 ps
CPU time 0.69 seconds
Started Jul 23 05:01:05 PM PDT 24
Finished Jul 23 05:01:21 PM PDT 24
Peak memory 206432 kb
Host smart-e0b626d9-3321-47a3-831d-93a9e76d5209
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=108465881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.108465881
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2959321118
Short name T2745
Test name
Test status
Simulation time 88141240 ps
CPU time 2.02 seconds
Started Jul 23 05:00:40 PM PDT 24
Finished Jul 23 05:00:50 PM PDT 24
Peak memory 206736 kb
Host smart-586e64f5-616b-4549-bd4e-6194f2ed1a72
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2959321118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2959321118
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2398560869
Short name T2832
Test name
Test status
Simulation time 230892839 ps
CPU time 4.06 seconds
Started Jul 23 05:00:40 PM PDT 24
Finished Jul 23 05:00:51 PM PDT 24
Peak memory 206628 kb
Host smart-2ecd49f1-5be4-483e-9f7a-b8edb8d17244
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2398560869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.2398560869
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2584894335
Short name T2812
Test name
Test status
Simulation time 260185969 ps
CPU time 1.07 seconds
Started Jul 23 05:00:38 PM PDT 24
Finished Jul 23 05:00:46 PM PDT 24
Peak memory 206548 kb
Host smart-80ce7a9e-11f5-467e-a6ee-6f7bd86497c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2584894335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.2584894335
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1157999097
Short name T219
Test name
Test status
Simulation time 113422243 ps
CPU time 1.33 seconds
Started Jul 23 05:00:39 PM PDT 24
Finished Jul 23 05:00:48 PM PDT 24
Peak memory 215044 kb
Host smart-7ada0ab0-272c-4017-9044-271891678409
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157999097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.1157999097
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3089448732
Short name T2786
Test name
Test status
Simulation time 57130487 ps
CPU time 1.04 seconds
Started Jul 23 05:00:36 PM PDT 24
Finished Jul 23 05:00:41 PM PDT 24
Peak memory 206772 kb
Host smart-fe04cd01-77d9-4686-b483-0d4c5fb674d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3089448732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.3089448732
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1075420029
Short name T2839
Test name
Test status
Simulation time 88385310 ps
CPU time 0.72 seconds
Started Jul 23 05:00:35 PM PDT 24
Finished Jul 23 05:00:37 PM PDT 24
Peak memory 206532 kb
Host smart-b480e0eb-2c96-4184-9868-c40ba94412a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1075420029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.1075420029
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.4243090783
Short name T257
Test name
Test status
Simulation time 124724733 ps
CPU time 1.54 seconds
Started Jul 23 05:00:38 PM PDT 24
Finished Jul 23 05:00:46 PM PDT 24
Peak memory 223172 kb
Host smart-7ee00e73-5acf-4673-8a6b-5c01fa6c73c2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4243090783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.4243090783
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2075514814
Short name T2825
Test name
Test status
Simulation time 337915624 ps
CPU time 2.77 seconds
Started Jul 23 05:00:38 PM PDT 24
Finished Jul 23 05:00:46 PM PDT 24
Peak memory 206792 kb
Host smart-50923e87-0797-4dfe-aa6b-2c4b034e7129
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2075514814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.2075514814
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.348889544
Short name T263
Test name
Test status
Simulation time 136093172 ps
CPU time 1.24 seconds
Started Jul 23 05:00:36 PM PDT 24
Finished Jul 23 05:00:42 PM PDT 24
Peak memory 206872 kb
Host smart-0cd948af-6f83-4116-b24d-cb60a45fb028
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=348889544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.348889544
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2192969203
Short name T2764
Test name
Test status
Simulation time 126284638 ps
CPU time 1.68 seconds
Started Jul 23 05:00:40 PM PDT 24
Finished Jul 23 05:00:49 PM PDT 24
Peak memory 222576 kb
Host smart-0702a315-004d-4afc-8538-19e76e9124da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2192969203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.2192969203
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3017159178
Short name T2819
Test name
Test status
Simulation time 489294538 ps
CPU time 2.87 seconds
Started Jul 23 05:00:40 PM PDT 24
Finished Jul 23 05:00:50 PM PDT 24
Peak memory 206740 kb
Host smart-5866a3e5-1f9b-4930-8b95-1acf194477db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3017159178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.3017159178
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.662601120
Short name T2803
Test name
Test status
Simulation time 55383273 ps
CPU time 0.78 seconds
Started Jul 23 05:01:03 PM PDT 24
Finished Jul 23 05:01:19 PM PDT 24
Peak memory 206532 kb
Host smart-c69a8d90-1679-4c1e-bcb8-b760bf671f37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=662601120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.662601120
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.703223028
Short name T277
Test name
Test status
Simulation time 37338448 ps
CPU time 0.66 seconds
Started Jul 23 05:01:05 PM PDT 24
Finished Jul 23 05:01:21 PM PDT 24
Peak memory 206420 kb
Host smart-2e63062b-1631-44be-ae87-d6515f9f3a9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=703223028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.703223028
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.716971292
Short name T274
Test name
Test status
Simulation time 32719456 ps
CPU time 0.68 seconds
Started Jul 23 05:01:02 PM PDT 24
Finished Jul 23 05:01:16 PM PDT 24
Peak memory 206516 kb
Host smart-649de406-f422-47ad-a491-12f1df64500a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=716971292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.716971292
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3480744053
Short name T203
Test name
Test status
Simulation time 72233443 ps
CPU time 0.78 seconds
Started Jul 23 05:01:03 PM PDT 24
Finished Jul 23 05:01:19 PM PDT 24
Peak memory 206532 kb
Host smart-b2eea2d9-7146-4f11-9ad3-6c149a6adb13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3480744053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3480744053
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1628117272
Short name T2753
Test name
Test status
Simulation time 35001334 ps
CPU time 0.66 seconds
Started Jul 23 05:01:02 PM PDT 24
Finished Jul 23 05:01:17 PM PDT 24
Peak memory 206528 kb
Host smart-674e4750-77be-40b6-b095-4ee79db5c9ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1628117272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.1628117272
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2768619813
Short name T2850
Test name
Test status
Simulation time 66035324 ps
CPU time 0.69 seconds
Started Jul 23 05:01:09 PM PDT 24
Finished Jul 23 05:01:27 PM PDT 24
Peak memory 206516 kb
Host smart-edf01a1c-1efa-4928-96fc-1872beb6a613
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2768619813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2768619813
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.842553632
Short name T206
Test name
Test status
Simulation time 47845517 ps
CPU time 0.66 seconds
Started Jul 23 05:01:06 PM PDT 24
Finished Jul 23 05:01:24 PM PDT 24
Peak memory 206496 kb
Host smart-2c4f2714-1b73-4a5e-9a48-e45b3b119ba8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=842553632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.842553632
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1323408862
Short name T2750
Test name
Test status
Simulation time 45555396 ps
CPU time 0.66 seconds
Started Jul 23 05:01:02 PM PDT 24
Finished Jul 23 05:01:18 PM PDT 24
Peak memory 206560 kb
Host smart-90efde14-90d4-4457-bc34-33890ce266a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1323408862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.1323408862
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2744316056
Short name T205
Test name
Test status
Simulation time 39745160 ps
CPU time 0.68 seconds
Started Jul 23 05:01:06 PM PDT 24
Finished Jul 23 05:01:23 PM PDT 24
Peak memory 206540 kb
Host smart-ebf8590a-04b3-4be2-b009-a5934cb50d74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2744316056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.2744316056
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1164143349
Short name T2779
Test name
Test status
Simulation time 60208272 ps
CPU time 0.73 seconds
Started Jul 23 05:01:07 PM PDT 24
Finished Jul 23 05:01:25 PM PDT 24
Peak memory 206432 kb
Host smart-19e70b13-0fe7-4d85-ac1a-751a4175322e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1164143349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.1164143349
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1583145480
Short name T2773
Test name
Test status
Simulation time 78616504 ps
CPU time 1.86 seconds
Started Jul 23 05:00:37 PM PDT 24
Finished Jul 23 05:00:44 PM PDT 24
Peak memory 215044 kb
Host smart-d143756b-31fa-47ec-b4ce-f9ccdff699c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583145480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.1583145480
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3495505003
Short name T255
Test name
Test status
Simulation time 91559770 ps
CPU time 1 seconds
Started Jul 23 05:00:37 PM PDT 24
Finished Jul 23 05:00:43 PM PDT 24
Peak memory 206852 kb
Host smart-f8c77fb9-e1be-45e1-a996-2c448a96c546
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3495505003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.3495505003
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.266394012
Short name T2766
Test name
Test status
Simulation time 43682518 ps
CPU time 0.7 seconds
Started Jul 23 05:00:40 PM PDT 24
Finished Jul 23 05:00:48 PM PDT 24
Peak memory 206520 kb
Host smart-5c21d0f7-70b7-436e-875e-9e21fff21ab4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=266394012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.266394012
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1723563632
Short name T2790
Test name
Test status
Simulation time 247575592 ps
CPU time 1.79 seconds
Started Jul 23 05:00:39 PM PDT 24
Finished Jul 23 05:00:48 PM PDT 24
Peak memory 206808 kb
Host smart-73c6a770-58aa-44cd-8c14-e9673659b95d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1723563632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.1723563632
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.558587496
Short name T2852
Test name
Test status
Simulation time 281319793 ps
CPU time 3.48 seconds
Started Jul 23 05:00:40 PM PDT 24
Finished Jul 23 05:00:51 PM PDT 24
Peak memory 215028 kb
Host smart-e8a88f6f-1afa-4eaa-b938-64b80eddacb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=558587496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.558587496
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.802605868
Short name T2791
Test name
Test status
Simulation time 826637136 ps
CPU time 5 seconds
Started Jul 23 05:00:36 PM PDT 24
Finished Jul 23 05:00:45 PM PDT 24
Peak memory 206828 kb
Host smart-3d8ff629-33aa-4dcf-8a84-c864b6e75902
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=802605868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.802605868
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3029474770
Short name T2811
Test name
Test status
Simulation time 90056438 ps
CPU time 1.28 seconds
Started Jul 23 05:00:40 PM PDT 24
Finished Jul 23 05:00:49 PM PDT 24
Peak memory 215068 kb
Host smart-602062bc-838f-4992-a032-175db317fdec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029474770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.3029474770
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2643929498
Short name T2841
Test name
Test status
Simulation time 35055424 ps
CPU time 0.64 seconds
Started Jul 23 05:00:39 PM PDT 24
Finished Jul 23 05:00:46 PM PDT 24
Peak memory 206504 kb
Host smart-8dcf0b1c-49c2-46b4-8c48-684059858e3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2643929498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.2643929498
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3899776531
Short name T2826
Test name
Test status
Simulation time 136932148 ps
CPU time 1.56 seconds
Started Jul 23 05:00:37 PM PDT 24
Finished Jul 23 05:00:44 PM PDT 24
Peak memory 206760 kb
Host smart-7ac8eedc-f1ee-4bd0-8970-d8f74a6add6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3899776531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.3899776531
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2959046645
Short name T2778
Test name
Test status
Simulation time 108686273 ps
CPU time 2.88 seconds
Started Jul 23 05:00:37 PM PDT 24
Finished Jul 23 05:00:44 PM PDT 24
Peak memory 215056 kb
Host smart-21f3e546-e427-46ca-a084-dcd1ace402f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2959046645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.2959046645
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2145390323
Short name T2843
Test name
Test status
Simulation time 916710880 ps
CPU time 3.16 seconds
Started Jul 23 05:00:38 PM PDT 24
Finished Jul 23 05:00:46 PM PDT 24
Peak memory 206852 kb
Host smart-aec79798-a5f0-4969-b370-9599637441ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2145390323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.2145390323
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2828122932
Short name T2831
Test name
Test status
Simulation time 146006416 ps
CPU time 1.91 seconds
Started Jul 23 05:00:37 PM PDT 24
Finished Jul 23 05:00:44 PM PDT 24
Peak memory 215104 kb
Host smart-80c9f10f-d381-41c6-945d-4a145db543e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828122932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.2828122932
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1068324872
Short name T2822
Test name
Test status
Simulation time 90268842 ps
CPU time 0.87 seconds
Started Jul 23 05:00:38 PM PDT 24
Finished Jul 23 05:00:44 PM PDT 24
Peak memory 206624 kb
Host smart-164f60e3-c33f-4996-bb7d-b283b7c392ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1068324872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.1068324872
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.958600803
Short name T2775
Test name
Test status
Simulation time 41890067 ps
CPU time 0.66 seconds
Started Jul 23 05:00:35 PM PDT 24
Finished Jul 23 05:00:37 PM PDT 24
Peak memory 206452 kb
Host smart-29f3bc5a-c229-41a0-84bf-37564de3a914
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=958600803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.958600803
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.512343568
Short name T2823
Test name
Test status
Simulation time 504453068 ps
CPU time 1.91 seconds
Started Jul 23 05:00:40 PM PDT 24
Finished Jul 23 05:00:49 PM PDT 24
Peak memory 206760 kb
Host smart-40263d0d-25d1-4bb4-bf6d-116e1a54c59a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=512343568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.512343568
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.916948688
Short name T2840
Test name
Test status
Simulation time 108844432 ps
CPU time 3 seconds
Started Jul 23 05:00:38 PM PDT 24
Finished Jul 23 05:00:46 PM PDT 24
Peak memory 214992 kb
Host smart-547951cd-6c08-4ea6-9088-77dbd005a0c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=916948688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.916948688
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.816201324
Short name T289
Test name
Test status
Simulation time 1151435919 ps
CPU time 5.21 seconds
Started Jul 23 05:00:35 PM PDT 24
Finished Jul 23 05:00:43 PM PDT 24
Peak memory 206804 kb
Host smart-239dc3a4-58d8-47b7-8a1c-9f1ffbfd7022
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=816201324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.816201324
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1623264711
Short name T229
Test name
Test status
Simulation time 208818236 ps
CPU time 2.06 seconds
Started Jul 23 05:00:38 PM PDT 24
Finished Jul 23 05:00:46 PM PDT 24
Peak memory 214992 kb
Host smart-27612ddb-3859-4dca-b046-3922a8149aea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623264711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.1623264711
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.24110954
Short name T252
Test name
Test status
Simulation time 72457418 ps
CPU time 0.98 seconds
Started Jul 23 05:00:36 PM PDT 24
Finished Jul 23 05:00:41 PM PDT 24
Peak memory 206828 kb
Host smart-54c251cc-4075-4c7c-a687-fe427e69e85a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=24110954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.24110954
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.260373167
Short name T2785
Test name
Test status
Simulation time 49009031 ps
CPU time 0.69 seconds
Started Jul 23 05:00:40 PM PDT 24
Finished Jul 23 05:00:48 PM PDT 24
Peak memory 206372 kb
Host smart-c01f46c4-349e-4165-b7c3-5177c50768ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=260373167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.260373167
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1485971608
Short name T2851
Test name
Test status
Simulation time 243724306 ps
CPU time 1.76 seconds
Started Jul 23 05:00:37 PM PDT 24
Finished Jul 23 05:00:44 PM PDT 24
Peak memory 206816 kb
Host smart-e38fa0c5-64ad-4902-a833-6e8080bfeee2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1485971608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.1485971608
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.4275674674
Short name T2793
Test name
Test status
Simulation time 180357546 ps
CPU time 2.73 seconds
Started Jul 23 05:00:40 PM PDT 24
Finished Jul 23 05:00:50 PM PDT 24
Peak memory 222768 kb
Host smart-0673c71e-a729-4a0a-8fbc-3abf8233e6f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4275674674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.4275674674
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.4177784424
Short name T2844
Test name
Test status
Simulation time 1649478951 ps
CPU time 5.52 seconds
Started Jul 23 05:00:39 PM PDT 24
Finished Jul 23 05:00:52 PM PDT 24
Peak memory 206800 kb
Host smart-2cf70ff0-ce4f-4436-85a2-8ae24db9e3ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4177784424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.4177784424
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2539119519
Short name T2813
Test name
Test status
Simulation time 156582010 ps
CPU time 2.02 seconds
Started Jul 23 05:00:53 PM PDT 24
Finished Jul 23 05:01:04 PM PDT 24
Peak memory 215028 kb
Host smart-4f3915b8-5480-4bdd-838d-f6d9deaa8319
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539119519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.2539119519
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2674969675
Short name T258
Test name
Test status
Simulation time 85848373 ps
CPU time 1.03 seconds
Started Jul 23 05:00:51 PM PDT 24
Finished Jul 23 05:00:56 PM PDT 24
Peak memory 206852 kb
Host smart-86f1dace-517b-406c-935e-954c8fa5b2ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2674969675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2674969675
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.437394693
Short name T2835
Test name
Test status
Simulation time 97829525 ps
CPU time 0.75 seconds
Started Jul 23 05:00:51 PM PDT 24
Finished Jul 23 05:00:56 PM PDT 24
Peak memory 206528 kb
Host smart-f02c58de-50ad-4baf-8560-63343be68a8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=437394693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.437394693
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3418639670
Short name T2814
Test name
Test status
Simulation time 150911755 ps
CPU time 1.61 seconds
Started Jul 23 05:00:52 PM PDT 24
Finished Jul 23 05:00:58 PM PDT 24
Peak memory 206660 kb
Host smart-4af4f7b8-881a-4570-9324-8c931da491f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3418639670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.3418639670
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.409351962
Short name T2776
Test name
Test status
Simulation time 284634365 ps
CPU time 2.99 seconds
Started Jul 23 05:00:35 PM PDT 24
Finished Jul 23 05:00:39 PM PDT 24
Peak memory 206788 kb
Host smart-727c83ac-269b-4779-bea3-8cd2406852da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=409351962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.409351962
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3857397712
Short name T2827
Test name
Test status
Simulation time 505906495 ps
CPU time 4.45 seconds
Started Jul 23 05:00:52 PM PDT 24
Finished Jul 23 05:01:03 PM PDT 24
Peak memory 206752 kb
Host smart-26874725-bee3-43e5-b2c6-932c32fc2971
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3857397712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.3857397712
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.2886603783
Short name T2266
Test name
Test status
Simulation time 3855961415 ps
CPU time 4.25 seconds
Started Jul 23 06:36:06 PM PDT 24
Finished Jul 23 06:36:11 PM PDT 24
Peak memory 206828 kb
Host smart-acf02096-6c4f-42f4-a1ee-779e617000eb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2886603783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.2886603783
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.469651709
Short name T2502
Test name
Test status
Simulation time 13290064297 ps
CPU time 11.86 seconds
Started Jul 23 06:36:10 PM PDT 24
Finished Jul 23 06:36:22 PM PDT 24
Peak memory 206904 kb
Host smart-45e8afb5-5e61-47c5-82d0-304e1d321578
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=469651709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.469651709
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.2089124160
Short name T11
Test name
Test status
Simulation time 23418574229 ps
CPU time 22.48 seconds
Started Jul 23 06:36:09 PM PDT 24
Finished Jul 23 06:36:32 PM PDT 24
Peak memory 206844 kb
Host smart-d8ff7129-c785-43fb-9f58-f9bdf2157362
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2089124160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.2089124160
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.3057595635
Short name T1662
Test name
Test status
Simulation time 166720115 ps
CPU time 0.84 seconds
Started Jul 23 06:36:10 PM PDT 24
Finished Jul 23 06:36:12 PM PDT 24
Peak memory 206796 kb
Host smart-664bdcae-a73f-42aa-9c62-87ec48d769fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30575
95635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.3057595635
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.3834118553
Short name T1309
Test name
Test status
Simulation time 150883911 ps
CPU time 0.83 seconds
Started Jul 23 06:36:10 PM PDT 24
Finished Jul 23 06:36:11 PM PDT 24
Peak memory 206752 kb
Host smart-64e3872e-e70a-4910-bb79-603eeac3d946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38341
18553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.3834118553
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.2125664581
Short name T1824
Test name
Test status
Simulation time 248095893 ps
CPU time 1.05 seconds
Started Jul 23 06:36:10 PM PDT 24
Finished Jul 23 06:36:12 PM PDT 24
Peak memory 206740 kb
Host smart-b2c10c7f-046a-4d0d-987d-1ba9ef6b05ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21256
64581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.2125664581
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.2538429726
Short name T505
Test name
Test status
Simulation time 507719446 ps
CPU time 1.29 seconds
Started Jul 23 06:36:18 PM PDT 24
Finished Jul 23 06:36:20 PM PDT 24
Peak memory 206760 kb
Host smart-b433860d-8f76-4af4-a7e0-4b281c9f38d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25384
29726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.2538429726
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.1829685583
Short name T1665
Test name
Test status
Simulation time 480669535 ps
CPU time 1.45 seconds
Started Jul 23 06:36:19 PM PDT 24
Finished Jul 23 06:36:21 PM PDT 24
Peak memory 206756 kb
Host smart-18243814-ba18-4337-9117-4593dc722190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18296
85583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.1829685583
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.2825141749
Short name T1645
Test name
Test status
Simulation time 139745165 ps
CPU time 0.77 seconds
Started Jul 23 06:36:20 PM PDT 24
Finished Jul 23 06:36:22 PM PDT 24
Peak memory 206716 kb
Host smart-e415e629-b212-4913-a0d7-a85f291b4f21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28251
41749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.2825141749
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.748768773
Short name T966
Test name
Test status
Simulation time 5114156411 ps
CPU time 43.08 seconds
Started Jul 23 06:36:20 PM PDT 24
Finished Jul 23 06:37:05 PM PDT 24
Peak memory 206876 kb
Host smart-3271b968-6a7f-4dd5-9b88-7f5fb72a8cd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74876
8773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.748768773
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_enable.4120740348
Short name T1940
Test name
Test status
Simulation time 47578027 ps
CPU time 0.69 seconds
Started Jul 23 06:36:20 PM PDT 24
Finished Jul 23 06:36:23 PM PDT 24
Peak memory 206744 kb
Host smart-d9b844f4-c1bd-4e3a-834c-58b337005e55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41207
40348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.4120740348
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.3457775401
Short name T1526
Test name
Test status
Simulation time 964447905 ps
CPU time 2.18 seconds
Started Jul 23 06:36:20 PM PDT 24
Finished Jul 23 06:36:24 PM PDT 24
Peak memory 206844 kb
Host smart-67d811bc-a594-44af-8730-7668e989b6dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34577
75401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.3457775401
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.2560536756
Short name T1556
Test name
Test status
Simulation time 241270552 ps
CPU time 2.19 seconds
Started Jul 23 06:36:20 PM PDT 24
Finished Jul 23 06:36:25 PM PDT 24
Peak memory 206848 kb
Host smart-d74114ee-07e2-4f78-8f22-03dd830dfe36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25605
36756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.2560536756
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.3254967969
Short name T464
Test name
Test status
Simulation time 116219292909 ps
CPU time 166.44 seconds
Started Jul 23 06:36:21 PM PDT 24
Finished Jul 23 06:39:10 PM PDT 24
Peak memory 206956 kb
Host smart-f2562489-ce57-4237-899e-9d7c5b5e6303
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3254967969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.3254967969
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.1558704679
Short name T2584
Test name
Test status
Simulation time 105329138716 ps
CPU time 144.47 seconds
Started Jul 23 06:36:21 PM PDT 24
Finished Jul 23 06:38:48 PM PDT 24
Peak memory 206912 kb
Host smart-4098600c-57d9-4462-a84c-953ac867d148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558704679 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.1558704679
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.1187855934
Short name T1133
Test name
Test status
Simulation time 110108936598 ps
CPU time 165.55 seconds
Started Jul 23 06:36:20 PM PDT 24
Finished Jul 23 06:39:08 PM PDT 24
Peak memory 206880 kb
Host smart-456e7559-ddff-44a6-b186-cd1a2fd8e624
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1187855934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.1187855934
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.4162705079
Short name T993
Test name
Test status
Simulation time 93165657583 ps
CPU time 124.97 seconds
Started Jul 23 06:36:19 PM PDT 24
Finished Jul 23 06:38:26 PM PDT 24
Peak memory 206984 kb
Host smart-44cf0742-7f9f-41c9-ba0d-7a72e2cfb5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162705079 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.4162705079
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.3987010235
Short name T211
Test name
Test status
Simulation time 100134987979 ps
CPU time 122.75 seconds
Started Jul 23 06:36:19 PM PDT 24
Finished Jul 23 06:38:24 PM PDT 24
Peak memory 206972 kb
Host smart-44c79d05-3078-457b-a13e-855c1497104c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39870
10235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.3987010235
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.2480186123
Short name T118
Test name
Test status
Simulation time 212475014 ps
CPU time 0.89 seconds
Started Jul 23 06:36:24 PM PDT 24
Finished Jul 23 06:36:26 PM PDT 24
Peak memory 206764 kb
Host smart-4d64eaaa-924d-471d-9226-f2ca82d6e30d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24801
86123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.2480186123
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.1444297250
Short name T712
Test name
Test status
Simulation time 152141442 ps
CPU time 0.75 seconds
Started Jul 23 06:36:28 PM PDT 24
Finished Jul 23 06:36:30 PM PDT 24
Peak memory 206760 kb
Host smart-1e253500-02f1-469d-9449-56ecdd72e8b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14442
97250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.1444297250
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.2117630861
Short name T1567
Test name
Test status
Simulation time 188696975 ps
CPU time 0.81 seconds
Started Jul 23 06:36:27 PM PDT 24
Finished Jul 23 06:36:29 PM PDT 24
Peak memory 206756 kb
Host smart-352b9cc2-b524-4440-8736-ab7eb375af6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21176
30861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.2117630861
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.533138058
Short name T1848
Test name
Test status
Simulation time 8761263014 ps
CPU time 82.1 seconds
Started Jul 23 06:36:18 PM PDT 24
Finished Jul 23 06:37:41 PM PDT 24
Peak memory 206900 kb
Host smart-9384c635-2596-4e4f-a0a0-03c7aff46b18
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=533138058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.533138058
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_iso_retraction.804937104
Short name T2688
Test name
Test status
Simulation time 5953529116 ps
CPU time 19.34 seconds
Started Jul 23 06:36:26 PM PDT 24
Finished Jul 23 06:36:46 PM PDT 24
Peak memory 206912 kb
Host smart-f41dadab-c69b-4d06-976c-0dd6c03e1e0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80493
7104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.804937104
Directory /workspace/0.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.1431072042
Short name T2377
Test name
Test status
Simulation time 205704345 ps
CPU time 0.85 seconds
Started Jul 23 06:36:27 PM PDT 24
Finished Jul 23 06:36:29 PM PDT 24
Peak memory 206740 kb
Host smart-5c048b55-55fe-48d4-9edc-d38b4837c3b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14310
72042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.1431072042
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.3992369904
Short name T71
Test name
Test status
Simulation time 491809833 ps
CPU time 1.34 seconds
Started Jul 23 06:36:25 PM PDT 24
Finished Jul 23 06:36:28 PM PDT 24
Peak memory 206752 kb
Host smart-feba4803-fcb0-436f-843f-5b1fdf35b7a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39923
69904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.3992369904
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.3841756922
Short name T2280
Test name
Test status
Simulation time 23270055928 ps
CPU time 24.29 seconds
Started Jul 23 06:36:24 PM PDT 24
Finished Jul 23 06:36:50 PM PDT 24
Peak memory 206792 kb
Host smart-f1139076-bd90-4d96-b5b5-214d1eb1d3ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38417
56922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.3841756922
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.1455741858
Short name T1997
Test name
Test status
Simulation time 3321179818 ps
CPU time 4.71 seconds
Started Jul 23 06:36:27 PM PDT 24
Finished Jul 23 06:36:33 PM PDT 24
Peak memory 206820 kb
Host smart-2b4026d0-b6a7-4fd9-8dd7-da586e99de68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14557
41858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.1455741858
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.2905398801
Short name T2532
Test name
Test status
Simulation time 9117486576 ps
CPU time 90.18 seconds
Started Jul 23 06:36:24 PM PDT 24
Finished Jul 23 06:37:56 PM PDT 24
Peak memory 206960 kb
Host smart-4af96538-7468-48ba-81b1-a8cfa1a893b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29053
98801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.2905398801
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.2047315704
Short name T1843
Test name
Test status
Simulation time 6698930405 ps
CPU time 183.93 seconds
Started Jul 23 06:36:24 PM PDT 24
Finished Jul 23 06:39:29 PM PDT 24
Peak memory 206888 kb
Host smart-ba19badc-609d-4471-a8eb-c61238057a20
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2047315704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.2047315704
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.1236147862
Short name T1095
Test name
Test status
Simulation time 245955571 ps
CPU time 0.96 seconds
Started Jul 23 06:36:28 PM PDT 24
Finished Jul 23 06:36:30 PM PDT 24
Peak memory 206740 kb
Host smart-ccf9be3f-e30b-4a61-914d-0127b004060b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1236147862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.1236147862
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.243292646
Short name T1802
Test name
Test status
Simulation time 194938866 ps
CPU time 0.88 seconds
Started Jul 23 06:36:24 PM PDT 24
Finished Jul 23 06:36:27 PM PDT 24
Peak memory 206676 kb
Host smart-89d5d15a-11f0-4bda-8641-91d7c14e3cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24329
2646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.243292646
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.4192597751
Short name T2110
Test name
Test status
Simulation time 5694551819 ps
CPU time 38.85 seconds
Started Jul 23 06:36:28 PM PDT 24
Finished Jul 23 06:37:08 PM PDT 24
Peak memory 206948 kb
Host smart-52050341-2d8e-43bb-9531-ceed3df9d875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41925
97751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.4192597751
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.1815285262
Short name T754
Test name
Test status
Simulation time 4037185212 ps
CPU time 102.61 seconds
Started Jul 23 06:36:29 PM PDT 24
Finished Jul 23 06:38:13 PM PDT 24
Peak memory 206916 kb
Host smart-21788666-1a2e-4865-b761-855b62af9f91
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1815285262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.1815285262
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.394052658
Short name T311
Test name
Test status
Simulation time 158783146 ps
CPU time 0.81 seconds
Started Jul 23 06:36:29 PM PDT 24
Finished Jul 23 06:36:31 PM PDT 24
Peak memory 206760 kb
Host smart-74bb9303-3b0d-40e2-a55d-fbf717f68386
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=394052658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.394052658
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.2444234253
Short name T734
Test name
Test status
Simulation time 150288874 ps
CPU time 0.76 seconds
Started Jul 23 06:36:31 PM PDT 24
Finished Jul 23 06:36:33 PM PDT 24
Peak memory 206768 kb
Host smart-ae77ced2-7174-48b8-b7e2-39fe47994228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24442
34253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.2444234253
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2551050202
Short name T72
Test name
Test status
Simulation time 515102433 ps
CPU time 1.5 seconds
Started Jul 23 06:36:30 PM PDT 24
Finished Jul 23 06:36:33 PM PDT 24
Peak memory 206740 kb
Host smart-0264ea21-81c6-49fb-9e55-12f48fa8c5d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25510
50202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2551050202
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.1355902175
Short name T2478
Test name
Test status
Simulation time 183340976 ps
CPU time 0.88 seconds
Started Jul 23 06:36:30 PM PDT 24
Finished Jul 23 06:36:32 PM PDT 24
Peak memory 206748 kb
Host smart-91596104-df2d-4d3b-be80-eca3c638f96b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13559
02175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.1355902175
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.964921664
Short name T2035
Test name
Test status
Simulation time 171532161 ps
CPU time 0.8 seconds
Started Jul 23 06:36:29 PM PDT 24
Finished Jul 23 06:36:30 PM PDT 24
Peak memory 206752 kb
Host smart-73649f40-845b-40ff-a7a9-df4d1cf0f381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96492
1664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.964921664
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.4097580084
Short name T924
Test name
Test status
Simulation time 205639613 ps
CPU time 0.85 seconds
Started Jul 23 06:36:30 PM PDT 24
Finished Jul 23 06:36:32 PM PDT 24
Peak memory 206744 kb
Host smart-9cc33f89-ee05-4ac1-91f2-6f80dcad1ac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40975
80084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.4097580084
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.3692738354
Short name T1084
Test name
Test status
Simulation time 148866693 ps
CPU time 0.77 seconds
Started Jul 23 06:36:30 PM PDT 24
Finished Jul 23 06:36:32 PM PDT 24
Peak memory 206752 kb
Host smart-3064dd9b-996e-4ec8-940e-34d881bbe789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36927
38354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.3692738354
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.4154880603
Short name T965
Test name
Test status
Simulation time 154538511 ps
CPU time 0.8 seconds
Started Jul 23 06:36:32 PM PDT 24
Finished Jul 23 06:36:34 PM PDT 24
Peak memory 206768 kb
Host smart-b35bb1fa-8ae1-49a1-9c36-561b0e7df14b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41548
80603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.4154880603
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.792799884
Short name T2278
Test name
Test status
Simulation time 187791137 ps
CPU time 0.85 seconds
Started Jul 23 06:36:30 PM PDT 24
Finished Jul 23 06:36:32 PM PDT 24
Peak memory 206760 kb
Host smart-3d57de73-d937-4781-b4f0-67a4aad22a61
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=792799884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.792799884
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.4105890254
Short name T1583
Test name
Test status
Simulation time 246349887 ps
CPU time 0.93 seconds
Started Jul 23 06:36:35 PM PDT 24
Finished Jul 23 06:36:37 PM PDT 24
Peak memory 206932 kb
Host smart-d64ac1fb-8452-4f0d-ad81-e8799cb15a51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41058
90254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.4105890254
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.1556218740
Short name T2185
Test name
Test status
Simulation time 266637783 ps
CPU time 0.91 seconds
Started Jul 23 06:36:38 PM PDT 24
Finished Jul 23 06:36:40 PM PDT 24
Peak memory 206752 kb
Host smart-a2fa931c-3f73-4f4c-b720-68e21f9068aa
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1556218740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.1556218740
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.4165655043
Short name T195
Test name
Test status
Simulation time 194419711 ps
CPU time 0.87 seconds
Started Jul 23 06:36:39 PM PDT 24
Finished Jul 23 06:36:41 PM PDT 24
Peak memory 206716 kb
Host smart-ff9aac76-01d8-45b3-a89d-5049cc4a2e6c
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4165655043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.4165655043
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.1088470754
Short name T861
Test name
Test status
Simulation time 150810480 ps
CPU time 0.79 seconds
Started Jul 23 06:36:38 PM PDT 24
Finished Jul 23 06:36:40 PM PDT 24
Peak memory 206660 kb
Host smart-19d98eb0-6372-47b0-b4a0-40d4509f55ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10884
70754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.1088470754
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.2291055947
Short name T1054
Test name
Test status
Simulation time 43323758 ps
CPU time 0.65 seconds
Started Jul 23 06:36:36 PM PDT 24
Finished Jul 23 06:36:38 PM PDT 24
Peak memory 206756 kb
Host smart-7fab7bb1-84a3-485f-aaf5-c0c5451eef35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22910
55947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.2291055947
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.195121685
Short name T241
Test name
Test status
Simulation time 22166489274 ps
CPU time 43.2 seconds
Started Jul 23 06:36:37 PM PDT 24
Finished Jul 23 06:37:22 PM PDT 24
Peak memory 206988 kb
Host smart-6d76b728-53b0-4e7b-9ba9-28cb8d58df27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19512
1685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.195121685
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.3136728494
Short name T581
Test name
Test status
Simulation time 200134466 ps
CPU time 0.89 seconds
Started Jul 23 06:36:37 PM PDT 24
Finished Jul 23 06:36:39 PM PDT 24
Peak memory 206764 kb
Host smart-0b9ea16a-cd78-46be-9c60-b23e8148843d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31367
28494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.3136728494
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.2782630549
Short name T353
Test name
Test status
Simulation time 247621063 ps
CPU time 0.91 seconds
Started Jul 23 06:36:37 PM PDT 24
Finished Jul 23 06:36:39 PM PDT 24
Peak memory 206776 kb
Host smart-09401c9b-8727-434a-9de9-3a3ef8629fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27826
30549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.2782630549
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.1826021648
Short name T170
Test name
Test status
Simulation time 13961816569 ps
CPU time 284.2 seconds
Started Jul 23 06:36:36 PM PDT 24
Finished Jul 23 06:41:22 PM PDT 24
Peak memory 206948 kb
Host smart-7301a684-25dc-41aa-81b4-7d47b1c9ed3c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1826021648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.1826021648
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.4245037872
Short name T1501
Test name
Test status
Simulation time 13066040855 ps
CPU time 253.72 seconds
Started Jul 23 06:36:40 PM PDT 24
Finished Jul 23 06:40:55 PM PDT 24
Peak memory 206964 kb
Host smart-320fbf76-0ee6-4267-b6f3-090f3eb16b95
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4245037872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.4245037872
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.1172035169
Short name T937
Test name
Test status
Simulation time 19694778721 ps
CPU time 154.94 seconds
Started Jul 23 06:36:36 PM PDT 24
Finished Jul 23 06:39:13 PM PDT 24
Peak memory 206968 kb
Host smart-1aa45cdc-abf7-4ed4-929d-004eda90b697
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1172035169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.1172035169
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.4213454326
Short name T2557
Test name
Test status
Simulation time 194124926 ps
CPU time 0.91 seconds
Started Jul 23 06:36:36 PM PDT 24
Finished Jul 23 06:36:38 PM PDT 24
Peak memory 206732 kb
Host smart-90ab98bb-2442-452b-bafd-65f1b2267ac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42134
54326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.4213454326
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.2607695097
Short name T1102
Test name
Test status
Simulation time 225922387 ps
CPU time 0.86 seconds
Started Jul 23 06:36:36 PM PDT 24
Finished Jul 23 06:36:38 PM PDT 24
Peak memory 206760 kb
Host smart-817a9c91-6fda-4c3b-b62b-1638930f458f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26076
95097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.2607695097
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.189123500
Short name T2444
Test name
Test status
Simulation time 140622089 ps
CPU time 0.81 seconds
Started Jul 23 06:36:37 PM PDT 24
Finished Jul 23 06:36:39 PM PDT 24
Peak memory 206752 kb
Host smart-50c9f108-2e30-4eb6-bfa6-40df93fb4220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18912
3500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.189123500
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.3209922140
Short name T77
Test name
Test status
Simulation time 189064936 ps
CPU time 0.84 seconds
Started Jul 23 06:36:37 PM PDT 24
Finished Jul 23 06:36:39 PM PDT 24
Peak memory 206776 kb
Host smart-a770b463-f915-40ad-bd5b-6ca7cd8c70b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32099
22140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.3209922140
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.3621936680
Short name T1149
Test name
Test status
Simulation time 303398999 ps
CPU time 0.97 seconds
Started Jul 23 06:36:40 PM PDT 24
Finished Jul 23 06:36:42 PM PDT 24
Peak memory 206772 kb
Host smart-53fa7b09-2180-4518-96be-a7a98ad90225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36219
36680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.3621936680
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.3292000352
Short name T811
Test name
Test status
Simulation time 243045776 ps
CPU time 0.86 seconds
Started Jul 23 06:36:37 PM PDT 24
Finished Jul 23 06:36:39 PM PDT 24
Peak memory 206772 kb
Host smart-d9c473c5-727d-4302-ad8f-d3668cd20c5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32920
00352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.3292000352
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.4198786482
Short name T2123
Test name
Test status
Simulation time 158346316 ps
CPU time 0.8 seconds
Started Jul 23 06:36:41 PM PDT 24
Finished Jul 23 06:36:43 PM PDT 24
Peak memory 206748 kb
Host smart-38f35ed3-797b-44c5-83cc-4d147b39f7a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41987
86482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.4198786482
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1915246163
Short name T842
Test name
Test status
Simulation time 213845214 ps
CPU time 0.94 seconds
Started Jul 23 06:36:43 PM PDT 24
Finished Jul 23 06:36:45 PM PDT 24
Peak memory 206764 kb
Host smart-e9cb2b83-67b1-4cd9-ae85-7323cc8c4c6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19152
46163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1915246163
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.1695199175
Short name T801
Test name
Test status
Simulation time 4294280470 ps
CPU time 114.97 seconds
Started Jul 23 06:36:40 PM PDT 24
Finished Jul 23 06:38:36 PM PDT 24
Peak memory 206864 kb
Host smart-45c107e3-473b-4348-828d-ea34d8547693
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1695199175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.1695199175
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.1416904065
Short name T150
Test name
Test status
Simulation time 181226838 ps
CPU time 0.9 seconds
Started Jul 23 06:36:42 PM PDT 24
Finished Jul 23 06:36:44 PM PDT 24
Peak memory 206756 kb
Host smart-0ad01f89-88d0-46ed-99d7-193c4acc80cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14169
04065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.1416904065
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.3483991034
Short name T1091
Test name
Test status
Simulation time 191339508 ps
CPU time 0.83 seconds
Started Jul 23 06:36:42 PM PDT 24
Finished Jul 23 06:36:43 PM PDT 24
Peak memory 206776 kb
Host smart-23dbb3fe-6a76-49f5-8e4e-24360f3c45db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34839
91034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.3483991034
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.1565520653
Short name T1871
Test name
Test status
Simulation time 1134343714 ps
CPU time 2.56 seconds
Started Jul 23 06:36:39 PM PDT 24
Finished Jul 23 06:36:43 PM PDT 24
Peak memory 206824 kb
Host smart-40e06f57-04da-451a-b842-44d78d07bf8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15655
20653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.1565520653
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.2245872788
Short name T2097
Test name
Test status
Simulation time 7362611199 ps
CPU time 70.47 seconds
Started Jul 23 06:36:44 PM PDT 24
Finished Jul 23 06:37:55 PM PDT 24
Peak memory 206980 kb
Host smart-aa2d6ef1-8e6d-47a1-b1e7-ae33dbbb06b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22458
72788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.2245872788
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.2600646719
Short name T174
Test name
Test status
Simulation time 23695717748 ps
CPU time 155.67 seconds
Started Jul 23 06:36:51 PM PDT 24
Finished Jul 23 06:39:28 PM PDT 24
Peak memory 207000 kb
Host smart-2fe3411c-31bf-4a94-b49b-16c367a1cf7a
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2600646719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.2600646719
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.3034577304
Short name T1075
Test name
Test status
Simulation time 120719505 ps
CPU time 0.75 seconds
Started Jul 23 06:37:19 PM PDT 24
Finished Jul 23 06:37:22 PM PDT 24
Peak memory 206716 kb
Host smart-4f799a7c-afe2-4af7-b586-447e0720b9d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3034577304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.3034577304
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.583323239
Short name T1132
Test name
Test status
Simulation time 4174999247 ps
CPU time 5.14 seconds
Started Jul 23 06:36:49 PM PDT 24
Finished Jul 23 06:36:57 PM PDT 24
Peak memory 206884 kb
Host smart-35d5a788-e952-49c9-ac9c-5c62566a5845
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=583323239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.583323239
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.2155859586
Short name T729
Test name
Test status
Simulation time 13388726503 ps
CPU time 12.8 seconds
Started Jul 23 06:36:50 PM PDT 24
Finished Jul 23 06:37:05 PM PDT 24
Peak memory 206788 kb
Host smart-3a4b826d-d4c3-488a-8775-9c6266ac7b53
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2155859586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.2155859586
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.3969388058
Short name T2242
Test name
Test status
Simulation time 23348162505 ps
CPU time 23.96 seconds
Started Jul 23 06:36:49 PM PDT 24
Finished Jul 23 06:37:15 PM PDT 24
Peak memory 206816 kb
Host smart-29989be0-3541-421c-bf9f-8cdf989d695c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3969388058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.3969388058
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.2890474746
Short name T1790
Test name
Test status
Simulation time 161215734 ps
CPU time 0.74 seconds
Started Jul 23 06:36:49 PM PDT 24
Finished Jul 23 06:36:52 PM PDT 24
Peak memory 206744 kb
Host smart-d7bbaef1-4756-441b-be3c-401e9b18a691
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28904
74746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.2890474746
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.513247272
Short name T1817
Test name
Test status
Simulation time 135524890 ps
CPU time 0.79 seconds
Started Jul 23 06:36:49 PM PDT 24
Finished Jul 23 06:36:52 PM PDT 24
Peak memory 206708 kb
Host smart-b8a4e220-dd1a-494d-9410-bd992d3cc58f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51324
7272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.513247272
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.384394444
Short name T1336
Test name
Test status
Simulation time 151500229 ps
CPU time 0.8 seconds
Started Jul 23 06:36:48 PM PDT 24
Finished Jul 23 06:36:51 PM PDT 24
Peak memory 206756 kb
Host smart-1ac2d10c-2031-4b45-9ea0-24967df022a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38439
4444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.384394444
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.663381686
Short name T1349
Test name
Test status
Simulation time 271699885 ps
CPU time 1.02 seconds
Started Jul 23 06:36:49 PM PDT 24
Finished Jul 23 06:36:53 PM PDT 24
Peak memory 206748 kb
Host smart-02bc6909-40db-40ba-b6b1-317d28f56ab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66338
1686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.663381686
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.32550675
Short name T774
Test name
Test status
Simulation time 1174258370 ps
CPU time 2.7 seconds
Started Jul 23 06:36:58 PM PDT 24
Finished Jul 23 06:37:01 PM PDT 24
Peak memory 206872 kb
Host smart-e2112716-d451-44b9-86e2-1d396aee1632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32550
675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.32550675
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.3195684224
Short name T1822
Test name
Test status
Simulation time 6655752566 ps
CPU time 14.83 seconds
Started Jul 23 06:36:56 PM PDT 24
Finished Jul 23 06:37:12 PM PDT 24
Peak memory 206848 kb
Host smart-5280e432-ff2d-405b-a04a-065477eb6229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31956
84224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.3195684224
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.1813218255
Short name T1804
Test name
Test status
Simulation time 496870527 ps
CPU time 1.42 seconds
Started Jul 23 06:36:57 PM PDT 24
Finished Jul 23 06:36:59 PM PDT 24
Peak memory 206732 kb
Host smart-16829e20-c334-45a2-8547-d93079613e8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18132
18255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.1813218255
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.2625847931
Short name T749
Test name
Test status
Simulation time 134103080 ps
CPU time 0.8 seconds
Started Jul 23 06:36:57 PM PDT 24
Finished Jul 23 06:36:59 PM PDT 24
Peak memory 206756 kb
Host smart-fe7db3a7-f49c-459c-a30a-f8d9ba3c2b6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26258
47931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.2625847931
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.3650022381
Short name T1680
Test name
Test status
Simulation time 42366818 ps
CPU time 0.66 seconds
Started Jul 23 06:36:57 PM PDT 24
Finished Jul 23 06:36:59 PM PDT 24
Peak memory 206756 kb
Host smart-a8048172-b482-4b57-872c-6860e69c8d14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36500
22381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.3650022381
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.2736225938
Short name T2282
Test name
Test status
Simulation time 776451693 ps
CPU time 2.28 seconds
Started Jul 23 06:36:56 PM PDT 24
Finished Jul 23 06:37:00 PM PDT 24
Peak memory 206864 kb
Host smart-6021ad72-3e91-499a-b83d-ab3c2a4e5574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27362
25938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.2736225938
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.671103287
Short name T2490
Test name
Test status
Simulation time 162384527 ps
CPU time 1.19 seconds
Started Jul 23 06:36:59 PM PDT 24
Finished Jul 23 06:37:01 PM PDT 24
Peak memory 206796 kb
Host smart-9daa96f9-53a0-400b-bd87-d3f334e28243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67110
3287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.671103287
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.928478412
Short name T894
Test name
Test status
Simulation time 94174569153 ps
CPU time 141.39 seconds
Started Jul 23 06:36:57 PM PDT 24
Finished Jul 23 06:39:20 PM PDT 24
Peak memory 206976 kb
Host smart-81e7b920-1870-4ea3-b1d7-af4edc9f45f4
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=928478412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.928478412
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.675840570
Short name T1875
Test name
Test status
Simulation time 101256816579 ps
CPU time 145.58 seconds
Started Jul 23 06:36:56 PM PDT 24
Finished Jul 23 06:39:22 PM PDT 24
Peak memory 206916 kb
Host smart-988440a6-cba5-4e9a-9477-01026a59d753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675840570 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.675840570
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.399013143
Short name T367
Test name
Test status
Simulation time 99103394835 ps
CPU time 128.42 seconds
Started Jul 23 06:36:56 PM PDT 24
Finished Jul 23 06:39:05 PM PDT 24
Peak memory 206988 kb
Host smart-85d8478a-7d60-492d-ae84-8c2126313113
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=399013143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.399013143
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.971470352
Short name T1196
Test name
Test status
Simulation time 88256619465 ps
CPU time 130.32 seconds
Started Jul 23 06:36:55 PM PDT 24
Finished Jul 23 06:39:06 PM PDT 24
Peak memory 206992 kb
Host smart-5728145a-65be-4d93-9e01-9f8fa4ce9ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971470352 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.971470352
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.2549737418
Short name T2232
Test name
Test status
Simulation time 109151668493 ps
CPU time 145.46 seconds
Started Jul 23 06:37:06 PM PDT 24
Finished Jul 23 06:39:33 PM PDT 24
Peak memory 206848 kb
Host smart-4f94edad-4f8e-4830-bf2b-f8f1fba4015a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25497
37418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.2549737418
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.1269458778
Short name T2201
Test name
Test status
Simulation time 185359531 ps
CPU time 0.85 seconds
Started Jul 23 06:37:06 PM PDT 24
Finished Jul 23 06:37:08 PM PDT 24
Peak memory 206684 kb
Host smart-8f3aa814-40f6-4d7a-a551-a473133266af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12694
58778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.1269458778
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.3988384943
Short name T2236
Test name
Test status
Simulation time 141371639 ps
CPU time 0.77 seconds
Started Jul 23 06:37:01 PM PDT 24
Finished Jul 23 06:37:03 PM PDT 24
Peak memory 206748 kb
Host smart-592d67a2-dc11-42b3-8659-e6123c7fc51c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39883
84943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.3988384943
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.476997354
Short name T2402
Test name
Test status
Simulation time 182985038 ps
CPU time 0.88 seconds
Started Jul 23 06:37:03 PM PDT 24
Finished Jul 23 06:37:05 PM PDT 24
Peak memory 206768 kb
Host smart-d082a54c-b6fc-4597-a7fa-f4a597939a86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47699
7354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.476997354
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.3071984677
Short name T2187
Test name
Test status
Simulation time 8316419042 ps
CPU time 233.91 seconds
Started Jul 23 06:37:00 PM PDT 24
Finished Jul 23 06:40:55 PM PDT 24
Peak memory 206884 kb
Host smart-37569e2b-bac5-4129-9a1b-87608839f55f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3071984677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.3071984677
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_iso_retraction.3452287776
Short name T1099
Test name
Test status
Simulation time 8797553566 ps
CPU time 30.5 seconds
Started Jul 23 06:37:04 PM PDT 24
Finished Jul 23 06:37:36 PM PDT 24
Peak memory 206968 kb
Host smart-c6bfb784-4fd9-4ae9-8c94-57d56ff2cc58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34522
87776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.3452287776
Directory /workspace/1.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.3776271984
Short name T895
Test name
Test status
Simulation time 201186788 ps
CPU time 0.88 seconds
Started Jul 23 06:37:00 PM PDT 24
Finished Jul 23 06:37:02 PM PDT 24
Peak memory 206724 kb
Host smart-043ef8a4-1f7f-4b6e-8c90-266130ad7377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37762
71984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.3776271984
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.344306367
Short name T455
Test name
Test status
Simulation time 23280202793 ps
CPU time 21.75 seconds
Started Jul 23 06:37:06 PM PDT 24
Finished Jul 23 06:37:29 PM PDT 24
Peak memory 206736 kb
Host smart-a6985d19-70d7-4aa2-9a8c-43656559d5e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34430
6367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.344306367
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.1318941365
Short name T1574
Test name
Test status
Simulation time 3347196118 ps
CPU time 4.14 seconds
Started Jul 23 06:37:02 PM PDT 24
Finished Jul 23 06:37:07 PM PDT 24
Peak memory 206808 kb
Host smart-263c0578-8bbd-4005-abdc-7386966e6e29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13189
41365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.1318941365
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.1090452839
Short name T2694
Test name
Test status
Simulation time 14215926685 ps
CPU time 133.01 seconds
Started Jul 23 06:37:04 PM PDT 24
Finished Jul 23 06:39:18 PM PDT 24
Peak memory 206988 kb
Host smart-25ee09f5-3b59-44da-8c63-6d3866577ae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10904
52839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.1090452839
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.1607496519
Short name T1410
Test name
Test status
Simulation time 7337897934 ps
CPU time 70.58 seconds
Started Jul 23 06:37:02 PM PDT 24
Finished Jul 23 06:38:14 PM PDT 24
Peak memory 206904 kb
Host smart-93341985-e25a-4ba4-916b-690b42170c7a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1607496519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.1607496519
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.2594256211
Short name T1852
Test name
Test status
Simulation time 253312321 ps
CPU time 0.94 seconds
Started Jul 23 06:37:02 PM PDT 24
Finished Jul 23 06:37:04 PM PDT 24
Peak memory 206668 kb
Host smart-2784df85-b382-497f-972c-00ee9ecc2a76
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2594256211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.2594256211
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.1143728847
Short name T1694
Test name
Test status
Simulation time 207266067 ps
CPU time 0.93 seconds
Started Jul 23 06:37:02 PM PDT 24
Finished Jul 23 06:37:04 PM PDT 24
Peak memory 206756 kb
Host smart-40733540-ebe4-4782-b7f2-bf572d5ac131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11437
28847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.1143728847
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.1527574989
Short name T2409
Test name
Test status
Simulation time 7013627093 ps
CPU time 193.09 seconds
Started Jul 23 06:37:01 PM PDT 24
Finished Jul 23 06:40:15 PM PDT 24
Peak memory 206908 kb
Host smart-447fa86e-e490-41b5-aa92-f6cfd7185343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15275
74989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.1527574989
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.56621194
Short name T1766
Test name
Test status
Simulation time 3979201408 ps
CPU time 36.79 seconds
Started Jul 23 06:37:02 PM PDT 24
Finished Jul 23 06:37:40 PM PDT 24
Peak memory 206964 kb
Host smart-0ed86242-f223-4fcd-87b3-3ad2a4e90f28
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=56621194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.56621194
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.2018102413
Short name T1138
Test name
Test status
Simulation time 162601031 ps
CPU time 0.82 seconds
Started Jul 23 06:37:02 PM PDT 24
Finished Jul 23 06:37:04 PM PDT 24
Peak memory 206764 kb
Host smart-67a6a30c-3333-423a-9929-737344b0f807
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2018102413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.2018102413
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.3545792250
Short name T2134
Test name
Test status
Simulation time 145427628 ps
CPU time 0.79 seconds
Started Jul 23 06:37:02 PM PDT 24
Finished Jul 23 06:37:05 PM PDT 24
Peak memory 206712 kb
Host smart-f313169d-0900-4685-a65b-d5300a3c03ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35457
92250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.3545792250
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.1997249099
Short name T621
Test name
Test status
Simulation time 213458023 ps
CPU time 0.89 seconds
Started Jul 23 06:37:11 PM PDT 24
Finished Jul 23 06:37:14 PM PDT 24
Peak memory 206748 kb
Host smart-201c6714-5ba7-48b0-a667-dfadb792cfc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19972
49099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.1997249099
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.2302895566
Short name T381
Test name
Test status
Simulation time 176625989 ps
CPU time 0.83 seconds
Started Jul 23 06:37:10 PM PDT 24
Finished Jul 23 06:37:14 PM PDT 24
Peak memory 206760 kb
Host smart-8cb45458-820c-4a2f-9625-fb6c69763d3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23028
95566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.2302895566
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.4194518097
Short name T1329
Test name
Test status
Simulation time 210715587 ps
CPU time 0.87 seconds
Started Jul 23 06:37:09 PM PDT 24
Finished Jul 23 06:37:12 PM PDT 24
Peak memory 206736 kb
Host smart-7f0caf1d-d447-4bd2-8aba-b20236aa8fad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41945
18097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.4194518097
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.28297597
Short name T2008
Test name
Test status
Simulation time 156882855 ps
CPU time 0.83 seconds
Started Jul 23 06:37:07 PM PDT 24
Finished Jul 23 06:37:10 PM PDT 24
Peak memory 206776 kb
Host smart-38c68523-8d94-4581-a33f-2f947482d509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28297
597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.28297597
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.3631680089
Short name T2227
Test name
Test status
Simulation time 207182704 ps
CPU time 0.98 seconds
Started Jul 23 06:37:08 PM PDT 24
Finished Jul 23 06:37:11 PM PDT 24
Peak memory 206760 kb
Host smart-f64e0680-172d-4042-aa4a-2855dcba4038
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3631680089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.3631680089
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.3268801911
Short name T196
Test name
Test status
Simulation time 225257978 ps
CPU time 0.94 seconds
Started Jul 23 06:37:09 PM PDT 24
Finished Jul 23 06:37:13 PM PDT 24
Peak memory 206752 kb
Host smart-7bb4a1d6-db28-452d-b610-f3b413f883d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32688
01911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.3268801911
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.535388254
Short name T1116
Test name
Test status
Simulation time 145853822 ps
CPU time 0.79 seconds
Started Jul 23 06:37:07 PM PDT 24
Finished Jul 23 06:37:10 PM PDT 24
Peak memory 206736 kb
Host smart-c63bb31e-ba7c-4920-8767-c2fa697110f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53538
8254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.535388254
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.3378013168
Short name T2133
Test name
Test status
Simulation time 70994777 ps
CPU time 0.7 seconds
Started Jul 23 06:37:11 PM PDT 24
Finished Jul 23 06:37:14 PM PDT 24
Peak memory 206748 kb
Host smart-bc58ae4a-82b4-416e-bec2-64f6e2ccf72b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33780
13168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.3378013168
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.2251512203
Short name T244
Test name
Test status
Simulation time 19684353068 ps
CPU time 43.51 seconds
Started Jul 23 06:37:08 PM PDT 24
Finished Jul 23 06:37:53 PM PDT 24
Peak memory 206988 kb
Host smart-b74cf1f5-f52d-46b0-880f-1e8c65786343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22515
12203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.2251512203
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.2310200151
Short name T1271
Test name
Test status
Simulation time 190829593 ps
CPU time 0.85 seconds
Started Jul 23 06:37:10 PM PDT 24
Finished Jul 23 06:37:14 PM PDT 24
Peak memory 206760 kb
Host smart-d6d2b645-9488-4dc3-ad6c-459fe7d3c317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23102
00151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.2310200151
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.436277785
Short name T2665
Test name
Test status
Simulation time 212545681 ps
CPU time 0.94 seconds
Started Jul 23 06:37:08 PM PDT 24
Finished Jul 23 06:37:12 PM PDT 24
Peak memory 206724 kb
Host smart-4335ce44-9d38-4579-b74b-18140c3c285b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43627
7785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.436277785
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.2792902663
Short name T932
Test name
Test status
Simulation time 12650402009 ps
CPU time 273.36 seconds
Started Jul 23 06:37:08 PM PDT 24
Finished Jul 23 06:41:43 PM PDT 24
Peak memory 206920 kb
Host smart-65721f2e-ed97-4a8e-86ce-1790c9be83c2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2792902663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.2792902663
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.2244501095
Short name T1963
Test name
Test status
Simulation time 7369166937 ps
CPU time 92.38 seconds
Started Jul 23 06:37:09 PM PDT 24
Finished Jul 23 06:38:43 PM PDT 24
Peak memory 206948 kb
Host smart-947212f3-4e70-4e57-bfd8-c3cb6d55d531
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2244501095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.2244501095
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.2607542567
Short name T1879
Test name
Test status
Simulation time 7406889612 ps
CPU time 111.83 seconds
Started Jul 23 06:37:09 PM PDT 24
Finished Jul 23 06:39:04 PM PDT 24
Peak memory 206880 kb
Host smart-e4a30d4b-44ec-4435-8d92-d17397d48856
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2607542567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.2607542567
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.3677746908
Short name T1106
Test name
Test status
Simulation time 188490573 ps
CPU time 0.84 seconds
Started Jul 23 06:37:09 PM PDT 24
Finished Jul 23 06:37:13 PM PDT 24
Peak memory 206764 kb
Host smart-d8a58dfd-073d-409c-9e0e-5fda81559416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36777
46908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.3677746908
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.2059148831
Short name T957
Test name
Test status
Simulation time 166465489 ps
CPU time 0.87 seconds
Started Jul 23 06:37:07 PM PDT 24
Finished Jul 23 06:37:10 PM PDT 24
Peak memory 206736 kb
Host smart-19fce098-07f4-4490-9e74-bbbafdaa8f43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20591
48831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.2059148831
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.1432983615
Short name T657
Test name
Test status
Simulation time 168630330 ps
CPU time 0.8 seconds
Started Jul 23 06:37:09 PM PDT 24
Finished Jul 23 06:37:13 PM PDT 24
Peak memory 206676 kb
Host smart-2702e642-03e8-4f33-84e1-b232fc256707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14329
83615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.1432983615
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.1765952249
Short name T190
Test name
Test status
Simulation time 1222868617 ps
CPU time 2.02 seconds
Started Jul 23 06:37:21 PM PDT 24
Finished Jul 23 06:37:25 PM PDT 24
Peak memory 225392 kb
Host smart-bc3cd938-c8be-4e86-b66d-2749982d2731
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1765952249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.1765952249
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.1863787965
Short name T1331
Test name
Test status
Simulation time 396902676 ps
CPU time 1.34 seconds
Started Jul 23 06:37:10 PM PDT 24
Finished Jul 23 06:37:15 PM PDT 24
Peak memory 206776 kb
Host smart-649b9787-cd29-4031-83b0-d8519b6f03c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18637
87965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.1863787965
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.255767247
Short name T352
Test name
Test status
Simulation time 318961022 ps
CPU time 1.05 seconds
Started Jul 23 06:37:08 PM PDT 24
Finished Jul 23 06:37:11 PM PDT 24
Peak memory 206736 kb
Host smart-ad30cc91-82b3-4414-a72c-44f5a1e273af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25576
7247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.255767247
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.2042426506
Short name T1398
Test name
Test status
Simulation time 179751092 ps
CPU time 0.79 seconds
Started Jul 23 06:37:08 PM PDT 24
Finished Jul 23 06:37:11 PM PDT 24
Peak memory 206768 kb
Host smart-89014e15-991d-4870-b484-61bcc26b3328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20424
26506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.2042426506
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.2245211926
Short name T920
Test name
Test status
Simulation time 179827850 ps
CPU time 0.83 seconds
Started Jul 23 06:37:09 PM PDT 24
Finished Jul 23 06:37:13 PM PDT 24
Peak memory 206772 kb
Host smart-b240dd1e-4d39-438f-b370-6961a096b0a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22452
11926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.2245211926
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.3170469205
Short name T492
Test name
Test status
Simulation time 254800799 ps
CPU time 0.95 seconds
Started Jul 23 06:37:20 PM PDT 24
Finished Jul 23 06:37:23 PM PDT 24
Peak memory 206748 kb
Host smart-bc23d094-a36c-4816-a4bc-0f8408a535c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31704
69205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.3170469205
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.1849778285
Short name T919
Test name
Test status
Simulation time 6063155654 ps
CPU time 41.89 seconds
Started Jul 23 06:37:18 PM PDT 24
Finished Jul 23 06:38:02 PM PDT 24
Peak memory 206944 kb
Host smart-c673b0c0-aad8-4aa2-b600-fcadcd9ee3ab
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1849778285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.1849778285
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.2261553847
Short name T1144
Test name
Test status
Simulation time 164400757 ps
CPU time 0.81 seconds
Started Jul 23 06:37:17 PM PDT 24
Finished Jul 23 06:37:19 PM PDT 24
Peak memory 206756 kb
Host smart-72633146-57f4-4b82-aba7-b8b2b50f1440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22615
53847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.2261553847
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.3213705968
Short name T790
Test name
Test status
Simulation time 151799365 ps
CPU time 0.78 seconds
Started Jul 23 06:37:18 PM PDT 24
Finished Jul 23 06:37:21 PM PDT 24
Peak memory 206764 kb
Host smart-893e985d-4e7c-4f67-9252-cfcedae4840c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32137
05968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.3213705968
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.1829183236
Short name T746
Test name
Test status
Simulation time 482168876 ps
CPU time 1.31 seconds
Started Jul 23 06:37:17 PM PDT 24
Finished Jul 23 06:37:20 PM PDT 24
Peak memory 206740 kb
Host smart-a4a7b9bc-cb58-4461-8de5-298287ede9b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18291
83236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.1829183236
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.4857816
Short name T802
Test name
Test status
Simulation time 3710054708 ps
CPU time 33.76 seconds
Started Jul 23 06:37:19 PM PDT 24
Finished Jul 23 06:37:55 PM PDT 24
Peak memory 206932 kb
Host smart-43e1d0a1-7aff-4120-b415-fb1ffc8c9b57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48578
16 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.4857816
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.1724055956
Short name T2740
Test name
Test status
Simulation time 41771234 ps
CPU time 0.72 seconds
Started Jul 23 06:40:04 PM PDT 24
Finished Jul 23 06:40:07 PM PDT 24
Peak memory 206720 kb
Host smart-9280f1b9-f0f5-48f3-aec6-6c9c86b2e5a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1724055956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.1724055956
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.668587872
Short name T1899
Test name
Test status
Simulation time 3786651565 ps
CPU time 4.42 seconds
Started Jul 23 06:39:50 PM PDT 24
Finished Jul 23 06:39:56 PM PDT 24
Peak memory 206840 kb
Host smart-f3416935-a50e-4b52-839f-de35887a7b37
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=668587872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.668587872
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.2693919764
Short name T2717
Test name
Test status
Simulation time 13325196965 ps
CPU time 12.01 seconds
Started Jul 23 06:39:55 PM PDT 24
Finished Jul 23 06:40:09 PM PDT 24
Peak memory 206820 kb
Host smart-d41e7abf-6be1-47f2-8328-519d4fed774a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2693919764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.2693919764
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.4242088977
Short name T1021
Test name
Test status
Simulation time 23446369903 ps
CPU time 22.76 seconds
Started Jul 23 06:39:54 PM PDT 24
Finished Jul 23 06:40:19 PM PDT 24
Peak memory 206972 kb
Host smart-9b0680ee-34e8-4f47-a420-c962153b9022
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4242088977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.4242088977
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.1897718046
Short name T710
Test name
Test status
Simulation time 165180645 ps
CPU time 0.8 seconds
Started Jul 23 06:39:52 PM PDT 24
Finished Jul 23 06:39:54 PM PDT 24
Peak memory 206772 kb
Host smart-37060c75-5550-44f8-b2d6-41b8043cc117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18977
18046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.1897718046
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.4086805466
Short name T792
Test name
Test status
Simulation time 142909922 ps
CPU time 0.75 seconds
Started Jul 23 06:39:52 PM PDT 24
Finished Jul 23 06:39:54 PM PDT 24
Peak memory 206748 kb
Host smart-40962adc-e3e2-4572-8e25-62c039198f1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40868
05466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.4086805466
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.137619818
Short name T1463
Test name
Test status
Simulation time 427558095 ps
CPU time 1.29 seconds
Started Jul 23 06:39:55 PM PDT 24
Finished Jul 23 06:39:58 PM PDT 24
Peak memory 206784 kb
Host smart-6a65aab0-f364-4b29-bdcc-bbbaf9a2961d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13761
9818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.137619818
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.1009523124
Short name T2366
Test name
Test status
Simulation time 816354923 ps
CPU time 1.97 seconds
Started Jul 23 06:39:50 PM PDT 24
Finished Jul 23 06:39:53 PM PDT 24
Peak memory 206868 kb
Host smart-2fcebe72-01ef-4c51-b6b3-6a02ffc54b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10095
23124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.1009523124
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.3609838432
Short name T1559
Test name
Test status
Simulation time 17329936348 ps
CPU time 32.78 seconds
Started Jul 23 06:39:50 PM PDT 24
Finished Jul 23 06:40:25 PM PDT 24
Peak memory 206944 kb
Host smart-da026221-5e1d-4b5a-a658-4aa443455842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36098
38432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.3609838432
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.4252750487
Short name T1689
Test name
Test status
Simulation time 427699210 ps
CPU time 1.32 seconds
Started Jul 23 06:39:52 PM PDT 24
Finished Jul 23 06:39:55 PM PDT 24
Peak memory 206768 kb
Host smart-a2da40fb-2df4-424e-acf8-82b1d7598cc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42527
50487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.4252750487
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.3920638435
Short name T483
Test name
Test status
Simulation time 132384633 ps
CPU time 0.74 seconds
Started Jul 23 06:39:50 PM PDT 24
Finished Jul 23 06:39:52 PM PDT 24
Peak memory 206760 kb
Host smart-662801bb-fd6f-4df2-ac1c-ae3bbf8e108b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39206
38435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.3920638435
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.3236392024
Short name T1792
Test name
Test status
Simulation time 35905095 ps
CPU time 0.66 seconds
Started Jul 23 06:39:52 PM PDT 24
Finished Jul 23 06:39:55 PM PDT 24
Peak memory 206736 kb
Host smart-f891cbef-4ed9-4d68-b6ac-beb650a76f20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32363
92024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.3236392024
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.62200244
Short name T1168
Test name
Test status
Simulation time 945119442 ps
CPU time 2.29 seconds
Started Jul 23 06:39:51 PM PDT 24
Finished Jul 23 06:39:55 PM PDT 24
Peak memory 206888 kb
Host smart-8896d48a-430c-4cf6-9283-f99f97ff37ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62200
244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.62200244
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.1850222924
Short name T706
Test name
Test status
Simulation time 222574031 ps
CPU time 0.88 seconds
Started Jul 23 06:39:51 PM PDT 24
Finished Jul 23 06:39:53 PM PDT 24
Peak memory 206708 kb
Host smart-8a96c64e-4019-411d-8a1e-b75806d5efde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18502
22924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.1850222924
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.3305265177
Short name T962
Test name
Test status
Simulation time 137163594 ps
CPU time 0.85 seconds
Started Jul 23 06:39:51 PM PDT 24
Finished Jul 23 06:39:54 PM PDT 24
Peak memory 206772 kb
Host smart-96aa2c0a-bc83-4758-aca8-a36c071fa571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33052
65177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.3305265177
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.2320479991
Short name T1090
Test name
Test status
Simulation time 175295462 ps
CPU time 0.8 seconds
Started Jul 23 06:39:52 PM PDT 24
Finished Jul 23 06:39:54 PM PDT 24
Peak memory 206760 kb
Host smart-32b79a89-1cfb-457d-819b-abd4c4d44305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23204
79991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.2320479991
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_iso_retraction.2406680627
Short name T2289
Test name
Test status
Simulation time 7395550279 ps
CPU time 64.6 seconds
Started Jul 23 06:39:52 PM PDT 24
Finished Jul 23 06:40:59 PM PDT 24
Peak memory 206964 kb
Host smart-5e0f8992-7c1e-40b3-941a-fa13f7303edd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24066
80627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.2406680627
Directory /workspace/10.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.2034122453
Short name T917
Test name
Test status
Simulation time 224179169 ps
CPU time 0.88 seconds
Started Jul 23 06:39:56 PM PDT 24
Finished Jul 23 06:39:59 PM PDT 24
Peak memory 206764 kb
Host smart-22c3b920-12cd-4523-8e61-97a8b1915ad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20341
22453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.2034122453
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.1532031779
Short name T1237
Test name
Test status
Simulation time 23311987890 ps
CPU time 30.41 seconds
Started Jul 23 06:39:55 PM PDT 24
Finished Jul 23 06:40:27 PM PDT 24
Peak memory 206808 kb
Host smart-18f1fb3c-7c43-4f4a-9ed8-2fd4c560dde2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15320
31779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.1532031779
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.1301204780
Short name T1610
Test name
Test status
Simulation time 3289315435 ps
CPU time 4.28 seconds
Started Jul 23 06:39:51 PM PDT 24
Finished Jul 23 06:39:57 PM PDT 24
Peak memory 206804 kb
Host smart-5274c1ae-9f1b-42d4-a7a4-87db76f3c6d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13012
04780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.1301204780
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.4133872047
Short name T99
Test name
Test status
Simulation time 5984959382 ps
CPU time 55.9 seconds
Started Jul 23 06:39:55 PM PDT 24
Finished Jul 23 06:40:54 PM PDT 24
Peak memory 206980 kb
Host smart-aa58981a-4a0b-4bbe-ba14-7312a246e391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41338
72047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.4133872047
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.2052994054
Short name T1223
Test name
Test status
Simulation time 4153495913 ps
CPU time 29.15 seconds
Started Jul 23 06:39:56 PM PDT 24
Finished Jul 23 06:40:27 PM PDT 24
Peak memory 206912 kb
Host smart-12a9ab18-c2a0-4129-b5ca-3077edb7a0f9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2052994054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.2052994054
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.83252765
Short name T1312
Test name
Test status
Simulation time 248452725 ps
CPU time 0.94 seconds
Started Jul 23 06:39:57 PM PDT 24
Finished Jul 23 06:40:01 PM PDT 24
Peak memory 206748 kb
Host smart-ed569fb2-f144-4324-8399-6a9694d57e58
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=83252765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.83252765
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.537490467
Short name T2548
Test name
Test status
Simulation time 188201053 ps
CPU time 0.84 seconds
Started Jul 23 06:39:56 PM PDT 24
Finished Jul 23 06:40:00 PM PDT 24
Peak memory 206752 kb
Host smart-9848ed44-e0dc-4642-ba23-6f5d009759f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53749
0467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.537490467
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.3468842997
Short name T702
Test name
Test status
Simulation time 4148878684 ps
CPU time 39.75 seconds
Started Jul 23 06:39:54 PM PDT 24
Finished Jul 23 06:40:36 PM PDT 24
Peak memory 206864 kb
Host smart-f4fe35a2-4473-47cc-95de-a5e3fc84ba9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34688
42997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.3468842997
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.3225778538
Short name T1856
Test name
Test status
Simulation time 6296943990 ps
CPU time 59.05 seconds
Started Jul 23 06:40:00 PM PDT 24
Finished Jul 23 06:41:01 PM PDT 24
Peak memory 206900 kb
Host smart-6e52b7e1-42c1-4dd5-a374-6fc0f57c0199
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3225778538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.3225778538
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.1707986910
Short name T2223
Test name
Test status
Simulation time 184343795 ps
CPU time 0.82 seconds
Started Jul 23 06:39:56 PM PDT 24
Finished Jul 23 06:40:00 PM PDT 24
Peak memory 206716 kb
Host smart-179651eb-40af-402d-ba0d-f8bf356e3700
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1707986910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.1707986910
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.1444816601
Short name T469
Test name
Test status
Simulation time 227068453 ps
CPU time 0.91 seconds
Started Jul 23 06:39:59 PM PDT 24
Finished Jul 23 06:40:03 PM PDT 24
Peak memory 206752 kb
Host smart-b25b5804-0418-48bc-837d-3ed1704c8aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14448
16601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.1444816601
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.1314213730
Short name T498
Test name
Test status
Simulation time 163888853 ps
CPU time 0.8 seconds
Started Jul 23 06:39:57 PM PDT 24
Finished Jul 23 06:40:00 PM PDT 24
Peak memory 206928 kb
Host smart-31c12022-8c4d-44e4-aa63-80a1801fd085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13142
13730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.1314213730
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.2330148293
Short name T1018
Test name
Test status
Simulation time 170326487 ps
CPU time 0.8 seconds
Started Jul 23 06:39:57 PM PDT 24
Finished Jul 23 06:40:00 PM PDT 24
Peak memory 206772 kb
Host smart-717974c3-902f-4161-8b54-059fd7c0c498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23301
48293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.2330148293
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.3059854501
Short name T1964
Test name
Test status
Simulation time 171553224 ps
CPU time 0.77 seconds
Started Jul 23 06:40:00 PM PDT 24
Finished Jul 23 06:40:03 PM PDT 24
Peak memory 206736 kb
Host smart-0c949932-8fee-4add-bf04-ffe0c2029a43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30598
54501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.3059854501
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.1304194447
Short name T561
Test name
Test status
Simulation time 156727092 ps
CPU time 0.78 seconds
Started Jul 23 06:39:57 PM PDT 24
Finished Jul 23 06:40:01 PM PDT 24
Peak memory 206756 kb
Host smart-c7e2a53e-0d50-4e40-bc3a-151c4b6925ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13041
94447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.1304194447
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.461702585
Short name T2363
Test name
Test status
Simulation time 213870715 ps
CPU time 0.93 seconds
Started Jul 23 06:39:55 PM PDT 24
Finished Jul 23 06:39:58 PM PDT 24
Peak memory 206732 kb
Host smart-7d9bfcc5-3a77-4d69-8fd6-ecfbaf846167
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=461702585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.461702585
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.1725126705
Short name T2679
Test name
Test status
Simulation time 50041867 ps
CPU time 0.64 seconds
Started Jul 23 06:39:57 PM PDT 24
Finished Jul 23 06:40:01 PM PDT 24
Peak memory 206732 kb
Host smart-216d3870-ab08-4f30-a26b-8edb4deda613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17251
26705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.1725126705
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.2362329312
Short name T1511
Test name
Test status
Simulation time 8213565030 ps
CPU time 17.7 seconds
Started Jul 23 06:39:57 PM PDT 24
Finished Jul 23 06:40:18 PM PDT 24
Peak memory 206980 kb
Host smart-bc90d9d2-3d26-4f79-a39c-fa49e07b1d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23623
29312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.2362329312
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.1856005516
Short name T2405
Test name
Test status
Simulation time 173448310 ps
CPU time 0.81 seconds
Started Jul 23 06:39:57 PM PDT 24
Finished Jul 23 06:40:01 PM PDT 24
Peak memory 206772 kb
Host smart-ae4d2a1e-e833-4326-b573-0a7633b7fd17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18560
05516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.1856005516
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.361857887
Short name T1983
Test name
Test status
Simulation time 210317212 ps
CPU time 0.89 seconds
Started Jul 23 06:39:56 PM PDT 24
Finished Jul 23 06:39:59 PM PDT 24
Peak memory 206724 kb
Host smart-96f54e6d-6c1a-4878-a10b-4660946f3bc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36185
7887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.361857887
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.1484230939
Short name T588
Test name
Test status
Simulation time 226978823 ps
CPU time 0.95 seconds
Started Jul 23 06:39:56 PM PDT 24
Finished Jul 23 06:39:59 PM PDT 24
Peak memory 206732 kb
Host smart-a12ed8cb-9cfa-4988-812e-fd3a5bb4969a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14842
30939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.1484230939
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.4247783724
Short name T2297
Test name
Test status
Simulation time 161458499 ps
CPU time 0.8 seconds
Started Jul 23 06:39:57 PM PDT 24
Finished Jul 23 06:40:00 PM PDT 24
Peak memory 206736 kb
Host smart-4b6829f2-5688-49d8-bd6f-79ca9bc86786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42477
83724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.4247783724
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.1994662767
Short name T507
Test name
Test status
Simulation time 144031824 ps
CPU time 0.77 seconds
Started Jul 23 06:40:00 PM PDT 24
Finished Jul 23 06:40:03 PM PDT 24
Peak memory 206736 kb
Host smart-d27f2a7b-3be7-46a0-82bc-55e3f7e87fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19946
62767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.1994662767
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.804617067
Short name T1516
Test name
Test status
Simulation time 174598072 ps
CPU time 0.78 seconds
Started Jul 23 06:39:56 PM PDT 24
Finished Jul 23 06:40:00 PM PDT 24
Peak memory 206744 kb
Host smart-82ccb1ff-e6da-41be-aca2-71cf291735d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80461
7067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.804617067
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.1485744766
Short name T1402
Test name
Test status
Simulation time 170746941 ps
CPU time 0.76 seconds
Started Jul 23 06:39:56 PM PDT 24
Finished Jul 23 06:39:59 PM PDT 24
Peak memory 206772 kb
Host smart-31572f01-f1e4-4460-b8fa-d02a9db336e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14857
44766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.1485744766
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.4035229859
Short name T1198
Test name
Test status
Simulation time 213731342 ps
CPU time 0.91 seconds
Started Jul 23 06:40:05 PM PDT 24
Finished Jul 23 06:40:09 PM PDT 24
Peak memory 206764 kb
Host smart-08b80cc0-f551-44bc-99f3-de334531c934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40352
29859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.4035229859
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.2254790201
Short name T154
Test name
Test status
Simulation time 5547128713 ps
CPU time 142.53 seconds
Started Jul 23 06:40:03 PM PDT 24
Finished Jul 23 06:42:27 PM PDT 24
Peak memory 206840 kb
Host smart-ee603d66-e691-4be1-89be-c4ac339e3a13
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2254790201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.2254790201
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.2566393525
Short name T2025
Test name
Test status
Simulation time 156225725 ps
CPU time 0.78 seconds
Started Jul 23 06:40:03 PM PDT 24
Finished Jul 23 06:40:05 PM PDT 24
Peak memory 206736 kb
Host smart-01809f85-7dc7-4a97-b9db-ca6a1f32c77d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25663
93525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.2566393525
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.2789758381
Short name T303
Test name
Test status
Simulation time 167467009 ps
CPU time 0.79 seconds
Started Jul 23 06:40:05 PM PDT 24
Finished Jul 23 06:40:08 PM PDT 24
Peak memory 206756 kb
Host smart-33ef3aa4-b5fc-4e36-8726-df8e475cd1bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27897
58381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.2789758381
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.3539182486
Short name T2656
Test name
Test status
Simulation time 1245091937 ps
CPU time 2.59 seconds
Started Jul 23 06:40:03 PM PDT 24
Finished Jul 23 06:40:07 PM PDT 24
Peak memory 206932 kb
Host smart-8225079e-f60f-4823-a199-1176d87cd56d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35391
82486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.3539182486
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.660177779
Short name T973
Test name
Test status
Simulation time 4741233591 ps
CPU time 132.25 seconds
Started Jul 23 06:40:04 PM PDT 24
Finished Jul 23 06:42:19 PM PDT 24
Peak memory 206820 kb
Host smart-15008b96-4253-4bc4-a261-e8ed0347e8cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66017
7779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.660177779
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.1363878324
Short name T1264
Test name
Test status
Simulation time 39505150 ps
CPU time 0.67 seconds
Started Jul 23 06:40:17 PM PDT 24
Finished Jul 23 06:40:20 PM PDT 24
Peak memory 206708 kb
Host smart-d40e8ac5-07d8-4c06-9965-f27afe6124db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1363878324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.1363878324
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.1384603887
Short name T2108
Test name
Test status
Simulation time 3760493965 ps
CPU time 4.7 seconds
Started Jul 23 06:40:05 PM PDT 24
Finished Jul 23 06:40:12 PM PDT 24
Peak memory 206892 kb
Host smart-f25453d0-2f32-44b2-a899-c14ddde67e23
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1384603887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.1384603887
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.3320568851
Short name T2616
Test name
Test status
Simulation time 13445456949 ps
CPU time 12.61 seconds
Started Jul 23 06:40:04 PM PDT 24
Finished Jul 23 06:40:20 PM PDT 24
Peak memory 206888 kb
Host smart-e6fd03d5-3fb5-435a-8d30-081f0285eb75
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3320568851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.3320568851
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.1367222938
Short name T2222
Test name
Test status
Simulation time 23435549364 ps
CPU time 25.88 seconds
Started Jul 23 06:40:05 PM PDT 24
Finished Jul 23 06:40:34 PM PDT 24
Peak memory 206928 kb
Host smart-f4646475-68a8-45ee-992a-e353d3a9ec44
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1367222938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.1367222938
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.1688120244
Short name T1592
Test name
Test status
Simulation time 167696369 ps
CPU time 0.86 seconds
Started Jul 23 06:40:05 PM PDT 24
Finished Jul 23 06:40:09 PM PDT 24
Peak memory 206660 kb
Host smart-54a6302d-5935-4a81-bdf7-74e06c5c7bd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16881
20244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.1688120244
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.1232329287
Short name T951
Test name
Test status
Simulation time 147440327 ps
CPU time 0.79 seconds
Started Jul 23 06:40:04 PM PDT 24
Finished Jul 23 06:40:07 PM PDT 24
Peak memory 206772 kb
Host smart-e091134e-c258-460e-957d-b261f8f8bed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12323
29287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.1232329287
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.1773791690
Short name T2015
Test name
Test status
Simulation time 495422586 ps
CPU time 1.32 seconds
Started Jul 23 06:40:07 PM PDT 24
Finished Jul 23 06:40:11 PM PDT 24
Peak memory 206740 kb
Host smart-c371bba1-ae4b-4bac-8bfe-e580b6e16c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17737
91690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.1773791690
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.3136967077
Short name T1758
Test name
Test status
Simulation time 21425742733 ps
CPU time 34.01 seconds
Started Jul 23 06:40:07 PM PDT 24
Finished Jul 23 06:40:44 PM PDT 24
Peak memory 206904 kb
Host smart-7ad7e3a2-1d4a-425f-be0c-5d5ff3612184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31369
67077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.3136967077
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.3770841004
Short name T83
Test name
Test status
Simulation time 387080961 ps
CPU time 1.29 seconds
Started Jul 23 06:40:04 PM PDT 24
Finished Jul 23 06:40:09 PM PDT 24
Peak memory 206756 kb
Host smart-da78ed57-d9d2-42cf-82be-751f6961bb57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37708
41004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.3770841004
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.2728269750
Short name T461
Test name
Test status
Simulation time 196287683 ps
CPU time 0.82 seconds
Started Jul 23 06:40:07 PM PDT 24
Finished Jul 23 06:40:10 PM PDT 24
Peak memory 206740 kb
Host smart-3cdc8998-ed37-470e-8beb-668d1e3cab5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27282
69750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.2728269750
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.1644783807
Short name T830
Test name
Test status
Simulation time 45143750 ps
CPU time 0.7 seconds
Started Jul 23 06:40:04 PM PDT 24
Finished Jul 23 06:40:07 PM PDT 24
Peak memory 206728 kb
Host smart-30873935-041d-4d90-b6f9-3083ea2097a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16447
83807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.1644783807
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.3792419667
Short name T914
Test name
Test status
Simulation time 1019646530 ps
CPU time 2.46 seconds
Started Jul 23 06:40:05 PM PDT 24
Finished Jul 23 06:40:11 PM PDT 24
Peak memory 206840 kb
Host smart-2a682a03-132d-4afa-a791-4823b2185090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37924
19667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.3792419667
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.2031980116
Short name T92
Test name
Test status
Simulation time 195928948 ps
CPU time 1.3 seconds
Started Jul 23 06:40:04 PM PDT 24
Finished Jul 23 06:40:08 PM PDT 24
Peak memory 206908 kb
Host smart-65ab0712-0648-42a5-b56a-1c457bb55ef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20319
80116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.2031980116
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.2690662555
Short name T784
Test name
Test status
Simulation time 158682376 ps
CPU time 0.82 seconds
Started Jul 23 06:40:10 PM PDT 24
Finished Jul 23 06:40:14 PM PDT 24
Peak memory 206752 kb
Host smart-6862e2ac-15aa-4331-8543-a511c0ee88eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26906
62555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.2690662555
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.1735784507
Short name T403
Test name
Test status
Simulation time 149793464 ps
CPU time 0.82 seconds
Started Jul 23 06:40:10 PM PDT 24
Finished Jul 23 06:40:12 PM PDT 24
Peak memory 206764 kb
Host smart-19c580bb-0941-4490-b8de-872a77c585c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17357
84507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.1735784507
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.2716772111
Short name T1870
Test name
Test status
Simulation time 235821700 ps
CPU time 0.95 seconds
Started Jul 23 06:40:12 PM PDT 24
Finished Jul 23 06:40:15 PM PDT 24
Peak memory 206772 kb
Host smart-a32e739f-bf3b-458a-851a-8a17d1bd5600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27167
72111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.2716772111
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_iso_retraction.827896716
Short name T2554
Test name
Test status
Simulation time 11678385116 ps
CPU time 33.39 seconds
Started Jul 23 06:40:10 PM PDT 24
Finished Jul 23 06:40:45 PM PDT 24
Peak memory 206972 kb
Host smart-8f4fbfd9-6e12-4d24-a514-ec9e6177aa3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82789
6716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.827896716
Directory /workspace/11.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.3250053701
Short name T1510
Test name
Test status
Simulation time 227004058 ps
CPU time 0.92 seconds
Started Jul 23 06:40:16 PM PDT 24
Finished Jul 23 06:40:19 PM PDT 24
Peak memory 206724 kb
Host smart-0dac0821-3137-4f39-b5b1-34707f13bea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32500
53701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.3250053701
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.3419553107
Short name T2349
Test name
Test status
Simulation time 23330731000 ps
CPU time 24.08 seconds
Started Jul 23 06:40:10 PM PDT 24
Finished Jul 23 06:40:35 PM PDT 24
Peak memory 206716 kb
Host smart-340d27fe-1fa6-4ae3-bdbb-b287e024d917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34195
53107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.3419553107
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.3581369876
Short name T335
Test name
Test status
Simulation time 3349302880 ps
CPU time 3.79 seconds
Started Jul 23 06:40:10 PM PDT 24
Finished Jul 23 06:40:15 PM PDT 24
Peak memory 206812 kb
Host smart-1f52a82c-9db4-43ad-a620-80e6d90f7f4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35813
69876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.3581369876
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.2290039785
Short name T2316
Test name
Test status
Simulation time 10036524854 ps
CPU time 278.72 seconds
Started Jul 23 06:40:11 PM PDT 24
Finished Jul 23 06:44:52 PM PDT 24
Peak memory 206960 kb
Host smart-0a3501bb-6892-4cef-827c-746cf5df8737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22900
39785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.2290039785
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.3604773478
Short name T912
Test name
Test status
Simulation time 5076434197 ps
CPU time 136.19 seconds
Started Jul 23 06:40:13 PM PDT 24
Finished Jul 23 06:42:32 PM PDT 24
Peak memory 206916 kb
Host smart-25ae1c4f-1e66-4326-b4ed-6f2630f4c4f7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3604773478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.3604773478
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.487742560
Short name T751
Test name
Test status
Simulation time 255452611 ps
CPU time 0.99 seconds
Started Jul 23 06:40:10 PM PDT 24
Finished Jul 23 06:40:14 PM PDT 24
Peak memory 206768 kb
Host smart-1b483a32-22a7-4abf-adaa-5760d4da0811
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=487742560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.487742560
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.2545224581
Short name T2398
Test name
Test status
Simulation time 187535914 ps
CPU time 0.83 seconds
Started Jul 23 06:40:13 PM PDT 24
Finished Jul 23 06:40:16 PM PDT 24
Peak memory 206772 kb
Host smart-147d5120-e811-40f6-9a13-77c5feb400a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25452
24581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.2545224581
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.209661359
Short name T459
Test name
Test status
Simulation time 7069677346 ps
CPU time 65.21 seconds
Started Jul 23 06:40:11 PM PDT 24
Finished Jul 23 06:41:19 PM PDT 24
Peak memory 206964 kb
Host smart-8b0475fa-e991-4839-bfd4-fe526665c1ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20966
1359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.209661359
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.621526370
Short name T1117
Test name
Test status
Simulation time 5580553412 ps
CPU time 164.06 seconds
Started Jul 23 06:40:13 PM PDT 24
Finished Jul 23 06:42:59 PM PDT 24
Peak memory 206900 kb
Host smart-3c313df8-7efa-455d-bb01-7977be4b91e1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=621526370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.621526370
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.3838644772
Short name T606
Test name
Test status
Simulation time 154272047 ps
CPU time 0.77 seconds
Started Jul 23 06:40:16 PM PDT 24
Finished Jul 23 06:40:19 PM PDT 24
Peak memory 206724 kb
Host smart-0d8beb23-245e-447c-a505-2208d3ff3065
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3838644772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.3838644772
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.692849866
Short name T2319
Test name
Test status
Simulation time 140631424 ps
CPU time 0.76 seconds
Started Jul 23 06:40:11 PM PDT 24
Finished Jul 23 06:40:14 PM PDT 24
Peak memory 206692 kb
Host smart-f5e64474-3f3b-4cab-b53c-871ecbca748e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69284
9866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.692849866
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.2463625976
Short name T137
Test name
Test status
Simulation time 168616062 ps
CPU time 0.86 seconds
Started Jul 23 06:40:10 PM PDT 24
Finished Jul 23 06:40:13 PM PDT 24
Peak memory 206740 kb
Host smart-a820d794-02b1-4e24-9b93-e10be1cd9dfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24636
25976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.2463625976
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.1844880290
Short name T1803
Test name
Test status
Simulation time 251256910 ps
CPU time 0.93 seconds
Started Jul 23 06:40:12 PM PDT 24
Finished Jul 23 06:40:15 PM PDT 24
Peak memory 205752 kb
Host smart-cb6af844-44f5-4b90-b90a-8aa182de1b1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18448
80290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.1844880290
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.1764635677
Short name T1747
Test name
Test status
Simulation time 153799142 ps
CPU time 0.77 seconds
Started Jul 23 06:40:12 PM PDT 24
Finished Jul 23 06:40:15 PM PDT 24
Peak memory 206768 kb
Host smart-d8371283-bcbd-4a30-b9d0-3824860b53e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17646
35677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.1764635677
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.3709399931
Short name T2658
Test name
Test status
Simulation time 177326682 ps
CPU time 0.88 seconds
Started Jul 23 06:40:10 PM PDT 24
Finished Jul 23 06:40:13 PM PDT 24
Peak memory 206748 kb
Host smart-7847abb0-f643-4908-b601-9728c97590d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37093
99931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.3709399931
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.4027713109
Short name T1930
Test name
Test status
Simulation time 151294521 ps
CPU time 0.79 seconds
Started Jul 23 06:40:11 PM PDT 24
Finished Jul 23 06:40:14 PM PDT 24
Peak memory 206772 kb
Host smart-b323b37d-f4d0-45a1-8c50-8698237266bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40277
13109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.4027713109
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.2337910686
Short name T1491
Test name
Test status
Simulation time 193844218 ps
CPU time 0.86 seconds
Started Jul 23 06:40:11 PM PDT 24
Finished Jul 23 06:40:14 PM PDT 24
Peak memory 206696 kb
Host smart-f0d2f40f-fc98-46d6-ae98-d99e34d9e112
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2337910686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.2337910686
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.666968053
Short name T1293
Test name
Test status
Simulation time 195052326 ps
CPU time 0.78 seconds
Started Jul 23 06:40:09 PM PDT 24
Finished Jul 23 06:40:12 PM PDT 24
Peak memory 206692 kb
Host smart-9037da56-c431-4a90-8d93-c11294ec62ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66696
8053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.666968053
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.2983642457
Short name T1136
Test name
Test status
Simulation time 7903238308 ps
CPU time 18.78 seconds
Started Jul 23 06:40:16 PM PDT 24
Finished Jul 23 06:40:37 PM PDT 24
Peak memory 206952 kb
Host smart-9c798994-fb77-432d-be98-b29838e96677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29836
42457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.2983642457
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.3456411623
Short name T2125
Test name
Test status
Simulation time 221628948 ps
CPU time 0.89 seconds
Started Jul 23 06:40:12 PM PDT 24
Finished Jul 23 06:40:15 PM PDT 24
Peak memory 205544 kb
Host smart-64a16506-f1df-4cb1-8473-91164e54970d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34564
11623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.3456411623
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.3111536117
Short name T775
Test name
Test status
Simulation time 207098800 ps
CPU time 0.86 seconds
Started Jul 23 06:40:10 PM PDT 24
Finished Jul 23 06:40:13 PM PDT 24
Peak memory 206744 kb
Host smart-ca803bfc-31cb-47aa-adcb-d59f2180e8b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31115
36117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.3111536117
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.253931322
Short name T1192
Test name
Test status
Simulation time 165580025 ps
CPU time 0.8 seconds
Started Jul 23 06:40:10 PM PDT 24
Finished Jul 23 06:40:13 PM PDT 24
Peak memory 206760 kb
Host smart-ffac90ee-2770-458a-9354-3e806c30b2d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25393
1322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.253931322
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.47517177
Short name T820
Test name
Test status
Simulation time 204904924 ps
CPU time 0.86 seconds
Started Jul 23 06:40:12 PM PDT 24
Finished Jul 23 06:40:15 PM PDT 24
Peak memory 206764 kb
Host smart-db3ca30d-8136-4272-931c-64a99acd8526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47517
177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.47517177
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.2290900620
Short name T1566
Test name
Test status
Simulation time 156280532 ps
CPU time 0.75 seconds
Started Jul 23 06:40:09 PM PDT 24
Finished Jul 23 06:40:12 PM PDT 24
Peak memory 206716 kb
Host smart-75169234-4dfa-4727-aff6-13613f987c9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22909
00620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.2290900620
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.1496622215
Short name T1954
Test name
Test status
Simulation time 155149174 ps
CPU time 0.81 seconds
Started Jul 23 06:40:10 PM PDT 24
Finished Jul 23 06:40:14 PM PDT 24
Peak memory 206736 kb
Host smart-9ee93dff-31bc-4a6f-9508-4553e623d0b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14966
22215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.1496622215
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.3837597399
Short name T1613
Test name
Test status
Simulation time 159457160 ps
CPU time 0.81 seconds
Started Jul 23 06:40:14 PM PDT 24
Finished Jul 23 06:40:17 PM PDT 24
Peak memory 206776 kb
Host smart-bfd7fdeb-2ccf-42b5-9041-afa118458ca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38375
97399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.3837597399
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.1777037668
Short name T1805
Test name
Test status
Simulation time 212601258 ps
CPU time 0.96 seconds
Started Jul 23 06:40:10 PM PDT 24
Finished Jul 23 06:40:13 PM PDT 24
Peak memory 206768 kb
Host smart-97a463e9-9a26-48ed-9101-22fcd17ef4f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17770
37668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.1777037668
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.3155859203
Short name T1524
Test name
Test status
Simulation time 5672166442 ps
CPU time 41.39 seconds
Started Jul 23 06:40:15 PM PDT 24
Finished Jul 23 06:40:58 PM PDT 24
Peak memory 206976 kb
Host smart-729807ce-a2a1-4edc-95b4-1e6cef0b2e51
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3155859203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.3155859203
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.4079017689
Short name T2691
Test name
Test status
Simulation time 185337678 ps
CPU time 0.85 seconds
Started Jul 23 06:40:18 PM PDT 24
Finished Jul 23 06:40:21 PM PDT 24
Peak memory 206732 kb
Host smart-68a55aa5-43ae-4742-a718-27fc1a34ed97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40790
17689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.4079017689
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.534659579
Short name T214
Test name
Test status
Simulation time 160124921 ps
CPU time 0.79 seconds
Started Jul 23 06:40:17 PM PDT 24
Finished Jul 23 06:40:20 PM PDT 24
Peak memory 206772 kb
Host smart-49bb1829-675c-460b-8b48-ed02b0c50482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53465
9579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.534659579
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.2660461802
Short name T1736
Test name
Test status
Simulation time 387211749 ps
CPU time 1.27 seconds
Started Jul 23 06:40:18 PM PDT 24
Finished Jul 23 06:40:21 PM PDT 24
Peak memory 206748 kb
Host smart-07c50a77-5cd2-441b-9357-c409bb2ea3d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26604
61802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.2660461802
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.401157316
Short name T1985
Test name
Test status
Simulation time 5993261431 ps
CPU time 44.41 seconds
Started Jul 23 06:40:16 PM PDT 24
Finished Jul 23 06:41:02 PM PDT 24
Peak memory 206892 kb
Host smart-098394ec-a23b-42af-aa7d-a12fdf1e5f22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40115
7316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.401157316
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.2543002779
Short name T1978
Test name
Test status
Simulation time 44302734 ps
CPU time 0.69 seconds
Started Jul 23 06:40:30 PM PDT 24
Finished Jul 23 06:40:33 PM PDT 24
Peak memory 206696 kb
Host smart-a84a9603-6d90-475c-852d-abad82166d4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2543002779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.2543002779
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.131040362
Short name T2138
Test name
Test status
Simulation time 3956995715 ps
CPU time 4.96 seconds
Started Jul 23 06:40:16 PM PDT 24
Finished Jul 23 06:40:23 PM PDT 24
Peak memory 206972 kb
Host smart-47202786-db9e-40a3-a350-b02ad80d1aa9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=131040362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.131040362
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.2273290554
Short name T2631
Test name
Test status
Simulation time 13318820240 ps
CPU time 16.11 seconds
Started Jul 23 06:40:15 PM PDT 24
Finished Jul 23 06:40:33 PM PDT 24
Peak memory 206820 kb
Host smart-ad30861b-e3aa-4011-b7fc-4d90bf887343
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2273290554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.2273290554
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.2211652660
Short name T2460
Test name
Test status
Simulation time 23348600457 ps
CPU time 28.44 seconds
Started Jul 23 06:40:16 PM PDT 24
Finished Jul 23 06:40:46 PM PDT 24
Peak memory 206780 kb
Host smart-5ad1b076-1445-4ec3-9c26-ee0445e4a4f2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2211652660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.2211652660
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.340883472
Short name T915
Test name
Test status
Simulation time 189663019 ps
CPU time 0.81 seconds
Started Jul 23 06:40:16 PM PDT 24
Finished Jul 23 06:40:19 PM PDT 24
Peak memory 206744 kb
Host smart-05410ca1-67bd-4cbc-8810-b7208fcaf32f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34088
3472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.340883472
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.3109687549
Short name T2096
Test name
Test status
Simulation time 184741450 ps
CPU time 0.85 seconds
Started Jul 23 06:40:17 PM PDT 24
Finished Jul 23 06:40:20 PM PDT 24
Peak memory 206756 kb
Host smart-e762e3cd-dde4-49ad-bfea-1f8a40889567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31096
87549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.3109687549
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.435590307
Short name T1862
Test name
Test status
Simulation time 386398793 ps
CPU time 1.19 seconds
Started Jul 23 06:40:18 PM PDT 24
Finished Jul 23 06:40:21 PM PDT 24
Peak memory 206776 kb
Host smart-24ed9c7c-3dc9-4cff-9003-8410736a7408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43559
0307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.435590307
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.3694094883
Short name T2082
Test name
Test status
Simulation time 705911391 ps
CPU time 1.71 seconds
Started Jul 23 06:40:17 PM PDT 24
Finished Jul 23 06:40:21 PM PDT 24
Peak memory 206924 kb
Host smart-169ed338-8991-4e43-8ce0-6fa3f769ae0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36940
94883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.3694094883
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.796791044
Short name T1351
Test name
Test status
Simulation time 22748798132 ps
CPU time 46.14 seconds
Started Jul 23 06:40:17 PM PDT 24
Finished Jul 23 06:41:06 PM PDT 24
Peak memory 206960 kb
Host smart-2a4e3161-a506-4264-aab4-ae3d678190b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79679
1044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.796791044
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.937323498
Short name T2002
Test name
Test status
Simulation time 468519497 ps
CPU time 1.39 seconds
Started Jul 23 06:40:16 PM PDT 24
Finished Jul 23 06:40:19 PM PDT 24
Peak memory 206776 kb
Host smart-5dafaf83-15f2-454e-b2da-b3e339f726bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93732
3498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.937323498
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.2523898053
Short name T832
Test name
Test status
Simulation time 180949325 ps
CPU time 0.79 seconds
Started Jul 23 06:40:17 PM PDT 24
Finished Jul 23 06:40:19 PM PDT 24
Peak memory 206776 kb
Host smart-c02d6604-f7e3-454a-8a27-a521f400fced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25238
98053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.2523898053
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.997290942
Short name T2254
Test name
Test status
Simulation time 53513454 ps
CPU time 0.7 seconds
Started Jul 23 06:40:18 PM PDT 24
Finished Jul 23 06:40:20 PM PDT 24
Peak memory 206744 kb
Host smart-4b75a7eb-f392-421a-ab45-3350bd7b2b53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99729
0942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.997290942
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.2218626550
Short name T1697
Test name
Test status
Simulation time 920479087 ps
CPU time 2.17 seconds
Started Jul 23 06:40:15 PM PDT 24
Finished Jul 23 06:40:19 PM PDT 24
Peak memory 206876 kb
Host smart-7080e799-6a24-4170-a27b-802a0bf30c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22186
26550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.2218626550
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.425716681
Short name T2591
Test name
Test status
Simulation time 198883508 ps
CPU time 1.35 seconds
Started Jul 23 06:40:16 PM PDT 24
Finished Jul 23 06:40:20 PM PDT 24
Peak memory 206904 kb
Host smart-214519f1-9aca-4eb9-9ccd-7c6e0c51b41f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42571
6681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.425716681
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.510384994
Short name T2644
Test name
Test status
Simulation time 212779034 ps
CPU time 0.86 seconds
Started Jul 23 06:40:18 PM PDT 24
Finished Jul 23 06:40:21 PM PDT 24
Peak memory 206748 kb
Host smart-786c4022-57f4-4389-9967-d7bfb63b617d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51038
4994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.510384994
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.2881448001
Short name T1570
Test name
Test status
Simulation time 146669117 ps
CPU time 0.76 seconds
Started Jul 23 06:40:25 PM PDT 24
Finished Jul 23 06:40:28 PM PDT 24
Peak memory 206756 kb
Host smart-3f5ebf50-2e83-4792-9048-21a956476a8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28814
48001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.2881448001
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.1694313512
Short name T499
Test name
Test status
Simulation time 209938562 ps
CPU time 0.94 seconds
Started Jul 23 06:40:24 PM PDT 24
Finished Jul 23 06:40:27 PM PDT 24
Peak memory 206708 kb
Host smart-215c2367-4a5d-42cc-ba34-556274a1bc49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16943
13512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.1694313512
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_iso_retraction.3436486825
Short name T563
Test name
Test status
Simulation time 7496870586 ps
CPU time 62.97 seconds
Started Jul 23 06:40:25 PM PDT 24
Finished Jul 23 06:41:31 PM PDT 24
Peak memory 206988 kb
Host smart-fb1675f8-bacc-465d-bd60-3e150b6b4105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34364
86825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.3436486825
Directory /workspace/12.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.1617382116
Short name T1621
Test name
Test status
Simulation time 280073607 ps
CPU time 1 seconds
Started Jul 23 06:40:22 PM PDT 24
Finished Jul 23 06:40:24 PM PDT 24
Peak memory 206768 kb
Host smart-ec831ff5-66be-4175-a694-dfc741ae9dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16173
82116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.1617382116
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.1097033904
Short name T501
Test name
Test status
Simulation time 23283767466 ps
CPU time 23.86 seconds
Started Jul 23 06:40:26 PM PDT 24
Finished Jul 23 06:40:52 PM PDT 24
Peak memory 206792 kb
Host smart-4d7bbdc1-fa3b-446b-80da-13000b638dc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10970
33904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.1097033904
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.2972726267
Short name T1155
Test name
Test status
Simulation time 3353938887 ps
CPU time 4.24 seconds
Started Jul 23 06:40:23 PM PDT 24
Finished Jul 23 06:40:30 PM PDT 24
Peak memory 206720 kb
Host smart-21a3b741-b592-494b-945c-fb5c07dc8425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29727
26267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.2972726267
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.3900699259
Short name T1859
Test name
Test status
Simulation time 5975000270 ps
CPU time 58.95 seconds
Started Jul 23 06:40:21 PM PDT 24
Finished Jul 23 06:41:21 PM PDT 24
Peak memory 206960 kb
Host smart-abb984b3-d945-4625-9842-b5695426c7c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39006
99259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.3900699259
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.4164837344
Short name T2150
Test name
Test status
Simulation time 3554480801 ps
CPU time 32.36 seconds
Started Jul 23 06:40:21 PM PDT 24
Finished Jul 23 06:40:54 PM PDT 24
Peak memory 206916 kb
Host smart-96543a3d-95ad-46b7-8522-e6cb163e16ca
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4164837344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.4164837344
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.997126702
Short name T713
Test name
Test status
Simulation time 248087060 ps
CPU time 0.96 seconds
Started Jul 23 06:40:23 PM PDT 24
Finished Jul 23 06:40:26 PM PDT 24
Peak memory 206756 kb
Host smart-5b0af74a-16cc-4e6e-9fce-3fe4ddd77ed0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=997126702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.997126702
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.338407666
Short name T978
Test name
Test status
Simulation time 198811576 ps
CPU time 0.84 seconds
Started Jul 23 06:40:23 PM PDT 24
Finished Jul 23 06:40:26 PM PDT 24
Peak memory 206752 kb
Host smart-cfd286fa-6386-4221-9f14-a2812c36583a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33840
7666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.338407666
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.2341170588
Short name T2079
Test name
Test status
Simulation time 6009894050 ps
CPU time 42.85 seconds
Started Jul 23 06:40:23 PM PDT 24
Finished Jul 23 06:41:08 PM PDT 24
Peak memory 206960 kb
Host smart-b7d00575-202f-4871-9b85-ce90afe82fac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23411
70588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.2341170588
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.2677231181
Short name T2516
Test name
Test status
Simulation time 4183426926 ps
CPU time 36.94 seconds
Started Jul 23 06:40:26 PM PDT 24
Finished Jul 23 06:41:05 PM PDT 24
Peak memory 206908 kb
Host smart-63a72283-45a8-4f25-9d13-5097689bd4c8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2677231181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.2677231181
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.935099281
Short name T2518
Test name
Test status
Simulation time 232862610 ps
CPU time 0.87 seconds
Started Jul 23 06:40:24 PM PDT 24
Finished Jul 23 06:40:27 PM PDT 24
Peak memory 206696 kb
Host smart-6a25a508-3e86-438b-be1b-3a9009394324
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=935099281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.935099281
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.3935341228
Short name T641
Test name
Test status
Simulation time 149333782 ps
CPU time 0.77 seconds
Started Jul 23 06:40:26 PM PDT 24
Finished Jul 23 06:40:28 PM PDT 24
Peak memory 206764 kb
Host smart-7741af31-54c7-431e-8d65-7ccb71c9d28e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39353
41228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.3935341228
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.540930346
Short name T1966
Test name
Test status
Simulation time 187464433 ps
CPU time 0.88 seconds
Started Jul 23 06:40:25 PM PDT 24
Finished Jul 23 06:40:28 PM PDT 24
Peak memory 206756 kb
Host smart-c5994993-ee49-4b0d-a2dc-082a8ac8ed34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54093
0346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.540930346
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.2442014458
Short name T1812
Test name
Test status
Simulation time 169708851 ps
CPU time 0.81 seconds
Started Jul 23 06:40:24 PM PDT 24
Finished Jul 23 06:40:27 PM PDT 24
Peak memory 206780 kb
Host smart-3af4cdad-454b-4702-bf5f-aea3bff656e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24420
14458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.2442014458
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.1837329284
Short name T385
Test name
Test status
Simulation time 171547047 ps
CPU time 0.78 seconds
Started Jul 23 06:40:21 PM PDT 24
Finished Jul 23 06:40:23 PM PDT 24
Peak memory 206768 kb
Host smart-344346b4-dffe-425d-b6a5-5dbb17caa260
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18373
29284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.1837329284
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.1728454568
Short name T2547
Test name
Test status
Simulation time 149466475 ps
CPU time 0.78 seconds
Started Jul 23 06:40:23 PM PDT 24
Finished Jul 23 06:40:25 PM PDT 24
Peak memory 206696 kb
Host smart-db761db9-ba1a-49c2-879f-1739032abf0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17284
54568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.1728454568
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.478649689
Short name T2277
Test name
Test status
Simulation time 266237268 ps
CPU time 0.95 seconds
Started Jul 23 06:40:23 PM PDT 24
Finished Jul 23 06:40:27 PM PDT 24
Peak memory 206764 kb
Host smart-be9f0f7e-e105-4eea-8276-abcf091b4fe7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=478649689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.478649689
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.4214603500
Short name T2360
Test name
Test status
Simulation time 146907099 ps
CPU time 0.84 seconds
Started Jul 23 06:40:23 PM PDT 24
Finished Jul 23 06:40:26 PM PDT 24
Peak memory 206768 kb
Host smart-4e723258-36d1-4aca-8b44-f6eb0b41ccd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42146
03500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.4214603500
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.323092592
Short name T2283
Test name
Test status
Simulation time 50106833 ps
CPU time 0.67 seconds
Started Jul 23 06:40:24 PM PDT 24
Finished Jul 23 06:40:27 PM PDT 24
Peak memory 206780 kb
Host smart-ca56565c-383d-4b1d-a4b3-d1efe96e8b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32309
2592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.323092592
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.2731475139
Short name T243
Test name
Test status
Simulation time 8805499994 ps
CPU time 20.66 seconds
Started Jul 23 06:40:23 PM PDT 24
Finished Jul 23 06:40:45 PM PDT 24
Peak memory 207008 kb
Host smart-a8b4e891-89e1-4512-98fa-3a39c9327ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27314
75139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.2731475139
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.1305680020
Short name T1444
Test name
Test status
Simulation time 163191685 ps
CPU time 0.82 seconds
Started Jul 23 06:40:23 PM PDT 24
Finished Jul 23 06:40:26 PM PDT 24
Peak memory 206744 kb
Host smart-cff77597-442c-47c3-8bff-f4a34c8e39d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13056
80020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.1305680020
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.3791345002
Short name T292
Test name
Test status
Simulation time 284310121 ps
CPU time 0.9 seconds
Started Jul 23 06:40:22 PM PDT 24
Finished Jul 23 06:40:24 PM PDT 24
Peak memory 206760 kb
Host smart-09d94248-1065-4292-81e5-f02451ff821f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37913
45002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.3791345002
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.1874935220
Short name T671
Test name
Test status
Simulation time 261574123 ps
CPU time 0.96 seconds
Started Jul 23 06:40:24 PM PDT 24
Finished Jul 23 06:40:28 PM PDT 24
Peak memory 206768 kb
Host smart-e643887c-5243-4056-acbc-f269279e233d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18749
35220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.1874935220
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.1806231583
Short name T1818
Test name
Test status
Simulation time 171349554 ps
CPU time 0.81 seconds
Started Jul 23 06:40:23 PM PDT 24
Finished Jul 23 06:40:26 PM PDT 24
Peak memory 206748 kb
Host smart-d2df879c-0edd-4944-85d1-8857cd9fb022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18062
31583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.1806231583
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.179701893
Short name T1770
Test name
Test status
Simulation time 175781512 ps
CPU time 0.8 seconds
Started Jul 23 06:40:23 PM PDT 24
Finished Jul 23 06:40:26 PM PDT 24
Peak memory 206740 kb
Host smart-d454912a-4262-4a7b-98a5-99fb058f59d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17970
1893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.179701893
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.1669816762
Short name T2428
Test name
Test status
Simulation time 151547623 ps
CPU time 0.79 seconds
Started Jul 23 06:40:22 PM PDT 24
Finished Jul 23 06:40:24 PM PDT 24
Peak memory 206744 kb
Host smart-2bccfe02-76b4-4108-b0a4-4e6168fac83d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16698
16762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.1669816762
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.3167850774
Short name T1375
Test name
Test status
Simulation time 256345443 ps
CPU time 0.98 seconds
Started Jul 23 06:40:23 PM PDT 24
Finished Jul 23 06:40:27 PM PDT 24
Peak memory 206744 kb
Host smart-d9aa3492-01ee-4235-a4f9-22d140aa57ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31678
50774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.3167850774
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.2951444834
Short name T1417
Test name
Test status
Simulation time 3028515106 ps
CPU time 20.71 seconds
Started Jul 23 06:40:28 PM PDT 24
Finished Jul 23 06:40:50 PM PDT 24
Peak memory 206904 kb
Host smart-2ee11e01-861b-498b-8e8c-e051b57cfc1e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2951444834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.2951444834
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.2285735656
Short name T2364
Test name
Test status
Simulation time 209537777 ps
CPU time 0.84 seconds
Started Jul 23 06:40:32 PM PDT 24
Finished Jul 23 06:40:35 PM PDT 24
Peak memory 206740 kb
Host smart-a92ff884-2791-45ca-9d86-661e5f08668d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22857
35656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.2285735656
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.2242975002
Short name T429
Test name
Test status
Simulation time 202317767 ps
CPU time 0.85 seconds
Started Jul 23 06:40:29 PM PDT 24
Finished Jul 23 06:40:32 PM PDT 24
Peak memory 206756 kb
Host smart-6ce49537-456a-4dba-aa34-a67bebc046d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22429
75002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.2242975002
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.3150216312
Short name T1720
Test name
Test status
Simulation time 466965799 ps
CPU time 1.34 seconds
Started Jul 23 06:40:30 PM PDT 24
Finished Jul 23 06:40:34 PM PDT 24
Peak memory 206676 kb
Host smart-3bbb2741-b731-4873-839a-caf192daca66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31502
16312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.3150216312
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.1963410346
Short name T791
Test name
Test status
Simulation time 6660383358 ps
CPU time 44.75 seconds
Started Jul 23 06:40:31 PM PDT 24
Finished Jul 23 06:41:19 PM PDT 24
Peak memory 206976 kb
Host smart-cd14ada3-eb10-49a0-9164-9b2c4aa6046f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19634
10346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.1963410346
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.3464395686
Short name T996
Test name
Test status
Simulation time 80050979 ps
CPU time 0.76 seconds
Started Jul 23 06:40:44 PM PDT 24
Finished Jul 23 06:40:46 PM PDT 24
Peak memory 206748 kb
Host smart-922b7bde-4dce-4b0a-a996-f913f691dec8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3464395686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.3464395686
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.3216286238
Short name T2579
Test name
Test status
Simulation time 4016006035 ps
CPU time 5.3 seconds
Started Jul 23 06:40:31 PM PDT 24
Finished Jul 23 06:40:40 PM PDT 24
Peak memory 206836 kb
Host smart-1633ad3b-b565-4f67-8ed9-075525e7c48e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3216286238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.3216286238
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.1001606892
Short name T1292
Test name
Test status
Simulation time 13374967087 ps
CPU time 15.19 seconds
Started Jul 23 06:40:30 PM PDT 24
Finished Jul 23 06:40:47 PM PDT 24
Peak memory 206804 kb
Host smart-176ea0cc-69cc-41b5-83ac-6b5ed47c928a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1001606892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.1001606892
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.3105341262
Short name T2660
Test name
Test status
Simulation time 23390180342 ps
CPU time 24.85 seconds
Started Jul 23 06:40:30 PM PDT 24
Finished Jul 23 06:40:57 PM PDT 24
Peak memory 206888 kb
Host smart-7101efcc-89f1-4f53-a90c-4054efac73cb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3105341262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.3105341262
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.882661078
Short name T967
Test name
Test status
Simulation time 152885504 ps
CPU time 0.86 seconds
Started Jul 23 06:40:30 PM PDT 24
Finished Jul 23 06:40:34 PM PDT 24
Peak memory 206752 kb
Host smart-fb457afa-f28f-4187-9961-07c7995844dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88266
1078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.882661078
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.1468142793
Short name T565
Test name
Test status
Simulation time 189080406 ps
CPU time 0.81 seconds
Started Jul 23 06:40:31 PM PDT 24
Finished Jul 23 06:40:35 PM PDT 24
Peak memory 206324 kb
Host smart-96bbb0f3-e1a8-4999-86f0-6c74ecea25e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14681
42793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.1468142793
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.3059344820
Short name T113
Test name
Test status
Simulation time 523215351 ps
CPU time 1.57 seconds
Started Jul 23 06:40:35 PM PDT 24
Finished Jul 23 06:40:38 PM PDT 24
Peak memory 206848 kb
Host smart-932f9648-0a91-4489-a40c-e3e16a3e5b31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30593
44820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.3059344820
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.4247093239
Short name T547
Test name
Test status
Simulation time 916458932 ps
CPU time 2.15 seconds
Started Jul 23 06:40:29 PM PDT 24
Finished Jul 23 06:40:34 PM PDT 24
Peak memory 206904 kb
Host smart-29dca51e-4437-470f-a716-ad90702c7307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42470
93239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.4247093239
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.1542721974
Short name T1590
Test name
Test status
Simulation time 16991937456 ps
CPU time 30.92 seconds
Started Jul 23 06:40:29 PM PDT 24
Finished Jul 23 06:41:01 PM PDT 24
Peak memory 206896 kb
Host smart-aed3a714-33c5-46f1-81dc-b08dcb89cce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15427
21974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.1542721974
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.2683827687
Short name T2292
Test name
Test status
Simulation time 317707276 ps
CPU time 1.25 seconds
Started Jul 23 06:40:31 PM PDT 24
Finished Jul 23 06:40:35 PM PDT 24
Peak memory 206772 kb
Host smart-1c258dee-1af3-4011-bf93-c68627739ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26838
27687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.2683827687
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.2217523409
Short name T1048
Test name
Test status
Simulation time 147822501 ps
CPU time 0.75 seconds
Started Jul 23 06:40:28 PM PDT 24
Finished Jul 23 06:40:30 PM PDT 24
Peak memory 206728 kb
Host smart-e08c2078-42ff-40b4-82e6-ac62e0845938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22175
23409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.2217523409
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.3020867325
Short name T1020
Test name
Test status
Simulation time 41142703 ps
CPU time 0.65 seconds
Started Jul 23 06:40:30 PM PDT 24
Finished Jul 23 06:40:33 PM PDT 24
Peak memory 206700 kb
Host smart-e7f62927-88c6-4e5d-b533-2ea532f40201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30208
67325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.3020867325
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.1338367011
Short name T1894
Test name
Test status
Simulation time 943746079 ps
CPU time 2.25 seconds
Started Jul 23 06:40:30 PM PDT 24
Finished Jul 23 06:40:35 PM PDT 24
Peak memory 206892 kb
Host smart-981f2f94-744e-4393-8a76-f9fae4c7a003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13383
67011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.1338367011
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.583310350
Short name T1481
Test name
Test status
Simulation time 168410894 ps
CPU time 1.44 seconds
Started Jul 23 06:40:31 PM PDT 24
Finished Jul 23 06:40:36 PM PDT 24
Peak memory 206908 kb
Host smart-e102649b-c59a-4cee-8d99-f5bd52f10b8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58331
0350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.583310350
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.4005649106
Short name T2423
Test name
Test status
Simulation time 217958437 ps
CPU time 0.83 seconds
Started Jul 23 06:40:30 PM PDT 24
Finished Jul 23 06:40:33 PM PDT 24
Peak memory 206752 kb
Host smart-5d00034b-7d4f-4644-a3b1-9a01ff8bf1d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40056
49106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.4005649106
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.396657552
Short name T1322
Test name
Test status
Simulation time 141052442 ps
CPU time 0.76 seconds
Started Jul 23 06:40:31 PM PDT 24
Finished Jul 23 06:40:35 PM PDT 24
Peak memory 206212 kb
Host smart-e2c754e2-539a-435e-8f94-ee725c275ee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39665
7552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.396657552
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.199723904
Short name T2582
Test name
Test status
Simulation time 212331153 ps
CPU time 0.85 seconds
Started Jul 23 06:40:33 PM PDT 24
Finished Jul 23 06:40:36 PM PDT 24
Peak memory 206756 kb
Host smart-26dea784-696f-4c69-abce-58fcf3122f0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19972
3904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.199723904
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_invalid_sync.3443719120
Short name T1399
Test name
Test status
Simulation time 8647909469 ps
CPU time 62.61 seconds
Started Jul 23 06:40:31 PM PDT 24
Finished Jul 23 06:41:36 PM PDT 24
Peak memory 206892 kb
Host smart-c247d3dd-0b9e-477a-b08e-ba317c7f79fb
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3443719120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.3443719120
Directory /workspace/13.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/13.usbdev_iso_retraction.3515310929
Short name T720
Test name
Test status
Simulation time 5341291795 ps
CPU time 47.53 seconds
Started Jul 23 06:40:31 PM PDT 24
Finished Jul 23 06:41:21 PM PDT 24
Peak memory 206896 kb
Host smart-162cd6f3-a42e-45d7-96b6-db954779da93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35153
10929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.3515310929
Directory /workspace/13.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.2446945528
Short name T1740
Test name
Test status
Simulation time 185305926 ps
CPU time 0.82 seconds
Started Jul 23 06:40:27 PM PDT 24
Finished Jul 23 06:40:29 PM PDT 24
Peak memory 206752 kb
Host smart-8760bb4e-3fc2-4b1a-8065-561d3260b4bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24469
45528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.2446945528
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.1390019773
Short name T1187
Test name
Test status
Simulation time 23299497356 ps
CPU time 27.08 seconds
Started Jul 23 06:40:29 PM PDT 24
Finished Jul 23 06:40:59 PM PDT 24
Peak memory 206780 kb
Host smart-3ebfb1c2-9c5c-4d9a-8f98-d2aac7b071b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13900
19773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.1390019773
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.4175511367
Short name T2206
Test name
Test status
Simulation time 3320972390 ps
CPU time 3.7 seconds
Started Jul 23 06:40:30 PM PDT 24
Finished Jul 23 06:40:36 PM PDT 24
Peak memory 206828 kb
Host smart-fd19f7cd-2573-40a2-91c4-c58098d6f14b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41755
11367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.4175511367
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.2008221575
Short name T1145
Test name
Test status
Simulation time 5022765013 ps
CPU time 142.06 seconds
Started Jul 23 06:40:36 PM PDT 24
Finished Jul 23 06:43:01 PM PDT 24
Peak memory 206920 kb
Host smart-a3957aed-c0f1-4923-91cb-fd0bbc668dca
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2008221575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.2008221575
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.3447000408
Short name T1065
Test name
Test status
Simulation time 252303737 ps
CPU time 0.96 seconds
Started Jul 23 06:40:35 PM PDT 24
Finished Jul 23 06:40:38 PM PDT 24
Peak memory 206752 kb
Host smart-5db4d4b3-f46c-4911-9293-75ecc2ac286b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3447000408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.3447000408
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.1319591709
Short name T85
Test name
Test status
Simulation time 258028946 ps
CPU time 0.92 seconds
Started Jul 23 06:40:37 PM PDT 24
Finished Jul 23 06:40:40 PM PDT 24
Peak memory 206764 kb
Host smart-ccadb09f-e418-4199-a0fd-74f4d11cf4ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13195
91709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.1319591709
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.3154282866
Short name T1259
Test name
Test status
Simulation time 3760775416 ps
CPU time 39.57 seconds
Started Jul 23 06:40:36 PM PDT 24
Finished Jul 23 06:41:18 PM PDT 24
Peak memory 206888 kb
Host smart-3797bdd6-16cf-4abf-9e9d-d7c3ae0f4e78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31542
82866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.3154282866
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.1141553075
Short name T1795
Test name
Test status
Simulation time 4338835776 ps
CPU time 115.46 seconds
Started Jul 23 06:40:36 PM PDT 24
Finished Jul 23 06:42:33 PM PDT 24
Peak memory 206880 kb
Host smart-4823f86e-40d9-4977-aa4b-f54d3d800373
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1141553075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.1141553075
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.1166957522
Short name T584
Test name
Test status
Simulation time 166437521 ps
CPU time 0.77 seconds
Started Jul 23 06:40:38 PM PDT 24
Finished Jul 23 06:40:42 PM PDT 24
Peak memory 206756 kb
Host smart-a3c13be7-7b4d-48e5-a859-fafcd046366a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1166957522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.1166957522
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.3235948732
Short name T528
Test name
Test status
Simulation time 200009210 ps
CPU time 0.8 seconds
Started Jul 23 06:40:40 PM PDT 24
Finished Jul 23 06:40:43 PM PDT 24
Peak memory 206752 kb
Host smart-46becc67-5050-489d-9237-e95dc42ad579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32359
48732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.3235948732
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.4076556316
Short name T874
Test name
Test status
Simulation time 210419910 ps
CPU time 0.84 seconds
Started Jul 23 06:40:36 PM PDT 24
Finished Jul 23 06:40:39 PM PDT 24
Peak memory 206764 kb
Host smart-6cb894db-47d0-4ddc-b175-9a601c7c0dc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40765
56316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.4076556316
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.2707775190
Short name T2276
Test name
Test status
Simulation time 161465882 ps
CPU time 0.81 seconds
Started Jul 23 06:40:35 PM PDT 24
Finished Jul 23 06:40:38 PM PDT 24
Peak memory 206724 kb
Host smart-2f8ba489-d864-48a6-89b7-ceecb9035d2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27077
75190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.2707775190
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.56041693
Short name T1853
Test name
Test status
Simulation time 155718216 ps
CPU time 0.78 seconds
Started Jul 23 06:40:35 PM PDT 24
Finished Jul 23 06:40:37 PM PDT 24
Peak memory 206760 kb
Host smart-0dd498f0-9ab9-4cd6-8b72-089804be07f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56041
693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.56041693
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.2416107106
Short name T783
Test name
Test status
Simulation time 145628305 ps
CPU time 0.79 seconds
Started Jul 23 06:40:37 PM PDT 24
Finished Jul 23 06:40:40 PM PDT 24
Peak memory 206712 kb
Host smart-51bc277a-a4d9-4103-ace5-5c0541a69c58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24161
07106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.2416107106
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.3208582594
Short name T835
Test name
Test status
Simulation time 226008273 ps
CPU time 0.97 seconds
Started Jul 23 06:40:36 PM PDT 24
Finished Jul 23 06:40:40 PM PDT 24
Peak memory 206772 kb
Host smart-a0f95dd8-badf-4d0d-a1fe-b263afc27aad
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3208582594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.3208582594
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.3028073208
Short name T711
Test name
Test status
Simulation time 139752694 ps
CPU time 0.8 seconds
Started Jul 23 06:40:41 PM PDT 24
Finished Jul 23 06:40:45 PM PDT 24
Peak memory 206756 kb
Host smart-d4152380-2dba-4bc4-a363-16f81fbdcaf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30280
73208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.3028073208
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.2227521637
Short name T1415
Test name
Test status
Simulation time 21534819149 ps
CPU time 50.09 seconds
Started Jul 23 06:40:41 PM PDT 24
Finished Jul 23 06:41:34 PM PDT 24
Peak memory 206944 kb
Host smart-134e133e-8dcf-4794-8cc4-ee85aa37da79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22275
21637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.2227521637
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.951794629
Short name T2026
Test name
Test status
Simulation time 156441118 ps
CPU time 0.8 seconds
Started Jul 23 06:40:35 PM PDT 24
Finished Jul 23 06:40:38 PM PDT 24
Peak memory 206712 kb
Host smart-f7732d15-a3d5-4045-9007-a2cc0c30e2b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95179
4629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.951794629
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.3352652556
Short name T525
Test name
Test status
Simulation time 311911173 ps
CPU time 0.96 seconds
Started Jul 23 06:40:40 PM PDT 24
Finished Jul 23 06:40:44 PM PDT 24
Peak memory 206756 kb
Host smart-678c72d4-2064-4901-93bc-9c3ff144f4f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33526
52556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.3352652556
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.2409540713
Short name T2601
Test name
Test status
Simulation time 183910813 ps
CPU time 0.83 seconds
Started Jul 23 06:40:40 PM PDT 24
Finished Jul 23 06:40:43 PM PDT 24
Peak memory 206756 kb
Host smart-86fbc789-bed4-4444-b356-f33e2670631f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24095
40713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.2409540713
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.3497778679
Short name T1742
Test name
Test status
Simulation time 185266722 ps
CPU time 0.87 seconds
Started Jul 23 06:40:36 PM PDT 24
Finished Jul 23 06:40:40 PM PDT 24
Peak memory 206776 kb
Host smart-322d2343-8593-411a-9987-06c2c4a68b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34977
78679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.3497778679
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.2612042505
Short name T97
Test name
Test status
Simulation time 169709904 ps
CPU time 0.81 seconds
Started Jul 23 06:40:35 PM PDT 24
Finished Jul 23 06:40:38 PM PDT 24
Peak memory 206740 kb
Host smart-fc160d1c-b4e0-4e0e-93d0-e315e918e0f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26120
42505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.2612042505
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.921516073
Short name T1025
Test name
Test status
Simulation time 150321470 ps
CPU time 0.77 seconds
Started Jul 23 06:40:36 PM PDT 24
Finished Jul 23 06:40:40 PM PDT 24
Peak memory 206748 kb
Host smart-964833b7-02df-4359-b108-3f11d09cfdbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92151
6073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.921516073
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.4027755861
Short name T2732
Test name
Test status
Simulation time 147537917 ps
CPU time 0.81 seconds
Started Jul 23 06:40:37 PM PDT 24
Finished Jul 23 06:40:40 PM PDT 24
Peak memory 206740 kb
Host smart-3875f8c6-bf1b-48cc-9fc8-6e6e6bddfdeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40277
55861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.4027755861
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.3592308659
Short name T330
Test name
Test status
Simulation time 254583113 ps
CPU time 0.93 seconds
Started Jul 23 06:40:36 PM PDT 24
Finished Jul 23 06:40:40 PM PDT 24
Peak memory 206776 kb
Host smart-f2c3a35c-71be-4e2f-830b-4c4415bce891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35923
08659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.3592308659
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.2803924907
Short name T748
Test name
Test status
Simulation time 3706859628 ps
CPU time 35.16 seconds
Started Jul 23 06:40:37 PM PDT 24
Finished Jul 23 06:41:15 PM PDT 24
Peak memory 206952 kb
Host smart-d1f6df47-bc15-4cdd-ac7f-d8024f24c831
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2803924907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.2803924907
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.379713944
Short name T1189
Test name
Test status
Simulation time 192395491 ps
CPU time 0.82 seconds
Started Jul 23 06:40:42 PM PDT 24
Finished Jul 23 06:40:45 PM PDT 24
Peak memory 206756 kb
Host smart-077c0cb4-19f1-49c3-afdf-fbc9772cb684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37971
3944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.379713944
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.4084385312
Short name T1088
Test name
Test status
Simulation time 169965837 ps
CPU time 0.79 seconds
Started Jul 23 06:40:36 PM PDT 24
Finished Jul 23 06:40:39 PM PDT 24
Peak memory 206752 kb
Host smart-b8d845e4-9a6d-495b-8bf5-3d273ecde57a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40843
85312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.4084385312
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.1039390117
Short name T2488
Test name
Test status
Simulation time 920310639 ps
CPU time 1.92 seconds
Started Jul 23 06:40:34 PM PDT 24
Finished Jul 23 06:40:38 PM PDT 24
Peak memory 206832 kb
Host smart-08b14570-a1e0-42c9-81ef-9ad876ce17b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10393
90117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.1039390117
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.2150040899
Short name T1659
Test name
Test status
Simulation time 6683307355 ps
CPU time 48.57 seconds
Started Jul 23 06:40:36 PM PDT 24
Finished Jul 23 06:41:27 PM PDT 24
Peak memory 206968 kb
Host smart-a8f8b76e-2b7b-4c0b-b5af-bb29408465f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21500
40899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.2150040899
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.900494569
Short name T2027
Test name
Test status
Simulation time 61952796 ps
CPU time 0.7 seconds
Started Jul 23 06:40:56 PM PDT 24
Finished Jul 23 06:41:02 PM PDT 24
Peak memory 206744 kb
Host smart-41a45ec7-495b-487d-b605-898e15be5ff8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=900494569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.900494569
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.1521382859
Short name T821
Test name
Test status
Simulation time 4461933140 ps
CPU time 5.51 seconds
Started Jul 23 06:40:40 PM PDT 24
Finished Jul 23 06:40:48 PM PDT 24
Peak memory 206852 kb
Host smart-46d1cea4-a6de-4b96-bcda-c3035e1eb3b7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1521382859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.1521382859
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.1976874265
Short name T199
Test name
Test status
Simulation time 13405252072 ps
CPU time 12.92 seconds
Started Jul 23 06:40:40 PM PDT 24
Finished Jul 23 06:40:56 PM PDT 24
Peak memory 206968 kb
Host smart-fb6edd1b-6b4a-486d-8e06-224d687a82fa
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1976874265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.1976874265
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.1962088134
Short name T688
Test name
Test status
Simulation time 23447456398 ps
CPU time 24.15 seconds
Started Jul 23 06:40:43 PM PDT 24
Finished Jul 23 06:41:09 PM PDT 24
Peak memory 206900 kb
Host smart-85c19671-fc69-4f02-a97c-46eda4a7fd8d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1962088134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.1962088134
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.3659124056
Short name T1732
Test name
Test status
Simulation time 177792212 ps
CPU time 0.85 seconds
Started Jul 23 06:40:42 PM PDT 24
Finished Jul 23 06:40:45 PM PDT 24
Peak memory 206748 kb
Host smart-fb214ffa-01fb-49af-8dd1-4bc293090cb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36591
24056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.3659124056
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.3055777603
Short name T1975
Test name
Test status
Simulation time 144909730 ps
CPU time 0.75 seconds
Started Jul 23 06:40:40 PM PDT 24
Finished Jul 23 06:40:44 PM PDT 24
Peak memory 206748 kb
Host smart-a8dcec41-028e-467e-9fa3-450c96da6035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30557
77603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.3055777603
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.1289435944
Short name T2401
Test name
Test status
Simulation time 495214748 ps
CPU time 1.57 seconds
Started Jul 23 06:40:41 PM PDT 24
Finished Jul 23 06:40:45 PM PDT 24
Peak memory 206768 kb
Host smart-7854dbff-a8c1-46f2-a456-d05334dc9cad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12894
35944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.1289435944
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.4062714668
Short name T110
Test name
Test status
Simulation time 939977994 ps
CPU time 2.25 seconds
Started Jul 23 06:40:42 PM PDT 24
Finished Jul 23 06:40:46 PM PDT 24
Peak memory 207080 kb
Host smart-06ca57da-d1b4-42e8-bd04-ee4603e40253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40627
14668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.4062714668
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.4098019980
Short name T2109
Test name
Test status
Simulation time 20224063124 ps
CPU time 38.79 seconds
Started Jul 23 06:40:43 PM PDT 24
Finished Jul 23 06:41:24 PM PDT 24
Peak memory 206964 kb
Host smart-66b60b94-691f-42ce-b43d-1aeea30284e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40980
19980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.4098019980
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.3359959834
Short name T950
Test name
Test status
Simulation time 344583902 ps
CPU time 1.14 seconds
Started Jul 23 06:40:40 PM PDT 24
Finished Jul 23 06:40:44 PM PDT 24
Peak memory 206712 kb
Host smart-e1647abf-3b95-403e-8e7a-f93e402af45f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33599
59834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.3359959834
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.588789074
Short name T2331
Test name
Test status
Simulation time 192351067 ps
CPU time 0.8 seconds
Started Jul 23 06:40:42 PM PDT 24
Finished Jul 23 06:40:45 PM PDT 24
Peak memory 206776 kb
Host smart-56e7a630-c8ec-409d-b6ae-165c8613a10a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58878
9074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.588789074
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.1619873763
Short name T537
Test name
Test status
Simulation time 47185958 ps
CPU time 0.67 seconds
Started Jul 23 06:40:41 PM PDT 24
Finished Jul 23 06:40:44 PM PDT 24
Peak memory 206744 kb
Host smart-a77e18c9-d7a1-4bf6-8120-0d505d4463e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16198
73763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.1619873763
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.152617631
Short name T1685
Test name
Test status
Simulation time 903941079 ps
CPU time 2.06 seconds
Started Jul 23 06:40:41 PM PDT 24
Finished Jul 23 06:40:46 PM PDT 24
Peak memory 206900 kb
Host smart-2fd97b46-a7a2-42c6-a1c5-d6f02142c4b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15261
7631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.152617631
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.3781545679
Short name T1949
Test name
Test status
Simulation time 150792137 ps
CPU time 1.3 seconds
Started Jul 23 06:40:47 PM PDT 24
Finished Jul 23 06:40:50 PM PDT 24
Peak memory 206896 kb
Host smart-b2bce5b0-9558-431c-97e3-5dd5cbb44f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37815
45679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.3781545679
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.1972578470
Short name T818
Test name
Test status
Simulation time 176815893 ps
CPU time 0.86 seconds
Started Jul 23 06:40:45 PM PDT 24
Finished Jul 23 06:40:47 PM PDT 24
Peak memory 206760 kb
Host smart-d8ad72be-2b8a-4bda-86bb-7d0a064c07d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19725
78470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.1972578470
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.3961799718
Short name T2742
Test name
Test status
Simulation time 155803313 ps
CPU time 0.77 seconds
Started Jul 23 06:40:46 PM PDT 24
Finished Jul 23 06:40:49 PM PDT 24
Peak memory 206756 kb
Host smart-f03533b0-1d38-40fd-bb99-4a42c545616c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39617
99718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.3961799718
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.2113412979
Short name T847
Test name
Test status
Simulation time 235510641 ps
CPU time 0.9 seconds
Started Jul 23 06:40:48 PM PDT 24
Finished Jul 23 06:40:51 PM PDT 24
Peak memory 206740 kb
Host smart-af1b8c03-0e1f-4a13-9950-b12fd6a08a42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21134
12979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.2113412979
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.1690429026
Short name T1603
Test name
Test status
Simulation time 6321248002 ps
CPU time 173.5 seconds
Started Jul 23 06:40:45 PM PDT 24
Finished Jul 23 06:43:39 PM PDT 24
Peak memory 206896 kb
Host smart-bcd7974b-c315-40af-8db9-a3db33837ec0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1690429026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.1690429026
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.3680366897
Short name T361
Test name
Test status
Simulation time 162870868 ps
CPU time 0.84 seconds
Started Jul 23 06:40:50 PM PDT 24
Finished Jul 23 06:40:52 PM PDT 24
Peak memory 206748 kb
Host smart-2648dafa-7cfe-4870-b24a-34c5b1378df2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36803
66897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.3680366897
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.3771448499
Short name T2339
Test name
Test status
Simulation time 23322775810 ps
CPU time 27.88 seconds
Started Jul 23 06:40:50 PM PDT 24
Finished Jul 23 06:41:19 PM PDT 24
Peak memory 206824 kb
Host smart-f6acf6a2-6b77-4456-b5f3-3eb844d18fed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37714
48499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.3771448499
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.706542273
Short name T1942
Test name
Test status
Simulation time 3304711420 ps
CPU time 4.26 seconds
Started Jul 23 06:40:48 PM PDT 24
Finished Jul 23 06:40:54 PM PDT 24
Peak memory 206832 kb
Host smart-f3ec0397-0aeb-4535-8769-1bce286fb9c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70654
2273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.706542273
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.632231811
Short name T2569
Test name
Test status
Simulation time 8175154765 ps
CPU time 57.58 seconds
Started Jul 23 06:40:46 PM PDT 24
Finished Jul 23 06:41:45 PM PDT 24
Peak memory 206948 kb
Host smart-87c930fb-d8da-441f-bd92-982baf89e1c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63223
1811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.632231811
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.1616043476
Short name T1551
Test name
Test status
Simulation time 4289395269 ps
CPU time 120.24 seconds
Started Jul 23 06:40:47 PM PDT 24
Finished Jul 23 06:42:49 PM PDT 24
Peak memory 206912 kb
Host smart-10a2831d-6a91-45df-a3e4-ac7e26112805
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1616043476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.1616043476
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.3261556601
Short name T2333
Test name
Test status
Simulation time 261268646 ps
CPU time 0.99 seconds
Started Jul 23 06:40:46 PM PDT 24
Finished Jul 23 06:40:48 PM PDT 24
Peak memory 206776 kb
Host smart-dd813315-8984-4a39-9dbc-7658f0b20586
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3261556601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.3261556601
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.1474881574
Short name T1244
Test name
Test status
Simulation time 190385472 ps
CPU time 0.86 seconds
Started Jul 23 06:40:47 PM PDT 24
Finished Jul 23 06:40:50 PM PDT 24
Peak memory 206660 kb
Host smart-c966dae6-e157-4265-a85f-474cc0074e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14748
81574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.1474881574
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.1080503298
Short name T2353
Test name
Test status
Simulation time 3870165152 ps
CPU time 105.34 seconds
Started Jul 23 06:40:53 PM PDT 24
Finished Jul 23 06:42:43 PM PDT 24
Peak memory 206908 kb
Host smart-8c9ba746-a62b-407d-a731-cfe4aeeb4587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10805
03298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.1080503298
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.368972669
Short name T2156
Test name
Test status
Simulation time 3291791373 ps
CPU time 88.82 seconds
Started Jul 23 06:40:54 PM PDT 24
Finished Jul 23 06:42:27 PM PDT 24
Peak memory 206912 kb
Host smart-3f5a0608-ae59-4689-98b1-3923dfeafff9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=368972669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.368972669
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.4084508630
Short name T1515
Test name
Test status
Simulation time 171288218 ps
CPU time 0.83 seconds
Started Jul 23 06:40:47 PM PDT 24
Finished Jul 23 06:40:50 PM PDT 24
Peak memory 206772 kb
Host smart-f3cdd640-c669-4645-a282-cf89e9182ad2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4084508630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.4084508630
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.2658398053
Short name T690
Test name
Test status
Simulation time 181527870 ps
CPU time 0.78 seconds
Started Jul 23 06:40:46 PM PDT 24
Finished Jul 23 06:40:48 PM PDT 24
Peak memory 206756 kb
Host smart-d3d0608f-c132-48ca-8c8e-77171818c8ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26583
98053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.2658398053
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.1291637683
Short name T143
Test name
Test status
Simulation time 179145136 ps
CPU time 0.79 seconds
Started Jul 23 06:40:53 PM PDT 24
Finished Jul 23 06:40:56 PM PDT 24
Peak memory 206748 kb
Host smart-848514a7-c918-4519-95d9-3511c3972623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12916
37683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.1291637683
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.2683813169
Short name T559
Test name
Test status
Simulation time 164365563 ps
CPU time 0.84 seconds
Started Jul 23 06:40:48 PM PDT 24
Finished Jul 23 06:40:51 PM PDT 24
Peak memory 206740 kb
Host smart-88c83bf6-27bc-4f17-8dc7-5b0bbaf346bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26838
13169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.2683813169
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.48129061
Short name T953
Test name
Test status
Simulation time 175421579 ps
CPU time 0.76 seconds
Started Jul 23 06:40:45 PM PDT 24
Finished Jul 23 06:40:47 PM PDT 24
Peak memory 206736 kb
Host smart-cbadcefd-b5fd-47c3-aff1-9934db56df24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48129
061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.48129061
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.1257908996
Short name T1277
Test name
Test status
Simulation time 181037192 ps
CPU time 0.78 seconds
Started Jul 23 06:40:46 PM PDT 24
Finished Jul 23 06:40:47 PM PDT 24
Peak memory 206740 kb
Host smart-b900753a-4af4-4c5e-a10b-a566989509ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12579
08996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.1257908996
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.3895070885
Short name T1708
Test name
Test status
Simulation time 160673021 ps
CPU time 0.79 seconds
Started Jul 23 06:40:53 PM PDT 24
Finished Jul 23 06:40:58 PM PDT 24
Peak memory 206748 kb
Host smart-bdb01d6f-55e1-4fd0-a9f2-b5b7e141e3fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38950
70885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.3895070885
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.124493920
Short name T624
Test name
Test status
Simulation time 253520612 ps
CPU time 0.93 seconds
Started Jul 23 06:40:53 PM PDT 24
Finished Jul 23 06:40:57 PM PDT 24
Peak memory 206756 kb
Host smart-f7764f40-d191-474d-958c-74725acfa20c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=124493920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.124493920
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.4145268133
Short name T2607
Test name
Test status
Simulation time 146758169 ps
CPU time 0.77 seconds
Started Jul 23 06:40:47 PM PDT 24
Finished Jul 23 06:40:49 PM PDT 24
Peak memory 206784 kb
Host smart-fbd5338a-0d52-42a6-94fb-8540e2f7abc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41452
68133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.4145268133
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.2023052167
Short name T2495
Test name
Test status
Simulation time 73741098 ps
CPU time 0.67 seconds
Started Jul 23 06:40:50 PM PDT 24
Finished Jul 23 06:40:52 PM PDT 24
Peak memory 206752 kb
Host smart-db765121-ed6d-42e7-b3ad-3f02fe0c6298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20230
52167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.2023052167
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.4203717607
Short name T2562
Test name
Test status
Simulation time 16724510371 ps
CPU time 37.73 seconds
Started Jul 23 06:40:47 PM PDT 24
Finished Jul 23 06:41:27 PM PDT 24
Peak memory 206996 kb
Host smart-ebf77161-03ef-4ec0-aae5-706b573e8411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42037
17607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.4203717607
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.2016164932
Short name T2515
Test name
Test status
Simulation time 180271436 ps
CPU time 0.88 seconds
Started Jul 23 06:40:48 PM PDT 24
Finished Jul 23 06:40:51 PM PDT 24
Peak memory 206744 kb
Host smart-336e3920-f2f7-40d5-8dba-aaf8a506d69a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20161
64932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.2016164932
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.1511373204
Short name T804
Test name
Test status
Simulation time 162326812 ps
CPU time 0.84 seconds
Started Jul 23 06:40:47 PM PDT 24
Finished Jul 23 06:40:49 PM PDT 24
Peak memory 206712 kb
Host smart-380310ab-1436-4344-ab03-fa8448b9ddba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15113
73204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.1511373204
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.4289449118
Short name T1110
Test name
Test status
Simulation time 223368617 ps
CPU time 0.92 seconds
Started Jul 23 06:40:53 PM PDT 24
Finished Jul 23 06:40:58 PM PDT 24
Peak memory 206648 kb
Host smart-2e28ba22-1f1c-497b-b50b-a729badae139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42894
49118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.4289449118
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.1892082347
Short name T340
Test name
Test status
Simulation time 210861972 ps
CPU time 0.92 seconds
Started Jul 23 06:40:53 PM PDT 24
Finished Jul 23 06:40:58 PM PDT 24
Peak memory 206760 kb
Host smart-4dc98e5d-5394-44cf-8e96-0f252252078a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18920
82347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.1892082347
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.1426350885
Short name T73
Test name
Test status
Simulation time 211822537 ps
CPU time 0.82 seconds
Started Jul 23 06:40:53 PM PDT 24
Finished Jul 23 06:40:58 PM PDT 24
Peak memory 206740 kb
Host smart-c0a65c04-e3cc-4c45-946b-211fb4c601e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14263
50885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.1426350885
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.1390187639
Short name T2663
Test name
Test status
Simulation time 195964579 ps
CPU time 0.84 seconds
Started Jul 23 06:40:53 PM PDT 24
Finished Jul 23 06:40:58 PM PDT 24
Peak memory 206756 kb
Host smart-f3918114-03ad-432a-8eb8-e8fa0bb5c609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13901
87639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.1390187639
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.1731673803
Short name T446
Test name
Test status
Simulation time 174004450 ps
CPU time 0.85 seconds
Started Jul 23 06:40:54 PM PDT 24
Finished Jul 23 06:40:59 PM PDT 24
Peak memory 206696 kb
Host smart-e7a45b1d-af44-4268-a959-3640ccaf32fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17316
73803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.1731673803
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.347671348
Short name T1318
Test name
Test status
Simulation time 247556362 ps
CPU time 0.96 seconds
Started Jul 23 06:40:54 PM PDT 24
Finished Jul 23 06:40:59 PM PDT 24
Peak memory 206764 kb
Host smart-ee4b4c1d-0e1c-4ed5-b8f9-5cbf02389ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34767
1348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.347671348
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.3234165848
Short name T2417
Test name
Test status
Simulation time 3833164411 ps
CPU time 104.23 seconds
Started Jul 23 06:40:52 PM PDT 24
Finished Jul 23 06:42:37 PM PDT 24
Peak memory 206880 kb
Host smart-610ceec8-c936-48b9-a479-b4b05da1b6c2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3234165848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.3234165848
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.97675574
Short name T1625
Test name
Test status
Simulation time 188079828 ps
CPU time 0.86 seconds
Started Jul 23 06:40:56 PM PDT 24
Finished Jul 23 06:41:03 PM PDT 24
Peak memory 206764 kb
Host smart-140c89b8-7a56-4f08-b890-5ea8e23dafe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97675
574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.97675574
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.1610210826
Short name T2021
Test name
Test status
Simulation time 166000989 ps
CPU time 0.83 seconds
Started Jul 23 06:40:53 PM PDT 24
Finished Jul 23 06:40:58 PM PDT 24
Peak memory 206716 kb
Host smart-e1be9c98-db5a-42a1-80a2-208f244cf35b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16102
10826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.1610210826
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.2699501375
Short name T1352
Test name
Test status
Simulation time 699248291 ps
CPU time 1.87 seconds
Started Jul 23 06:40:55 PM PDT 24
Finished Jul 23 06:41:02 PM PDT 24
Peak memory 206868 kb
Host smart-d18ab021-aa3e-4631-918f-8720133384c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26995
01375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.2699501375
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.938476780
Short name T509
Test name
Test status
Simulation time 5291016634 ps
CPU time 150.11 seconds
Started Jul 23 06:40:55 PM PDT 24
Finished Jul 23 06:43:29 PM PDT 24
Peak memory 206928 kb
Host smart-122ee6ad-d8a2-4c7b-9036-ad5880837e0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93847
6780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.938476780
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.1286527067
Short name T181
Test name
Test status
Simulation time 45103834 ps
CPU time 0.74 seconds
Started Jul 23 06:41:00 PM PDT 24
Finished Jul 23 06:41:06 PM PDT 24
Peak memory 206760 kb
Host smart-29b84bb6-b637-42d1-97ca-88eeb7b3cba3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1286527067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.1286527067
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.1800727794
Short name T1191
Test name
Test status
Simulation time 3776893909 ps
CPU time 4.83 seconds
Started Jul 23 06:40:55 PM PDT 24
Finished Jul 23 06:41:05 PM PDT 24
Peak memory 206796 kb
Host smart-a75eb0c7-c519-4b3c-be98-d8b4f808b71a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1800727794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.1800727794
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.312754525
Short name T411
Test name
Test status
Simulation time 13456224624 ps
CPU time 14.66 seconds
Started Jul 23 06:40:52 PM PDT 24
Finished Jul 23 06:41:09 PM PDT 24
Peak memory 206952 kb
Host smart-5a909a03-d763-41d2-8933-2cf68aa322ab
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=312754525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.312754525
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.3185189303
Short name T16
Test name
Test status
Simulation time 23392662649 ps
CPU time 23.78 seconds
Started Jul 23 06:40:55 PM PDT 24
Finished Jul 23 06:41:24 PM PDT 24
Peak memory 206804 kb
Host smart-18bbd202-9be0-4a58-9678-39965e10784e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3185189303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.3185189303
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.2435030496
Short name T2064
Test name
Test status
Simulation time 190766837 ps
CPU time 0.86 seconds
Started Jul 23 06:40:52 PM PDT 24
Finished Jul 23 06:40:54 PM PDT 24
Peak memory 206744 kb
Host smart-a47e961d-019d-436b-a8df-cda3eade8f37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24350
30496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.2435030496
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.1099046484
Short name T63
Test name
Test status
Simulation time 151140577 ps
CPU time 0.77 seconds
Started Jul 23 06:40:53 PM PDT 24
Finished Jul 23 06:40:57 PM PDT 24
Peak memory 206740 kb
Host smart-4b032b93-2bd4-473a-b47d-9dd37d147291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10990
46484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.1099046484
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.1896036578
Short name T1447
Test name
Test status
Simulation time 352334430 ps
CPU time 1.27 seconds
Started Jul 23 06:40:55 PM PDT 24
Finished Jul 23 06:41:00 PM PDT 24
Peak memory 206768 kb
Host smart-d3b41ba1-23a6-41e6-9efb-f58899860ced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18960
36578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.1896036578
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.3199576053
Short name T1548
Test name
Test status
Simulation time 321300692 ps
CPU time 1.07 seconds
Started Jul 23 06:40:55 PM PDT 24
Finished Jul 23 06:41:01 PM PDT 24
Peak memory 206752 kb
Host smart-8e7a3552-98f1-4083-ba0d-bad3facb19ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31995
76053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.3199576053
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.1405253476
Short name T169
Test name
Test status
Simulation time 7835993105 ps
CPU time 16.05 seconds
Started Jul 23 06:40:53 PM PDT 24
Finished Jul 23 06:41:13 PM PDT 24
Peak memory 207140 kb
Host smart-a3d13f86-fc8e-4cf5-89a4-9e3d9cbf2c40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14052
53476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.1405253476
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.2935648691
Short name T1367
Test name
Test status
Simulation time 456024454 ps
CPU time 1.48 seconds
Started Jul 23 06:40:54 PM PDT 24
Finished Jul 23 06:41:01 PM PDT 24
Peak memory 206776 kb
Host smart-007af1ae-8775-4ad3-aebf-fad9a53e93a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29356
48691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.2935648691
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.3809101845
Short name T1435
Test name
Test status
Simulation time 162246843 ps
CPU time 0.75 seconds
Started Jul 23 06:40:57 PM PDT 24
Finished Jul 23 06:41:03 PM PDT 24
Peak memory 206752 kb
Host smart-012af9b8-3d52-4393-8a00-4b85434d30b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38091
01845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.3809101845
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.721722197
Short name T433
Test name
Test status
Simulation time 61166819 ps
CPU time 0.7 seconds
Started Jul 23 06:40:57 PM PDT 24
Finished Jul 23 06:41:03 PM PDT 24
Peak memory 206660 kb
Host smart-3b82f761-88aa-42f8-8acb-e20f2c62e677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72172
2197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.721722197
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.2071288198
Short name T2202
Test name
Test status
Simulation time 982087164 ps
CPU time 2.14 seconds
Started Jul 23 06:40:54 PM PDT 24
Finished Jul 23 06:41:01 PM PDT 24
Peak memory 206840 kb
Host smart-6ff62aff-65a2-42a2-93d2-aa59bfd07eac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20712
88198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.2071288198
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.3791517757
Short name T648
Test name
Test status
Simulation time 240366580 ps
CPU time 2 seconds
Started Jul 23 06:40:52 PM PDT 24
Finished Jul 23 06:40:56 PM PDT 24
Peak memory 206860 kb
Host smart-1d5e1a6a-edcc-4529-baee-36d118aa123c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37915
17757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.3791517757
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.2779574806
Short name T1376
Test name
Test status
Simulation time 151464436 ps
CPU time 0.83 seconds
Started Jul 23 06:40:53 PM PDT 24
Finished Jul 23 06:40:57 PM PDT 24
Peak memory 206740 kb
Host smart-ec6fdc3b-127f-4b52-97c2-121380f8dc62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27795
74806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.2779574806
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.2704129375
Short name T1072
Test name
Test status
Simulation time 182208446 ps
CPU time 0.81 seconds
Started Jul 23 06:40:54 PM PDT 24
Finished Jul 23 06:40:59 PM PDT 24
Peak memory 206760 kb
Host smart-d9142ecd-f124-4c9b-948f-8aacd2ffc6cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27041
29375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.2704129375
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.820061843
Short name T2537
Test name
Test status
Simulation time 221965055 ps
CPU time 0.96 seconds
Started Jul 23 06:40:52 PM PDT 24
Finished Jul 23 06:40:54 PM PDT 24
Peak memory 206760 kb
Host smart-cd6cafcc-1b7b-400d-8d2e-9c7a3f1aeb2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82006
1843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.820061843
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_iso_retraction.2461001004
Short name T1646
Test name
Test status
Simulation time 9919057523 ps
CPU time 93.27 seconds
Started Jul 23 06:40:52 PM PDT 24
Finished Jul 23 06:42:27 PM PDT 24
Peak memory 206952 kb
Host smart-78c2a0d4-d38b-47b8-8231-f15808c91cc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24610
01004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.2461001004
Directory /workspace/15.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.2869078026
Short name T2457
Test name
Test status
Simulation time 195004705 ps
CPU time 0.84 seconds
Started Jul 23 06:40:55 PM PDT 24
Finished Jul 23 06:41:01 PM PDT 24
Peak memory 206688 kb
Host smart-928f09f6-d689-4f5c-8a29-16ad9cfe90d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28690
78026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.2869078026
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.3207012706
Short name T2039
Test name
Test status
Simulation time 23307322684 ps
CPU time 28.99 seconds
Started Jul 23 06:40:55 PM PDT 24
Finished Jul 23 06:41:29 PM PDT 24
Peak memory 206808 kb
Host smart-08604c4c-4c6d-4b6d-91df-7a4dbc7fe984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32070
12706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.3207012706
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.2127880692
Short name T2022
Test name
Test status
Simulation time 3263807293 ps
CPU time 4.45 seconds
Started Jul 23 06:40:54 PM PDT 24
Finished Jul 23 06:41:02 PM PDT 24
Peak memory 206740 kb
Host smart-f8869a59-a1e7-40f6-a821-b51229346e1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21278
80692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.2127880692
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.1590039604
Short name T2494
Test name
Test status
Simulation time 6009365249 ps
CPU time 40.7 seconds
Started Jul 23 06:40:54 PM PDT 24
Finished Jul 23 06:41:39 PM PDT 24
Peak memory 206956 kb
Host smart-0f759139-1284-410c-8057-189b27a61927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15900
39604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.1590039604
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.2407963132
Short name T2447
Test name
Test status
Simulation time 4565820747 ps
CPU time 124.6 seconds
Started Jul 23 06:40:54 PM PDT 24
Finished Jul 23 06:43:04 PM PDT 24
Peak memory 206916 kb
Host smart-2dc2addd-6d72-40a3-a1fd-84ea41f5088c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2407963132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.2407963132
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.3627350222
Short name T1449
Test name
Test status
Simulation time 247435510 ps
CPU time 0.95 seconds
Started Jul 23 06:40:52 PM PDT 24
Finished Jul 23 06:40:55 PM PDT 24
Peak memory 206744 kb
Host smart-c364d7df-76e8-4d3a-b5c9-c8f718d2723f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3627350222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.3627350222
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.1390661021
Short name T2175
Test name
Test status
Simulation time 215112909 ps
CPU time 0.89 seconds
Started Jul 23 06:40:53 PM PDT 24
Finished Jul 23 06:40:57 PM PDT 24
Peak memory 206752 kb
Host smart-951ce64f-a698-4cce-873f-935373f4deb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13906
61021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.1390661021
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.2799287748
Short name T2215
Test name
Test status
Simulation time 6704053801 ps
CPU time 63.69 seconds
Started Jul 23 06:40:58 PM PDT 24
Finished Jul 23 06:42:07 PM PDT 24
Peak memory 206888 kb
Host smart-2c72be25-f749-494a-a907-127c8f82fc71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27992
87748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.2799287748
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.1265022967
Short name T1778
Test name
Test status
Simulation time 7267401051 ps
CPU time 68.43 seconds
Started Jul 23 06:40:59 PM PDT 24
Finished Jul 23 06:42:13 PM PDT 24
Peak memory 206960 kb
Host smart-474fdc62-d69f-4078-b3b6-7fa3c911cc58
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1265022967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.1265022967
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.3913868009
Short name T1059
Test name
Test status
Simulation time 168189826 ps
CPU time 0.82 seconds
Started Jul 23 06:41:00 PM PDT 24
Finished Jul 23 06:41:07 PM PDT 24
Peak memory 206756 kb
Host smart-b4d37001-3da6-411a-9f30-31e486d6d3f1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3913868009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.3913868009
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.3172415840
Short name T295
Test name
Test status
Simulation time 144603193 ps
CPU time 0.77 seconds
Started Jul 23 06:41:02 PM PDT 24
Finished Jul 23 06:41:09 PM PDT 24
Peak memory 206780 kb
Host smart-edd5ccca-e4ca-459f-b968-432910a4535c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31724
15840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.3172415840
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.3653460214
Short name T1944
Test name
Test status
Simulation time 181737343 ps
CPU time 0.83 seconds
Started Jul 23 06:40:59 PM PDT 24
Finished Jul 23 06:41:06 PM PDT 24
Peak memory 206724 kb
Host smart-db7042ce-78a9-42fc-b398-a2d620493872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36534
60214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.3653460214
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.1261584441
Short name T1301
Test name
Test status
Simulation time 242462534 ps
CPU time 0.94 seconds
Started Jul 23 06:41:00 PM PDT 24
Finished Jul 23 06:41:07 PM PDT 24
Peak memory 206744 kb
Host smart-815c95cb-db9c-4864-9598-f30f1cb5164b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12615
84441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.1261584441
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.1046106170
Short name T356
Test name
Test status
Simulation time 194079502 ps
CPU time 0.8 seconds
Started Jul 23 06:40:59 PM PDT 24
Finished Jul 23 06:41:06 PM PDT 24
Peak memory 206764 kb
Host smart-e2a18684-6e3f-4cc5-8784-1f76689b7257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10461
06170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.1046106170
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.4052270929
Short name T2706
Test name
Test status
Simulation time 163771634 ps
CPU time 0.84 seconds
Started Jul 23 06:41:01 PM PDT 24
Finished Jul 23 06:41:08 PM PDT 24
Peak memory 206640 kb
Host smart-29ddc03c-6c63-46ed-8373-e122cf8bd44e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40522
70929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.4052270929
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.4258589988
Short name T1581
Test name
Test status
Simulation time 149461401 ps
CPU time 0.77 seconds
Started Jul 23 06:41:00 PM PDT 24
Finished Jul 23 06:41:06 PM PDT 24
Peak memory 206764 kb
Host smart-fd71246f-7825-42bb-8849-3bac279135b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42585
89988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.4258589988
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.2402583482
Short name T836
Test name
Test status
Simulation time 205521383 ps
CPU time 0.88 seconds
Started Jul 23 06:41:01 PM PDT 24
Finished Jul 23 06:41:08 PM PDT 24
Peak memory 206672 kb
Host smart-7687bd30-88d8-4674-a495-84bfaba203df
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2402583482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.2402583482
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.2647802457
Short name T646
Test name
Test status
Simulation time 143078539 ps
CPU time 0.73 seconds
Started Jul 23 06:41:01 PM PDT 24
Finished Jul 23 06:41:08 PM PDT 24
Peak memory 206552 kb
Host smart-c6ef4079-8179-4de3-8ec6-b298dc82cd22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26478
02457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.2647802457
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.4001934502
Short name T1525
Test name
Test status
Simulation time 29716881 ps
CPU time 0.67 seconds
Started Jul 23 06:40:59 PM PDT 24
Finished Jul 23 06:41:06 PM PDT 24
Peak memory 206924 kb
Host smart-70893709-827d-48cf-9ab9-c2465496c2ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40019
34502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.4001934502
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.2110961800
Short name T1914
Test name
Test status
Simulation time 7843405002 ps
CPU time 15.77 seconds
Started Jul 23 06:40:59 PM PDT 24
Finished Jul 23 06:41:21 PM PDT 24
Peak memory 215108 kb
Host smart-55d341b8-6d8d-46e6-9a5c-9522d3cd3039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21109
61800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.2110961800
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.558849896
Short name T755
Test name
Test status
Simulation time 242668267 ps
CPU time 0.97 seconds
Started Jul 23 06:41:02 PM PDT 24
Finished Jul 23 06:41:09 PM PDT 24
Peak memory 206772 kb
Host smart-343a8417-bc97-4c3b-83f9-3107e0223b1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55884
9896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.558849896
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.2152621839
Short name T1378
Test name
Test status
Simulation time 239756356 ps
CPU time 0.96 seconds
Started Jul 23 06:41:01 PM PDT 24
Finished Jul 23 06:41:08 PM PDT 24
Peak memory 206728 kb
Host smart-5617b473-76b0-4dbd-97cb-ec05fc0c35b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21526
21839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.2152621839
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.3508692982
Short name T444
Test name
Test status
Simulation time 262613231 ps
CPU time 0.93 seconds
Started Jul 23 06:41:00 PM PDT 24
Finished Jul 23 06:41:07 PM PDT 24
Peak memory 206752 kb
Host smart-dae3d869-0d83-464c-bd1b-d8e96ff75205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35086
92982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.3508692982
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.2957512057
Short name T760
Test name
Test status
Simulation time 169796867 ps
CPU time 0.85 seconds
Started Jul 23 06:41:01 PM PDT 24
Finished Jul 23 06:41:09 PM PDT 24
Peak memory 206736 kb
Host smart-757f237e-e4f2-4dc8-a3f1-c1625998446b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29575
12057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.2957512057
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.872884546
Short name T1266
Test name
Test status
Simulation time 145827573 ps
CPU time 0.76 seconds
Started Jul 23 06:41:00 PM PDT 24
Finished Jul 23 06:41:06 PM PDT 24
Peak memory 206756 kb
Host smart-2ebaa096-8c51-4214-a84a-a39aafa89559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87288
4546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.872884546
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.369996927
Short name T2067
Test name
Test status
Simulation time 161388284 ps
CPU time 0.81 seconds
Started Jul 23 06:41:01 PM PDT 24
Finished Jul 23 06:41:08 PM PDT 24
Peak memory 206536 kb
Host smart-eaee0f16-6fd6-453f-94bb-73ea901684b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36999
6927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.369996927
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.1659833693
Short name T2461
Test name
Test status
Simulation time 152846960 ps
CPU time 0.84 seconds
Started Jul 23 06:40:59 PM PDT 24
Finished Jul 23 06:41:06 PM PDT 24
Peak memory 206760 kb
Host smart-c36b060b-4cad-49f5-9642-42e5e69b441a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16598
33693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.1659833693
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.2521560723
Short name T607
Test name
Test status
Simulation time 196767103 ps
CPU time 0.85 seconds
Started Jul 23 06:40:59 PM PDT 24
Finished Jul 23 06:41:06 PM PDT 24
Peak memory 206764 kb
Host smart-a9c40cc9-5f02-4742-9e89-7bbf310aefeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25215
60723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.2521560723
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.3872828723
Short name T1232
Test name
Test status
Simulation time 2929471847 ps
CPU time 20.43 seconds
Started Jul 23 06:40:59 PM PDT 24
Finished Jul 23 06:41:25 PM PDT 24
Peak memory 206932 kb
Host smart-cb6b20da-6387-4f49-856f-2b7066947633
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3872828723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.3872828723
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.3933736481
Short name T989
Test name
Test status
Simulation time 175325095 ps
CPU time 0.86 seconds
Started Jul 23 06:41:00 PM PDT 24
Finished Jul 23 06:41:07 PM PDT 24
Peak memory 206740 kb
Host smart-c4f59744-d1c6-4feb-bddb-0aba87388e9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39337
36481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.3933736481
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.162730388
Short name T1706
Test name
Test status
Simulation time 269109596 ps
CPU time 0.9 seconds
Started Jul 23 06:41:01 PM PDT 24
Finished Jul 23 06:41:08 PM PDT 24
Peak memory 206676 kb
Host smart-02885f79-058b-4714-8111-ae2ce039683b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16273
0388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.162730388
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.525439187
Short name T2226
Test name
Test status
Simulation time 545162357 ps
CPU time 1.35 seconds
Started Jul 23 06:41:01 PM PDT 24
Finished Jul 23 06:41:09 PM PDT 24
Peak memory 206752 kb
Host smart-f89db7ee-2702-4cea-8137-bd77d32b3537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52543
9187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.525439187
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.1268246261
Short name T1272
Test name
Test status
Simulation time 7293693980 ps
CPU time 53.24 seconds
Started Jul 23 06:40:59 PM PDT 24
Finished Jul 23 06:41:58 PM PDT 24
Peak memory 206980 kb
Host smart-b0066b70-1f5c-4215-ac13-444cd17247a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12682
46261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.1268246261
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.3958796581
Short name T964
Test name
Test status
Simulation time 37580183 ps
CPU time 0.68 seconds
Started Jul 23 06:41:16 PM PDT 24
Finished Jul 23 06:41:25 PM PDT 24
Peak memory 206768 kb
Host smart-bcc2e3a4-ae70-4b95-8358-4fc466428d37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3958796581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.3958796581
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.1139041639
Short name T2655
Test name
Test status
Simulation time 3580959973 ps
CPU time 4.59 seconds
Started Jul 23 06:41:01 PM PDT 24
Finished Jul 23 06:41:13 PM PDT 24
Peak memory 206840 kb
Host smart-2d03114f-56a1-456d-83fa-d98ace550f68
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1139041639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.1139041639
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.1796770842
Short name T456
Test name
Test status
Simulation time 13388636224 ps
CPU time 14.55 seconds
Started Jul 23 06:40:59 PM PDT 24
Finished Jul 23 06:41:19 PM PDT 24
Peak memory 206824 kb
Host smart-5d9a7276-a4d7-4b3a-a6b0-baa49fd43dee
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1796770842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.1796770842
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.2087029087
Short name T2173
Test name
Test status
Simulation time 23371751557 ps
CPU time 23.47 seconds
Started Jul 23 06:41:00 PM PDT 24
Finished Jul 23 06:41:30 PM PDT 24
Peak memory 206816 kb
Host smart-7350f22e-e10d-47be-ae0c-b3dde49d0d29
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2087029087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.2087029087
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.1907869380
Short name T2475
Test name
Test status
Simulation time 184145622 ps
CPU time 0.8 seconds
Started Jul 23 06:40:59 PM PDT 24
Finished Jul 23 06:41:06 PM PDT 24
Peak memory 206772 kb
Host smart-a8caa400-cf4d-4f1b-87e8-3ca71b5d72e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19078
69380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.1907869380
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.389237698
Short name T2508
Test name
Test status
Simulation time 158937066 ps
CPU time 0.8 seconds
Started Jul 23 06:41:00 PM PDT 24
Finished Jul 23 06:41:07 PM PDT 24
Peak memory 206776 kb
Host smart-c7a05586-5d33-44f3-b34b-2605b7eb459f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38923
7698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.389237698
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.2596832668
Short name T2068
Test name
Test status
Simulation time 459279585 ps
CPU time 1.4 seconds
Started Jul 23 06:41:01 PM PDT 24
Finished Jul 23 06:41:09 PM PDT 24
Peak memory 206736 kb
Host smart-1dcaf2d7-2c13-475a-9deb-96249c379da4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25968
32668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.2596832668
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.3747443219
Short name T952
Test name
Test status
Simulation time 897887188 ps
CPU time 2.06 seconds
Started Jul 23 06:41:01 PM PDT 24
Finished Jul 23 06:41:10 PM PDT 24
Peak memory 206836 kb
Host smart-35bf57c9-38af-4e92-a3eb-d542f0884a2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37474
43219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.3747443219
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.2192327748
Short name T1860
Test name
Test status
Simulation time 13018805097 ps
CPU time 24.86 seconds
Started Jul 23 06:41:08 PM PDT 24
Finished Jul 23 06:41:40 PM PDT 24
Peak memory 206780 kb
Host smart-9f8e9ab1-4690-410b-8d07-df9f68ce02e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21923
27748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.2192327748
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.3466308172
Short name T2484
Test name
Test status
Simulation time 497543059 ps
CPU time 1.38 seconds
Started Jul 23 06:41:06 PM PDT 24
Finished Jul 23 06:41:15 PM PDT 24
Peak memory 206760 kb
Host smart-be1c29bf-c1f2-40ba-b971-6ed4b91b526c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34663
08172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.3466308172
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.3172380010
Short name T829
Test name
Test status
Simulation time 138372992 ps
CPU time 0.83 seconds
Started Jul 23 06:41:09 PM PDT 24
Finished Jul 23 06:41:17 PM PDT 24
Peak memory 206772 kb
Host smart-059c351d-09b5-469a-8eac-e027fbfe36b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31723
80010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.3172380010
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.1906887465
Short name T2627
Test name
Test status
Simulation time 41382681 ps
CPU time 0.67 seconds
Started Jul 23 06:41:08 PM PDT 24
Finished Jul 23 06:41:16 PM PDT 24
Peak memory 206700 kb
Host smart-55243a09-280b-4fb1-836e-5e2d4e8af999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19068
87465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.1906887465
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.2230889831
Short name T1979
Test name
Test status
Simulation time 983797578 ps
CPU time 2.22 seconds
Started Jul 23 06:41:06 PM PDT 24
Finished Jul 23 06:41:15 PM PDT 24
Peak memory 206932 kb
Host smart-1ecc6f6a-e236-46ac-b654-242d283deedc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22308
89831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.2230889831
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.2894996
Short name T2407
Test name
Test status
Simulation time 331902709 ps
CPU time 1.71 seconds
Started Jul 23 06:41:10 PM PDT 24
Finished Jul 23 06:41:20 PM PDT 24
Peak memory 206912 kb
Host smart-d428f816-f2c5-4837-a689-9b5789e4154a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28949
96 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.2894996
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.1514929935
Short name T834
Test name
Test status
Simulation time 172362573 ps
CPU time 0.79 seconds
Started Jul 23 06:41:07 PM PDT 24
Finished Jul 23 06:41:14 PM PDT 24
Peak memory 206748 kb
Host smart-37ed4c00-c1fa-4201-906f-9649895205ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15149
29935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.1514929935
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.1640973806
Short name T1607
Test name
Test status
Simulation time 140737885 ps
CPU time 0.79 seconds
Started Jul 23 06:41:11 PM PDT 24
Finished Jul 23 06:41:20 PM PDT 24
Peak memory 206768 kb
Host smart-e9043a59-6380-40bf-9c10-3d8c77c7dab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16409
73806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.1640973806
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.3509455720
Short name T1522
Test name
Test status
Simulation time 174999924 ps
CPU time 0.82 seconds
Started Jul 23 06:41:06 PM PDT 24
Finished Jul 23 06:41:13 PM PDT 24
Peak memory 206696 kb
Host smart-89300014-9cca-44e3-a36c-5c64a4354a70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35094
55720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.3509455720
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.4191961873
Short name T2662
Test name
Test status
Simulation time 8142810676 ps
CPU time 75.36 seconds
Started Jul 23 06:41:06 PM PDT 24
Finished Jul 23 06:42:28 PM PDT 24
Peak memory 206964 kb
Host smart-00489e70-9a69-459a-988f-4e9c1ec29e64
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4191961873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.4191961873
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/16.usbdev_iso_retraction.3483809640
Short name T1037
Test name
Test status
Simulation time 7727398551 ps
CPU time 24.73 seconds
Started Jul 23 06:41:10 PM PDT 24
Finished Jul 23 06:41:42 PM PDT 24
Peak memory 206856 kb
Host smart-0ab480bf-84bb-4057-8ff3-18554d0ca88f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34838
09640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.3483809640
Directory /workspace/16.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.498137017
Short name T2127
Test name
Test status
Simulation time 163623504 ps
CPU time 0.83 seconds
Started Jul 23 06:41:06 PM PDT 24
Finished Jul 23 06:41:13 PM PDT 24
Peak memory 206748 kb
Host smart-2fc7ad70-d3df-4350-b292-ce029b8250d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49813
7017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.498137017
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.27006154
Short name T1939
Test name
Test status
Simulation time 23364455016 ps
CPU time 22.67 seconds
Started Jul 23 06:41:05 PM PDT 24
Finished Jul 23 06:41:34 PM PDT 24
Peak memory 206740 kb
Host smart-22089f81-0cc3-4bc7-bbb9-3511f7674c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27006
154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.27006154
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.1085074531
Short name T1151
Test name
Test status
Simulation time 3286714943 ps
CPU time 3.58 seconds
Started Jul 23 06:41:10 PM PDT 24
Finished Jul 23 06:41:21 PM PDT 24
Peak memory 206748 kb
Host smart-d668c5a7-17b1-4d02-879f-7e9b43bfe719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10850
74531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.1085074531
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.583238871
Short name T578
Test name
Test status
Simulation time 6819525571 ps
CPU time 63.64 seconds
Started Jul 23 06:41:10 PM PDT 24
Finished Jul 23 06:42:22 PM PDT 24
Peak memory 207000 kb
Host smart-e98928a9-60f4-4b6b-b157-5d6e6fe4d02b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58323
8871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.583238871
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.50744664
Short name T2295
Test name
Test status
Simulation time 6946794417 ps
CPU time 189.65 seconds
Started Jul 23 06:41:08 PM PDT 24
Finished Jul 23 06:44:24 PM PDT 24
Peak memory 206912 kb
Host smart-569a79c2-5ec6-4768-9db6-5635facc2632
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=50744664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.50744664
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.4220291583
Short name T2221
Test name
Test status
Simulation time 233174718 ps
CPU time 0.89 seconds
Started Jul 23 06:41:05 PM PDT 24
Finished Jul 23 06:41:13 PM PDT 24
Peak memory 206768 kb
Host smart-893871d1-b7ef-4526-840f-7df7133ccca1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4220291583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.4220291583
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.1772332895
Short name T2199
Test name
Test status
Simulation time 221579439 ps
CPU time 0.94 seconds
Started Jul 23 06:41:05 PM PDT 24
Finished Jul 23 06:41:13 PM PDT 24
Peak memory 206768 kb
Host smart-ee7e8b80-7c16-4fcb-806b-674891b8831b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17723
32895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.1772332895
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.461168905
Short name T946
Test name
Test status
Simulation time 3864193301 ps
CPU time 26.43 seconds
Started Jul 23 06:41:05 PM PDT 24
Finished Jul 23 06:41:38 PM PDT 24
Peak memory 206956 kb
Host smart-2060f3e0-311d-406e-b68a-83dfc3a61b22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46116
8905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.461168905
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.3717504220
Short name T418
Test name
Test status
Simulation time 2890641123 ps
CPU time 75.88 seconds
Started Jul 23 06:41:04 PM PDT 24
Finished Jul 23 06:42:27 PM PDT 24
Peak memory 206904 kb
Host smart-d94b8b34-f88d-4769-8156-6c047b0c03a5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3717504220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.3717504220
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.2628995924
Short name T1177
Test name
Test status
Simulation time 170976838 ps
CPU time 0.77 seconds
Started Jul 23 06:41:06 PM PDT 24
Finished Jul 23 06:41:14 PM PDT 24
Peak memory 206760 kb
Host smart-b821fa06-16c1-4687-ab8c-b83d7af2808a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2628995924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.2628995924
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.190692774
Short name T317
Test name
Test status
Simulation time 175908798 ps
CPU time 0.79 seconds
Started Jul 23 06:41:05 PM PDT 24
Finished Jul 23 06:41:13 PM PDT 24
Peak memory 206760 kb
Host smart-218bf010-3fe4-4d55-9393-b780e2a0a1d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19069
2774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.190692774
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.4086243661
Short name T144
Test name
Test status
Simulation time 243810830 ps
CPU time 0.88 seconds
Started Jul 23 06:41:06 PM PDT 24
Finished Jul 23 06:41:14 PM PDT 24
Peak memory 206756 kb
Host smart-59e1c3bc-e09e-4e4b-8b71-b959ac6fa0c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40862
43661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.4086243661
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.1051737893
Short name T1294
Test name
Test status
Simulation time 180815589 ps
CPU time 0.83 seconds
Started Jul 23 06:41:06 PM PDT 24
Finished Jul 23 06:41:14 PM PDT 24
Peak memory 206724 kb
Host smart-973724d3-af92-4ee2-8a0c-fc097520e6c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10517
37893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.1051737893
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.1308243804
Short name T1982
Test name
Test status
Simulation time 154343627 ps
CPU time 0.79 seconds
Started Jul 23 06:41:10 PM PDT 24
Finished Jul 23 06:41:18 PM PDT 24
Peak memory 206780 kb
Host smart-8ba62144-365d-4cf3-a941-a39ce938eadb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13082
43804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.1308243804
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.3374783288
Short name T1385
Test name
Test status
Simulation time 185323468 ps
CPU time 0.79 seconds
Started Jul 23 06:41:06 PM PDT 24
Finished Jul 23 06:41:14 PM PDT 24
Peak memory 206756 kb
Host smart-88868c76-e0cd-4369-bb00-7a0c0f0d14d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33747
83288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.3374783288
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.2471042055
Short name T703
Test name
Test status
Simulation time 158814969 ps
CPU time 0.79 seconds
Started Jul 23 06:41:06 PM PDT 24
Finished Jul 23 06:41:14 PM PDT 24
Peak memory 206752 kb
Host smart-d05924d6-ceb6-4d53-8a3b-66b2ca1dd332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24710
42055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.2471042055
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.3042203054
Short name T1502
Test name
Test status
Simulation time 211751609 ps
CPU time 0.96 seconds
Started Jul 23 06:41:06 PM PDT 24
Finished Jul 23 06:41:14 PM PDT 24
Peak memory 206672 kb
Host smart-93b86f96-37d2-4114-b09a-223c4c9bc9f6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3042203054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.3042203054
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.372362105
Short name T1062
Test name
Test status
Simulation time 167708970 ps
CPU time 0.81 seconds
Started Jul 23 06:41:13 PM PDT 24
Finished Jul 23 06:41:22 PM PDT 24
Peak memory 206740 kb
Host smart-39f81e23-3d09-43a9-a0ba-bde7a4fee358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37236
2105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.372362105
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.3047575108
Short name T1085
Test name
Test status
Simulation time 40211959 ps
CPU time 0.66 seconds
Started Jul 23 06:41:10 PM PDT 24
Finished Jul 23 06:41:18 PM PDT 24
Peak memory 206724 kb
Host smart-8c760953-77dc-4266-975a-a3530de7c194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30475
75108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.3047575108
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.3802732153
Short name T2610
Test name
Test status
Simulation time 13250635007 ps
CPU time 29.63 seconds
Started Jul 23 06:41:10 PM PDT 24
Finished Jul 23 06:41:49 PM PDT 24
Peak memory 206968 kb
Host smart-b5ad8ac2-c3a2-4c1e-b2b9-a072c113629a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38027
32153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.3802732153
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.1927322267
Short name T1623
Test name
Test status
Simulation time 148878146 ps
CPU time 0.79 seconds
Started Jul 23 06:41:11 PM PDT 24
Finished Jul 23 06:41:21 PM PDT 24
Peak memory 206756 kb
Host smart-f6e5c00b-0ce6-404f-95b5-39427f4fcbfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19273
22267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.1927322267
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.382843364
Short name T2087
Test name
Test status
Simulation time 220418154 ps
CPU time 0.91 seconds
Started Jul 23 06:41:10 PM PDT 24
Finished Jul 23 06:41:18 PM PDT 24
Peak memory 206748 kb
Host smart-17610032-e78f-41ee-bc61-e70dbc111e4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38284
3364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.382843364
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.3369712258
Short name T2480
Test name
Test status
Simulation time 234125453 ps
CPU time 0.88 seconds
Started Jul 23 06:41:11 PM PDT 24
Finished Jul 23 06:41:21 PM PDT 24
Peak memory 206744 kb
Host smart-83286656-9d12-4e99-926c-6a9c69cf2dcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33697
12258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.3369712258
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.3601942871
Short name T1968
Test name
Test status
Simulation time 151151084 ps
CPU time 0.79 seconds
Started Jul 23 06:41:11 PM PDT 24
Finished Jul 23 06:41:20 PM PDT 24
Peak memory 206712 kb
Host smart-04a2c751-b52a-4070-baca-f1846af6040c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36019
42871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.3601942871
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.42655064
Short name T1573
Test name
Test status
Simulation time 159222048 ps
CPU time 0.76 seconds
Started Jul 23 06:41:15 PM PDT 24
Finished Jul 23 06:41:24 PM PDT 24
Peak memory 206780 kb
Host smart-64b303e2-e5ef-4b5e-a629-651f0a0b343a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42655
064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.42655064
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.1888876769
Short name T941
Test name
Test status
Simulation time 165196371 ps
CPU time 0.81 seconds
Started Jul 23 06:41:17 PM PDT 24
Finished Jul 23 06:41:27 PM PDT 24
Peak memory 206748 kb
Host smart-b4839830-c25b-4cd7-af99-104694179b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18888
76769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.1888876769
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.3767012038
Short name T1082
Test name
Test status
Simulation time 148359423 ps
CPU time 0.84 seconds
Started Jul 23 06:41:11 PM PDT 24
Finished Jul 23 06:41:20 PM PDT 24
Peak memory 206712 kb
Host smart-36557b0c-b83d-4534-b462-480ce2d443b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37670
12038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.3767012038
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.2152077855
Short name T630
Test name
Test status
Simulation time 213550509 ps
CPU time 0.9 seconds
Started Jul 23 06:41:13 PM PDT 24
Finished Jul 23 06:41:22 PM PDT 24
Peak memory 206732 kb
Host smart-edde580a-e510-49ce-8cd7-1163c2249f60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21520
77855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.2152077855
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.4279967472
Short name T2239
Test name
Test status
Simulation time 3802213214 ps
CPU time 35.98 seconds
Started Jul 23 06:41:10 PM PDT 24
Finished Jul 23 06:41:53 PM PDT 24
Peak memory 206904 kb
Host smart-9e42e459-e6e9-4b59-93e7-a04c073b3eac
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4279967472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.4279967472
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.3733945123
Short name T1455
Test name
Test status
Simulation time 266542897 ps
CPU time 0.89 seconds
Started Jul 23 06:41:16 PM PDT 24
Finished Jul 23 06:41:25 PM PDT 24
Peak memory 206764 kb
Host smart-acc7ae9d-8103-4dfe-8b68-67bd0555bdc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37339
45123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.3733945123
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.1696322605
Short name T808
Test name
Test status
Simulation time 269306955 ps
CPU time 0.89 seconds
Started Jul 23 06:41:12 PM PDT 24
Finished Jul 23 06:41:21 PM PDT 24
Peak memory 206768 kb
Host smart-4a4e5199-8dec-4dbe-b8ed-b69ca08622d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16963
22605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.1696322605
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.2380277568
Short name T841
Test name
Test status
Simulation time 746717041 ps
CPU time 1.69 seconds
Started Jul 23 06:41:12 PM PDT 24
Finished Jul 23 06:41:22 PM PDT 24
Peak memory 206784 kb
Host smart-dc923fa8-956f-4421-9ff5-7215d3e73930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23802
77568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.2380277568
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.2908430888
Short name T1806
Test name
Test status
Simulation time 6662859672 ps
CPU time 188.29 seconds
Started Jul 23 06:41:17 PM PDT 24
Finished Jul 23 06:44:34 PM PDT 24
Peak memory 206936 kb
Host smart-890c0e4f-1c84-4cb1-8289-008529c4dd85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29084
30888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.2908430888
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.236399274
Short name T180
Test name
Test status
Simulation time 56363912 ps
CPU time 0.7 seconds
Started Jul 23 06:41:23 PM PDT 24
Finished Jul 23 06:41:29 PM PDT 24
Peak memory 206900 kb
Host smart-ef1ebb10-3285-48a5-885f-036ce451a8ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=236399274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.236399274
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.794118347
Short name T1404
Test name
Test status
Simulation time 4209328470 ps
CPU time 4.94 seconds
Started Jul 23 06:41:14 PM PDT 24
Finished Jul 23 06:41:27 PM PDT 24
Peak memory 206796 kb
Host smart-2b63ce37-2ca9-4240-9733-7ad363e9c1d6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=794118347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.794118347
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.3811684649
Short name T2629
Test name
Test status
Simulation time 13385161064 ps
CPU time 12.19 seconds
Started Jul 23 06:41:11 PM PDT 24
Finished Jul 23 06:41:32 PM PDT 24
Peak memory 206824 kb
Host smart-8cfdb45d-6c9d-441e-a806-6e7a51e81840
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3811684649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.3811684649
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.2384520989
Short name T1033
Test name
Test status
Simulation time 23380784068 ps
CPU time 22.25 seconds
Started Jul 23 06:41:11 PM PDT 24
Finished Jul 23 06:41:42 PM PDT 24
Peak memory 206976 kb
Host smart-9264fc88-cae1-4bec-bc85-2454c4535167
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2384520989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.2384520989
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.1344962131
Short name T432
Test name
Test status
Simulation time 197784878 ps
CPU time 0.83 seconds
Started Jul 23 06:41:11 PM PDT 24
Finished Jul 23 06:41:21 PM PDT 24
Peak memory 206740 kb
Host smart-043a34da-44d9-45e7-86d5-b1cd7567242f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13449
62131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.1344962131
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.548904106
Short name T2486
Test name
Test status
Simulation time 160386746 ps
CPU time 0.82 seconds
Started Jul 23 06:41:10 PM PDT 24
Finished Jul 23 06:41:18 PM PDT 24
Peak memory 206760 kb
Host smart-c69604e5-817c-42c2-9d4b-ee222123c875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54890
4106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.548904106
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.1688198241
Short name T508
Test name
Test status
Simulation time 506901610 ps
CPU time 1.53 seconds
Started Jul 23 06:41:16 PM PDT 24
Finished Jul 23 06:41:25 PM PDT 24
Peak memory 206764 kb
Host smart-e2cca0d8-92cd-4fdd-a1f9-15fa6a7947d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16881
98241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.1688198241
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_device_address.3648721168
Short name T1955
Test name
Test status
Simulation time 19769241481 ps
CPU time 42.5 seconds
Started Jul 23 06:41:15 PM PDT 24
Finished Jul 23 06:42:06 PM PDT 24
Peak memory 206940 kb
Host smart-e2d0a209-5634-43e6-ab91-51cb6afc30e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36487
21168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.3648721168
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.3320215410
Short name T1201
Test name
Test status
Simulation time 371279806 ps
CPU time 1.23 seconds
Started Jul 23 06:41:12 PM PDT 24
Finished Jul 23 06:41:21 PM PDT 24
Peak memory 206772 kb
Host smart-19f2f05a-dc29-4893-bef5-0b7b6683d2aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33202
15410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.3320215410
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.591782347
Short name T591
Test name
Test status
Simulation time 136193144 ps
CPU time 0.79 seconds
Started Jul 23 06:41:15 PM PDT 24
Finished Jul 23 06:41:24 PM PDT 24
Peak memory 206732 kb
Host smart-5c189597-b30c-4832-b9c2-4efa7d006dcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59178
2347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.591782347
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.3524276356
Short name T2212
Test name
Test status
Simulation time 127141744 ps
CPU time 0.72 seconds
Started Jul 23 06:41:15 PM PDT 24
Finished Jul 23 06:41:24 PM PDT 24
Peak memory 206724 kb
Host smart-365fe5a2-ac36-4e6c-8c94-b598353999d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35242
76356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.3524276356
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.3761529283
Short name T1114
Test name
Test status
Simulation time 916377026 ps
CPU time 2.18 seconds
Started Jul 23 06:41:13 PM PDT 24
Finished Jul 23 06:41:23 PM PDT 24
Peak memory 206832 kb
Host smart-8a6c0d26-17be-4223-87d3-bdcc6ab30145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37615
29283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.3761529283
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.3227403515
Short name T1688
Test name
Test status
Simulation time 339348871 ps
CPU time 1.67 seconds
Started Jul 23 06:41:10 PM PDT 24
Finished Jul 23 06:41:20 PM PDT 24
Peak memory 206908 kb
Host smart-2f9076bf-06eb-495e-adc2-8436d1ba944d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32274
03515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.3227403515
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.737337348
Short name T1078
Test name
Test status
Simulation time 255560046 ps
CPU time 0.9 seconds
Started Jul 23 06:41:16 PM PDT 24
Finished Jul 23 06:41:25 PM PDT 24
Peak memory 206732 kb
Host smart-33cd5337-c3ea-433a-8395-93f7ec9832dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73733
7348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.737337348
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.821000288
Short name T1098
Test name
Test status
Simulation time 185911754 ps
CPU time 0.79 seconds
Started Jul 23 06:41:15 PM PDT 24
Finished Jul 23 06:41:24 PM PDT 24
Peak memory 206760 kb
Host smart-9d00a48f-61a7-493c-a46c-5b7ee3113152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82100
0288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.821000288
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.324316820
Short name T814
Test name
Test status
Simulation time 196446764 ps
CPU time 0.88 seconds
Started Jul 23 06:41:18 PM PDT 24
Finished Jul 23 06:41:27 PM PDT 24
Peak memory 206744 kb
Host smart-da48a435-2d0e-4bdc-a084-0902abae714e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32431
6820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.324316820
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.3752988489
Short name T106
Test name
Test status
Simulation time 5344942523 ps
CPU time 143.51 seconds
Started Jul 23 06:41:17 PM PDT 24
Finished Jul 23 06:43:48 PM PDT 24
Peak memory 206916 kb
Host smart-7ba83f87-f56b-42a1-9e0a-4c17626436ad
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3752988489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.3752988489
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.868502601
Short name T479
Test name
Test status
Simulation time 224029741 ps
CPU time 0.89 seconds
Started Jul 23 06:41:18 PM PDT 24
Finished Jul 23 06:41:27 PM PDT 24
Peak memory 206724 kb
Host smart-9dbc618f-f169-499d-896e-2ed127da687f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86850
2601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.868502601
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.4142262044
Short name T302
Test name
Test status
Simulation time 23330238456 ps
CPU time 21.56 seconds
Started Jul 23 06:41:18 PM PDT 24
Finished Jul 23 06:41:47 PM PDT 24
Peak memory 206708 kb
Host smart-9836b65f-33f9-4d8e-a6e2-fec0346b3352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41422
62044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.4142262044
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.1030246810
Short name T1304
Test name
Test status
Simulation time 3366015145 ps
CPU time 3.61 seconds
Started Jul 23 06:41:16 PM PDT 24
Finished Jul 23 06:41:28 PM PDT 24
Peak memory 206828 kb
Host smart-451944c9-f73a-46f6-8cda-7643b1359f79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10302
46810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.1030246810
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.322258368
Short name T898
Test name
Test status
Simulation time 9660614466 ps
CPU time 90.43 seconds
Started Jul 23 06:41:16 PM PDT 24
Finished Jul 23 06:42:55 PM PDT 24
Peak memory 206880 kb
Host smart-588189f9-7b93-4dea-97a7-8ddcfbac321c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32225
8368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.322258368
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.556398766
Short name T1004
Test name
Test status
Simulation time 5043938675 ps
CPU time 49.54 seconds
Started Jul 23 06:41:17 PM PDT 24
Finished Jul 23 06:42:15 PM PDT 24
Peak memory 206960 kb
Host smart-fd2cbf6d-0342-43a6-85af-9b938ac3fe21
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=556398766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.556398766
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.1087310595
Short name T1743
Test name
Test status
Simulation time 283503832 ps
CPU time 0.96 seconds
Started Jul 23 06:41:18 PM PDT 24
Finished Jul 23 06:41:27 PM PDT 24
Peak memory 206720 kb
Host smart-02512762-8976-440f-a934-8cace52f41d0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1087310595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.1087310595
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.963791752
Short name T1251
Test name
Test status
Simulation time 189999481 ps
CPU time 0.88 seconds
Started Jul 23 06:41:18 PM PDT 24
Finished Jul 23 06:41:27 PM PDT 24
Peak memory 206684 kb
Host smart-b3b247ed-f37f-4ac4-bfb0-d7afb76d01c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96379
1752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.963791752
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.55584813
Short name T1353
Test name
Test status
Simulation time 4881868940 ps
CPU time 47.5 seconds
Started Jul 23 06:41:18 PM PDT 24
Finished Jul 23 06:42:13 PM PDT 24
Peak memory 206996 kb
Host smart-502c7800-be66-4c6c-9b11-b56a6d6b444c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55584
813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.55584813
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.1184418762
Short name T2038
Test name
Test status
Simulation time 4521864176 ps
CPU time 36.6 seconds
Started Jul 23 06:41:16 PM PDT 24
Finished Jul 23 06:42:01 PM PDT 24
Peak memory 206840 kb
Host smart-5d2b2924-27ba-431f-99cc-32244430a858
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1184418762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.1184418762
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.706241518
Short name T1498
Test name
Test status
Simulation time 162062076 ps
CPU time 0.8 seconds
Started Jul 23 06:41:18 PM PDT 24
Finished Jul 23 06:41:27 PM PDT 24
Peak memory 206748 kb
Host smart-c0c6f6d7-6801-4a9a-a86c-d777d12d15d3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=706241518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.706241518
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.3699435492
Short name T2225
Test name
Test status
Simulation time 138118967 ps
CPU time 0.77 seconds
Started Jul 23 06:41:17 PM PDT 24
Finished Jul 23 06:41:26 PM PDT 24
Peak memory 206768 kb
Host smart-59649b15-44b8-4fbc-81a4-025fc1af682f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36994
35492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.3699435492
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.3072646289
Short name T692
Test name
Test status
Simulation time 208097443 ps
CPU time 0.84 seconds
Started Jul 23 06:41:16 PM PDT 24
Finished Jul 23 06:41:25 PM PDT 24
Peak memory 206720 kb
Host smart-4083b965-2d58-4223-aed3-adb79122f5dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30726
46289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.3072646289
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.2286824667
Short name T1334
Test name
Test status
Simulation time 178184131 ps
CPU time 0.79 seconds
Started Jul 23 06:41:16 PM PDT 24
Finished Jul 23 06:41:24 PM PDT 24
Peak memory 206756 kb
Host smart-30852901-4a2f-4d55-bbdb-0f725f667fa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22868
24667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.2286824667
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.3696133057
Short name T1923
Test name
Test status
Simulation time 190877467 ps
CPU time 0.79 seconds
Started Jul 23 06:41:17 PM PDT 24
Finished Jul 23 06:41:26 PM PDT 24
Peak memory 206740 kb
Host smart-a9ac082c-6611-4fa0-87ac-b1f8598d256c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36961
33057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.3696133057
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.3096700631
Short name T544
Test name
Test status
Simulation time 151147785 ps
CPU time 0.81 seconds
Started Jul 23 06:41:16 PM PDT 24
Finished Jul 23 06:41:25 PM PDT 24
Peak memory 206768 kb
Host smart-75c0466d-f613-4fe0-a689-a8ab935c3fc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30967
00631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.3096700631
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.3510772782
Short name T1876
Test name
Test status
Simulation time 267007002 ps
CPU time 1.07 seconds
Started Jul 23 06:41:16 PM PDT 24
Finished Jul 23 06:41:25 PM PDT 24
Peak memory 206732 kb
Host smart-911775a2-1c82-4140-90c3-8ad25aa77fef
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3510772782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.3510772782
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.1236353214
Short name T1002
Test name
Test status
Simulation time 152268185 ps
CPU time 0.75 seconds
Started Jul 23 06:41:24 PM PDT 24
Finished Jul 23 06:41:30 PM PDT 24
Peak memory 206756 kb
Host smart-5b3720e5-375e-40f1-bd66-c5cc45d5edad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12363
53214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.1236353214
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.3997723234
Short name T1956
Test name
Test status
Simulation time 29219921 ps
CPU time 0.64 seconds
Started Jul 23 06:41:21 PM PDT 24
Finished Jul 23 06:41:28 PM PDT 24
Peak memory 206768 kb
Host smart-6aa26a38-90fa-415f-9720-7e39ba65fa12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39977
23234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.3997723234
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.55737216
Short name T210
Test name
Test status
Simulation time 16337275415 ps
CPU time 39.79 seconds
Started Jul 23 06:41:27 PM PDT 24
Finished Jul 23 06:42:12 PM PDT 24
Peak memory 215112 kb
Host smart-1697eb26-4dd7-4716-990e-60596208b502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55737
216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.55737216
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.469844527
Short name T639
Test name
Test status
Simulation time 175539727 ps
CPU time 0.81 seconds
Started Jul 23 06:41:24 PM PDT 24
Finished Jul 23 06:41:30 PM PDT 24
Peak memory 206772 kb
Host smart-8e6748d6-90d3-4dcf-8edc-153a237e10c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46984
4527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.469844527
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.401292833
Short name T1214
Test name
Test status
Simulation time 183435800 ps
CPU time 0.89 seconds
Started Jul 23 06:41:24 PM PDT 24
Finished Jul 23 06:41:30 PM PDT 24
Peak memory 206504 kb
Host smart-f1d4109d-c15c-4d4e-8812-923a4c6d01e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40129
2833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.401292833
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.3500705201
Short name T1837
Test name
Test status
Simulation time 222633456 ps
CPU time 0.91 seconds
Started Jul 23 06:41:23 PM PDT 24
Finished Jul 23 06:41:30 PM PDT 24
Peak memory 206768 kb
Host smart-ab695066-037f-42a6-a16e-7bff183bdf8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35007
05201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.3500705201
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.1432753966
Short name T475
Test name
Test status
Simulation time 216525789 ps
CPU time 0.86 seconds
Started Jul 23 06:41:25 PM PDT 24
Finished Jul 23 06:41:32 PM PDT 24
Peak memory 206756 kb
Host smart-68ab8854-801a-4457-970c-f0017feb9807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14327
53966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.1432753966
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.2047779223
Short name T1162
Test name
Test status
Simulation time 146858991 ps
CPU time 0.79 seconds
Started Jul 23 06:41:23 PM PDT 24
Finished Jul 23 06:41:29 PM PDT 24
Peak memory 206764 kb
Host smart-1b41e69d-720b-484f-b9a5-5c24fda9c7ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20477
79223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.2047779223
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.40590133
Short name T596
Test name
Test status
Simulation time 153867063 ps
CPU time 0.86 seconds
Started Jul 23 06:41:23 PM PDT 24
Finished Jul 23 06:41:29 PM PDT 24
Peak memory 206740 kb
Host smart-5a2434a4-4a37-46ff-a296-4b726a7e318c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40590
133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.40590133
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.2912047941
Short name T785
Test name
Test status
Simulation time 167945016 ps
CPU time 0.83 seconds
Started Jul 23 06:41:25 PM PDT 24
Finished Jul 23 06:41:31 PM PDT 24
Peak memory 206712 kb
Host smart-86142025-428a-4081-9f99-95c59fa6e170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29120
47941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.2912047941
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.2239454109
Short name T2527
Test name
Test status
Simulation time 261135215 ps
CPU time 1.04 seconds
Started Jul 23 06:41:23 PM PDT 24
Finished Jul 23 06:41:29 PM PDT 24
Peak memory 206752 kb
Host smart-9d5f13ce-f7ae-4054-84f0-e0b5626d98e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22394
54109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.2239454109
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.178073564
Short name T1081
Test name
Test status
Simulation time 6986801412 ps
CPU time 188.05 seconds
Started Jul 23 06:41:23 PM PDT 24
Finished Jul 23 06:44:37 PM PDT 24
Peak memory 206852 kb
Host smart-72439b74-3e84-402f-af21-4f21630aa04f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=178073564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.178073564
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.608230529
Short name T1174
Test name
Test status
Simulation time 160207020 ps
CPU time 0.9 seconds
Started Jul 23 06:41:24 PM PDT 24
Finished Jul 23 06:41:30 PM PDT 24
Peak memory 206768 kb
Host smart-df1cf43d-8864-46bd-b995-87778d1c83bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60823
0529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.608230529
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.834295555
Short name T2130
Test name
Test status
Simulation time 184382292 ps
CPU time 0.8 seconds
Started Jul 23 06:41:23 PM PDT 24
Finished Jul 23 06:41:30 PM PDT 24
Peak memory 206668 kb
Host smart-5d686cbf-31c6-4788-9282-939dd7d181d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83429
5555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.834295555
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.4229278280
Short name T884
Test name
Test status
Simulation time 591931834 ps
CPU time 1.46 seconds
Started Jul 23 06:41:24 PM PDT 24
Finished Jul 23 06:41:31 PM PDT 24
Peak memory 206752 kb
Host smart-4b8c86c2-ab40-4772-9e9f-636c8541a555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42292
78280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.4229278280
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.2150161942
Short name T1183
Test name
Test status
Simulation time 3767063312 ps
CPU time 35.61 seconds
Started Jul 23 06:41:24 PM PDT 24
Finished Jul 23 06:42:05 PM PDT 24
Peak memory 206680 kb
Host smart-e1bfa919-8c0c-4317-a86f-5a8e61ea1c5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21501
61942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.2150161942
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.145818820
Short name T365
Test name
Test status
Simulation time 36161561 ps
CPU time 0.7 seconds
Started Jul 23 06:41:35 PM PDT 24
Finished Jul 23 06:41:40 PM PDT 24
Peak memory 206740 kb
Host smart-d43ec546-900b-4b22-8330-4a329292c19d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=145818820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.145818820
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.1958883940
Short name T1354
Test name
Test status
Simulation time 3923617104 ps
CPU time 4.79 seconds
Started Jul 23 06:41:25 PM PDT 24
Finished Jul 23 06:41:35 PM PDT 24
Peak memory 206776 kb
Host smart-a5f81a5c-e147-4cc6-bf6c-09c0b3b79db1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1958883940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.1958883940
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.4070464936
Short name T2517
Test name
Test status
Simulation time 23313407934 ps
CPU time 25.47 seconds
Started Jul 23 06:41:26 PM PDT 24
Finished Jul 23 06:41:56 PM PDT 24
Peak memory 206928 kb
Host smart-9b094564-9b75-4c43-8f49-945766d695f8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4070464936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.4070464936
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.1287755648
Short name T1261
Test name
Test status
Simulation time 234338309 ps
CPU time 0.94 seconds
Started Jul 23 06:41:24 PM PDT 24
Finished Jul 23 06:41:31 PM PDT 24
Peak memory 206780 kb
Host smart-93886064-cca0-4918-ad34-a05b613845ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12877
55648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.1287755648
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.1594309208
Short name T798
Test name
Test status
Simulation time 145003353 ps
CPU time 0.77 seconds
Started Jul 23 06:41:23 PM PDT 24
Finished Jul 23 06:41:29 PM PDT 24
Peak memory 206776 kb
Host smart-d5d89901-8a27-4ff8-93b2-108585e370f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15943
09208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.1594309208
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.601905746
Short name T1007
Test name
Test status
Simulation time 432345004 ps
CPU time 1.44 seconds
Started Jul 23 06:41:24 PM PDT 24
Finished Jul 23 06:41:31 PM PDT 24
Peak memory 206768 kb
Host smart-b7d92e66-1710-4adb-9994-c740288e1ab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60190
5746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.601905746
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.2967605551
Short name T2741
Test name
Test status
Simulation time 1212966550 ps
CPU time 2.65 seconds
Started Jul 23 06:41:26 PM PDT 24
Finished Jul 23 06:41:34 PM PDT 24
Peak memory 206876 kb
Host smart-65d415c5-6901-4e34-bbb5-b083567c9bd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29676
05551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.2967605551
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.365923490
Short name T1704
Test name
Test status
Simulation time 8931946953 ps
CPU time 17.3 seconds
Started Jul 23 06:41:21 PM PDT 24
Finished Jul 23 06:41:45 PM PDT 24
Peak memory 206940 kb
Host smart-2116f510-7cbc-40ac-8590-7aa9e9099f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36592
3490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.365923490
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.423516547
Short name T833
Test name
Test status
Simulation time 470122841 ps
CPU time 1.48 seconds
Started Jul 23 06:41:30 PM PDT 24
Finished Jul 23 06:41:37 PM PDT 24
Peak memory 206756 kb
Host smart-983574b6-b89e-445c-b15d-c57063bdfd22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42351
6547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.423516547
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.2926268957
Short name T491
Test name
Test status
Simulation time 159014270 ps
CPU time 0.8 seconds
Started Jul 23 06:41:27 PM PDT 24
Finished Jul 23 06:41:33 PM PDT 24
Peak memory 206740 kb
Host smart-f60be978-b606-47e5-8e00-8f809d5da122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29262
68957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.2926268957
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.99416685
Short name T1032
Test name
Test status
Simulation time 61671561 ps
CPU time 0.7 seconds
Started Jul 23 06:41:27 PM PDT 24
Finished Jul 23 06:41:33 PM PDT 24
Peak memory 206708 kb
Host smart-6df183da-a748-4a8c-b46a-1c423957a8a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99416
685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.99416685
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.3753895627
Short name T1230
Test name
Test status
Simulation time 961759579 ps
CPU time 2.31 seconds
Started Jul 23 06:41:30 PM PDT 24
Finished Jul 23 06:41:37 PM PDT 24
Peak memory 206884 kb
Host smart-8c056b2a-4e4f-4f99-8e75-6a6e2ebf80df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37538
95627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.3753895627
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.3967941365
Short name T314
Test name
Test status
Simulation time 356296473 ps
CPU time 2.46 seconds
Started Jul 23 06:41:29 PM PDT 24
Finished Jul 23 06:41:37 PM PDT 24
Peak memory 206904 kb
Host smart-6c7fdaac-d1af-408b-927e-676104abc1a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39679
41365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.3967941365
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.4117432005
Short name T2685
Test name
Test status
Simulation time 163549001 ps
CPU time 0.88 seconds
Started Jul 23 06:41:27 PM PDT 24
Finished Jul 23 06:41:33 PM PDT 24
Peak memory 206772 kb
Host smart-a3486dc6-396b-42c1-8a96-870ce05a637c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41174
32005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.4117432005
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.4065124295
Short name T943
Test name
Test status
Simulation time 157906929 ps
CPU time 0.81 seconds
Started Jul 23 06:41:28 PM PDT 24
Finished Jul 23 06:41:34 PM PDT 24
Peak memory 206736 kb
Host smart-6eeaa0fc-3390-40b7-a5bf-225d4e608ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40651
24295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.4065124295
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.255391768
Short name T2481
Test name
Test status
Simulation time 235891835 ps
CPU time 0.96 seconds
Started Jul 23 06:41:36 PM PDT 24
Finished Jul 23 06:41:42 PM PDT 24
Peak memory 206748 kb
Host smart-68d492f9-5169-4144-b351-518ed030ba32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25539
1768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.255391768
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.3872512738
Short name T512
Test name
Test status
Simulation time 216414270 ps
CPU time 0.85 seconds
Started Jul 23 06:41:29 PM PDT 24
Finished Jul 23 06:41:35 PM PDT 24
Peak memory 206732 kb
Host smart-ae0b1b7e-6bff-4735-a523-8e3fbd66dbbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38725
12738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.3872512738
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.292548123
Short name T1615
Test name
Test status
Simulation time 23271420731 ps
CPU time 22.52 seconds
Started Jul 23 06:41:30 PM PDT 24
Finished Jul 23 06:41:57 PM PDT 24
Peak memory 206808 kb
Host smart-e8d2d769-bf21-49d0-af60-fc8111a7d645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29254
8123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.292548123
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.3034579705
Short name T1416
Test name
Test status
Simulation time 3303230119 ps
CPU time 4.31 seconds
Started Jul 23 06:41:29 PM PDT 24
Finished Jul 23 06:41:39 PM PDT 24
Peak memory 206836 kb
Host smart-fae7075a-be93-4df5-89fb-baf0b02d0a3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30345
79705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.3034579705
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.4055725081
Short name T817
Test name
Test status
Simulation time 9406035913 ps
CPU time 249.79 seconds
Started Jul 23 06:41:29 PM PDT 24
Finished Jul 23 06:45:44 PM PDT 24
Peak memory 206948 kb
Host smart-daa026be-d2d9-4ba1-9476-c6b785bf1855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40557
25081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.4055725081
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.667298679
Short name T1335
Test name
Test status
Simulation time 6861648607 ps
CPU time 61.99 seconds
Started Jul 23 06:41:30 PM PDT 24
Finished Jul 23 06:42:37 PM PDT 24
Peak memory 206896 kb
Host smart-71e92301-3eb6-4caa-86ec-35da7608b84c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=667298679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.667298679
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.2076374444
Short name T2180
Test name
Test status
Simulation time 242225708 ps
CPU time 0.96 seconds
Started Jul 23 06:41:28 PM PDT 24
Finished Jul 23 06:41:34 PM PDT 24
Peak memory 206772 kb
Host smart-1fe94d02-e275-4fbe-a840-456843a68a25
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2076374444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.2076374444
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.1013267427
Short name T1970
Test name
Test status
Simulation time 231254345 ps
CPU time 0.9 seconds
Started Jul 23 06:41:26 PM PDT 24
Finished Jul 23 06:41:33 PM PDT 24
Peak memory 206780 kb
Host smart-81421791-4667-4381-9ec4-c6caed241bb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10132
67427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.1013267427
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.4055837622
Short name T1707
Test name
Test status
Simulation time 5602458344 ps
CPU time 43.14 seconds
Started Jul 23 06:41:29 PM PDT 24
Finished Jul 23 06:42:18 PM PDT 24
Peak memory 206976 kb
Host smart-4e6b4bc7-c34e-435c-a71f-0d2c499bba05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40558
37622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.4055837622
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.3426960323
Short name T308
Test name
Test status
Simulation time 6802617371 ps
CPU time 50.19 seconds
Started Jul 23 06:41:28 PM PDT 24
Finished Jul 23 06:42:24 PM PDT 24
Peak memory 206960 kb
Host smart-f869fded-d0ff-490d-a5d5-4b505a68cb3e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3426960323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.3426960323
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.1038464
Short name T2238
Test name
Test status
Simulation time 151741412 ps
CPU time 0.8 seconds
Started Jul 23 06:41:28 PM PDT 24
Finished Jul 23 06:41:34 PM PDT 24
Peak memory 206672 kb
Host smart-9d35e021-7b5c-479e-a7da-696675979ef0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1038464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.1038464
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.3985808097
Short name T906
Test name
Test status
Simulation time 166867157 ps
CPU time 0.8 seconds
Started Jul 23 06:41:27 PM PDT 24
Finished Jul 23 06:41:33 PM PDT 24
Peak memory 206736 kb
Host smart-be5bf7a5-eae2-4b55-b4b0-3b60c52644c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39858
08097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.3985808097
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.3364064741
Short name T2205
Test name
Test status
Simulation time 204581962 ps
CPU time 0.83 seconds
Started Jul 23 06:41:34 PM PDT 24
Finished Jul 23 06:41:39 PM PDT 24
Peak memory 206744 kb
Host smart-d04b33b7-65e2-40e0-9a1c-75ff3b06d5fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33640
64741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.3364064741
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.1588873691
Short name T2454
Test name
Test status
Simulation time 185251050 ps
CPU time 0.84 seconds
Started Jul 23 06:41:28 PM PDT 24
Finished Jul 23 06:41:34 PM PDT 24
Peak memory 206760 kb
Host smart-77a30663-9732-41ab-aa57-82ec02d45bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15888
73691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.1588873691
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.3816204113
Short name T1620
Test name
Test status
Simulation time 151237236 ps
CPU time 0.78 seconds
Started Jul 23 06:41:33 PM PDT 24
Finished Jul 23 06:41:38 PM PDT 24
Peak memory 206720 kb
Host smart-563c9309-2b32-423d-9001-67efa49a9fff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38162
04113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.3816204113
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.2099738822
Short name T1089
Test name
Test status
Simulation time 171873567 ps
CPU time 0.83 seconds
Started Jul 23 06:41:34 PM PDT 24
Finished Jul 23 06:41:39 PM PDT 24
Peak memory 206748 kb
Host smart-4fb21d85-8844-4260-bff8-9def9c5532a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20997
38822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.2099738822
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.1370599820
Short name T998
Test name
Test status
Simulation time 216384709 ps
CPU time 0.9 seconds
Started Jul 23 06:41:33 PM PDT 24
Finished Jul 23 06:41:39 PM PDT 24
Peak memory 206764 kb
Host smart-69d80bd8-bd2a-461c-a15a-c14d95cb12a7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1370599820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.1370599820
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.3794468439
Short name T2256
Test name
Test status
Simulation time 162542469 ps
CPU time 0.78 seconds
Started Jul 23 06:41:34 PM PDT 24
Finished Jul 23 06:41:40 PM PDT 24
Peak memory 206736 kb
Host smart-488a3b61-47b7-4346-99ab-6eb56cec961f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37944
68439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.3794468439
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.1221763412
Short name T1540
Test name
Test status
Simulation time 95127507 ps
CPU time 0.69 seconds
Started Jul 23 06:41:39 PM PDT 24
Finished Jul 23 06:41:44 PM PDT 24
Peak memory 206704 kb
Host smart-4af31123-b42e-42ad-a5ea-a64cac02c1c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12217
63412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.1221763412
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.1857421469
Short name T1324
Test name
Test status
Simulation time 7067975157 ps
CPU time 16.31 seconds
Started Jul 23 06:41:34 PM PDT 24
Finished Jul 23 06:41:56 PM PDT 24
Peak memory 215212 kb
Host smart-8503b540-3cac-4b25-96b6-394a05ab6d2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18574
21469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.1857421469
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.852234146
Short name T2285
Test name
Test status
Simulation time 151961698 ps
CPU time 0.79 seconds
Started Jul 23 06:41:35 PM PDT 24
Finished Jul 23 06:41:40 PM PDT 24
Peak memory 206756 kb
Host smart-c7286268-482f-40df-bd9a-f0be6cf88598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85223
4146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.852234146
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.3770979275
Short name T1107
Test name
Test status
Simulation time 269523102 ps
CPU time 0.97 seconds
Started Jul 23 06:41:36 PM PDT 24
Finished Jul 23 06:41:41 PM PDT 24
Peak memory 206764 kb
Host smart-32e79cdc-da94-41ff-b3cf-b7b958ca4ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37709
79275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.3770979275
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.70669955
Short name T2574
Test name
Test status
Simulation time 163658678 ps
CPU time 0.82 seconds
Started Jul 23 06:41:37 PM PDT 24
Finished Jul 23 06:41:42 PM PDT 24
Peak memory 206756 kb
Host smart-a5e4dbcb-6af9-4bf9-ad0a-a507dfb38cee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70669
955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.70669955
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.3016181272
Short name T2036
Test name
Test status
Simulation time 154831650 ps
CPU time 0.78 seconds
Started Jul 23 06:41:35 PM PDT 24
Finished Jul 23 06:41:40 PM PDT 24
Peak memory 206752 kb
Host smart-df41819a-aba5-4459-b031-35311d068561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30161
81272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.3016181272
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.4096440588
Short name T2153
Test name
Test status
Simulation time 156650978 ps
CPU time 0.83 seconds
Started Jul 23 06:41:34 PM PDT 24
Finished Jul 23 06:41:40 PM PDT 24
Peak memory 206752 kb
Host smart-4b932e48-7667-41ea-9020-d6ab49687d41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40964
40588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.4096440588
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.1183814838
Short name T2145
Test name
Test status
Simulation time 160115036 ps
CPU time 0.77 seconds
Started Jul 23 06:41:34 PM PDT 24
Finished Jul 23 06:41:40 PM PDT 24
Peak memory 206756 kb
Host smart-ab88fb8a-ce30-44c2-ba81-024bc6ef81a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11838
14838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.1183814838
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.2592846047
Short name T438
Test name
Test status
Simulation time 185869916 ps
CPU time 0.84 seconds
Started Jul 23 06:41:34 PM PDT 24
Finished Jul 23 06:41:40 PM PDT 24
Peak memory 206768 kb
Host smart-3db42082-f875-4264-b799-e0fbd5e7b6ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25928
46047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.2592846047
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.710756684
Short name T2713
Test name
Test status
Simulation time 218777947 ps
CPU time 0.9 seconds
Started Jul 23 06:41:35 PM PDT 24
Finished Jul 23 06:41:41 PM PDT 24
Peak memory 206752 kb
Host smart-5fe7d514-4ef7-42ca-b8b8-147bdf4f9317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71075
6684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.710756684
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.466597283
Short name T152
Test name
Test status
Simulation time 5172457903 ps
CPU time 47.29 seconds
Started Jul 23 06:41:33 PM PDT 24
Finished Jul 23 06:42:25 PM PDT 24
Peak memory 206960 kb
Host smart-1c788fb0-6f46-4b58-bcda-0e4622509e88
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=466597283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.466597283
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.1330774976
Short name T2585
Test name
Test status
Simulation time 196483508 ps
CPU time 0.81 seconds
Started Jul 23 06:41:34 PM PDT 24
Finished Jul 23 06:41:40 PM PDT 24
Peak memory 206740 kb
Host smart-3aaf712b-2d01-4c49-ae5c-96ca400f0583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13307
74976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.1330774976
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.2234720054
Short name T1044
Test name
Test status
Simulation time 201874190 ps
CPU time 0.84 seconds
Started Jul 23 06:41:35 PM PDT 24
Finished Jul 23 06:41:41 PM PDT 24
Peak memory 206752 kb
Host smart-8b39c47e-d316-4640-98af-c3447425e01d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22347
20054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.2234720054
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.4056692373
Short name T1019
Test name
Test status
Simulation time 551586607 ps
CPU time 1.62 seconds
Started Jul 23 06:41:34 PM PDT 24
Finished Jul 23 06:41:40 PM PDT 24
Peak memory 206776 kb
Host smart-cc4a52dd-29d7-4533-a11b-efae2f9cc28b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40566
92373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.4056692373
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.1255718884
Short name T1512
Test name
Test status
Simulation time 3304519366 ps
CPU time 31.29 seconds
Started Jul 23 06:41:34 PM PDT 24
Finished Jul 23 06:42:10 PM PDT 24
Peak memory 206964 kb
Host smart-8640f745-cdd1-4599-ab31-96ce5c2b81fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12557
18884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.1255718884
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.229515794
Short name T178
Test name
Test status
Simulation time 36452025 ps
CPU time 0.64 seconds
Started Jul 23 06:41:46 PM PDT 24
Finished Jul 23 06:41:48 PM PDT 24
Peak memory 206744 kb
Host smart-691e5c68-079b-412a-b831-b2ab6509d6b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=229515794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.229515794
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.789664080
Short name T465
Test name
Test status
Simulation time 4335382844 ps
CPU time 5.67 seconds
Started Jul 23 06:41:34 PM PDT 24
Finished Jul 23 06:41:44 PM PDT 24
Peak memory 206792 kb
Host smart-2b0de886-3533-4589-8845-a932a5f28562
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=789664080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.789664080
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.610911912
Short name T623
Test name
Test status
Simulation time 13488852752 ps
CPU time 13.01 seconds
Started Jul 23 06:41:34 PM PDT 24
Finished Jul 23 06:41:51 PM PDT 24
Peak memory 206968 kb
Host smart-5af9c701-1067-4ef6-b310-19cab2c9f241
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=610911912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.610911912
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.647626520
Short name T15
Test name
Test status
Simulation time 23385472284 ps
CPU time 21.46 seconds
Started Jul 23 06:41:35 PM PDT 24
Finished Jul 23 06:42:01 PM PDT 24
Peak memory 206920 kb
Host smart-28952b5f-2b18-47ea-a487-6cae3a660f2b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=647626520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.647626520
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.51408223
Short name T1716
Test name
Test status
Simulation time 152983672 ps
CPU time 0.78 seconds
Started Jul 23 06:41:33 PM PDT 24
Finished Jul 23 06:41:39 PM PDT 24
Peak memory 206744 kb
Host smart-e05f61c2-c2ef-47b1-9204-eb1fbbbaaff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51408
223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.51408223
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.1949723401
Short name T1245
Test name
Test status
Simulation time 159223498 ps
CPU time 0.81 seconds
Started Jul 23 06:41:39 PM PDT 24
Finished Jul 23 06:41:44 PM PDT 24
Peak memory 206728 kb
Host smart-1f62ee09-c275-45c8-b069-2b21c1034225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19497
23401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.1949723401
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.2531330955
Short name T1234
Test name
Test status
Simulation time 484578321 ps
CPU time 1.53 seconds
Started Jul 23 06:41:35 PM PDT 24
Finished Jul 23 06:41:41 PM PDT 24
Peak memory 206740 kb
Host smart-ed4ac386-348f-43de-9c8f-5393dbca8150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25313
30955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.2531330955
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.3785889519
Short name T2573
Test name
Test status
Simulation time 824673192 ps
CPU time 1.95 seconds
Started Jul 23 06:41:36 PM PDT 24
Finished Jul 23 06:41:43 PM PDT 24
Peak memory 206816 kb
Host smart-c7578f8a-93c6-4380-8265-ab2135e4d2d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37858
89519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.3785889519
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.2246269047
Short name T1115
Test name
Test status
Simulation time 10071201503 ps
CPU time 17.58 seconds
Started Jul 23 06:41:35 PM PDT 24
Finished Jul 23 06:41:57 PM PDT 24
Peak memory 206924 kb
Host smart-e674d721-41c3-4ee1-bf6f-988f2dea1b0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22462
69047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.2246269047
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.399038192
Short name T1927
Test name
Test status
Simulation time 483099554 ps
CPU time 1.52 seconds
Started Jul 23 06:41:38 PM PDT 24
Finished Jul 23 06:41:44 PM PDT 24
Peak memory 206728 kb
Host smart-d9e86235-e302-4c80-b93f-b62277b758dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39903
8192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.399038192
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.4188203008
Short name T2452
Test name
Test status
Simulation time 140672955 ps
CPU time 0.76 seconds
Started Jul 23 06:41:34 PM PDT 24
Finished Jul 23 06:41:40 PM PDT 24
Peak memory 206772 kb
Host smart-100d5be5-f4e2-444a-b1c8-0d831fdf4ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41882
03008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.4188203008
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.600869451
Short name T1143
Test name
Test status
Simulation time 46018428 ps
CPU time 0.67 seconds
Started Jul 23 06:41:34 PM PDT 24
Finished Jul 23 06:41:39 PM PDT 24
Peak memory 206772 kb
Host smart-4a1c0173-9026-4e6b-a755-6f8215ce7eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60086
9451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.600869451
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.1729474909
Short name T568
Test name
Test status
Simulation time 892893123 ps
CPU time 2.13 seconds
Started Jul 23 06:41:37 PM PDT 24
Finished Jul 23 06:41:43 PM PDT 24
Peak memory 206900 kb
Host smart-e6550321-242e-40d5-b0de-67dea7be0d3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17294
74909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.1729474909
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.1464695627
Short name T1182
Test name
Test status
Simulation time 225021215 ps
CPU time 1.25 seconds
Started Jul 23 06:41:41 PM PDT 24
Finished Jul 23 06:41:46 PM PDT 24
Peak memory 206852 kb
Host smart-49322a19-a27c-4c76-b08c-3409fa37e7bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14646
95627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.1464695627
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.4262159004
Short name T117
Test name
Test status
Simulation time 268388815 ps
CPU time 0.94 seconds
Started Jul 23 06:41:42 PM PDT 24
Finished Jul 23 06:41:47 PM PDT 24
Peak memory 206760 kb
Host smart-6b00116f-f956-4f19-a429-ac5e75067e93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42621
59004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.4262159004
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.2146669201
Short name T2587
Test name
Test status
Simulation time 141092655 ps
CPU time 0.76 seconds
Started Jul 23 06:41:42 PM PDT 24
Finished Jul 23 06:41:46 PM PDT 24
Peak memory 206768 kb
Host smart-bb9eb2d2-6bf6-45a6-a6f2-c01bd3efc540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21466
69201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.2146669201
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.2015185030
Short name T2450
Test name
Test status
Simulation time 217655425 ps
CPU time 0.89 seconds
Started Jul 23 06:41:40 PM PDT 24
Finished Jul 23 06:41:45 PM PDT 24
Peak memory 206716 kb
Host smart-7f306c24-f905-4c8e-ab17-f1f7c1c29289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20151
85030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.2015185030
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.2100341833
Short name T2296
Test name
Test status
Simulation time 6313745017 ps
CPU time 57.59 seconds
Started Jul 23 06:41:42 PM PDT 24
Finished Jul 23 06:42:43 PM PDT 24
Peak memory 206920 kb
Host smart-3fae9cea-e535-4c5a-adc4-c15a199cf36c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2100341833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.2100341833
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/19.usbdev_iso_retraction.2320794783
Short name T859
Test name
Test status
Simulation time 12410873465 ps
CPU time 49.57 seconds
Started Jul 23 06:41:41 PM PDT 24
Finished Jul 23 06:42:34 PM PDT 24
Peak memory 206952 kb
Host smart-9778292f-f037-4540-a0c0-d557ab8b7057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23207
94783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.2320794783
Directory /workspace/19.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.3526212466
Short name T387
Test name
Test status
Simulation time 223576891 ps
CPU time 0.89 seconds
Started Jul 23 06:41:42 PM PDT 24
Finished Jul 23 06:41:47 PM PDT 24
Peak memory 206692 kb
Host smart-0a2de749-5581-43b7-8777-2612bd4421a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35262
12466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.3526212466
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.2455117610
Short name T1433
Test name
Test status
Simulation time 23314620701 ps
CPU time 27.07 seconds
Started Jul 23 06:41:39 PM PDT 24
Finished Jul 23 06:42:10 PM PDT 24
Peak memory 206832 kb
Host smart-8dc79017-c8e3-42b4-a9d5-2e6fcb4cc45b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24551
17610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.2455117610
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.2845664771
Short name T1568
Test name
Test status
Simulation time 3287828805 ps
CPU time 4.47 seconds
Started Jul 23 06:41:41 PM PDT 24
Finished Jul 23 06:41:49 PM PDT 24
Peak memory 206768 kb
Host smart-11384ab3-05ee-4e23-a313-fe99a6063480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28456
64771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.2845664771
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.2742267608
Short name T1816
Test name
Test status
Simulation time 6426147528 ps
CPU time 178.85 seconds
Started Jul 23 06:41:39 PM PDT 24
Finished Jul 23 06:44:42 PM PDT 24
Peak memory 206968 kb
Host smart-0dc3615d-018f-4c19-ab48-1906ace64a07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27422
67608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.2742267608
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.1841820502
Short name T2638
Test name
Test status
Simulation time 7067091888 ps
CPU time 51.38 seconds
Started Jul 23 06:41:40 PM PDT 24
Finished Jul 23 06:42:35 PM PDT 24
Peak memory 206972 kb
Host smart-8e2c5e2c-1427-4af7-b762-e88fd1c63263
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1841820502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.1841820502
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.813773371
Short name T515
Test name
Test status
Simulation time 295821955 ps
CPU time 0.94 seconds
Started Jul 23 06:41:41 PM PDT 24
Finished Jul 23 06:41:46 PM PDT 24
Peak memory 206724 kb
Host smart-fb853d2a-9c53-4b12-8046-7b64d6e095ef
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=813773371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.813773371
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.2065666305
Short name T587
Test name
Test status
Simulation time 191533736 ps
CPU time 0.85 seconds
Started Jul 23 06:41:40 PM PDT 24
Finished Jul 23 06:41:45 PM PDT 24
Peak memory 206720 kb
Host smart-78d72652-9146-4e97-9043-77640bd2f3cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20656
66305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.2065666305
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.33742658
Short name T1395
Test name
Test status
Simulation time 4673300593 ps
CPU time 131.23 seconds
Started Jul 23 06:41:40 PM PDT 24
Finished Jul 23 06:43:55 PM PDT 24
Peak memory 206896 kb
Host smart-3d80891e-8177-429c-839d-e2dd6eae33a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33742
658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.33742658
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.905098100
Short name T164
Test name
Test status
Simulation time 6678315426 ps
CPU time 48.96 seconds
Started Jul 23 06:41:42 PM PDT 24
Finished Jul 23 06:42:34 PM PDT 24
Peak memory 206836 kb
Host smart-b44f10b6-4e78-47a9-ae06-93c699b4286f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=905098100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.905098100
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.933039245
Short name T1602
Test name
Test status
Simulation time 171433675 ps
CPU time 0.81 seconds
Started Jul 23 06:41:42 PM PDT 24
Finished Jul 23 06:41:46 PM PDT 24
Peak memory 206752 kb
Host smart-b524fe9e-2966-4fc1-840a-7d512c5988fa
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=933039245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.933039245
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.2299720454
Short name T2228
Test name
Test status
Simulation time 163890655 ps
CPU time 0.78 seconds
Started Jul 23 06:41:41 PM PDT 24
Finished Jul 23 06:41:45 PM PDT 24
Peak memory 206756 kb
Host smart-beb6b9b5-e25c-42c0-b6d8-588db9879484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22997
20454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.2299720454
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.2515993269
Short name T2623
Test name
Test status
Simulation time 173396433 ps
CPU time 0.85 seconds
Started Jul 23 06:41:41 PM PDT 24
Finished Jul 23 06:41:45 PM PDT 24
Peak memory 206664 kb
Host smart-ce0ebdd2-ee00-407a-9fee-49444476344f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25159
93269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.2515993269
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.2134011577
Short name T885
Test name
Test status
Simulation time 163486215 ps
CPU time 0.8 seconds
Started Jul 23 06:41:40 PM PDT 24
Finished Jul 23 06:41:44 PM PDT 24
Peak memory 206680 kb
Host smart-f62b3296-f8b5-415f-ac36-837e7c0bbed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21340
11577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.2134011577
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.2234121072
Short name T2240
Test name
Test status
Simulation time 159135256 ps
CPU time 0.82 seconds
Started Jul 23 06:41:41 PM PDT 24
Finished Jul 23 06:41:46 PM PDT 24
Peak memory 206740 kb
Host smart-f387dc6f-9a3e-4c03-a652-bd9f20620b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22341
21072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.2234121072
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.576404197
Short name T1064
Test name
Test status
Simulation time 229073263 ps
CPU time 0.91 seconds
Started Jul 23 06:41:40 PM PDT 24
Finished Jul 23 06:41:45 PM PDT 24
Peak memory 206736 kb
Host smart-537cdf2b-7c27-4a43-aa95-df91e0593e1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57640
4197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.576404197
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.3446427534
Short name T1597
Test name
Test status
Simulation time 187864984 ps
CPU time 0.83 seconds
Started Jul 23 06:41:48 PM PDT 24
Finished Jul 23 06:41:51 PM PDT 24
Peak memory 206772 kb
Host smart-a6f65be0-fcf2-4c00-ae46-d038c5a5e1ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34464
27534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.3446427534
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.933620148
Short name T2595
Test name
Test status
Simulation time 217741435 ps
CPU time 0.93 seconds
Started Jul 23 06:41:48 PM PDT 24
Finished Jul 23 06:41:52 PM PDT 24
Peak memory 206688 kb
Host smart-f2d8fb74-08fa-4872-b10e-fb5f6edb5fb5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=933620148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.933620148
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.3052381739
Short name T1728
Test name
Test status
Simulation time 192752848 ps
CPU time 0.86 seconds
Started Jul 23 06:41:48 PM PDT 24
Finished Jul 23 06:41:51 PM PDT 24
Peak memory 206772 kb
Host smart-2ac261e8-1541-4a35-b6e3-c71f16f40c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30523
81739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.3052381739
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.1527791287
Short name T35
Test name
Test status
Simulation time 33110293 ps
CPU time 0.65 seconds
Started Jul 23 06:41:48 PM PDT 24
Finished Jul 23 06:41:52 PM PDT 24
Peak memory 206672 kb
Host smart-7f13d311-fce8-4350-9d3e-efb88d487ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15277
91287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.1527791287
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.429979050
Short name T2162
Test name
Test status
Simulation time 10679638667 ps
CPU time 26.39 seconds
Started Jul 23 06:41:49 PM PDT 24
Finished Jul 23 06:42:18 PM PDT 24
Peak memory 206944 kb
Host smart-c3b8a88e-4644-4b79-9320-ecb305f58055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42997
9050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.429979050
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.2622395149
Short name T2075
Test name
Test status
Simulation time 184518847 ps
CPU time 0.8 seconds
Started Jul 23 06:41:50 PM PDT 24
Finished Jul 23 06:41:53 PM PDT 24
Peak memory 206756 kb
Host smart-d8c18f75-8c52-476b-9d84-d9deff9a9ac2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26223
95149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.2622395149
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.3041204864
Short name T2575
Test name
Test status
Simulation time 273614515 ps
CPU time 0.97 seconds
Started Jul 23 06:41:49 PM PDT 24
Finished Jul 23 06:41:53 PM PDT 24
Peak memory 206764 kb
Host smart-fc8759fe-5c1b-473e-83fd-4ff083606a0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30412
04864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.3041204864
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.249495105
Short name T28
Test name
Test status
Simulation time 188583728 ps
CPU time 0.8 seconds
Started Jul 23 06:41:48 PM PDT 24
Finished Jul 23 06:41:51 PM PDT 24
Peak memory 206652 kb
Host smart-323db231-3f1a-4824-85ab-8112442f6d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24949
5105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.249495105
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.2533992743
Short name T1782
Test name
Test status
Simulation time 229747722 ps
CPU time 0.92 seconds
Started Jul 23 06:41:45 PM PDT 24
Finished Jul 23 06:41:48 PM PDT 24
Peak memory 206748 kb
Host smart-77ec6bc8-d670-4dad-8a11-b75dc399dbd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25339
92743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.2533992743
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.2052279369
Short name T2525
Test name
Test status
Simulation time 182931941 ps
CPU time 0.79 seconds
Started Jul 23 06:41:47 PM PDT 24
Finished Jul 23 06:41:50 PM PDT 24
Peak memory 206736 kb
Host smart-a38df432-bf27-44bb-9b82-12ff40c83763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20522
79369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.2052279369
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.1178451163
Short name T2291
Test name
Test status
Simulation time 238376711 ps
CPU time 0.85 seconds
Started Jul 23 06:41:49 PM PDT 24
Finished Jul 23 06:41:53 PM PDT 24
Peak memory 206676 kb
Host smart-9d898dbf-63e8-4528-9906-d6906fee6306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11784
51163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.1178451163
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.280333096
Short name T1929
Test name
Test status
Simulation time 167714538 ps
CPU time 0.79 seconds
Started Jul 23 06:41:51 PM PDT 24
Finished Jul 23 06:41:54 PM PDT 24
Peak memory 206768 kb
Host smart-3833a65d-2589-46d3-9c2d-fb828c1a1e6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28033
3096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.280333096
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.3834186223
Short name T1389
Test name
Test status
Simulation time 262511261 ps
CPU time 1.04 seconds
Started Jul 23 06:41:49 PM PDT 24
Finished Jul 23 06:41:53 PM PDT 24
Peak memory 206760 kb
Host smart-e17d7a94-9cc8-4f53-b59f-932f423b9df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38341
86223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.3834186223
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.2380231628
Short name T2169
Test name
Test status
Simulation time 3347859336 ps
CPU time 88.5 seconds
Started Jul 23 06:41:48 PM PDT 24
Finished Jul 23 06:43:19 PM PDT 24
Peak memory 206840 kb
Host smart-b28c3a95-3e3e-4ff6-8eef-76d4889ba7d9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2380231628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.2380231628
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.4237468224
Short name T1231
Test name
Test status
Simulation time 160981410 ps
CPU time 0.81 seconds
Started Jul 23 06:41:50 PM PDT 24
Finished Jul 23 06:41:53 PM PDT 24
Peak memory 206744 kb
Host smart-b1033a8e-373d-4265-a34b-d2890d314489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42374
68224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.4237468224
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.3554840621
Short name T1901
Test name
Test status
Simulation time 155220531 ps
CPU time 0.77 seconds
Started Jul 23 06:41:49 PM PDT 24
Finished Jul 23 06:41:52 PM PDT 24
Peak memory 206692 kb
Host smart-f1b7d1de-3e25-4de6-928c-3d729159cc87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35548
40621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.3554840621
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.95354547
Short name T1926
Test name
Test status
Simulation time 983799247 ps
CPU time 2.21 seconds
Started Jul 23 06:41:47 PM PDT 24
Finished Jul 23 06:41:51 PM PDT 24
Peak memory 206900 kb
Host smart-fcf3e1d5-471e-4e55-aead-28d5d0fb475e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95354
547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.95354547
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.1327627066
Short name T344
Test name
Test status
Simulation time 3679925923 ps
CPU time 101.98 seconds
Started Jul 23 06:41:52 PM PDT 24
Finished Jul 23 06:43:36 PM PDT 24
Peak memory 206924 kb
Host smart-79de60c8-f7f3-4dd8-bf07-047aa5ef210d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13276
27066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.1327627066
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.412344056
Short name T1379
Test name
Test status
Simulation time 95881693 ps
CPU time 0.74 seconds
Started Jul 23 06:37:44 PM PDT 24
Finished Jul 23 06:37:46 PM PDT 24
Peak memory 206752 kb
Host smart-8e76e944-8425-4034-a6a4-8ad647f511f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=412344056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.412344056
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.1598298485
Short name T980
Test name
Test status
Simulation time 4238205982 ps
CPU time 4.88 seconds
Started Jul 23 06:37:18 PM PDT 24
Finished Jul 23 06:37:24 PM PDT 24
Peak memory 206800 kb
Host smart-40682b17-88d0-4045-8539-96185c5b197b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1598298485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.1598298485
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.3735546430
Short name T1278
Test name
Test status
Simulation time 13356410141 ps
CPU time 13.48 seconds
Started Jul 23 06:37:19 PM PDT 24
Finished Jul 23 06:37:35 PM PDT 24
Peak memory 206772 kb
Host smart-09843ecd-90f0-4c60-b7de-e28e19f64f44
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3735546430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.3735546430
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.2135357046
Short name T1422
Test name
Test status
Simulation time 23366726194 ps
CPU time 24.9 seconds
Started Jul 23 06:37:18 PM PDT 24
Finished Jul 23 06:37:44 PM PDT 24
Peak memory 207120 kb
Host smart-c7195c11-7cc4-45b9-b3a0-65ce57b2b792
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2135357046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.2135357046
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.1513231818
Short name T694
Test name
Test status
Simulation time 156704800 ps
CPU time 0.78 seconds
Started Jul 23 06:37:19 PM PDT 24
Finished Jul 23 06:37:22 PM PDT 24
Peak memory 206796 kb
Host smart-f8345ad8-76ca-41aa-87dc-f996847ad675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15132
31818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.1513231818
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.544886561
Short name T60
Test name
Test status
Simulation time 153124325 ps
CPU time 0.8 seconds
Started Jul 23 06:37:19 PM PDT 24
Finished Jul 23 06:37:22 PM PDT 24
Peak memory 206764 kb
Host smart-bee13065-fbfe-4fd8-8f1c-72da9ddd2a26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54488
6561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.544886561
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.2689730656
Short name T2261
Test name
Test status
Simulation time 142672978 ps
CPU time 0.82 seconds
Started Jul 23 06:37:19 PM PDT 24
Finished Jul 23 06:37:22 PM PDT 24
Peak memory 206740 kb
Host smart-e31b59f3-584a-4578-bb8f-cb3c7db4e1d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26897
30656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.2689730656
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.117095188
Short name T79
Test name
Test status
Simulation time 204173873 ps
CPU time 0.85 seconds
Started Jul 23 06:37:18 PM PDT 24
Finished Jul 23 06:37:21 PM PDT 24
Peak memory 206736 kb
Host smart-e06a510b-cca8-4522-8248-efb3441a3bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11709
5188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.117095188
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.789642433
Short name T1772
Test name
Test status
Simulation time 518836849 ps
CPU time 1.52 seconds
Started Jul 23 06:37:16 PM PDT 24
Finished Jul 23 06:37:19 PM PDT 24
Peak memory 206812 kb
Host smart-70102431-6a20-4492-848a-599763e139c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78964
2433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.789642433
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.2747238169
Short name T1056
Test name
Test status
Simulation time 428816723 ps
CPU time 1.21 seconds
Started Jul 23 06:37:20 PM PDT 24
Finished Jul 23 06:37:23 PM PDT 24
Peak memory 206756 kb
Host smart-c330db9a-f7c0-461f-a373-382b765ab0a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27472
38169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.2747238169
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.3380487696
Short name T738
Test name
Test status
Simulation time 15411531891 ps
CPU time 27.07 seconds
Started Jul 23 06:37:18 PM PDT 24
Finished Jul 23 06:37:46 PM PDT 24
Peak memory 206952 kb
Host smart-bc15bd64-eda9-4ad1-a289-8ba215f91e24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33804
87696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.3380487696
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.2354979820
Short name T2373
Test name
Test status
Simulation time 338214786 ps
CPU time 1.19 seconds
Started Jul 23 06:37:22 PM PDT 24
Finished Jul 23 06:37:24 PM PDT 24
Peak memory 206756 kb
Host smart-31c01703-9715-4f34-9047-118654c0b51f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23549
79820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.2354979820
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.1256605903
Short name T1791
Test name
Test status
Simulation time 148363799 ps
CPU time 0.77 seconds
Started Jul 23 06:37:25 PM PDT 24
Finished Jul 23 06:37:27 PM PDT 24
Peak memory 206712 kb
Host smart-52b02f9e-b87b-4a8e-8bc7-00c1b00d6307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12566
05903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.1256605903
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.3967121889
Short name T1644
Test name
Test status
Simulation time 50920190 ps
CPU time 0.66 seconds
Started Jul 23 06:37:22 PM PDT 24
Finished Jul 23 06:37:24 PM PDT 24
Peak memory 206760 kb
Host smart-8f96562c-437b-4ee9-a861-8e0fb93f4289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39671
21889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.3967121889
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.3621296561
Short name T2237
Test name
Test status
Simulation time 970776112 ps
CPU time 2.17 seconds
Started Jul 23 06:37:23 PM PDT 24
Finished Jul 23 06:37:26 PM PDT 24
Peak memory 206912 kb
Host smart-eeea474d-a816-47b0-b735-843a1032479c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36212
96561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.3621296561
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.2811131995
Short name T889
Test name
Test status
Simulation time 161142374 ps
CPU time 1.36 seconds
Started Jul 23 06:37:26 PM PDT 24
Finished Jul 23 06:37:29 PM PDT 24
Peak memory 206864 kb
Host smart-cb7865b2-7017-4bdb-9bdf-2326f3571d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28111
31995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.2811131995
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.1199229825
Short name T1487
Test name
Test status
Simulation time 99177703223 ps
CPU time 130.63 seconds
Started Jul 23 06:37:23 PM PDT 24
Finished Jul 23 06:39:35 PM PDT 24
Peak memory 207124 kb
Host smart-71c16e93-e611-44b3-b5ad-a4c0a8411522
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1199229825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.1199229825
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.3852095389
Short name T666
Test name
Test status
Simulation time 105141617085 ps
CPU time 146.87 seconds
Started Jul 23 06:37:26 PM PDT 24
Finished Jul 23 06:39:54 PM PDT 24
Peak memory 206908 kb
Host smart-1cb41b23-c259-48f4-a687-30b47191483a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852095389 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.3852095389
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.555934028
Short name T2570
Test name
Test status
Simulation time 90108042589 ps
CPU time 115.61 seconds
Started Jul 23 06:37:26 PM PDT 24
Finished Jul 23 06:39:23 PM PDT 24
Peak memory 206936 kb
Host smart-8f4426e8-4c65-40ad-90bc-df27766096c3
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=555934028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.555934028
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.4211767389
Short name T1882
Test name
Test status
Simulation time 101296548840 ps
CPU time 133.48 seconds
Started Jul 23 06:37:23 PM PDT 24
Finished Jul 23 06:39:38 PM PDT 24
Peak memory 206964 kb
Host smart-84164c71-a348-4d63-a6ee-8180d8a4ebe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211767389 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.4211767389
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.3400953095
Short name T2701
Test name
Test status
Simulation time 97143877557 ps
CPU time 139.87 seconds
Started Jul 23 06:37:26 PM PDT 24
Finished Jul 23 06:39:47 PM PDT 24
Peak memory 206852 kb
Host smart-fabc4bb8-34a0-4b32-9b6f-6990d72c2bc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34009
53095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.3400953095
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.395464511
Short name T2014
Test name
Test status
Simulation time 180945015 ps
CPU time 0.84 seconds
Started Jul 23 06:37:23 PM PDT 24
Finished Jul 23 06:37:26 PM PDT 24
Peak memory 206744 kb
Host smart-c8055b07-9ace-43c6-a279-6f9993fdb907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39546
4511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.395464511
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.1832247719
Short name T1861
Test name
Test status
Simulation time 164147261 ps
CPU time 0.74 seconds
Started Jul 23 06:37:29 PM PDT 24
Finished Jul 23 06:37:31 PM PDT 24
Peak memory 206748 kb
Host smart-36904aca-f073-4ff5-97c4-7755dac6d6c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18322
47719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.1832247719
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.1322954160
Short name T1146
Test name
Test status
Simulation time 212594875 ps
CPU time 0.88 seconds
Started Jul 23 06:37:31 PM PDT 24
Finished Jul 23 06:37:33 PM PDT 24
Peak memory 206756 kb
Host smart-3d44399e-d2b1-40d7-8b72-95aea64802af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13229
54160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.1322954160
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_iso_retraction.2853964968
Short name T731
Test name
Test status
Simulation time 4839820512 ps
CPU time 18.27 seconds
Started Jul 23 06:37:30 PM PDT 24
Finished Jul 23 06:37:50 PM PDT 24
Peak memory 206964 kb
Host smart-089a67d3-24a7-456e-a9bd-4cbf1b640b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28539
64968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_iso_retraction.2853964968
Directory /workspace/2.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.1361527783
Short name T1828
Test name
Test status
Simulation time 199177684 ps
CPU time 0.79 seconds
Started Jul 23 06:37:30 PM PDT 24
Finished Jul 23 06:37:32 PM PDT 24
Peak memory 206736 kb
Host smart-78dde24b-1863-45ec-8c43-c6f8605dff23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13615
27783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.1361527783
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.774646934
Short name T1988
Test name
Test status
Simulation time 23294775707 ps
CPU time 25.43 seconds
Started Jul 23 06:37:30 PM PDT 24
Finished Jul 23 06:37:57 PM PDT 24
Peak memory 206800 kb
Host smart-74d8b323-6a05-47ae-b3cd-e34b2ea6ef46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77464
6934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.774646934
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.3144692894
Short name T350
Test name
Test status
Simulation time 3315241739 ps
CPU time 3.92 seconds
Started Jul 23 06:37:31 PM PDT 24
Finished Jul 23 06:37:36 PM PDT 24
Peak memory 206776 kb
Host smart-2cd2cb69-4250-41c5-91f8-120f8d13f5df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31446
92894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.3144692894
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.491379278
Short name T2636
Test name
Test status
Simulation time 6690253193 ps
CPU time 64.26 seconds
Started Jul 23 06:37:30 PM PDT 24
Finished Jul 23 06:38:35 PM PDT 24
Peak memory 207000 kb
Host smart-d5f47a49-b17d-4edf-9d8f-d48d86ebb69b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49137
9278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.491379278
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.1321131617
Short name T312
Test name
Test status
Simulation time 4742090177 ps
CPU time 44.73 seconds
Started Jul 23 06:37:29 PM PDT 24
Finished Jul 23 06:38:15 PM PDT 24
Peak memory 206916 kb
Host smart-fdbbca3b-9657-4935-a410-33416cf5da3b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1321131617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.1321131617
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.183296060
Short name T2116
Test name
Test status
Simulation time 243059909 ps
CPU time 0.91 seconds
Started Jul 23 06:37:30 PM PDT 24
Finished Jul 23 06:37:32 PM PDT 24
Peak memory 206772 kb
Host smart-69e37603-60b4-429c-a297-8e3591138653
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=183296060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.183296060
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.4042798765
Short name T1839
Test name
Test status
Simulation time 189322388 ps
CPU time 0.87 seconds
Started Jul 23 06:37:31 PM PDT 24
Finished Jul 23 06:37:32 PM PDT 24
Peak memory 206732 kb
Host smart-dc3368cb-a6a9-40e1-a050-af6266e084de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40427
98765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.4042798765
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.2959908389
Short name T1496
Test name
Test status
Simulation time 5604409865 ps
CPU time 164.03 seconds
Started Jul 23 06:37:30 PM PDT 24
Finished Jul 23 06:40:15 PM PDT 24
Peak memory 206936 kb
Host smart-aeddd117-4321-4e23-a986-fad0e0696601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29599
08389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.2959908389
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.1904579875
Short name T958
Test name
Test status
Simulation time 5116140125 ps
CPU time 143 seconds
Started Jul 23 06:37:31 PM PDT 24
Finished Jul 23 06:39:55 PM PDT 24
Peak memory 206972 kb
Host smart-ee9051bd-3726-4380-9439-5229a8844e8f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1904579875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.1904579875
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.2783804896
Short name T540
Test name
Test status
Simulation time 147320787 ps
CPU time 0.84 seconds
Started Jul 23 06:37:30 PM PDT 24
Finished Jul 23 06:37:31 PM PDT 24
Peak memory 206760 kb
Host smart-97f836d7-a640-4a18-926b-30e61cab2392
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2783804896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.2783804896
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.2057790834
Short name T2191
Test name
Test status
Simulation time 187874903 ps
CPU time 0.82 seconds
Started Jul 23 06:37:35 PM PDT 24
Finished Jul 23 06:37:38 PM PDT 24
Peak memory 206768 kb
Host smart-bd49b11f-bd6e-4887-a111-1034fd758e68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20577
90834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.2057790834
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.1121774510
Short name T2652
Test name
Test status
Simulation time 173695164 ps
CPU time 0.83 seconds
Started Jul 23 06:37:34 PM PDT 24
Finished Jul 23 06:37:36 PM PDT 24
Peak memory 206748 kb
Host smart-4d6598ad-7c1c-4044-b5af-4f1cf35c6061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11217
74510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.1121774510
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.2537274100
Short name T1030
Test name
Test status
Simulation time 206248441 ps
CPU time 0.8 seconds
Started Jul 23 06:37:35 PM PDT 24
Finished Jul 23 06:37:36 PM PDT 24
Peak memory 206760 kb
Host smart-b2a2e9b7-ca25-40d0-a0ae-8ae7f92ac2dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25372
74100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.2537274100
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.745481410
Short name T2303
Test name
Test status
Simulation time 227186906 ps
CPU time 0.87 seconds
Started Jul 23 06:37:36 PM PDT 24
Finished Jul 23 06:37:38 PM PDT 24
Peak memory 206728 kb
Host smart-a54f05e0-5c80-4842-ac16-e7f1885e54c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74548
1410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.745481410
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.2206287752
Short name T155
Test name
Test status
Simulation time 166331922 ps
CPU time 0.82 seconds
Started Jul 23 06:37:36 PM PDT 24
Finished Jul 23 06:37:38 PM PDT 24
Peak memory 206732 kb
Host smart-8d59c5b7-3232-45b1-89af-cef233609bde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22062
87752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.2206287752
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.3984145735
Short name T1026
Test name
Test status
Simulation time 299317711 ps
CPU time 1.01 seconds
Started Jul 23 06:37:34 PM PDT 24
Finished Jul 23 06:37:35 PM PDT 24
Peak memory 206756 kb
Host smart-e6b146f9-49d0-47aa-86ff-3ed4f2f03469
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3984145735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.3984145735
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.2538915205
Short name T197
Test name
Test status
Simulation time 214457396 ps
CPU time 0.85 seconds
Started Jul 23 06:37:35 PM PDT 24
Finished Jul 23 06:37:37 PM PDT 24
Peak memory 206740 kb
Host smart-b4165efa-2987-4275-bc6d-d497d25f4a49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25389
15205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.2538915205
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.3390157891
Short name T1808
Test name
Test status
Simulation time 138206016 ps
CPU time 0.75 seconds
Started Jul 23 06:37:35 PM PDT 24
Finished Jul 23 06:37:37 PM PDT 24
Peak memory 206752 kb
Host smart-9c495d80-f376-4013-9b88-2c0dd5c3d449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33901
57891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.3390157891
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.2766377331
Short name T1418
Test name
Test status
Simulation time 50517492 ps
CPU time 0.68 seconds
Started Jul 23 06:37:33 PM PDT 24
Finished Jul 23 06:37:34 PM PDT 24
Peak memory 206736 kb
Host smart-023778ae-5b0f-41c9-be33-ceeb3146dd68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27663
77331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.2766377331
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.3183271249
Short name T2197
Test name
Test status
Simulation time 15165394235 ps
CPU time 33.46 seconds
Started Jul 23 06:37:36 PM PDT 24
Finished Jul 23 06:38:11 PM PDT 24
Peak memory 206996 kb
Host smart-123f3db0-3c06-4f23-847e-ded9369728f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31832
71249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.3183271249
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.1438739859
Short name T2395
Test name
Test status
Simulation time 225738074 ps
CPU time 0.86 seconds
Started Jul 23 06:37:35 PM PDT 24
Finished Jul 23 06:37:38 PM PDT 24
Peak memory 206768 kb
Host smart-ef2032fc-8bdb-4bfb-9a8f-0d664918ab39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14387
39859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.1438739859
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.617691479
Short name T669
Test name
Test status
Simulation time 231814130 ps
CPU time 0.91 seconds
Started Jul 23 06:37:37 PM PDT 24
Finished Jul 23 06:37:39 PM PDT 24
Peak memory 206768 kb
Host smart-3161543e-6507-45c2-a31f-5fdd6e30b4c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61769
1479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.617691479
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.1865691877
Short name T172
Test name
Test status
Simulation time 10407140649 ps
CPU time 83.61 seconds
Started Jul 23 06:37:40 PM PDT 24
Finished Jul 23 06:39:05 PM PDT 24
Peak memory 206936 kb
Host smart-d9494b37-c0d2-4d88-8562-1b2087869c71
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1865691877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.1865691877
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.2133990559
Short name T477
Test name
Test status
Simulation time 14151003225 ps
CPU time 291.16 seconds
Started Jul 23 06:37:42 PM PDT 24
Finished Jul 23 06:42:34 PM PDT 24
Peak memory 206964 kb
Host smart-a5d4fedd-b6bb-48e3-9895-b82292bad1ec
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2133990559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.2133990559
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.2469522297
Short name T719
Test name
Test status
Simulation time 11590351597 ps
CPU time 62.64 seconds
Started Jul 23 06:37:41 PM PDT 24
Finished Jul 23 06:38:45 PM PDT 24
Peak memory 206832 kb
Host smart-e402fb70-5722-4566-86bc-141e46c46039
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2469522297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.2469522297
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.3255089765
Short name T1241
Test name
Test status
Simulation time 228249538 ps
CPU time 0.89 seconds
Started Jul 23 06:37:41 PM PDT 24
Finished Jul 23 06:37:43 PM PDT 24
Peak memory 206748 kb
Host smart-f9242982-801a-4258-b067-dfeda4de1f91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32550
89765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.3255089765
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.3372208951
Short name T687
Test name
Test status
Simulation time 226193575 ps
CPU time 0.88 seconds
Started Jul 23 06:37:39 PM PDT 24
Finished Jul 23 06:37:41 PM PDT 24
Peak memory 206772 kb
Host smart-6f82967b-3c50-4cef-a621-bf15c267c776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33722
08951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.3372208951
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.762872859
Short name T854
Test name
Test status
Simulation time 187161952 ps
CPU time 0.84 seconds
Started Jul 23 06:37:39 PM PDT 24
Finished Jul 23 06:37:41 PM PDT 24
Peak memory 206744 kb
Host smart-238c5d25-1ad0-4b73-ae77-ac22153c3388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76287
2859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.762872859
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.1620529538
Short name T2497
Test name
Test status
Simulation time 187114570 ps
CPU time 0.89 seconds
Started Jul 23 06:37:40 PM PDT 24
Finished Jul 23 06:37:43 PM PDT 24
Peak memory 206728 kb
Host smart-c9e16416-89e6-41cc-9911-7b4174b236a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16205
29538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.1620529538
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.1668480290
Short name T189
Test name
Test status
Simulation time 1510077243 ps
CPU time 2.22 seconds
Started Jul 23 06:37:46 PM PDT 24
Finished Jul 23 06:37:50 PM PDT 24
Peak memory 225484 kb
Host smart-7d635c6b-54ad-4b6d-aea9-f1ae10359a24
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1668480290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.1668480290
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.2046509152
Short name T2172
Test name
Test status
Simulation time 328522930 ps
CPU time 1.19 seconds
Started Jul 23 06:37:39 PM PDT 24
Finished Jul 23 06:37:41 PM PDT 24
Peak memory 206748 kb
Host smart-a4b225f0-8c0d-4f23-a762-685a62d73c18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20465
09152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.2046509152
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.470543409
Short name T1083
Test name
Test status
Simulation time 201945360 ps
CPU time 0.89 seconds
Started Jul 23 06:37:40 PM PDT 24
Finished Jul 23 06:37:43 PM PDT 24
Peak memory 206720 kb
Host smart-6e9584bf-f788-4ef8-b09a-219037f59bbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47054
3409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.470543409
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.742671495
Short name T2476
Test name
Test status
Simulation time 197111378 ps
CPU time 0.8 seconds
Started Jul 23 06:37:40 PM PDT 24
Finished Jul 23 06:37:42 PM PDT 24
Peak memory 206752 kb
Host smart-d231186b-04cb-4927-823e-c8fc043f8dcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74267
1495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.742671495
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.391982110
Short name T986
Test name
Test status
Simulation time 179039419 ps
CPU time 0.82 seconds
Started Jul 23 06:37:40 PM PDT 24
Finished Jul 23 06:37:42 PM PDT 24
Peak memory 206720 kb
Host smart-63d17b79-b025-405b-ac49-e53c61b78088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39198
2110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.391982110
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.1999011091
Short name T1374
Test name
Test status
Simulation time 234191727 ps
CPU time 0.95 seconds
Started Jul 23 06:37:43 PM PDT 24
Finished Jul 23 06:37:44 PM PDT 24
Peak memory 206764 kb
Host smart-95635e37-edec-4b8e-99cc-b019de303ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19990
11091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.1999011091
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.3043908800
Short name T1626
Test name
Test status
Simulation time 4400814348 ps
CPU time 41.84 seconds
Started Jul 23 06:37:40 PM PDT 24
Finished Jul 23 06:38:24 PM PDT 24
Peak memory 206840 kb
Host smart-2fafbf73-4fbb-4d8a-9735-2e15d9320e24
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3043908800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.3043908800
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.273521277
Short name T2332
Test name
Test status
Simulation time 211364247 ps
CPU time 0.86 seconds
Started Jul 23 06:37:40 PM PDT 24
Finished Jul 23 06:37:43 PM PDT 24
Peak memory 206728 kb
Host smart-4d6c910f-5daa-4fd0-bf6c-8701b98c7e37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27352
1277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.273521277
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.3471098014
Short name T677
Test name
Test status
Simulation time 203619555 ps
CPU time 0.86 seconds
Started Jul 23 06:37:50 PM PDT 24
Finished Jul 23 06:37:52 PM PDT 24
Peak memory 206708 kb
Host smart-b2f53e7a-c056-4c93-a130-0b1578d4d2c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34710
98014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.3471098014
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.1260338826
Short name T638
Test name
Test status
Simulation time 937206892 ps
CPU time 2.06 seconds
Started Jul 23 06:37:50 PM PDT 24
Finished Jul 23 06:37:54 PM PDT 24
Peak memory 206856 kb
Host smart-77c03511-8b5a-4e2e-af94-423b6c0fdb88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12603
38826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.1260338826
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.2377670147
Short name T1256
Test name
Test status
Simulation time 6676896666 ps
CPU time 180.58 seconds
Started Jul 23 06:37:46 PM PDT 24
Finished Jul 23 06:40:47 PM PDT 24
Peak memory 206924 kb
Host smart-eaf29487-7559-477f-a653-7ff3368e7b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23776
70147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.2377670147
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.3204873742
Short name T167
Test name
Test status
Simulation time 5054368382 ps
CPU time 45.57 seconds
Started Jul 23 06:37:45 PM PDT 24
Finished Jul 23 06:38:32 PM PDT 24
Peak memory 207052 kb
Host smart-19f3c8ca-e945-4f3c-a05e-504ef389688a
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3204873742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.3204873742
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.3931045248
Short name T1686
Test name
Test status
Simulation time 55979780 ps
CPU time 0.71 seconds
Started Jul 23 06:42:02 PM PDT 24
Finished Jul 23 06:42:05 PM PDT 24
Peak memory 206748 kb
Host smart-e83a6060-92bd-4ba9-8e89-ed1605ac4ad3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3931045248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.3931045248
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.2622705861
Short name T750
Test name
Test status
Simulation time 3613117438 ps
CPU time 4.09 seconds
Started Jul 23 06:41:52 PM PDT 24
Finished Jul 23 06:41:58 PM PDT 24
Peak memory 206836 kb
Host smart-e7030831-dd58-451a-bc66-c0f75fef85cb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2622705861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.2622705861
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.523073541
Short name T9
Test name
Test status
Simulation time 13341536643 ps
CPU time 13.37 seconds
Started Jul 23 06:41:48 PM PDT 24
Finished Jul 23 06:42:04 PM PDT 24
Peak memory 206972 kb
Host smart-a57eb6e9-33bd-45cf-a610-c4c5896187e4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=523073541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.523073541
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.1615436127
Short name T1147
Test name
Test status
Simulation time 23321049851 ps
CPU time 24.26 seconds
Started Jul 23 06:41:50 PM PDT 24
Finished Jul 23 06:42:17 PM PDT 24
Peak memory 206836 kb
Host smart-d102e677-bd93-4c8a-8fc5-dfe24024bb7c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1615436127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.1615436127
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.2161656909
Short name T466
Test name
Test status
Simulation time 165121356 ps
CPU time 0.77 seconds
Started Jul 23 06:41:49 PM PDT 24
Finished Jul 23 06:41:53 PM PDT 24
Peak memory 206760 kb
Host smart-14d5e196-3f6b-44ea-833d-46e7c90cc713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21616
56909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.2161656909
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.2049281563
Short name T2451
Test name
Test status
Simulation time 159670690 ps
CPU time 0.83 seconds
Started Jul 23 06:41:49 PM PDT 24
Finished Jul 23 06:41:53 PM PDT 24
Peak memory 206752 kb
Host smart-f08c8e31-8ed4-422e-850c-5a94b76570b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20492
81563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.2049281563
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.1111616820
Short name T1565
Test name
Test status
Simulation time 353230587 ps
CPU time 1.18 seconds
Started Jul 23 06:41:47 PM PDT 24
Finished Jul 23 06:41:49 PM PDT 24
Peak memory 206736 kb
Host smart-6c31cee4-94df-4b3b-928c-a2dc526e9c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11116
16820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.1111616820
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.1086739176
Short name T631
Test name
Test status
Simulation time 1003848259 ps
CPU time 2.38 seconds
Started Jul 23 06:41:47 PM PDT 24
Finished Jul 23 06:41:51 PM PDT 24
Peak memory 206892 kb
Host smart-2921ec97-ca8e-4e69-a28f-14d32b5a865f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10867
39176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.1086739176
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.1800702564
Short name T2241
Test name
Test status
Simulation time 22399561994 ps
CPU time 42.98 seconds
Started Jul 23 06:41:48 PM PDT 24
Finished Jul 23 06:42:33 PM PDT 24
Peak memory 206988 kb
Host smart-5a011580-6937-4a37-900d-0b6e8b53a948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18007
02564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.1800702564
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.724484979
Short name T2568
Test name
Test status
Simulation time 456087292 ps
CPU time 1.48 seconds
Started Jul 23 06:41:49 PM PDT 24
Finished Jul 23 06:41:53 PM PDT 24
Peak memory 206760 kb
Host smart-ef0cfce8-ff29-4004-8cc7-0c0d08b62a47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72448
4979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.724484979
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.1973492267
Short name T944
Test name
Test status
Simulation time 161356993 ps
CPU time 0.83 seconds
Started Jul 23 06:41:48 PM PDT 24
Finished Jul 23 06:41:51 PM PDT 24
Peak memory 206760 kb
Host smart-923ee170-9519-4f63-919e-307469bf2ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19734
92267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.1973492267
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.3130265710
Short name T234
Test name
Test status
Simulation time 39324124 ps
CPU time 0.65 seconds
Started Jul 23 06:41:47 PM PDT 24
Finished Jul 23 06:41:50 PM PDT 24
Peak memory 206748 kb
Host smart-87af739e-19af-470f-b985-0fddab83579b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31302
65710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.3130265710
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.2139680984
Short name T709
Test name
Test status
Simulation time 1079709302 ps
CPU time 2.27 seconds
Started Jul 23 06:41:48 PM PDT 24
Finished Jul 23 06:41:54 PM PDT 24
Peak memory 206844 kb
Host smart-99d1707e-f5b1-4b4e-a00b-5984df9a2015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21396
80984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.2139680984
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.3219769714
Short name T2376
Test name
Test status
Simulation time 264375087 ps
CPU time 1.65 seconds
Started Jul 23 06:41:53 PM PDT 24
Finished Jul 23 06:41:57 PM PDT 24
Peak memory 206816 kb
Host smart-4cad0cac-d61e-4eb7-8fa3-6ffe9c01a2d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32197
69714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.3219769714
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.165591587
Short name T627
Test name
Test status
Simulation time 183992024 ps
CPU time 0.81 seconds
Started Jul 23 06:41:53 PM PDT 24
Finished Jul 23 06:41:57 PM PDT 24
Peak memory 206720 kb
Host smart-0b15355e-cfc1-4fc4-bd61-04e40bdcdd22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16559
1587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.165591587
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.2331051283
Short name T566
Test name
Test status
Simulation time 140981958 ps
CPU time 0.76 seconds
Started Jul 23 06:41:53 PM PDT 24
Finished Jul 23 06:41:57 PM PDT 24
Peak memory 206780 kb
Host smart-34d77451-241f-4e53-ba3e-b89ce3be862e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23310
51283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.2331051283
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.2152450335
Short name T983
Test name
Test status
Simulation time 238017920 ps
CPU time 0.94 seconds
Started Jul 23 06:41:53 PM PDT 24
Finished Jul 23 06:41:57 PM PDT 24
Peak memory 206772 kb
Host smart-9f426623-a4fb-450d-9654-f0e914aaf733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21524
50335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.2152450335
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.3856084797
Short name T1681
Test name
Test status
Simulation time 177599135 ps
CPU time 0.82 seconds
Started Jul 23 06:41:55 PM PDT 24
Finished Jul 23 06:41:59 PM PDT 24
Peak memory 206540 kb
Host smart-f1092123-9b7d-4d51-b15c-d94bebe0c4ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38560
84797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.3856084797
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.831053014
Short name T1311
Test name
Test status
Simulation time 23340996923 ps
CPU time 24.8 seconds
Started Jul 23 06:41:55 PM PDT 24
Finished Jul 23 06:42:23 PM PDT 24
Peak memory 206808 kb
Host smart-5fbb2b0d-fbfb-466b-9ec0-cd47a4ca6b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83105
3014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.831053014
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.2240883865
Short name T2186
Test name
Test status
Simulation time 3288451780 ps
CPU time 4.54 seconds
Started Jul 23 06:41:57 PM PDT 24
Finished Jul 23 06:42:04 PM PDT 24
Peak memory 206808 kb
Host smart-13222a10-89cc-465b-b3d0-e4c221e50b5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22408
83865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.2240883865
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.3343986398
Short name T1008
Test name
Test status
Simulation time 8360774539 ps
CPU time 239.67 seconds
Started Jul 23 06:41:55 PM PDT 24
Finished Jul 23 06:45:58 PM PDT 24
Peak memory 206980 kb
Host smart-47d6a5d7-54c8-4543-ae42-746efe5b3055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33439
86398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.3343986398
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.3739996144
Short name T1719
Test name
Test status
Simulation time 3746062387 ps
CPU time 36.15 seconds
Started Jul 23 06:41:56 PM PDT 24
Finished Jul 23 06:42:35 PM PDT 24
Peak memory 206908 kb
Host smart-81157040-5102-49d3-8531-7a7e297fa951
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3739996144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.3739996144
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.3526218961
Short name T1437
Test name
Test status
Simulation time 241782571 ps
CPU time 0.89 seconds
Started Jul 23 06:41:52 PM PDT 24
Finished Jul 23 06:41:56 PM PDT 24
Peak memory 206756 kb
Host smart-f2fe1028-3275-4c17-afeb-2a37833a3a3b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3526218961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.3526218961
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.2029483386
Short name T424
Test name
Test status
Simulation time 194610989 ps
CPU time 0.87 seconds
Started Jul 23 06:42:05 PM PDT 24
Finished Jul 23 06:42:08 PM PDT 24
Peak memory 206752 kb
Host smart-a325a341-b82f-44b1-99ba-d54781d63b68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20294
83386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.2029483386
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.2149165252
Short name T1781
Test name
Test status
Simulation time 5070463481 ps
CPU time 136.43 seconds
Started Jul 23 06:41:57 PM PDT 24
Finished Jul 23 06:44:16 PM PDT 24
Peak memory 206908 kb
Host smart-58f37e5f-0f94-4e55-a4c5-43189b4a3a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21491
65252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.2149165252
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.845369485
Short name T348
Test name
Test status
Simulation time 3082710046 ps
CPU time 27.91 seconds
Started Jul 23 06:42:07 PM PDT 24
Finished Jul 23 06:42:39 PM PDT 24
Peak memory 206896 kb
Host smart-6924202e-4509-461a-adba-3cf839749945
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=845369485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.845369485
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.4270364116
Short name T940
Test name
Test status
Simulation time 144637121 ps
CPU time 0.76 seconds
Started Jul 23 06:41:54 PM PDT 24
Finished Jul 23 06:41:58 PM PDT 24
Peak memory 206760 kb
Host smart-72df310a-9645-411e-b3f1-48ddb39ecae7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4270364116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.4270364116
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.1320267828
Short name T1442
Test name
Test status
Simulation time 168738824 ps
CPU time 0.77 seconds
Started Jul 23 06:41:53 PM PDT 24
Finished Jul 23 06:41:57 PM PDT 24
Peak memory 206748 kb
Host smart-c37df422-b0ef-41d8-bb34-9bab4d410211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13202
67828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.1320267828
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.246073161
Short name T2142
Test name
Test status
Simulation time 195678281 ps
CPU time 0.85 seconds
Started Jul 23 06:42:07 PM PDT 24
Finished Jul 23 06:42:12 PM PDT 24
Peak memory 206756 kb
Host smart-25a5c8f9-ed84-46a7-b74b-5aaf30d686fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24607
3161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.246073161
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.2745370962
Short name T1355
Test name
Test status
Simulation time 258523821 ps
CPU time 0.87 seconds
Started Jul 23 06:41:54 PM PDT 24
Finished Jul 23 06:41:57 PM PDT 24
Peak memory 206668 kb
Host smart-33380fb0-d421-4e8d-a8d6-227e4be1788e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27453
70962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.2745370962
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.716949829
Short name T1840
Test name
Test status
Simulation time 227988247 ps
CPU time 0.93 seconds
Started Jul 23 06:41:54 PM PDT 24
Finished Jul 23 06:41:58 PM PDT 24
Peak memory 206708 kb
Host smart-96b19389-4841-4400-81ba-afb5e73098b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71694
9829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.716949829
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.3360725884
Short name T2560
Test name
Test status
Simulation time 179173565 ps
CPU time 0.84 seconds
Started Jul 23 06:41:54 PM PDT 24
Finished Jul 23 06:41:58 PM PDT 24
Peak memory 206748 kb
Host smart-2a91ed6c-3384-4e2b-aa41-b430d6e2dd89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33607
25884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.3360725884
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.2095318918
Short name T523
Test name
Test status
Simulation time 153572623 ps
CPU time 0.76 seconds
Started Jul 23 06:41:53 PM PDT 24
Finished Jul 23 06:41:57 PM PDT 24
Peak memory 206772 kb
Host smart-e1c9db58-bd9e-45d1-bec7-ca507865ac60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20953
18918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.2095318918
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.1620847397
Short name T1027
Test name
Test status
Simulation time 216820513 ps
CPU time 0.92 seconds
Started Jul 23 06:41:53 PM PDT 24
Finished Jul 23 06:41:56 PM PDT 24
Peak memory 206696 kb
Host smart-c0e010a7-3483-46c1-8ba3-eb2d46eb5938
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1620847397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.1620847397
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.197444746
Short name T583
Test name
Test status
Simulation time 154841272 ps
CPU time 0.83 seconds
Started Jul 23 06:41:53 PM PDT 24
Finished Jul 23 06:41:57 PM PDT 24
Peak memory 206932 kb
Host smart-62bc85cb-6e71-42de-8294-852d636b9622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19744
4746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.197444746
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.633553217
Short name T1170
Test name
Test status
Simulation time 37487392 ps
CPU time 0.68 seconds
Started Jul 23 06:42:07 PM PDT 24
Finished Jul 23 06:42:11 PM PDT 24
Peak memory 206648 kb
Host smart-fb4d7d8e-dc76-44e3-a19c-0f4a1badf4b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63355
3217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.633553217
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.329893681
Short name T89
Test name
Test status
Simulation time 14959804221 ps
CPU time 32.61 seconds
Started Jul 23 06:41:54 PM PDT 24
Finished Jul 23 06:42:30 PM PDT 24
Peak memory 206984 kb
Host smart-e50a1009-ef74-440e-834d-c7147db06a16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32989
3681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.329893681
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.4115731507
Short name T1705
Test name
Test status
Simulation time 167467008 ps
CPU time 0.81 seconds
Started Jul 23 06:41:56 PM PDT 24
Finished Jul 23 06:41:59 PM PDT 24
Peak memory 206768 kb
Host smart-1081f285-faed-4478-a58b-144c22556e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41157
31507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.4115731507
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.3806610826
Short name T1535
Test name
Test status
Simulation time 245648267 ps
CPU time 0.94 seconds
Started Jul 23 06:42:07 PM PDT 24
Finished Jul 23 06:42:12 PM PDT 24
Peak memory 206680 kb
Host smart-b39c554c-6075-47bf-9ff8-cfd83571812d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38066
10826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.3806610826
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.3938954128
Short name T334
Test name
Test status
Simulation time 208650509 ps
CPU time 0.85 seconds
Started Jul 23 06:42:05 PM PDT 24
Finished Jul 23 06:42:08 PM PDT 24
Peak memory 206752 kb
Host smart-365c3885-eccd-44b3-adbf-153890c442b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39389
54128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.3938954128
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.1834313631
Short name T2100
Test name
Test status
Simulation time 149566557 ps
CPU time 0.84 seconds
Started Jul 23 06:41:53 PM PDT 24
Finished Jul 23 06:41:57 PM PDT 24
Peak memory 206752 kb
Host smart-2730f1b9-35d7-467a-b535-0c4ce9ffb4af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18343
13631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.1834313631
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.2726789499
Short name T880
Test name
Test status
Simulation time 175759514 ps
CPU time 0.8 seconds
Started Jul 23 06:41:53 PM PDT 24
Finished Jul 23 06:41:57 PM PDT 24
Peak memory 206764 kb
Host smart-62c57f42-f592-4f5b-8f25-9708451df72a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27267
89499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.2726789499
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.2551238506
Short name T327
Test name
Test status
Simulation time 224340364 ps
CPU time 0.88 seconds
Started Jul 23 06:41:52 PM PDT 24
Finished Jul 23 06:41:56 PM PDT 24
Peak memory 206728 kb
Host smart-bdd7038e-d875-4f21-86da-096823bd1201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25512
38506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.2551238506
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.1957081136
Short name T1514
Test name
Test status
Simulation time 186210133 ps
CPU time 0.85 seconds
Started Jul 23 06:41:54 PM PDT 24
Finished Jul 23 06:41:58 PM PDT 24
Peak memory 206720 kb
Host smart-fbf5ddd2-c6a1-47fe-93d2-ea14f0627912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19570
81136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.1957081136
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.2238823463
Short name T401
Test name
Test status
Simulation time 235638133 ps
CPU time 0.97 seconds
Started Jul 23 06:41:55 PM PDT 24
Finished Jul 23 06:41:59 PM PDT 24
Peak memory 206556 kb
Host smart-d14fe250-5e9e-4ac6-81be-77890e529531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22388
23463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.2238823463
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.1318433374
Short name T2055
Test name
Test status
Simulation time 4447064429 ps
CPU time 29.22 seconds
Started Jul 23 06:42:00 PM PDT 24
Finished Jul 23 06:42:32 PM PDT 24
Peak memory 206732 kb
Host smart-73422b1f-f467-430b-9299-f5cfa10d121b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1318433374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.1318433374
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.393361002
Short name T2472
Test name
Test status
Simulation time 172382745 ps
CPU time 0.85 seconds
Started Jul 23 06:41:59 PM PDT 24
Finished Jul 23 06:42:02 PM PDT 24
Peak memory 206784 kb
Host smart-951f9848-58e8-4f8d-b0b7-90a250b8848f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39336
1002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.393361002
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.1497145126
Short name T351
Test name
Test status
Simulation time 189787060 ps
CPU time 0.86 seconds
Started Jul 23 06:42:01 PM PDT 24
Finished Jul 23 06:42:04 PM PDT 24
Peak memory 206764 kb
Host smart-81780a5f-476a-4c1e-ade4-ca6f5f15e532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14971
45126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.1497145126
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.368336055
Short name T1746
Test name
Test status
Simulation time 815620342 ps
CPU time 1.85 seconds
Started Jul 23 06:42:01 PM PDT 24
Finished Jul 23 06:42:05 PM PDT 24
Peak memory 206916 kb
Host smart-e1817b23-e865-425f-ab57-5194a072188d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36833
6055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.368336055
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.3920378119
Short name T759
Test name
Test status
Simulation time 3488910253 ps
CPU time 95.87 seconds
Started Jul 23 06:42:00 PM PDT 24
Finished Jul 23 06:43:38 PM PDT 24
Peak memory 206892 kb
Host smart-9a9a75bc-ca0a-4e03-b5e0-8852c3ca3af1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39203
78119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.3920378119
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.1372787637
Short name T1323
Test name
Test status
Simulation time 48060301 ps
CPU time 0.68 seconds
Started Jul 23 06:42:11 PM PDT 24
Finished Jul 23 06:42:15 PM PDT 24
Peak memory 206728 kb
Host smart-9777f4ee-8a48-451d-aad8-9670d7b29a76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1372787637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.1372787637
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.845921137
Short name T7
Test name
Test status
Simulation time 3682199627 ps
CPU time 4.2 seconds
Started Jul 23 06:41:59 PM PDT 24
Finished Jul 23 06:42:05 PM PDT 24
Peak memory 206828 kb
Host smart-48fef7ca-5ae5-4ff1-b762-84fe8138475e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=845921137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.845921137
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.40650974
Short name T865
Test name
Test status
Simulation time 13394602905 ps
CPU time 13.07 seconds
Started Jul 23 06:42:00 PM PDT 24
Finished Jul 23 06:42:15 PM PDT 24
Peak memory 206824 kb
Host smart-f946b123-0f46-4992-b06e-876ec3e71f1f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=40650974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.40650974
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.4142057825
Short name T224
Test name
Test status
Simulation time 23382388087 ps
CPU time 22.54 seconds
Started Jul 23 06:42:11 PM PDT 24
Finished Jul 23 06:42:36 PM PDT 24
Peak memory 207080 kb
Host smart-22abdf7f-04d7-41c1-b0f6-06470cbf4ea5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4142057825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.4142057825
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.2246350646
Short name T486
Test name
Test status
Simulation time 188252270 ps
CPU time 0.83 seconds
Started Jul 23 06:42:00 PM PDT 24
Finished Jul 23 06:42:03 PM PDT 24
Peak memory 206784 kb
Host smart-364eebde-eb3b-4166-a5b8-1f33b7dac8e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22463
50646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2246350646
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.2857370296
Short name T824
Test name
Test status
Simulation time 150199386 ps
CPU time 0.76 seconds
Started Jul 23 06:42:03 PM PDT 24
Finished Jul 23 06:42:05 PM PDT 24
Peak memory 206880 kb
Host smart-efb201d3-c05e-4f18-957b-503e1c16661d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28573
70296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.2857370296
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.1115238967
Short name T108
Test name
Test status
Simulation time 549861673 ps
CPU time 1.69 seconds
Started Jul 23 06:42:00 PM PDT 24
Finished Jul 23 06:42:05 PM PDT 24
Peak memory 206888 kb
Host smart-c246e42a-9bcf-4eee-9948-b68816ba3a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11152
38967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.1115238967
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.4290443740
Short name T899
Test name
Test status
Simulation time 599406589 ps
CPU time 1.63 seconds
Started Jul 23 06:42:01 PM PDT 24
Finished Jul 23 06:42:05 PM PDT 24
Peak memory 206656 kb
Host smart-c4dfcfbc-ba79-40a6-95dd-c30e28c6fd97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42904
43740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.4290443740
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.1553259083
Short name T1830
Test name
Test status
Simulation time 23276813881 ps
CPU time 44.34 seconds
Started Jul 23 06:41:59 PM PDT 24
Finished Jul 23 06:42:45 PM PDT 24
Peak memory 206960 kb
Host smart-dfda0f59-ae27-40e6-a8e0-fbbd97c9cda9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15532
59083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.1553259083
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.2429462492
Short name T2300
Test name
Test status
Simulation time 484786079 ps
CPU time 1.38 seconds
Started Jul 23 06:42:00 PM PDT 24
Finished Jul 23 06:42:04 PM PDT 24
Peak memory 206756 kb
Host smart-d13f1133-100d-4270-9d4c-33b9a1a514b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24294
62492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.2429462492
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.3903515659
Short name T2120
Test name
Test status
Simulation time 173633313 ps
CPU time 0.77 seconds
Started Jul 23 06:42:03 PM PDT 24
Finished Jul 23 06:42:05 PM PDT 24
Peak memory 206880 kb
Host smart-85233b81-370f-48df-9a55-b62f82e216d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39035
15659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.3903515659
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.1723037340
Short name T1299
Test name
Test status
Simulation time 64008344 ps
CPU time 0.68 seconds
Started Jul 23 06:42:07 PM PDT 24
Finished Jul 23 06:42:11 PM PDT 24
Peak memory 206740 kb
Host smart-ad422d72-7b9c-43c7-a515-67409b8515ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17230
37340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.1723037340
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.1948967546
Short name T685
Test name
Test status
Simulation time 880095859 ps
CPU time 2.02 seconds
Started Jul 23 06:42:00 PM PDT 24
Finished Jul 23 06:42:05 PM PDT 24
Peak memory 206624 kb
Host smart-a5a61196-a0a4-4240-a539-ca950c5d5b14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19489
67546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.1948967546
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.1533277463
Short name T1996
Test name
Test status
Simulation time 336456842 ps
CPU time 2.03 seconds
Started Jul 23 06:42:00 PM PDT 24
Finished Jul 23 06:42:05 PM PDT 24
Peak memory 206576 kb
Host smart-6455a852-910e-4901-9d3f-3c90c135b0d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15332
77463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.1533277463
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.1997481893
Short name T2731
Test name
Test status
Simulation time 223970729 ps
CPU time 0.85 seconds
Started Jul 23 06:42:00 PM PDT 24
Finished Jul 23 06:42:03 PM PDT 24
Peak memory 206736 kb
Host smart-8092d346-f11f-464b-a4a3-c49c4135a78e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19974
81893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.1997481893
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.1496032108
Short name T2535
Test name
Test status
Simulation time 138336395 ps
CPU time 0.76 seconds
Started Jul 23 06:42:00 PM PDT 24
Finished Jul 23 06:42:03 PM PDT 24
Peak memory 206764 kb
Host smart-7ca59e94-a4bd-4f92-82da-55164a0ad8e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14960
32108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.1496032108
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.2087780169
Short name T1785
Test name
Test status
Simulation time 230860221 ps
CPU time 0.88 seconds
Started Jul 23 06:42:03 PM PDT 24
Finished Jul 23 06:42:05 PM PDT 24
Peak memory 206884 kb
Host smart-ffbc13cc-4865-4e66-af71-dea4af3d1c59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20877
80169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.2087780169
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_iso_retraction.3926547356
Short name T2729
Test name
Test status
Simulation time 4923938740 ps
CPU time 36.03 seconds
Started Jul 23 06:42:00 PM PDT 24
Finished Jul 23 06:42:38 PM PDT 24
Peak memory 206952 kb
Host smart-ea6f7fa7-d15a-481a-a1f2-d3ccf4c6226b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39265
47356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_iso_retraction.3926547356
Directory /workspace/21.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.79564819
Short name T1580
Test name
Test status
Simulation time 203867389 ps
CPU time 0.88 seconds
Started Jul 23 06:42:09 PM PDT 24
Finished Jul 23 06:42:14 PM PDT 24
Peak memory 206736 kb
Host smart-565668e0-f276-471f-98e4-8097acf0d651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79564
819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.79564819
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.357303682
Short name T645
Test name
Test status
Simulation time 23342925827 ps
CPU time 26.56 seconds
Started Jul 23 06:42:00 PM PDT 24
Finished Jul 23 06:42:29 PM PDT 24
Peak memory 206812 kb
Host smart-05d0e4bc-8dc6-4d8b-8e6e-c60d169eb9d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35730
3682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.357303682
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.914278149
Short name T2006
Test name
Test status
Simulation time 3257847832 ps
CPU time 3.94 seconds
Started Jul 23 06:42:00 PM PDT 24
Finished Jul 23 06:42:07 PM PDT 24
Peak memory 206816 kb
Host smart-9469c580-944a-41f4-a314-628b6df9fe2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91427
8149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.914278149
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.1137746966
Short name T2561
Test name
Test status
Simulation time 9347927004 ps
CPU time 251.31 seconds
Started Jul 23 06:42:00 PM PDT 24
Finished Jul 23 06:46:14 PM PDT 24
Peak memory 206952 kb
Host smart-b85f2d36-cc32-46ae-9280-6ed2fc7f2e4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11377
46966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.1137746966
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.31623954
Short name T1166
Test name
Test status
Simulation time 5196679959 ps
CPU time 139.5 seconds
Started Jul 23 06:42:00 PM PDT 24
Finished Jul 23 06:44:21 PM PDT 24
Peak memory 206904 kb
Host smart-d1c40fce-3a39-4733-80db-84fa55556363
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=31623954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.31623954
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.1612799033
Short name T1909
Test name
Test status
Simulation time 250696339 ps
CPU time 0.99 seconds
Started Jul 23 06:41:58 PM PDT 24
Finished Jul 23 06:42:01 PM PDT 24
Peak memory 206708 kb
Host smart-4a539f57-a785-4f54-83a7-5eecaf435317
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1612799033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.1612799033
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.2500580650
Short name T896
Test name
Test status
Simulation time 188460519 ps
CPU time 0.89 seconds
Started Jul 23 06:42:07 PM PDT 24
Finished Jul 23 06:42:11 PM PDT 24
Peak memory 206748 kb
Host smart-12c55e14-1aba-405d-b077-8b72e265c270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25005
80650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.2500580650
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.2027549629
Short name T826
Test name
Test status
Simulation time 4454448208 ps
CPU time 119.57 seconds
Started Jul 23 06:42:08 PM PDT 24
Finished Jul 23 06:44:11 PM PDT 24
Peak memory 206944 kb
Host smart-743460ca-c425-4a92-aae6-fa4547487dd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20275
49629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.2027549629
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.329579827
Short name T532
Test name
Test status
Simulation time 5963795386 ps
CPU time 56.62 seconds
Started Jul 23 06:42:11 PM PDT 24
Finished Jul 23 06:43:11 PM PDT 24
Peak memory 206912 kb
Host smart-b9e88bf5-327f-4de4-9ff1-54d6acb9585d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=329579827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.329579827
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.2183466528
Short name T1010
Test name
Test status
Simulation time 156372226 ps
CPU time 0.82 seconds
Started Jul 23 06:42:05 PM PDT 24
Finished Jul 23 06:42:09 PM PDT 24
Peak memory 206772 kb
Host smart-f1d723d2-5bf7-43ba-8ae1-094ce004e99b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2183466528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.2183466528
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.576950190
Short name T2424
Test name
Test status
Simulation time 145291881 ps
CPU time 0.79 seconds
Started Jul 23 06:42:06 PM PDT 24
Finished Jul 23 06:42:09 PM PDT 24
Peak memory 206768 kb
Host smart-ec6901cd-b9ed-40c0-9b37-684886229288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57695
0190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.576950190
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.1217933544
Short name T1911
Test name
Test status
Simulation time 219500585 ps
CPU time 0.88 seconds
Started Jul 23 06:42:07 PM PDT 24
Finished Jul 23 06:42:11 PM PDT 24
Peak memory 206772 kb
Host smart-e4c5f574-def2-4d6b-904d-0e5e136e4f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12179
33544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.1217933544
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.2605401198
Short name T2536
Test name
Test status
Simulation time 157826698 ps
CPU time 0.79 seconds
Started Jul 23 06:42:05 PM PDT 24
Finished Jul 23 06:42:08 PM PDT 24
Peak memory 206752 kb
Host smart-80b63f5c-c83d-40ef-a60c-121d88794e7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26054
01198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.2605401198
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.124500193
Short name T1755
Test name
Test status
Simulation time 191008955 ps
CPU time 0.84 seconds
Started Jul 23 06:42:04 PM PDT 24
Finished Jul 23 06:42:07 PM PDT 24
Peak memory 206744 kb
Host smart-acfadb94-8b27-41e7-bfc6-9efc16de390b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12450
0193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.124500193
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.1754887342
Short name T573
Test name
Test status
Simulation time 211184439 ps
CPU time 0.82 seconds
Started Jul 23 06:42:05 PM PDT 24
Finished Jul 23 06:42:08 PM PDT 24
Peak memory 206768 kb
Host smart-2f9574a2-1500-469d-bf57-69e759f1aea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17548
87342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.1754887342
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.2947001192
Short name T1594
Test name
Test status
Simulation time 146828139 ps
CPU time 0.79 seconds
Started Jul 23 06:42:06 PM PDT 24
Finished Jul 23 06:42:11 PM PDT 24
Peak memory 206748 kb
Host smart-f03e4f47-e912-46b4-a988-757a95ecf90b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29470
01192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.2947001192
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.3535722731
Short name T1432
Test name
Test status
Simulation time 232787391 ps
CPU time 1 seconds
Started Jul 23 06:42:05 PM PDT 24
Finished Jul 23 06:42:08 PM PDT 24
Peak memory 206796 kb
Host smart-eb9d5ad7-ccbf-44dc-8157-fdd2404bd422
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3535722731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.3535722731
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.120321185
Short name T722
Test name
Test status
Simulation time 145450105 ps
CPU time 0.73 seconds
Started Jul 23 06:42:08 PM PDT 24
Finished Jul 23 06:42:12 PM PDT 24
Peak memory 206732 kb
Host smart-a4822384-f2bb-42d4-a407-eee86d2ae4ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12032
1185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.120321185
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.2153924616
Short name T1648
Test name
Test status
Simulation time 37022068 ps
CPU time 0.66 seconds
Started Jul 23 06:42:11 PM PDT 24
Finished Jul 23 06:42:15 PM PDT 24
Peak memory 206748 kb
Host smart-b35fa0d4-561b-46e0-be4f-22d12a025186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21539
24616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.2153924616
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.373685999
Short name T2651
Test name
Test status
Simulation time 17719181558 ps
CPU time 40.7 seconds
Started Jul 23 06:42:05 PM PDT 24
Finished Jul 23 06:42:47 PM PDT 24
Peak memory 206984 kb
Host smart-f9330760-ca72-4824-9e4e-24254c11b9fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37368
5999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.373685999
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.112449735
Short name T2743
Test name
Test status
Simulation time 173565233 ps
CPU time 0.85 seconds
Started Jul 23 06:42:05 PM PDT 24
Finished Jul 23 06:42:09 PM PDT 24
Peak memory 206648 kb
Host smart-1b8da15c-4978-4456-b480-d572faef03ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11244
9735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.112449735
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.778230054
Short name T402
Test name
Test status
Simulation time 235786988 ps
CPU time 0.91 seconds
Started Jul 23 06:42:06 PM PDT 24
Finished Jul 23 06:42:10 PM PDT 24
Peak memory 206772 kb
Host smart-9d4d0521-6b42-4a57-80e6-d3d992fea93f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77823
0054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.778230054
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.3530128562
Short name T2101
Test name
Test status
Simulation time 290932007 ps
CPU time 1 seconds
Started Jul 23 06:42:10 PM PDT 24
Finished Jul 23 06:42:14 PM PDT 24
Peak memory 206716 kb
Host smart-49e5074d-c1f1-487d-9fab-6f47e5be4960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35301
28562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.3530128562
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.3640338168
Short name T888
Test name
Test status
Simulation time 205386590 ps
CPU time 0.92 seconds
Started Jul 23 06:42:05 PM PDT 24
Finished Jul 23 06:42:08 PM PDT 24
Peak memory 206740 kb
Host smart-aa9f3f71-561b-4088-88fa-40ad40dd240e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36403
38168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.3640338168
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.603416188
Short name T2062
Test name
Test status
Simulation time 208798999 ps
CPU time 0.86 seconds
Started Jul 23 06:42:11 PM PDT 24
Finished Jul 23 06:42:16 PM PDT 24
Peak memory 206728 kb
Host smart-ed9373f3-b7b4-438a-9c8b-a451966155d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60341
6188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.603416188
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.920669710
Short name T160
Test name
Test status
Simulation time 170348122 ps
CPU time 0.8 seconds
Started Jul 23 06:42:05 PM PDT 24
Finished Jul 23 06:42:09 PM PDT 24
Peak memory 206708 kb
Host smart-0a23ba53-7834-47c1-9d97-278c484ed064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92066
9710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.920669710
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.3873014499
Short name T1228
Test name
Test status
Simulation time 142911730 ps
CPU time 0.74 seconds
Started Jul 23 06:42:05 PM PDT 24
Finished Jul 23 06:42:08 PM PDT 24
Peak memory 206728 kb
Host smart-9a1e8404-c3e9-4aaf-ba48-b489d734c965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38730
14499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.3873014499
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.3468877046
Short name T879
Test name
Test status
Simulation time 257261087 ps
CPU time 1.03 seconds
Started Jul 23 06:42:06 PM PDT 24
Finished Jul 23 06:42:11 PM PDT 24
Peak memory 206732 kb
Host smart-022f8bd9-c355-43a2-a9fb-0d23b2c5964f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34688
77046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.3468877046
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.2410884450
Short name T2640
Test name
Test status
Simulation time 5174579870 ps
CPU time 45.76 seconds
Started Jul 23 06:42:06 PM PDT 24
Finished Jul 23 06:42:54 PM PDT 24
Peak memory 206932 kb
Host smart-0a7e867a-b026-4e2c-8bf4-b88fc639a8d1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2410884450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.2410884450
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.1600502423
Short name T1380
Test name
Test status
Simulation time 167232748 ps
CPU time 0.82 seconds
Started Jul 23 06:42:06 PM PDT 24
Finished Jul 23 06:42:10 PM PDT 24
Peak memory 206736 kb
Host smart-522bcd1d-925b-4927-8237-d2edc6decac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16005
02423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.1600502423
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.3717771050
Short name T1124
Test name
Test status
Simulation time 208395915 ps
CPU time 0.78 seconds
Started Jul 23 06:42:07 PM PDT 24
Finished Jul 23 06:42:11 PM PDT 24
Peak memory 206752 kb
Host smart-c027153b-d3cd-45d6-89d1-07d22a0a7417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37177
71050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.3717771050
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.75199905
Short name T1093
Test name
Test status
Simulation time 1268541099 ps
CPU time 2.66 seconds
Started Jul 23 06:42:06 PM PDT 24
Finished Jul 23 06:42:11 PM PDT 24
Peak memory 207084 kb
Host smart-839d18dd-e672-4489-b47b-02dd74518125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75199
905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.75199905
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.888729019
Short name T1835
Test name
Test status
Simulation time 5002529961 ps
CPU time 34.71 seconds
Started Jul 23 06:42:09 PM PDT 24
Finished Jul 23 06:42:47 PM PDT 24
Peak memory 206964 kb
Host smart-e6dc69c8-e945-4cd1-8034-ea0bc4b84d64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88872
9019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.888729019
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.2707502859
Short name T329
Test name
Test status
Simulation time 42796786 ps
CPU time 0.69 seconds
Started Jul 23 06:42:19 PM PDT 24
Finished Jul 23 06:42:23 PM PDT 24
Peak memory 206744 kb
Host smart-38b59592-9d5d-4793-9f82-749f28ec354d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2707502859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.2707502859
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.101930918
Short name T1211
Test name
Test status
Simulation time 3572624069 ps
CPU time 4.74 seconds
Started Jul 23 06:42:08 PM PDT 24
Finished Jul 23 06:42:16 PM PDT 24
Peak memory 206888 kb
Host smart-c1435916-150d-4223-8f96-849d55889751
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=101930918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.101930918
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.1562352024
Short name T1544
Test name
Test status
Simulation time 13410165721 ps
CPU time 12.47 seconds
Started Jul 23 06:42:06 PM PDT 24
Finished Jul 23 06:42:22 PM PDT 24
Peak memory 206896 kb
Host smart-f774e00e-079d-4c32-81c7-7f6494f95e87
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1562352024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.1562352024
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.2654165772
Short name T536
Test name
Test status
Simulation time 23378802959 ps
CPU time 23.62 seconds
Started Jul 23 06:42:07 PM PDT 24
Finished Jul 23 06:42:34 PM PDT 24
Peak memory 206836 kb
Host smart-4bf263b5-44e1-4a4d-9e59-cd00d56f951a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2654165772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.2654165772
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.3925635996
Short name T2533
Test name
Test status
Simulation time 184104746 ps
CPU time 0.82 seconds
Started Jul 23 06:42:06 PM PDT 24
Finished Jul 23 06:42:10 PM PDT 24
Peak memory 206748 kb
Host smart-9cbfa314-b472-40fa-a9a3-50dfdc5ca968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39256
35996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.3925635996
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.1261735805
Short name T2272
Test name
Test status
Simulation time 149245532 ps
CPU time 0.79 seconds
Started Jul 23 06:42:05 PM PDT 24
Finished Jul 23 06:42:09 PM PDT 24
Peak memory 206748 kb
Host smart-b2dd6669-9e63-42c9-ab59-6b9432e904ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12617
35805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.1261735805
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.1990662925
Short name T1509
Test name
Test status
Simulation time 477888537 ps
CPU time 1.5 seconds
Started Jul 23 06:42:08 PM PDT 24
Finished Jul 23 06:42:13 PM PDT 24
Peak memory 206900 kb
Host smart-a12fc5d3-b295-4c01-8142-5c1460961415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19906
62925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.1990662925
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.2926371007
Short name T2724
Test name
Test status
Simulation time 1509073398 ps
CPU time 3.08 seconds
Started Jul 23 06:42:06 PM PDT 24
Finished Jul 23 06:42:13 PM PDT 24
Peak memory 206864 kb
Host smart-ffd76185-b7fd-4bea-82a2-4fc25a33c396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29263
71007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.2926371007
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.3014727106
Short name T1881
Test name
Test status
Simulation time 10798876399 ps
CPU time 23.92 seconds
Started Jul 23 06:42:08 PM PDT 24
Finished Jul 23 06:42:35 PM PDT 24
Peak memory 206944 kb
Host smart-f05a80dd-fcf0-449c-b8bd-a9f7ec3f8309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30147
27106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.3014727106
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.2703493724
Short name T1325
Test name
Test status
Simulation time 496639994 ps
CPU time 1.36 seconds
Started Jul 23 06:42:11 PM PDT 24
Finished Jul 23 06:42:16 PM PDT 24
Peak memory 206748 kb
Host smart-75637cc8-37bd-4e84-83d1-0414f280c576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27034
93724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.2703493724
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.1352063087
Short name T2531
Test name
Test status
Simulation time 193074023 ps
CPU time 0.8 seconds
Started Jul 23 06:42:07 PM PDT 24
Finished Jul 23 06:42:11 PM PDT 24
Peak memory 206772 kb
Host smart-bf2b2ac1-e7c7-4a73-a6f6-c457e9e597a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13520
63087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.1352063087
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.872428602
Short name T2147
Test name
Test status
Simulation time 66766114 ps
CPU time 0.66 seconds
Started Jul 23 06:42:15 PM PDT 24
Finished Jul 23 06:42:18 PM PDT 24
Peak memory 206740 kb
Host smart-d9c82935-2291-40ef-9a3c-ae87efe5868f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87242
8602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.872428602
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.2756232768
Short name T1904
Test name
Test status
Simulation time 889229552 ps
CPU time 2.04 seconds
Started Jul 23 06:42:11 PM PDT 24
Finished Jul 23 06:42:17 PM PDT 24
Peak memory 206880 kb
Host smart-089938e7-d46e-4ce3-9922-ba0eef9c8e21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27562
32768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.2756232768
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.661061663
Short name T2119
Test name
Test status
Simulation time 244182889 ps
CPU time 1.59 seconds
Started Jul 23 06:42:13 PM PDT 24
Finished Jul 23 06:42:18 PM PDT 24
Peak memory 206808 kb
Host smart-6da32f28-74d0-4ed3-8dd3-af492edeb10b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66106
1663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.661061663
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.1707398575
Short name T1495
Test name
Test status
Simulation time 214567208 ps
CPU time 0.94 seconds
Started Jul 23 06:42:10 PM PDT 24
Finished Jul 23 06:42:14 PM PDT 24
Peak memory 206732 kb
Host smart-c644a83e-a4a5-4bd3-b731-840380514c9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17073
98575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.1707398575
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.52080706
Short name T972
Test name
Test status
Simulation time 144783704 ps
CPU time 0.76 seconds
Started Jul 23 06:42:12 PM PDT 24
Finished Jul 23 06:42:16 PM PDT 24
Peak memory 206756 kb
Host smart-b9c56f2b-f23a-497d-86e9-b075bb6b6f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52080
706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.52080706
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.1678081806
Short name T322
Test name
Test status
Simulation time 209785701 ps
CPU time 0.95 seconds
Started Jul 23 06:42:15 PM PDT 24
Finished Jul 23 06:42:18 PM PDT 24
Peak memory 206768 kb
Host smart-a709c111-9897-4bad-b0de-ff6c0fcc08b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16780
81806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.1678081806
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.645242167
Short name T2190
Test name
Test status
Simulation time 7410047934 ps
CPU time 205.94 seconds
Started Jul 23 06:42:11 PM PDT 24
Finished Jul 23 06:45:41 PM PDT 24
Peak memory 206848 kb
Host smart-e82a3c05-10d8-48e9-97e4-4073de69446b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=645242167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.645242167
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_iso_retraction.3410476236
Short name T1971
Test name
Test status
Simulation time 14195499326 ps
CPU time 45.8 seconds
Started Jul 23 06:42:11 PM PDT 24
Finished Jul 23 06:43:01 PM PDT 24
Peak memory 206988 kb
Host smart-44e74cb8-6a80-4433-be2d-071d9f9037b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34104
76236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.3410476236
Directory /workspace/22.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.3231480821
Short name T372
Test name
Test status
Simulation time 175641021 ps
CPU time 0.81 seconds
Started Jul 23 06:42:12 PM PDT 24
Finished Jul 23 06:42:16 PM PDT 24
Peak memory 206744 kb
Host smart-720939a7-0e0d-4752-91cb-ab6b214a86d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32314
80821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.3231480821
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.1694300793
Short name T629
Test name
Test status
Simulation time 23331995120 ps
CPU time 24.63 seconds
Started Jul 23 06:42:13 PM PDT 24
Finished Jul 23 06:42:41 PM PDT 24
Peak memory 206832 kb
Host smart-c3103a7e-d871-4a70-b4e6-b30dee9105ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16943
00793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.1694300793
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.962992707
Short name T2542
Test name
Test status
Simulation time 3295404613 ps
CPU time 4.83 seconds
Started Jul 23 06:42:13 PM PDT 24
Finished Jul 23 06:42:21 PM PDT 24
Peak memory 206812 kb
Host smart-483df141-cdfe-4ed9-bdfa-0efa8a8583b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96299
2707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.962992707
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.189387807
Short name T1735
Test name
Test status
Simulation time 12467282907 ps
CPU time 352.99 seconds
Started Jul 23 06:42:11 PM PDT 24
Finished Jul 23 06:48:08 PM PDT 24
Peak memory 206900 kb
Host smart-dfd5f8d9-9451-4078-94df-55f962553f86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18938
7807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.189387807
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.2094471299
Short name T450
Test name
Test status
Simulation time 3937472370 ps
CPU time 110.91 seconds
Started Jul 23 06:42:13 PM PDT 24
Finished Jul 23 06:44:07 PM PDT 24
Peak memory 206944 kb
Host smart-66c449d2-3fe8-4e05-9e2b-a8943c841e26
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2094471299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.2094471299
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.1191161006
Short name T355
Test name
Test status
Simulation time 271583006 ps
CPU time 0.92 seconds
Started Jul 23 06:42:14 PM PDT 24
Finished Jul 23 06:42:18 PM PDT 24
Peak memory 206752 kb
Host smart-00f97c4d-a984-4e59-84f1-50e0f810ad33
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1191161006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.1191161006
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.670152583
Short name T1569
Test name
Test status
Simulation time 197426463 ps
CPU time 0.87 seconds
Started Jul 23 06:42:11 PM PDT 24
Finished Jul 23 06:42:15 PM PDT 24
Peak memory 206656 kb
Host smart-51c51783-1a55-49af-8a37-f1bc04548f67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67015
2583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.670152583
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.1001256245
Short name T2061
Test name
Test status
Simulation time 5451295166 ps
CPU time 39.2 seconds
Started Jul 23 06:42:11 PM PDT 24
Finished Jul 23 06:42:54 PM PDT 24
Peak memory 206904 kb
Host smart-ad492073-16f4-42cc-996d-ac1fcd9ee104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10012
56245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.1001256245
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.904949686
Short name T1171
Test name
Test status
Simulation time 6074195243 ps
CPU time 43.46 seconds
Started Jul 23 06:42:11 PM PDT 24
Finished Jul 23 06:42:59 PM PDT 24
Peak memory 206984 kb
Host smart-defa7020-1035-4993-91ad-2201dcfb7126
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=904949686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.904949686
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.1992547903
Short name T2657
Test name
Test status
Simulation time 149270790 ps
CPU time 0.79 seconds
Started Jul 23 06:42:13 PM PDT 24
Finished Jul 23 06:42:17 PM PDT 24
Peak memory 206668 kb
Host smart-7a4c5a63-93ac-44df-82be-94375652f610
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1992547903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.1992547903
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.742323887
Short name T1653
Test name
Test status
Simulation time 135410590 ps
CPU time 0.82 seconds
Started Jul 23 06:42:11 PM PDT 24
Finished Jul 23 06:42:15 PM PDT 24
Peak memory 206692 kb
Host smart-49a559db-ae59-4e9a-a64d-0cde8739e6d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74232
3887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.742323887
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.3779865567
Short name T142
Test name
Test status
Simulation time 220954782 ps
CPU time 0.89 seconds
Started Jul 23 06:42:11 PM PDT 24
Finished Jul 23 06:42:15 PM PDT 24
Peak memory 206772 kb
Host smart-85a09352-957b-4249-ae8a-347a7589de5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37798
65567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.3779865567
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.2054878303
Short name T883
Test name
Test status
Simulation time 170114084 ps
CPU time 0.88 seconds
Started Jul 23 06:42:13 PM PDT 24
Finished Jul 23 06:42:18 PM PDT 24
Peak memory 206768 kb
Host smart-414d2025-214f-4ac9-bf35-268abce0f484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20548
78303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.2054878303
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.3255986139
Short name T24
Test name
Test status
Simulation time 207123740 ps
CPU time 0.88 seconds
Started Jul 23 06:42:12 PM PDT 24
Finished Jul 23 06:42:17 PM PDT 24
Peak memory 206704 kb
Host smart-0b426709-4f7c-418b-9d53-bc29abc1a0ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32559
86139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.3255986139
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.852972278
Short name T2493
Test name
Test status
Simulation time 174106659 ps
CPU time 0.79 seconds
Started Jul 23 06:42:11 PM PDT 24
Finished Jul 23 06:42:14 PM PDT 24
Peak memory 206728 kb
Host smart-282b7f64-fb1d-42c0-abc0-8e8fb6a5df79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85297
2278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.852972278
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.2129745603
Short name T1555
Test name
Test status
Simulation time 152172232 ps
CPU time 0.78 seconds
Started Jul 23 06:42:12 PM PDT 24
Finished Jul 23 06:42:16 PM PDT 24
Peak memory 206760 kb
Host smart-fedea4da-4cd3-494f-a981-1ef70ea1aa1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21297
45603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.2129745603
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.3730710442
Short name T1647
Test name
Test status
Simulation time 217405984 ps
CPU time 0.94 seconds
Started Jul 23 06:42:13 PM PDT 24
Finished Jul 23 06:42:17 PM PDT 24
Peak memory 206752 kb
Host smart-fbaba869-5cc1-40a2-9579-5964ba4ce123
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3730710442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.3730710442
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.3272140939
Short name T893
Test name
Test status
Simulation time 153286577 ps
CPU time 0.77 seconds
Started Jul 23 06:42:18 PM PDT 24
Finished Jul 23 06:42:20 PM PDT 24
Peak memory 206768 kb
Host smart-01fea77a-83e3-4f3b-9f2d-862ecfb67c4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32721
40939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.3272140939
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.1279386968
Short name T25
Test name
Test status
Simulation time 43327226 ps
CPU time 0.68 seconds
Started Jul 23 06:42:19 PM PDT 24
Finished Jul 23 06:42:21 PM PDT 24
Peak memory 206728 kb
Host smart-b6dff511-c95a-4229-a9d2-1ef53e47715d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12793
86968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.1279386968
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.2059877185
Short name T1552
Test name
Test status
Simulation time 17079505024 ps
CPU time 37.98 seconds
Started Jul 23 06:42:18 PM PDT 24
Finished Jul 23 06:42:57 PM PDT 24
Peak memory 206988 kb
Host smart-248d96d4-b42d-4e4f-bd43-95f52433eae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20598
77185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.2059877185
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.959481110
Short name T2249
Test name
Test status
Simulation time 176412910 ps
CPU time 0.88 seconds
Started Jul 23 06:42:20 PM PDT 24
Finished Jul 23 06:42:25 PM PDT 24
Peak memory 206776 kb
Host smart-ef59865e-1d13-4869-8433-f2409348f5c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95948
1110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.959481110
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.684357797
Short name T1703
Test name
Test status
Simulation time 254146198 ps
CPU time 0.9 seconds
Started Jul 23 06:42:16 PM PDT 24
Finished Jul 23 06:42:19 PM PDT 24
Peak memory 206756 kb
Host smart-b9bac2a5-571d-4f0b-b535-a2d13a1d6065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68435
7797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.684357797
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.635249976
Short name T2661
Test name
Test status
Simulation time 329536851 ps
CPU time 1.02 seconds
Started Jul 23 06:42:17 PM PDT 24
Finished Jul 23 06:42:20 PM PDT 24
Peak memory 206760 kb
Host smart-01705eb0-3076-4568-bda9-af21315afb36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63524
9976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.635249976
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.3750641045
Short name T304
Test name
Test status
Simulation time 215799681 ps
CPU time 0.83 seconds
Started Jul 23 06:42:17 PM PDT 24
Finished Jul 23 06:42:20 PM PDT 24
Peak memory 206736 kb
Host smart-332700f9-d3fd-4bec-8994-f5204d8ab384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37506
41045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.3750641045
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.237339714
Short name T2487
Test name
Test status
Simulation time 142767584 ps
CPU time 0.77 seconds
Started Jul 23 06:42:19 PM PDT 24
Finished Jul 23 06:42:23 PM PDT 24
Peak memory 206720 kb
Host smart-bae2a3c1-cfb9-4798-a8b3-e2b545172a5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23733
9714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.237339714
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.2231491005
Short name T1798
Test name
Test status
Simulation time 180328021 ps
CPU time 0.83 seconds
Started Jul 23 06:42:19 PM PDT 24
Finished Jul 23 06:42:23 PM PDT 24
Peak memory 206756 kb
Host smart-29c4ff7a-b8b4-4f08-812d-babf6378dcfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22314
91005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.2231491005
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.588247446
Short name T2506
Test name
Test status
Simulation time 160843172 ps
CPU time 0.78 seconds
Started Jul 23 06:42:19 PM PDT 24
Finished Jul 23 06:42:22 PM PDT 24
Peak memory 206776 kb
Host smart-5171e6d0-c560-4fb9-a7d9-c356b12e3b3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58824
7446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.588247446
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.1864475098
Short name T1595
Test name
Test status
Simulation time 213271489 ps
CPU time 0.88 seconds
Started Jul 23 06:42:18 PM PDT 24
Finished Jul 23 06:42:20 PM PDT 24
Peak memory 206712 kb
Host smart-22a7a9ac-0430-44a9-9069-9517a62aa33b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18644
75098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.1864475098
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.3219361500
Short name T2195
Test name
Test status
Simulation time 3752392246 ps
CPU time 107.6 seconds
Started Jul 23 06:42:19 PM PDT 24
Finished Jul 23 06:44:10 PM PDT 24
Peak memory 206844 kb
Host smart-0e52ba79-f9ed-40d5-9060-67f37792a03c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3219361500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.3219361500
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.998608046
Short name T1763
Test name
Test status
Simulation time 164024216 ps
CPU time 0.9 seconds
Started Jul 23 06:42:17 PM PDT 24
Finished Jul 23 06:42:20 PM PDT 24
Peak memory 206764 kb
Host smart-3a0de976-3c21-4986-8f01-bfe331853fd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99860
8046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.998608046
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.2136079142
Short name T1281
Test name
Test status
Simulation time 171018826 ps
CPU time 0.82 seconds
Started Jul 23 06:42:20 PM PDT 24
Finished Jul 23 06:42:23 PM PDT 24
Peak memory 206752 kb
Host smart-bcd17070-6a70-4d14-8adf-e94e0832af67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21360
79142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.2136079142
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.4290033300
Short name T823
Test name
Test status
Simulation time 825543554 ps
CPU time 1.89 seconds
Started Jul 23 06:42:17 PM PDT 24
Finished Jul 23 06:42:21 PM PDT 24
Peak memory 206900 kb
Host smart-971f13a8-98d3-4fb0-b8d5-ccf97a859452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42900
33300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.4290033300
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.2575169581
Short name T668
Test name
Test status
Simulation time 4243258103 ps
CPU time 29.15 seconds
Started Jul 23 06:42:20 PM PDT 24
Finished Jul 23 06:42:53 PM PDT 24
Peak memory 206964 kb
Host smart-59a8e091-ddc6-4ff5-b634-cb8dbddc9545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25751
69581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.2575169581
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.2164607520
Short name T179
Test name
Test status
Simulation time 50348188 ps
CPU time 0.7 seconds
Started Jul 23 06:42:35 PM PDT 24
Finished Jul 23 06:42:37 PM PDT 24
Peak memory 206724 kb
Host smart-396edee2-f975-4704-a936-da852b56c44d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2164607520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.2164607520
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.2502490986
Short name T454
Test name
Test status
Simulation time 3729176513 ps
CPU time 4.19 seconds
Started Jul 23 06:42:21 PM PDT 24
Finished Jul 23 06:42:28 PM PDT 24
Peak memory 206824 kb
Host smart-8d36d320-1bc0-4e97-9a05-74015c79d7b5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2502490986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.2502490986
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.3628651529
Short name T997
Test name
Test status
Simulation time 13381554913 ps
CPU time 12.3 seconds
Started Jul 23 06:42:19 PM PDT 24
Finished Jul 23 06:42:34 PM PDT 24
Peak memory 206928 kb
Host smart-132d38d0-37d3-4c22-9677-5da22f6e29fd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3628651529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.3628651529
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.1652911699
Short name T1748
Test name
Test status
Simulation time 23355812297 ps
CPU time 29.79 seconds
Started Jul 23 06:42:19 PM PDT 24
Finished Jul 23 06:42:51 PM PDT 24
Peak memory 206836 kb
Host smart-4a84b346-c743-43e6-b936-ceb51613522a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1652911699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.1652911699
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.3140815417
Short name T2639
Test name
Test status
Simulation time 199473076 ps
CPU time 0.91 seconds
Started Jul 23 06:42:20 PM PDT 24
Finished Jul 23 06:42:25 PM PDT 24
Peak memory 206176 kb
Host smart-6d93c806-c91e-4334-9d3e-887dc37294a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31408
15417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.3140815417
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.3623624800
Short name T2455
Test name
Test status
Simulation time 141725031 ps
CPU time 0.77 seconds
Started Jul 23 06:42:19 PM PDT 24
Finished Jul 23 06:42:22 PM PDT 24
Peak memory 206740 kb
Host smart-c32512a9-a3f4-4acf-ae4b-5843847e3b02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36236
24800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.3623624800
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.2468941264
Short name T2628
Test name
Test status
Simulation time 166823985 ps
CPU time 0.83 seconds
Started Jul 23 06:42:18 PM PDT 24
Finished Jul 23 06:42:21 PM PDT 24
Peak memory 206744 kb
Host smart-730dccce-0435-4f5f-b2cc-49bed2472813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24689
41264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.2468941264
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.3224496
Short name T2465
Test name
Test status
Simulation time 1239439312 ps
CPU time 2.61 seconds
Started Jul 23 06:42:18 PM PDT 24
Finished Jul 23 06:42:22 PM PDT 24
Peak memory 206924 kb
Host smart-b2bca4de-0395-4811-ad50-cfde6fdd393d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32244
96 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.3224496
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.851989325
Short name T1350
Test name
Test status
Simulation time 22600805279 ps
CPU time 44.13 seconds
Started Jul 23 06:42:19 PM PDT 24
Finished Jul 23 06:43:05 PM PDT 24
Peak memory 206932 kb
Host smart-f09bc74b-a781-45ec-8bbf-1f8cb7073d1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85198
9325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.851989325
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.2018110279
Short name T1430
Test name
Test status
Simulation time 447524810 ps
CPU time 1.46 seconds
Started Jul 23 06:42:21 PM PDT 24
Finished Jul 23 06:42:26 PM PDT 24
Peak memory 206760 kb
Host smart-0b036df4-976d-483a-a667-dea98727dcab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20181
10279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.2018110279
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.1896327636
Short name T569
Test name
Test status
Simulation time 138456004 ps
CPU time 0.84 seconds
Started Jul 23 06:42:20 PM PDT 24
Finished Jul 23 06:42:24 PM PDT 24
Peak memory 206776 kb
Host smart-a71be447-4c6e-4ebc-a41b-c812ea144205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18963
27636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.1896327636
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.4028409589
Short name T500
Test name
Test status
Simulation time 38903757 ps
CPU time 0.67 seconds
Started Jul 23 06:42:19 PM PDT 24
Finished Jul 23 06:42:22 PM PDT 24
Peak memory 206748 kb
Host smart-c688c90d-5ce5-4c0f-9046-28191bbd59f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40284
09589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.4028409589
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.170720084
Short name T1678
Test name
Test status
Simulation time 894491194 ps
CPU time 2.16 seconds
Started Jul 23 06:42:18 PM PDT 24
Finished Jul 23 06:42:22 PM PDT 24
Peak memory 206836 kb
Host smart-2040e7b2-eb59-4ae6-9b85-b4beddffa937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17072
0084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.170720084
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.1259526614
Short name T2421
Test name
Test status
Simulation time 363198180 ps
CPU time 2.33 seconds
Started Jul 23 06:42:22 PM PDT 24
Finished Jul 23 06:42:27 PM PDT 24
Peak memory 206884 kb
Host smart-db7e81de-adae-49ed-9ec1-019d54517847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12595
26614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.1259526614
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.1712853681
Short name T364
Test name
Test status
Simulation time 239885865 ps
CPU time 0.9 seconds
Started Jul 23 06:42:21 PM PDT 24
Finished Jul 23 06:42:25 PM PDT 24
Peak memory 206780 kb
Host smart-a2dd1d60-6411-4f8c-b9fc-ae82b7309007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17128
53681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.1712853681
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.2414713287
Short name T17
Test name
Test status
Simulation time 141271366 ps
CPU time 0.75 seconds
Started Jul 23 06:42:20 PM PDT 24
Finished Jul 23 06:42:23 PM PDT 24
Peak memory 206760 kb
Host smart-9d8eb954-ccdd-4ef0-8a43-372e9238d0f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24147
13287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.2414713287
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.974079132
Short name T1254
Test name
Test status
Simulation time 178943314 ps
CPU time 0.89 seconds
Started Jul 23 06:42:21 PM PDT 24
Finished Jul 23 06:42:25 PM PDT 24
Peak memory 206752 kb
Host smart-1a103df7-4984-4ed9-9d8b-db70ae0c48ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97407
9132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.974079132
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.3754311632
Short name T1810
Test name
Test status
Simulation time 7682806008 ps
CPU time 208.48 seconds
Started Jul 23 06:42:20 PM PDT 24
Finished Jul 23 06:45:52 PM PDT 24
Peak memory 206348 kb
Host smart-566a9339-f634-46b8-a2c2-80e0d3eb78f4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3754311632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.3754311632
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_iso_retraction.1912801567
Short name T1931
Test name
Test status
Simulation time 8232526630 ps
CPU time 31.73 seconds
Started Jul 23 06:42:19 PM PDT 24
Finished Jul 23 06:42:53 PM PDT 24
Peak memory 206924 kb
Host smart-7b509905-a27a-477e-9b21-108164cbf801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19128
01567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_iso_retraction.1912801567
Directory /workspace/23.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.336608576
Short name T215
Test name
Test status
Simulation time 230915843 ps
CPU time 0.88 seconds
Started Jul 23 06:42:19 PM PDT 24
Finished Jul 23 06:42:23 PM PDT 24
Peak memory 206744 kb
Host smart-83562c38-41f0-41b1-b1f5-5613d153fefc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33660
8576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.336608576
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.81997736
Short name T1754
Test name
Test status
Simulation time 23329837581 ps
CPU time 23.27 seconds
Started Jul 23 06:42:19 PM PDT 24
Finished Jul 23 06:42:44 PM PDT 24
Peak memory 206800 kb
Host smart-04acaed6-9eb4-4c8b-8d2c-3066de93dc4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81997
736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.81997736
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.227832475
Short name T476
Test name
Test status
Simulation time 3311763052 ps
CPU time 4.44 seconds
Started Jul 23 06:42:19 PM PDT 24
Finished Jul 23 06:42:27 PM PDT 24
Peak memory 206820 kb
Host smart-45b6986b-bb65-4ff9-a75d-7482762ed931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22783
2475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.227832475
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.3295654247
Short name T2325
Test name
Test status
Simulation time 11858410587 ps
CPU time 113.29 seconds
Started Jul 23 06:42:18 PM PDT 24
Finished Jul 23 06:44:13 PM PDT 24
Peak memory 206852 kb
Host smart-6e5a4e88-1f2a-47a5-aca6-86cdc7800cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32956
54247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.3295654247
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.1451976707
Short name T2390
Test name
Test status
Simulation time 4346458466 ps
CPU time 29.72 seconds
Started Jul 23 06:42:18 PM PDT 24
Finished Jul 23 06:42:49 PM PDT 24
Peak memory 206924 kb
Host smart-1a00c4c0-b639-4dee-9b79-f139003d23f8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1451976707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.1451976707
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.3041125683
Short name T1148
Test name
Test status
Simulation time 240147392 ps
CPU time 0.89 seconds
Started Jul 23 06:42:28 PM PDT 24
Finished Jul 23 06:42:32 PM PDT 24
Peak memory 206724 kb
Host smart-1cf9716f-a88f-4b7a-8178-2119878f8c9c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3041125683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.3041125683
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.3985345908
Short name T2464
Test name
Test status
Simulation time 240340386 ps
CPU time 0.95 seconds
Started Jul 23 06:42:29 PM PDT 24
Finished Jul 23 06:42:32 PM PDT 24
Peak memory 206752 kb
Host smart-07d9a792-64b3-4c30-94e6-1c0d0b508a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39853
45908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.3985345908
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.708114701
Short name T2446
Test name
Test status
Simulation time 6235489407 ps
CPU time 178.81 seconds
Started Jul 23 06:42:28 PM PDT 24
Finished Jul 23 06:45:30 PM PDT 24
Peak memory 206900 kb
Host smart-8e292cb7-09e9-462c-971a-eac65096ffff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70811
4701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.708114701
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.395303452
Short name T531
Test name
Test status
Simulation time 3951129636 ps
CPU time 107.32 seconds
Started Jul 23 06:42:26 PM PDT 24
Finished Jul 23 06:44:15 PM PDT 24
Peak memory 206900 kb
Host smart-15a159ae-7b1f-4e84-bb69-740d917c8336
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=395303452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.395303452
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.312072963
Short name T971
Test name
Test status
Simulation time 224418464 ps
CPU time 0.89 seconds
Started Jul 23 06:42:26 PM PDT 24
Finished Jul 23 06:42:29 PM PDT 24
Peak memory 206756 kb
Host smart-da9aba66-2156-474a-8c18-798ed882b13d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=312072963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.312072963
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.3776217066
Short name T628
Test name
Test status
Simulation time 144225675 ps
CPU time 0.8 seconds
Started Jul 23 06:42:27 PM PDT 24
Finished Jul 23 06:42:31 PM PDT 24
Peak memory 206736 kb
Host smart-ba8c0b25-1319-47c4-b7c9-4a0f712a2d9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37762
17066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.3776217066
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.4041487661
Short name T127
Test name
Test status
Simulation time 176095743 ps
CPU time 0.8 seconds
Started Jul 23 06:42:26 PM PDT 24
Finished Jul 23 06:42:28 PM PDT 24
Peak memory 206656 kb
Host smart-4e4edcf0-0b9c-4cde-a583-2e99e7dab640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40414
87661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.4041487661
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.3052698210
Short name T1024
Test name
Test status
Simulation time 192024955 ps
CPU time 0.98 seconds
Started Jul 23 06:42:26 PM PDT 24
Finished Jul 23 06:42:29 PM PDT 24
Peak memory 206752 kb
Host smart-90ad74be-3583-4b5d-a543-d0e7626b3256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30526
98210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.3052698210
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.418862043
Short name T1771
Test name
Test status
Simulation time 162914423 ps
CPU time 0.82 seconds
Started Jul 23 06:42:28 PM PDT 24
Finished Jul 23 06:42:32 PM PDT 24
Peak memory 206748 kb
Host smart-7f489caf-f900-4198-8dff-2b9b30aff17b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41886
2043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.418862043
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.2287946130
Short name T1226
Test name
Test status
Simulation time 203328949 ps
CPU time 0.91 seconds
Started Jul 23 06:42:26 PM PDT 24
Finished Jul 23 06:42:29 PM PDT 24
Peak memory 206764 kb
Host smart-df3df8bd-dc56-43f3-acb5-ca7edcde415f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22879
46130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.2287946130
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.1490640395
Short name T2307
Test name
Test status
Simulation time 140480687 ps
CPU time 0.8 seconds
Started Jul 23 06:42:26 PM PDT 24
Finished Jul 23 06:42:29 PM PDT 24
Peak memory 206760 kb
Host smart-3e0104fb-0361-428c-8764-cfd4a91150ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14906
40395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.1490640395
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.3977955509
Short name T1863
Test name
Test status
Simulation time 231249461 ps
CPU time 1.02 seconds
Started Jul 23 06:42:27 PM PDT 24
Finished Jul 23 06:42:30 PM PDT 24
Peak memory 206752 kb
Host smart-a8fe91c1-5bf7-4aa1-a00f-b51bbe506f6f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3977955509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.3977955509
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.1471259376
Short name T1387
Test name
Test status
Simulation time 140992985 ps
CPU time 0.76 seconds
Started Jul 23 06:42:25 PM PDT 24
Finished Jul 23 06:42:27 PM PDT 24
Peak memory 206752 kb
Host smart-3451c631-4baf-4a0e-9b22-ca372d27eeb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14712
59376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.1471259376
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2885959073
Short name T2235
Test name
Test status
Simulation time 113458693 ps
CPU time 0.76 seconds
Started Jul 23 06:42:26 PM PDT 24
Finished Jul 23 06:42:29 PM PDT 24
Peak memory 206732 kb
Host smart-24e1b244-12c9-4ad2-913c-718ceefa7846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28859
59073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2885959073
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.3655569105
Short name T862
Test name
Test status
Simulation time 10548108881 ps
CPU time 23.73 seconds
Started Jul 23 06:42:27 PM PDT 24
Finished Jul 23 06:42:53 PM PDT 24
Peak memory 215160 kb
Host smart-f831d6f2-6a0e-4d34-a1c0-1999f344e7d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36555
69105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.3655569105
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.2603029495
Short name T2040
Test name
Test status
Simulation time 166473743 ps
CPU time 0.8 seconds
Started Jul 23 06:42:25 PM PDT 24
Finished Jul 23 06:42:27 PM PDT 24
Peak memory 206756 kb
Host smart-9e875741-f200-49e1-b4d0-9ee4e0a9689e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26030
29495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.2603029495
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.236655017
Short name T1490
Test name
Test status
Simulation time 247035876 ps
CPU time 0.89 seconds
Started Jul 23 06:42:26 PM PDT 24
Finished Jul 23 06:42:30 PM PDT 24
Peak memory 206664 kb
Host smart-992d7c34-59ec-4ad2-8a57-3bebede05634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23665
5017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.236655017
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.1207893180
Short name T1912
Test name
Test status
Simulation time 190337088 ps
CPU time 0.83 seconds
Started Jul 23 06:42:28 PM PDT 24
Finished Jul 23 06:42:31 PM PDT 24
Peak memory 206752 kb
Host smart-7ba4e430-ce04-446d-9092-4532c6ab5204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12078
93180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.1207893180
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.2374897835
Short name T337
Test name
Test status
Simulation time 166453633 ps
CPU time 0.81 seconds
Started Jul 23 06:42:28 PM PDT 24
Finished Jul 23 06:42:32 PM PDT 24
Peak memory 206760 kb
Host smart-589ebbb1-50b7-4bdc-8888-a6447f7a7bfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23748
97835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.2374897835
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.2990200231
Short name T1457
Test name
Test status
Simulation time 159163493 ps
CPU time 0.75 seconds
Started Jul 23 06:42:26 PM PDT 24
Finished Jul 23 06:42:28 PM PDT 24
Peak memory 206748 kb
Host smart-4c3c4b7a-5371-4ac9-8a98-f70a1e77d81b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29902
00231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.2990200231
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.1521256625
Short name T428
Test name
Test status
Simulation time 153718082 ps
CPU time 0.77 seconds
Started Jul 23 06:42:28 PM PDT 24
Finished Jul 23 06:42:31 PM PDT 24
Peak memory 206692 kb
Host smart-3c431465-0b6b-4a1b-996b-77349e7b7236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15212
56625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.1521256625
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.4110145711
Short name T2118
Test name
Test status
Simulation time 152220436 ps
CPU time 0.82 seconds
Started Jul 23 06:42:28 PM PDT 24
Finished Jul 23 06:42:32 PM PDT 24
Peak memory 206752 kb
Host smart-4a3eb2fe-8e9c-4b5f-9862-a815f68c459e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41101
45711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.4110145711
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.2177562119
Short name T1807
Test name
Test status
Simulation time 187072894 ps
CPU time 0.88 seconds
Started Jul 23 06:42:27 PM PDT 24
Finished Jul 23 06:42:30 PM PDT 24
Peak memory 206756 kb
Host smart-bc5ddf57-d0c8-44a8-b724-f4629d228e32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21775
62119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.2177562119
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.777737193
Short name T2473
Test name
Test status
Simulation time 4854695532 ps
CPU time 131.42 seconds
Started Jul 23 06:42:27 PM PDT 24
Finished Jul 23 06:44:42 PM PDT 24
Peak memory 206864 kb
Host smart-650a0225-8b71-406d-bd3c-b6528b04e7bb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=777737193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.777737193
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.445284177
Short name T1905
Test name
Test status
Simulation time 192543131 ps
CPU time 0.86 seconds
Started Jul 23 06:42:26 PM PDT 24
Finished Jul 23 06:42:28 PM PDT 24
Peak memory 206716 kb
Host smart-c91eaa8f-29cf-46e8-9057-065e9a954d2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44528
4177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.445284177
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.1669609704
Short name T1438
Test name
Test status
Simulation time 206476207 ps
CPU time 0.91 seconds
Started Jul 23 06:42:27 PM PDT 24
Finished Jul 23 06:42:30 PM PDT 24
Peak memory 206772 kb
Host smart-8bb9eeb3-abdc-462c-a626-3cad1c12905d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16696
09704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.1669609704
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.3673394934
Short name T1800
Test name
Test status
Simulation time 207473017 ps
CPU time 0.88 seconds
Started Jul 23 06:42:27 PM PDT 24
Finished Jul 23 06:42:31 PM PDT 24
Peak memory 206740 kb
Host smart-db1591b8-84d4-4fa8-a6c4-cc1b8ff2cd47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36733
94934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.3673394934
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.3561488352
Short name T2419
Test name
Test status
Simulation time 3407731792 ps
CPU time 92.06 seconds
Started Jul 23 06:42:27 PM PDT 24
Finished Jul 23 06:44:01 PM PDT 24
Peak memory 206880 kb
Host smart-cfab699d-29a7-40fb-9cef-2ff924c18b00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35614
88352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.3561488352
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.2323210899
Short name T2702
Test name
Test status
Simulation time 44623370 ps
CPU time 0.69 seconds
Started Jul 23 06:42:41 PM PDT 24
Finished Jul 23 06:42:45 PM PDT 24
Peak memory 206740 kb
Host smart-756d540f-3a84-4705-b12b-0bf12e035862
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2323210899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.2323210899
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.4097917896
Short name T1128
Test name
Test status
Simulation time 3993470653 ps
CPU time 4.6 seconds
Started Jul 23 06:42:42 PM PDT 24
Finished Jul 23 06:42:50 PM PDT 24
Peak memory 206836 kb
Host smart-cb82d074-8369-4a84-8f3c-260c0f8ff351
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4097917896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.4097917896
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.2830852193
Short name T1420
Test name
Test status
Simulation time 13430065378 ps
CPU time 13.53 seconds
Started Jul 23 06:42:37 PM PDT 24
Finished Jul 23 06:42:54 PM PDT 24
Peak memory 206868 kb
Host smart-9b4530cd-b0a6-48d3-b4ea-c3373c64b3f1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2830852193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.2830852193
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.2743391231
Short name T1517
Test name
Test status
Simulation time 23507590950 ps
CPU time 27.4 seconds
Started Jul 23 06:42:40 PM PDT 24
Finished Jul 23 06:43:11 PM PDT 24
Peak memory 206916 kb
Host smart-aa494f34-a4e7-49cc-b0c9-64a7e2f6ac5d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2743391231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.2743391231
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.676462037
Short name T1122
Test name
Test status
Simulation time 164930468 ps
CPU time 0.81 seconds
Started Jul 23 06:42:39 PM PDT 24
Finished Jul 23 06:42:44 PM PDT 24
Peak memory 206664 kb
Host smart-ac5d71e7-2f0e-41a2-b509-bd741e52922c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67646
2037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.676462037
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.321044659
Short name T1179
Test name
Test status
Simulation time 186437555 ps
CPU time 0.84 seconds
Started Jul 23 06:42:36 PM PDT 24
Finished Jul 23 06:42:39 PM PDT 24
Peak memory 206684 kb
Host smart-d06d2d39-65ab-40ba-b865-f3c907c3c40d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32104
4659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.321044659
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.2394369363
Short name T913
Test name
Test status
Simulation time 365192945 ps
CPU time 1.28 seconds
Started Jul 23 06:42:36 PM PDT 24
Finished Jul 23 06:42:40 PM PDT 24
Peak memory 206740 kb
Host smart-925d8204-fe9a-4b9e-ad40-9027a9a32202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23943
69363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.2394369363
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.3485793761
Short name T2320
Test name
Test status
Simulation time 1264658775 ps
CPU time 2.94 seconds
Started Jul 23 06:42:37 PM PDT 24
Finished Jul 23 06:42:43 PM PDT 24
Peak memory 206912 kb
Host smart-a7c99054-0952-44a2-aeef-e81b76b9e83a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34857
93761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.3485793761
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.1172250980
Short name T101
Test name
Test status
Simulation time 12930446933 ps
CPU time 25.02 seconds
Started Jul 23 06:42:36 PM PDT 24
Finished Jul 23 06:43:04 PM PDT 24
Peak memory 206876 kb
Host smart-a2ff57c0-cbce-4eb7-815d-1747abc379c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11722
50980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.1172250980
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.2735301551
Short name T307
Test name
Test status
Simulation time 509381534 ps
CPU time 1.72 seconds
Started Jul 23 06:42:42 PM PDT 24
Finished Jul 23 06:42:47 PM PDT 24
Peak memory 206772 kb
Host smart-c941ad0a-75bf-457c-a4e7-4b3773ba3f8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27353
01551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.2735301551
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.31113257
Short name T2000
Test name
Test status
Simulation time 139091882 ps
CPU time 0.76 seconds
Started Jul 23 06:42:36 PM PDT 24
Finished Jul 23 06:42:40 PM PDT 24
Peak memory 206768 kb
Host smart-6a9cad93-508a-4fc4-bbbf-e6e15a0c2d27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31113
257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.31113257
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.1166838232
Short name T30
Test name
Test status
Simulation time 36568888 ps
CPU time 0.64 seconds
Started Jul 23 06:42:36 PM PDT 24
Finished Jul 23 06:42:38 PM PDT 24
Peak memory 206724 kb
Host smart-ad38eeed-c421-4124-a1bb-41ca7e3aa7ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11668
38232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.1166838232
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.169073453
Short name T2581
Test name
Test status
Simulation time 638858223 ps
CPU time 1.68 seconds
Started Jul 23 06:42:35 PM PDT 24
Finished Jul 23 06:42:39 PM PDT 24
Peak memory 206844 kb
Host smart-c9c4d893-99fa-44dc-b702-5d708c40dcf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16907
3453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.169073453
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.2375095583
Short name T2090
Test name
Test status
Simulation time 312592709 ps
CPU time 1.97 seconds
Started Jul 23 06:42:35 PM PDT 24
Finished Jul 23 06:42:39 PM PDT 24
Peak memory 206916 kb
Host smart-23d7b7e8-6045-451d-a4bd-ecd5df49d5a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23750
95583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.2375095583
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.3058783108
Short name T431
Test name
Test status
Simulation time 177508405 ps
CPU time 0.84 seconds
Started Jul 23 06:42:36 PM PDT 24
Finished Jul 23 06:42:40 PM PDT 24
Peak memory 206752 kb
Host smart-39342937-5436-4d46-a47d-cb35ce6d4808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30587
83108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.3058783108
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.3636060498
Short name T2594
Test name
Test status
Simulation time 169196707 ps
CPU time 0.78 seconds
Started Jul 23 06:42:37 PM PDT 24
Finished Jul 23 06:42:41 PM PDT 24
Peak memory 206768 kb
Host smart-fbb9a6e5-bbe2-47da-a714-3ccfbce041bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36360
60498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.3636060498
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.3303767335
Short name T374
Test name
Test status
Simulation time 231975572 ps
CPU time 1.08 seconds
Started Jul 23 06:42:37 PM PDT 24
Finished Jul 23 06:42:42 PM PDT 24
Peak memory 206768 kb
Host smart-6cdd15ae-113c-4595-adb6-a10602f9bf02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33037
67335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.3303767335
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.2796967200
Short name T2210
Test name
Test status
Simulation time 7608070152 ps
CPU time 56.95 seconds
Started Jul 23 06:42:36 PM PDT 24
Finished Jul 23 06:43:36 PM PDT 24
Peak memory 206888 kb
Host smart-ff66deca-15c5-49e4-a93e-7ac661a4fbf4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2796967200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.2796967200
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_iso_retraction.3134051222
Short name T2294
Test name
Test status
Simulation time 5090092764 ps
CPU time 16.15 seconds
Started Jul 23 06:42:37 PM PDT 24
Finished Jul 23 06:42:56 PM PDT 24
Peak memory 206948 kb
Host smart-13b1aac9-4581-4a75-9fe7-8ef2fbec3122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31340
51222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_iso_retraction.3134051222
Directory /workspace/24.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.776333561
Short name T61
Test name
Test status
Simulation time 264170716 ps
CPU time 0.9 seconds
Started Jul 23 06:42:40 PM PDT 24
Finished Jul 23 06:42:45 PM PDT 24
Peak memory 206708 kb
Host smart-9116bd36-c9ac-4473-ad13-374c06fb04aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77633
3561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.776333561
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.1449200062
Short name T2260
Test name
Test status
Simulation time 23377535502 ps
CPU time 24.39 seconds
Started Jul 23 06:42:38 PM PDT 24
Finished Jul 23 06:43:07 PM PDT 24
Peak memory 206820 kb
Host smart-278ee947-a0d2-49d9-a9a8-2a0897fb5c25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14492
00062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.1449200062
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.1036904707
Short name T1411
Test name
Test status
Simulation time 3324027951 ps
CPU time 3.98 seconds
Started Jul 23 06:42:36 PM PDT 24
Finished Jul 23 06:42:42 PM PDT 24
Peak memory 206836 kb
Host smart-2f4a9f19-02c8-4bc9-b763-6f86ec1006c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10369
04707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.1036904707
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.1434971018
Short name T1671
Test name
Test status
Simulation time 8289852007 ps
CPU time 80.79 seconds
Started Jul 23 06:42:36 PM PDT 24
Finished Jul 23 06:43:58 PM PDT 24
Peak memory 206988 kb
Host smart-9dbf8bdd-4ca4-4ad1-8708-1b7ca4322269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14349
71018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.1434971018
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.919953432
Short name T338
Test name
Test status
Simulation time 4608267314 ps
CPU time 34.26 seconds
Started Jul 23 06:42:37 PM PDT 24
Finished Jul 23 06:43:15 PM PDT 24
Peak memory 206872 kb
Host smart-d2d96e58-5895-4832-8eb8-2cf3c0059c5c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=919953432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.919953432
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.3241310267
Short name T1240
Test name
Test status
Simulation time 232802696 ps
CPU time 0.91 seconds
Started Jul 23 06:42:38 PM PDT 24
Finished Jul 23 06:42:43 PM PDT 24
Peak memory 206776 kb
Host smart-a90a84b4-a02a-453f-9642-fcb9bb7b5761
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3241310267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.3241310267
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.3781840524
Short name T1125
Test name
Test status
Simulation time 213087201 ps
CPU time 0.94 seconds
Started Jul 23 06:42:39 PM PDT 24
Finished Jul 23 06:42:44 PM PDT 24
Peak memory 206660 kb
Host smart-c2b1989e-145a-4401-b49b-4ab5a082dd13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37818
40524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.3781840524
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.1279897590
Short name T1711
Test name
Test status
Simulation time 3689542675 ps
CPU time 34.48 seconds
Started Jul 23 06:42:37 PM PDT 24
Finished Jul 23 06:43:14 PM PDT 24
Peak memory 206912 kb
Host smart-18ce9102-bff0-4af4-b6aa-afbec4595cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12798
97590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.1279897590
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.244091057
Short name T478
Test name
Test status
Simulation time 6250419782 ps
CPU time 167.83 seconds
Started Jul 23 06:42:38 PM PDT 24
Finished Jul 23 06:45:30 PM PDT 24
Peak memory 206920 kb
Host smart-60bdee4c-4d5d-40ba-8bba-2dfe500f01fd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=244091057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.244091057
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.518336807
Short name T1344
Test name
Test status
Simulation time 143796926 ps
CPU time 0.8 seconds
Started Jul 23 06:42:36 PM PDT 24
Finished Jul 23 06:42:40 PM PDT 24
Peak memory 206776 kb
Host smart-21591554-6e97-4382-afda-070a246f95ca
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=518336807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.518336807
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.292853511
Short name T2032
Test name
Test status
Simulation time 172278341 ps
CPU time 0.86 seconds
Started Jul 23 06:42:38 PM PDT 24
Finished Jul 23 06:42:43 PM PDT 24
Peak memory 206752 kb
Host smart-afc9586d-fab0-438c-8bff-a189b844efb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29285
3511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.292853511
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.2814491225
Short name T2544
Test name
Test status
Simulation time 152982015 ps
CPU time 0.8 seconds
Started Jul 23 06:42:37 PM PDT 24
Finished Jul 23 06:42:42 PM PDT 24
Peak memory 206688 kb
Host smart-7476d95a-f545-4517-9e2f-ecbb01e6fb48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28144
91225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.2814491225
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.3321066320
Short name T1550
Test name
Test status
Simulation time 183096623 ps
CPU time 0.81 seconds
Started Jul 23 06:42:37 PM PDT 24
Finished Jul 23 06:42:41 PM PDT 24
Peak memory 206772 kb
Host smart-a0b1e5e8-282c-4cab-b52f-ca00fe62c2e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33210
66320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.3321066320
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.3413344021
Short name T521
Test name
Test status
Simulation time 163651057 ps
CPU time 0.77 seconds
Started Jul 23 06:42:36 PM PDT 24
Finished Jul 23 06:42:38 PM PDT 24
Peak memory 206744 kb
Host smart-a4763732-e498-4241-a13e-1f5a080d2b35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34133
44021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.3413344021
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.4221449364
Short name T2001
Test name
Test status
Simulation time 180857182 ps
CPU time 0.82 seconds
Started Jul 23 06:42:40 PM PDT 24
Finished Jul 23 06:42:45 PM PDT 24
Peak memory 206756 kb
Host smart-6ae56041-9baa-410a-b739-e15345930835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42214
49364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.4221449364
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.3387517725
Short name T2007
Test name
Test status
Simulation time 231005199 ps
CPU time 0.89 seconds
Started Jul 23 06:42:38 PM PDT 24
Finished Jul 23 06:42:43 PM PDT 24
Peak memory 206696 kb
Host smart-c5c8e005-7db6-4e64-b35c-666915b99b8c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3387517725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.3387517725
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.1584413952
Short name T752
Test name
Test status
Simulation time 144543343 ps
CPU time 0.78 seconds
Started Jul 23 06:42:38 PM PDT 24
Finished Jul 23 06:42:42 PM PDT 24
Peak memory 206752 kb
Host smart-597312e8-f9d8-4fed-a483-41eb758a8025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15844
13952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.1584413952
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.743991542
Short name T2122
Test name
Test status
Simulation time 64776490 ps
CPU time 0.67 seconds
Started Jul 23 06:42:35 PM PDT 24
Finished Jul 23 06:42:37 PM PDT 24
Peak memory 206732 kb
Host smart-bf11fa38-5fcc-4d87-8b31-b30a77d6b7e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74399
1542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.743991542
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.3150610219
Short name T2469
Test name
Test status
Simulation time 10677417905 ps
CPU time 23.99 seconds
Started Jul 23 06:42:38 PM PDT 24
Finished Jul 23 06:43:06 PM PDT 24
Peak memory 207000 kb
Host smart-f1bd5ef6-c39e-4feb-9411-eccba3abdf19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31506
10219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.3150610219
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.2234392405
Short name T1823
Test name
Test status
Simulation time 192535268 ps
CPU time 0.89 seconds
Started Jul 23 06:42:38 PM PDT 24
Finished Jul 23 06:42:43 PM PDT 24
Peak memory 206696 kb
Host smart-8e2ab425-812b-46ea-8a72-915378c6e9a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22343
92405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.2234392405
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.3784552112
Short name T1953
Test name
Test status
Simulation time 225471066 ps
CPU time 0.89 seconds
Started Jul 23 06:42:36 PM PDT 24
Finished Jul 23 06:42:40 PM PDT 24
Peak memory 206768 kb
Host smart-e202982b-f89b-4cab-ba96-e452637e9aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37845
52112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.3784552112
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.3971515029
Short name T2530
Test name
Test status
Simulation time 209638971 ps
CPU time 0.87 seconds
Started Jul 23 06:42:38 PM PDT 24
Finished Jul 23 06:42:43 PM PDT 24
Peak memory 206776 kb
Host smart-150a1374-f195-4039-9f22-e0b0257b73d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39715
15029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.3971515029
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.2763850408
Short name T1055
Test name
Test status
Simulation time 139703811 ps
CPU time 0.73 seconds
Started Jul 23 06:42:36 PM PDT 24
Finished Jul 23 06:42:39 PM PDT 24
Peak memory 206764 kb
Host smart-196e6a9e-2c52-4e33-848d-927d5642d9e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27638
50408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.2763850408
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.4159532981
Short name T2155
Test name
Test status
Simulation time 152070627 ps
CPU time 0.79 seconds
Started Jul 23 06:42:36 PM PDT 24
Finished Jul 23 06:42:40 PM PDT 24
Peak memory 206740 kb
Host smart-f333da3a-40cb-480c-9f15-2908014e7b69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41595
32981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.4159532981
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.1390968212
Short name T533
Test name
Test status
Simulation time 160648642 ps
CPU time 0.79 seconds
Started Jul 23 06:42:43 PM PDT 24
Finished Jul 23 06:42:47 PM PDT 24
Peak memory 206768 kb
Host smart-0cfe75be-987a-41ba-85e6-27a05fd917fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13909
68212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.1390968212
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.356767154
Short name T2659
Test name
Test status
Simulation time 223383131 ps
CPU time 0.92 seconds
Started Jul 23 06:42:44 PM PDT 24
Finished Jul 23 06:42:48 PM PDT 24
Peak memory 206688 kb
Host smart-e26241e8-3ba4-4195-9962-85b7c1203a4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35676
7154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.356767154
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.149881037
Short name T1359
Test name
Test status
Simulation time 4746083638 ps
CPU time 31.79 seconds
Started Jul 23 06:42:44 PM PDT 24
Finished Jul 23 06:43:19 PM PDT 24
Peak memory 206968 kb
Host smart-2ab20dc7-0047-40f7-8453-1252191880af
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=149881037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.149881037
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.3328486527
Short name T590
Test name
Test status
Simulation time 162431456 ps
CPU time 0.8 seconds
Started Jul 23 06:42:42 PM PDT 24
Finished Jul 23 06:42:46 PM PDT 24
Peak memory 206728 kb
Host smart-b5ef3868-d40f-449c-bd37-b85c8f6afc23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33284
86527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.3328486527
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.2875337421
Short name T840
Test name
Test status
Simulation time 194370110 ps
CPU time 0.84 seconds
Started Jul 23 06:42:47 PM PDT 24
Finished Jul 23 06:42:52 PM PDT 24
Peak memory 206744 kb
Host smart-bd4e0305-aba5-452e-8c83-16cf9f53ca2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28753
37421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.2875337421
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.598463244
Short name T2107
Test name
Test status
Simulation time 1056661070 ps
CPU time 2.32 seconds
Started Jul 23 06:42:48 PM PDT 24
Finished Jul 23 06:42:54 PM PDT 24
Peak memory 206880 kb
Host smart-e566f3ae-152a-45ef-9ace-dd7dfa92117a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59846
3244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.598463244
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.3754738700
Short name T878
Test name
Test status
Simulation time 7778211893 ps
CPU time 57.93 seconds
Started Jul 23 06:42:44 PM PDT 24
Finished Jul 23 06:43:45 PM PDT 24
Peak memory 206992 kb
Host smart-a167c1a0-152f-442f-b4b2-31ad6ca0ba4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37547
38700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.3754738700
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.837931678
Short name T2288
Test name
Test status
Simulation time 43267204 ps
CPU time 0.67 seconds
Started Jul 23 06:42:55 PM PDT 24
Finished Jul 23 06:43:01 PM PDT 24
Peak memory 206428 kb
Host smart-67df21f7-2a68-4ab5-b702-c25b5e9b37aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=837931678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.837931678
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.2497925330
Short name T2538
Test name
Test status
Simulation time 3658550218 ps
CPU time 5.22 seconds
Started Jul 23 06:42:46 PM PDT 24
Finished Jul 23 06:42:54 PM PDT 24
Peak memory 206904 kb
Host smart-5b85c993-2c1b-4eff-ad6a-698a05cf0376
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2497925330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.2497925330
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.157411094
Short name T1722
Test name
Test status
Simulation time 13385932002 ps
CPU time 13.99 seconds
Started Jul 23 06:42:45 PM PDT 24
Finished Jul 23 06:43:03 PM PDT 24
Peak memory 206976 kb
Host smart-fd210f7c-8cea-4620-882b-b79d66e89b20
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=157411094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.157411094
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.1288215353
Short name T489
Test name
Test status
Simulation time 23422486351 ps
CPU time 24.71 seconds
Started Jul 23 06:42:42 PM PDT 24
Finished Jul 23 06:43:10 PM PDT 24
Peak memory 206908 kb
Host smart-f54abd5b-c4af-4798-91a0-3534a254093d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1288215353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.1288215353
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.1672169497
Short name T1546
Test name
Test status
Simulation time 189368153 ps
CPU time 0.79 seconds
Started Jul 23 06:42:41 PM PDT 24
Finished Jul 23 06:42:45 PM PDT 24
Peak memory 206736 kb
Host smart-abd81c96-0f66-4c50-b1ab-e3a23bef3af2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16721
69497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.1672169497
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.3063662563
Short name T1152
Test name
Test status
Simulation time 157285695 ps
CPU time 0.77 seconds
Started Jul 23 06:42:49 PM PDT 24
Finished Jul 23 06:42:53 PM PDT 24
Peak memory 206732 kb
Host smart-0f0c3b52-c963-4efc-8272-0771ca62613d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30636
62563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.3063662563
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.4018098311
Short name T2281
Test name
Test status
Simulation time 265559052 ps
CPU time 1.07 seconds
Started Jul 23 06:42:44 PM PDT 24
Finished Jul 23 06:42:48 PM PDT 24
Peak memory 206764 kb
Host smart-b88cbf5b-7b3a-4a53-b663-0b4770259c12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40180
98311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.4018098311
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.2890828804
Short name T1224
Test name
Test status
Simulation time 368669383 ps
CPU time 1.09 seconds
Started Jul 23 06:42:50 PM PDT 24
Finished Jul 23 06:42:55 PM PDT 24
Peak memory 206728 kb
Host smart-b448b71b-27b5-4a1a-b9ff-750937b87042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28908
28804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.2890828804
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.2664184290
Short name T2343
Test name
Test status
Simulation time 6521500869 ps
CPU time 12.93 seconds
Started Jul 23 06:42:42 PM PDT 24
Finished Jul 23 06:42:58 PM PDT 24
Peak memory 207112 kb
Host smart-355e0880-7da0-4255-8dfe-98082aaaedc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26641
84290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.2664184290
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.3618953565
Short name T2674
Test name
Test status
Simulation time 427977505 ps
CPU time 1.32 seconds
Started Jul 23 06:42:48 PM PDT 24
Finished Jul 23 06:42:53 PM PDT 24
Peak memory 206732 kb
Host smart-5efc0374-f088-48ae-8783-3aca91742921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36189
53565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.3618953565
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.1910520417
Short name T1709
Test name
Test status
Simulation time 152562342 ps
CPU time 0.76 seconds
Started Jul 23 06:42:47 PM PDT 24
Finished Jul 23 06:42:52 PM PDT 24
Peak memory 206764 kb
Host smart-2d59f38b-9032-4a24-95c9-c554adfc1860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19105
20417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.1910520417
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.65922074
Short name T2726
Test name
Test status
Simulation time 80616503 ps
CPU time 0.69 seconds
Started Jul 23 06:42:41 PM PDT 24
Finished Jul 23 06:42:45 PM PDT 24
Peak memory 206736 kb
Host smart-17de6e85-8b87-45c9-a067-cbf5513e10fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65922
074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.65922074
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.174299558
Short name T601
Test name
Test status
Simulation time 1058595094 ps
CPU time 2.31 seconds
Started Jul 23 06:42:42 PM PDT 24
Finished Jul 23 06:42:48 PM PDT 24
Peak memory 206792 kb
Host smart-ea60848a-60b5-4837-9521-40b0ca7d7dec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17429
9558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.174299558
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.1683103509
Short name T778
Test name
Test status
Simulation time 305629055 ps
CPU time 2.11 seconds
Started Jul 23 06:42:44 PM PDT 24
Finished Jul 23 06:42:49 PM PDT 24
Peak memory 206908 kb
Host smart-43c01d9a-4297-4da1-8d09-85eda4b0c251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16831
03509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.1683103509
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.1811467312
Short name T400
Test name
Test status
Simulation time 231941634 ps
CPU time 0.94 seconds
Started Jul 23 06:42:42 PM PDT 24
Finished Jul 23 06:42:47 PM PDT 24
Peak memory 206700 kb
Host smart-10ac71a2-ce8a-414c-803c-35413cece2a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18114
67312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.1811467312
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.2767856997
Short name T1519
Test name
Test status
Simulation time 170544742 ps
CPU time 0.79 seconds
Started Jul 23 06:42:43 PM PDT 24
Finished Jul 23 06:42:47 PM PDT 24
Peak memory 206760 kb
Host smart-a380f609-7e2b-4d65-babe-67d16583ac8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27678
56997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.2767856997
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.3912735448
Short name T86
Test name
Test status
Simulation time 196818976 ps
CPU time 0.92 seconds
Started Jul 23 06:42:42 PM PDT 24
Finished Jul 23 06:42:46 PM PDT 24
Peak memory 206748 kb
Host smart-d26e3900-f6f7-4343-affb-0c76e3e479c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39127
35448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.3912735448
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.117834065
Short name T1006
Test name
Test status
Simulation time 9317023706 ps
CPU time 268.61 seconds
Started Jul 23 06:42:43 PM PDT 24
Finished Jul 23 06:47:15 PM PDT 24
Peak memory 206912 kb
Host smart-7043ecb9-3ff9-4ad4-9cda-f7fa806e54ac
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=117834065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.117834065
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_iso_retraction.1476500712
Short name T2612
Test name
Test status
Simulation time 9555483256 ps
CPU time 34.22 seconds
Started Jul 23 06:42:42 PM PDT 24
Finished Jul 23 06:43:20 PM PDT 24
Peak memory 206952 kb
Host smart-36b38c1a-6ed0-4d6e-a82b-f0206a4a583c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14765
00712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_iso_retraction.1476500712
Directory /workspace/25.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.1072953429
Short name T416
Test name
Test status
Simulation time 186006172 ps
CPU time 0.87 seconds
Started Jul 23 06:42:42 PM PDT 24
Finished Jul 23 06:42:46 PM PDT 24
Peak memory 206748 kb
Host smart-414a8f3a-32e4-439b-a183-c44f68a4a6a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10729
53429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.1072953429
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.1583285815
Short name T1300
Test name
Test status
Simulation time 23266670733 ps
CPU time 23.55 seconds
Started Jul 23 06:42:47 PM PDT 24
Finished Jul 23 06:43:14 PM PDT 24
Peak memory 206824 kb
Host smart-b81995aa-f2fc-49e6-b791-d8c0ad0643b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15832
85815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.1583285815
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.1510660795
Short name T615
Test name
Test status
Simulation time 3285519600 ps
CPU time 3.52 seconds
Started Jul 23 06:42:50 PM PDT 24
Finished Jul 23 06:42:57 PM PDT 24
Peak memory 206784 kb
Host smart-3d596413-04eb-401a-8644-18b4243b5fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15106
60795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.1510660795
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.2244366673
Short name T2541
Test name
Test status
Simulation time 11743091024 ps
CPU time 111.49 seconds
Started Jul 23 06:42:43 PM PDT 24
Finished Jul 23 06:44:37 PM PDT 24
Peak memory 206884 kb
Host smart-da543503-ff77-4059-bff6-0020f82982e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22443
66673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.2244366673
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.2693874680
Short name T2298
Test name
Test status
Simulation time 5209813006 ps
CPU time 144.87 seconds
Started Jul 23 06:42:48 PM PDT 24
Finished Jul 23 06:45:17 PM PDT 24
Peak memory 206872 kb
Host smart-5706b5c9-fc0c-4b8a-8cf6-48717a3eab6e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2693874680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.2693874680
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.3798818110
Short name T2430
Test name
Test status
Simulation time 266081913 ps
CPU time 0.9 seconds
Started Jul 23 06:42:42 PM PDT 24
Finished Jul 23 06:42:46 PM PDT 24
Peak memory 206752 kb
Host smart-4591e9c7-ac88-4692-9df2-133885fd3987
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3798818110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.3798818110
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.1777103380
Short name T1451
Test name
Test status
Simulation time 197262155 ps
CPU time 0.92 seconds
Started Jul 23 06:42:42 PM PDT 24
Finished Jul 23 06:42:47 PM PDT 24
Peak memory 206756 kb
Host smart-83702f9a-6974-4e4b-808e-31e9c44d7bb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17771
03380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.1777103380
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.3530016162
Short name T514
Test name
Test status
Simulation time 5420101029 ps
CPU time 152.14 seconds
Started Jul 23 06:42:45 PM PDT 24
Finished Jul 23 06:45:21 PM PDT 24
Peak memory 206940 kb
Host smart-08ae6cb2-bf45-4955-89d8-b4dc63ac36a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35300
16162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.3530016162
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.3718116080
Short name T2626
Test name
Test status
Simulation time 7068599106 ps
CPU time 49.74 seconds
Started Jul 23 06:42:45 PM PDT 24
Finished Jul 23 06:43:38 PM PDT 24
Peak memory 206924 kb
Host smart-c891893d-17fd-4b40-ae44-7372db2b69cc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3718116080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.3718116080
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.2152845888
Short name T2605
Test name
Test status
Simulation time 158393915 ps
CPU time 0.8 seconds
Started Jul 23 06:42:43 PM PDT 24
Finished Jul 23 06:42:47 PM PDT 24
Peak memory 206772 kb
Host smart-30e4c5a4-8a1e-4dff-baa5-91d1a4a7e03c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2152845888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.2152845888
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.328725860
Short name T2522
Test name
Test status
Simulation time 159595085 ps
CPU time 0.81 seconds
Started Jul 23 06:42:43 PM PDT 24
Finished Jul 23 06:42:47 PM PDT 24
Peak memory 206772 kb
Host smart-0ba13e1b-6369-4b10-baab-05be43e8c5d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32872
5860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.328725860
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.1739107657
Short name T139
Test name
Test status
Simulation time 293179106 ps
CPU time 1.04 seconds
Started Jul 23 06:42:44 PM PDT 24
Finished Jul 23 06:42:49 PM PDT 24
Peak memory 206744 kb
Host smart-14663fbc-ab12-42a7-abe7-1d18458cbae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17391
07657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.1739107657
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.1127844111
Short name T1363
Test name
Test status
Simulation time 153508021 ps
CPU time 0.81 seconds
Started Jul 23 06:42:47 PM PDT 24
Finished Jul 23 06:42:51 PM PDT 24
Peak memory 206752 kb
Host smart-b480e6e9-cfe8-4b34-b3b0-47100885ba7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11278
44111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.1127844111
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.3466852423
Short name T575
Test name
Test status
Simulation time 167457612 ps
CPU time 0.77 seconds
Started Jul 23 06:42:55 PM PDT 24
Finished Jul 23 06:43:01 PM PDT 24
Peak memory 206756 kb
Host smart-44633e4d-1e43-4a45-aa78-1db28eed00ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34668
52423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.3466852423
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.1748683537
Short name T2164
Test name
Test status
Simulation time 182715291 ps
CPU time 0.85 seconds
Started Jul 23 06:42:44 PM PDT 24
Finished Jul 23 06:42:48 PM PDT 24
Peak memory 206748 kb
Host smart-155286a5-2ad9-4384-bb8a-38c526cd95ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17486
83537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.1748683537
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.615922497
Short name T1543
Test name
Test status
Simulation time 185069839 ps
CPU time 0.86 seconds
Started Jul 23 06:42:45 PM PDT 24
Finished Jul 23 06:42:49 PM PDT 24
Peak memory 206796 kb
Host smart-24008d1f-3d37-4a23-8b86-36eb757a83bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61592
2497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.615922497
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.1717809770
Short name T1497
Test name
Test status
Simulation time 184194147 ps
CPU time 0.93 seconds
Started Jul 23 06:42:56 PM PDT 24
Finished Jul 23 06:43:03 PM PDT 24
Peak memory 206760 kb
Host smart-76e42758-4891-40dc-a677-b8c7450ede9d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1717809770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.1717809770
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.4235722921
Short name T187
Test name
Test status
Simulation time 141753547 ps
CPU time 0.77 seconds
Started Jul 23 06:42:47 PM PDT 24
Finished Jul 23 06:42:51 PM PDT 24
Peak memory 206764 kb
Host smart-11bb99d8-85ed-4b21-acbb-9edb712556d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42357
22921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.4235722921
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.953533318
Short name T2693
Test name
Test status
Simulation time 38823553 ps
CPU time 0.65 seconds
Started Jul 23 06:42:46 PM PDT 24
Finished Jul 23 06:42:51 PM PDT 24
Peak memory 206632 kb
Host smart-0ef9e54a-f259-432a-94ec-408332de33e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95353
3318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.953533318
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.3024629952
Short name T2368
Test name
Test status
Simulation time 15563862917 ps
CPU time 35.32 seconds
Started Jul 23 06:42:51 PM PDT 24
Finished Jul 23 06:43:30 PM PDT 24
Peak memory 215208 kb
Host smart-0d3249bd-f741-48f7-8e91-2e49761ae8d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30246
29952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.3024629952
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.3958930852
Short name T2174
Test name
Test status
Simulation time 143690653 ps
CPU time 0.76 seconds
Started Jul 23 06:42:47 PM PDT 24
Finished Jul 23 06:42:52 PM PDT 24
Peak memory 206776 kb
Host smart-c7d1cfdd-eac1-4698-a99f-4cd04ed7a9c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39589
30852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.3958930852
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.2796591617
Short name T1368
Test name
Test status
Simulation time 165869319 ps
CPU time 0.83 seconds
Started Jul 23 06:42:55 PM PDT 24
Finished Jul 23 06:43:01 PM PDT 24
Peak memory 206348 kb
Host smart-7f71dbc4-d359-4734-b9fd-62fa31974424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27965
91617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.2796591617
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.1259413476
Short name T881
Test name
Test status
Simulation time 259688344 ps
CPU time 0.9 seconds
Started Jul 23 06:42:45 PM PDT 24
Finished Jul 23 06:42:49 PM PDT 24
Peak memory 206764 kb
Host smart-e087555c-dd51-440d-ad74-c292c4b7ab44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12594
13476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.1259413476
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.3040340637
Short name T2042
Test name
Test status
Simulation time 228606806 ps
CPU time 0.85 seconds
Started Jul 23 06:42:45 PM PDT 24
Finished Jul 23 06:42:49 PM PDT 24
Peak memory 206736 kb
Host smart-4fdc59c6-84e3-44bb-8e90-2b265a39a2a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30403
40637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.3040340637
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.3044877937
Short name T1310
Test name
Test status
Simulation time 213991714 ps
CPU time 0.88 seconds
Started Jul 23 06:42:46 PM PDT 24
Finished Jul 23 06:42:50 PM PDT 24
Peak memory 206752 kb
Host smart-f59afe46-60f5-4f75-b4b1-02c12adcd072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30448
77937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.3044877937
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.3615060851
Short name T2146
Test name
Test status
Simulation time 144945684 ps
CPU time 0.75 seconds
Started Jul 23 06:42:54 PM PDT 24
Finished Jul 23 06:43:00 PM PDT 24
Peak memory 206756 kb
Host smart-d3a39755-7d40-4ca5-8df0-fe2e023ff509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36150
60851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.3615060851
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.2071263268
Short name T1660
Test name
Test status
Simulation time 154528828 ps
CPU time 0.78 seconds
Started Jul 23 06:42:50 PM PDT 24
Finished Jul 23 06:42:55 PM PDT 24
Peak memory 206732 kb
Host smart-dfb40ea2-adee-4db8-b55a-f30b5ced9396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20712
63268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.2071263268
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.1484126663
Short name T313
Test name
Test status
Simulation time 243763810 ps
CPU time 0.94 seconds
Started Jul 23 06:42:46 PM PDT 24
Finished Jul 23 06:42:50 PM PDT 24
Peak memory 206724 kb
Host smart-d497aee9-23cf-4378-a0bb-ff8297de340f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14841
26663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.1484126663
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.1673483934
Short name T2149
Test name
Test status
Simulation time 7098704758 ps
CPU time 49.57 seconds
Started Jul 23 06:42:49 PM PDT 24
Finished Jul 23 06:43:43 PM PDT 24
Peak memory 206964 kb
Host smart-95fbba73-b045-4e71-acca-b81c25f40685
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1673483934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.1673483934
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.773380905
Short name T1446
Test name
Test status
Simulation time 183725367 ps
CPU time 0.83 seconds
Started Jul 23 06:42:55 PM PDT 24
Finished Jul 23 06:43:01 PM PDT 24
Peak memory 206752 kb
Host smart-cca873c6-de8d-4d55-8fa6-826caab73c8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77338
0905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.773380905
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.3909085275
Short name T2054
Test name
Test status
Simulation time 206730698 ps
CPU time 0.84 seconds
Started Jul 23 06:42:55 PM PDT 24
Finished Jul 23 06:43:01 PM PDT 24
Peak memory 206728 kb
Host smart-2e21eb4c-f812-48bf-bbc5-124834e3c21a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39090
85275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.3909085275
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.1059677580
Short name T1360
Test name
Test status
Simulation time 1112062934 ps
CPU time 2.45 seconds
Started Jul 23 06:42:52 PM PDT 24
Finished Jul 23 06:42:59 PM PDT 24
Peak memory 206856 kb
Host smart-90c131ff-5bb4-4018-8763-f0d2e96ebd00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10596
77580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.1059677580
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.711497248
Short name T1499
Test name
Test status
Simulation time 4670564528 ps
CPU time 32.19 seconds
Started Jul 23 06:42:55 PM PDT 24
Finished Jul 23 06:43:33 PM PDT 24
Peak memory 206964 kb
Host smart-f1c82b97-64d2-4fc8-b31b-821a3497b10e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71149
7248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.711497248
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.2744188177
Short name T864
Test name
Test status
Simulation time 32589025 ps
CPU time 0.68 seconds
Started Jul 23 06:42:56 PM PDT 24
Finished Jul 23 06:43:03 PM PDT 24
Peak memory 206688 kb
Host smart-68c20404-3dbc-4006-9e9d-45f065ec5d75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2744188177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.2744188177
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.3301386209
Short name T419
Test name
Test status
Simulation time 4361659871 ps
CPU time 5.67 seconds
Started Jul 23 06:42:55 PM PDT 24
Finished Jul 23 06:43:06 PM PDT 24
Peak memory 206824 kb
Host smart-c193acef-f0cd-4b15-b6fc-7fafeb8af0ef
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3301386209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.3301386209
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.3162171652
Short name T497
Test name
Test status
Simulation time 13475697118 ps
CPU time 12.95 seconds
Started Jul 23 06:42:51 PM PDT 24
Finished Jul 23 06:43:08 PM PDT 24
Peak memory 206848 kb
Host smart-9d5f1753-5dfc-44f3-bf8d-f91e9c081436
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3162171652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.3162171652
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.3100119073
Short name T1937
Test name
Test status
Simulation time 23461649948 ps
CPU time 24 seconds
Started Jul 23 06:42:55 PM PDT 24
Finished Jul 23 06:43:24 PM PDT 24
Peak memory 206948 kb
Host smart-f8105208-1b6b-49e4-b6b1-a368648b2e73
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3100119073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.3100119073
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.2210834130
Short name T1158
Test name
Test status
Simulation time 168022620 ps
CPU time 0.79 seconds
Started Jul 23 06:42:52 PM PDT 24
Finished Jul 23 06:42:57 PM PDT 24
Peak memory 206728 kb
Host smart-ee216c19-dc77-4094-a050-b909ab98459e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22108
34130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.2210834130
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.2108555847
Short name T2384
Test name
Test status
Simulation time 145534605 ps
CPU time 0.77 seconds
Started Jul 23 06:42:55 PM PDT 24
Finished Jul 23 06:43:01 PM PDT 24
Peak memory 206756 kb
Host smart-26c39889-7a77-4814-a9b3-48c993e148b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21085
55847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.2108555847
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.3614483059
Short name T1382
Test name
Test status
Simulation time 399136275 ps
CPU time 1.29 seconds
Started Jul 23 06:42:55 PM PDT 24
Finished Jul 23 06:43:02 PM PDT 24
Peak memory 206752 kb
Host smart-79ee2ad8-3b2b-4929-b855-5a071f3ca942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36144
83059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.3614483059
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.2397934080
Short name T922
Test name
Test status
Simulation time 1497951727 ps
CPU time 3.11 seconds
Started Jul 23 06:42:52 PM PDT 24
Finished Jul 23 06:42:59 PM PDT 24
Peak memory 206876 kb
Host smart-c4210b60-0ae7-457a-bc98-78b9bb35163c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23979
34080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.2397934080
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.2926595077
Short name T1165
Test name
Test status
Simulation time 22431466319 ps
CPU time 44.59 seconds
Started Jul 23 06:42:51 PM PDT 24
Finished Jul 23 06:43:40 PM PDT 24
Peak memory 206864 kb
Host smart-e7952feb-f3c2-4baa-9ecb-23eefb464aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29265
95077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.2926595077
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.4156754166
Short name T2439
Test name
Test status
Simulation time 371685708 ps
CPU time 1.14 seconds
Started Jul 23 06:42:50 PM PDT 24
Finished Jul 23 06:42:55 PM PDT 24
Peak memory 206756 kb
Host smart-2dfb5698-ee37-428a-af64-111634a36911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41567
54166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.4156754166
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_enable.3255336230
Short name T2723
Test name
Test status
Simulation time 42419756 ps
CPU time 0.66 seconds
Started Jul 23 06:42:52 PM PDT 24
Finished Jul 23 06:42:57 PM PDT 24
Peak memory 206664 kb
Host smart-1113118b-fae9-4be9-8a49-f68cca198d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32553
36230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.3255336230
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.2845401871
Short name T1855
Test name
Test status
Simulation time 880307213 ps
CPU time 1.99 seconds
Started Jul 23 06:42:53 PM PDT 24
Finished Jul 23 06:43:01 PM PDT 24
Peak memory 206856 kb
Host smart-3e1c8012-ff9d-43e0-9f3f-dee2eec074e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28454
01871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.2845401871
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.159010102
Short name T1777
Test name
Test status
Simulation time 263926717 ps
CPU time 1.79 seconds
Started Jul 23 06:42:53 PM PDT 24
Finished Jul 23 06:43:00 PM PDT 24
Peak memory 206912 kb
Host smart-84112608-bf85-41d6-95a1-dfb6650bf5d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15901
0102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.159010102
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.3531059381
Short name T1129
Test name
Test status
Simulation time 243383256 ps
CPU time 0.86 seconds
Started Jul 23 06:42:51 PM PDT 24
Finished Jul 23 06:42:56 PM PDT 24
Peak memory 206716 kb
Host smart-fc05b88f-9d13-412d-86db-4d77f0ae4234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35310
59381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.3531059381
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.179847103
Short name T2011
Test name
Test status
Simulation time 139465242 ps
CPU time 0.76 seconds
Started Jul 23 06:42:51 PM PDT 24
Finished Jul 23 06:42:56 PM PDT 24
Peak memory 206744 kb
Host smart-b8e091be-f6b6-460c-9f11-3cf000f507c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17984
7103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.179847103
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.1120233527
Short name T1453
Test name
Test status
Simulation time 231877291 ps
CPU time 0.88 seconds
Started Jul 23 06:42:53 PM PDT 24
Finished Jul 23 06:42:59 PM PDT 24
Peak memory 206780 kb
Host smart-f5592ba3-69ba-41a8-9250-224b93548128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11202
33527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.1120233527
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_iso_retraction.1812878390
Short name T689
Test name
Test status
Simulation time 8705750873 ps
CPU time 76.52 seconds
Started Jul 23 06:42:54 PM PDT 24
Finished Jul 23 06:44:16 PM PDT 24
Peak memory 206872 kb
Host smart-020be836-70db-43e1-8253-bf0eb0ea528f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18128
78390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_iso_retraction.1812878390
Directory /workspace/26.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.2569555196
Short name T21
Test name
Test status
Simulation time 237853527 ps
CPU time 0.92 seconds
Started Jul 23 06:42:51 PM PDT 24
Finished Jul 23 06:42:56 PM PDT 24
Peak memory 206792 kb
Host smart-6b1e1a68-0ff5-4e32-b292-da08e044cfb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25695
55196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.2569555196
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.3128271509
Short name T1235
Test name
Test status
Simulation time 23292387846 ps
CPU time 20.91 seconds
Started Jul 23 06:42:53 PM PDT 24
Finished Jul 23 06:43:18 PM PDT 24
Peak memory 206828 kb
Host smart-426d834f-1fd1-4cb2-9287-3f830ff1e4af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31282
71509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.3128271509
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.371991647
Short name T1578
Test name
Test status
Simulation time 3282409051 ps
CPU time 3.54 seconds
Started Jul 23 06:42:54 PM PDT 24
Finished Jul 23 06:43:03 PM PDT 24
Peak memory 206812 kb
Host smart-ee60db61-ca1a-4750-9e1a-0b317b5abc1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37199
1647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.371991647
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.373077550
Short name T851
Test name
Test status
Simulation time 11293793547 ps
CPU time 310.88 seconds
Started Jul 23 06:42:53 PM PDT 24
Finished Jul 23 06:48:09 PM PDT 24
Peak memory 207008 kb
Host smart-f180decb-2427-4396-a996-3936ffdb9478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37307
7550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.373077550
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.865414784
Short name T2456
Test name
Test status
Simulation time 2818943725 ps
CPU time 76.63 seconds
Started Jul 23 06:42:52 PM PDT 24
Finished Jul 23 06:44:13 PM PDT 24
Peak memory 207064 kb
Host smart-c412c2f5-96bd-49b7-8cf7-b1547b6a1f9f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=865414784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.865414784
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.1040145395
Short name T620
Test name
Test status
Simulation time 248103645 ps
CPU time 0.92 seconds
Started Jul 23 06:42:53 PM PDT 24
Finished Jul 23 06:42:59 PM PDT 24
Peak memory 206744 kb
Host smart-4c62afa5-e051-4ab9-b22d-c2008078c539
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1040145395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.1040145395
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.2737108736
Short name T570
Test name
Test status
Simulation time 195522522 ps
CPU time 0.83 seconds
Started Jul 23 06:42:52 PM PDT 24
Finished Jul 23 06:42:58 PM PDT 24
Peak memory 206764 kb
Host smart-587df26b-19d5-42c5-89c6-03310c737fb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27371
08736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.2737108736
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.3823278161
Short name T1471
Test name
Test status
Simulation time 5573192060 ps
CPU time 49.65 seconds
Started Jul 23 06:42:53 PM PDT 24
Finished Jul 23 06:43:48 PM PDT 24
Peak memory 206976 kb
Host smart-de86acd6-9e16-4ab8-99ff-1490c6453fb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38232
78161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.3823278161
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.1637241642
Short name T212
Test name
Test status
Simulation time 4722954251 ps
CPU time 131.66 seconds
Started Jul 23 06:42:52 PM PDT 24
Finished Jul 23 06:45:08 PM PDT 24
Peak memory 206900 kb
Host smart-132bc44c-4173-4f89-95c5-5dce2363b471
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1637241642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.1637241642
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.304573130
Short name T2635
Test name
Test status
Simulation time 155457005 ps
CPU time 0.82 seconds
Started Jul 23 06:42:49 PM PDT 24
Finished Jul 23 06:42:54 PM PDT 24
Peak memory 206740 kb
Host smart-be5d008b-98fe-4624-a420-2dc7de5c0a57
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=304573130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.304573130
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.3921633560
Short name T1713
Test name
Test status
Simulation time 172150434 ps
CPU time 0.8 seconds
Started Jul 23 06:42:51 PM PDT 24
Finished Jul 23 06:42:56 PM PDT 24
Peak memory 206692 kb
Host smart-7c47be9f-1d99-493b-903e-b1afc2154eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39216
33560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.3921633560
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.3441775025
Short name T141
Test name
Test status
Simulation time 222425216 ps
CPU time 0.88 seconds
Started Jul 23 06:42:52 PM PDT 24
Finished Jul 23 06:42:58 PM PDT 24
Peak memory 206784 kb
Host smart-ed35c5be-3f7b-49bd-baf7-421ee541522b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34417
75025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.3441775025
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.3941289973
Short name T1097
Test name
Test status
Simulation time 204639496 ps
CPU time 0.87 seconds
Started Jul 23 06:42:52 PM PDT 24
Finished Jul 23 06:42:58 PM PDT 24
Peak memory 206752 kb
Host smart-07750d2b-e088-4c6f-920c-4593155de593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39412
89973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.3941289973
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.721905429
Short name T320
Test name
Test status
Simulation time 211302858 ps
CPU time 0.84 seconds
Started Jul 23 06:42:53 PM PDT 24
Finished Jul 23 06:42:59 PM PDT 24
Peak memory 206784 kb
Host smart-208a4b70-317a-4ad3-9227-c0595510c413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72190
5429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.721905429
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.2080623215
Short name T2567
Test name
Test status
Simulation time 176101400 ps
CPU time 0.83 seconds
Started Jul 23 06:42:53 PM PDT 24
Finished Jul 23 06:43:00 PM PDT 24
Peak memory 206756 kb
Host smart-be7d7863-d4f5-4524-8cf6-14b6489cec73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20806
23215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.2080623215
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.2158677613
Short name T670
Test name
Test status
Simulation time 152949167 ps
CPU time 0.76 seconds
Started Jul 23 06:42:52 PM PDT 24
Finished Jul 23 06:42:57 PM PDT 24
Peak memory 206760 kb
Host smart-01fe84c0-d132-4e76-9168-9996344ee56f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21586
77613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.2158677613
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.780990327
Short name T1109
Test name
Test status
Simulation time 241472431 ps
CPU time 0.91 seconds
Started Jul 23 06:42:51 PM PDT 24
Finished Jul 23 06:42:56 PM PDT 24
Peak memory 206756 kb
Host smart-497a9e9b-e7e5-4074-b893-761cd0915caf
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=780990327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.780990327
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.2234206359
Short name T739
Test name
Test status
Simulation time 161830716 ps
CPU time 0.77 seconds
Started Jul 23 06:42:52 PM PDT 24
Finished Jul 23 06:42:57 PM PDT 24
Peak memory 206772 kb
Host smart-7feea215-5b7c-434d-bec4-d24981989670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22342
06359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.2234206359
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.3891136438
Short name T1773
Test name
Test status
Simulation time 35524415 ps
CPU time 0.62 seconds
Started Jul 23 06:42:53 PM PDT 24
Finished Jul 23 06:42:59 PM PDT 24
Peak memory 206704 kb
Host smart-929486ab-23b1-4971-8faf-e0c6b8fb6917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38911
36438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.3891136438
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.505389871
Short name T2501
Test name
Test status
Simulation time 6329701110 ps
CPU time 13.77 seconds
Started Jul 23 06:42:52 PM PDT 24
Finished Jul 23 06:43:10 PM PDT 24
Peak memory 206952 kb
Host smart-5db52c39-f3d9-40c7-beb5-a27e650e10c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50538
9871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.505389871
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.1688931099
Short name T50
Test name
Test status
Simulation time 188513269 ps
CPU time 0.81 seconds
Started Jul 23 06:42:52 PM PDT 24
Finished Jul 23 06:42:57 PM PDT 24
Peak memory 206728 kb
Host smart-bb9705a8-ce43-4cc4-ba4d-daf08e3e6f63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16889
31099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.1688931099
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.2373764535
Short name T394
Test name
Test status
Simulation time 187388339 ps
CPU time 0.8 seconds
Started Jul 23 06:42:51 PM PDT 24
Finished Jul 23 06:42:56 PM PDT 24
Peak memory 206744 kb
Host smart-23c8d2a9-3656-4655-b71a-45e7bbabfb45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23737
64535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.2373764535
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.2583064955
Short name T1337
Test name
Test status
Simulation time 171095146 ps
CPU time 0.83 seconds
Started Jul 23 06:42:56 PM PDT 24
Finished Jul 23 06:43:03 PM PDT 24
Peak memory 206760 kb
Host smart-c5eedcda-8b33-4565-998b-a5e7494a28c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25830
64955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.2583064955
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.4130064404
Short name T1974
Test name
Test status
Simulation time 157426344 ps
CPU time 0.84 seconds
Started Jul 23 06:42:54 PM PDT 24
Finished Jul 23 06:43:00 PM PDT 24
Peak memory 206728 kb
Host smart-44927555-2499-4936-baa4-f819c744e87a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41300
64404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.4130064404
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.1196780744
Short name T1314
Test name
Test status
Simulation time 160416026 ps
CPU time 0.76 seconds
Started Jul 23 06:42:57 PM PDT 24
Finished Jul 23 06:43:03 PM PDT 24
Peak memory 206744 kb
Host smart-4b157988-8caa-4b25-a94b-79a259aaaaa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11967
80744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.1196780744
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.3091513861
Short name T1657
Test name
Test status
Simulation time 165026210 ps
CPU time 0.78 seconds
Started Jul 23 06:42:56 PM PDT 24
Finished Jul 23 06:43:03 PM PDT 24
Peak memory 206752 kb
Host smart-bb6bc864-71bd-4486-a026-c0e7a36c2b19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30915
13861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.3091513861
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.3099018802
Short name T838
Test name
Test status
Simulation time 151042262 ps
CPU time 0.81 seconds
Started Jul 23 06:42:56 PM PDT 24
Finished Jul 23 06:43:02 PM PDT 24
Peak memory 206772 kb
Host smart-41aa4751-002b-4846-aa67-5c79b8de097a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30990
18802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.3099018802
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.1840810834
Short name T51
Test name
Test status
Simulation time 225675193 ps
CPU time 1.08 seconds
Started Jul 23 06:42:56 PM PDT 24
Finished Jul 23 06:43:03 PM PDT 24
Peak memory 206724 kb
Host smart-3b257360-72fb-4834-a6f7-e134884159a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18408
10834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.1840810834
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.1254584850
Short name T1873
Test name
Test status
Simulation time 5041813955 ps
CPU time 135.06 seconds
Started Jul 23 06:42:54 PM PDT 24
Finished Jul 23 06:45:15 PM PDT 24
Peak memory 206916 kb
Host smart-a3b7ceee-22ce-4b3b-abf2-16084c0f380a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1254584850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.1254584850
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.3568574614
Short name T149
Test name
Test status
Simulation time 206331419 ps
CPU time 0.86 seconds
Started Jul 23 06:42:58 PM PDT 24
Finished Jul 23 06:43:04 PM PDT 24
Peak memory 206740 kb
Host smart-0aec4a19-3447-4944-88e7-ed669bda145c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35685
74614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.3568574614
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.4143746890
Short name T1560
Test name
Test status
Simulation time 161439985 ps
CPU time 0.81 seconds
Started Jul 23 06:42:57 PM PDT 24
Finished Jul 23 06:43:03 PM PDT 24
Peak memory 206756 kb
Host smart-9be8d88e-bf3c-43d0-99e8-1d4ca68c1ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41437
46890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.4143746890
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.254962120
Short name T2328
Test name
Test status
Simulation time 1040253225 ps
CPU time 2.06 seconds
Started Jul 23 06:42:56 PM PDT 24
Finished Jul 23 06:43:03 PM PDT 24
Peak memory 206900 kb
Host smart-60ee4e66-fcef-47ed-b81c-97b7b805578d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25496
2120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.254962120
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.2130400020
Short name T2485
Test name
Test status
Simulation time 4484916367 ps
CPU time 125.28 seconds
Started Jul 23 06:42:55 PM PDT 24
Finished Jul 23 06:45:06 PM PDT 24
Peak memory 206836 kb
Host smart-ebeeeb41-6035-4946-b7ee-ea7476bb684a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21304
00020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.2130400020
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.3576715675
Short name T611
Test name
Test status
Simulation time 35373372 ps
CPU time 0.73 seconds
Started Jul 23 06:43:06 PM PDT 24
Finished Jul 23 06:43:11 PM PDT 24
Peak memory 206744 kb
Host smart-bef59d06-6a2a-4479-bc16-a083b527ef64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3576715675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.3576715675
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.3284474274
Short name T970
Test name
Test status
Simulation time 4246957313 ps
CPU time 4.67 seconds
Started Jul 23 06:42:56 PM PDT 24
Finished Jul 23 06:43:06 PM PDT 24
Peak memory 206732 kb
Host smart-76ec8671-f810-40b1-8131-bed841c12bd1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3284474274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.3284474274
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.2684686128
Short name T2161
Test name
Test status
Simulation time 13329379123 ps
CPU time 11.74 seconds
Started Jul 23 06:42:56 PM PDT 24
Finished Jul 23 06:43:14 PM PDT 24
Peak memory 206976 kb
Host smart-7ba9141d-751d-43c1-879b-a5d1e617715d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2684686128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.2684686128
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.726159700
Short name T2553
Test name
Test status
Simulation time 23398865777 ps
CPU time 24.25 seconds
Started Jul 23 06:42:56 PM PDT 24
Finished Jul 23 06:43:26 PM PDT 24
Peak memory 206836 kb
Host smart-22e14177-33b8-4401-a5cc-7b9adc08b9f2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=726159700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.726159700
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.3844309763
Short name T805
Test name
Test status
Simulation time 166493072 ps
CPU time 0.8 seconds
Started Jul 23 06:42:55 PM PDT 24
Finished Jul 23 06:43:01 PM PDT 24
Peak memory 206736 kb
Host smart-447dcc36-5894-4fd7-aed9-451714028db3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38443
09763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.3844309763
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.4210993658
Short name T1883
Test name
Test status
Simulation time 139500520 ps
CPU time 0.79 seconds
Started Jul 23 06:42:55 PM PDT 24
Finished Jul 23 06:43:01 PM PDT 24
Peak memory 206748 kb
Host smart-4b1e42da-edea-4b22-b151-7712b3a41753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42109
93658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.4210993658
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.655678007
Short name T1745
Test name
Test status
Simulation time 338348881 ps
CPU time 1.2 seconds
Started Jul 23 06:42:57 PM PDT 24
Finished Jul 23 06:43:04 PM PDT 24
Peak memory 206752 kb
Host smart-d427f3ef-a587-4c3c-81c0-d7d08c2a2272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65567
8007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.655678007
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.3960078284
Short name T2273
Test name
Test status
Simulation time 351150721 ps
CPU time 1.01 seconds
Started Jul 23 06:42:55 PM PDT 24
Finished Jul 23 06:43:02 PM PDT 24
Peak memory 206740 kb
Host smart-da2fb9d5-d240-4ad6-b9aa-bf5c147a0783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39600
78284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.3960078284
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.630607156
Short name T1169
Test name
Test status
Simulation time 22571579972 ps
CPU time 41.17 seconds
Started Jul 23 06:42:59 PM PDT 24
Finished Jul 23 06:43:46 PM PDT 24
Peak memory 206952 kb
Host smart-ab684631-fcd1-4986-afc5-fa9b02135ff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63060
7156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.630607156
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.3091958547
Short name T868
Test name
Test status
Simulation time 322252764 ps
CPU time 1.17 seconds
Started Jul 23 06:42:58 PM PDT 24
Finished Jul 23 06:43:04 PM PDT 24
Peak memory 206784 kb
Host smart-e16f1137-8bdf-4860-8c4a-cbbeb1f857d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30919
58547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.3091958547
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.3426859575
Short name T1258
Test name
Test status
Simulation time 149204767 ps
CPU time 0.76 seconds
Started Jul 23 06:43:01 PM PDT 24
Finished Jul 23 06:43:06 PM PDT 24
Peak memory 206732 kb
Host smart-0c454867-aa3c-4910-82de-5401f93c374a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34268
59575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.3426859575
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.129527069
Short name T926
Test name
Test status
Simulation time 32851026 ps
CPU time 0.75 seconds
Started Jul 23 06:42:57 PM PDT 24
Finished Jul 23 06:43:04 PM PDT 24
Peak memory 206756 kb
Host smart-fad43620-cd14-4454-8c9c-e94ed271e230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12952
7069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.129527069
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.3996942
Short name T812
Test name
Test status
Simulation time 849475476 ps
CPU time 2.02 seconds
Started Jul 23 06:42:57 PM PDT 24
Finished Jul 23 06:43:05 PM PDT 24
Peak memory 206844 kb
Host smart-80c907a5-9067-4785-843f-3e1270cf6532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39969
42 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.3996942
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.3456975127
Short name T552
Test name
Test status
Simulation time 186451220 ps
CPU time 2.16 seconds
Started Jul 23 06:42:57 PM PDT 24
Finished Jul 23 06:43:05 PM PDT 24
Peak memory 206748 kb
Host smart-2aa9dd31-ee24-4ef0-8265-f9801cab2235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34569
75127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.3456975127
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.4183447209
Short name T1154
Test name
Test status
Simulation time 204923005 ps
CPU time 0.88 seconds
Started Jul 23 06:42:57 PM PDT 24
Finished Jul 23 06:43:03 PM PDT 24
Peak memory 206748 kb
Host smart-9d1170f6-5cd4-4186-9f79-7cc60676510d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41834
47209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.4183447209
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.2150330082
Short name T2069
Test name
Test status
Simulation time 133685166 ps
CPU time 0.8 seconds
Started Jul 23 06:42:56 PM PDT 24
Finished Jul 23 06:43:03 PM PDT 24
Peak memory 206716 kb
Host smart-7451c2b1-830b-48bc-9922-d291fe3ad345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21503
30082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.2150330082
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.359200067
Short name T1086
Test name
Test status
Simulation time 243274104 ps
CPU time 0.9 seconds
Started Jul 23 06:42:56 PM PDT 24
Finished Jul 23 06:43:03 PM PDT 24
Peak memory 206748 kb
Host smart-696b067d-b046-4032-aaeb-ed9d75d724fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35920
0067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.359200067
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.3555093254
Short name T216
Test name
Test status
Simulation time 5812801183 ps
CPU time 58.11 seconds
Started Jul 23 06:42:56 PM PDT 24
Finished Jul 23 06:43:59 PM PDT 24
Peak memory 206968 kb
Host smart-084f2a6d-7acc-486b-8cc3-1fe9cb83afeb
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3555093254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.3555093254
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_iso_retraction.3598691003
Short name T858
Test name
Test status
Simulation time 6885976204 ps
CPU time 23.83 seconds
Started Jul 23 06:43:02 PM PDT 24
Finished Jul 23 06:43:30 PM PDT 24
Peak memory 206948 kb
Host smart-375f4e8b-e636-44f4-ac03-7633f0cf6393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35986
91003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.3598691003
Directory /workspace/27.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.4030502347
Short name T2329
Test name
Test status
Simulation time 174012039 ps
CPU time 0.85 seconds
Started Jul 23 06:43:03 PM PDT 24
Finished Jul 23 06:43:07 PM PDT 24
Peak memory 206756 kb
Host smart-24e39a07-1b27-4e03-9a33-c7fe8e8c1028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40305
02347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.4030502347
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.224754612
Short name T2425
Test name
Test status
Simulation time 23311781700 ps
CPU time 23.12 seconds
Started Jul 23 06:43:00 PM PDT 24
Finished Jul 23 06:43:28 PM PDT 24
Peak memory 206808 kb
Host smart-50efde53-b101-45a6-ba4a-aad932b43358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22475
4612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.224754612
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.1658805639
Short name T1928
Test name
Test status
Simulation time 3330377095 ps
CPU time 3.89 seconds
Started Jul 23 06:43:02 PM PDT 24
Finished Jul 23 06:43:10 PM PDT 24
Peak memory 206828 kb
Host smart-a889337e-2a76-4e8d-8c03-17387363474e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16588
05639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.1658805639
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.1064840490
Short name T2416
Test name
Test status
Simulation time 7509523696 ps
CPU time 50.03 seconds
Started Jul 23 06:43:04 PM PDT 24
Finished Jul 23 06:43:58 PM PDT 24
Peak memory 206936 kb
Host smart-8a0fd034-95ff-44bf-a61c-e623a77478f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10648
40490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.1064840490
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.2574505290
Short name T2393
Test name
Test status
Simulation time 3981168186 ps
CPU time 104.58 seconds
Started Jul 23 06:43:04 PM PDT 24
Finished Jul 23 06:44:52 PM PDT 24
Peak memory 206880 kb
Host smart-bc3a25c9-84c0-4538-9872-5ce37c9ec16e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2574505290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.2574505290
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.1078226353
Short name T1796
Test name
Test status
Simulation time 244857176 ps
CPU time 0.91 seconds
Started Jul 23 06:43:02 PM PDT 24
Finished Jul 23 06:43:07 PM PDT 24
Peak memory 206768 kb
Host smart-5902b8ba-e93d-4ec1-b0cc-42dab99a94bf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1078226353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.1078226353
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.2365031061
Short name T493
Test name
Test status
Simulation time 203975856 ps
CPU time 0.86 seconds
Started Jul 23 06:43:04 PM PDT 24
Finished Jul 23 06:43:09 PM PDT 24
Peak memory 206756 kb
Host smart-e539da02-c750-427c-8c68-0ab1163dbb7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23650
31061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.2365031061
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.2224149897
Short name T1276
Test name
Test status
Simulation time 7045401955 ps
CPU time 189.04 seconds
Started Jul 23 06:43:05 PM PDT 24
Finished Jul 23 06:46:18 PM PDT 24
Peak memory 206896 kb
Host smart-a8c8621b-eec2-4c01-9baa-86318fe7f1e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22241
49897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.2224149897
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.1770281622
Short name T1482
Test name
Test status
Simulation time 5167034595 ps
CPU time 39.94 seconds
Started Jul 23 06:43:03 PM PDT 24
Finished Jul 23 06:43:46 PM PDT 24
Peak memory 206932 kb
Host smart-341ee1ea-a4a4-41f6-8bc7-3ee30cb7a2c5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1770281622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.1770281622
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.1531726886
Short name T1053
Test name
Test status
Simulation time 153316045 ps
CPU time 0.78 seconds
Started Jul 23 06:43:01 PM PDT 24
Finished Jul 23 06:43:06 PM PDT 24
Peak memory 206720 kb
Host smart-8b8b0875-fa0a-4260-b58c-230bf6c084b1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1531726886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.1531726886
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.490347263
Short name T2436
Test name
Test status
Simulation time 188888510 ps
CPU time 0.81 seconds
Started Jul 23 06:43:00 PM PDT 24
Finished Jul 23 06:43:06 PM PDT 24
Peak memory 206756 kb
Host smart-361c8939-c86a-42c2-83c1-dc818899c04c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49034
7263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.490347263
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.47868489
Short name T1865
Test name
Test status
Simulation time 165578889 ps
CPU time 0.81 seconds
Started Jul 23 06:43:00 PM PDT 24
Finished Jul 23 06:43:06 PM PDT 24
Peak memory 206768 kb
Host smart-670c65be-b521-4150-8d2a-7ca0b0c9e87b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47868
489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.47868489
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.580690530
Short name T1215
Test name
Test status
Simulation time 162834221 ps
CPU time 0.9 seconds
Started Jul 23 06:43:01 PM PDT 24
Finished Jul 23 06:43:06 PM PDT 24
Peak memory 206768 kb
Host smart-896dd9e2-7471-4100-b552-4917dcd65099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58069
0530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.580690530
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.3154269794
Short name T378
Test name
Test status
Simulation time 201325070 ps
CPU time 0.84 seconds
Started Jul 23 06:43:01 PM PDT 24
Finished Jul 23 06:43:06 PM PDT 24
Peak memory 206756 kb
Host smart-3b7c1dae-a3c3-494d-8611-3ab6110aedcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31542
69794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.3154269794
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.3731965457
Short name T1175
Test name
Test status
Simulation time 171189784 ps
CPU time 0.76 seconds
Started Jul 23 06:43:00 PM PDT 24
Finished Jul 23 06:43:06 PM PDT 24
Peak memory 206756 kb
Host smart-ced9968e-b196-4002-b258-2f004759101d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37319
65457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.3731965457
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.2974962229
Short name T1867
Test name
Test status
Simulation time 160235874 ps
CPU time 0.83 seconds
Started Jul 23 06:43:01 PM PDT 24
Finished Jul 23 06:43:06 PM PDT 24
Peak memory 206796 kb
Host smart-291757f1-ba41-4349-a413-e137e551844a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29749
62229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.2974962229
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.3363527310
Short name T2489
Test name
Test status
Simulation time 271300285 ps
CPU time 1.05 seconds
Started Jul 23 06:43:01 PM PDT 24
Finished Jul 23 06:43:06 PM PDT 24
Peak memory 206748 kb
Host smart-f9509b5f-7e43-4a4b-9fe7-bd41424a52bd
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3363527310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.3363527310
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.1276802694
Short name T1767
Test name
Test status
Simulation time 142469296 ps
CPU time 0.8 seconds
Started Jul 23 06:43:00 PM PDT 24
Finished Jul 23 06:43:06 PM PDT 24
Peak memory 206756 kb
Host smart-1dc657b9-8bf3-4f5d-807e-12dda3aa58d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12768
02694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.1276802694
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.3198901935
Short name T463
Test name
Test status
Simulation time 115321465 ps
CPU time 0.73 seconds
Started Jul 23 06:43:02 PM PDT 24
Finished Jul 23 06:43:07 PM PDT 24
Peak memory 206756 kb
Host smart-66b7e472-c4fa-4332-9b8f-9a28c2ffc80a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31989
01935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.3198901935
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.115044643
Short name T1454
Test name
Test status
Simulation time 15539800788 ps
CPU time 32.73 seconds
Started Jul 23 06:43:04 PM PDT 24
Finished Jul 23 06:43:40 PM PDT 24
Peak memory 206984 kb
Host smart-2d625d66-d409-4840-afdd-f34fa32ca20e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11504
4643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.115044643
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.3181374312
Short name T2350
Test name
Test status
Simulation time 177376728 ps
CPU time 0.88 seconds
Started Jul 23 06:43:01 PM PDT 24
Finished Jul 23 06:43:06 PM PDT 24
Peak memory 206744 kb
Host smart-628a9705-dae7-493b-9194-18c6dc990310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31813
74312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.3181374312
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.224486615
Short name T2066
Test name
Test status
Simulation time 179784536 ps
CPU time 0.81 seconds
Started Jul 23 06:43:02 PM PDT 24
Finished Jul 23 06:43:07 PM PDT 24
Peak memory 206772 kb
Host smart-be833564-8035-4b78-a540-b70c221f04f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22448
6615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.224486615
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.2542432334
Short name T443
Test name
Test status
Simulation time 195688793 ps
CPU time 0.83 seconds
Started Jul 23 06:43:01 PM PDT 24
Finished Jul 23 06:43:06 PM PDT 24
Peak memory 206740 kb
Host smart-0b51610d-de11-468f-827a-580734cf1de2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25424
32334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.2542432334
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.1592832376
Short name T2013
Test name
Test status
Simulation time 243709724 ps
CPU time 0.9 seconds
Started Jul 23 06:43:02 PM PDT 24
Finished Jul 23 06:43:06 PM PDT 24
Peak memory 206756 kb
Host smart-52b77b4b-f0a5-47a5-894c-ffe5aa7476b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15928
32376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.1592832376
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.1171633456
Short name T2049
Test name
Test status
Simulation time 217009939 ps
CPU time 0.88 seconds
Started Jul 23 06:43:02 PM PDT 24
Finished Jul 23 06:43:07 PM PDT 24
Peak memory 206740 kb
Host smart-f9af8e27-ef56-447c-bd78-e2c0a5a16fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11716
33456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.1171633456
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.418693556
Short name T1727
Test name
Test status
Simulation time 147469950 ps
CPU time 0.76 seconds
Started Jul 23 06:43:04 PM PDT 24
Finished Jul 23 06:43:08 PM PDT 24
Peak memory 206784 kb
Host smart-6b64aa9e-fcf3-45aa-aea1-aedf676d452d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41869
3556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.418693556
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.881745100
Short name T319
Test name
Test status
Simulation time 144655600 ps
CPU time 0.87 seconds
Started Jul 23 06:43:02 PM PDT 24
Finished Jul 23 06:43:07 PM PDT 24
Peak memory 206764 kb
Host smart-0455989f-c37b-412d-9aba-b1d883781aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88174
5100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.881745100
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.3727177504
Short name T1066
Test name
Test status
Simulation time 240505495 ps
CPU time 0.96 seconds
Started Jul 23 06:43:07 PM PDT 24
Finished Jul 23 06:43:12 PM PDT 24
Peak memory 206752 kb
Host smart-727df8c9-53b6-485e-b71f-70ef9d518dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37271
77504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.3727177504
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.2140747467
Short name T2016
Test name
Test status
Simulation time 5469242445 ps
CPU time 153.07 seconds
Started Jul 23 06:43:10 PM PDT 24
Finished Jul 23 06:45:46 PM PDT 24
Peak memory 206852 kb
Host smart-b9af4aa0-b469-49a0-98a1-721b84176953
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2140747467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.2140747467
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.2187256717
Short name T678
Test name
Test status
Simulation time 188615542 ps
CPU time 0.88 seconds
Started Jul 23 06:43:09 PM PDT 24
Finished Jul 23 06:43:13 PM PDT 24
Peak memory 206740 kb
Host smart-41cbc34a-120a-41e6-8dbf-a1560a4dde79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21872
56717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.2187256717
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.2162969918
Short name T2672
Test name
Test status
Simulation time 194970774 ps
CPU time 0.89 seconds
Started Jul 23 06:43:06 PM PDT 24
Finished Jul 23 06:43:10 PM PDT 24
Peak memory 206748 kb
Host smart-85df8e3b-edf0-4a57-b0f3-58e502e92c30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21629
69918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.2162969918
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.2157938021
Short name T2270
Test name
Test status
Simulation time 881257034 ps
CPU time 2.06 seconds
Started Jul 23 06:43:06 PM PDT 24
Finished Jul 23 06:43:12 PM PDT 24
Peak memory 206868 kb
Host smart-c98ee592-0ced-4610-882e-097cb0f61348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21579
38021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.2157938021
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.1378023296
Short name T1210
Test name
Test status
Simulation time 7032089156 ps
CPU time 67.6 seconds
Started Jul 23 06:43:07 PM PDT 24
Finished Jul 23 06:44:18 PM PDT 24
Peak memory 206968 kb
Host smart-7ff433af-4416-492f-b6d6-4b1464efcf8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13780
23296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.1378023296
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.1340378353
Short name T1130
Test name
Test status
Simulation time 51647593 ps
CPU time 0.73 seconds
Started Jul 23 06:43:24 PM PDT 24
Finished Jul 23 06:43:29 PM PDT 24
Peak memory 206744 kb
Host smart-9413e8c9-9600-4d60-bff6-375abfdd68af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1340378353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.1340378353
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.602288752
Short name T1919
Test name
Test status
Simulation time 4102364526 ps
CPU time 5.76 seconds
Started Jul 23 06:43:06 PM PDT 24
Finished Jul 23 06:43:15 PM PDT 24
Peak memory 206816 kb
Host smart-178a157e-5036-443f-ace0-bd197b796ef2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=602288752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.602288752
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.846301144
Short name T1874
Test name
Test status
Simulation time 13360789794 ps
CPU time 15.16 seconds
Started Jul 23 06:43:08 PM PDT 24
Finished Jul 23 06:43:27 PM PDT 24
Peak memory 206820 kb
Host smart-52be9949-d038-4dec-aee0-ee18932d1415
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=846301144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.846301144
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.258016872
Short name T406
Test name
Test status
Simulation time 23369272157 ps
CPU time 25.22 seconds
Started Jul 23 06:43:06 PM PDT 24
Finished Jul 23 06:43:35 PM PDT 24
Peak memory 206852 kb
Host smart-22bb0f41-1e4e-4380-bd75-6d9af84a9312
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=258016872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.258016872
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.2517032978
Short name T1127
Test name
Test status
Simulation time 163258797 ps
CPU time 0.8 seconds
Started Jul 23 06:43:08 PM PDT 24
Finished Jul 23 06:43:12 PM PDT 24
Peak memory 206744 kb
Host smart-a4cc3390-41d7-4521-a0cf-b682207f13a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25170
32978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.2517032978
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.3568062368
Short name T844
Test name
Test status
Simulation time 184622082 ps
CPU time 0.79 seconds
Started Jul 23 06:43:09 PM PDT 24
Finished Jul 23 06:43:13 PM PDT 24
Peak memory 206760 kb
Host smart-77196cca-2840-42df-a578-2bfbbf930e87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35680
62368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.3568062368
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.2578075547
Short name T1759
Test name
Test status
Simulation time 202948758 ps
CPU time 0.91 seconds
Started Jul 23 06:43:08 PM PDT 24
Finished Jul 23 06:43:12 PM PDT 24
Peak memory 206736 kb
Host smart-e5cc7379-01cb-4f57-8fc1-7249c6303c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25780
75547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.2578075547
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.2854636814
Short name T961
Test name
Test status
Simulation time 943637965 ps
CPU time 2.38 seconds
Started Jul 23 06:43:07 PM PDT 24
Finished Jul 23 06:43:13 PM PDT 24
Peak memory 206896 kb
Host smart-1c3619ae-2346-4df9-847c-6e853307dd6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28546
36814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.2854636814
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.3550922082
Short name T1185
Test name
Test status
Simulation time 6016370415 ps
CPU time 11.48 seconds
Started Jul 23 06:43:08 PM PDT 24
Finished Jul 23 06:43:23 PM PDT 24
Peak memory 206988 kb
Host smart-b7d3d19d-e531-41b7-b813-9482d6361936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35509
22082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.3550922082
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.1138435499
Short name T1070
Test name
Test status
Simulation time 367927174 ps
CPU time 1.19 seconds
Started Jul 23 06:43:05 PM PDT 24
Finished Jul 23 06:43:10 PM PDT 24
Peak memory 206768 kb
Host smart-cc6871e9-9ebf-47dc-93ff-b88cd7933916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11384
35499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.1138435499
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.209521043
Short name T38
Test name
Test status
Simulation time 178100992 ps
CPU time 0.81 seconds
Started Jul 23 06:43:07 PM PDT 24
Finished Jul 23 06:43:11 PM PDT 24
Peak memory 206756 kb
Host smart-1d6014f2-3f25-4b03-9ee1-d4d9369802fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20952
1043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.209521043
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.1720788263
Short name T1593
Test name
Test status
Simulation time 58607674 ps
CPU time 0.69 seconds
Started Jul 23 06:43:08 PM PDT 24
Finished Jul 23 06:43:12 PM PDT 24
Peak memory 206740 kb
Host smart-fcd23610-4750-4665-a5be-d10e36b4c29c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17207
88263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.1720788263
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.1697406787
Short name T1695
Test name
Test status
Simulation time 862809075 ps
CPU time 2.07 seconds
Started Jul 23 06:43:06 PM PDT 24
Finished Jul 23 06:43:12 PM PDT 24
Peak memory 206840 kb
Host smart-a4f12c13-7606-43c1-af7c-fa81d2bff091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16974
06787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.1697406787
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.1019331509
Short name T1907
Test name
Test status
Simulation time 388578002 ps
CPU time 2.32 seconds
Started Jul 23 06:43:06 PM PDT 24
Finished Jul 23 06:43:12 PM PDT 24
Peak memory 206904 kb
Host smart-d47a6493-ded1-438c-90e8-362b002e7a99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10193
31509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.1019331509
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.4040458253
Short name T1880
Test name
Test status
Simulation time 186898250 ps
CPU time 0.83 seconds
Started Jul 23 06:43:06 PM PDT 24
Finished Jul 23 06:43:11 PM PDT 24
Peak memory 206748 kb
Host smart-abf57b13-6bd9-415e-b4c9-5cec3b9c9955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40404
58253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.4040458253
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.3927530734
Short name T413
Test name
Test status
Simulation time 145104766 ps
CPU time 0.75 seconds
Started Jul 23 06:43:08 PM PDT 24
Finished Jul 23 06:43:12 PM PDT 24
Peak memory 206756 kb
Host smart-fc1c1f1c-14ff-498c-8e7b-1a11e8d63d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39275
30734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.3927530734
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.3388899205
Short name T1431
Test name
Test status
Simulation time 286582820 ps
CPU time 1 seconds
Started Jul 23 06:43:08 PM PDT 24
Finished Jul 23 06:43:13 PM PDT 24
Peak memory 206748 kb
Host smart-8aebdc2b-3871-43df-9901-9dc6b1850014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33888
99205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.3388899205
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.3281497194
Short name T2696
Test name
Test status
Simulation time 8681611124 ps
CPU time 83.93 seconds
Started Jul 23 06:43:08 PM PDT 24
Finished Jul 23 06:44:35 PM PDT 24
Peak memory 206960 kb
Host smart-62344c55-dc94-4a79-976b-88cca4cea112
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3281497194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.3281497194
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_iso_retraction.4282015376
Short name T1305
Test name
Test status
Simulation time 5862814834 ps
CPU time 55.07 seconds
Started Jul 23 06:43:10 PM PDT 24
Finished Jul 23 06:44:08 PM PDT 24
Peak memory 206964 kb
Host smart-bbbe583b-c425-422c-b48f-5d660011ba55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42820
15376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_iso_retraction.4282015376
Directory /workspace/28.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.168976025
Short name T1386
Test name
Test status
Simulation time 262901013 ps
CPU time 0.9 seconds
Started Jul 23 06:43:06 PM PDT 24
Finished Jul 23 06:43:10 PM PDT 24
Peak memory 206772 kb
Host smart-11a20717-64cf-49a8-94ae-ab48071683c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16897
6025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.168976025
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.587991703
Short name T2335
Test name
Test status
Simulation time 23299815019 ps
CPU time 22.66 seconds
Started Jul 23 06:43:07 PM PDT 24
Finished Jul 23 06:43:33 PM PDT 24
Peak memory 206776 kb
Host smart-99c4608f-4a84-49e4-94a0-25099ac71e05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58799
1703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.587991703
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.674908342
Short name T2151
Test name
Test status
Simulation time 3311678376 ps
CPU time 4.03 seconds
Started Jul 23 06:43:09 PM PDT 24
Finished Jul 23 06:43:16 PM PDT 24
Peak memory 206824 kb
Host smart-46da22fc-fdc4-4337-8dc2-a2413a1d70c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67490
8342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.674908342
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.1754201150
Short name T535
Test name
Test status
Simulation time 6839708914 ps
CPU time 64.45 seconds
Started Jul 23 06:43:06 PM PDT 24
Finished Jul 23 06:44:14 PM PDT 24
Peak memory 206980 kb
Host smart-1d02dab1-0ed2-4b12-8040-56eb914ab44b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17542
01150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.1754201150
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.2315737531
Short name T490
Test name
Test status
Simulation time 7075754723 ps
CPU time 64.6 seconds
Started Jul 23 06:43:13 PM PDT 24
Finished Jul 23 06:44:20 PM PDT 24
Peak memory 206972 kb
Host smart-7f14ce23-e1b1-4e58-9d7f-d2da53b2cc95
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2315737531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.2315737531
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.531301228
Short name T585
Test name
Test status
Simulation time 241795772 ps
CPU time 1 seconds
Started Jul 23 06:43:14 PM PDT 24
Finished Jul 23 06:43:17 PM PDT 24
Peak memory 206756 kb
Host smart-036b0bbd-2d63-46d4-a2ab-ca7095271455
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=531301228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.531301228
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.825452631
Short name T863
Test name
Test status
Simulation time 221851311 ps
CPU time 0.99 seconds
Started Jul 23 06:43:14 PM PDT 24
Finished Jul 23 06:43:17 PM PDT 24
Peak memory 206760 kb
Host smart-e00996e3-c1db-44f6-a853-aba071bd9866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82545
2631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.825452631
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.999906498
Short name T2351
Test name
Test status
Simulation time 4780569496 ps
CPU time 32.98 seconds
Started Jul 23 06:43:14 PM PDT 24
Finished Jul 23 06:43:49 PM PDT 24
Peak memory 206932 kb
Host smart-c458d277-2ebe-4a1c-a7a1-5d028139ae53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99990
6498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.999906498
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.3165599537
Short name T988
Test name
Test status
Simulation time 4912235527 ps
CPU time 127.93 seconds
Started Jul 23 06:43:14 PM PDT 24
Finished Jul 23 06:45:23 PM PDT 24
Peak memory 206900 kb
Host smart-d5e3e515-c4a4-4849-bbd3-7785cc6c3e09
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3165599537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.3165599537
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.2981515328
Short name T397
Test name
Test status
Simulation time 170899056 ps
CPU time 0.82 seconds
Started Jul 23 06:43:13 PM PDT 24
Finished Jul 23 06:43:16 PM PDT 24
Peak memory 206776 kb
Host smart-00ee1801-9009-4937-8e66-2d8d988ba764
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2981515328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.2981515328
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.931442131
Short name T1023
Test name
Test status
Simulation time 166249310 ps
CPU time 0.81 seconds
Started Jul 23 06:43:15 PM PDT 24
Finished Jul 23 06:43:17 PM PDT 24
Peak memory 206772 kb
Host smart-d47f0c95-0af6-4c7c-88fb-587e03bfcf4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93144
2131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.931442131
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.117960397
Short name T132
Test name
Test status
Simulation time 232264047 ps
CPU time 0.94 seconds
Started Jul 23 06:43:14 PM PDT 24
Finished Jul 23 06:43:17 PM PDT 24
Peak memory 206752 kb
Host smart-6a734b3c-bca9-4a50-8ca9-14d44cbfbbe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11796
0397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.117960397
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.2460143191
Short name T2091
Test name
Test status
Simulation time 209858859 ps
CPU time 0.86 seconds
Started Jul 23 06:43:15 PM PDT 24
Finished Jul 23 06:43:17 PM PDT 24
Peak memory 206764 kb
Host smart-fbe1585d-3114-4bb3-8b96-b21448e7a029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24601
43191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.2460143191
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.3143400552
Short name T2443
Test name
Test status
Simulation time 200713285 ps
CPU time 0.8 seconds
Started Jul 23 06:43:12 PM PDT 24
Finished Jul 23 06:43:14 PM PDT 24
Peak memory 206736 kb
Host smart-2376b643-bca0-4666-9bb3-4d06dc570593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31434
00552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.3143400552
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.2828614660
Short name T603
Test name
Test status
Simulation time 147375601 ps
CPU time 0.75 seconds
Started Jul 23 06:43:13 PM PDT 24
Finished Jul 23 06:43:15 PM PDT 24
Peak memory 206668 kb
Host smart-19c11306-9bff-4ed0-9887-75fd73117231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28286
14660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.2828614660
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.916977490
Short name T1361
Test name
Test status
Simulation time 205379248 ps
CPU time 0.85 seconds
Started Jul 23 06:43:18 PM PDT 24
Finished Jul 23 06:43:20 PM PDT 24
Peak memory 206732 kb
Host smart-cdf45ff8-c1d1-4a47-9bdf-2025f6069e27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91697
7490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.916977490
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.1646249953
Short name T1195
Test name
Test status
Simulation time 226631138 ps
CPU time 0.93 seconds
Started Jul 23 06:43:13 PM PDT 24
Finished Jul 23 06:43:15 PM PDT 24
Peak memory 206696 kb
Host smart-ae41763b-c292-4a75-bfd3-caad9abd3a7e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1646249953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.1646249953
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.3778806695
Short name T1243
Test name
Test status
Simulation time 142521633 ps
CPU time 0.84 seconds
Started Jul 23 06:43:13 PM PDT 24
Finished Jul 23 06:43:15 PM PDT 24
Peak memory 206768 kb
Host smart-2ffa9c0f-fc34-4cea-b7f8-a07c2b2dfaf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37788
06695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.3778806695
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.3524178653
Short name T2711
Test name
Test status
Simulation time 49239715 ps
CPU time 0.68 seconds
Started Jul 23 06:43:13 PM PDT 24
Finished Jul 23 06:43:16 PM PDT 24
Peak memory 206672 kb
Host smart-c18bbefb-75ae-4881-bdaa-47f2208414e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35241
78653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.3524178653
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.4073403058
Short name T1831
Test name
Test status
Simulation time 11173317864 ps
CPU time 27.92 seconds
Started Jul 23 06:43:13 PM PDT 24
Finished Jul 23 06:43:42 PM PDT 24
Peak memory 207020 kb
Host smart-e6099c25-4fdf-46c2-b2db-76a436a3c4c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40734
03058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.4073403058
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.2456235073
Short name T1582
Test name
Test status
Simulation time 175043778 ps
CPU time 0.82 seconds
Started Jul 23 06:43:13 PM PDT 24
Finished Jul 23 06:43:16 PM PDT 24
Peak memory 206760 kb
Host smart-3b5f1b6d-b4a8-4bd7-8f06-2ac5fd6369fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24562
35073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.2456235073
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.2940310801
Short name T2410
Test name
Test status
Simulation time 225903557 ps
CPU time 0.96 seconds
Started Jul 23 06:43:18 PM PDT 24
Finished Jul 23 06:43:20 PM PDT 24
Peak memory 206724 kb
Host smart-4bec250f-416c-48ce-bf31-a4d6f7e565b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29403
10801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.2940310801
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.2253216375
Short name T90
Test name
Test status
Simulation time 183893676 ps
CPU time 0.84 seconds
Started Jul 23 06:43:12 PM PDT 24
Finished Jul 23 06:43:14 PM PDT 24
Peak memory 206756 kb
Host smart-ddd90f45-f629-44c1-a1e9-02e4aa1f966f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22532
16375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.2253216375
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.3724693359
Short name T2523
Test name
Test status
Simulation time 215679996 ps
CPU time 0.9 seconds
Started Jul 23 06:43:20 PM PDT 24
Finished Jul 23 06:43:22 PM PDT 24
Peak memory 206748 kb
Host smart-89de3fcd-91ef-447a-831d-27929f77fb3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37246
93359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.3724693359
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.861166886
Short name T1303
Test name
Test status
Simulation time 197015425 ps
CPU time 0.87 seconds
Started Jul 23 06:43:24 PM PDT 24
Finished Jul 23 06:43:29 PM PDT 24
Peak memory 206740 kb
Host smart-5f84fa54-3e5c-4f90-9c42-65e15327276a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86116
6886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.861166886
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.1220982556
Short name T807
Test name
Test status
Simulation time 153618397 ps
CPU time 0.76 seconds
Started Jul 23 06:43:21 PM PDT 24
Finished Jul 23 06:43:24 PM PDT 24
Peak memory 206676 kb
Host smart-af342093-56e6-4deb-b1eb-f2809535b672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12209
82556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.1220982556
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.1413938691
Short name T1150
Test name
Test status
Simulation time 147388196 ps
CPU time 0.75 seconds
Started Jul 23 06:43:22 PM PDT 24
Finished Jul 23 06:43:26 PM PDT 24
Peak memory 206752 kb
Host smart-41592140-426e-4bc9-9c46-e1dc98ed2eed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14139
38691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.1413938691
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.194362251
Short name T1729
Test name
Test status
Simulation time 237372487 ps
CPU time 1.02 seconds
Started Jul 23 06:43:23 PM PDT 24
Finished Jul 23 06:43:28 PM PDT 24
Peak memory 206764 kb
Host smart-e745167c-748d-4dd8-b682-2fed7e241495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19436
2251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.194362251
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.3678818958
Short name T1488
Test name
Test status
Simulation time 5441633177 ps
CPU time 39.31 seconds
Started Jul 23 06:43:22 PM PDT 24
Finished Jul 23 06:44:05 PM PDT 24
Peak memory 206936 kb
Host smart-c81f7b8e-2886-4b5c-993e-0bff2726c3f5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3678818958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.3678818958
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.633236726
Short name T1407
Test name
Test status
Simulation time 187776893 ps
CPU time 0.86 seconds
Started Jul 23 06:43:21 PM PDT 24
Finished Jul 23 06:43:24 PM PDT 24
Peak memory 206756 kb
Host smart-b96302a1-dbbd-4321-be2c-65fdad7b5656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63323
6726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.633236726
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.2213637096
Short name T458
Test name
Test status
Simulation time 156185127 ps
CPU time 0.86 seconds
Started Jul 23 06:43:22 PM PDT 24
Finished Jul 23 06:43:26 PM PDT 24
Peak memory 206748 kb
Host smart-81f1d718-9ce2-4bc2-bc21-4921ecbb148d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22136
37096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.2213637096
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.1614453871
Short name T1291
Test name
Test status
Simulation time 910303019 ps
CPU time 1.9 seconds
Started Jul 23 06:43:22 PM PDT 24
Finished Jul 23 06:43:27 PM PDT 24
Peak memory 206884 kb
Host smart-43cec415-a26c-45c5-8635-5af0978588a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16144
53871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.1614453871
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.4204633402
Short name T2666
Test name
Test status
Simulation time 4725986964 ps
CPU time 130.47 seconds
Started Jul 23 06:43:22 PM PDT 24
Finished Jul 23 06:45:36 PM PDT 24
Peak memory 206924 kb
Host smart-0c821a1c-8128-42b5-890c-0fd6a7bced82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42046
33402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.4204633402
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.2031788594
Short name T1638
Test name
Test status
Simulation time 86352073 ps
CPU time 0.7 seconds
Started Jul 23 06:43:30 PM PDT 24
Finished Jul 23 06:43:35 PM PDT 24
Peak memory 206740 kb
Host smart-a4f055e1-83fb-4c7c-8134-4e9fa98a3fd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2031788594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.2031788594
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.19608237
Short name T1951
Test name
Test status
Simulation time 3515988502 ps
CPU time 3.86 seconds
Started Jul 23 06:43:20 PM PDT 24
Finished Jul 23 06:43:26 PM PDT 24
Peak memory 206916 kb
Host smart-39dfb27e-2e5e-483b-a3fc-c7079fd7ae43
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=19608237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.19608237
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.2287685577
Short name T2284
Test name
Test status
Simulation time 13407062711 ps
CPU time 16.36 seconds
Started Jul 23 06:43:22 PM PDT 24
Finished Jul 23 06:43:42 PM PDT 24
Peak memory 206836 kb
Host smart-2191e913-cdf6-4592-a474-41699d823633
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2287685577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.2287685577
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.2956239738
Short name T1995
Test name
Test status
Simulation time 23373872261 ps
CPU time 24.94 seconds
Started Jul 23 06:43:20 PM PDT 24
Finished Jul 23 06:43:47 PM PDT 24
Peak memory 206968 kb
Host smart-e6e5975b-3266-4bfb-a25b-e689ca3891f8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2956239738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.2956239738
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.1831302213
Short name T1886
Test name
Test status
Simulation time 161152557 ps
CPU time 0.8 seconds
Started Jul 23 06:43:21 PM PDT 24
Finished Jul 23 06:43:24 PM PDT 24
Peak memory 206756 kb
Host smart-4588fdf4-9073-4915-8502-9af51f201af4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18313
02213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.1831302213
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.817342733
Short name T2073
Test name
Test status
Simulation time 214364784 ps
CPU time 0.8 seconds
Started Jul 23 06:43:23 PM PDT 24
Finished Jul 23 06:43:28 PM PDT 24
Peak memory 206776 kb
Host smart-f182b4c5-a8ac-4813-a385-bfa0d0e40ac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81734
2733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.817342733
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.3844651202
Short name T1887
Test name
Test status
Simulation time 425339375 ps
CPU time 1.46 seconds
Started Jul 23 06:43:20 PM PDT 24
Finished Jul 23 06:43:24 PM PDT 24
Peak memory 206764 kb
Host smart-b1b75d54-495c-4050-b8f9-fe466b9bc28b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38446
51202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.3844651202
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.78544035
Short name T107
Test name
Test status
Simulation time 772154627 ps
CPU time 2.04 seconds
Started Jul 23 06:43:26 PM PDT 24
Finished Jul 23 06:43:31 PM PDT 24
Peak memory 206824 kb
Host smart-a4e71155-e17c-46f3-ab8c-1c56252bf9c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78544
035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.78544035
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.3437174610
Short name T1396
Test name
Test status
Simulation time 8008667837 ps
CPU time 15.09 seconds
Started Jul 23 06:43:20 PM PDT 24
Finished Jul 23 06:43:37 PM PDT 24
Peak memory 206896 kb
Host smart-f69f5006-c816-4653-884e-bcd0a69ec1f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34371
74610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.3437174610
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.1124005685
Short name T939
Test name
Test status
Simulation time 477230296 ps
CPU time 1.38 seconds
Started Jul 23 06:43:21 PM PDT 24
Finished Jul 23 06:43:26 PM PDT 24
Peak memory 206932 kb
Host smart-b5bbc582-6222-4645-a442-538147011b22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11240
05685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.1124005685
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.1730295520
Short name T2512
Test name
Test status
Simulation time 142612376 ps
CPU time 0.78 seconds
Started Jul 23 06:43:22 PM PDT 24
Finished Jul 23 06:43:27 PM PDT 24
Peak memory 206772 kb
Host smart-069f3ec6-1df7-4a1d-9dee-baebf5bdc943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17302
95520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.1730295520
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.1401129114
Short name T1058
Test name
Test status
Simulation time 30926633 ps
CPU time 0.66 seconds
Started Jul 23 06:43:22 PM PDT 24
Finished Jul 23 06:43:26 PM PDT 24
Peak memory 206756 kb
Host smart-f4b1051d-8159-4e88-8276-b563d3b7b057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14011
29114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.1401129114
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.659323530
Short name T1799
Test name
Test status
Simulation time 1051812426 ps
CPU time 2.44 seconds
Started Jul 23 06:43:21 PM PDT 24
Finished Jul 23 06:43:27 PM PDT 24
Peak memory 206832 kb
Host smart-227f334d-117f-4af8-9660-8f2ecc27753c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65932
3530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.659323530
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.1912405604
Short name T177
Test name
Test status
Simulation time 436346898 ps
CPU time 2.7 seconds
Started Jul 23 06:43:20 PM PDT 24
Finished Jul 23 06:43:25 PM PDT 24
Peak memory 206796 kb
Host smart-dbc580d5-2347-4bc9-8a04-f173deb62d88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19124
05604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.1912405604
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.2165299282
Short name T2675
Test name
Test status
Simulation time 239813235 ps
CPU time 0.95 seconds
Started Jul 23 06:43:23 PM PDT 24
Finished Jul 23 06:43:28 PM PDT 24
Peak memory 206676 kb
Host smart-3942dd79-b857-4639-bacd-c009306401fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21652
99282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.2165299282
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.2142104117
Short name T1268
Test name
Test status
Simulation time 155859767 ps
CPU time 0.75 seconds
Started Jul 23 06:43:22 PM PDT 24
Finished Jul 23 06:43:27 PM PDT 24
Peak memory 206772 kb
Host smart-4c6c5d13-13cc-4438-9cc5-efbaa407abb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21421
04117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.2142104117
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.3159263317
Short name T1941
Test name
Test status
Simulation time 209828227 ps
CPU time 0.93 seconds
Started Jul 23 06:43:20 PM PDT 24
Finished Jul 23 06:43:23 PM PDT 24
Peak memory 206760 kb
Host smart-0adceb08-d92b-4681-a05d-55ecefffd93e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31592
63317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.3159263317
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_iso_retraction.3695394158
Short name T1783
Test name
Test status
Simulation time 5030427285 ps
CPU time 38.57 seconds
Started Jul 23 06:43:26 PM PDT 24
Finished Jul 23 06:44:07 PM PDT 24
Peak memory 206832 kb
Host smart-547f0166-4f5a-48d9-b3b0-d4fa0273c6f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36953
94158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.3695394158
Directory /workspace/29.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.1854305726
Short name T290
Test name
Test status
Simulation time 181554995 ps
CPU time 0.93 seconds
Started Jul 23 06:43:21 PM PDT 24
Finished Jul 23 06:43:25 PM PDT 24
Peak memory 206740 kb
Host smart-a975f75c-f0d4-44f5-87a3-ac2833c80bdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18543
05726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.1854305726
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.195033736
Short name T852
Test name
Test status
Simulation time 23361900935 ps
CPU time 21.35 seconds
Started Jul 23 06:43:23 PM PDT 24
Finished Jul 23 06:43:48 PM PDT 24
Peak memory 206836 kb
Host smart-671fbd47-c0dc-455e-8e35-affef0be5236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19503
3736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.195033736
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.3862696915
Short name T1450
Test name
Test status
Simulation time 3274408738 ps
CPU time 4.35 seconds
Started Jul 23 06:43:23 PM PDT 24
Finished Jul 23 06:43:31 PM PDT 24
Peak memory 206744 kb
Host smart-fb73fc6f-7173-4465-b7ca-cc4bba5fa6b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38626
96915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.3862696915
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.3262858182
Short name T2374
Test name
Test status
Simulation time 7559176916 ps
CPU time 59.99 seconds
Started Jul 23 06:43:23 PM PDT 24
Finished Jul 23 06:44:27 PM PDT 24
Peak memory 206988 kb
Host smart-5f567481-9c27-4d1f-ae38-5826caafdf0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32628
58182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.3262858182
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.116406711
Short name T2524
Test name
Test status
Simulation time 7824467518 ps
CPU time 202.34 seconds
Started Jul 23 06:43:21 PM PDT 24
Finished Jul 23 06:46:46 PM PDT 24
Peak memory 206868 kb
Host smart-05a89f70-bc41-46a0-a49c-21e5a0ffe565
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=116406711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.116406711
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.3438719651
Short name T1820
Test name
Test status
Simulation time 238524829 ps
CPU time 0.91 seconds
Started Jul 23 06:43:21 PM PDT 24
Finished Jul 23 06:43:25 PM PDT 24
Peak memory 206756 kb
Host smart-01d2bbad-e993-42cd-9ad6-885cfff100af
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3438719651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.3438719651
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.2939463275
Short name T1537
Test name
Test status
Simulation time 194182871 ps
CPU time 0.84 seconds
Started Jul 23 06:43:25 PM PDT 24
Finished Jul 23 06:43:29 PM PDT 24
Peak memory 206692 kb
Host smart-3a1d4d22-b80b-4790-aa39-1b8d695a66cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29394
63275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.2939463275
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.461386168
Short name T995
Test name
Test status
Simulation time 5132341901 ps
CPU time 49.14 seconds
Started Jul 23 06:43:22 PM PDT 24
Finished Jul 23 06:44:15 PM PDT 24
Peak memory 206908 kb
Host smart-62b45e32-5466-4623-84ba-25bf213b572a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46138
6168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.461386168
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.3322863540
Short name T1622
Test name
Test status
Simulation time 5146581870 ps
CPU time 140.99 seconds
Started Jul 23 06:43:21 PM PDT 24
Finished Jul 23 06:45:44 PM PDT 24
Peak memory 206916 kb
Host smart-045d2ac3-a637-4d27-a8bc-aa709ff41530
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3322863540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.3322863540
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.733129516
Short name T1967
Test name
Test status
Simulation time 153976445 ps
CPU time 0.76 seconds
Started Jul 23 06:43:30 PM PDT 24
Finished Jul 23 06:43:36 PM PDT 24
Peak memory 206768 kb
Host smart-61960a1d-5cdf-4c3c-a4cd-999436b2d42d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=733129516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.733129516
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.2814310671
Short name T1819
Test name
Test status
Simulation time 160130112 ps
CPU time 0.78 seconds
Started Jul 23 06:43:27 PM PDT 24
Finished Jul 23 06:43:32 PM PDT 24
Peak memory 206756 kb
Host smart-865772f3-e3e5-4125-81ec-52703b1f6f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28143
10671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.2814310671
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.3879472522
Short name T2510
Test name
Test status
Simulation time 228316559 ps
CPU time 0.89 seconds
Started Jul 23 06:43:32 PM PDT 24
Finished Jul 23 06:43:37 PM PDT 24
Peak memory 206768 kb
Host smart-34609489-97a9-41d7-a2fe-f01c211c3a09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38794
72522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.3879472522
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.3455066935
Short name T2683
Test name
Test status
Simulation time 174094390 ps
CPU time 0.82 seconds
Started Jul 23 06:43:29 PM PDT 24
Finished Jul 23 06:43:35 PM PDT 24
Peak memory 206768 kb
Host smart-271cccfb-9c3b-42ed-a61a-073a9b67c562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34550
66935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.3455066935
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.1797900845
Short name T2171
Test name
Test status
Simulation time 171559230 ps
CPU time 0.83 seconds
Started Jul 23 06:43:29 PM PDT 24
Finished Jul 23 06:43:34 PM PDT 24
Peak memory 206760 kb
Host smart-383fda25-2377-4319-ba1c-5558528b78e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17979
00845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.1797900845
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.2608903729
Short name T1043
Test name
Test status
Simulation time 197072669 ps
CPU time 0.83 seconds
Started Jul 23 06:43:28 PM PDT 24
Finished Jul 23 06:43:33 PM PDT 24
Peak memory 206748 kb
Host smart-8050306d-929c-4c39-9945-ff2bdd874675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26089
03729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.2608903729
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.1819353466
Short name T2313
Test name
Test status
Simulation time 178880152 ps
CPU time 0.8 seconds
Started Jul 23 06:43:27 PM PDT 24
Finished Jul 23 06:43:30 PM PDT 24
Peak memory 206760 kb
Host smart-9489dafc-236b-4f03-862a-e9246cb671b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18193
53466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.1819353466
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.2598092937
Short name T740
Test name
Test status
Simulation time 231241883 ps
CPU time 0.89 seconds
Started Jul 23 06:43:30 PM PDT 24
Finished Jul 23 06:43:36 PM PDT 24
Peak memory 206740 kb
Host smart-0640cab5-1feb-4319-9ea9-90864beaa52a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2598092937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.2598092937
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.1700228940
Short name T2063
Test name
Test status
Simulation time 138854130 ps
CPU time 0.78 seconds
Started Jul 23 06:43:31 PM PDT 24
Finished Jul 23 06:43:36 PM PDT 24
Peak memory 206732 kb
Host smart-d48041f0-2f17-482d-b49a-4e0fe6ee3499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17002
28940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.1700228940
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.3061963746
Short name T2714
Test name
Test status
Simulation time 33718253 ps
CPU time 0.68 seconds
Started Jul 23 06:43:29 PM PDT 24
Finished Jul 23 06:43:34 PM PDT 24
Peak memory 206772 kb
Host smart-dd503323-cc65-4d8b-be0e-003fa45391ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30619
63746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.3061963746
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.3556147353
Short name T1667
Test name
Test status
Simulation time 8284976827 ps
CPU time 19.53 seconds
Started Jul 23 06:43:29 PM PDT 24
Finished Jul 23 06:43:53 PM PDT 24
Peak memory 206988 kb
Host smart-9a98d619-498c-4af9-96b2-2a3a0fcc6c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35561
47353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.3556147353
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.45302213
Short name T1789
Test name
Test status
Simulation time 181321727 ps
CPU time 0.83 seconds
Started Jul 23 06:43:31 PM PDT 24
Finished Jul 23 06:43:37 PM PDT 24
Peak memory 206764 kb
Host smart-b477264a-69d2-441d-aa79-63d83af20b31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45302
213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.45302213
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.1721819862
Short name T2143
Test name
Test status
Simulation time 224315825 ps
CPU time 0.91 seconds
Started Jul 23 06:43:29 PM PDT 24
Finished Jul 23 06:43:35 PM PDT 24
Peak memory 206748 kb
Host smart-f9645bc7-9e35-4f24-b3fa-8575dd02ecf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17218
19862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.1721819862
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.2420344412
Short name T1690
Test name
Test status
Simulation time 251289404 ps
CPU time 0.9 seconds
Started Jul 23 06:43:29 PM PDT 24
Finished Jul 23 06:43:34 PM PDT 24
Peak memory 206772 kb
Host smart-aa9b1e0d-2865-4649-a542-02504574c636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24203
44412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.2420344412
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.21804478
Short name T2103
Test name
Test status
Simulation time 189445835 ps
CPU time 0.85 seconds
Started Jul 23 06:43:27 PM PDT 24
Finished Jul 23 06:43:31 PM PDT 24
Peak memory 206764 kb
Host smart-ab9270f0-9751-45b2-8c75-44e5ac53a888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21804
478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.21804478
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.2862376214
Short name T1892
Test name
Test status
Simulation time 218555928 ps
CPU time 0.85 seconds
Started Jul 23 06:43:30 PM PDT 24
Finished Jul 23 06:43:35 PM PDT 24
Peak memory 206752 kb
Host smart-0381264e-d60f-44a6-8ce5-521734ebee72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28623
76214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.2862376214
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.4160301904
Short name T457
Test name
Test status
Simulation time 143530490 ps
CPU time 0.84 seconds
Started Jul 23 06:43:31 PM PDT 24
Finished Jul 23 06:43:36 PM PDT 24
Peak memory 206764 kb
Host smart-042a3b2b-71f3-48d1-af73-e8876daecda8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41603
01904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.4160301904
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.2866511593
Short name T1429
Test name
Test status
Simulation time 214451787 ps
CPU time 0.82 seconds
Started Jul 23 06:43:31 PM PDT 24
Finished Jul 23 06:43:37 PM PDT 24
Peak memory 206712 kb
Host smart-58da14c5-3285-4a68-b0ab-501084ed1c45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28665
11593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.2866511593
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.472557275
Short name T2359
Test name
Test status
Simulation time 263732423 ps
CPU time 0.94 seconds
Started Jul 23 06:43:30 PM PDT 24
Finished Jul 23 06:43:36 PM PDT 24
Peak memory 206720 kb
Host smart-f8b87a6f-ac8e-4ec6-9e16-406cf7d585c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47255
7275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.472557275
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.2014850699
Short name T763
Test name
Test status
Simulation time 3396951763 ps
CPU time 24.01 seconds
Started Jul 23 06:43:29 PM PDT 24
Finished Jul 23 06:43:57 PM PDT 24
Peak memory 206928 kb
Host smart-f2f8b518-3315-4061-9510-e1be638ddd6e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2014850699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.2014850699
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.4038948223
Short name T427
Test name
Test status
Simulation time 159314316 ps
CPU time 0.82 seconds
Started Jul 23 06:43:35 PM PDT 24
Finished Jul 23 06:43:39 PM PDT 24
Peak memory 206748 kb
Host smart-db9122d4-30b5-4402-839a-616330220656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40389
48223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.4038948223
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.475772892
Short name T1752
Test name
Test status
Simulation time 186406577 ps
CPU time 0.79 seconds
Started Jul 23 06:43:26 PM PDT 24
Finished Jul 23 06:43:30 PM PDT 24
Peak memory 206756 kb
Host smart-cdb8aec3-1374-45e1-b932-11d42d9222b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47577
2892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.475772892
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.971582357
Short name T1373
Test name
Test status
Simulation time 199366628 ps
CPU time 0.85 seconds
Started Jul 23 06:43:29 PM PDT 24
Finished Jul 23 06:43:35 PM PDT 24
Peak memory 206744 kb
Host smart-c2730c9a-3acf-43d5-940c-a712167eaa62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97158
2357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.971582357
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.1756010248
Short name T948
Test name
Test status
Simulation time 3021412881 ps
CPU time 21.87 seconds
Started Jul 23 06:43:31 PM PDT 24
Finished Jul 23 06:43:57 PM PDT 24
Peak memory 206948 kb
Host smart-a2c60088-42fd-4726-b32c-4529e744a714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17560
10248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.1756010248
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.3221668127
Short name T1825
Test name
Test status
Simulation time 39371266 ps
CPU time 0.69 seconds
Started Jul 23 06:38:09 PM PDT 24
Finished Jul 23 06:38:12 PM PDT 24
Peak memory 206744 kb
Host smart-a8aae5b2-191d-40eb-8196-bcd2ca889101
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3221668127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.3221668127
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.2500378279
Short name T510
Test name
Test status
Simulation time 3687554495 ps
CPU time 4.24 seconds
Started Jul 23 06:37:51 PM PDT 24
Finished Jul 23 06:37:59 PM PDT 24
Peak memory 206924 kb
Host smart-adb0694e-6f75-46fb-9a80-2f8fa1b556e4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2500378279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.2500378279
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.1130307019
Short name T1405
Test name
Test status
Simulation time 13326609805 ps
CPU time 15.6 seconds
Started Jul 23 06:37:47 PM PDT 24
Finished Jul 23 06:38:03 PM PDT 24
Peak memory 206800 kb
Host smart-d564d609-9116-430a-bb8a-96687636e4c8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1130307019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.1130307019
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.3283359796
Short name T928
Test name
Test status
Simulation time 23352381594 ps
CPU time 25.22 seconds
Started Jul 23 06:37:48 PM PDT 24
Finished Jul 23 06:38:15 PM PDT 24
Peak memory 206776 kb
Host smart-89344a0e-11d9-4254-b85a-b1ccb26214d8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3283359796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.3283359796
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.1413251620
Short name T2203
Test name
Test status
Simulation time 195231019 ps
CPU time 0.81 seconds
Started Jul 23 06:37:43 PM PDT 24
Finished Jul 23 06:37:45 PM PDT 24
Peak memory 206696 kb
Host smart-48fd429d-a2d1-4e39-9ad0-d25ec9f98e4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14132
51620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.1413251620
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.2917531478
Short name T53
Test name
Test status
Simulation time 204673382 ps
CPU time 0.89 seconds
Started Jul 23 06:37:47 PM PDT 24
Finished Jul 23 06:37:49 PM PDT 24
Peak memory 206756 kb
Host smart-a227816e-013f-476f-9943-4b1dbe7a491f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29175
31478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.2917531478
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.877761071
Short name T66
Test name
Test status
Simulation time 221990967 ps
CPU time 0.83 seconds
Started Jul 23 06:37:49 PM PDT 24
Finished Jul 23 06:37:52 PM PDT 24
Peak memory 206704 kb
Host smart-aa31688a-d5c3-4fe9-9239-d56bfe615f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87776
1071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.877761071
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.2971421016
Short name T504
Test name
Test status
Simulation time 153917502 ps
CPU time 0.75 seconds
Started Jul 23 06:37:46 PM PDT 24
Finished Jul 23 06:37:48 PM PDT 24
Peak memory 206756 kb
Host smart-7734249b-d313-477b-9087-f6fe0940b077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29714
21016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.2971421016
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.1839697272
Short name T112
Test name
Test status
Simulation time 143583015 ps
CPU time 0.77 seconds
Started Jul 23 06:37:50 PM PDT 24
Finished Jul 23 06:37:52 PM PDT 24
Peak memory 206724 kb
Host smart-e318c6e5-0bde-4512-9354-f30e9f1f3f1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18396
97272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.1839697272
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.3348057113
Short name T1205
Test name
Test status
Simulation time 1316106680 ps
CPU time 2.74 seconds
Started Jul 23 06:37:47 PM PDT 24
Finished Jul 23 06:37:51 PM PDT 24
Peak memory 206880 kb
Host smart-9c6c16cf-05f8-43ce-b240-49d0386d70f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33480
57113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.3348057113
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.3719754139
Short name T100
Test name
Test status
Simulation time 21614371196 ps
CPU time 36.57 seconds
Started Jul 23 06:37:46 PM PDT 24
Finished Jul 23 06:38:23 PM PDT 24
Peak memory 206948 kb
Host smart-02cd5e28-b174-4238-82d7-6b66b359d0ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37197
54139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.3719754139
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.3427344083
Short name T2406
Test name
Test status
Simulation time 366651686 ps
CPU time 1.29 seconds
Started Jul 23 06:37:52 PM PDT 24
Finished Jul 23 06:37:57 PM PDT 24
Peak memory 206732 kb
Host smart-0e3f7d4e-1e04-4347-a609-ddf0bff85300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34273
44083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.3427344083
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.2305014143
Short name T43
Test name
Test status
Simulation time 170379771 ps
CPU time 0.82 seconds
Started Jul 23 06:37:52 PM PDT 24
Finished Jul 23 06:37:56 PM PDT 24
Peak memory 206744 kb
Host smart-b1e226bc-bf98-44d5-8487-3cd22d3fcb81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23050
14143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.2305014143
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.238700984
Short name T1693
Test name
Test status
Simulation time 36609895 ps
CPU time 0.67 seconds
Started Jul 23 06:37:51 PM PDT 24
Finished Jul 23 06:37:55 PM PDT 24
Peak memory 206752 kb
Host smart-5e6dc25c-33f4-4c3f-b0df-1002d349c4e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23870
0984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.238700984
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.3825783892
Short name T828
Test name
Test status
Simulation time 895851138 ps
CPU time 2.04 seconds
Started Jul 23 06:37:55 PM PDT 24
Finished Jul 23 06:37:59 PM PDT 24
Peak memory 206808 kb
Host smart-6645f358-15d6-45d4-afc3-9aff621170fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38257
83892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.3825783892
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.2547783237
Short name T612
Test name
Test status
Simulation time 176749283 ps
CPU time 2.06 seconds
Started Jul 23 06:37:51 PM PDT 24
Finished Jul 23 06:37:56 PM PDT 24
Peak memory 206916 kb
Host smart-24caacf4-b463-4835-a3a1-2b86ae376c3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25477
83237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.2547783237
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.1812130226
Short name T37
Test name
Test status
Simulation time 92173947027 ps
CPU time 120.08 seconds
Started Jul 23 06:37:52 PM PDT 24
Finished Jul 23 06:39:56 PM PDT 24
Peak memory 206920 kb
Host smart-589cb5a0-ed6e-45cf-8e61-a3ae1c48130a
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1812130226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.1812130226
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.389202681
Short name T1439
Test name
Test status
Simulation time 100149606688 ps
CPU time 147.74 seconds
Started Jul 23 06:37:51 PM PDT 24
Finished Jul 23 06:40:22 PM PDT 24
Peak memory 206980 kb
Host smart-d192dfd6-898f-43f7-a050-f56dc87d7341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389202681 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.389202681
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.3609820675
Short name T954
Test name
Test status
Simulation time 83135879346 ps
CPU time 103.82 seconds
Started Jul 23 06:37:55 PM PDT 24
Finished Jul 23 06:39:41 PM PDT 24
Peak memory 206980 kb
Host smart-42dc2f62-d645-4918-9737-2d16a48460b2
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3609820675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.3609820675
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.850444023
Short name T1696
Test name
Test status
Simulation time 99942880212 ps
CPU time 146.52 seconds
Started Jul 23 06:37:51 PM PDT 24
Finished Jul 23 06:40:21 PM PDT 24
Peak memory 206976 kb
Host smart-533442a9-98ba-4b14-8d88-eb60346731de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850444023 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.850444023
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.457968849
Short name T2057
Test name
Test status
Simulation time 98146240860 ps
CPU time 127.33 seconds
Started Jul 23 06:37:51 PM PDT 24
Finished Jul 23 06:40:02 PM PDT 24
Peak memory 206928 kb
Host smart-5358d055-0b36-4490-9621-dcb6f1931dd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45796
8849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.457968849
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.1271392740
Short name T825
Test name
Test status
Simulation time 220905430 ps
CPU time 0.88 seconds
Started Jul 23 06:37:51 PM PDT 24
Finished Jul 23 06:37:54 PM PDT 24
Peak memory 206748 kb
Host smart-cd7f3b2d-f90f-461e-968f-d3b683f141a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12713
92740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.1271392740
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.161054610
Short name T366
Test name
Test status
Simulation time 139633695 ps
CPU time 0.74 seconds
Started Jul 23 06:37:55 PM PDT 24
Finished Jul 23 06:37:58 PM PDT 24
Peak memory 206760 kb
Host smart-d73f00a8-08c5-4275-8143-d6850cf7382d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16105
4610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.161054610
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.645717842
Short name T1972
Test name
Test status
Simulation time 160040650 ps
CPU time 0.78 seconds
Started Jul 23 06:37:51 PM PDT 24
Finished Jul 23 06:37:56 PM PDT 24
Peak memory 206764 kb
Host smart-be18f6b9-ea8f-49d5-9259-37585357262b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64571
7842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.645717842
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_iso_retraction.311039519
Short name T564
Test name
Test status
Simulation time 5170567802 ps
CPU time 18.37 seconds
Started Jul 23 06:37:50 PM PDT 24
Finished Jul 23 06:38:11 PM PDT 24
Peak memory 206936 kb
Host smart-18fec93b-880b-45b6-98e7-079bfea85978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31103
9519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.311039519
Directory /workspace/3.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.2764418216
Short name T1327
Test name
Test status
Simulation time 176880949 ps
CPU time 0.82 seconds
Started Jul 23 06:38:00 PM PDT 24
Finished Jul 23 06:38:02 PM PDT 24
Peak memory 206740 kb
Host smart-e70e1727-40c2-4565-8bad-8d7143251929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27644
18216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.2764418216
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.904167379
Short name T2482
Test name
Test status
Simulation time 23294112644 ps
CPU time 23.25 seconds
Started Jul 23 06:37:59 PM PDT 24
Finished Jul 23 06:38:24 PM PDT 24
Peak memory 206812 kb
Host smart-2fad7b84-c148-4413-bb65-34586c711db1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90416
7379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.904167379
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.184780237
Short name T975
Test name
Test status
Simulation time 3333859286 ps
CPU time 3.6 seconds
Started Jul 23 06:38:00 PM PDT 24
Finished Jul 23 06:38:05 PM PDT 24
Peak memory 206784 kb
Host smart-3e8ce4ec-106d-4429-a087-9d9840a50a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18478
0237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.184780237
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.2844700595
Short name T2677
Test name
Test status
Simulation time 10905909535 ps
CPU time 311.06 seconds
Started Jul 23 06:38:02 PM PDT 24
Finished Jul 23 06:43:14 PM PDT 24
Peak memory 207028 kb
Host smart-cddc7010-8e5d-43a6-8b67-8b9f0b7ccd83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28447
00595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.2844700595
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.1973430466
Short name T1296
Test name
Test status
Simulation time 4258318876 ps
CPU time 28.54 seconds
Started Jul 23 06:38:02 PM PDT 24
Finished Jul 23 06:38:32 PM PDT 24
Peak memory 206964 kb
Host smart-6e7b72a1-0417-4ef1-867d-b6c854ecebf4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1973430466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.1973430466
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.2447686348
Short name T18
Test name
Test status
Simulation time 238598598 ps
CPU time 1 seconds
Started Jul 23 06:38:00 PM PDT 24
Finished Jul 23 06:38:03 PM PDT 24
Peak memory 206756 kb
Host smart-f87c10a3-fdfd-45dc-a45f-30a1cc044e35
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2447686348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.2447686348
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.2240989897
Short name T1315
Test name
Test status
Simulation time 199487723 ps
CPU time 0.86 seconds
Started Jul 23 06:38:01 PM PDT 24
Finished Jul 23 06:38:03 PM PDT 24
Peak memory 206740 kb
Host smart-3337b38e-4d22-4e35-8471-9032563eb6f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22409
89897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.2240989897
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.1541184564
Short name T2141
Test name
Test status
Simulation time 4000908086 ps
CPU time 28.4 seconds
Started Jul 23 06:38:01 PM PDT 24
Finished Jul 23 06:38:30 PM PDT 24
Peak memory 206920 kb
Host smart-bbd95f77-5fc2-454c-a37d-0e7af8c9643f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15411
84564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.1541184564
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.3218862913
Short name T1096
Test name
Test status
Simulation time 5072985246 ps
CPU time 135.17 seconds
Started Jul 23 06:38:00 PM PDT 24
Finished Jul 23 06:40:16 PM PDT 24
Peak memory 206960 kb
Host smart-b93295de-2ade-4514-9570-52477dc077db
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3218862913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.3218862913
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.3326210087
Short name T389
Test name
Test status
Simulation time 161725900 ps
CPU time 0.8 seconds
Started Jul 23 06:37:59 PM PDT 24
Finished Jul 23 06:38:01 PM PDT 24
Peak memory 206756 kb
Host smart-e954e020-cb6a-4b95-b977-139fe05851e5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3326210087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.3326210087
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.3303078542
Short name T2624
Test name
Test status
Simulation time 151654337 ps
CPU time 0.82 seconds
Started Jul 23 06:38:01 PM PDT 24
Finished Jul 23 06:38:03 PM PDT 24
Peak memory 206776 kb
Host smart-dcf443e9-25e5-4db7-ace3-a10e0eda7fdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33030
78542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.3303078542
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.2348986664
Short name T103
Test name
Test status
Simulation time 233925076 ps
CPU time 0.91 seconds
Started Jul 23 06:38:01 PM PDT 24
Finished Jul 23 06:38:04 PM PDT 24
Peak memory 206764 kb
Host smart-7e602383-2fbd-44f8-9304-893d98e35fca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23489
86664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.2348986664
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.3044828552
Short name T2003
Test name
Test status
Simulation time 210384712 ps
CPU time 0.83 seconds
Started Jul 23 06:37:59 PM PDT 24
Finished Jul 23 06:38:01 PM PDT 24
Peak memory 206768 kb
Host smart-b2373d8f-245c-47f1-a3f8-1228dd492524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30448
28552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.3044828552
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.2307952962
Short name T2148
Test name
Test status
Simulation time 165087452 ps
CPU time 0.77 seconds
Started Jul 23 06:37:59 PM PDT 24
Finished Jul 23 06:38:01 PM PDT 24
Peak memory 206764 kb
Host smart-de789ab0-2b99-4c77-81b7-0fe1f078a8c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23079
52962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.2307952962
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.846854365
Short name T1242
Test name
Test status
Simulation time 149606417 ps
CPU time 0.81 seconds
Started Jul 23 06:38:02 PM PDT 24
Finished Jul 23 06:38:04 PM PDT 24
Peak memory 206756 kb
Host smart-9f528c61-3e86-4d19-b3a7-ed7ccf873e88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84685
4365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.846854365
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.321519489
Short name T2076
Test name
Test status
Simulation time 224115895 ps
CPU time 0.97 seconds
Started Jul 23 06:38:00 PM PDT 24
Finished Jul 23 06:38:02 PM PDT 24
Peak memory 206760 kb
Host smart-5a1adabf-338a-40e2-83d6-48599aa6cf05
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=321519489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.321519489
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.2372143032
Short name T2437
Test name
Test status
Simulation time 202565330 ps
CPU time 0.92 seconds
Started Jul 23 06:37:57 PM PDT 24
Finished Jul 23 06:38:00 PM PDT 24
Peak memory 206748 kb
Host smart-87894d8d-0f92-407a-916b-4f485fa5cecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23721
43032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.2372143032
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.2218930009
Short name T2608
Test name
Test status
Simulation time 151461154 ps
CPU time 0.79 seconds
Started Jul 23 06:38:07 PM PDT 24
Finished Jul 23 06:38:10 PM PDT 24
Peak memory 206760 kb
Host smart-10bdba7c-eb40-45a7-a08d-8f609fe59f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22189
30009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.2218930009
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.2530481565
Short name T788
Test name
Test status
Simulation time 38460803 ps
CPU time 0.75 seconds
Started Jul 23 06:38:05 PM PDT 24
Finished Jul 23 06:38:07 PM PDT 24
Peak memory 206748 kb
Host smart-bcc6dc96-8d00-41a2-82d3-98f1ab1e6485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25304
81565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.2530481565
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.2870536376
Short name T2340
Test name
Test status
Simulation time 14086203616 ps
CPU time 29.4 seconds
Started Jul 23 06:38:03 PM PDT 24
Finished Jul 23 06:38:34 PM PDT 24
Peak memory 206944 kb
Host smart-836546dc-ba26-42ce-8f21-0f711abaa988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28705
36376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.2870536376
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.1206017848
Short name T726
Test name
Test status
Simulation time 180751705 ps
CPU time 0.88 seconds
Started Jul 23 06:38:03 PM PDT 24
Finished Jul 23 06:38:06 PM PDT 24
Peak memory 206780 kb
Host smart-0e972029-5df0-4006-83be-180cf6d94246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12060
17848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.1206017848
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.1104201337
Short name T2621
Test name
Test status
Simulation time 239142455 ps
CPU time 0.98 seconds
Started Jul 23 06:38:04 PM PDT 24
Finished Jul 23 06:38:06 PM PDT 24
Peak memory 206752 kb
Host smart-e54efae0-6e45-4f8d-a60c-6ade2bd8d144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11042
01337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.1104201337
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.3471367336
Short name T1539
Test name
Test status
Simulation time 10796047646 ps
CPU time 186.4 seconds
Started Jul 23 06:38:02 PM PDT 24
Finished Jul 23 06:41:10 PM PDT 24
Peak memory 206960 kb
Host smart-b6d4c39f-be09-4cef-b2bf-14da496ea5ad
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3471367336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.3471367336
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.2869618079
Short name T2354
Test name
Test status
Simulation time 13188485797 ps
CPU time 68.13 seconds
Started Jul 23 06:38:05 PM PDT 24
Finished Jul 23 06:39:15 PM PDT 24
Peak memory 206944 kb
Host smart-e96039c2-12a8-4135-9296-79b0fcab2364
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2869618079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.2869618079
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.3245839664
Short name T2268
Test name
Test status
Simulation time 8777518636 ps
CPU time 39.92 seconds
Started Jul 23 06:38:03 PM PDT 24
Finished Jul 23 06:38:44 PM PDT 24
Peak memory 206984 kb
Host smart-aa1e1fdd-a0fa-4427-82ab-6d4c815a5fcd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3245839664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.3245839664
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.1313892791
Short name T1466
Test name
Test status
Simulation time 174105380 ps
CPU time 0.82 seconds
Started Jul 23 06:38:03 PM PDT 24
Finished Jul 23 06:38:06 PM PDT 24
Peak memory 206780 kb
Host smart-120a2d69-9e42-41ad-896e-b8b590088646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13138
92791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.1313892791
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.1092759339
Short name T2492
Test name
Test status
Simulation time 200972094 ps
CPU time 0.89 seconds
Started Jul 23 06:38:05 PM PDT 24
Finished Jul 23 06:38:07 PM PDT 24
Peak memory 206708 kb
Host smart-511e8b8f-2a56-432b-8f27-5e283043db99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10927
59339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.1092759339
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.3880673177
Short name T1935
Test name
Test status
Simulation time 221440843 ps
CPU time 0.88 seconds
Started Jul 23 06:38:06 PM PDT 24
Finished Jul 23 06:38:08 PM PDT 24
Peak memory 206744 kb
Host smart-8861443e-0e6b-43a9-a1ca-10f21fdeabf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38806
73177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.3880673177
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.760447575
Short name T2166
Test name
Test status
Simulation time 163858448 ps
CPU time 0.78 seconds
Started Jul 23 06:38:06 PM PDT 24
Finished Jul 23 06:38:08 PM PDT 24
Peak memory 206740 kb
Host smart-61e55bef-1258-4a46-b065-4dd87ae43fad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76044
7575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.760447575
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.2703351759
Short name T208
Test name
Test status
Simulation time 488824102 ps
CPU time 1.35 seconds
Started Jul 23 06:38:09 PM PDT 24
Finished Jul 23 06:38:13 PM PDT 24
Peak memory 225468 kb
Host smart-80db8723-885c-44f4-897e-821b14b3ebbf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2703351759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.2703351759
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.1324544668
Short name T57
Test name
Test status
Simulation time 437306906 ps
CPU time 1.28 seconds
Started Jul 23 06:38:02 PM PDT 24
Finished Jul 23 06:38:05 PM PDT 24
Peak memory 206720 kb
Host smart-9f06f6c1-9cce-4b34-9083-d7a73021c902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13245
44668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.1324544668
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.2095901823
Short name T2727
Test name
Test status
Simulation time 192424084 ps
CPU time 0.87 seconds
Started Jul 23 06:38:03 PM PDT 24
Finished Jul 23 06:38:05 PM PDT 24
Peak memory 206664 kb
Host smart-e3c2652c-2fc6-4d03-8073-2474814f6c41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20959
01823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.2095901823
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.3090975607
Short name T2470
Test name
Test status
Simulation time 145660111 ps
CPU time 0.79 seconds
Started Jul 23 06:38:07 PM PDT 24
Finished Jul 23 06:38:10 PM PDT 24
Peak memory 206752 kb
Host smart-110b7655-512c-400b-8688-be5c517fc3e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30909
75607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.3090975607
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.1943736801
Short name T2500
Test name
Test status
Simulation time 157173715 ps
CPU time 0.84 seconds
Started Jul 23 06:38:07 PM PDT 24
Finished Jul 23 06:38:10 PM PDT 24
Peak memory 206748 kb
Host smart-dff8f492-af49-4ccc-b43b-95b66277d7c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19437
36801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.1943736801
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.891342640
Short name T1684
Test name
Test status
Simulation time 226328700 ps
CPU time 0.98 seconds
Started Jul 23 06:38:06 PM PDT 24
Finished Jul 23 06:38:08 PM PDT 24
Peak memory 206732 kb
Host smart-9f4cd12c-734a-487a-83a3-a25d02c53021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89134
2640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.891342640
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.18029778
Short name T633
Test name
Test status
Simulation time 4546176278 ps
CPU time 128.7 seconds
Started Jul 23 06:38:07 PM PDT 24
Finished Jul 23 06:40:17 PM PDT 24
Peak memory 206888 kb
Host smart-4b5a4c06-4f28-4368-ba3f-c6668d9626a6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=18029778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.18029778
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.1365099545
Short name T2453
Test name
Test status
Simulation time 156505905 ps
CPU time 0.82 seconds
Started Jul 23 06:38:03 PM PDT 24
Finished Jul 23 06:38:05 PM PDT 24
Peak memory 206764 kb
Host smart-e120c8c2-cd37-422e-b0c8-9a14b6f736de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13650
99545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.1365099545
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.1198071372
Short name T2154
Test name
Test status
Simulation time 187559258 ps
CPU time 0.85 seconds
Started Jul 23 06:38:10 PM PDT 24
Finished Jul 23 06:38:13 PM PDT 24
Peak memory 206740 kb
Host smart-fc38722f-5d13-483e-8b1f-c09f25b5f2a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11980
71372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.1198071372
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.846520858
Short name T707
Test name
Test status
Simulation time 569027263 ps
CPU time 1.56 seconds
Started Jul 23 06:38:10 PM PDT 24
Finished Jul 23 06:38:13 PM PDT 24
Peak memory 206772 kb
Host smart-9e12923a-6c52-4f55-bb07-52d182adb50e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84652
0858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.846520858
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.2080076385
Short name T1295
Test name
Test status
Simulation time 6167210972 ps
CPU time 57.58 seconds
Started Jul 23 06:38:09 PM PDT 24
Finished Jul 23 06:39:08 PM PDT 24
Peak memory 206952 kb
Host smart-0f68223d-7790-4970-baef-3a0684567141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20800
76385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.2080076385
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.2267785009
Short name T2504
Test name
Test status
Simulation time 11997397097 ps
CPU time 233.08 seconds
Started Jul 23 06:38:10 PM PDT 24
Finished Jul 23 06:42:05 PM PDT 24
Peak memory 206960 kb
Host smart-08a3b833-ccb4-43e2-b7f6-7875e512758a
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2267785009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.2267785009
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.3588198535
Short name T1504
Test name
Test status
Simulation time 44330783 ps
CPU time 0.66 seconds
Started Jul 23 06:43:36 PM PDT 24
Finished Jul 23 06:43:40 PM PDT 24
Peak memory 206684 kb
Host smart-2262a563-2a1d-4966-8641-a42b4fb16f4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3588198535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.3588198535
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.274780438
Short name T571
Test name
Test status
Simulation time 4153547811 ps
CPU time 5.19 seconds
Started Jul 23 06:43:30 PM PDT 24
Finished Jul 23 06:43:40 PM PDT 24
Peak memory 206984 kb
Host smart-6e211603-b5a2-4a5a-91d5-20135f89e989
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=274780438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.274780438
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.983163739
Short name T527
Test name
Test status
Simulation time 13354294884 ps
CPU time 12.48 seconds
Started Jul 23 06:43:28 PM PDT 24
Finished Jul 23 06:43:45 PM PDT 24
Peak memory 206792 kb
Host smart-bd82fcb7-252d-4386-a7cd-fe6e9883ac8b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=983163739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.983163739
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.622100139
Short name T2183
Test name
Test status
Simulation time 23315811146 ps
CPU time 23.51 seconds
Started Jul 23 06:43:32 PM PDT 24
Finished Jul 23 06:44:00 PM PDT 24
Peak memory 206832 kb
Host smart-f3c2d6cc-d85e-488d-8ada-0bf4e965e6a1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=622100139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.622100139
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.2644239501
Short name T1113
Test name
Test status
Simulation time 162665985 ps
CPU time 0.81 seconds
Started Jul 23 06:43:30 PM PDT 24
Finished Jul 23 06:43:36 PM PDT 24
Peak memory 206732 kb
Host smart-56cef281-dc2f-45bc-96ac-a088c306a0eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26442
39501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.2644239501
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.2569949854
Short name T1737
Test name
Test status
Simulation time 144101811 ps
CPU time 0.74 seconds
Started Jul 23 06:43:28 PM PDT 24
Finished Jul 23 06:43:32 PM PDT 24
Peak memory 206784 kb
Host smart-ca38fef7-617b-4966-b433-d0df29bc1d33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25699
49854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.2569949854
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.857176734
Short name T2738
Test name
Test status
Simulation time 323197111 ps
CPU time 1.09 seconds
Started Jul 23 06:43:29 PM PDT 24
Finished Jul 23 06:43:35 PM PDT 24
Peak memory 206792 kb
Host smart-29a1101a-505f-40a0-8a03-721c8761b81d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85717
6734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.857176734
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.363794500
Short name T715
Test name
Test status
Simulation time 1390333427 ps
CPU time 2.89 seconds
Started Jul 23 06:43:30 PM PDT 24
Finished Jul 23 06:43:38 PM PDT 24
Peak memory 206816 kb
Host smart-ee31f12b-889d-4175-91af-bf4b10cca2a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36379
4500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.363794500
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.4213407780
Short name T2188
Test name
Test status
Simulation time 8166900328 ps
CPU time 17.95 seconds
Started Jul 23 06:43:32 PM PDT 24
Finished Jul 23 06:43:54 PM PDT 24
Peak memory 206984 kb
Host smart-f6e6768e-2fb9-4c5d-abe0-16d6284120e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42134
07780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.4213407780
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.787541725
Short name T1028
Test name
Test status
Simulation time 322144074 ps
CPU time 1.14 seconds
Started Jul 23 06:43:30 PM PDT 24
Finished Jul 23 06:43:36 PM PDT 24
Peak memory 206760 kb
Host smart-9e1adfc0-06d2-4466-b868-e948e07a844e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78754
1725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.787541725
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.1333403629
Short name T649
Test name
Test status
Simulation time 140077795 ps
CPU time 0.73 seconds
Started Jul 23 06:43:27 PM PDT 24
Finished Jul 23 06:43:30 PM PDT 24
Peak memory 206740 kb
Host smart-d1167e82-deed-4273-9d21-b5cb9a179ac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13334
03629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.1333403629
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.1228155103
Short name T2686
Test name
Test status
Simulation time 49239448 ps
CPU time 0.68 seconds
Started Jul 23 06:43:28 PM PDT 24
Finished Jul 23 06:43:33 PM PDT 24
Peak memory 206744 kb
Host smart-592a4696-872b-4f7a-8aa6-95ccb45cce34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12281
55103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.1228155103
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.1844218939
Short name T2669
Test name
Test status
Simulation time 941403253 ps
CPU time 2 seconds
Started Jul 23 06:43:27 PM PDT 24
Finished Jul 23 06:43:33 PM PDT 24
Peak memory 206832 kb
Host smart-fb23146e-5287-4338-bf62-b2e096d1f6a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18442
18939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.1844218939
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.2382494546
Short name T1427
Test name
Test status
Simulation time 227811028 ps
CPU time 1.59 seconds
Started Jul 23 06:43:29 PM PDT 24
Finished Jul 23 06:43:34 PM PDT 24
Peak memory 206744 kb
Host smart-17a10349-6e4e-4d4e-bae8-9648f3cdef65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23824
94546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.2382494546
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.515439557
Short name T1015
Test name
Test status
Simulation time 173529918 ps
CPU time 0.81 seconds
Started Jul 23 06:43:31 PM PDT 24
Finished Jul 23 06:43:37 PM PDT 24
Peak memory 206756 kb
Host smart-afa50860-999e-454f-9cb3-66b996f44e6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51543
9557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.515439557
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.361783701
Short name T2496
Test name
Test status
Simulation time 137623910 ps
CPU time 0.76 seconds
Started Jul 23 06:43:31 PM PDT 24
Finished Jul 23 06:43:37 PM PDT 24
Peak memory 206760 kb
Host smart-92e945aa-ca05-4305-a0dc-09ba20aee4fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36178
3701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.361783701
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.3423405021
Short name T296
Test name
Test status
Simulation time 278808452 ps
CPU time 0.99 seconds
Started Jul 23 06:43:28 PM PDT 24
Finished Jul 23 06:43:33 PM PDT 24
Peak memory 206756 kb
Host smart-d5b16773-bfc1-40f4-b76d-8bfd28b9bff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34234
05021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.3423405021
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_invalid_sync.2381439268
Short name T1563
Test name
Test status
Simulation time 10051143852 ps
CPU time 78.26 seconds
Started Jul 23 06:43:28 PM PDT 24
Finished Jul 23 06:44:50 PM PDT 24
Peak memory 206992 kb
Host smart-e9f7c25a-3672-46c7-a2fe-f4811def42ec
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2381439268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.2381439268
Directory /workspace/30.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.3096811577
Short name T390
Test name
Test status
Simulation time 195682540 ps
CPU time 0.89 seconds
Started Jul 23 06:43:28 PM PDT 24
Finished Jul 23 06:43:32 PM PDT 24
Peak memory 206688 kb
Host smart-16fdf6c9-da58-4826-85b8-2864c723b6a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30968
11577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.3096811577
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.2794609130
Short name T1390
Test name
Test status
Simulation time 23304564682 ps
CPU time 21.78 seconds
Started Jul 23 06:43:28 PM PDT 24
Finished Jul 23 06:43:54 PM PDT 24
Peak memory 206804 kb
Host smart-b1d368bf-4c0e-4b92-81d5-4f4e3fa85fdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27946
09130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.2794609130
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.1110054386
Short name T2459
Test name
Test status
Simulation time 3356250548 ps
CPU time 3.85 seconds
Started Jul 23 06:43:31 PM PDT 24
Finished Jul 23 06:43:40 PM PDT 24
Peak memory 206776 kb
Host smart-3a0d591d-7bcb-489d-9469-a1abb7f60c88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11100
54386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.1110054386
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.3223615840
Short name T376
Test name
Test status
Simulation time 12169722907 ps
CPU time 107.31 seconds
Started Jul 23 06:43:44 PM PDT 24
Finished Jul 23 06:45:39 PM PDT 24
Peak memory 206964 kb
Host smart-603af9bf-86df-4bdd-9bc9-3d1f6e9db41b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32236
15840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.3223615840
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.3367033231
Short name T1821
Test name
Test status
Simulation time 7300872249 ps
CPU time 49.86 seconds
Started Jul 23 06:43:33 PM PDT 24
Finished Jul 23 06:44:27 PM PDT 24
Peak memory 206852 kb
Host smart-49163782-c97a-4a02-80d7-60a62646223a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3367033231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.3367033231
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.624274192
Short name T887
Test name
Test status
Simulation time 255148340 ps
CPU time 0.97 seconds
Started Jul 23 06:43:33 PM PDT 24
Finished Jul 23 06:43:38 PM PDT 24
Peak memory 206756 kb
Host smart-20d76921-19ec-45b2-8c92-5419c899a7e3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=624274192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.624274192
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.1960486680
Short name T2499
Test name
Test status
Simulation time 199681106 ps
CPU time 0.93 seconds
Started Jul 23 06:43:37 PM PDT 24
Finished Jul 23 06:43:42 PM PDT 24
Peak memory 206772 kb
Host smart-c8ed20f2-4ccd-49a0-847b-cf92e5a2696a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19604
86680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.1960486680
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.221684876
Short name T2649
Test name
Test status
Simulation time 3649378111 ps
CPU time 27.41 seconds
Started Jul 23 06:43:33 PM PDT 24
Finished Jul 23 06:44:05 PM PDT 24
Peak memory 206896 kb
Host smart-435b2857-d5ad-40da-abfa-cad20638aa06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22168
4876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.221684876
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.3048913921
Short name T6
Test name
Test status
Simulation time 6380854440 ps
CPU time 45.95 seconds
Started Jul 23 06:43:36 PM PDT 24
Finished Jul 23 06:44:25 PM PDT 24
Peak memory 206872 kb
Host smart-51c85816-1dfa-42ae-bb57-ee4f364522ac
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3048913921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.3048913921
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.1599851161
Short name T930
Test name
Test status
Simulation time 153355550 ps
CPU time 0.86 seconds
Started Jul 23 06:43:44 PM PDT 24
Finished Jul 23 06:43:52 PM PDT 24
Peak memory 206752 kb
Host smart-f38ab6ee-8dfc-4e4f-9be9-0cb0a7b3d29b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1599851161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.1599851161
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.3919922868
Short name T1269
Test name
Test status
Simulation time 152341237 ps
CPU time 0.81 seconds
Started Jul 23 06:43:35 PM PDT 24
Finished Jul 23 06:43:39 PM PDT 24
Peak memory 206736 kb
Host smart-0d8b3ff3-d4a1-42d1-ada1-ea7b8df1eef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39199
22868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.3919922868
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.933863961
Short name T119
Test name
Test status
Simulation time 251351144 ps
CPU time 0.88 seconds
Started Jul 23 06:43:34 PM PDT 24
Finished Jul 23 06:43:39 PM PDT 24
Peak memory 206428 kb
Host smart-b8d93276-d47d-4e2e-8354-554d31fb6c48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93386
3961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.933863961
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.725329915
Short name T1868
Test name
Test status
Simulation time 169556602 ps
CPU time 0.82 seconds
Started Jul 23 06:43:34 PM PDT 24
Finished Jul 23 06:43:39 PM PDT 24
Peak memory 206744 kb
Host smart-0cec657b-4d36-4362-a2e8-791c24521015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72532
9915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.725329915
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.1247752412
Short name T875
Test name
Test status
Simulation time 153478837 ps
CPU time 0.79 seconds
Started Jul 23 06:43:38 PM PDT 24
Finished Jul 23 06:43:43 PM PDT 24
Peak memory 206612 kb
Host smart-94d1a509-da6b-43d0-828d-86310f182c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12477
52412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.1247752412
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.754803549
Short name T1616
Test name
Test status
Simulation time 165118290 ps
CPU time 0.78 seconds
Started Jul 23 06:43:32 PM PDT 24
Finished Jul 23 06:43:38 PM PDT 24
Peak memory 206756 kb
Host smart-87135fa9-9fb9-4f3f-aa99-c3b5a46191ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75480
3549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.754803549
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.1533076637
Short name T2264
Test name
Test status
Simulation time 149678193 ps
CPU time 0.8 seconds
Started Jul 23 06:43:38 PM PDT 24
Finished Jul 23 06:43:43 PM PDT 24
Peak memory 206748 kb
Host smart-d923fba5-95af-4a9b-a36b-a11b7328e0bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15330
76637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.1533076637
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.1609134946
Short name T1532
Test name
Test status
Simulation time 227635940 ps
CPU time 0.93 seconds
Started Jul 23 06:43:44 PM PDT 24
Finished Jul 23 06:43:52 PM PDT 24
Peak memory 206752 kb
Host smart-fad58bc5-0c39-44eb-9cbd-b4ff76b80e49
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1609134946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.1609134946
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.2732240468
Short name T2689
Test name
Test status
Simulation time 143676764 ps
CPU time 0.79 seconds
Started Jul 23 06:43:35 PM PDT 24
Finished Jul 23 06:43:39 PM PDT 24
Peak memory 206756 kb
Host smart-2b00ce8a-cd3a-4d0f-a1bd-20748f9307f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27322
40468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.2732240468
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.1539335705
Short name T1307
Test name
Test status
Simulation time 36567860 ps
CPU time 0.67 seconds
Started Jul 23 06:43:40 PM PDT 24
Finished Jul 23 06:43:45 PM PDT 24
Peak memory 206728 kb
Host smart-e7382d32-5aa3-4843-9529-fa12a59da4d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15393
35705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.1539335705
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.299987531
Short name T84
Test name
Test status
Simulation time 18193202630 ps
CPU time 41.76 seconds
Started Jul 23 06:43:34 PM PDT 24
Finished Jul 23 06:44:20 PM PDT 24
Peak memory 206928 kb
Host smart-e0e85efe-a08d-4f57-982a-358873e58a70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29998
7531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.299987531
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.3171587075
Short name T990
Test name
Test status
Simulation time 180435719 ps
CPU time 0.85 seconds
Started Jul 23 06:43:38 PM PDT 24
Finished Jul 23 06:43:43 PM PDT 24
Peak memory 206612 kb
Host smart-f8448182-9e29-47ff-ad52-72f8df95585d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31715
87075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.3171587075
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.88430607
Short name T2159
Test name
Test status
Simulation time 251518251 ps
CPU time 0.88 seconds
Started Jul 23 06:43:43 PM PDT 24
Finished Jul 23 06:43:51 PM PDT 24
Peak memory 206768 kb
Host smart-a2eada21-ef89-45b3-b0de-cb612139d058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88430
607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.88430607
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.3563475781
Short name T2
Test name
Test status
Simulation time 269029031 ps
CPU time 0.94 seconds
Started Jul 23 06:43:43 PM PDT 24
Finished Jul 23 06:43:51 PM PDT 24
Peak memory 206772 kb
Host smart-d0660c5f-72fb-4af5-818a-b986961fc38b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35634
75781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.3563475781
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.3558303343
Short name T2214
Test name
Test status
Simulation time 171929608 ps
CPU time 0.85 seconds
Started Jul 23 06:43:44 PM PDT 24
Finished Jul 23 06:43:52 PM PDT 24
Peak memory 206748 kb
Host smart-760bc7af-5c97-47a3-a87b-f6f514866d41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35583
03343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.3558303343
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.1351114986
Short name T787
Test name
Test status
Simulation time 148364828 ps
CPU time 0.81 seconds
Started Jul 23 06:43:35 PM PDT 24
Finished Jul 23 06:43:39 PM PDT 24
Peak memory 206744 kb
Host smart-0e04d1f5-d6c4-4c43-b3e2-3b88f358e798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13511
14986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.1351114986
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.1885101491
Short name T1897
Test name
Test status
Simulation time 154401969 ps
CPU time 0.84 seconds
Started Jul 23 06:43:38 PM PDT 24
Finished Jul 23 06:43:43 PM PDT 24
Peak memory 206744 kb
Host smart-d4716668-64d2-41cf-a21b-3aba9943df6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18851
01491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.1885101491
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.556521013
Short name T1910
Test name
Test status
Simulation time 143622471 ps
CPU time 0.77 seconds
Started Jul 23 06:43:41 PM PDT 24
Finished Jul 23 06:43:48 PM PDT 24
Peak memory 206728 kb
Host smart-0e488319-136c-4dcf-9793-a59a32ccf9b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55652
1013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.556521013
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.1784033535
Short name T399
Test name
Test status
Simulation time 200150861 ps
CPU time 0.9 seconds
Started Jul 23 06:43:33 PM PDT 24
Finished Jul 23 06:43:38 PM PDT 24
Peak memory 206704 kb
Host smart-818e5432-88df-4540-875f-f0526bc16229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17840
33535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.1784033535
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.4158036934
Short name T866
Test name
Test status
Simulation time 5409760140 ps
CPU time 50.42 seconds
Started Jul 23 06:43:36 PM PDT 24
Finished Jul 23 06:44:30 PM PDT 24
Peak memory 206824 kb
Host smart-3c940396-9b72-4b38-b890-c5809f64d76d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4158036934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.4158036934
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.124641384
Short name T2124
Test name
Test status
Simulation time 173379290 ps
CPU time 0.84 seconds
Started Jul 23 06:43:35 PM PDT 24
Finished Jul 23 06:43:40 PM PDT 24
Peak memory 206748 kb
Host smart-bc909c05-da37-44eb-a9bd-f22eaa99b736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12464
1384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.124641384
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.1320384196
Short name T1947
Test name
Test status
Simulation time 154255480 ps
CPU time 0.75 seconds
Started Jul 23 06:43:34 PM PDT 24
Finished Jul 23 06:43:39 PM PDT 24
Peak memory 206488 kb
Host smart-5a709a2b-8033-49e1-8357-b523a2af599c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13203
84196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.1320384196
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.1235205661
Short name T562
Test name
Test status
Simulation time 799796462 ps
CPU time 1.98 seconds
Started Jul 23 06:43:44 PM PDT 24
Finished Jul 23 06:43:53 PM PDT 24
Peak memory 206900 kb
Host smart-220f47b4-250b-4638-8899-969ca78fe32c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12352
05661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.1235205661
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.976889402
Short name T1846
Test name
Test status
Simulation time 7309723463 ps
CPU time 50.29 seconds
Started Jul 23 06:43:41 PM PDT 24
Finished Jul 23 06:44:37 PM PDT 24
Peak memory 206940 kb
Host smart-aa8cda45-10f3-425c-b086-45b5e7bf7809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97688
9402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.976889402
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.521880155
Short name T2306
Test name
Test status
Simulation time 45189718 ps
CPU time 0.73 seconds
Started Jul 23 06:43:44 PM PDT 24
Finished Jul 23 06:43:52 PM PDT 24
Peak memory 206744 kb
Host smart-723ec3c5-d469-4e19-a67b-9c3b0c74ed8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=521880155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.521880155
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.951963257
Short name T2739
Test name
Test status
Simulation time 4318467340 ps
CPU time 5.8 seconds
Started Jul 23 06:43:37 PM PDT 24
Finished Jul 23 06:43:47 PM PDT 24
Peak memory 206908 kb
Host smart-716c0408-6bbc-4f8c-9867-4fa7fd52b808
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=951963257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.951963257
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.1290017916
Short name T992
Test name
Test status
Simulation time 13351427978 ps
CPU time 12.15 seconds
Started Jul 23 06:43:32 PM PDT 24
Finished Jul 23 06:43:49 PM PDT 24
Peak memory 206836 kb
Host smart-61501f0f-c35a-461e-84c1-f463300e5ca0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1290017916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.1290017916
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.1368938953
Short name T12
Test name
Test status
Simulation time 23426282789 ps
CPU time 21.57 seconds
Started Jul 23 06:43:32 PM PDT 24
Finished Jul 23 06:43:59 PM PDT 24
Peak memory 206924 kb
Host smart-1ab2a2bb-b142-4ef0-9f9e-1136f32a3725
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1368938953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.1368938953
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.2238699444
Short name T2400
Test name
Test status
Simulation time 166405974 ps
CPU time 0.8 seconds
Started Jul 23 06:43:33 PM PDT 24
Finished Jul 23 06:43:38 PM PDT 24
Peak memory 206692 kb
Host smart-53af8886-6f90-4ffc-91eb-3d038074b868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22386
99444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.2238699444
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.574257842
Short name T2441
Test name
Test status
Simulation time 142609361 ps
CPU time 0.77 seconds
Started Jul 23 06:43:44 PM PDT 24
Finished Jul 23 06:43:52 PM PDT 24
Peak memory 206752 kb
Host smart-b7fbfb0a-b9a0-476e-9926-8951b61b74e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57425
7842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.574257842
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.2057343501
Short name T1503
Test name
Test status
Simulation time 355238491 ps
CPU time 1.25 seconds
Started Jul 23 06:43:40 PM PDT 24
Finished Jul 23 06:43:46 PM PDT 24
Peak memory 206728 kb
Host smart-2952a9e3-6286-4e4e-bf9c-3464c3764a06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20573
43501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.2057343501
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.3832531711
Short name T1494
Test name
Test status
Simulation time 483002473 ps
CPU time 1.33 seconds
Started Jul 23 06:43:32 PM PDT 24
Finished Jul 23 06:43:39 PM PDT 24
Peak memory 206756 kb
Host smart-4070397c-5e1c-4942-9c31-c9347cc9126d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38325
31711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.3832531711
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.3547047782
Short name T2243
Test name
Test status
Simulation time 19369437663 ps
CPU time 40.22 seconds
Started Jul 23 06:43:43 PM PDT 24
Finished Jul 23 06:44:30 PM PDT 24
Peak memory 206988 kb
Host smart-bef4f19b-8acd-467a-9d52-50ab10d9eb54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35470
47782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.3547047782
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.38902984
Short name T976
Test name
Test status
Simulation time 419670059 ps
CPU time 1.3 seconds
Started Jul 23 06:43:39 PM PDT 24
Finished Jul 23 06:43:45 PM PDT 24
Peak memory 206704 kb
Host smart-f9f30baf-8b98-45b0-8eb5-cd87b7c550c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38902
984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.38902984
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.2720191264
Short name T882
Test name
Test status
Simulation time 162310316 ps
CPU time 0.83 seconds
Started Jul 23 06:43:39 PM PDT 24
Finished Jul 23 06:43:44 PM PDT 24
Peak memory 206728 kb
Host smart-a1dba059-f3ba-4142-b95e-a23d616fe006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27201
91264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.2720191264
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.509181683
Short name T2438
Test name
Test status
Simulation time 27880429 ps
CPU time 0.64 seconds
Started Jul 23 06:43:33 PM PDT 24
Finished Jul 23 06:43:38 PM PDT 24
Peak memory 206780 kb
Host smart-265208b6-d29e-4ba6-94b3-6f7b2718732a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50918
1683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.509181683
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.3328825554
Short name T582
Test name
Test status
Simulation time 995101954 ps
CPU time 2.38 seconds
Started Jul 23 06:43:37 PM PDT 24
Finished Jul 23 06:43:43 PM PDT 24
Peak memory 206904 kb
Host smart-412697cc-8b8b-4ce5-82c4-e89f0104cce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33288
25554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.3328825554
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.2797456131
Short name T2736
Test name
Test status
Simulation time 238814902 ps
CPU time 1.25 seconds
Started Jul 23 06:43:33 PM PDT 24
Finished Jul 23 06:43:39 PM PDT 24
Peak memory 206852 kb
Host smart-a5f81cda-bc63-4756-b7cd-8c3912cf2dd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27974
56131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.2797456131
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.3186863191
Short name T850
Test name
Test status
Simulation time 232129768 ps
CPU time 0.93 seconds
Started Jul 23 06:43:43 PM PDT 24
Finished Jul 23 06:43:51 PM PDT 24
Peak memory 206756 kb
Host smart-dd237c83-1ef4-485f-a008-a75612323a35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31868
63191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.3186863191
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.75505625
Short name T1248
Test name
Test status
Simulation time 144993600 ps
CPU time 0.83 seconds
Started Jul 23 06:43:39 PM PDT 24
Finished Jul 23 06:43:45 PM PDT 24
Peak memory 206748 kb
Host smart-62207148-5732-4fba-ac45-3719aa685914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75505
625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.75505625
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.2873327975
Short name T2010
Test name
Test status
Simulation time 214422326 ps
CPU time 0.87 seconds
Started Jul 23 06:43:45 PM PDT 24
Finished Jul 23 06:43:53 PM PDT 24
Peak memory 206728 kb
Host smart-762647ae-09c8-4c43-90ee-23c6284f1a2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28733
27975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.2873327975
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.4057682685
Short name T2334
Test name
Test status
Simulation time 5086114504 ps
CPU time 142.69 seconds
Started Jul 23 06:43:39 PM PDT 24
Finished Jul 23 06:46:06 PM PDT 24
Peak memory 206892 kb
Host smart-68dc23a1-cb6d-4aef-803b-54b0f2c07b6b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4057682685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.4057682685
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_iso_retraction.2340507005
Short name T1898
Test name
Test status
Simulation time 9829343231 ps
CPU time 84.24 seconds
Started Jul 23 06:43:40 PM PDT 24
Finished Jul 23 06:45:09 PM PDT 24
Peak memory 206896 kb
Host smart-f0066d8b-dc9f-461f-9737-3351822bcfbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23405
07005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_iso_retraction.2340507005
Directory /workspace/31.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.1100152197
Short name T1589
Test name
Test status
Simulation time 204956332 ps
CPU time 0.89 seconds
Started Jul 23 06:43:40 PM PDT 24
Finished Jul 23 06:43:47 PM PDT 24
Peak memory 206776 kb
Host smart-387f9fac-e126-40fc-ae85-4eef2e0499e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11001
52197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.1100152197
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.1611308150
Short name T1779
Test name
Test status
Simulation time 23285194252 ps
CPU time 23.59 seconds
Started Jul 23 06:43:41 PM PDT 24
Finished Jul 23 06:44:11 PM PDT 24
Peak memory 206824 kb
Host smart-ee343d93-b2ef-458c-8056-a7b1feab79a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16113
08150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.1611308150
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.1945782714
Short name T1204
Test name
Test status
Simulation time 3342105144 ps
CPU time 4.24 seconds
Started Jul 23 06:43:46 PM PDT 24
Finished Jul 23 06:43:57 PM PDT 24
Peak memory 206792 kb
Host smart-cff41664-ff90-45d3-a822-dc7e3d4d41ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19457
82714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.1945782714
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.1325060259
Short name T1275
Test name
Test status
Simulation time 7449308024 ps
CPU time 205.43 seconds
Started Jul 23 06:43:42 PM PDT 24
Finished Jul 23 06:47:14 PM PDT 24
Peak memory 206960 kb
Host smart-8509d26a-0a6e-46fe-9e78-03d1e5825b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13250
60259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.1325060259
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.746687859
Short name T1691
Test name
Test status
Simulation time 7348785262 ps
CPU time 69.9 seconds
Started Jul 23 06:43:39 PM PDT 24
Finished Jul 23 06:44:53 PM PDT 24
Peak memory 206888 kb
Host smart-f1c81e19-592f-49a7-bc36-081e8d96f8bd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=746687859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.746687859
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.2291421541
Short name T1724
Test name
Test status
Simulation time 235890629 ps
CPU time 0.92 seconds
Started Jul 23 06:43:44 PM PDT 24
Finished Jul 23 06:43:53 PM PDT 24
Peak memory 206748 kb
Host smart-7dfcaf52-17b2-47eb-8a29-b79269a4c9ce
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2291421541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.2291421541
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.2851049554
Short name T2653
Test name
Test status
Simulation time 225489238 ps
CPU time 0.91 seconds
Started Jul 23 06:43:42 PM PDT 24
Finished Jul 23 06:43:49 PM PDT 24
Peak memory 206768 kb
Host smart-b145126d-81b7-4072-b47a-3e62b2124589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28510
49554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.2851049554
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.2775124575
Short name T2449
Test name
Test status
Simulation time 4792160933 ps
CPU time 35.68 seconds
Started Jul 23 06:43:38 PM PDT 24
Finished Jul 23 06:44:18 PM PDT 24
Peak memory 206932 kb
Host smart-e0bff5e6-0fb2-48c8-990f-5e54f4096b4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27751
24575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.2775124575
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.2697727283
Short name T796
Test name
Test status
Simulation time 6909660193 ps
CPU time 61.86 seconds
Started Jul 23 06:43:43 PM PDT 24
Finished Jul 23 06:44:53 PM PDT 24
Peak memory 206956 kb
Host smart-360f90d1-40aa-4223-a924-04e5206566bb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2697727283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.2697727283
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.1572841275
Short name T2387
Test name
Test status
Simulation time 174399434 ps
CPU time 0.87 seconds
Started Jul 23 06:43:42 PM PDT 24
Finished Jul 23 06:43:51 PM PDT 24
Peak memory 206760 kb
Host smart-85bb3be7-b88c-4724-b747-f5ba0d38b5f5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1572841275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.1572841275
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.2455561281
Short name T2051
Test name
Test status
Simulation time 152094089 ps
CPU time 0.77 seconds
Started Jul 23 06:43:44 PM PDT 24
Finished Jul 23 06:43:53 PM PDT 24
Peak memory 206768 kb
Host smart-34c052ad-63b9-445c-b8aa-c31b658acff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24555
61281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.2455561281
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.2759393703
Short name T147
Test name
Test status
Simulation time 208212862 ps
CPU time 0.88 seconds
Started Jul 23 06:43:38 PM PDT 24
Finished Jul 23 06:43:43 PM PDT 24
Peak memory 206752 kb
Host smart-04004096-6ac2-41d6-9ddb-2b53d8d3d987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27593
93703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.2759393703
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.2658272431
Short name T2690
Test name
Test status
Simulation time 194332771 ps
CPU time 0.88 seconds
Started Jul 23 06:43:44 PM PDT 24
Finished Jul 23 06:43:52 PM PDT 24
Peak memory 206752 kb
Host smart-e9fd7ef8-c5d6-41eb-82ea-0648f99cfddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26582
72431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.2658272431
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.822585889
Short name T2728
Test name
Test status
Simulation time 145020396 ps
CPU time 0.76 seconds
Started Jul 23 06:43:45 PM PDT 24
Finished Jul 23 06:43:53 PM PDT 24
Peak memory 206748 kb
Host smart-36d1c79d-2032-432f-b117-df1c5bd169a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82258
5889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.822585889
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.2088595120
Short name T1320
Test name
Test status
Simulation time 217854609 ps
CPU time 0.87 seconds
Started Jul 23 06:43:43 PM PDT 24
Finished Jul 23 06:43:52 PM PDT 24
Peak memory 206740 kb
Host smart-5d3c8452-e8de-4f45-9afc-120888ebc59b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20885
95120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.2088595120
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.2993296085
Short name T2046
Test name
Test status
Simulation time 161933439 ps
CPU time 0.8 seconds
Started Jul 23 06:43:41 PM PDT 24
Finished Jul 23 06:43:47 PM PDT 24
Peak memory 206784 kb
Host smart-6af7d78f-9b8d-45d9-aedb-ade1525634c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29932
96085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.2993296085
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.3214240622
Short name T1039
Test name
Test status
Simulation time 223484614 ps
CPU time 0.86 seconds
Started Jul 23 06:43:41 PM PDT 24
Finished Jul 23 06:43:48 PM PDT 24
Peak memory 206740 kb
Host smart-1ab64389-8d88-450c-92af-6bca631954f6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3214240622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.3214240622
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.3169445261
Short name T891
Test name
Test status
Simulation time 210331635 ps
CPU time 0.89 seconds
Started Jul 23 06:43:45 PM PDT 24
Finished Jul 23 06:43:54 PM PDT 24
Peak memory 206724 kb
Host smart-a1cb8f8a-82ca-448c-ba3a-7aebd5eafdbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31694
45261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.3169445261
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.615573363
Short name T968
Test name
Test status
Simulation time 37166375 ps
CPU time 0.64 seconds
Started Jul 23 06:43:41 PM PDT 24
Finished Jul 23 06:43:47 PM PDT 24
Peak memory 206748 kb
Host smart-e84dc843-47f5-404f-8517-fea653be982c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61557
3363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.615573363
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.1723736024
Short name T246
Test name
Test status
Simulation time 21423866479 ps
CPU time 49.45 seconds
Started Jul 23 06:43:40 PM PDT 24
Finished Jul 23 06:44:34 PM PDT 24
Peak memory 206972 kb
Host smart-137fdd2d-a769-46b7-98cb-fd10b662804f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17237
36024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.1723736024
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.3462073346
Short name T1213
Test name
Test status
Simulation time 197583204 ps
CPU time 0.83 seconds
Started Jul 23 06:43:40 PM PDT 24
Finished Jul 23 06:43:45 PM PDT 24
Peak memory 206744 kb
Host smart-03a4956f-2eba-4c6d-bfd1-588120b72b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34620
73346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.3462073346
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.477921375
Short name T1639
Test name
Test status
Simulation time 170479667 ps
CPU time 0.8 seconds
Started Jul 23 06:43:39 PM PDT 24
Finished Jul 23 06:43:43 PM PDT 24
Peak memory 206764 kb
Host smart-980266db-ea70-4263-933c-6afa8f8479e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47792
1375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.477921375
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.1063385180
Short name T2404
Test name
Test status
Simulation time 231447385 ps
CPU time 0.95 seconds
Started Jul 23 06:43:39 PM PDT 24
Finished Jul 23 06:43:44 PM PDT 24
Peak memory 206784 kb
Host smart-6974ed8e-049d-4b6f-a1fa-1703d3926a75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10633
85180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.1063385180
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.1637759506
Short name T1413
Test name
Test status
Simulation time 177002861 ps
CPU time 0.82 seconds
Started Jul 23 06:43:40 PM PDT 24
Finished Jul 23 06:43:45 PM PDT 24
Peak memory 206736 kb
Host smart-4f08c640-4914-496d-8e8a-05489c2f3ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16377
59506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.1637759506
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.3479084061
Short name T1998
Test name
Test status
Simulation time 158006846 ps
CPU time 0.77 seconds
Started Jul 23 06:43:45 PM PDT 24
Finished Jul 23 06:43:53 PM PDT 24
Peak memory 206704 kb
Host smart-54e62885-1a71-4c0a-8eb3-151b78474ef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34790
84061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.3479084061
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.4085728023
Short name T757
Test name
Test status
Simulation time 167726935 ps
CPU time 0.78 seconds
Started Jul 23 06:43:38 PM PDT 24
Finished Jul 23 06:43:43 PM PDT 24
Peak memory 206928 kb
Host smart-064b3303-fcc9-4d83-a7f4-e75610abc344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40857
28023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.4085728023
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.1121928099
Short name T1987
Test name
Test status
Simulation time 205382732 ps
CPU time 0.84 seconds
Started Jul 23 06:43:42 PM PDT 24
Finished Jul 23 06:43:49 PM PDT 24
Peak memory 206760 kb
Host smart-0b12624d-e7be-43da-8e7d-d53d8ba2c69b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11219
28099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.1121928099
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.425843964
Short name T2552
Test name
Test status
Simulation time 178235092 ps
CPU time 0.84 seconds
Started Jul 23 06:43:41 PM PDT 24
Finished Jul 23 06:43:48 PM PDT 24
Peak memory 206764 kb
Host smart-2ddf06b2-62a6-4dd0-8f49-3a64dcf090a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42584
3964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.425843964
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.4177286815
Short name T2678
Test name
Test status
Simulation time 3319399636 ps
CPU time 24.21 seconds
Started Jul 23 06:43:40 PM PDT 24
Finished Jul 23 06:44:08 PM PDT 24
Peak memory 206952 kb
Host smart-6fe2c132-412e-4a6a-8ab7-38c95daeb767
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4177286815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.4177286815
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.754609612
Short name T1220
Test name
Test status
Simulation time 190479550 ps
CPU time 0.83 seconds
Started Jul 23 06:43:44 PM PDT 24
Finished Jul 23 06:43:52 PM PDT 24
Peak memory 206768 kb
Host smart-25dcf6e8-52bc-41c5-8a23-634a5714c22b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75460
9612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.754609612
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.1395887057
Short name T2098
Test name
Test status
Simulation time 203678020 ps
CPU time 0.87 seconds
Started Jul 23 06:43:42 PM PDT 24
Finished Jul 23 06:43:49 PM PDT 24
Peak memory 206768 kb
Host smart-b7e86e96-917e-4e2f-9696-7d7af8f66ac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13958
87057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.1395887057
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.2425351829
Short name T2647
Test name
Test status
Simulation time 443622449 ps
CPU time 1.33 seconds
Started Jul 23 06:43:40 PM PDT 24
Finished Jul 23 06:43:46 PM PDT 24
Peak memory 206776 kb
Host smart-59ba7c97-858a-4b20-b58b-a108cd3812e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24253
51829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.2425351829
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.3453735713
Short name T572
Test name
Test status
Simulation time 7917779322 ps
CPU time 230.93 seconds
Started Jul 23 06:43:41 PM PDT 24
Finished Jul 23 06:47:39 PM PDT 24
Peak memory 206900 kb
Host smart-79b7b176-c13b-4249-b7aa-f2697eb21212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34537
35713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.3453735713
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.2781338615
Short name T2269
Test name
Test status
Simulation time 39482606 ps
CPU time 0.69 seconds
Started Jul 23 06:43:54 PM PDT 24
Finished Jul 23 06:43:58 PM PDT 24
Peak memory 206752 kb
Host smart-accd58dd-9718-44bf-b917-4477bdc4f334
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2781338615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.2781338615
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.1017901580
Short name T927
Test name
Test status
Simulation time 4391632235 ps
CPU time 4.98 seconds
Started Jul 23 06:43:44 PM PDT 24
Finished Jul 23 06:43:57 PM PDT 24
Peak memory 206984 kb
Host smart-c7b4bf66-28b4-4e3a-8a01-9408af7f1bca
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1017901580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.1017901580
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.2976577112
Short name T436
Test name
Test status
Simulation time 13442713661 ps
CPU time 14.58 seconds
Started Jul 23 06:43:42 PM PDT 24
Finished Jul 23 06:44:03 PM PDT 24
Peak memory 206892 kb
Host smart-f5c3ff86-ae31-4736-99f9-ccc2bb0e4d45
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2976577112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.2976577112
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.1378739204
Short name T13
Test name
Test status
Simulation time 23309903386 ps
CPU time 27.45 seconds
Started Jul 23 06:43:43 PM PDT 24
Finished Jul 23 06:44:18 PM PDT 24
Peak memory 206964 kb
Host smart-81429453-f814-49f8-90a0-4a85e984b031
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1378739204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.1378739204
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.2506721996
Short name T1467
Test name
Test status
Simulation time 179267669 ps
CPU time 0.86 seconds
Started Jul 23 06:43:43 PM PDT 24
Finished Jul 23 06:43:51 PM PDT 24
Peak memory 206760 kb
Host smart-e7f10b67-faec-44fb-96fc-9abc3db40271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25067
21996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.2506721996
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.4225041891
Short name T1369
Test name
Test status
Simulation time 159609422 ps
CPU time 0.86 seconds
Started Jul 23 06:43:43 PM PDT 24
Finished Jul 23 06:43:52 PM PDT 24
Peak memory 206728 kb
Host smart-4cc6c6ec-9745-467d-a0af-564dd260b293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42250
41891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.4225041891
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.1739200925
Short name T2219
Test name
Test status
Simulation time 407390050 ps
CPU time 1.33 seconds
Started Jul 23 06:43:53 PM PDT 24
Finished Jul 23 06:43:57 PM PDT 24
Peak memory 206740 kb
Host smart-8b6410a6-30d0-4ab9-9ae9-7c95ea3b6093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17392
00925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.1739200925
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.3938211233
Short name T2604
Test name
Test status
Simulation time 558587644 ps
CPU time 1.47 seconds
Started Jul 23 06:43:43 PM PDT 24
Finished Jul 23 06:43:53 PM PDT 24
Peak memory 206732 kb
Host smart-22d6b04e-e368-423e-92d2-f7bfbdbcc330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39382
11233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.3938211233
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.1915013930
Short name T2167
Test name
Test status
Simulation time 12106745165 ps
CPU time 26.44 seconds
Started Jul 23 06:43:43 PM PDT 24
Finished Jul 23 06:44:18 PM PDT 24
Peak memory 206904 kb
Host smart-3c331c77-380a-48db-bda6-2522d464b217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19150
13930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.1915013930
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.4196670841
Short name T487
Test name
Test status
Simulation time 349169395 ps
CPU time 1.21 seconds
Started Jul 23 06:43:44 PM PDT 24
Finished Jul 23 06:43:53 PM PDT 24
Peak memory 206760 kb
Host smart-3acb236c-2c86-4731-a512-68d573de2fb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41966
70841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.4196670841
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.2692319110
Short name T1572
Test name
Test status
Simulation time 199733508 ps
CPU time 0.77 seconds
Started Jul 23 06:43:44 PM PDT 24
Finished Jul 23 06:43:52 PM PDT 24
Peak memory 206776 kb
Host smart-97cae36d-ac66-4984-b2cf-01cf175a4c7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26923
19110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.2692319110
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.322803739
Short name T691
Test name
Test status
Simulation time 38447051 ps
CPU time 0.69 seconds
Started Jul 23 06:43:45 PM PDT 24
Finished Jul 23 06:43:53 PM PDT 24
Peak memory 206760 kb
Host smart-2ef9c0d3-3182-4adb-b187-e4f1911883e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32280
3739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.322803739
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.2814091249
Short name T1715
Test name
Test status
Simulation time 884087607 ps
CPU time 2.15 seconds
Started Jul 23 06:43:53 PM PDT 24
Finished Jul 23 06:43:58 PM PDT 24
Peak memory 206888 kb
Host smart-bc492c04-f311-4207-964e-63d924aaf900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28140
91249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.2814091249
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.1532877622
Short name T2566
Test name
Test status
Simulation time 212418036 ps
CPU time 1.63 seconds
Started Jul 23 06:43:43 PM PDT 24
Finished Jul 23 06:43:52 PM PDT 24
Peak memory 206852 kb
Host smart-7c3ebf00-846c-42f7-8f64-6e873b96d023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15328
77622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.1532877622
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.4164629547
Short name T1316
Test name
Test status
Simulation time 224287514 ps
CPU time 0.96 seconds
Started Jul 23 06:43:45 PM PDT 24
Finished Jul 23 06:43:53 PM PDT 24
Peak memory 206760 kb
Host smart-116f4752-cce4-4f20-8413-d60c2a36c992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41646
29547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.4164629547
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.1482773739
Short name T517
Test name
Test status
Simulation time 146786930 ps
CPU time 0.8 seconds
Started Jul 23 06:43:46 PM PDT 24
Finished Jul 23 06:43:54 PM PDT 24
Peak memory 206708 kb
Host smart-040f5ba2-6ede-4d5f-bd5a-cfd492899b5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14827
73739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.1482773739
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.730206988
Short name T560
Test name
Test status
Simulation time 224376735 ps
CPU time 1 seconds
Started Jul 23 06:43:44 PM PDT 24
Finished Jul 23 06:43:52 PM PDT 24
Peak memory 206752 kb
Host smart-62a1a5fa-873c-4511-82cb-f9cc934c502c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73020
6988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.730206988
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_iso_retraction.3508896064
Short name T96
Test name
Test status
Simulation time 7894492776 ps
CPU time 72.91 seconds
Started Jul 23 06:43:45 PM PDT 24
Finished Jul 23 06:45:05 PM PDT 24
Peak memory 206900 kb
Host smart-a2dddddf-c365-4eb1-af77-c6672d13d084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35088
96064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.3508896064
Directory /workspace/32.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.2949645601
Short name T1654
Test name
Test status
Simulation time 182053661 ps
CPU time 0.8 seconds
Started Jul 23 06:43:42 PM PDT 24
Finished Jul 23 06:43:50 PM PDT 24
Peak memory 206736 kb
Host smart-dbdba2da-1df6-419c-9517-63a94f657188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29496
45601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.2949645601
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.1675049494
Short name T2388
Test name
Test status
Simulation time 23316314457 ps
CPU time 21.12 seconds
Started Jul 23 06:43:44 PM PDT 24
Finished Jul 23 06:44:12 PM PDT 24
Peak memory 206796 kb
Host smart-ff9bc50b-2cdb-458d-acbc-7407471d2fca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16750
49494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.1675049494
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.445427287
Short name T2045
Test name
Test status
Simulation time 3388736294 ps
CPU time 3.99 seconds
Started Jul 23 06:43:44 PM PDT 24
Finished Jul 23 06:43:55 PM PDT 24
Peak memory 206784 kb
Host smart-57f9a705-92fb-4731-84df-c0935374e17e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44542
7287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.445427287
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.3767709571
Short name T1173
Test name
Test status
Simulation time 10748440869 ps
CPU time 107.34 seconds
Started Jul 23 06:43:44 PM PDT 24
Finished Jul 23 06:45:39 PM PDT 24
Peak memory 206988 kb
Host smart-44eadee2-0ca9-48f8-bdb0-d100f3159f93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37677
09571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.3767709571
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.1125489512
Short name T2041
Test name
Test status
Simulation time 4308686969 ps
CPU time 29.76 seconds
Started Jul 23 06:43:43 PM PDT 24
Finished Jul 23 06:44:21 PM PDT 24
Peak memory 206864 kb
Host smart-42ae4405-91ae-4f46-813e-1db739ca5c58
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1125489512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.1125489512
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.2988668204
Short name T2396
Test name
Test status
Simulation time 276486589 ps
CPU time 0.92 seconds
Started Jul 23 06:43:52 PM PDT 24
Finished Jul 23 06:43:57 PM PDT 24
Peak memory 206752 kb
Host smart-46aefc23-5263-4c30-a019-33dbb07b12d1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2988668204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.2988668204
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.3834118066
Short name T2181
Test name
Test status
Simulation time 209494922 ps
CPU time 0.89 seconds
Started Jul 23 06:43:54 PM PDT 24
Finished Jul 23 06:43:59 PM PDT 24
Peak memory 206756 kb
Host smart-ffda09f8-dab9-4aea-ac37-b4547594dfe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38341
18066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.3834118066
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.2889870497
Short name T1934
Test name
Test status
Simulation time 6826003056 ps
CPU time 64.85 seconds
Started Jul 23 06:43:53 PM PDT 24
Finished Jul 23 06:45:01 PM PDT 24
Peak memory 206964 kb
Host smart-7c93e7f7-eacf-413b-ac76-bfe7014d36b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28898
70497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.2889870497
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.743391684
Short name T2491
Test name
Test status
Simulation time 6743231202 ps
CPU time 173.88 seconds
Started Jul 23 06:43:53 PM PDT 24
Finished Jul 23 06:46:50 PM PDT 24
Peak memory 206828 kb
Host smart-ab86fff1-ff67-4727-8ed5-1a10b5423280
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=743391684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.743391684
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.4667609
Short name T779
Test name
Test status
Simulation time 162793484 ps
CPU time 0.83 seconds
Started Jul 23 06:43:56 PM PDT 24
Finished Jul 23 06:44:01 PM PDT 24
Peak memory 206724 kb
Host smart-c7528106-1825-46a8-bde9-95819a6d92ec
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4667609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.4667609
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.202378304
Short name T1538
Test name
Test status
Simulation time 152389310 ps
CPU time 0.79 seconds
Started Jul 23 06:43:53 PM PDT 24
Finished Jul 23 06:43:57 PM PDT 24
Peak memory 206732 kb
Host smart-ee1954b5-6fbe-4549-94e4-cf34672d8a92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20237
8304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.202378304
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.2997078137
Short name T123
Test name
Test status
Simulation time 197282668 ps
CPU time 0.89 seconds
Started Jul 23 06:43:54 PM PDT 24
Finished Jul 23 06:43:58 PM PDT 24
Peak memory 206748 kb
Host smart-a0f9e918-d111-468f-ba17-3afc8775b23c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29970
78137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.2997078137
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.2060414420
Short name T1118
Test name
Test status
Simulation time 170231930 ps
CPU time 0.85 seconds
Started Jul 23 06:43:55 PM PDT 24
Finished Jul 23 06:44:01 PM PDT 24
Peak memory 206772 kb
Host smart-7c957406-f226-40ac-84c5-e66b850658a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20604
14420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.2060414420
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.2022408950
Short name T2725
Test name
Test status
Simulation time 163035607 ps
CPU time 0.88 seconds
Started Jul 23 06:43:55 PM PDT 24
Finished Jul 23 06:43:59 PM PDT 24
Peak memory 206780 kb
Host smart-b0a55394-3da9-469c-900f-a50480c7ee9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20224
08950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.2022408950
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.3170144833
Short name T1425
Test name
Test status
Simulation time 155601308 ps
CPU time 0.84 seconds
Started Jul 23 06:43:53 PM PDT 24
Finished Jul 23 06:43:57 PM PDT 24
Peak memory 206748 kb
Host smart-670f5d25-d3a5-4966-ad21-5ac21727fc86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31701
44833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.3170144833
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.2931138267
Short name T1139
Test name
Test status
Simulation time 168329321 ps
CPU time 0.82 seconds
Started Jul 23 06:43:55 PM PDT 24
Finished Jul 23 06:44:00 PM PDT 24
Peak memory 206772 kb
Host smart-d24050a2-9dc8-4448-9ff9-e99dafb4e5b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29311
38267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.2931138267
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.2777092944
Short name T2379
Test name
Test status
Simulation time 211427065 ps
CPU time 0.95 seconds
Started Jul 23 06:43:55 PM PDT 24
Finished Jul 23 06:44:01 PM PDT 24
Peak memory 206756 kb
Host smart-a7f0353c-2d14-418f-8af1-af9066e67d7f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2777092944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.2777092944
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.549038504
Short name T2625
Test name
Test status
Simulation time 149306705 ps
CPU time 0.78 seconds
Started Jul 23 06:43:55 PM PDT 24
Finished Jul 23 06:43:59 PM PDT 24
Peak memory 206756 kb
Host smart-13502561-1422-4998-97f3-5af4b23b24ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54903
8504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.549038504
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.3276294626
Short name T33
Test name
Test status
Simulation time 52459426 ps
CPU time 0.68 seconds
Started Jul 23 06:43:56 PM PDT 24
Finished Jul 23 06:44:01 PM PDT 24
Peak memory 206748 kb
Host smart-863fe831-826b-4bf3-96bb-266fedaa5c8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32762
94626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.3276294626
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.1447492917
Short name T1131
Test name
Test status
Simulation time 20690499696 ps
CPU time 45.32 seconds
Started Jul 23 06:43:56 PM PDT 24
Finished Jul 23 06:44:46 PM PDT 24
Peak memory 206984 kb
Host smart-49566a30-7193-47cf-8083-632d216c0a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14474
92917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.1447492917
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.1289653604
Short name T2129
Test name
Test status
Simulation time 189221462 ps
CPU time 0.89 seconds
Started Jul 23 06:43:53 PM PDT 24
Finished Jul 23 06:43:57 PM PDT 24
Peak memory 206740 kb
Host smart-dc2fe5b9-78df-47b9-86ae-d8c996cf8114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12896
53604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.1289653604
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.2008818451
Short name T1850
Test name
Test status
Simulation time 198785336 ps
CPU time 0.9 seconds
Started Jul 23 06:43:57 PM PDT 24
Finished Jul 23 06:44:03 PM PDT 24
Peak memory 206756 kb
Host smart-ca9368f3-e9ba-4728-bbbc-1560dbb3c988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20088
18451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.2008818451
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.25617618
Short name T1666
Test name
Test status
Simulation time 212643962 ps
CPU time 0.85 seconds
Started Jul 23 06:43:58 PM PDT 24
Finished Jul 23 06:44:04 PM PDT 24
Peak memory 206748 kb
Host smart-8063ba35-0d47-4388-98b2-2292df298975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25617
618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.25617618
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.2395828795
Short name T1505
Test name
Test status
Simulation time 156327864 ps
CPU time 0.82 seconds
Started Jul 23 06:43:56 PM PDT 24
Finished Jul 23 06:44:03 PM PDT 24
Peak memory 206748 kb
Host smart-755ee903-67a0-4c01-a493-a30b24b4884a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23958
28795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.2395828795
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.2834952937
Short name T2157
Test name
Test status
Simulation time 154294601 ps
CPU time 0.79 seconds
Started Jul 23 06:43:54 PM PDT 24
Finished Jul 23 06:43:58 PM PDT 24
Peak memory 206740 kb
Host smart-8a9f0839-a22b-4ada-8d68-cb4af8fe3bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28349
52937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.2834952937
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.736442109
Short name T1069
Test name
Test status
Simulation time 155677583 ps
CPU time 0.77 seconds
Started Jul 23 06:43:55 PM PDT 24
Finished Jul 23 06:44:01 PM PDT 24
Peak memory 206720 kb
Host smart-62a42a9c-3021-47ee-b2e4-d43df1e603d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73644
2109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.736442109
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.86762054
Short name T1739
Test name
Test status
Simulation time 151140200 ps
CPU time 0.79 seconds
Started Jul 23 06:43:58 PM PDT 24
Finished Jul 23 06:44:03 PM PDT 24
Peak memory 206748 kb
Host smart-ca0b6541-b96e-446d-aa62-004ee41c5011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86762
054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.86762054
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.642844568
Short name T1460
Test name
Test status
Simulation time 179740832 ps
CPU time 0.9 seconds
Started Jul 23 06:43:57 PM PDT 24
Finished Jul 23 06:44:03 PM PDT 24
Peak memory 206760 kb
Host smart-437f39ae-d09a-4162-9ea3-e8921574d410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64284
4568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.642844568
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.3427806538
Short name T2365
Test name
Test status
Simulation time 3716796865 ps
CPU time 34.91 seconds
Started Jul 23 06:43:56 PM PDT 24
Finished Jul 23 06:44:37 PM PDT 24
Peak memory 206884 kb
Host smart-7789d56a-133e-4956-a1bc-fc56b28603da
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3427806538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.3427806538
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.1896278765
Short name T2005
Test name
Test status
Simulation time 161157630 ps
CPU time 0.83 seconds
Started Jul 23 06:43:57 PM PDT 24
Finished Jul 23 06:44:03 PM PDT 24
Peak memory 206740 kb
Host smart-3a158ce4-c469-4b4e-a1c1-6c2db1fe0336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18962
78765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.1896278765
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.1146385899
Short name T2324
Test name
Test status
Simulation time 183265718 ps
CPU time 0.8 seconds
Started Jul 23 06:43:56 PM PDT 24
Finished Jul 23 06:44:01 PM PDT 24
Peak memory 206764 kb
Host smart-4408c404-2e5b-48ad-9ec9-5411b90070cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11463
85899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.1146385899
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.2938762901
Short name T358
Test name
Test status
Simulation time 332668560 ps
CPU time 1.11 seconds
Started Jul 23 06:43:58 PM PDT 24
Finished Jul 23 06:44:04 PM PDT 24
Peak memory 206752 kb
Host smart-d304ed37-4908-48a6-9cc9-ef5c9bfab892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29387
62901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.2938762901
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.370590124
Short name T342
Test name
Test status
Simulation time 5961711158 ps
CPU time 45.44 seconds
Started Jul 23 06:43:53 PM PDT 24
Finished Jul 23 06:44:41 PM PDT 24
Peak memory 206964 kb
Host smart-d76656c2-3265-400d-ae4c-0fb8c5698146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37059
0124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.370590124
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.3547732362
Short name T2391
Test name
Test status
Simulation time 52556736 ps
CPU time 0.67 seconds
Started Jul 23 06:44:18 PM PDT 24
Finished Jul 23 06:44:22 PM PDT 24
Peak memory 206728 kb
Host smart-315d89ff-ee59-4c80-b9db-706904a0924b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3547732362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.3547732362
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.4041379854
Short name T1714
Test name
Test status
Simulation time 4255366750 ps
CPU time 4.86 seconds
Started Jul 23 06:43:59 PM PDT 24
Finished Jul 23 06:44:09 PM PDT 24
Peak memory 206972 kb
Host smart-c5fc9e69-b908-4d43-81f4-4259ea2d6678
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4041379854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.4041379854
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.1612086367
Short name T198
Test name
Test status
Simulation time 13430931849 ps
CPU time 12.55 seconds
Started Jul 23 06:44:00 PM PDT 24
Finished Jul 23 06:44:17 PM PDT 24
Peak memory 206836 kb
Host smart-fc250e1f-08e9-42d9-b583-1d9ce143c170
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1612086367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.1612086367
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.1007944921
Short name T398
Test name
Test status
Simulation time 23319697122 ps
CPU time 22.89 seconds
Started Jul 23 06:44:00 PM PDT 24
Finished Jul 23 06:44:27 PM PDT 24
Peak memory 206920 kb
Host smart-5c72304e-558c-4154-b2b5-20f7d30d6af3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1007944921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.1007944921
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.1872826407
Short name T1348
Test name
Test status
Simulation time 180107533 ps
CPU time 0.85 seconds
Started Jul 23 06:44:02 PM PDT 24
Finished Jul 23 06:44:06 PM PDT 24
Peak memory 206784 kb
Host smart-704dc780-283f-456f-9c2b-bfb325a149aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18728
26407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.1872826407
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.52677825
Short name T2599
Test name
Test status
Simulation time 157039837 ps
CPU time 0.79 seconds
Started Jul 23 06:44:00 PM PDT 24
Finished Jul 23 06:44:05 PM PDT 24
Peak memory 206736 kb
Host smart-4a3e69fd-9561-4aa5-8de6-5df12a0e15b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52677
825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.52677825
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.1233478442
Short name T589
Test name
Test status
Simulation time 446616438 ps
CPU time 1.49 seconds
Started Jul 23 06:44:02 PM PDT 24
Finished Jul 23 06:44:07 PM PDT 24
Peak memory 206924 kb
Host smart-09daf036-ad83-4795-be81-a96be01d63bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12334
78442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.1233478442
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.2193890495
Short name T1635
Test name
Test status
Simulation time 936288034 ps
CPU time 2.36 seconds
Started Jul 23 06:44:01 PM PDT 24
Finished Jul 23 06:44:07 PM PDT 24
Peak memory 206880 kb
Host smart-3af90363-7f2d-41ba-bbe7-b34c90a04dca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21938
90495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.2193890495
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.2651859020
Short name T1636
Test name
Test status
Simulation time 21695092382 ps
CPU time 42.94 seconds
Started Jul 23 06:43:59 PM PDT 24
Finished Jul 23 06:44:47 PM PDT 24
Peak memory 206896 kb
Host smart-2e56888f-f683-4cf4-8499-bf159ce54474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26518
59020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.2651859020
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.482266603
Short name T721
Test name
Test status
Simulation time 423604582 ps
CPU time 1.35 seconds
Started Jul 23 06:44:07 PM PDT 24
Finished Jul 23 06:44:11 PM PDT 24
Peak memory 206724 kb
Host smart-ef9ef638-241e-40e8-a46e-a4a15cdd5983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48226
6603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.482266603
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.2553591929
Short name T1961
Test name
Test status
Simulation time 164579328 ps
CPU time 0.79 seconds
Started Jul 23 06:44:08 PM PDT 24
Finished Jul 23 06:44:11 PM PDT 24
Peak memory 206748 kb
Host smart-0bf60a1d-2218-4393-b87e-71765b20c153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25535
91929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.2553591929
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.2627055513
Short name T1545
Test name
Test status
Simulation time 46122885 ps
CPU time 0.65 seconds
Started Jul 23 06:44:10 PM PDT 24
Finished Jul 23 06:44:13 PM PDT 24
Peak memory 206740 kb
Host smart-abaae92c-b537-476b-b38b-6d60b297b4ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26270
55513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.2627055513
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.512399915
Short name T769
Test name
Test status
Simulation time 946363155 ps
CPU time 2.28 seconds
Started Jul 23 06:44:08 PM PDT 24
Finished Jul 23 06:44:13 PM PDT 24
Peak memory 206880 kb
Host smart-98f9af35-58fe-41ef-80ea-ee88f6851dd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51239
9915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.512399915
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.3782718096
Short name T2539
Test name
Test status
Simulation time 273961242 ps
CPU time 1.53 seconds
Started Jul 23 06:44:06 PM PDT 24
Finished Jul 23 06:44:11 PM PDT 24
Peak memory 206916 kb
Host smart-766d0792-d93e-43de-a9a2-b0123316e39f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37827
18096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.3782718096
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.4017251200
Short name T2468
Test name
Test status
Simulation time 210714547 ps
CPU time 0.83 seconds
Started Jul 23 06:44:17 PM PDT 24
Finished Jul 23 06:44:21 PM PDT 24
Peak memory 206720 kb
Host smart-af7b806f-6e11-4287-a880-26eb7bdc0250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40172
51200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.4017251200
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.2069066080
Short name T2058
Test name
Test status
Simulation time 159939535 ps
CPU time 0.77 seconds
Started Jul 23 06:44:08 PM PDT 24
Finished Jul 23 06:44:11 PM PDT 24
Peak memory 206772 kb
Host smart-76ef38c7-25d0-46e2-a847-67b2dcb8af4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20690
66080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.2069066080
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.4044467602
Short name T1167
Test name
Test status
Simulation time 236835040 ps
CPU time 0.93 seconds
Started Jul 23 06:44:08 PM PDT 24
Finished Jul 23 06:44:12 PM PDT 24
Peak memory 206768 kb
Host smart-0f482062-602c-4f4b-8486-1d7059487d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40444
67602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.4044467602
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_invalid_sync.1421486269
Short name T2603
Test name
Test status
Simulation time 8433175767 ps
CPU time 62.42 seconds
Started Jul 23 06:44:06 PM PDT 24
Finished Jul 23 06:45:11 PM PDT 24
Peak memory 206944 kb
Host smart-9cc849b1-ab11-43e7-9ce2-34e687e0748d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1421486269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.1421486269
Directory /workspace/33.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/33.usbdev_iso_retraction.3104801247
Short name T1903
Test name
Test status
Simulation time 8362615435 ps
CPU time 25.53 seconds
Started Jul 23 06:44:08 PM PDT 24
Finished Jul 23 06:44:37 PM PDT 24
Peak memory 206904 kb
Host smart-361c419f-133d-4ad9-8d3b-af1b4e157d1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31048
01247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.3104801247
Directory /workspace/33.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.2731023291
Short name T383
Test name
Test status
Simulation time 161793991 ps
CPU time 0.82 seconds
Started Jul 23 06:44:08 PM PDT 24
Finished Jul 23 06:44:12 PM PDT 24
Peak memory 206744 kb
Host smart-c37d5cac-7fd1-4a3b-b7c0-15f978b3e7eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27310
23291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.2731023291
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.564679039
Short name T2709
Test name
Test status
Simulation time 3285592299 ps
CPU time 4.44 seconds
Started Jul 23 06:44:06 PM PDT 24
Finished Jul 23 06:44:13 PM PDT 24
Peak memory 206816 kb
Host smart-9f8b864e-21bf-4e59-8448-2a2e6bb8b89d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56467
9039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.564679039
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.309118413
Short name T1842
Test name
Test status
Simulation time 6648084944 ps
CPU time 64.62 seconds
Started Jul 23 06:44:07 PM PDT 24
Finished Jul 23 06:45:14 PM PDT 24
Peak memory 206976 kb
Host smart-f312ab69-1503-4130-ad69-619265ae0b59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30911
8413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.309118413
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.1127374509
Short name T1834
Test name
Test status
Simulation time 3956670145 ps
CPU time 106.33 seconds
Started Jul 23 06:44:10 PM PDT 24
Finished Jul 23 06:45:59 PM PDT 24
Peak memory 206896 kb
Host smart-f4d31cb6-f24d-4e09-8d9b-ca1a3eb6a89d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1127374509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.1127374509
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.4162353615
Short name T1319
Test name
Test status
Simulation time 239693250 ps
CPU time 0.9 seconds
Started Jul 23 06:44:06 PM PDT 24
Finished Jul 23 06:44:10 PM PDT 24
Peak memory 206676 kb
Host smart-bcb400cd-7a57-4fdc-9d72-3dd8e8bd202b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4162353615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.4162353615
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.3113883472
Short name T386
Test name
Test status
Simulation time 208153906 ps
CPU time 0.95 seconds
Started Jul 23 06:44:08 PM PDT 24
Finished Jul 23 06:44:12 PM PDT 24
Peak memory 206772 kb
Host smart-40a06b7d-1edb-4234-94c9-12ef96668d67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31138
83472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.3113883472
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.2130223043
Short name T2168
Test name
Test status
Simulation time 6670187227 ps
CPU time 183.86 seconds
Started Jul 23 06:44:11 PM PDT 24
Finished Jul 23 06:47:17 PM PDT 24
Peak memory 206912 kb
Host smart-1cba0357-0a67-41b9-8c0c-00adb851a9ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21302
23043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.2130223043
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.692545124
Short name T2680
Test name
Test status
Simulation time 7117413092 ps
CPU time 201.82 seconds
Started Jul 23 06:44:22 PM PDT 24
Finished Jul 23 06:47:49 PM PDT 24
Peak memory 206872 kb
Host smart-b31d054d-c171-4ec0-99a2-1f9341dd0d65
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=692545124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.692545124
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.2926261740
Short name T420
Test name
Test status
Simulation time 156447697 ps
CPU time 0.77 seconds
Started Jul 23 06:44:15 PM PDT 24
Finished Jul 23 06:44:16 PM PDT 24
Peak memory 206752 kb
Host smart-4689b59e-8c16-4372-b231-c074a0594f4b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2926261740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.2926261740
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.836585796
Short name T2646
Test name
Test status
Simulation time 163116551 ps
CPU time 0.74 seconds
Started Jul 23 06:44:24 PM PDT 24
Finished Jul 23 06:44:30 PM PDT 24
Peak memory 206756 kb
Host smart-865764ac-b29d-420a-a55e-d13d8e03612e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83658
5796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.836585796
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.4095415845
Short name T126
Test name
Test status
Simulation time 205596664 ps
CPU time 0.86 seconds
Started Jul 23 06:44:19 PM PDT 24
Finished Jul 23 06:44:25 PM PDT 24
Peak memory 206760 kb
Host smart-0abb566d-6630-45a5-889a-5134efd40923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40954
15845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.4095415845
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.561034362
Short name T1943
Test name
Test status
Simulation time 170872536 ps
CPU time 0.83 seconds
Started Jul 23 06:44:20 PM PDT 24
Finished Jul 23 06:44:26 PM PDT 24
Peak memory 206764 kb
Host smart-b780573c-9f15-4e48-8137-664a4af2ba8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56103
4362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.561034362
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.3010037875
Short name T391
Test name
Test status
Simulation time 184000750 ps
CPU time 0.87 seconds
Started Jul 23 06:44:19 PM PDT 24
Finished Jul 23 06:44:25 PM PDT 24
Peak memory 206760 kb
Host smart-dba19892-42c6-422d-a2b2-ae46b401bae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30100
37875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.3010037875
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.1107509754
Short name T2170
Test name
Test status
Simulation time 188048074 ps
CPU time 0.81 seconds
Started Jul 23 06:44:15 PM PDT 24
Finished Jul 23 06:44:16 PM PDT 24
Peak memory 206640 kb
Host smart-4a564961-7836-4274-9baf-ba3feb856c71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11075
09754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.1107509754
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.1133308809
Short name T518
Test name
Test status
Simulation time 174046861 ps
CPU time 0.86 seconds
Started Jul 23 06:44:16 PM PDT 24
Finished Jul 23 06:44:19 PM PDT 24
Peak memory 206772 kb
Host smart-74dfcf98-cb8d-429f-ade0-44c240d2a67b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11333
08809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.1133308809
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.2289652678
Short name T1134
Test name
Test status
Simulation time 253784612 ps
CPU time 0.89 seconds
Started Jul 23 06:44:15 PM PDT 24
Finished Jul 23 06:44:16 PM PDT 24
Peak memory 206756 kb
Host smart-91e0b5ce-529b-44ba-b6a3-3f105052bf52
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2289652678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.2289652678
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.3343705016
Short name T1005
Test name
Test status
Simulation time 142035120 ps
CPU time 0.79 seconds
Started Jul 23 06:44:19 PM PDT 24
Finished Jul 23 06:44:25 PM PDT 24
Peak memory 206736 kb
Host smart-aece2f01-ed1c-4b4a-ba9f-add0dec18d8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33437
05016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.3343705016
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.3747483878
Short name T2380
Test name
Test status
Simulation time 93934592 ps
CPU time 0.71 seconds
Started Jul 23 06:44:17 PM PDT 24
Finished Jul 23 06:44:21 PM PDT 24
Peak memory 206716 kb
Host smart-da1c01d9-1ea6-4fde-8907-8c0e2e620eb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37474
83878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.3747483878
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.3280257814
Short name T2132
Test name
Test status
Simulation time 20706765295 ps
CPU time 44.62 seconds
Started Jul 23 06:44:18 PM PDT 24
Finished Jul 23 06:45:07 PM PDT 24
Peak memory 206980 kb
Host smart-c5e21d1a-f975-4061-b254-6951d945e774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32802
57814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.3280257814
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.3142840745
Short name T49
Test name
Test status
Simulation time 169243062 ps
CPU time 0.85 seconds
Started Jul 23 06:44:25 PM PDT 24
Finished Jul 23 06:44:31 PM PDT 24
Peak memory 206756 kb
Host smart-28a231a4-6b64-4764-aa5e-3f46d5831c8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31428
40745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.3142840745
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.4273248753
Short name T816
Test name
Test status
Simulation time 199869447 ps
CPU time 0.86 seconds
Started Jul 23 06:44:17 PM PDT 24
Finished Jul 23 06:44:21 PM PDT 24
Peak memory 206744 kb
Host smart-e3ed59dc-7ccf-4758-9e84-8f78605399e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42732
48753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.4273248753
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.4080334978
Short name T766
Test name
Test status
Simulation time 235310423 ps
CPU time 0.9 seconds
Started Jul 23 06:44:18 PM PDT 24
Finished Jul 23 06:44:23 PM PDT 24
Peak memory 206764 kb
Host smart-4d9fa214-c9ee-4978-a083-370869109358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40803
34978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.4080334978
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.3252883546
Short name T388
Test name
Test status
Simulation time 164092766 ps
CPU time 0.85 seconds
Started Jul 23 06:44:14 PM PDT 24
Finished Jul 23 06:44:16 PM PDT 24
Peak memory 206736 kb
Host smart-c1549d46-8649-4b02-8fe4-aeb17132963b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32528
83546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.3252883546
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.2536411957
Short name T1760
Test name
Test status
Simulation time 209979386 ps
CPU time 0.83 seconds
Started Jul 23 06:44:18 PM PDT 24
Finished Jul 23 06:44:23 PM PDT 24
Peak memory 206716 kb
Host smart-cbdd73e5-f714-44d0-81cf-ce1056a51cf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25364
11957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.2536411957
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.2945266
Short name T1047
Test name
Test status
Simulation time 147828807 ps
CPU time 0.77 seconds
Started Jul 23 06:44:16 PM PDT 24
Finished Jul 23 06:44:18 PM PDT 24
Peak memory 206736 kb
Host smart-a8217817-01e8-405e-8dd4-40d529166125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29452
66 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.2945266
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.2100482900
Short name T1650
Test name
Test status
Simulation time 226200757 ps
CPU time 0.84 seconds
Started Jul 23 06:44:18 PM PDT 24
Finished Jul 23 06:44:23 PM PDT 24
Peak memory 206772 kb
Host smart-5a3c9aa2-c9c6-423f-980f-2e90e07badac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21004
82900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.2100482900
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.2085876194
Short name T770
Test name
Test status
Simulation time 234074829 ps
CPU time 0.99 seconds
Started Jul 23 06:44:19 PM PDT 24
Finished Jul 23 06:44:24 PM PDT 24
Peak memory 206924 kb
Host smart-5020bb2a-1d17-428f-bef2-f6db8825182e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20858
76194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.2085876194
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.1278217520
Short name T451
Test name
Test status
Simulation time 5735204843 ps
CPU time 156.87 seconds
Started Jul 23 06:44:18 PM PDT 24
Finished Jul 23 06:47:00 PM PDT 24
Peak memory 206840 kb
Host smart-1a024038-9ed1-44c8-88ca-9ac8455e5176
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1278217520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.1278217520
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.3085906907
Short name T2302
Test name
Test status
Simulation time 150481362 ps
CPU time 0.82 seconds
Started Jul 23 06:44:15 PM PDT 24
Finished Jul 23 06:44:17 PM PDT 24
Peak memory 206740 kb
Host smart-e75fbc12-4b21-4a32-b12b-ba1783e8717a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30859
06907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.3085906907
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.646769060
Short name T595
Test name
Test status
Simulation time 202210023 ps
CPU time 0.88 seconds
Started Jul 23 06:44:16 PM PDT 24
Finished Jul 23 06:44:18 PM PDT 24
Peak memory 206744 kb
Host smart-597cfc2e-d650-4789-b491-9beefe9a7c2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64676
9060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.646769060
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.1229673766
Short name T1841
Test name
Test status
Simulation time 1299895620 ps
CPU time 2.64 seconds
Started Jul 23 06:44:17 PM PDT 24
Finished Jul 23 06:44:23 PM PDT 24
Peak memory 206896 kb
Host smart-db7e04f4-135a-438c-9b3b-95e15b18874e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12296
73766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.1229673766
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.4281317377
Short name T1575
Test name
Test status
Simulation time 5238082094 ps
CPU time 42.23 seconds
Started Jul 23 06:44:19 PM PDT 24
Finished Jul 23 06:45:06 PM PDT 24
Peak memory 206920 kb
Host smart-07a35804-a149-4192-aca8-f7d74a95cba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42813
17377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.4281317377
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.958284887
Short name T931
Test name
Test status
Simulation time 41823579 ps
CPU time 0.67 seconds
Started Jul 23 06:44:34 PM PDT 24
Finished Jul 23 06:44:40 PM PDT 24
Peak memory 206732 kb
Host smart-b9d5fc19-1f4b-4d49-81c3-4c242583c06e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=958284887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.958284887
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.4032041628
Short name T744
Test name
Test status
Simulation time 4045377518 ps
CPU time 4.85 seconds
Started Jul 23 06:44:17 PM PDT 24
Finished Jul 23 06:44:26 PM PDT 24
Peak memory 206832 kb
Host smart-247d2684-fdbf-4cbe-9823-0e6cd0f7971b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4032041628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.4032041628
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.3605958546
Short name T2620
Test name
Test status
Simulation time 13335867322 ps
CPU time 14.43 seconds
Started Jul 23 06:44:19 PM PDT 24
Finished Jul 23 06:44:38 PM PDT 24
Peak memory 206912 kb
Host smart-f19cf622-9468-4b11-85ec-0b504e76e58a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3605958546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.3605958546
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.3685175509
Short name T2094
Test name
Test status
Simulation time 23353030810 ps
CPU time 26.1 seconds
Started Jul 23 06:44:18 PM PDT 24
Finished Jul 23 06:44:48 PM PDT 24
Peak memory 206760 kb
Host smart-469c8b17-3d81-4880-8c65-66c0142391a0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3685175509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.3685175509
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.2505026521
Short name T2024
Test name
Test status
Simulation time 188310282 ps
CPU time 0.83 seconds
Started Jul 23 06:44:19 PM PDT 24
Finished Jul 23 06:44:24 PM PDT 24
Peak memory 206756 kb
Host smart-8d9c6dce-8b39-4503-850a-641c1e2c13fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25050
26521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.2505026521
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.1320981327
Short name T1247
Test name
Test status
Simulation time 152227289 ps
CPU time 0.8 seconds
Started Jul 23 06:44:20 PM PDT 24
Finished Jul 23 06:44:26 PM PDT 24
Peak memory 206776 kb
Host smart-b5ddad7a-e057-4a29-a098-e9f4fd6dd63a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13209
81327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.1320981327
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.1191683099
Short name T1641
Test name
Test status
Simulation time 224665795 ps
CPU time 0.88 seconds
Started Jul 23 06:44:24 PM PDT 24
Finished Jul 23 06:44:30 PM PDT 24
Peak memory 206752 kb
Host smart-98b223c3-9c5c-4543-8245-e55104404e30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11916
83099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.1191683099
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.3895865110
Short name T659
Test name
Test status
Simulation time 813415001 ps
CPU time 1.74 seconds
Started Jul 23 06:44:19 PM PDT 24
Finished Jul 23 06:44:26 PM PDT 24
Peak memory 206832 kb
Host smart-537269fb-36ca-4eed-9c83-de1b6ecbccfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38958
65110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.3895865110
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.316354001
Short name T1209
Test name
Test status
Simulation time 13641444450 ps
CPU time 27.95 seconds
Started Jul 23 06:44:34 PM PDT 24
Finished Jul 23 06:45:07 PM PDT 24
Peak memory 206952 kb
Host smart-51ff84f4-9400-4318-ad10-90f1d72fd24a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31635
4001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.316354001
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.438390241
Short name T2362
Test name
Test status
Simulation time 409767330 ps
CPU time 1.27 seconds
Started Jul 23 06:44:35 PM PDT 24
Finished Jul 23 06:44:41 PM PDT 24
Peak memory 206748 kb
Host smart-715e35ef-c92e-4f43-a769-02b014e49642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43839
0241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.438390241
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.3930874500
Short name T1674
Test name
Test status
Simulation time 147362065 ps
CPU time 0.71 seconds
Started Jul 23 06:44:16 PM PDT 24
Finished Jul 23 06:44:18 PM PDT 24
Peak memory 206756 kb
Host smart-90255c50-9952-47b0-9e42-38e075c365e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39308
74500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.3930874500
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.3105293190
Short name T1965
Test name
Test status
Simulation time 71481678 ps
CPU time 0.68 seconds
Started Jul 23 06:44:35 PM PDT 24
Finished Jul 23 06:44:42 PM PDT 24
Peak memory 206740 kb
Host smart-8e92fa01-5c63-4c5e-ab40-bb60cd64a1ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31052
93190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.3105293190
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.3342831955
Short name T1675
Test name
Test status
Simulation time 903005761 ps
CPU time 2.04 seconds
Started Jul 23 06:44:20 PM PDT 24
Finished Jul 23 06:44:27 PM PDT 24
Peak memory 206924 kb
Host smart-280fe703-a02a-40a1-a081-d227e25b1abf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33428
31955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.3342831955
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.3135424974
Short name T23
Test name
Test status
Simulation time 289295374 ps
CPU time 1.75 seconds
Started Jul 23 06:44:34 PM PDT 24
Finished Jul 23 06:44:42 PM PDT 24
Peak memory 206888 kb
Host smart-4ee70f3f-7185-4bb6-8464-571fd02f6886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31354
24974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.3135424974
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.3902291315
Short name T524
Test name
Test status
Simulation time 222361573 ps
CPU time 0.89 seconds
Started Jul 23 06:44:18 PM PDT 24
Finished Jul 23 06:44:24 PM PDT 24
Peak memory 206752 kb
Host smart-af504fd9-c85c-49a4-a9e3-bd38065556e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39022
91315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.3902291315
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.3714906997
Short name T2018
Test name
Test status
Simulation time 140880308 ps
CPU time 0.75 seconds
Started Jul 23 06:44:20 PM PDT 24
Finished Jul 23 06:44:26 PM PDT 24
Peak memory 206740 kb
Host smart-45c2fa2a-427a-4154-a732-a42e9124c011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37149
06997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.3714906997
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.2354402446
Short name T2511
Test name
Test status
Simulation time 237349028 ps
CPU time 0.91 seconds
Started Jul 23 06:44:24 PM PDT 24
Finished Jul 23 06:44:30 PM PDT 24
Peak memory 206656 kb
Host smart-b4c98eaa-3058-4f81-aee8-0ecff72c8093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23544
02446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.2354402446
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.87127926
Short name T1424
Test name
Test status
Simulation time 5706557708 ps
CPU time 152.96 seconds
Started Jul 23 06:44:34 PM PDT 24
Finished Jul 23 06:47:12 PM PDT 24
Peak memory 206856 kb
Host smart-a6fac54e-289e-4b98-9642-88d4567b900c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=87127926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.87127926
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/34.usbdev_iso_retraction.3130181141
Short name T1045
Test name
Test status
Simulation time 11821113204 ps
CPU time 41.39 seconds
Started Jul 23 06:44:24 PM PDT 24
Finished Jul 23 06:45:10 PM PDT 24
Peak memory 206944 kb
Host smart-a96a508e-cf17-4d83-ba61-48f2e51587fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31301
81141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_iso_retraction.3130181141
Directory /workspace/34.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.3041728709
Short name T846
Test name
Test status
Simulation time 190758105 ps
CPU time 0.86 seconds
Started Jul 23 06:44:25 PM PDT 24
Finished Jul 23 06:44:31 PM PDT 24
Peak memory 206744 kb
Host smart-62ca83fc-c50e-47c9-8b8c-2ec8e1cb385d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30417
28709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.3041728709
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.1461932146
Short name T2471
Test name
Test status
Simulation time 23373012819 ps
CPU time 27.27 seconds
Started Jul 23 06:44:27 PM PDT 24
Finished Jul 23 06:44:59 PM PDT 24
Peak memory 206836 kb
Host smart-fe71d339-56ca-4c31-afb9-462d38245bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14619
32146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.1461932146
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.1050812437
Short name T2216
Test name
Test status
Simulation time 3328240624 ps
CPU time 4.14 seconds
Started Jul 23 06:44:23 PM PDT 24
Finished Jul 23 06:44:32 PM PDT 24
Peak memory 206784 kb
Host smart-e479901f-0f02-43d8-beb0-8e5d954169a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10508
12437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.1050812437
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.2242849973
Short name T2528
Test name
Test status
Simulation time 8475218852 ps
CPU time 80.09 seconds
Started Jul 23 06:44:28 PM PDT 24
Finished Jul 23 06:45:53 PM PDT 24
Peak memory 206972 kb
Host smart-10f1f313-3d23-4d8e-bf86-f2ae4b37dc4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22428
49973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.2242849973
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.2211480440
Short name T724
Test name
Test status
Simulation time 3974157202 ps
CPU time 115.27 seconds
Started Jul 23 06:44:23 PM PDT 24
Finished Jul 23 06:46:23 PM PDT 24
Peak memory 206900 kb
Host smart-677367a0-aaa2-41f6-9fdd-0388a64b37d8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2211480440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.2211480440
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.2050863942
Short name T2106
Test name
Test status
Simulation time 254655153 ps
CPU time 0.95 seconds
Started Jul 23 06:44:27 PM PDT 24
Finished Jul 23 06:44:33 PM PDT 24
Peak memory 206748 kb
Host smart-4ffa5f9f-e7de-4dbc-8f24-00868ddb4c55
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2050863942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.2050863942
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.2423453829
Short name T1475
Test name
Test status
Simulation time 192877097 ps
CPU time 0.86 seconds
Started Jul 23 06:44:27 PM PDT 24
Finished Jul 23 06:44:33 PM PDT 24
Peak memory 206744 kb
Host smart-9b1fa03f-46bf-46c9-b230-144bd5fba111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24234
53829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.2423453829
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.3701716839
Short name T910
Test name
Test status
Simulation time 3387671534 ps
CPU time 23.93 seconds
Started Jul 23 06:44:27 PM PDT 24
Finished Jul 23 06:44:56 PM PDT 24
Peak memory 206960 kb
Host smart-ecf7380f-96c4-4115-8a73-3bdf4686a998
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37017
16839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.3701716839
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.3896156142
Short name T157
Test name
Test status
Simulation time 3501587639 ps
CPU time 24.51 seconds
Started Jul 23 06:44:24 PM PDT 24
Finished Jul 23 06:44:53 PM PDT 24
Peak memory 206928 kb
Host smart-16f5cd36-cafc-4091-ad78-45f5b4409042
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3896156142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.3896156142
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.1521967319
Short name T2632
Test name
Test status
Simulation time 165341277 ps
CPU time 0.8 seconds
Started Jul 23 06:44:27 PM PDT 24
Finished Jul 23 06:44:32 PM PDT 24
Peak memory 206696 kb
Host smart-a6ec598f-8641-4370-a552-219cbcf87aa6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1521967319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.1521967319
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.4004095817
Short name T1014
Test name
Test status
Simulation time 155988138 ps
CPU time 0.76 seconds
Started Jul 23 06:44:27 PM PDT 24
Finished Jul 23 06:44:33 PM PDT 24
Peak memory 206724 kb
Host smart-0f4fb5a1-193c-4062-9c38-f10d3b170ea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40040
95817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.4004095817
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.823993243
Short name T146
Test name
Test status
Simulation time 182813790 ps
CPU time 0.88 seconds
Started Jul 23 06:44:28 PM PDT 24
Finished Jul 23 06:44:33 PM PDT 24
Peak memory 206764 kb
Host smart-443864b2-878b-4fba-b1b5-5a436bcdf80e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82399
3243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.823993243
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.4243998839
Short name T1111
Test name
Test status
Simulation time 194379153 ps
CPU time 0.85 seconds
Started Jul 23 06:44:29 PM PDT 24
Finished Jul 23 06:44:34 PM PDT 24
Peak memory 206760 kb
Host smart-e6873a3d-843b-469e-a442-1b14e3419760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42439
98839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.4243998839
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.276702308
Short name T2466
Test name
Test status
Simulation time 190445951 ps
CPU time 0.8 seconds
Started Jul 23 06:44:29 PM PDT 24
Finished Jul 23 06:44:34 PM PDT 24
Peak memory 206776 kb
Host smart-942330e8-4f2b-40a4-854b-fde4ad69bc3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27670
2308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.276702308
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.1701986996
Short name T1762
Test name
Test status
Simulation time 264771369 ps
CPU time 0.85 seconds
Started Jul 23 06:44:33 PM PDT 24
Finished Jul 23 06:44:39 PM PDT 24
Peak memory 206744 kb
Host smart-3b510abd-d130-4581-89e4-1fe0b903b0aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17019
86996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.1701986996
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.3638374431
Short name T908
Test name
Test status
Simulation time 152237142 ps
CPU time 0.78 seconds
Started Jul 23 06:44:35 PM PDT 24
Finished Jul 23 06:44:41 PM PDT 24
Peak memory 206756 kb
Host smart-f56058fb-7c51-496e-8573-f034877411f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36383
74431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.3638374431
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.4092934984
Short name T2193
Test name
Test status
Simulation time 194718855 ps
CPU time 0.9 seconds
Started Jul 23 06:44:33 PM PDT 24
Finished Jul 23 06:44:39 PM PDT 24
Peak memory 206784 kb
Host smart-8c0e4708-a7a9-48ff-9ebe-58456c19332f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4092934984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.4092934984
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.3803977304
Short name T186
Test name
Test status
Simulation time 158808618 ps
CPU time 0.76 seconds
Started Jul 23 06:44:33 PM PDT 24
Finished Jul 23 06:44:39 PM PDT 24
Peak memory 206588 kb
Host smart-9a11496f-7e7c-482a-8768-ab364368a508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38039
77304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.3803977304
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.2954441052
Short name T686
Test name
Test status
Simulation time 37835717 ps
CPU time 0.67 seconds
Started Jul 23 06:44:30 PM PDT 24
Finished Jul 23 06:44:35 PM PDT 24
Peak memory 206664 kb
Host smart-ba506e0a-1298-40e7-87c9-e94a40b7f6bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29544
41052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.2954441052
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.2039494834
Short name T247
Test name
Test status
Simulation time 19629526231 ps
CPU time 48.84 seconds
Started Jul 23 06:44:31 PM PDT 24
Finished Jul 23 06:45:24 PM PDT 24
Peak memory 206988 kb
Host smart-b1add65b-52fc-4aff-a32f-932c2cd90c67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20394
94834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.2039494834
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.1882399284
Short name T2165
Test name
Test status
Simulation time 225088929 ps
CPU time 0.85 seconds
Started Jul 23 06:44:39 PM PDT 24
Finished Jul 23 06:44:46 PM PDT 24
Peak memory 206752 kb
Host smart-32db36d3-f66d-4a29-83e2-414604fe3dfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18823
99284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.1882399284
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.1714505976
Short name T2182
Test name
Test status
Simulation time 273143222 ps
CPU time 0.92 seconds
Started Jul 23 06:44:32 PM PDT 24
Finished Jul 23 06:44:37 PM PDT 24
Peak memory 206764 kb
Host smart-54725cf1-cfa4-4061-9cfc-0aebab774d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17145
05976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.1714505976
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.3049611519
Short name T1358
Test name
Test status
Simulation time 172614274 ps
CPU time 0.83 seconds
Started Jul 23 06:44:32 PM PDT 24
Finished Jul 23 06:44:37 PM PDT 24
Peak memory 206768 kb
Host smart-b60174a3-611c-46ee-ae72-ee98edce540a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30496
11519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.3049611519
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.126194115
Short name T1900
Test name
Test status
Simulation time 190492577 ps
CPU time 0.91 seconds
Started Jul 23 06:44:36 PM PDT 24
Finished Jul 23 06:44:43 PM PDT 24
Peak memory 206772 kb
Host smart-e60e7107-b34d-4695-b29b-6de93150b756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12619
4115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.126194115
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.3281308103
Short name T2733
Test name
Test status
Simulation time 153168573 ps
CPU time 0.77 seconds
Started Jul 23 06:44:33 PM PDT 24
Finished Jul 23 06:44:39 PM PDT 24
Peak memory 206752 kb
Host smart-dd524fe2-1f5d-4d3c-9a32-ada35cbbfb77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32813
08103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.3281308103
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.1583222474
Short name T1584
Test name
Test status
Simulation time 155858891 ps
CPU time 0.74 seconds
Started Jul 23 06:44:34 PM PDT 24
Finished Jul 23 06:44:40 PM PDT 24
Peak memory 206756 kb
Host smart-ab264848-dd97-450e-b4e4-9c04da1dd9ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15832
22474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.1583222474
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.1078152920
Short name T1160
Test name
Test status
Simulation time 167475924 ps
CPU time 0.81 seconds
Started Jul 23 06:44:35 PM PDT 24
Finished Jul 23 06:44:41 PM PDT 24
Peak memory 206756 kb
Host smart-2ef246c6-a1ae-40d8-b698-38c1845dbff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10781
52920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.1078152920
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.3008632656
Short name T2498
Test name
Test status
Simulation time 222058950 ps
CPU time 0.87 seconds
Started Jul 23 06:44:35 PM PDT 24
Finished Jul 23 06:44:42 PM PDT 24
Peak memory 206748 kb
Host smart-fc71c8b2-5c30-4bff-88bc-b291a9d2b40c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30086
32656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.3008632656
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.1795766838
Short name T1506
Test name
Test status
Simulation time 5376248814 ps
CPU time 149.55 seconds
Started Jul 23 06:44:33 PM PDT 24
Finished Jul 23 06:47:07 PM PDT 24
Peak memory 206916 kb
Host smart-fe02f9f6-650b-4705-9d9b-9ed84eed2b50
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1795766838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.1795766838
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.2142436236
Short name T604
Test name
Test status
Simulation time 229595518 ps
CPU time 0.95 seconds
Started Jul 23 06:44:30 PM PDT 24
Finished Jul 23 06:44:35 PM PDT 24
Peak memory 206776 kb
Host smart-dd2af43d-78a6-4581-8f19-327f97dbf0b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21424
36236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.2142436236
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.545057555
Short name T1476
Test name
Test status
Simulation time 170711979 ps
CPU time 0.84 seconds
Started Jul 23 06:44:33 PM PDT 24
Finished Jul 23 06:44:38 PM PDT 24
Peak memory 206752 kb
Host smart-c5cc3dcc-3b77-422c-884e-997e67a36e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54505
7555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.545057555
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.4238925873
Short name T1888
Test name
Test status
Simulation time 936178534 ps
CPU time 2.11 seconds
Started Jul 23 06:44:32 PM PDT 24
Finished Jul 23 06:44:38 PM PDT 24
Peak memory 206888 kb
Host smart-0c293c86-9679-4fbe-86f5-87bc32670cc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42389
25873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.4238925873
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.4129632507
Short name T1328
Test name
Test status
Simulation time 5566537264 ps
CPU time 53.72 seconds
Started Jul 23 06:44:35 PM PDT 24
Finished Jul 23 06:45:35 PM PDT 24
Peak memory 206924 kb
Host smart-131447e7-31de-4483-9639-d7fb46daff95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41296
32507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.4129632507
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.937970489
Short name T1932
Test name
Test status
Simulation time 35425646 ps
CPU time 0.67 seconds
Started Jul 23 06:44:46 PM PDT 24
Finished Jul 23 06:44:52 PM PDT 24
Peak memory 206724 kb
Host smart-d0d5fde3-d464-4fc3-b599-de07ce37fa1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=937970489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.937970489
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.1997761853
Short name T200
Test name
Test status
Simulation time 3776977299 ps
CPU time 4.4 seconds
Started Jul 23 06:44:33 PM PDT 24
Finished Jul 23 06:44:42 PM PDT 24
Peak memory 206824 kb
Host smart-3aa35909-cac8-4101-905c-ddfa850aa2cb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1997761853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.1997761853
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.364146703
Short name T2483
Test name
Test status
Simulation time 13321552828 ps
CPU time 12.54 seconds
Started Jul 23 06:44:33 PM PDT 24
Finished Jul 23 06:44:50 PM PDT 24
Peak memory 206788 kb
Host smart-6be110cd-c2e5-4607-afd2-e612e9e5d8c2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=364146703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.364146703
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.526744442
Short name T1255
Test name
Test status
Simulation time 23381539480 ps
CPU time 24.21 seconds
Started Jul 23 06:44:39 PM PDT 24
Finished Jul 23 06:45:09 PM PDT 24
Peak memory 206820 kb
Host smart-a753fd5c-ca72-4b79-88a5-33fc38f91ad9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=526744442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.526744442
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.2592962610
Short name T872
Test name
Test status
Simulation time 164210876 ps
CPU time 0.83 seconds
Started Jul 23 06:44:33 PM PDT 24
Finished Jul 23 06:44:39 PM PDT 24
Peak memory 206772 kb
Host smart-54f9f9e9-1162-4ec5-be05-c5451c719581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25929
62610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.2592962610
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.2977615594
Short name T2255
Test name
Test status
Simulation time 166779292 ps
CPU time 0.78 seconds
Started Jul 23 06:44:33 PM PDT 24
Finished Jul 23 06:44:39 PM PDT 24
Peak memory 206600 kb
Host smart-ed480acf-2f15-41ec-8435-aeb6689bcf17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29776
15594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.2977615594
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.3356092881
Short name T1756
Test name
Test status
Simulation time 243537354 ps
CPU time 0.96 seconds
Started Jul 23 06:44:36 PM PDT 24
Finished Jul 23 06:44:43 PM PDT 24
Peak memory 206736 kb
Host smart-00b48100-42b9-4875-8b3e-f40820f0c29b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33560
92881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.3356092881
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.4195406044
Short name T2234
Test name
Test status
Simulation time 1553684815 ps
CPU time 3.58 seconds
Started Jul 23 06:44:47 PM PDT 24
Finished Jul 23 06:44:56 PM PDT 24
Peak memory 206844 kb
Host smart-8dceeaa8-724e-4626-87aa-81d7eed42232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41954
06044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.4195406044
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.482326648
Short name T1123
Test name
Test status
Simulation time 7148724728 ps
CPU time 13.73 seconds
Started Jul 23 06:44:38 PM PDT 24
Finished Jul 23 06:44:58 PM PDT 24
Peak memory 206952 kb
Host smart-c2d0a695-9220-4072-aafb-47b51eed1aa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48232
6648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.482326648
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.3967506368
Short name T370
Test name
Test status
Simulation time 367193662 ps
CPU time 1.19 seconds
Started Jul 23 06:44:39 PM PDT 24
Finished Jul 23 06:44:46 PM PDT 24
Peak memory 206740 kb
Host smart-c801aa92-8691-4f89-966a-d53893fac175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39675
06368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.3967506368
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.401922169
Short name T1670
Test name
Test status
Simulation time 141440603 ps
CPU time 0.76 seconds
Started Jul 23 06:44:37 PM PDT 24
Finished Jul 23 06:44:43 PM PDT 24
Peak memory 206740 kb
Host smart-35bec413-950e-4357-993a-ce74d361353c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40192
2169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.401922169
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.3564806190
Short name T642
Test name
Test status
Simulation time 41019391 ps
CPU time 0.68 seconds
Started Jul 23 06:44:35 PM PDT 24
Finished Jul 23 06:44:42 PM PDT 24
Peak memory 206764 kb
Host smart-e093f049-fb1c-437a-b117-bfb4b68c466e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35648
06190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.3564806190
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.3230812081
Short name T2703
Test name
Test status
Simulation time 1024121973 ps
CPU time 2.26 seconds
Started Jul 23 06:44:39 PM PDT 24
Finished Jul 23 06:44:47 PM PDT 24
Peak memory 206840 kb
Host smart-3ffada2d-1115-4f63-aa99-316ee1594d13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32308
12081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.3230812081
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.638844047
Short name T696
Test name
Test status
Simulation time 344719569 ps
CPU time 2.34 seconds
Started Jul 23 06:44:38 PM PDT 24
Finished Jul 23 06:44:47 PM PDT 24
Peak memory 206912 kb
Host smart-1360ec5c-a306-40c4-bb73-15b279415f9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63884
4047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.638844047
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.3651518693
Short name T1050
Test name
Test status
Simulation time 196874243 ps
CPU time 0.88 seconds
Started Jul 23 06:44:36 PM PDT 24
Finished Jul 23 06:44:43 PM PDT 24
Peak memory 206744 kb
Host smart-a93a9154-cb7a-42dd-ac61-9a7f47f85994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36515
18693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.3651518693
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.2395085476
Short name T767
Test name
Test status
Simulation time 171814701 ps
CPU time 0.76 seconds
Started Jul 23 06:44:41 PM PDT 24
Finished Jul 23 06:44:48 PM PDT 24
Peak memory 206728 kb
Host smart-bfbe643f-87cc-42ca-9e04-fb7e18cf064a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23950
85476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.2395085476
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.773860303
Short name T506
Test name
Test status
Simulation time 194045150 ps
CPU time 0.84 seconds
Started Jul 23 06:44:39 PM PDT 24
Finished Jul 23 06:44:46 PM PDT 24
Peak memory 206752 kb
Host smart-30787f99-987f-441e-b7f8-46f9b087a5a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77386
0303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.773860303
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.2295042849
Short name T1009
Test name
Test status
Simulation time 8743033957 ps
CPU time 82.74 seconds
Started Jul 23 06:44:39 PM PDT 24
Finished Jul 23 06:46:08 PM PDT 24
Peak memory 206972 kb
Host smart-31e41ceb-de14-4cee-bddc-191aadc56175
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2295042849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.2295042849
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.4207462598
Short name T1489
Test name
Test status
Simulation time 245443297 ps
CPU time 0.9 seconds
Started Jul 23 06:44:39 PM PDT 24
Finished Jul 23 06:44:46 PM PDT 24
Peak memory 206764 kb
Host smart-1c202348-a034-4442-a572-fd56765d20df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42074
62598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.4207462598
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.1110958837
Short name T2600
Test name
Test status
Simulation time 23281943117 ps
CPU time 27.11 seconds
Started Jul 23 06:44:38 PM PDT 24
Finished Jul 23 06:45:11 PM PDT 24
Peak memory 206816 kb
Host smart-d3db0bf7-2bba-4410-bed2-9bca72efdbbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11109
58837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.1110958837
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.3084558553
Short name T1962
Test name
Test status
Simulation time 3333478101 ps
CPU time 3.76 seconds
Started Jul 23 06:44:35 PM PDT 24
Finished Jul 23 06:44:44 PM PDT 24
Peak memory 206824 kb
Host smart-3315b439-1ca8-4d48-8d69-d26a75cce8d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30845
58553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.3084558553
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.2990563453
Short name T782
Test name
Test status
Simulation time 11772939951 ps
CPU time 319.79 seconds
Started Jul 23 06:44:48 PM PDT 24
Finished Jul 23 06:50:14 PM PDT 24
Peak memory 206984 kb
Host smart-4e524cea-a448-4c58-9d6c-e25ac39dd041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29905
63453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.2990563453
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.3734950969
Short name T676
Test name
Test status
Simulation time 3334224921 ps
CPU time 23.41 seconds
Started Jul 23 06:44:41 PM PDT 24
Finished Jul 23 06:45:10 PM PDT 24
Peak memory 206924 kb
Host smart-2a6c59b5-fb11-42b2-9289-8fab50d431e5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3734950969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.3734950969
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.2208866518
Short name T545
Test name
Test status
Simulation time 252192602 ps
CPU time 0.95 seconds
Started Jul 23 06:44:39 PM PDT 24
Finished Jul 23 06:44:46 PM PDT 24
Peak memory 206732 kb
Host smart-cde19009-bee8-49e6-bd50-9bb3deca7471
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2208866518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.2208866518
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.2800065113
Short name T1308
Test name
Test status
Simulation time 258427146 ps
CPU time 0.94 seconds
Started Jul 23 06:44:36 PM PDT 24
Finished Jul 23 06:44:43 PM PDT 24
Peak memory 206716 kb
Host smart-1c0358c5-9fac-497d-8d55-ce57f3eeb365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28000
65113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.2800065113
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.2238768586
Short name T2650
Test name
Test status
Simulation time 4817767932 ps
CPU time 32.68 seconds
Started Jul 23 06:44:36 PM PDT 24
Finished Jul 23 06:45:14 PM PDT 24
Peak memory 206848 kb
Host smart-c403708a-0cdd-4a1f-8005-3c24ef889cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22387
68586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.2238768586
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.1228400685
Short name T747
Test name
Test status
Simulation time 4719780274 ps
CPU time 44.59 seconds
Started Jul 23 06:44:38 PM PDT 24
Finished Jul 23 06:45:29 PM PDT 24
Peak memory 206904 kb
Host smart-aad604d0-cd4b-4253-ab34-a8df946caae9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1228400685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.1228400685
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.651579166
Short name T1142
Test name
Test status
Simulation time 151357179 ps
CPU time 0.78 seconds
Started Jul 23 06:44:38 PM PDT 24
Finished Jul 23 06:44:44 PM PDT 24
Peak memory 206728 kb
Host smart-a7e9422f-66e9-4935-ba02-6d56160bbafc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=651579166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.651579166
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.3966849981
Short name T1080
Test name
Test status
Simulation time 149293158 ps
CPU time 0.82 seconds
Started Jul 23 06:44:48 PM PDT 24
Finished Jul 23 06:44:55 PM PDT 24
Peak memory 206768 kb
Host smart-c4f9f446-d003-4543-9527-2a51cf6f60ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39668
49981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.3966849981
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.3692924444
Short name T131
Test name
Test status
Simulation time 213695713 ps
CPU time 0.87 seconds
Started Jul 23 06:44:37 PM PDT 24
Finished Jul 23 06:44:44 PM PDT 24
Peak memory 206772 kb
Host smart-d999c86c-0a41-4539-9cf8-cefeddd8d039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36929
24444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.3692924444
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.211497483
Short name T2593
Test name
Test status
Simulation time 186282740 ps
CPU time 0.85 seconds
Started Jul 23 06:44:38 PM PDT 24
Finished Jul 23 06:44:45 PM PDT 24
Peak memory 206768 kb
Host smart-391965c5-1d95-45d0-804b-797a9965f494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21149
7483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.211497483
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.2083249352
Short name T1547
Test name
Test status
Simulation time 178619412 ps
CPU time 0.8 seconds
Started Jul 23 06:44:47 PM PDT 24
Finished Jul 23 06:44:53 PM PDT 24
Peak memory 206784 kb
Host smart-f9a6988c-fa61-4ea7-a0ba-c0501f91cf83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20832
49352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.2083249352
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.2321732864
Short name T1445
Test name
Test status
Simulation time 196502261 ps
CPU time 0.9 seconds
Started Jul 23 06:44:48 PM PDT 24
Finished Jul 23 06:44:56 PM PDT 24
Peak memory 206744 kb
Host smart-3fb389be-7e94-4060-8d60-7a862d7b4b40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23217
32864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.2321732864
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.2532575562
Short name T153
Test name
Test status
Simulation time 161001372 ps
CPU time 0.79 seconds
Started Jul 23 06:44:49 PM PDT 24
Finished Jul 23 06:44:57 PM PDT 24
Peak memory 206772 kb
Host smart-6199da53-7dfd-4e8a-a80b-dac3d4be57b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25325
75562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.2532575562
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.3175008789
Short name T2347
Test name
Test status
Simulation time 197055172 ps
CPU time 0.89 seconds
Started Jul 23 06:44:47 PM PDT 24
Finished Jul 23 06:44:53 PM PDT 24
Peak memory 206684 kb
Host smart-512c7eac-fb5e-4e56-b2da-a40798b47339
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3175008789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.3175008789
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.620461532
Short name T2597
Test name
Test status
Simulation time 196248432 ps
CPU time 0.79 seconds
Started Jul 23 06:44:47 PM PDT 24
Finished Jul 23 06:44:53 PM PDT 24
Peak memory 206768 kb
Host smart-36d02ab5-5b77-41bc-9301-e3a6f7774f4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62046
1532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.620461532
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.563839713
Short name T32
Test name
Test status
Simulation time 44879652 ps
CPU time 0.65 seconds
Started Jul 23 06:44:45 PM PDT 24
Finished Jul 23 06:44:51 PM PDT 24
Peak memory 206744 kb
Host smart-98e615d1-082b-470c-9982-254b7ba8f54c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56383
9713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.563839713
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.2808678875
Short name T1126
Test name
Test status
Simulation time 14025807081 ps
CPU time 31.29 seconds
Started Jul 23 06:44:46 PM PDT 24
Finished Jul 23 06:45:23 PM PDT 24
Peak memory 207012 kb
Host smart-a5fac33b-a37d-41f6-ac6f-9463379dc01d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28086
78875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.2808678875
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.3371143969
Short name T616
Test name
Test status
Simulation time 193303881 ps
CPU time 0.93 seconds
Started Jul 23 06:44:47 PM PDT 24
Finished Jul 23 06:44:55 PM PDT 24
Peak memory 206748 kb
Host smart-49f99284-9cc7-421b-a50e-bb50991b7b7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33711
43969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.3371143969
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.757794803
Short name T2609
Test name
Test status
Simulation time 182411342 ps
CPU time 0.84 seconds
Started Jul 23 06:44:49 PM PDT 24
Finished Jul 23 06:44:57 PM PDT 24
Peak memory 206688 kb
Host smart-004f5515-4994-4f2c-8267-48787197def5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75779
4803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.757794803
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.1738355765
Short name T1751
Test name
Test status
Simulation time 262397427 ps
CPU time 0.95 seconds
Started Jul 23 06:44:46 PM PDT 24
Finished Jul 23 06:44:52 PM PDT 24
Peak memory 206676 kb
Host smart-057df1df-28a8-4fca-9ad1-0161ae8aa360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17383
55765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.1738355765
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.1834821863
Short name T2435
Test name
Test status
Simulation time 223695389 ps
CPU time 0.92 seconds
Started Jul 23 06:44:49 PM PDT 24
Finished Jul 23 06:44:57 PM PDT 24
Peak memory 206768 kb
Host smart-51689479-5b63-4294-a4fe-5e5891a631cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18348
21863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.1834821863
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.4000569614
Short name T1159
Test name
Test status
Simulation time 166958839 ps
CPU time 0.79 seconds
Started Jul 23 06:44:45 PM PDT 24
Finished Jul 23 06:44:51 PM PDT 24
Peak memory 206780 kb
Host smart-08f6e5e2-1070-4555-94ab-a3bcbd35d76a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40005
69614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.4000569614
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.1191560737
Short name T2034
Test name
Test status
Simulation time 170456295 ps
CPU time 0.77 seconds
Started Jul 23 06:44:47 PM PDT 24
Finished Jul 23 06:44:53 PM PDT 24
Peak memory 206752 kb
Host smart-68aacb30-9ef5-42e6-bcb4-e140e126a73d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11915
60737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.1191560737
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.1733836139
Short name T503
Test name
Test status
Simulation time 163717489 ps
CPU time 0.82 seconds
Started Jul 23 06:44:46 PM PDT 24
Finished Jul 23 06:44:52 PM PDT 24
Peak memory 206740 kb
Host smart-ac4d09ff-3d47-4fc8-8250-d652131ae35e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17338
36139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.1733836139
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.782610057
Short name T714
Test name
Test status
Simulation time 242817190 ps
CPU time 1 seconds
Started Jul 23 06:44:51 PM PDT 24
Finished Jul 23 06:44:58 PM PDT 24
Peak memory 206768 kb
Host smart-b21aac42-0bfa-49a2-b54f-64f6319484ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78261
0057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.782610057
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.4143339402
Short name T2509
Test name
Test status
Simulation time 5170969327 ps
CPU time 145.39 seconds
Started Jul 23 06:44:46 PM PDT 24
Finished Jul 23 06:47:17 PM PDT 24
Peak memory 206832 kb
Host smart-0a13786f-5775-4854-b0c9-1ea1c5daff31
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4143339402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.4143339402
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.3682140526
Short name T1536
Test name
Test status
Simulation time 147694666 ps
CPU time 0.78 seconds
Started Jul 23 06:44:47 PM PDT 24
Finished Jul 23 06:44:54 PM PDT 24
Peak memory 206736 kb
Host smart-c3518143-f7ae-4d49-bf43-7d73ecda1a13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36821
40526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.3682140526
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.2830724615
Short name T860
Test name
Test status
Simulation time 179551949 ps
CPU time 0.8 seconds
Started Jul 23 06:44:46 PM PDT 24
Finished Jul 23 06:44:52 PM PDT 24
Peak memory 206744 kb
Host smart-88d5e24f-6bb4-45cc-909b-5122e68b2b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28307
24615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.2830724615
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.1990762895
Short name T1784
Test name
Test status
Simulation time 748268890 ps
CPU time 1.83 seconds
Started Jul 23 06:44:50 PM PDT 24
Finished Jul 23 06:44:58 PM PDT 24
Peak memory 207076 kb
Host smart-155c62f3-b6b3-42ba-b9f1-5e2949b0db5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19907
62895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.1990762895
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.1197091396
Short name T2231
Test name
Test status
Simulation time 7070213457 ps
CPU time 195.47 seconds
Started Jul 23 06:44:47 PM PDT 24
Finished Jul 23 06:48:08 PM PDT 24
Peak memory 206912 kb
Host smart-e6bf3226-0824-4f0e-8555-ca2f8436ca73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11970
91396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.1197091396
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.795816799
Short name T1811
Test name
Test status
Simulation time 46696151 ps
CPU time 0.7 seconds
Started Jul 23 06:45:06 PM PDT 24
Finished Jul 23 06:45:12 PM PDT 24
Peak memory 206724 kb
Host smart-13726e55-9991-4a21-b135-d42ec8d23f38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=795816799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.795816799
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.2965767682
Short name T2031
Test name
Test status
Simulation time 3770712471 ps
CPU time 4.38 seconds
Started Jul 23 06:44:55 PM PDT 24
Finished Jul 23 06:45:05 PM PDT 24
Peak memory 206988 kb
Host smart-6e4995c7-07b3-40a5-b650-fae2d522dcb2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2965767682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.2965767682
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.2385923566
Short name T717
Test name
Test status
Simulation time 13379560927 ps
CPU time 12.04 seconds
Started Jul 23 06:44:56 PM PDT 24
Finished Jul 23 06:45:14 PM PDT 24
Peak memory 206992 kb
Host smart-311f4990-6599-411f-8537-79f0ba2e7d45
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2385923566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.2385923566
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.3357012122
Short name T2060
Test name
Test status
Simulation time 192677854 ps
CPU time 0.86 seconds
Started Jul 23 06:44:55 PM PDT 24
Finished Jul 23 06:45:02 PM PDT 24
Peak memory 206760 kb
Host smart-fcfe8d0b-4baa-44cd-8fd4-13d562e23c84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33570
12122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.3357012122
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.1014432556
Short name T2375
Test name
Test status
Simulation time 189057959 ps
CPU time 0.87 seconds
Started Jul 23 06:44:53 PM PDT 24
Finished Jul 23 06:45:00 PM PDT 24
Peak memory 206712 kb
Host smart-cb7cd126-0cc7-4463-bbca-f6613e042d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10144
32556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.1014432556
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.3326897760
Short name T114
Test name
Test status
Simulation time 310669259 ps
CPU time 1.09 seconds
Started Jul 23 06:44:53 PM PDT 24
Finished Jul 23 06:45:00 PM PDT 24
Peak memory 206636 kb
Host smart-8834c06c-6d4a-495b-9e16-dc3f98000932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33268
97760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.3326897760
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.3001984276
Short name T1973
Test name
Test status
Simulation time 941694506 ps
CPU time 2.11 seconds
Started Jul 23 06:44:55 PM PDT 24
Finished Jul 23 06:45:02 PM PDT 24
Peak memory 206848 kb
Host smart-3f68829d-569c-473d-8204-cad51d793777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30019
84276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.3001984276
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.2248082014
Short name T613
Test name
Test status
Simulation time 22463623383 ps
CPU time 42.54 seconds
Started Jul 23 06:44:53 PM PDT 24
Finished Jul 23 06:45:41 PM PDT 24
Peak memory 206936 kb
Host smart-6f619007-f20f-414c-88d6-7467e04b3ed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22480
82014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.2248082014
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.3106792575
Short name T494
Test name
Test status
Simulation time 459838070 ps
CPU time 1.5 seconds
Started Jul 23 06:44:56 PM PDT 24
Finished Jul 23 06:45:04 PM PDT 24
Peak memory 206756 kb
Host smart-790e38d3-8d1f-4d86-b801-98a3b3d6aaeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31067
92575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.3106792575
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.2605699558
Short name T2263
Test name
Test status
Simulation time 144177155 ps
CPU time 0.76 seconds
Started Jul 23 06:44:53 PM PDT 24
Finished Jul 23 06:45:00 PM PDT 24
Peak memory 206932 kb
Host smart-ed070479-88d2-4257-b37b-65c420e27296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26056
99558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.2605699558
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.1156818260
Short name T408
Test name
Test status
Simulation time 49864126 ps
CPU time 0.66 seconds
Started Jul 23 06:44:55 PM PDT 24
Finished Jul 23 06:45:01 PM PDT 24
Peak memory 206756 kb
Host smart-9a063137-a187-4607-b8bb-0ee32979871a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11568
18260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.1156818260
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.453208913
Short name T2589
Test name
Test status
Simulation time 971306514 ps
CPU time 2.21 seconds
Started Jul 23 06:44:55 PM PDT 24
Finished Jul 23 06:45:03 PM PDT 24
Peak memory 206924 kb
Host smart-036d6cd9-7e18-4292-b047-0b49dab5c0de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45320
8913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.453208913
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.258961415
Short name T682
Test name
Test status
Simulation time 254279470 ps
CPU time 1.83 seconds
Started Jul 23 06:44:58 PM PDT 24
Finished Jul 23 06:45:05 PM PDT 24
Peak memory 206916 kb
Host smart-1d6ae0ee-80c3-4a95-bd35-af2131c2ad78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25896
1415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.258961415
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.2253565674
Short name T1181
Test name
Test status
Simulation time 157279506 ps
CPU time 0.81 seconds
Started Jul 23 06:44:53 PM PDT 24
Finished Jul 23 06:45:00 PM PDT 24
Peak memory 206752 kb
Host smart-5feb683c-eff8-4c15-8279-b7a00956d935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22535
65674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.2253565674
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.4014396202
Short name T2411
Test name
Test status
Simulation time 160918358 ps
CPU time 0.81 seconds
Started Jul 23 06:44:57 PM PDT 24
Finished Jul 23 06:45:03 PM PDT 24
Peak memory 206764 kb
Host smart-d60be184-7f31-48a3-9194-1374cac265a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40143
96202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.4014396202
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.756419479
Short name T900
Test name
Test status
Simulation time 200108319 ps
CPU time 0.85 seconds
Started Jul 23 06:44:58 PM PDT 24
Finished Jul 23 06:45:05 PM PDT 24
Peak memory 206756 kb
Host smart-a16009d4-90ad-45a2-a421-622a01320694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75641
9479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.756419479
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_iso_retraction.2538899771
Short name T1163
Test name
Test status
Simulation time 3899378295 ps
CPU time 14.95 seconds
Started Jul 23 06:44:53 PM PDT 24
Finished Jul 23 06:45:14 PM PDT 24
Peak memory 206956 kb
Host smart-cc8a3928-2874-4da4-95a0-3ed2fe288322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25388
99771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_iso_retraction.2538899771
Directory /workspace/36.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.1209418934
Short name T1507
Test name
Test status
Simulation time 239251998 ps
CPU time 0.9 seconds
Started Jul 23 06:44:54 PM PDT 24
Finished Jul 23 06:45:00 PM PDT 24
Peak memory 206756 kb
Host smart-e1009b00-d8d4-4bbb-a174-7c5f8dd6f9e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12094
18934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.1209418934
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.1078565961
Short name T2622
Test name
Test status
Simulation time 23319473560 ps
CPU time 21.37 seconds
Started Jul 23 06:44:53 PM PDT 24
Finished Jul 23 06:45:20 PM PDT 24
Peak memory 206780 kb
Host smart-249890db-a196-4649-b3ac-f2bdd8d69033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10785
65961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.1078565961
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.1683915787
Short name T1267
Test name
Test status
Simulation time 3292914629 ps
CPU time 3.91 seconds
Started Jul 23 06:44:55 PM PDT 24
Finished Jul 23 06:45:04 PM PDT 24
Peak memory 206812 kb
Host smart-f47fa9ac-883a-4ee3-a949-316e6186c4ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16839
15787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.1683915787
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.1022010726
Short name T2386
Test name
Test status
Simulation time 4783710473 ps
CPU time 34.34 seconds
Started Jul 23 06:44:58 PM PDT 24
Finished Jul 23 06:45:38 PM PDT 24
Peak memory 206900 kb
Host smart-0593b9d0-73e0-48b8-914f-9cfc3784b512
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1022010726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.1022010726
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.620179831
Short name T293
Test name
Test status
Simulation time 250174892 ps
CPU time 1 seconds
Started Jul 23 06:45:02 PM PDT 24
Finished Jul 23 06:45:09 PM PDT 24
Peak memory 206760 kb
Host smart-2bb14475-975c-4d41-9a80-600115e481b6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=620179831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.620179831
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.1106767665
Short name T1794
Test name
Test status
Simulation time 189996428 ps
CPU time 0.96 seconds
Started Jul 23 06:45:05 PM PDT 24
Finished Jul 23 06:45:11 PM PDT 24
Peak memory 206728 kb
Host smart-a15f1379-3ed0-4e16-b51a-9c2c5ceae9dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11067
67665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.1106767665
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.4160534271
Short name T1388
Test name
Test status
Simulation time 6045852947 ps
CPU time 54.57 seconds
Started Jul 23 06:45:00 PM PDT 24
Finished Jul 23 06:46:00 PM PDT 24
Peak memory 206820 kb
Host smart-65695148-49d3-4eb2-8e62-564ff083147d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41605
34271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.4160534271
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.4211414909
Short name T877
Test name
Test status
Simulation time 4385743782 ps
CPU time 123.27 seconds
Started Jul 23 06:44:59 PM PDT 24
Finished Jul 23 06:47:08 PM PDT 24
Peak memory 206892 kb
Host smart-23c56e81-2c8f-4ac7-9a23-056af85d53d3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4211414909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.4211414909
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.2968321554
Short name T549
Test name
Test status
Simulation time 157077225 ps
CPU time 0.78 seconds
Started Jul 23 06:44:59 PM PDT 24
Finished Jul 23 06:45:05 PM PDT 24
Peak memory 206780 kb
Host smart-8865cea9-c84f-49c1-bc1f-c7ec4a70f856
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2968321554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.2968321554
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.586461215
Short name T1793
Test name
Test status
Simulation time 144959382 ps
CPU time 0.76 seconds
Started Jul 23 06:45:00 PM PDT 24
Finished Jul 23 06:45:06 PM PDT 24
Peak memory 206768 kb
Host smart-e5cae5bb-6936-4624-ad9c-689f7a967ef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58646
1215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.586461215
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.4237383482
Short name T2336
Test name
Test status
Simulation time 183347761 ps
CPU time 0.86 seconds
Started Jul 23 06:44:59 PM PDT 24
Finished Jul 23 06:45:05 PM PDT 24
Peak memory 206764 kb
Host smart-23aff49c-69ac-44d8-9b91-ce6a15af0212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42373
83482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.4237383482
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.1145061198
Short name T2004
Test name
Test status
Simulation time 183084982 ps
CPU time 0.87 seconds
Started Jul 23 06:44:57 PM PDT 24
Finished Jul 23 06:45:03 PM PDT 24
Peak memory 206752 kb
Host smart-d2a55d54-b8c9-4c19-8d2f-2d060a6c95f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11450
61198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.1145061198
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.3802737990
Short name T1366
Test name
Test status
Simulation time 241316557 ps
CPU time 0.85 seconds
Started Jul 23 06:44:59 PM PDT 24
Finished Jul 23 06:45:05 PM PDT 24
Peak memory 206732 kb
Host smart-44c7d787-fd9a-4462-88fd-b44db4633cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38027
37990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.3802737990
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.2908356049
Short name T663
Test name
Test status
Simulation time 161477919 ps
CPU time 0.86 seconds
Started Jul 23 06:45:05 PM PDT 24
Finished Jul 23 06:45:11 PM PDT 24
Peak memory 206732 kb
Host smart-bfffa44e-78b9-4286-8d8e-729c49c6d183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29083
56049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.2908356049
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.2257928461
Short name T2198
Test name
Test status
Simulation time 172219136 ps
CPU time 0.8 seconds
Started Jul 23 06:44:59 PM PDT 24
Finished Jul 23 06:45:05 PM PDT 24
Peak memory 206748 kb
Host smart-6c05817d-d09d-4d92-bb92-091f25f74a48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22579
28461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.2257928461
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.2076548153
Short name T1273
Test name
Test status
Simulation time 268035314 ps
CPU time 0.96 seconds
Started Jul 23 06:44:58 PM PDT 24
Finished Jul 23 06:45:05 PM PDT 24
Peak memory 206760 kb
Host smart-6252d540-9472-448b-8daf-bf88c89c5be8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2076548153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.2076548153
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.316997498
Short name T2668
Test name
Test status
Simulation time 147042509 ps
CPU time 0.79 seconds
Started Jul 23 06:45:01 PM PDT 24
Finished Jul 23 06:45:07 PM PDT 24
Peak memory 206748 kb
Host smart-aac21b45-02ba-4598-bfc0-7ecd78d0d411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31699
7498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.316997498
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.961126875
Short name T1036
Test name
Test status
Simulation time 41487323 ps
CPU time 0.67 seconds
Started Jul 23 06:45:01 PM PDT 24
Finished Jul 23 06:45:08 PM PDT 24
Peak memory 206756 kb
Host smart-fe32fbc3-19ba-4929-98ce-54b65b2d6033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96112
6875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.961126875
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.2051611696
Short name T1341
Test name
Test status
Simulation time 10013661950 ps
CPU time 21.15 seconds
Started Jul 23 06:44:58 PM PDT 24
Finished Jul 23 06:45:25 PM PDT 24
Peak memory 206996 kb
Host smart-2bb76fee-1bf6-42c1-b80a-ce80f76d5afa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20516
11696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.2051611696
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.1832928901
Short name T516
Test name
Test status
Simulation time 165272392 ps
CPU time 0.84 seconds
Started Jul 23 06:44:59 PM PDT 24
Finished Jul 23 06:45:06 PM PDT 24
Peak memory 206784 kb
Host smart-a85baac7-d0ac-428d-9cfe-bf91edaf1efd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18329
28901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.1832928901
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.401138377
Short name T2163
Test name
Test status
Simulation time 203637003 ps
CPU time 0.92 seconds
Started Jul 23 06:44:59 PM PDT 24
Finished Jul 23 06:45:06 PM PDT 24
Peak memory 206756 kb
Host smart-4196f33e-56bb-46cf-b32d-1a93e303afaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40113
8377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.401138377
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.508438566
Short name T2614
Test name
Test status
Simulation time 249950076 ps
CPU time 0.94 seconds
Started Jul 23 06:44:57 PM PDT 24
Finished Jul 23 06:45:04 PM PDT 24
Peak memory 206708 kb
Host smart-4fd47f6b-fabc-4703-a42d-f119d260597f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50843
8566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.508438566
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.304048101
Short name T1262
Test name
Test status
Simulation time 200126901 ps
CPU time 0.81 seconds
Started Jul 23 06:45:00 PM PDT 24
Finished Jul 23 06:45:07 PM PDT 24
Peak memory 206736 kb
Host smart-cfeb3bb9-0a99-427e-a5d4-c33f904330dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30404
8101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.304048101
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.3167205554
Short name T1652
Test name
Test status
Simulation time 155216730 ps
CPU time 0.83 seconds
Started Jul 23 06:45:00 PM PDT 24
Finished Jul 23 06:45:07 PM PDT 24
Peak memory 206660 kb
Host smart-a9329d00-a01c-42d1-86c6-eeeb8a1289d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31672
05554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.3167205554
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.380040715
Short name T1884
Test name
Test status
Simulation time 148465638 ps
CPU time 0.77 seconds
Started Jul 23 06:45:03 PM PDT 24
Finished Jul 23 06:45:10 PM PDT 24
Peak memory 206768 kb
Host smart-f38e92e2-4055-44bd-8404-4607683aebff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38004
0715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.380040715
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.2155746053
Short name T781
Test name
Test status
Simulation time 147998805 ps
CPU time 0.77 seconds
Started Jul 23 06:45:07 PM PDT 24
Finished Jul 23 06:45:13 PM PDT 24
Peak memory 206772 kb
Host smart-58d91c43-ddda-49b5-a4ee-33dd8781928d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21557
46053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.2155746053
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.2934401993
Short name T1669
Test name
Test status
Simulation time 211065612 ps
CPU time 0.91 seconds
Started Jul 23 06:45:05 PM PDT 24
Finished Jul 23 06:45:11 PM PDT 24
Peak memory 206764 kb
Host smart-9a322d34-ea72-4417-9327-ec0a12db44bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29344
01993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.2934401993
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.3903280391
Short name T2408
Test name
Test status
Simulation time 3831806414 ps
CPU time 26.27 seconds
Started Jul 23 06:45:13 PM PDT 24
Finished Jul 23 06:45:43 PM PDT 24
Peak memory 206924 kb
Host smart-8b707231-b093-4810-9a83-861cd0a99914
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3903280391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.3903280391
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.1786621050
Short name T2208
Test name
Test status
Simulation time 178613395 ps
CPU time 0.93 seconds
Started Jul 23 06:45:04 PM PDT 24
Finished Jul 23 06:45:11 PM PDT 24
Peak memory 206760 kb
Host smart-8c501edf-cef3-4a04-9014-30e3faea4913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17866
21050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.1786621050
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.2240898213
Short name T2583
Test name
Test status
Simulation time 189190066 ps
CPU time 0.88 seconds
Started Jul 23 06:45:03 PM PDT 24
Finished Jul 23 06:45:10 PM PDT 24
Peak memory 206780 kb
Host smart-a3d167f4-233f-40d8-a310-c1720bee33e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22408
98213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.2240898213
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.730384274
Short name T548
Test name
Test status
Simulation time 1104448933 ps
CPU time 2.46 seconds
Started Jul 23 06:45:05 PM PDT 24
Finished Jul 23 06:45:13 PM PDT 24
Peak memory 206904 kb
Host smart-eb34ff48-f874-4fa0-b1d2-5de02f618817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73038
4274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.730384274
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.294711199
Short name T2383
Test name
Test status
Simulation time 4842100048 ps
CPU time 43.33 seconds
Started Jul 23 06:45:06 PM PDT 24
Finished Jul 23 06:45:55 PM PDT 24
Peak memory 206908 kb
Host smart-259c4118-4fc7-468c-837c-2bbcb85be209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29471
1199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.294711199
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.1839280889
Short name T756
Test name
Test status
Simulation time 35871026 ps
CPU time 0.66 seconds
Started Jul 23 06:45:23 PM PDT 24
Finished Jul 23 06:45:27 PM PDT 24
Peak memory 206744 kb
Host smart-d3161441-4fba-4b92-a6bc-e7593c30c896
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1839280889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.1839280889
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.158344400
Short name T1364
Test name
Test status
Simulation time 3704209673 ps
CPU time 4.16 seconds
Started Jul 23 06:45:08 PM PDT 24
Finished Jul 23 06:45:17 PM PDT 24
Peak memory 206900 kb
Host smart-c02b5625-3afa-4c92-94cd-1e9fd5f86757
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=158344400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.158344400
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.3964834200
Short name T2059
Test name
Test status
Simulation time 13368038089 ps
CPU time 12.23 seconds
Started Jul 23 06:45:05 PM PDT 24
Finished Jul 23 06:45:23 PM PDT 24
Peak memory 206836 kb
Host smart-df0cc44f-9270-4fa0-afc7-ee04dc939b91
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3964834200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.3964834200
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.3118787532
Short name T2462
Test name
Test status
Simulation time 23434144776 ps
CPU time 24.58 seconds
Started Jul 23 06:45:01 PM PDT 24
Finished Jul 23 06:45:32 PM PDT 24
Peak memory 206908 kb
Host smart-4eabeffb-bdac-4289-a7b5-9ab5b5e85bd6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3118787532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.3118787532
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.1079194254
Short name T1394
Test name
Test status
Simulation time 150107069 ps
CPU time 0.78 seconds
Started Jul 23 06:45:03 PM PDT 24
Finished Jul 23 06:45:10 PM PDT 24
Peak memory 206720 kb
Host smart-978b9bed-1305-4f92-82d4-35f6e00a8e3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10791
94254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.1079194254
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.4161060483
Short name T2275
Test name
Test status
Simulation time 152786228 ps
CPU time 0.77 seconds
Started Jul 23 06:45:03 PM PDT 24
Finished Jul 23 06:45:10 PM PDT 24
Peak memory 206720 kb
Host smart-e6351cc2-5888-45ae-ae38-cc0d1d394dfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41610
60483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.4161060483
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.3840359548
Short name T115
Test name
Test status
Simulation time 549316628 ps
CPU time 1.55 seconds
Started Jul 23 06:45:09 PM PDT 24
Finished Jul 23 06:45:16 PM PDT 24
Peak memory 206828 kb
Host smart-b5090c33-31b5-4721-8d8f-452f50b2b59f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38403
59548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.3840359548
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.598283646
Short name T1290
Test name
Test status
Simulation time 1017256907 ps
CPU time 2.28 seconds
Started Jul 23 06:45:07 PM PDT 24
Finished Jul 23 06:45:15 PM PDT 24
Peak memory 206912 kb
Host smart-8387d4f9-f4fc-43da-9ea6-cf0d46ed5bfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59828
3646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.598283646
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.1706242948
Short name T600
Test name
Test status
Simulation time 13379857093 ps
CPU time 26.4 seconds
Started Jul 23 06:45:12 PM PDT 24
Finished Jul 23 06:45:43 PM PDT 24
Peak memory 206876 kb
Host smart-43b299de-fb12-4c4b-93ce-6e7390804a10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17062
42948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.1706242948
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.3364441873
Short name T2323
Test name
Test status
Simulation time 406928769 ps
CPU time 1.2 seconds
Started Jul 23 06:45:06 PM PDT 24
Finished Jul 23 06:45:13 PM PDT 24
Peak memory 206772 kb
Host smart-0592fe0e-0bca-4d55-bbf3-5302ce4cb4f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33644
41873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.3364441873
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.3362858817
Short name T1562
Test name
Test status
Simulation time 187327231 ps
CPU time 0.82 seconds
Started Jul 23 06:45:13 PM PDT 24
Finished Jul 23 06:45:17 PM PDT 24
Peak memory 206772 kb
Host smart-eee79c00-d2f3-4dc4-8914-97a6d54441b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33628
58817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.3362858817
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.1716369762
Short name T1288
Test name
Test status
Simulation time 33257091 ps
CPU time 0.7 seconds
Started Jul 23 06:45:11 PM PDT 24
Finished Jul 23 06:45:16 PM PDT 24
Peak memory 206684 kb
Host smart-dd69e411-84c4-4155-a4b1-3e34234da72b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17163
69762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.1716369762
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.2695591743
Short name T326
Test name
Test status
Simulation time 883332972 ps
CPU time 2.15 seconds
Started Jul 23 06:45:09 PM PDT 24
Finished Jul 23 06:45:16 PM PDT 24
Peak memory 206820 kb
Host smart-1d01b37d-6412-4cdf-bdf7-b349c688cd43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26955
91743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.2695591743
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.2152330416
Short name T1206
Test name
Test status
Simulation time 308843497 ps
CPU time 1.94 seconds
Started Jul 23 06:45:08 PM PDT 24
Finished Jul 23 06:45:15 PM PDT 24
Peak memory 206852 kb
Host smart-27dcb948-1aaf-4a7b-9d79-8121d0ad25c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21523
30416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.2152330416
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.190392663
Short name T718
Test name
Test status
Simulation time 220388761 ps
CPU time 0.92 seconds
Started Jul 23 06:45:11 PM PDT 24
Finished Jul 23 06:45:16 PM PDT 24
Peak memory 206756 kb
Host smart-13e5d7ea-1e10-4ff7-a901-2c373c288c24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19039
2663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.190392663
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.704401348
Short name T2721
Test name
Test status
Simulation time 149713189 ps
CPU time 0.76 seconds
Started Jul 23 06:45:11 PM PDT 24
Finished Jul 23 06:45:16 PM PDT 24
Peak memory 206792 kb
Host smart-1baeedd9-c291-42bc-ba96-049893646dc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70440
1348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.704401348
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.3224475428
Short name T905
Test name
Test status
Simulation time 186870595 ps
CPU time 0.88 seconds
Started Jul 23 06:45:11 PM PDT 24
Finished Jul 23 06:45:17 PM PDT 24
Peak memory 206756 kb
Host smart-2b25b6c6-7540-4a53-8c4e-f537bf75257b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32244
75428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.3224475428
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.2883284168
Short name T109
Test name
Test status
Simulation time 7024686224 ps
CPU time 67.58 seconds
Started Jul 23 06:45:09 PM PDT 24
Finished Jul 23 06:46:21 PM PDT 24
Peak memory 206944 kb
Host smart-d993d295-04ba-4604-866f-b9be1da48525
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2883284168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.2883284168
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_iso_retraction.1181806159
Short name T2093
Test name
Test status
Simulation time 7952457114 ps
CPU time 22.87 seconds
Started Jul 23 06:45:09 PM PDT 24
Finished Jul 23 06:45:37 PM PDT 24
Peak memory 206932 kb
Host smart-8616bde4-b6b1-47eb-831c-68a9ef3dfb14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11818
06159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_iso_retraction.1181806159
Directory /workspace/37.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.4104769388
Short name T730
Test name
Test status
Simulation time 175532820 ps
CPU time 0.84 seconds
Started Jul 23 06:45:09 PM PDT 24
Finished Jul 23 06:45:15 PM PDT 24
Peak memory 206764 kb
Host smart-99edcdc9-b075-404b-8007-666798913ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41047
69388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.4104769388
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.1681499276
Short name T448
Test name
Test status
Simulation time 23308364087 ps
CPU time 27.51 seconds
Started Jul 23 06:45:08 PM PDT 24
Finished Jul 23 06:45:41 PM PDT 24
Peak memory 206832 kb
Host smart-879db2a7-4bad-4617-990e-bcf3b00e92fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16814
99276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.1681499276
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.2615600038
Short name T743
Test name
Test status
Simulation time 3368702838 ps
CPU time 3.91 seconds
Started Jul 23 06:45:10 PM PDT 24
Finished Jul 23 06:45:19 PM PDT 24
Peak memory 206800 kb
Host smart-0a09cd00-909f-4e6d-af6b-36705e12f783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26156
00038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.2615600038
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.427887145
Short name T442
Test name
Test status
Simulation time 12053225065 ps
CPU time 119.22 seconds
Started Jul 23 06:45:11 PM PDT 24
Finished Jul 23 06:47:15 PM PDT 24
Peak memory 207008 kb
Host smart-1d255ddf-74b1-4d72-91ca-f3d4084df1b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42788
7145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.427887145
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.3773858654
Short name T1298
Test name
Test status
Simulation time 6099648326 ps
CPU time 54.49 seconds
Started Jul 23 06:45:11 PM PDT 24
Finished Jul 23 06:46:10 PM PDT 24
Peak memory 206908 kb
Host smart-5ab133d7-8e8b-4e3b-8ee7-5081156b38f0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3773858654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.3773858654
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.987679686
Short name T1280
Test name
Test status
Simulation time 246184942 ps
CPU time 0.9 seconds
Started Jul 23 06:45:09 PM PDT 24
Finished Jul 23 06:45:15 PM PDT 24
Peak memory 206756 kb
Host smart-f60504cb-0a31-47ce-98ca-14e79de8b3f1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=987679686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.987679686
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.1711076915
Short name T1087
Test name
Test status
Simulation time 228795343 ps
CPU time 0.96 seconds
Started Jul 23 06:45:08 PM PDT 24
Finished Jul 23 06:45:14 PM PDT 24
Peak memory 206724 kb
Host smart-6580c0eb-4600-4ca4-ba6e-cde655a65265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17110
76915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.1711076915
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.72737484
Short name T923
Test name
Test status
Simulation time 4418034275 ps
CPU time 40.83 seconds
Started Jul 23 06:45:17 PM PDT 24
Finished Jul 23 06:45:59 PM PDT 24
Peak memory 206920 kb
Host smart-c35e76e8-ddaa-4a09-84b0-ce5e47c4d2ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72737
484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.72737484
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.892045144
Short name T1317
Test name
Test status
Simulation time 4875253415 ps
CPU time 127.64 seconds
Started Jul 23 06:45:17 PM PDT 24
Finished Jul 23 06:47:27 PM PDT 24
Peak memory 206936 kb
Host smart-a294c0ec-f173-4442-88d5-9348ad6e5264
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=892045144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.892045144
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.2143996232
Short name T1233
Test name
Test status
Simulation time 152416812 ps
CPU time 0.81 seconds
Started Jul 23 06:45:18 PM PDT 24
Finished Jul 23 06:45:22 PM PDT 24
Peak memory 206772 kb
Host smart-75a8830e-2b9b-41b9-a18f-cb3b7c080c49
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2143996232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.2143996232
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.791432780
Short name T2136
Test name
Test status
Simulation time 140463393 ps
CPU time 0.75 seconds
Started Jul 23 06:45:17 PM PDT 24
Finished Jul 23 06:45:19 PM PDT 24
Peak memory 206776 kb
Host smart-3ee140f9-ef46-4f5a-9617-dd09845f0c6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79143
2780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.791432780
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.3050166799
Short name T1730
Test name
Test status
Simulation time 163790043 ps
CPU time 0.8 seconds
Started Jul 23 06:45:17 PM PDT 24
Finished Jul 23 06:45:19 PM PDT 24
Peak memory 206664 kb
Host smart-205e180d-03c5-47b7-a698-c04c529aef98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30501
66799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.3050166799
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.255912964
Short name T1031
Test name
Test status
Simulation time 168904161 ps
CPU time 0.79 seconds
Started Jul 23 06:45:21 PM PDT 24
Finished Jul 23 06:45:23 PM PDT 24
Peak memory 206728 kb
Host smart-1e5ca6af-8c41-4413-9409-2c53fbb583eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25591
2964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.255912964
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.1447607256
Short name T2304
Test name
Test status
Simulation time 171948531 ps
CPU time 0.82 seconds
Started Jul 23 06:45:21 PM PDT 24
Finished Jul 23 06:45:23 PM PDT 24
Peak memory 206692 kb
Host smart-ff75f936-58b2-4ef5-a915-366e03033db2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14476
07256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.1447607256
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.1679035261
Short name T460
Test name
Test status
Simulation time 180219322 ps
CPU time 0.83 seconds
Started Jul 23 06:45:17 PM PDT 24
Finished Jul 23 06:45:20 PM PDT 24
Peak memory 206744 kb
Host smart-a04e5b66-263a-4959-9f19-e50e582c9238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16790
35261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.1679035261
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.1524561316
Short name T901
Test name
Test status
Simulation time 156487059 ps
CPU time 0.78 seconds
Started Jul 23 06:45:17 PM PDT 24
Finished Jul 23 06:45:20 PM PDT 24
Peak memory 206768 kb
Host smart-f3967ff7-44d8-4c1d-aa9e-98eb7c81bc43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15245
61316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.1524561316
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.329510014
Short name T2358
Test name
Test status
Simulation time 240038570 ps
CPU time 0.94 seconds
Started Jul 23 06:45:18 PM PDT 24
Finished Jul 23 06:45:22 PM PDT 24
Peak memory 206744 kb
Host smart-505d5527-8d1b-4e4b-8785-3bc07d5aa088
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=329510014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.329510014
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.3823246682
Short name T1668
Test name
Test status
Simulation time 171004384 ps
CPU time 0.79 seconds
Started Jul 23 06:45:18 PM PDT 24
Finished Jul 23 06:45:20 PM PDT 24
Peak memory 206692 kb
Host smart-94853136-3047-4059-8b21-30771e5bc352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38232
46682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.3823246682
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.2188361837
Short name T2209
Test name
Test status
Simulation time 38101916 ps
CPU time 0.67 seconds
Started Jul 23 06:45:26 PM PDT 24
Finished Jul 23 06:45:29 PM PDT 24
Peak memory 206756 kb
Host smart-ea4f863c-eff8-4d63-8c5a-db7b03ce4e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21883
61837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.2188361837
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.3462507804
Short name T2617
Test name
Test status
Simulation time 7922219320 ps
CPU time 16.88 seconds
Started Jul 23 06:45:22 PM PDT 24
Finished Jul 23 06:45:41 PM PDT 24
Peak memory 206924 kb
Host smart-c84fc477-7f64-459c-8021-d99a0daae803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34625
07804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.3462507804
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.647758502
Short name T1611
Test name
Test status
Simulation time 212506744 ps
CPU time 0.88 seconds
Started Jul 23 06:45:18 PM PDT 24
Finished Jul 23 06:45:21 PM PDT 24
Peak memory 206720 kb
Host smart-34712422-bc52-436e-9d50-98986dd9388e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64775
8502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.647758502
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.1320534600
Short name T1699
Test name
Test status
Simulation time 229381341 ps
CPU time 0.9 seconds
Started Jul 23 06:45:28 PM PDT 24
Finished Jul 23 06:45:32 PM PDT 24
Peak memory 206768 kb
Host smart-39d93536-04d3-487b-a6a0-34e12fe3b749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13205
34600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.1320534600
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.1461233687
Short name T753
Test name
Test status
Simulation time 161464162 ps
CPU time 0.8 seconds
Started Jul 23 06:45:34 PM PDT 24
Finished Jul 23 06:45:40 PM PDT 24
Peak memory 206732 kb
Host smart-65868404-28ef-46a3-9377-f55e0aa37744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14612
33687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.1461233687
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.3431453853
Short name T2345
Test name
Test status
Simulation time 182500837 ps
CPU time 0.88 seconds
Started Jul 23 06:45:33 PM PDT 24
Finished Jul 23 06:45:37 PM PDT 24
Peak memory 206760 kb
Host smart-4fb4a070-8cfd-4467-8418-558a576953b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34314
53853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.3431453853
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.2103027475
Short name T1769
Test name
Test status
Simulation time 204962389 ps
CPU time 0.82 seconds
Started Jul 23 06:45:31 PM PDT 24
Finished Jul 23 06:45:35 PM PDT 24
Peak memory 206708 kb
Host smart-5d18e638-5e34-4d6d-9759-bc3303e1b712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21030
27475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.2103027475
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.3345435888
Short name T684
Test name
Test status
Simulation time 184187060 ps
CPU time 0.81 seconds
Started Jul 23 06:45:21 PM PDT 24
Finished Jul 23 06:45:24 PM PDT 24
Peak memory 206736 kb
Host smart-427ead42-23ea-4c6e-8cf8-0df232756d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33454
35888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.3345435888
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.2952732879
Short name T732
Test name
Test status
Simulation time 195847910 ps
CPU time 0.77 seconds
Started Jul 23 06:45:23 PM PDT 24
Finished Jul 23 06:45:27 PM PDT 24
Peak memory 206756 kb
Host smart-d3819e89-bd10-4a3d-a019-538ed4b23f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29527
32879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.2952732879
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.492894513
Short name T2697
Test name
Test status
Simulation time 214050339 ps
CPU time 0.87 seconds
Started Jul 23 06:45:23 PM PDT 24
Finished Jul 23 06:45:26 PM PDT 24
Peak memory 206700 kb
Host smart-1999b929-db56-40f0-bcec-3dfd9525d8d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49289
4513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.492894513
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.4161954792
Short name T2426
Test name
Test status
Simulation time 4737025551 ps
CPU time 43.86 seconds
Started Jul 23 06:45:23 PM PDT 24
Finished Jul 23 06:46:09 PM PDT 24
Peak memory 206876 kb
Host smart-0524ef25-15fe-4b95-a06b-e5a36632e59e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4161954792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.4161954792
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.1043660331
Short name T2397
Test name
Test status
Simulation time 204240834 ps
CPU time 0.81 seconds
Started Jul 23 06:45:28 PM PDT 24
Finished Jul 23 06:45:31 PM PDT 24
Peak memory 206752 kb
Host smart-61682902-a793-41ed-8feb-142560d8efd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10436
60331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.1043660331
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.979028388
Short name T934
Test name
Test status
Simulation time 221125886 ps
CPU time 0.87 seconds
Started Jul 23 06:45:36 PM PDT 24
Finished Jul 23 06:45:42 PM PDT 24
Peak memory 206752 kb
Host smart-2e642420-6e34-43bd-bfe6-cbb7d4e79653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97902
8388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.979028388
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.3258695311
Short name T654
Test name
Test status
Simulation time 385922267 ps
CPU time 1.16 seconds
Started Jul 23 06:45:24 PM PDT 24
Finished Jul 23 06:45:28 PM PDT 24
Peak memory 206752 kb
Host smart-85639a24-428f-45c1-8384-e00eb4e5638e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32586
95311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.3258695311
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.1095735432
Short name T2321
Test name
Test status
Simulation time 3141685213 ps
CPU time 81.39 seconds
Started Jul 23 06:45:25 PM PDT 24
Finished Jul 23 06:46:50 PM PDT 24
Peak memory 207084 kb
Host smart-9f4cb238-730c-47ab-a3e6-735074b94e38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10957
35432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.1095735432
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.620129185
Short name T1549
Test name
Test status
Simulation time 31120590 ps
CPU time 0.66 seconds
Started Jul 23 06:45:42 PM PDT 24
Finished Jul 23 06:45:48 PM PDT 24
Peak memory 206756 kb
Host smart-7f55f881-de0d-4952-9f07-8041a2daa4b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=620129185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.620129185
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.2014759294
Short name T1738
Test name
Test status
Simulation time 3802353640 ps
CPU time 4.87 seconds
Started Jul 23 06:45:24 PM PDT 24
Finished Jul 23 06:45:31 PM PDT 24
Peak memory 206824 kb
Host smart-6343a3b8-0894-4ab0-8108-012860f9d177
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2014759294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.2014759294
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.1297312004
Short name T593
Test name
Test status
Simulation time 13358154948 ps
CPU time 13.4 seconds
Started Jul 23 06:45:23 PM PDT 24
Finished Jul 23 06:45:39 PM PDT 24
Peak memory 206964 kb
Host smart-56a50983-3388-4caf-87bd-32d5e8f568f3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1297312004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.1297312004
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.3000995171
Short name T14
Test name
Test status
Simulation time 23430644957 ps
CPU time 25.22 seconds
Started Jul 23 06:45:34 PM PDT 24
Finished Jul 23 06:46:05 PM PDT 24
Peak memory 206828 kb
Host smart-d2740127-c7b8-4681-a039-8bbb07a4d788
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3000995171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.3000995171
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.4092935210
Short name T1608
Test name
Test status
Simulation time 154778599 ps
CPU time 0.84 seconds
Started Jul 23 06:45:30 PM PDT 24
Finished Jul 23 06:45:34 PM PDT 24
Peak memory 206732 kb
Host smart-0de99ea0-d99e-4f36-8399-2cb1ee05909e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40929
35210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.4092935210
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.1842133967
Short name T1712
Test name
Test status
Simulation time 528664283 ps
CPU time 1.67 seconds
Started Jul 23 06:45:25 PM PDT 24
Finished Jul 23 06:45:29 PM PDT 24
Peak memory 206884 kb
Host smart-b1ceb413-c3e3-4ee6-9f75-2cac8cc62358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18421
33967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.1842133967
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.3347899674
Short name T538
Test name
Test status
Simulation time 345152821 ps
CPU time 1.06 seconds
Started Jul 23 06:45:24 PM PDT 24
Finished Jul 23 06:45:28 PM PDT 24
Peak memory 206656 kb
Host smart-cab45ed3-40d5-439a-8840-1b74dbfcc43e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33478
99674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.3347899674
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.257788737
Short name T1744
Test name
Test status
Simulation time 20161733484 ps
CPU time 34.38 seconds
Started Jul 23 06:45:29 PM PDT 24
Finished Jul 23 06:46:07 PM PDT 24
Peak memory 206932 kb
Host smart-2f72022c-8be7-4fa1-ad8a-1e4100e7113a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25778
8737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.257788737
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.3385598323
Short name T1632
Test name
Test status
Simulation time 408307232 ps
CPU time 1.27 seconds
Started Jul 23 06:45:26 PM PDT 24
Finished Jul 23 06:45:30 PM PDT 24
Peak memory 206756 kb
Host smart-b1d4b201-284a-4865-966e-fde8164df718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33855
98323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.3385598323
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.2688894168
Short name T1564
Test name
Test status
Simulation time 141580538 ps
CPU time 0.74 seconds
Started Jul 23 06:45:39 PM PDT 24
Finished Jul 23 06:45:46 PM PDT 24
Peak memory 206760 kb
Host smart-ad41d09f-9b1e-4675-ad36-e8389938e760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26888
94168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.2688894168
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.4267150361
Short name T1401
Test name
Test status
Simulation time 37159267 ps
CPU time 0.68 seconds
Started Jul 23 06:45:34 PM PDT 24
Finished Jul 23 06:45:39 PM PDT 24
Peak memory 206916 kb
Host smart-4d84418e-d099-4964-b286-96a71fb020fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42671
50361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.4267150361
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.1882701080
Short name T1618
Test name
Test status
Simulation time 940645224 ps
CPU time 2.4 seconds
Started Jul 23 06:45:25 PM PDT 24
Finished Jul 23 06:45:31 PM PDT 24
Peak memory 206868 kb
Host smart-9afb5e5b-ffd5-4bf6-a4c2-7f2c676bfe33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18827
01080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.1882701080
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.2372276467
Short name T2361
Test name
Test status
Simulation time 147257266 ps
CPU time 1.17 seconds
Started Jul 23 06:45:30 PM PDT 24
Finished Jul 23 06:45:33 PM PDT 24
Peak memory 206868 kb
Host smart-d1b13466-83aa-4597-9ae5-8142601f51e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23722
76467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.2372276467
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.3798437614
Short name T2369
Test name
Test status
Simulation time 185307232 ps
CPU time 0.88 seconds
Started Jul 23 06:45:32 PM PDT 24
Finished Jul 23 06:45:37 PM PDT 24
Peak memory 206756 kb
Host smart-82db6c0d-ead3-431d-b59d-9db474144020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37984
37614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.3798437614
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.3214433359
Short name T947
Test name
Test status
Simulation time 148751342 ps
CPU time 0.76 seconds
Started Jul 23 06:45:26 PM PDT 24
Finished Jul 23 06:45:30 PM PDT 24
Peak memory 206760 kb
Host smart-1f1a1015-c50f-46c6-9f93-43a35e82f85a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32144
33359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.3214433359
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.2759038777
Short name T768
Test name
Test status
Simulation time 177671852 ps
CPU time 0.9 seconds
Started Jul 23 06:45:32 PM PDT 24
Finished Jul 23 06:45:35 PM PDT 24
Peak memory 206764 kb
Host smart-920e04f2-90d8-400e-b06d-30d427d68ca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27590
38777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.2759038777
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.1136453179
Short name T1508
Test name
Test status
Simulation time 8249439967 ps
CPU time 71.26 seconds
Started Jul 23 06:45:26 PM PDT 24
Finished Jul 23 06:46:40 PM PDT 24
Peak memory 206964 kb
Host smart-7aa19040-a473-4bd0-8936-dab7020b26fc
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1136453179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.1136453179
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_iso_retraction.2532236450
Short name T380
Test name
Test status
Simulation time 5686974611 ps
CPU time 19.28 seconds
Started Jul 23 06:45:32 PM PDT 24
Finished Jul 23 06:45:53 PM PDT 24
Peak memory 206892 kb
Host smart-008634e5-22a9-48e7-8b3c-17d31f555ddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25322
36450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_iso_retraction.2532236450
Directory /workspace/38.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.406304933
Short name T873
Test name
Test status
Simulation time 266457643 ps
CPU time 0.92 seconds
Started Jul 23 06:45:29 PM PDT 24
Finished Jul 23 06:45:33 PM PDT 24
Peak memory 206664 kb
Host smart-a74b9f2f-8097-49d2-b92d-1645b8c1df43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40630
4933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.406304933
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.3281577032
Short name T1287
Test name
Test status
Simulation time 23291113893 ps
CPU time 22.16 seconds
Started Jul 23 06:45:31 PM PDT 24
Finished Jul 23 06:45:55 PM PDT 24
Peak memory 206812 kb
Host smart-2f3ad1de-f861-49ac-b1dd-01b5cdfe18ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32815
77032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.3281577032
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.996205038
Short name T405
Test name
Test status
Simulation time 3287185760 ps
CPU time 3.82 seconds
Started Jul 23 06:45:30 PM PDT 24
Finished Jul 23 06:45:36 PM PDT 24
Peak memory 206820 kb
Host smart-67892dd2-7666-466a-a2dd-3fe30271e8ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99620
5038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.996205038
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.1627439100
Short name T1585
Test name
Test status
Simulation time 9622931186 ps
CPU time 250.35 seconds
Started Jul 23 06:45:31 PM PDT 24
Finished Jul 23 06:49:44 PM PDT 24
Peak memory 206952 kb
Host smart-0b16508e-5304-4ba4-b88c-59e58978b013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16274
39100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.1627439100
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.3846290537
Short name T2699
Test name
Test status
Simulation time 4277066089 ps
CPU time 107.53 seconds
Started Jul 23 06:45:33 PM PDT 24
Finished Jul 23 06:47:25 PM PDT 24
Peak memory 206900 kb
Host smart-a3da8a67-e6e0-4935-9d3e-6cb629627436
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3846290537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.3846290537
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.1821643456
Short name T384
Test name
Test status
Simulation time 259321017 ps
CPU time 0.96 seconds
Started Jul 23 06:45:33 PM PDT 24
Finished Jul 23 06:45:38 PM PDT 24
Peak memory 206772 kb
Host smart-5a1bb2e5-6081-4885-bff0-4632d3c6b82d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1821643456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.1821643456
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.134277352
Short name T301
Test name
Test status
Simulation time 193457997 ps
CPU time 0.88 seconds
Started Jul 23 06:45:35 PM PDT 24
Finished Jul 23 06:45:41 PM PDT 24
Peak memory 206552 kb
Host smart-8cd579d7-5a0a-4ad3-803f-df24bb666e7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13427
7352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.134277352
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.1886322233
Short name T733
Test name
Test status
Simulation time 3026010314 ps
CPU time 21.31 seconds
Started Jul 23 06:45:37 PM PDT 24
Finished Jul 23 06:46:04 PM PDT 24
Peak memory 206904 kb
Host smart-ff52a638-9b6f-4cc6-900c-954abb658564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18863
22233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.1886322233
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.3014957680
Short name T310
Test name
Test status
Simulation time 5428270364 ps
CPU time 147.91 seconds
Started Jul 23 06:45:35 PM PDT 24
Finished Jul 23 06:48:08 PM PDT 24
Peak memory 206916 kb
Host smart-b4a48f29-8bfd-4497-9ee2-1f253cecd6a1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3014957680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.3014957680
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.414644923
Short name T1878
Test name
Test status
Simulation time 153791122 ps
CPU time 0.81 seconds
Started Jul 23 06:45:36 PM PDT 24
Finished Jul 23 06:45:42 PM PDT 24
Peak memory 206740 kb
Host smart-bf3e5f5d-576b-4d41-8fa1-6421bba04a7c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=414644923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.414644923
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.2196822622
Short name T2367
Test name
Test status
Simulation time 217489277 ps
CPU time 0.84 seconds
Started Jul 23 06:45:37 PM PDT 24
Finished Jul 23 06:45:44 PM PDT 24
Peak memory 206748 kb
Host smart-09c9bd46-bef6-4495-a611-d17a11f3f948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21968
22622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.2196822622
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.2821495182
Short name T138
Test name
Test status
Simulation time 251473626 ps
CPU time 0.95 seconds
Started Jul 23 06:45:34 PM PDT 24
Finished Jul 23 06:45:39 PM PDT 24
Peak memory 206696 kb
Host smart-88a44728-a515-4ccc-84aa-c2adcce33d33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28214
95182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.2821495182
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.603471312
Short name T2267
Test name
Test status
Simulation time 174255508 ps
CPU time 0.84 seconds
Started Jul 23 06:45:35 PM PDT 24
Finished Jul 23 06:45:41 PM PDT 24
Peak memory 206592 kb
Host smart-62fcce34-c84a-456a-8bf7-97a746c9efca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60347
1312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.603471312
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.174377863
Short name T1434
Test name
Test status
Simulation time 199226227 ps
CPU time 0.9 seconds
Started Jul 23 06:45:35 PM PDT 24
Finished Jul 23 06:45:42 PM PDT 24
Peak memory 206756 kb
Host smart-4b23c154-cf25-4ac3-93e6-96549284f2ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17437
7863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.174377863
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.3654687241
Short name T1600
Test name
Test status
Simulation time 178719162 ps
CPU time 0.78 seconds
Started Jul 23 06:45:38 PM PDT 24
Finished Jul 23 06:45:45 PM PDT 24
Peak memory 206756 kb
Host smart-3f127c2d-ba36-462c-89e7-7033d91d0631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36546
87241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.3654687241
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.387367267
Short name T156
Test name
Test status
Simulation time 157817241 ps
CPU time 0.78 seconds
Started Jul 23 06:45:34 PM PDT 24
Finished Jul 23 06:45:40 PM PDT 24
Peak memory 206756 kb
Host smart-3d361387-5d88-4e66-8a11-3119265fcc09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38736
7267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.387367267
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.2698092353
Short name T1112
Test name
Test status
Simulation time 239700434 ps
CPU time 1.01 seconds
Started Jul 23 06:45:29 PM PDT 24
Finished Jul 23 06:45:33 PM PDT 24
Peak memory 206760 kb
Host smart-d73d039a-d57d-41e9-88e3-cdc6e8721504
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2698092353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.2698092353
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.3744196229
Short name T1836
Test name
Test status
Simulation time 142836681 ps
CPU time 0.76 seconds
Started Jul 23 06:45:35 PM PDT 24
Finished Jul 23 06:45:41 PM PDT 24
Peak memory 206752 kb
Host smart-531a64c2-f2a0-41df-9bb5-a8f82f4b3c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37441
96229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.3744196229
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.4035912502
Short name T1925
Test name
Test status
Simulation time 36097386 ps
CPU time 0.67 seconds
Started Jul 23 06:45:33 PM PDT 24
Finished Jul 23 06:45:38 PM PDT 24
Peak memory 206704 kb
Host smart-def4c6a8-6e60-44a6-ae71-0841dc2ec46a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40359
12502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.4035912502
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.2325125636
Short name T1365
Test name
Test status
Simulation time 11795927705 ps
CPU time 26.76 seconds
Started Jul 23 06:45:33 PM PDT 24
Finished Jul 23 06:46:04 PM PDT 24
Peak memory 206896 kb
Host smart-4ded3062-cfe7-42c7-90ba-5ae95e42fe63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23251
25636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.2325125636
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.2507873261
Short name T1478
Test name
Test status
Simulation time 187026396 ps
CPU time 0.92 seconds
Started Jul 23 06:45:38 PM PDT 24
Finished Jul 23 06:45:46 PM PDT 24
Peak memory 206756 kb
Host smart-9d369ab7-18d4-4f81-932a-49876d0dc7c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25078
73261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.2507873261
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.1934601402
Short name T2571
Test name
Test status
Simulation time 304021090 ps
CPU time 1.05 seconds
Started Jul 23 06:45:37 PM PDT 24
Finished Jul 23 06:45:44 PM PDT 24
Peak memory 206744 kb
Host smart-0c2c3d84-d38a-4853-85b1-dc58af9c300f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19346
01402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.1934601402
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.360742572
Short name T1827
Test name
Test status
Simulation time 226724105 ps
CPU time 0.9 seconds
Started Jul 23 06:45:45 PM PDT 24
Finished Jul 23 06:45:51 PM PDT 24
Peak memory 206724 kb
Host smart-12a67a10-4a89-49e7-96ef-30c46200446b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36074
2572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.360742572
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.3509612720
Short name T2253
Test name
Test status
Simulation time 196169768 ps
CPU time 0.8 seconds
Started Jul 23 06:45:40 PM PDT 24
Finished Jul 23 06:45:47 PM PDT 24
Peak memory 206736 kb
Host smart-d6789a2d-3ea4-4560-a625-7d588f3d0313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35096
12720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.3509612720
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.1336899595
Short name T1854
Test name
Test status
Simulation time 183897872 ps
CPU time 0.8 seconds
Started Jul 23 06:45:36 PM PDT 24
Finished Jul 23 06:45:43 PM PDT 24
Peak memory 206752 kb
Host smart-a53be8a5-915a-41ed-8032-44728c955612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13368
99595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.1336899595
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.234870596
Short name T2563
Test name
Test status
Simulation time 148407966 ps
CPU time 0.75 seconds
Started Jul 23 06:45:36 PM PDT 24
Finished Jul 23 06:45:43 PM PDT 24
Peak memory 206736 kb
Host smart-c05ba1b3-ad5c-4812-a9c0-dc4329e15031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23487
0596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.234870596
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.3331433952
Short name T2105
Test name
Test status
Simulation time 147687780 ps
CPU time 0.84 seconds
Started Jul 23 06:45:45 PM PDT 24
Finished Jul 23 06:45:51 PM PDT 24
Peak memory 206772 kb
Host smart-a82bf5f0-2149-460b-9654-deafe13bc994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33314
33952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.3331433952
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.468178077
Short name T693
Test name
Test status
Simulation time 266272800 ps
CPU time 1.03 seconds
Started Jul 23 06:45:36 PM PDT 24
Finished Jul 23 06:45:43 PM PDT 24
Peak memory 206712 kb
Host smart-aa610977-7a80-4493-b7d8-0f0961b99815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46817
8077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.468178077
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.3654844949
Short name T780
Test name
Test status
Simulation time 5987297508 ps
CPU time 43.78 seconds
Started Jul 23 06:45:42 PM PDT 24
Finished Jul 23 06:46:31 PM PDT 24
Peak memory 206896 kb
Host smart-947b3aaf-4dfb-44a2-af56-f2d6d1525a4c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3654844949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.3654844949
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.381113135
Short name T2642
Test name
Test status
Simulation time 196378615 ps
CPU time 0.86 seconds
Started Jul 23 06:45:40 PM PDT 24
Finished Jul 23 06:45:47 PM PDT 24
Peak memory 206696 kb
Host smart-2ccf3298-a21c-469c-b420-cd128d39dae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38111
3135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.381113135
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.4076034192
Short name T2633
Test name
Test status
Simulation time 199682944 ps
CPU time 0.87 seconds
Started Jul 23 06:45:37 PM PDT 24
Finished Jul 23 06:45:44 PM PDT 24
Peak memory 206756 kb
Host smart-2be6513d-0592-4d1f-b033-48414a54eaac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40760
34192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.4076034192
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.4195807103
Short name T794
Test name
Test status
Simulation time 1137895830 ps
CPU time 2.33 seconds
Started Jul 23 06:45:37 PM PDT 24
Finished Jul 23 06:45:45 PM PDT 24
Peak memory 206900 kb
Host smart-c5e55a9e-cc1d-43a1-a5cf-ad54ea08a562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41958
07103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.4195807103
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.2213389295
Short name T644
Test name
Test status
Simulation time 3571366081 ps
CPU time 98.59 seconds
Started Jul 23 06:45:38 PM PDT 24
Finished Jul 23 06:47:23 PM PDT 24
Peak memory 206912 kb
Host smart-cee65bb1-f4df-495a-85fd-099c6d0081a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22133
89295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.2213389295
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.242553222
Short name T2551
Test name
Test status
Simulation time 55331167 ps
CPU time 0.81 seconds
Started Jul 23 06:45:51 PM PDT 24
Finished Jul 23 06:45:59 PM PDT 24
Peak memory 206724 kb
Host smart-3eda9166-af0a-43a6-a2b7-424f10245c18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=242553222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.242553222
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.1588829922
Short name T1661
Test name
Test status
Simulation time 3609698669 ps
CPU time 4.22 seconds
Started Jul 23 06:45:37 PM PDT 24
Finished Jul 23 06:45:47 PM PDT 24
Peak memory 206968 kb
Host smart-d8ef7817-5a6c-430e-89e3-7c0ea459cba9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1588829922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.1588829922
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.1741936938
Short name T2529
Test name
Test status
Simulation time 13409925844 ps
CPU time 12.03 seconds
Started Jul 23 06:45:40 PM PDT 24
Finished Jul 23 06:45:58 PM PDT 24
Peak memory 206924 kb
Host smart-5376809c-635c-4193-ba1a-f9e5608f3be2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1741936938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.1741936938
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.1721647048
Short name T1952
Test name
Test status
Simulation time 23453755272 ps
CPU time 21.95 seconds
Started Jul 23 06:45:43 PM PDT 24
Finished Jul 23 06:46:10 PM PDT 24
Peak memory 206916 kb
Host smart-289bec2c-d35b-4ceb-87d5-2ecd329b6295
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1721647048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.1721647048
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.3867886678
Short name T1477
Test name
Test status
Simulation time 220392809 ps
CPU time 0.87 seconds
Started Jul 23 06:45:50 PM PDT 24
Finished Jul 23 06:45:57 PM PDT 24
Peak memory 206748 kb
Host smart-00eb3da2-bcd9-47b2-8c5f-e9aead892a45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38678
86678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.3867886678
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.4173322863
Short name T64
Test name
Test status
Simulation time 150209535 ps
CPU time 0.76 seconds
Started Jul 23 06:45:48 PM PDT 24
Finished Jul 23 06:45:56 PM PDT 24
Peak memory 206748 kb
Host smart-0e6ff39f-806c-454a-b2d6-25c9ddc3938d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41733
22863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.4173322863
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.2456830938
Short name T959
Test name
Test status
Simulation time 443900051 ps
CPU time 1.36 seconds
Started Jul 23 06:45:43 PM PDT 24
Finished Jul 23 06:45:49 PM PDT 24
Peak memory 206776 kb
Host smart-e20cbc97-6279-4531-b7bd-8570c684eaef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24568
30938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.2456830938
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.592391202
Short name T530
Test name
Test status
Simulation time 1564955433 ps
CPU time 3.29 seconds
Started Jul 23 06:45:43 PM PDT 24
Finished Jul 23 06:45:52 PM PDT 24
Peak memory 206852 kb
Host smart-9777f587-ec4d-44ae-b14c-efd7a673bb30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59239
1202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.592391202
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.2895550684
Short name T1302
Test name
Test status
Simulation time 15103613676 ps
CPU time 26.25 seconds
Started Jul 23 06:45:49 PM PDT 24
Finished Jul 23 06:46:21 PM PDT 24
Peak memory 206904 kb
Host smart-114cd86a-03d3-417e-a708-5172288b5b6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28955
50684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.2895550684
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.1135999760
Short name T1076
Test name
Test status
Simulation time 463985272 ps
CPU time 1.38 seconds
Started Jul 23 06:45:49 PM PDT 24
Finished Jul 23 06:45:57 PM PDT 24
Peak memory 206756 kb
Host smart-57b5994c-1bdb-4a85-9b91-bcb70eb003b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11359
99760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.1135999760
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.2559333294
Short name T349
Test name
Test status
Simulation time 144159307 ps
CPU time 0.74 seconds
Started Jul 23 06:45:45 PM PDT 24
Finished Jul 23 06:45:52 PM PDT 24
Peak memory 206760 kb
Host smart-aff7e9e6-d431-4264-b6d5-cbba41af036b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25593
33294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.2559333294
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.563908538
Short name T227
Test name
Test status
Simulation time 71076700 ps
CPU time 0.68 seconds
Started Jul 23 06:45:45 PM PDT 24
Finished Jul 23 06:45:51 PM PDT 24
Peak memory 206564 kb
Host smart-da9dad83-3559-41a2-9f3e-5672f83e3ec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56390
8538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.563908538
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.1184190862
Short name T2440
Test name
Test status
Simulation time 993617220 ps
CPU time 2.18 seconds
Started Jul 23 06:45:44 PM PDT 24
Finished Jul 23 06:45:51 PM PDT 24
Peak memory 206844 kb
Host smart-47c5bf8b-63e7-4500-8d02-cd14761930ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11841
90862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.1184190862
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.3130964071
Short name T1851
Test name
Test status
Simulation time 263598973 ps
CPU time 1.72 seconds
Started Jul 23 06:45:45 PM PDT 24
Finished Jul 23 06:45:52 PM PDT 24
Peak memory 206904 kb
Host smart-5545e146-92e8-473f-b8d2-90cfdf3ce9e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31309
64071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.3130964071
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.2681775338
Short name T2592
Test name
Test status
Simulation time 221263728 ps
CPU time 0.88 seconds
Started Jul 23 06:45:50 PM PDT 24
Finished Jul 23 06:45:58 PM PDT 24
Peak memory 206740 kb
Host smart-0cf1b734-8b9a-4310-a886-61badadaecc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26817
75338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.2681775338
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.897715019
Short name T550
Test name
Test status
Simulation time 160277271 ps
CPU time 0.74 seconds
Started Jul 23 06:45:49 PM PDT 24
Finished Jul 23 06:45:57 PM PDT 24
Peak memory 206752 kb
Host smart-efd42ab6-6eaf-44a0-9db4-ff3d73c99654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89771
5019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.897715019
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.2788306712
Short name T1571
Test name
Test status
Simulation time 292596696 ps
CPU time 1.04 seconds
Started Jul 23 06:45:43 PM PDT 24
Finished Jul 23 06:45:49 PM PDT 24
Peak memory 206760 kb
Host smart-f4d8f908-94f3-4aa6-9d02-b778e14c7e8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27883
06712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.2788306712
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_iso_retraction.2174232623
Short name T1579
Test name
Test status
Simulation time 9187855277 ps
CPU time 35.73 seconds
Started Jul 23 06:45:46 PM PDT 24
Finished Jul 23 06:46:28 PM PDT 24
Peak memory 206896 kb
Host smart-105d2e6d-d545-4611-9352-70f12e234a07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21742
32623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_iso_retraction.2174232623
Directory /workspace/39.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.4016684115
Short name T2716
Test name
Test status
Simulation time 180045603 ps
CPU time 0.79 seconds
Started Jul 23 06:45:45 PM PDT 24
Finished Jul 23 06:45:51 PM PDT 24
Peak memory 206752 kb
Host smart-aa791f6f-9fe2-48b1-ab9a-2780d15348fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40166
84115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.4016684115
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.2567183878
Short name T2099
Test name
Test status
Simulation time 23284221388 ps
CPU time 22.36 seconds
Started Jul 23 06:45:47 PM PDT 24
Finished Jul 23 06:46:15 PM PDT 24
Peak memory 206812 kb
Host smart-2aae7ea8-e60d-4d25-9116-e1576ce4ecc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25671
83878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.2567183878
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.4262483966
Short name T745
Test name
Test status
Simulation time 3345888123 ps
CPU time 4.49 seconds
Started Jul 23 06:45:43 PM PDT 24
Finished Jul 23 06:45:53 PM PDT 24
Peak memory 206836 kb
Host smart-622e70ee-ae5c-4db4-8605-1e024324289a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42624
83966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.4262483966
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.1902809544
Short name T1022
Test name
Test status
Simulation time 9774301426 ps
CPU time 264.16 seconds
Started Jul 23 06:45:47 PM PDT 24
Finished Jul 23 06:50:18 PM PDT 24
Peak memory 206952 kb
Host smart-1125d299-d1d8-463a-838b-8dd3e63b82fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19028
09544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.1902809544
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.2448522101
Short name T2355
Test name
Test status
Simulation time 3536074702 ps
CPU time 32.4 seconds
Started Jul 23 06:45:46 PM PDT 24
Finished Jul 23 06:46:25 PM PDT 24
Peak memory 206912 kb
Host smart-4d10c7ad-957e-4c4a-8d4e-411b688b4d7a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2448522101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.2448522101
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.1592531801
Short name T2117
Test name
Test status
Simulation time 253944624 ps
CPU time 1 seconds
Started Jul 23 06:45:49 PM PDT 24
Finished Jul 23 06:45:57 PM PDT 24
Peak memory 206728 kb
Host smart-fd4c8d9b-748a-43ab-9e30-19f8023262e6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1592531801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.1592531801
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.283721218
Short name T1253
Test name
Test status
Simulation time 237195884 ps
CPU time 0.88 seconds
Started Jul 23 06:45:44 PM PDT 24
Finished Jul 23 06:45:49 PM PDT 24
Peak memory 206692 kb
Host smart-2867641f-ba95-472c-9008-c0a31404276c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28372
1218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.283721218
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.222378498
Short name T1891
Test name
Test status
Simulation time 5699939539 ps
CPU time 53.94 seconds
Started Jul 23 06:45:44 PM PDT 24
Finished Jul 23 06:46:44 PM PDT 24
Peak memory 206896 kb
Host smart-42bb205a-a321-4746-9d1c-166875d014b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22237
8498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.222378498
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.2993465326
Short name T2720
Test name
Test status
Simulation time 8082690728 ps
CPU time 214.66 seconds
Started Jul 23 06:45:45 PM PDT 24
Finished Jul 23 06:49:25 PM PDT 24
Peak memory 206828 kb
Host smart-a40f490c-95b9-4e11-932b-2ec1db7d6fd7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2993465326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.2993465326
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.2373072074
Short name T2559
Test name
Test status
Simulation time 157156882 ps
CPU time 0.83 seconds
Started Jul 23 06:45:50 PM PDT 24
Finished Jul 23 06:45:57 PM PDT 24
Peak memory 206784 kb
Host smart-d9e8cfd8-0d26-47ee-bfa5-98b4b62f2e65
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2373072074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.2373072074
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.1843779581
Short name T526
Test name
Test status
Simulation time 137914201 ps
CPU time 0.77 seconds
Started Jul 23 06:45:53 PM PDT 24
Finished Jul 23 06:46:01 PM PDT 24
Peak memory 206748 kb
Host smart-b81b448e-6f31-4b30-a184-5526bb0cd540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18437
79581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.1843779581
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.3598330528
Short name T136
Test name
Test status
Simulation time 226497664 ps
CPU time 0.87 seconds
Started Jul 23 06:45:49 PM PDT 24
Finished Jul 23 06:45:57 PM PDT 24
Peak memory 206756 kb
Host smart-64b16a59-f1b4-4f87-b0ba-439afc96d221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35983
30528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.3598330528
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.691791996
Short name T2290
Test name
Test status
Simulation time 184367433 ps
CPU time 0.85 seconds
Started Jul 23 06:45:52 PM PDT 24
Finished Jul 23 06:46:00 PM PDT 24
Peak memory 206768 kb
Host smart-1a9827ef-07ce-4b02-9cb0-3343744badd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69179
1996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.691791996
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.3453457603
Short name T1119
Test name
Test status
Simulation time 177049869 ps
CPU time 0.78 seconds
Started Jul 23 06:45:47 PM PDT 24
Finished Jul 23 06:45:55 PM PDT 24
Peak memory 206652 kb
Host smart-12443a3b-4023-46a5-b1f5-971d9fb12a36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34534
57603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.3453457603
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.1791919265
Short name T602
Test name
Test status
Simulation time 173058837 ps
CPU time 0.79 seconds
Started Jul 23 06:45:55 PM PDT 24
Finished Jul 23 06:46:04 PM PDT 24
Peak memory 206764 kb
Host smart-a115aacf-d15b-4d7a-9187-6f3be8df32f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17919
19265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.1791919265
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.276530954
Short name T2611
Test name
Test status
Simulation time 153769485 ps
CPU time 0.81 seconds
Started Jul 23 06:45:50 PM PDT 24
Finished Jul 23 06:45:57 PM PDT 24
Peak memory 206720 kb
Host smart-814843c3-d35d-4bfd-9bbc-c2227b0e8bad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27653
0954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.276530954
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.1082642636
Short name T1486
Test name
Test status
Simulation time 212595021 ps
CPU time 0.92 seconds
Started Jul 23 06:45:49 PM PDT 24
Finished Jul 23 06:45:56 PM PDT 24
Peak memory 206756 kb
Host smart-e9a40dc0-4101-4e83-889a-88eb943b82dc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1082642636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.1082642636
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.2044191198
Short name T1042
Test name
Test status
Simulation time 147437743 ps
CPU time 0.77 seconds
Started Jul 23 06:45:48 PM PDT 24
Finished Jul 23 06:45:55 PM PDT 24
Peak memory 206740 kb
Host smart-c860a232-207d-4aea-b5ad-66bc02b03b98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20441
91198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.2044191198
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.2299278249
Short name T1101
Test name
Test status
Simulation time 43489925 ps
CPU time 0.68 seconds
Started Jul 23 06:45:49 PM PDT 24
Finished Jul 23 06:46:03 PM PDT 24
Peak memory 206748 kb
Host smart-3da674a6-fdf0-4c29-bb78-8b48c5440cd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22992
78249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.2299278249
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.1851702566
Short name T1664
Test name
Test status
Simulation time 16050674010 ps
CPU time 32.01 seconds
Started Jul 23 06:45:49 PM PDT 24
Finished Jul 23 06:46:28 PM PDT 24
Peak memory 207008 kb
Host smart-db444090-2916-4d13-99be-19f02a49f2b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18517
02566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.1851702566
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.1763436302
Short name T786
Test name
Test status
Simulation time 155029883 ps
CPU time 0.8 seconds
Started Jul 23 06:45:49 PM PDT 24
Finished Jul 23 06:45:57 PM PDT 24
Peak memory 206760 kb
Host smart-ee0a292c-0897-4d19-9c70-178fe41c35e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17634
36302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.1763436302
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.1922433893
Short name T1225
Test name
Test status
Simulation time 179578016 ps
CPU time 0.88 seconds
Started Jul 23 06:45:51 PM PDT 24
Finished Jul 23 06:46:00 PM PDT 24
Peak memory 206780 kb
Host smart-fb31b2cf-d5f4-448f-9a25-0778cee7b92f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19224
33893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.1922433893
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.272650943
Short name T2526
Test name
Test status
Simulation time 217100959 ps
CPU time 0.9 seconds
Started Jul 23 06:45:50 PM PDT 24
Finished Jul 23 06:45:58 PM PDT 24
Peak memory 206780 kb
Host smart-9cd50a7d-f4de-44c8-a453-0f7db85f6bc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27265
0943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.272650943
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.3872719694
Short name T2664
Test name
Test status
Simulation time 181197759 ps
CPU time 0.84 seconds
Started Jul 23 06:45:55 PM PDT 24
Finished Jul 23 06:46:04 PM PDT 24
Peak memory 206692 kb
Host smart-d458fac0-0d38-4840-8511-920c555931f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38727
19694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.3872719694
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.2430265185
Short name T98
Test name
Test status
Simulation time 166120501 ps
CPU time 0.75 seconds
Started Jul 23 06:45:50 PM PDT 24
Finished Jul 23 06:45:58 PM PDT 24
Peak memory 206748 kb
Host smart-4ee6bd6e-361e-4a81-9cf5-abc68b6ecae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24302
65185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.2430265185
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.1247674065
Short name T977
Test name
Test status
Simulation time 209616346 ps
CPU time 0.83 seconds
Started Jul 23 06:45:52 PM PDT 24
Finished Jul 23 06:46:00 PM PDT 24
Peak memory 206768 kb
Host smart-e0aa4f35-1160-415b-ae3a-109d3c2da7f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12476
74065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.1247674065
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.4050309238
Short name T2144
Test name
Test status
Simulation time 193229933 ps
CPU time 0.81 seconds
Started Jul 23 06:45:54 PM PDT 24
Finished Jul 23 06:46:03 PM PDT 24
Peak memory 206760 kb
Host smart-ce725d80-a6d8-4fb2-9106-d949adc92dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40503
09238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.4050309238
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.129033197
Short name T1844
Test name
Test status
Simulation time 253055735 ps
CPU time 0.95 seconds
Started Jul 23 06:45:55 PM PDT 24
Finished Jul 23 06:46:04 PM PDT 24
Peak memory 206660 kb
Host smart-6bd0f596-ec96-4630-9227-4a1706912a82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12903
3197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.129033197
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.4074889380
Short name T1105
Test name
Test status
Simulation time 5882278784 ps
CPU time 55.71 seconds
Started Jul 23 06:45:54 PM PDT 24
Finished Jul 23 06:46:58 PM PDT 24
Peak memory 206912 kb
Host smart-735398a6-900a-41f5-9f83-5adafecbdde8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4074889380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.4074889380
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.2933582975
Short name T1197
Test name
Test status
Simulation time 155967606 ps
CPU time 0.8 seconds
Started Jul 23 06:45:51 PM PDT 24
Finished Jul 23 06:45:59 PM PDT 24
Peak memory 206784 kb
Host smart-a6cc7cfa-1072-4b66-8f96-b4b755298098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29335
82975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.2933582975
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.2356328226
Short name T2429
Test name
Test status
Simulation time 183242922 ps
CPU time 0.82 seconds
Started Jul 23 06:45:52 PM PDT 24
Finished Jul 23 06:46:00 PM PDT 24
Peak memory 206768 kb
Host smart-65b3574a-8b8e-42f5-b19d-73a3aedc3ae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23563
28226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.2356328226
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.1090472327
Short name T1391
Test name
Test status
Simulation time 198967524 ps
CPU time 0.92 seconds
Started Jul 23 06:45:52 PM PDT 24
Finished Jul 23 06:46:01 PM PDT 24
Peak memory 206708 kb
Host smart-71efee23-3b67-43cd-92f8-e09577dea2ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10904
72327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.1090472327
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.1781326933
Short name T2196
Test name
Test status
Simulation time 3130290105 ps
CPU time 85.09 seconds
Started Jul 23 06:45:52 PM PDT 24
Finished Jul 23 06:47:25 PM PDT 24
Peak memory 206960 kb
Host smart-c10c696f-27a7-4bcb-9b94-40f79ae6bd8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17813
26933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.1781326933
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.678739320
Short name T2229
Test name
Test status
Simulation time 41603487 ps
CPU time 0.65 seconds
Started Jul 23 06:38:34 PM PDT 24
Finished Jul 23 06:38:36 PM PDT 24
Peak memory 206744 kb
Host smart-7b5f54d1-0cc8-4d2f-b0dc-163249dda91c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=678739320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.678739320
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.619303565
Short name T1741
Test name
Test status
Simulation time 3661184628 ps
CPU time 4.63 seconds
Started Jul 23 06:38:10 PM PDT 24
Finished Jul 23 06:38:16 PM PDT 24
Peak memory 206860 kb
Host smart-84f37e96-963a-44bb-afc0-b74f4ec5ce67
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=619303565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.619303565
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.1106249143
Short name T2381
Test name
Test status
Simulation time 13365177538 ps
CPU time 12.43 seconds
Started Jul 23 06:38:09 PM PDT 24
Finished Jul 23 06:38:23 PM PDT 24
Peak memory 206764 kb
Host smart-1ee547c6-f095-44f1-8e7c-902b067e98f1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1106249143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.1106249143
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.3109524489
Short name T2019
Test name
Test status
Simulation time 23314066058 ps
CPU time 29.52 seconds
Started Jul 23 06:38:09 PM PDT 24
Finished Jul 23 06:38:41 PM PDT 24
Peak memory 206820 kb
Host smart-d3af2d55-02d9-4737-955c-bdb06bd04f4b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3109524489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.3109524489
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.3917201954
Short name T1710
Test name
Test status
Simulation time 169011326 ps
CPU time 0.83 seconds
Started Jul 23 06:38:13 PM PDT 24
Finished Jul 23 06:38:15 PM PDT 24
Peak memory 206744 kb
Host smart-c06757e6-e771-4afc-9f03-0b20d2d8ce6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39172
01954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.3917201954
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.3521828067
Short name T52
Test name
Test status
Simulation time 185278525 ps
CPU time 0.86 seconds
Started Jul 23 06:38:10 PM PDT 24
Finished Jul 23 06:38:13 PM PDT 24
Peak memory 206756 kb
Host smart-8c8a3f34-f9d2-4ccf-8bf3-cc4cb97a096f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35218
28067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.3521828067
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.1718052462
Short name T67
Test name
Test status
Simulation time 141181548 ps
CPU time 0.83 seconds
Started Jul 23 06:38:12 PM PDT 24
Finished Jul 23 06:38:15 PM PDT 24
Peak memory 206724 kb
Host smart-a5f3e9dd-fed7-40b2-871d-7bb25b950144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17180
52462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.1718052462
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.2535213189
Short name T1263
Test name
Test status
Simulation time 170462908 ps
CPU time 0.85 seconds
Started Jul 23 06:38:08 PM PDT 24
Finished Jul 23 06:38:11 PM PDT 24
Peak memory 206768 kb
Host smart-86e3a552-4ffe-4dc5-b510-6578d68396ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25352
13189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.2535213189
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.2599417985
Short name T1013
Test name
Test status
Simulation time 351777896 ps
CPU time 1.16 seconds
Started Jul 23 06:38:16 PM PDT 24
Finished Jul 23 06:38:18 PM PDT 24
Peak memory 206740 kb
Host smart-41d09fdf-3f2a-4a90-9440-10fd0b25cc61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25994
17985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.2599417985
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.2007594244
Short name T2301
Test name
Test status
Simulation time 670510916 ps
CPU time 1.81 seconds
Started Jul 23 06:38:17 PM PDT 24
Finished Jul 23 06:38:19 PM PDT 24
Peak memory 206740 kb
Host smart-dd78d260-14d5-455f-ae3b-6d5059145346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20075
94244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.2007594244
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.421629230
Short name T1038
Test name
Test status
Simulation time 6261957485 ps
CPU time 12.73 seconds
Started Jul 23 06:38:19 PM PDT 24
Finished Jul 23 06:38:34 PM PDT 24
Peak memory 206988 kb
Host smart-93820b3a-0c73-4946-a8b8-16cb80640657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42162
9230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.421629230
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.944846936
Short name T1990
Test name
Test status
Simulation time 411182168 ps
CPU time 1.22 seconds
Started Jul 23 06:38:18 PM PDT 24
Finished Jul 23 06:38:20 PM PDT 24
Peak memory 206728 kb
Host smart-c6b59406-9170-4828-a10a-51d6efff1084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94484
6936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.944846936
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.1450452888
Short name T1492
Test name
Test status
Simulation time 146246813 ps
CPU time 0.78 seconds
Started Jul 23 06:38:19 PM PDT 24
Finished Jul 23 06:38:21 PM PDT 24
Peak memory 206748 kb
Host smart-f8f90c36-ea69-4891-b137-c7d4a56f7c83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14504
52888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.1450452888
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.359686004
Short name T2050
Test name
Test status
Simulation time 72300210 ps
CPU time 0.72 seconds
Started Jul 23 06:38:19 PM PDT 24
Finished Jul 23 06:38:22 PM PDT 24
Peak memory 206740 kb
Host smart-59d24a15-e53b-4874-8b64-425d255d056c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35968
6004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.359686004
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.1596496952
Short name T762
Test name
Test status
Simulation time 791051308 ps
CPU time 1.92 seconds
Started Jul 23 06:38:19 PM PDT 24
Finished Jul 23 06:38:23 PM PDT 24
Peak memory 206928 kb
Host smart-a80eee2d-6e37-4d5b-9c70-595abaa9c092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15964
96952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.1596496952
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.1214189204
Short name T2257
Test name
Test status
Simulation time 257091814 ps
CPU time 1.89 seconds
Started Jul 23 06:38:20 PM PDT 24
Finished Jul 23 06:38:23 PM PDT 24
Peak memory 206832 kb
Host smart-03e3959d-889d-4e74-8a1d-d30c8427d977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12141
89204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.1214189204
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.1769130856
Short name T1908
Test name
Test status
Simulation time 89174696673 ps
CPU time 118.5 seconds
Started Jul 23 06:38:19 PM PDT 24
Finished Jul 23 06:40:19 PM PDT 24
Peak memory 206912 kb
Host smart-9270d0aa-5b20-4e63-b493-66e8f4ba562e
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1769130856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.1769130856
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.2343694835
Short name T1553
Test name
Test status
Simulation time 107384074574 ps
CPU time 150.56 seconds
Started Jul 23 06:38:21 PM PDT 24
Finished Jul 23 06:40:53 PM PDT 24
Peak memory 206972 kb
Host smart-f477eb74-6b64-4302-b69d-3ce8744e9573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343694835 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.2343694835
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.1808138104
Short name T1683
Test name
Test status
Simulation time 100126000331 ps
CPU time 133.89 seconds
Started Jul 23 06:38:21 PM PDT 24
Finished Jul 23 06:40:37 PM PDT 24
Peak memory 206976 kb
Host smart-d4a37992-f0b8-47da-8a9c-0eec2418df93
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1808138104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.1808138104
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.2908142478
Short name T1976
Test name
Test status
Simulation time 88117334053 ps
CPU time 115.72 seconds
Started Jul 23 06:38:19 PM PDT 24
Finished Jul 23 06:40:16 PM PDT 24
Peak memory 206868 kb
Host smart-57c874a0-94cb-4e23-a434-cf81158f4608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908142478 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.2908142478
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.3183129084
Short name T1135
Test name
Test status
Simulation time 95115114773 ps
CPU time 115.01 seconds
Started Jul 23 06:38:19 PM PDT 24
Finished Jul 23 06:40:15 PM PDT 24
Peak memory 206968 kb
Host smart-ff03f0cf-273b-430a-aa2d-3251b8e31830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31831
29084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.3183129084
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.1161160657
Short name T1377
Test name
Test status
Simulation time 226422514 ps
CPU time 0.89 seconds
Started Jul 23 06:38:19 PM PDT 24
Finished Jul 23 06:38:22 PM PDT 24
Peak memory 206768 kb
Host smart-3476084f-7098-41c2-85c6-8627896f3d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11611
60657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.1161160657
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.105282850
Short name T897
Test name
Test status
Simulation time 148639894 ps
CPU time 0.76 seconds
Started Jul 23 06:38:18 PM PDT 24
Finished Jul 23 06:38:20 PM PDT 24
Peak memory 206756 kb
Host smart-5b70673f-d2c9-41d0-82b9-43e41d425333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10528
2850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.105282850
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.1096383146
Short name T789
Test name
Test status
Simulation time 176276220 ps
CPU time 0.85 seconds
Started Jul 23 06:38:19 PM PDT 24
Finished Jul 23 06:38:22 PM PDT 24
Peak memory 206756 kb
Host smart-5a321889-1fbc-4d15-a3f2-fd4d30d9a14e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10963
83146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.1096383146
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_iso_retraction.1107175213
Short name T1530
Test name
Test status
Simulation time 9594507835 ps
CPU time 29.14 seconds
Started Jul 23 06:38:18 PM PDT 24
Finished Jul 23 06:38:49 PM PDT 24
Peak memory 206948 kb
Host smart-e3463ff9-5e59-4ff8-a93f-907377976e0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11071
75213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.1107175213
Directory /workspace/4.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.2865448240
Short name T867
Test name
Test status
Simulation time 254012906 ps
CPU time 0.87 seconds
Started Jul 23 06:38:21 PM PDT 24
Finished Jul 23 06:38:24 PM PDT 24
Peak memory 206764 kb
Host smart-82cb4bf1-e662-4d62-b7a8-adc49641fd47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28654
48240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.2865448240
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.360689802
Short name T2286
Test name
Test status
Simulation time 23344165823 ps
CPU time 23 seconds
Started Jul 23 06:38:19 PM PDT 24
Finished Jul 23 06:38:44 PM PDT 24
Peak memory 206816 kb
Host smart-426f9412-abb5-4ad0-9e0e-ae14c30f88d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36068
9802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.360689802
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.296018423
Short name T151
Test name
Test status
Simulation time 3295175425 ps
CPU time 4.72 seconds
Started Jul 23 06:38:19 PM PDT 24
Finished Jul 23 06:38:26 PM PDT 24
Peak memory 206808 kb
Host smart-1c9d029f-5b29-4b3f-8361-d4b1a5ab748d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29601
8423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.296018423
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.3460468510
Short name T161
Test name
Test status
Simulation time 9492032115 ps
CPU time 67.65 seconds
Started Jul 23 06:38:21 PM PDT 24
Finished Jul 23 06:39:30 PM PDT 24
Peak memory 206940 kb
Host smart-914eda59-7974-4414-b879-3b1f86d8ad06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34604
68510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.3460468510
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.909000638
Short name T91
Test name
Test status
Simulation time 7136389807 ps
CPU time 51.13 seconds
Started Jul 23 06:38:18 PM PDT 24
Finished Jul 23 06:39:10 PM PDT 24
Peak memory 206956 kb
Host smart-11e72587-94b0-4ac4-9b29-48dfa574551c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=909000638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.909000638
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.820299068
Short name T1750
Test name
Test status
Simulation time 249560656 ps
CPU time 0.95 seconds
Started Jul 23 06:38:19 PM PDT 24
Finished Jul 23 06:38:22 PM PDT 24
Peak memory 206756 kb
Host smart-60c2bad3-e231-4fea-91c5-c755ea3767ff
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=820299068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.820299068
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.2853722912
Short name T1500
Test name
Test status
Simulation time 201956380 ps
CPU time 0.89 seconds
Started Jul 23 06:38:27 PM PDT 24
Finished Jul 23 06:38:29 PM PDT 24
Peak memory 206732 kb
Host smart-6b60dfbb-e9ab-43c4-9d5d-d32b160b519a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28537
22912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.2853722912
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.281470388
Short name T1470
Test name
Test status
Simulation time 5927835541 ps
CPU time 170.91 seconds
Started Jul 23 06:38:30 PM PDT 24
Finished Jul 23 06:41:23 PM PDT 24
Peak memory 206928 kb
Host smart-4386290a-99cb-4832-9f36-dd792252bbb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28147
0388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.281470388
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.3353338804
Short name T1052
Test name
Test status
Simulation time 6841947535 ps
CPU time 69.07 seconds
Started Jul 23 06:38:24 PM PDT 24
Finished Jul 23 06:39:35 PM PDT 24
Peak memory 206908 kb
Host smart-2ae3bdaa-2760-4d88-95a4-3ced0cbd0a54
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3353338804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.3353338804
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.2803904286
Short name T2112
Test name
Test status
Simulation time 167686498 ps
CPU time 0.8 seconds
Started Jul 23 06:38:28 PM PDT 24
Finished Jul 23 06:38:31 PM PDT 24
Peak memory 206768 kb
Host smart-be6915a7-5c99-4c02-906e-3a8cce81c381
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2803904286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.2803904286
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.2587466869
Short name T305
Test name
Test status
Simulation time 183561185 ps
CPU time 0.79 seconds
Started Jul 23 06:38:24 PM PDT 24
Finished Jul 23 06:38:26 PM PDT 24
Peak memory 206932 kb
Host smart-8fee6621-6161-4310-ae83-7b8788131243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25874
66869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.2587466869
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.2648287636
Short name T120
Test name
Test status
Simulation time 178815079 ps
CPU time 0.81 seconds
Started Jul 23 06:38:27 PM PDT 24
Finished Jul 23 06:38:30 PM PDT 24
Peak memory 206784 kb
Host smart-eca80519-8ee4-4737-8d45-f3d969af14f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26482
87636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.2648287636
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.4123148382
Short name T1814
Test name
Test status
Simulation time 169503606 ps
CPU time 0.83 seconds
Started Jul 23 06:38:27 PM PDT 24
Finished Jul 23 06:38:30 PM PDT 24
Peak memory 206736 kb
Host smart-bd4bba4d-b108-4187-9319-f3d15296416c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41231
48382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.4123148382
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.1270269668
Short name T2637
Test name
Test status
Simulation time 151621825 ps
CPU time 0.77 seconds
Started Jul 23 06:38:26 PM PDT 24
Finished Jul 23 06:38:28 PM PDT 24
Peak memory 206760 kb
Host smart-5712d992-8bf4-453e-9547-8e41c99c5e16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12702
69668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.1270269668
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.2223056199
Short name T2634
Test name
Test status
Simulation time 241334739 ps
CPU time 0.85 seconds
Started Jul 23 06:38:24 PM PDT 24
Finished Jul 23 06:38:27 PM PDT 24
Peak memory 206772 kb
Host smart-157004db-66f3-4089-a1db-d583116b5356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22230
56199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.2223056199
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.3785391280
Short name T1725
Test name
Test status
Simulation time 155303849 ps
CPU time 0.8 seconds
Started Jul 23 06:38:24 PM PDT 24
Finished Jul 23 06:38:26 PM PDT 24
Peak memory 206760 kb
Host smart-e32b1e10-72e9-4f2f-aa52-440a24aeab58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37853
91280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.3785391280
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.1454938119
Short name T1631
Test name
Test status
Simulation time 245145672 ps
CPU time 0.98 seconds
Started Jul 23 06:38:26 PM PDT 24
Finished Jul 23 06:38:28 PM PDT 24
Peak memory 206772 kb
Host smart-e8d53647-1be5-478d-983c-6c3b6c24ca44
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1454938119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.1454938119
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.2126168377
Short name T773
Test name
Test status
Simulation time 213859806 ps
CPU time 0.9 seconds
Started Jul 23 06:38:25 PM PDT 24
Finished Jul 23 06:38:27 PM PDT 24
Peak memory 206740 kb
Host smart-32c4332f-2924-4ec6-8931-819d00c28bfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21261
68377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.2126168377
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.3129759429
Short name T837
Test name
Test status
Simulation time 138704769 ps
CPU time 0.85 seconds
Started Jul 23 06:38:28 PM PDT 24
Finished Jul 23 06:38:31 PM PDT 24
Peak memory 206760 kb
Host smart-f8a783d3-e2d3-41d2-abaa-1bef5efc2d39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31297
59429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.3129759429
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.1246344686
Short name T36
Test name
Test status
Simulation time 32556492 ps
CPU time 0.66 seconds
Started Jul 23 06:38:23 PM PDT 24
Finished Jul 23 06:38:25 PM PDT 24
Peak memory 206736 kb
Host smart-95476f79-0286-45f3-beb6-13c8d88df097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12463
44686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.1246344686
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.2587050861
Short name T1913
Test name
Test status
Simulation time 12998268606 ps
CPU time 28.81 seconds
Started Jul 23 06:38:27 PM PDT 24
Finished Jul 23 06:38:57 PM PDT 24
Peak memory 215208 kb
Host smart-aaff4c57-dd92-4ceb-873d-a4522f0dc8d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25870
50861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.2587050861
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.155227755
Short name T2262
Test name
Test status
Simulation time 184395843 ps
CPU time 0.85 seconds
Started Jul 23 06:38:27 PM PDT 24
Finished Jul 23 06:38:29 PM PDT 24
Peak memory 206732 kb
Host smart-0e8d22bd-e7d9-4dce-ae05-15384787a512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15522
7755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.155227755
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.2291136771
Short name T2121
Test name
Test status
Simulation time 178913336 ps
CPU time 0.84 seconds
Started Jul 23 06:38:28 PM PDT 24
Finished Jul 23 06:38:31 PM PDT 24
Peak memory 206760 kb
Host smart-8d8a78a6-920d-46c5-a9a0-224f356ad46a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22911
36771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.2291136771
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.4259291031
Short name T1634
Test name
Test status
Simulation time 10709572189 ps
CPU time 191.59 seconds
Started Jul 23 06:38:25 PM PDT 24
Finished Jul 23 06:41:38 PM PDT 24
Peak memory 206956 kb
Host smart-d9141ce7-3df7-4e11-93e3-719a1a87c1dd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4259291031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.4259291031
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.3451485196
Short name T377
Test name
Test status
Simulation time 202578528 ps
CPU time 0.82 seconds
Started Jul 23 06:38:24 PM PDT 24
Finished Jul 23 06:38:26 PM PDT 24
Peak memory 206720 kb
Host smart-b2c03912-af33-4288-b650-2a9acf97952c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34514
85196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.3451485196
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.3700709835
Short name T949
Test name
Test status
Simulation time 181469392 ps
CPU time 0.86 seconds
Started Jul 23 06:38:24 PM PDT 24
Finished Jul 23 06:38:26 PM PDT 24
Peak memory 206736 kb
Host smart-d371b0aa-dfbe-4ceb-9973-d2f5f59f1c7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37007
09835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.3700709835
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.1368761312
Short name T1959
Test name
Test status
Simulation time 171591141 ps
CPU time 0.78 seconds
Started Jul 23 06:38:27 PM PDT 24
Finished Jul 23 06:38:28 PM PDT 24
Peak memory 206732 kb
Host smart-405a89f8-a294-41a5-a4b4-45a6a2315359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13687
61312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.1368761312
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.2587964100
Short name T78
Test name
Test status
Simulation time 178038968 ps
CPU time 0.8 seconds
Started Jul 23 06:38:31 PM PDT 24
Finished Jul 23 06:38:34 PM PDT 24
Peak memory 206572 kb
Host smart-a4a85208-b346-4921-a480-3d3cebdc080d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25879
64100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.2587964100
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.3587968771
Short name T207
Test name
Test status
Simulation time 1016334004 ps
CPU time 1.87 seconds
Started Jul 23 06:38:35 PM PDT 24
Finished Jul 23 06:38:38 PM PDT 24
Peak memory 225508 kb
Host smart-f4975af1-96e4-4e94-bd13-19abcee41211
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3587968771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.3587968771
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.3945329864
Short name T56
Test name
Test status
Simulation time 486707899 ps
CPU time 1.41 seconds
Started Jul 23 06:38:34 PM PDT 24
Finished Jul 23 06:38:37 PM PDT 24
Peak memory 206772 kb
Host smart-98cc5451-8a4b-47b6-ac7e-cadc9614823f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39453
29864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.3945329864
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.1592836248
Short name T502
Test name
Test status
Simulation time 182921475 ps
CPU time 0.86 seconds
Started Jul 23 06:38:35 PM PDT 24
Finished Jul 23 06:38:37 PM PDT 24
Peak memory 206772 kb
Host smart-2f2ec327-0354-4ac2-ab22-ec19ca77dc0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15928
36248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.1592836248
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.1360182357
Short name T1774
Test name
Test status
Simulation time 159281047 ps
CPU time 0.74 seconds
Started Jul 23 06:38:29 PM PDT 24
Finished Jul 23 06:38:32 PM PDT 24
Peak memory 206752 kb
Host smart-86b70cb1-5a99-4e59-8530-edd4f6c803de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13601
82357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.1360182357
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.2382204904
Short name T2540
Test name
Test status
Simulation time 161869442 ps
CPU time 0.83 seconds
Started Jul 23 06:38:31 PM PDT 24
Finished Jul 23 06:38:34 PM PDT 24
Peak memory 206760 kb
Host smart-0b32c5d5-e243-4742-a4f0-e6688eac4bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23822
04904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.2382204904
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.434129237
Short name T1184
Test name
Test status
Simulation time 245301076 ps
CPU time 0.95 seconds
Started Jul 23 06:38:30 PM PDT 24
Finished Jul 23 06:38:33 PM PDT 24
Peak memory 206740 kb
Host smart-25ed1f40-521a-4ac9-9c26-76078594fe7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43412
9237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.434129237
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.1603064582
Short name T1717
Test name
Test status
Simulation time 4890091366 ps
CPU time 132.79 seconds
Started Jul 23 06:38:35 PM PDT 24
Finished Jul 23 06:40:50 PM PDT 24
Peak memory 206852 kb
Host smart-f84aae0c-b47c-448e-8cab-018c2debdee0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1603064582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.1603064582
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.3211832240
Short name T2230
Test name
Test status
Simulation time 240099310 ps
CPU time 0.89 seconds
Started Jul 23 06:38:29 PM PDT 24
Finished Jul 23 06:38:31 PM PDT 24
Peak memory 206684 kb
Host smart-59f5527c-b05e-49b7-a75b-18e3c92ef349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32118
32240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.3211832240
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.466518420
Short name T414
Test name
Test status
Simulation time 179912192 ps
CPU time 0.79 seconds
Started Jul 23 06:38:31 PM PDT 24
Finished Jul 23 06:38:34 PM PDT 24
Peak memory 206748 kb
Host smart-8101895f-79c7-495e-b7d4-8f236c047252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46651
8420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.466518420
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.4254097934
Short name T410
Test name
Test status
Simulation time 217967906 ps
CPU time 0.93 seconds
Started Jul 23 06:38:29 PM PDT 24
Finished Jul 23 06:38:32 PM PDT 24
Peak memory 206756 kb
Host smart-c55d80d4-5998-4e53-9e43-5accfda12c10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42540
97934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.4254097934
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.2389624556
Short name T2715
Test name
Test status
Simulation time 5001564649 ps
CPU time 48.54 seconds
Started Jul 23 06:38:31 PM PDT 24
Finished Jul 23 06:39:21 PM PDT 24
Peak memory 206964 kb
Host smart-00f79f4b-9e88-46e2-9835-301fc0f46fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23896
24556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.2389624556
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.1689771908
Short name T168
Test name
Test status
Simulation time 14382015170 ps
CPU time 400.75 seconds
Started Jul 23 06:38:34 PM PDT 24
Finished Jul 23 06:45:17 PM PDT 24
Peak memory 207080 kb
Host smart-eabd5849-63ce-42fe-bdff-a6e81d6e3016
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1689771908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.1689771908
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.3875762730
Short name T1283
Test name
Test status
Simulation time 111512319 ps
CPU time 0.73 seconds
Started Jul 23 06:46:28 PM PDT 24
Finished Jul 23 06:46:35 PM PDT 24
Peak memory 206548 kb
Host smart-dfaabcde-f7fb-41f9-b0e5-df1d7be4b435
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3875762730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.3875762730
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.1680324780
Short name T2427
Test name
Test status
Simulation time 4167193154 ps
CPU time 4.66 seconds
Started Jul 23 06:45:59 PM PDT 24
Finished Jul 23 06:46:11 PM PDT 24
Peak memory 206848 kb
Host smart-f28ed20a-a858-4383-b5bb-ef6e4ec0d846
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1680324780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.1680324780
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.1977458303
Short name T2065
Test name
Test status
Simulation time 13362185982 ps
CPU time 12.32 seconds
Started Jul 23 06:45:57 PM PDT 24
Finished Jul 23 06:46:17 PM PDT 24
Peak memory 206824 kb
Host smart-4a970922-ab27-48f7-8deb-263f00dec3e8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1977458303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.1977458303
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.866093765
Short name T1679
Test name
Test status
Simulation time 23286697552 ps
CPU time 24.95 seconds
Started Jul 23 06:45:57 PM PDT 24
Finished Jul 23 06:46:30 PM PDT 24
Peak memory 206812 kb
Host smart-595e5ba8-9b74-4a3e-bf92-4afbdff95228
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=866093765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.866093765
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.3908220733
Short name T2177
Test name
Test status
Simulation time 172558024 ps
CPU time 0.82 seconds
Started Jul 23 06:45:57 PM PDT 24
Finished Jul 23 06:46:06 PM PDT 24
Peak memory 206772 kb
Host smart-3976c5a7-8cef-4880-8e8c-0da529e18c4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39082
20733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.3908220733
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.3126340728
Short name T716
Test name
Test status
Simulation time 145018977 ps
CPU time 0.8 seconds
Started Jul 23 06:45:57 PM PDT 24
Finished Jul 23 06:46:06 PM PDT 24
Peak memory 206768 kb
Host smart-7e5ab20d-79b8-4314-a77a-6a3c91914c6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31263
40728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.3126340728
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.3542807585
Short name T632
Test name
Test status
Simulation time 235470361 ps
CPU time 0.98 seconds
Started Jul 23 06:45:57 PM PDT 24
Finished Jul 23 06:46:06 PM PDT 24
Peak memory 206660 kb
Host smart-bb19fbd5-339e-4107-a047-765d7a302b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35428
07585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.3542807585
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.592550526
Short name T2445
Test name
Test status
Simulation time 869758245 ps
CPU time 2.13 seconds
Started Jul 23 06:45:56 PM PDT 24
Finished Jul 23 06:46:06 PM PDT 24
Peak memory 206856 kb
Host smart-7d1f21eb-01f6-4f0b-9f46-388bdca9f88d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59255
0526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.592550526
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.1155515571
Short name T994
Test name
Test status
Simulation time 16971192847 ps
CPU time 33.37 seconds
Started Jul 23 06:45:55 PM PDT 24
Finished Jul 23 06:46:37 PM PDT 24
Peak memory 206948 kb
Host smart-97c67dd4-3741-40b4-9d7b-63de7518a2b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11555
15571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.1155515571
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.1709509207
Short name T1332
Test name
Test status
Simulation time 414860272 ps
CPU time 1.23 seconds
Started Jul 23 06:46:05 PM PDT 24
Finished Jul 23 06:46:13 PM PDT 24
Peak memory 206748 kb
Host smart-c4b60929-c7aa-4c66-98b0-35c59ff9812a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17095
09207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.1709509207
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.1206760242
Short name T1991
Test name
Test status
Simulation time 143708088 ps
CPU time 0.76 seconds
Started Jul 23 06:45:58 PM PDT 24
Finished Jul 23 06:46:06 PM PDT 24
Peak memory 206748 kb
Host smart-b7f3b3fe-3e3e-4daa-b1a2-bb6cb741a5e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12067
60242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.1206760242
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.1430487887
Short name T1222
Test name
Test status
Simulation time 37367301 ps
CPU time 0.65 seconds
Started Jul 23 06:45:56 PM PDT 24
Finished Jul 23 06:46:05 PM PDT 24
Peak memory 206712 kb
Host smart-7078e005-747f-4c95-a34d-e230f5c4eae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14304
87887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.1430487887
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.4082588019
Short name T2131
Test name
Test status
Simulation time 898354195 ps
CPU time 2.27 seconds
Started Jul 23 06:45:57 PM PDT 24
Finished Jul 23 06:46:07 PM PDT 24
Peak memory 206836 kb
Host smart-5531688f-4af5-4fcd-93d6-933d644fab31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40825
88019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.4082588019
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.3075779112
Short name T1596
Test name
Test status
Simulation time 262245021 ps
CPU time 1.85 seconds
Started Jul 23 06:45:56 PM PDT 24
Finished Jul 23 06:46:06 PM PDT 24
Peak memory 206812 kb
Host smart-d5d1c2f4-f6b4-4445-93b7-30f4d4d4db86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30757
79112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.3075779112
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.775810221
Short name T871
Test name
Test status
Simulation time 276704920 ps
CPU time 0.98 seconds
Started Jul 23 06:45:57 PM PDT 24
Finished Jul 23 06:46:06 PM PDT 24
Peak memory 206720 kb
Host smart-c645d3a6-78d0-4214-9fcf-59c472948b73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77581
0221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.775810221
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.1514826539
Short name T1246
Test name
Test status
Simulation time 168813199 ps
CPU time 0.75 seconds
Started Jul 23 06:45:57 PM PDT 24
Finished Jul 23 06:46:06 PM PDT 24
Peak memory 206772 kb
Host smart-87f0d166-e4ee-4777-b56b-af11f5b07477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15148
26539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.1514826539
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.2406937009
Short name T1753
Test name
Test status
Simulation time 202624529 ps
CPU time 0.82 seconds
Started Jul 23 06:46:00 PM PDT 24
Finished Jul 23 06:46:07 PM PDT 24
Peak memory 206772 kb
Host smart-f7e7191f-3190-4c9e-8e1f-917660ba389c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24069
37009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.2406937009
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_iso_retraction.2432798055
Short name T2247
Test name
Test status
Simulation time 4643831912 ps
CPU time 14.17 seconds
Started Jul 23 06:46:11 PM PDT 24
Finished Jul 23 06:46:29 PM PDT 24
Peak memory 206908 kb
Host smart-7bf50204-df5f-4efb-bfd8-49e3316964ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24327
98055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.2432798055
Directory /workspace/40.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.953816999
Short name T614
Test name
Test status
Simulation time 193120856 ps
CPU time 0.82 seconds
Started Jul 23 06:46:02 PM PDT 24
Finished Jul 23 06:46:10 PM PDT 24
Peak memory 206732 kb
Host smart-1587bf9e-5c04-4f81-9940-48956c26ed3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95381
6999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.953816999
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.3814951326
Short name T1829
Test name
Test status
Simulation time 23328616525 ps
CPU time 22.24 seconds
Started Jul 23 06:45:59 PM PDT 24
Finished Jul 23 06:46:28 PM PDT 24
Peak memory 206796 kb
Host smart-4b5f11e6-b689-45a6-a87c-5565ae232bb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38149
51326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.3814951326
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.3906979162
Short name T382
Test name
Test status
Simulation time 3370094719 ps
CPU time 4.09 seconds
Started Jul 23 06:46:07 PM PDT 24
Finished Jul 23 06:46:17 PM PDT 24
Peak memory 206812 kb
Host smart-1436501c-cc97-4612-81b6-b9b84f60907e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39069
79162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.3906979162
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.2061206601
Short name T651
Test name
Test status
Simulation time 13639848637 ps
CPU time 99.15 seconds
Started Jul 23 06:46:04 PM PDT 24
Finished Jul 23 06:47:50 PM PDT 24
Peak memory 206960 kb
Host smart-a34ad223-8d3a-48bf-ab68-8e9678deb41e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20612
06601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.2061206601
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.1852870216
Short name T1826
Test name
Test status
Simulation time 4053985971 ps
CPU time 112.35 seconds
Started Jul 23 06:46:00 PM PDT 24
Finished Jul 23 06:47:59 PM PDT 24
Peak memory 206912 kb
Host smart-5a2988b8-6103-41f3-93b1-1cbb135d0046
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1852870216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.1852870216
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.3820020087
Short name T445
Test name
Test status
Simulation time 254195794 ps
CPU time 0.94 seconds
Started Jul 23 06:46:02 PM PDT 24
Finished Jul 23 06:46:14 PM PDT 24
Peak memory 206728 kb
Host smart-1ee52101-cb33-436b-bcfb-22d5a4a77d6c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3820020087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.3820020087
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.1786403175
Short name T737
Test name
Test status
Simulation time 194969868 ps
CPU time 0.86 seconds
Started Jul 23 06:46:04 PM PDT 24
Finished Jul 23 06:46:12 PM PDT 24
Peak memory 206728 kb
Host smart-d627d477-7a72-40d6-80db-00537a0f101b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17864
03175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.1786403175
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.1888404615
Short name T379
Test name
Test status
Simulation time 3123908324 ps
CPU time 28.82 seconds
Started Jul 23 06:45:58 PM PDT 24
Finished Jul 23 06:46:34 PM PDT 24
Peak memory 206908 kb
Host smart-859399e4-fb02-4ba0-a4f0-c187980e34a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18884
04615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.1888404615
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.1495712438
Short name T736
Test name
Test status
Simulation time 4698276136 ps
CPU time 31.76 seconds
Started Jul 23 06:46:02 PM PDT 24
Finished Jul 23 06:46:41 PM PDT 24
Peak memory 206896 kb
Host smart-4e8c252f-5f5c-4779-a5be-fc24f5e30c12
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1495712438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.1495712438
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.1952554182
Short name T2179
Test name
Test status
Simulation time 149093965 ps
CPU time 0.84 seconds
Started Jul 23 06:46:04 PM PDT 24
Finished Jul 23 06:46:12 PM PDT 24
Peak memory 206772 kb
Host smart-d4ff4995-cfad-481d-98ea-45a5ae59f108
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1952554182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.1952554182
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.2127718285
Short name T2442
Test name
Test status
Simulation time 157169331 ps
CPU time 0.9 seconds
Started Jul 23 06:46:09 PM PDT 24
Finished Jul 23 06:46:15 PM PDT 24
Peak memory 206744 kb
Host smart-baed5f58-0ce4-4bbb-a8c9-fdcd3e453c88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21277
18285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.2127718285
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.439902192
Short name T2104
Test name
Test status
Simulation time 200629446 ps
CPU time 0.84 seconds
Started Jul 23 06:46:01 PM PDT 24
Finished Jul 23 06:46:08 PM PDT 24
Peak memory 206752 kb
Host smart-0ea0f1ea-bcb5-42b8-b5ec-6a0b2dcdede0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43990
2192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.439902192
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.3845094294
Short name T634
Test name
Test status
Simulation time 174816862 ps
CPU time 0.86 seconds
Started Jul 23 06:46:08 PM PDT 24
Finished Jul 23 06:46:14 PM PDT 24
Peak memory 206728 kb
Host smart-db7bf90c-c9c6-432a-9ce6-c870af93f408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38450
94294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.3845094294
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.3346184737
Short name T1757
Test name
Test status
Simulation time 155152510 ps
CPU time 0.8 seconds
Started Jul 23 06:46:01 PM PDT 24
Finished Jul 23 06:46:08 PM PDT 24
Peak memory 206772 kb
Host smart-0118d9c1-c91f-40ac-b800-eb4303202f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33461
84737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.3346184737
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.1947611483
Short name T480
Test name
Test status
Simulation time 187321410 ps
CPU time 0.86 seconds
Started Jul 23 06:46:04 PM PDT 24
Finished Jul 23 06:46:12 PM PDT 24
Peak memory 206740 kb
Host smart-06a26580-7ff2-4463-aa07-4c13eed938d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19476
11483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.1947611483
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.2533841181
Short name T2415
Test name
Test status
Simulation time 150562249 ps
CPU time 0.78 seconds
Started Jul 23 06:46:06 PM PDT 24
Finished Jul 23 06:46:16 PM PDT 24
Peak memory 206760 kb
Host smart-57dcc84e-bce2-4682-b2a8-4c366c818c30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25338
41181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.2533841181
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.3424446652
Short name T449
Test name
Test status
Simulation time 319757724 ps
CPU time 1 seconds
Started Jul 23 06:46:06 PM PDT 24
Finished Jul 23 06:46:13 PM PDT 24
Peak memory 206776 kb
Host smart-f9e185b2-bb07-46c3-95f0-28e66a3d6017
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3424446652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.3424446652
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.2130682417
Short name T485
Test name
Test status
Simulation time 156247558 ps
CPU time 0.79 seconds
Started Jul 23 06:46:03 PM PDT 24
Finished Jul 23 06:46:10 PM PDT 24
Peak memory 206752 kb
Host smart-961327fa-6220-4949-805c-1d056bc055de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21306
82417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.2130682417
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.3790574690
Short name T605
Test name
Test status
Simulation time 61256539 ps
CPU time 0.68 seconds
Started Jul 23 06:46:03 PM PDT 24
Finished Jul 23 06:46:10 PM PDT 24
Peak memory 206716 kb
Host smart-8f21474d-63f9-4091-8297-3d5f5f5915a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37905
74690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.3790574690
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.62136647
Short name T242
Test name
Test status
Simulation time 23850712000 ps
CPU time 50.6 seconds
Started Jul 23 06:46:16 PM PDT 24
Finished Jul 23 06:47:08 PM PDT 24
Peak memory 207016 kb
Host smart-93f327ec-3a93-4814-8f55-fbb83b767a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62136
647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.62136647
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.3875143291
Short name T1448
Test name
Test status
Simulation time 239253605 ps
CPU time 0.9 seconds
Started Jul 23 06:46:25 PM PDT 24
Finished Jul 23 06:46:28 PM PDT 24
Peak memory 206720 kb
Host smart-8b00e0b1-538e-4123-8709-1b3e7d3194a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38751
43291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.3875143291
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.1093275889
Short name T1218
Test name
Test status
Simulation time 238942395 ps
CPU time 0.93 seconds
Started Jul 23 06:46:04 PM PDT 24
Finished Jul 23 06:46:12 PM PDT 24
Peak memory 206740 kb
Host smart-e1c1adb0-86ec-454d-a303-2c58afceb9be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10932
75889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.1093275889
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.1744168059
Short name T452
Test name
Test status
Simulation time 184886440 ps
CPU time 0.85 seconds
Started Jul 23 06:46:13 PM PDT 24
Finished Jul 23 06:46:17 PM PDT 24
Peak memory 206720 kb
Host smart-195644cf-8d1b-4c22-b0bd-c6dc554a0865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17441
68059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.1744168059
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.1509869303
Short name T481
Test name
Test status
Simulation time 270072254 ps
CPU time 0.96 seconds
Started Jul 23 06:46:13 PM PDT 24
Finished Jul 23 06:46:17 PM PDT 24
Peak memory 206744 kb
Host smart-7ab1c5ef-4da8-4215-91df-5e60d218c0cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15098
69303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.1509869303
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.2489739448
Short name T2503
Test name
Test status
Simulation time 173613475 ps
CPU time 0.8 seconds
Started Jul 23 06:46:04 PM PDT 24
Finished Jul 23 06:46:12 PM PDT 24
Peak memory 206676 kb
Host smart-9a7ac6bc-01f5-4ba7-87c0-c8ddf1b6fb2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24897
39448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.2489739448
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.1587115532
Short name T1212
Test name
Test status
Simulation time 149630545 ps
CPU time 0.79 seconds
Started Jul 23 06:46:07 PM PDT 24
Finished Jul 23 06:46:13 PM PDT 24
Peak memory 206716 kb
Host smart-0680a183-cce5-4dd3-999e-63746e761c48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15871
15532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.1587115532
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.3207320721
Short name T1156
Test name
Test status
Simulation time 155787752 ps
CPU time 0.81 seconds
Started Jul 23 06:46:03 PM PDT 24
Finished Jul 23 06:46:11 PM PDT 24
Peak memory 206764 kb
Host smart-f795cd72-2e8a-47e5-bb58-f626ffc12aa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32073
20721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.3207320721
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.404115314
Short name T373
Test name
Test status
Simulation time 227613265 ps
CPU time 1 seconds
Started Jul 23 06:46:06 PM PDT 24
Finished Jul 23 06:46:13 PM PDT 24
Peak memory 206764 kb
Host smart-44fc3ddc-66ce-409d-b088-188e70dfecac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40411
5314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.404115314
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.3076411551
Short name T2710
Test name
Test status
Simulation time 6619402370 ps
CPU time 58.67 seconds
Started Jul 23 06:46:24 PM PDT 24
Finished Jul 23 06:47:26 PM PDT 24
Peak memory 206888 kb
Host smart-8d33eb80-69bd-4e13-8a96-77a6e4934e3a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3076411551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.3076411551
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.2791940308
Short name T1642
Test name
Test status
Simulation time 206706619 ps
CPU time 0.79 seconds
Started Jul 23 06:46:25 PM PDT 24
Finished Jul 23 06:46:29 PM PDT 24
Peak memory 206732 kb
Host smart-3984ea2f-2011-4eac-9674-3feeed09141d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27919
40308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.2791940308
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.1252898856
Short name T2137
Test name
Test status
Simulation time 159801474 ps
CPU time 0.79 seconds
Started Jul 23 06:46:09 PM PDT 24
Finished Jul 23 06:46:14 PM PDT 24
Peak memory 206724 kb
Host smart-c4a17559-c313-4840-804b-a9c36769a6c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12528
98856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.1252898856
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.4294114625
Short name T1393
Test name
Test status
Simulation time 468312319 ps
CPU time 1.31 seconds
Started Jul 23 06:46:21 PM PDT 24
Finished Jul 23 06:46:24 PM PDT 24
Peak memory 206756 kb
Host smart-4fc2bd26-ae25-4952-8d21-f59c62214a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42941
14625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.4294114625
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.337493543
Short name T1780
Test name
Test status
Simulation time 4777223324 ps
CPU time 43.29 seconds
Started Jul 23 06:46:28 PM PDT 24
Finished Jul 23 06:47:17 PM PDT 24
Peak memory 206788 kb
Host smart-3bf85f90-c61d-443c-b64d-bc3eb7b8bdc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33749
3543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.337493543
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.3587099176
Short name T2392
Test name
Test status
Simulation time 36967990 ps
CPU time 0.69 seconds
Started Jul 23 06:46:34 PM PDT 24
Finished Jul 23 06:46:42 PM PDT 24
Peak memory 206688 kb
Host smart-d71b6570-f12d-4449-a31d-670d36a3a8d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3587099176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.3587099176
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.3572980730
Short name T2315
Test name
Test status
Simulation time 3913991755 ps
CPU time 4.61 seconds
Started Jul 23 06:46:28 PM PDT 24
Finished Jul 23 06:46:39 PM PDT 24
Peak memory 206644 kb
Host smart-3bda1746-7f49-45bc-926e-56d65746be7b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3572980730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.3572980730
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.2970511944
Short name T1338
Test name
Test status
Simulation time 13391958194 ps
CPU time 12.91 seconds
Started Jul 23 06:46:30 PM PDT 24
Finished Jul 23 06:46:49 PM PDT 24
Peak memory 206652 kb
Host smart-27e8ede5-c72d-4b9b-ba2c-f45e8db46975
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2970511944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.2970511944
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.1131637924
Short name T892
Test name
Test status
Simulation time 23311660227 ps
CPU time 23.56 seconds
Started Jul 23 06:46:08 PM PDT 24
Finished Jul 23 06:46:37 PM PDT 24
Peak memory 206824 kb
Host smart-0c53cd39-b865-487b-b0da-edb61e366eee
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1131637924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.1131637924
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.3590761260
Short name T2259
Test name
Test status
Simulation time 214969318 ps
CPU time 0.89 seconds
Started Jul 23 06:46:09 PM PDT 24
Finished Jul 23 06:46:15 PM PDT 24
Peak memory 206752 kb
Host smart-41fc8c1e-ab89-4ac2-9b58-bdb70fb7aa47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35907
61260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.3590761260
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.281956478
Short name T1591
Test name
Test status
Simulation time 148410640 ps
CPU time 0.78 seconds
Started Jul 23 06:46:09 PM PDT 24
Finished Jul 23 06:46:15 PM PDT 24
Peak memory 206772 kb
Host smart-35a2348e-3fc7-48d2-8e7b-74ee66c34da6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28195
6478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.281956478
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.3276567477
Short name T467
Test name
Test status
Simulation time 286184696 ps
CPU time 0.97 seconds
Started Jul 23 06:46:08 PM PDT 24
Finished Jul 23 06:46:14 PM PDT 24
Peak memory 206688 kb
Host smart-1be25224-c6c3-43fc-8f24-8c81be174283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32765
67477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.3276567477
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.3277645833
Short name T2521
Test name
Test status
Simulation time 955591868 ps
CPU time 2.13 seconds
Started Jul 23 06:46:20 PM PDT 24
Finished Jul 23 06:46:23 PM PDT 24
Peak memory 206916 kb
Host smart-11ab1a38-47c3-40c8-bec3-52846c531d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32776
45833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.3277645833
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.41339544
Short name T1768
Test name
Test status
Simulation time 21119333027 ps
CPU time 40.13 seconds
Started Jul 23 06:46:10 PM PDT 24
Finished Jul 23 06:46:54 PM PDT 24
Peak memory 206920 kb
Host smart-82c34a73-f148-42a3-bbb9-44f47459d409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41339
544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.41339544
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.701712126
Short name T1120
Test name
Test status
Simulation time 486411099 ps
CPU time 1.36 seconds
Started Jul 23 06:46:11 PM PDT 24
Finished Jul 23 06:46:16 PM PDT 24
Peak memory 206712 kb
Host smart-713fbb16-3cb4-4a7f-968b-5d60fe02f378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70171
2126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.701712126
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.1431294242
Short name T800
Test name
Test status
Simulation time 194018545 ps
CPU time 0.78 seconds
Started Jul 23 06:46:14 PM PDT 24
Finished Jul 23 06:46:17 PM PDT 24
Peak memory 206772 kb
Host smart-f32874b0-ae0d-4a13-9713-ff359743bfdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14312
94242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.1431294242
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.2241579766
Short name T2314
Test name
Test status
Simulation time 73952105 ps
CPU time 0.7 seconds
Started Jul 23 06:46:28 PM PDT 24
Finished Jul 23 06:46:35 PM PDT 24
Peak memory 206772 kb
Host smart-7a121f0d-ca5e-4194-b672-60f6065c6dd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22415
79766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.2241579766
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.3879021592
Short name T2389
Test name
Test status
Simulation time 940062015 ps
CPU time 2.07 seconds
Started Jul 23 06:46:19 PM PDT 24
Finished Jul 23 06:46:22 PM PDT 24
Peak memory 206832 kb
Host smart-1a381c31-dd48-4c67-aacb-3d96aaff6c89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38790
21592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.3879021592
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.3093172600
Short name T1577
Test name
Test status
Simulation time 159445849 ps
CPU time 1.31 seconds
Started Jul 23 06:46:27 PM PDT 24
Finished Jul 23 06:46:33 PM PDT 24
Peak memory 206856 kb
Host smart-5ceb7038-be41-4957-8f49-171f388e1922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30931
72600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.3093172600
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.97812534
Short name T425
Test name
Test status
Simulation time 168636701 ps
CPU time 0.81 seconds
Started Jul 23 06:46:18 PM PDT 24
Finished Jul 23 06:46:20 PM PDT 24
Peak memory 206728 kb
Host smart-fb3c09cb-ff69-4dec-8525-f6eb7383b41e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97812
534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.97812534
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.2595562391
Short name T1994
Test name
Test status
Simulation time 141684943 ps
CPU time 0.75 seconds
Started Jul 23 06:46:17 PM PDT 24
Finished Jul 23 06:46:19 PM PDT 24
Peak memory 206760 kb
Host smart-7ebdef17-fa98-4fc1-8030-2eb156fb3bb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25955
62391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.2595562391
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.3712873810
Short name T1016
Test name
Test status
Simulation time 205220284 ps
CPU time 0.88 seconds
Started Jul 23 06:46:30 PM PDT 24
Finished Jul 23 06:46:37 PM PDT 24
Peak memory 206744 kb
Host smart-04af0737-e0cc-4801-9776-7db4953057ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37128
73810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.3712873810
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_iso_retraction.1902715638
Short name T95
Test name
Test status
Simulation time 10137856536 ps
CPU time 32.31 seconds
Started Jul 23 06:46:31 PM PDT 24
Finished Jul 23 06:47:10 PM PDT 24
Peak memory 206924 kb
Host smart-52e5cc65-188a-46e7-ad73-b471794b0d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19027
15638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.1902715638
Directory /workspace/41.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.2791441257
Short name T1643
Test name
Test status
Simulation time 224111290 ps
CPU time 0.86 seconds
Started Jul 23 06:46:27 PM PDT 24
Finished Jul 23 06:46:32 PM PDT 24
Peak memory 206768 kb
Host smart-a579c2ba-82ad-497d-bf76-879bc1a1312c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27914
41257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.2791441257
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.195735635
Short name T1456
Test name
Test status
Simulation time 23338796695 ps
CPU time 25.68 seconds
Started Jul 23 06:46:18 PM PDT 24
Finished Jul 23 06:46:44 PM PDT 24
Peak memory 206796 kb
Host smart-a81a79b8-758c-434c-8414-0e2e1624b68c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19573
5635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.195735635
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.2804978566
Short name T2673
Test name
Test status
Simulation time 3332906841 ps
CPU time 4.05 seconds
Started Jul 23 06:46:25 PM PDT 24
Finished Jul 23 06:46:32 PM PDT 24
Peak memory 206820 kb
Host smart-b801e4dc-ce60-4d45-95a8-fa2b69bb922d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28049
78566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.2804978566
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.2107414909
Short name T1406
Test name
Test status
Simulation time 12067583942 ps
CPU time 325.13 seconds
Started Jul 23 06:46:16 PM PDT 24
Finished Jul 23 06:51:43 PM PDT 24
Peak memory 206924 kb
Host smart-c298d40f-0708-4729-801f-866ff2332628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21074
14909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.2107414909
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.3536797944
Short name T1068
Test name
Test status
Simulation time 5846085600 ps
CPU time 148.46 seconds
Started Jul 23 06:46:28 PM PDT 24
Finished Jul 23 06:49:02 PM PDT 24
Peak memory 206904 kb
Host smart-c4af3015-d559-4387-aa1d-0874fb611233
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3536797944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.3536797944
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.1930252012
Short name T2160
Test name
Test status
Simulation time 238318137 ps
CPU time 0.9 seconds
Started Jul 23 06:46:24 PM PDT 24
Finished Jul 23 06:46:27 PM PDT 24
Peak memory 206748 kb
Host smart-9909ab12-1729-400a-8a6a-4d11e9bd2d27
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1930252012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.1930252012
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.1913469953
Short name T809
Test name
Test status
Simulation time 191526722 ps
CPU time 0.9 seconds
Started Jul 23 06:46:27 PM PDT 24
Finished Jul 23 06:46:33 PM PDT 24
Peak memory 206744 kb
Host smart-7a01565e-9a85-4536-a887-fbf58081afe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19134
69953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.1913469953
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.1666642925
Short name T1601
Test name
Test status
Simulation time 3616791293 ps
CPU time 100.19 seconds
Started Jul 23 06:46:20 PM PDT 24
Finished Jul 23 06:48:02 PM PDT 24
Peak memory 206832 kb
Host smart-0a4f3dcc-b1f4-4a03-9473-8aa919f4aec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16666
42925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.1666642925
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.2652856479
Short name T1440
Test name
Test status
Simulation time 3059402773 ps
CPU time 21.53 seconds
Started Jul 23 06:46:28 PM PDT 24
Finished Jul 23 06:46:55 PM PDT 24
Peak memory 206964 kb
Host smart-7b121223-7a62-4e61-b5da-efaf0e79c012
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2652856479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.2652856479
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.3848654511
Short name T332
Test name
Test status
Simulation time 184878478 ps
CPU time 0.79 seconds
Started Jul 23 06:46:31 PM PDT 24
Finished Jul 23 06:46:39 PM PDT 24
Peak memory 206744 kb
Host smart-22add50e-b851-409e-b8fe-5f2bd2d0e426
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3848654511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.3848654511
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.2599465783
Short name T2394
Test name
Test status
Simulation time 163435780 ps
CPU time 0.79 seconds
Started Jul 23 06:46:20 PM PDT 24
Finished Jul 23 06:46:22 PM PDT 24
Peak memory 206736 kb
Host smart-99175084-6bba-41e9-b480-27f90662cb83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25994
65783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.2599465783
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.1163916821
Short name T121
Test name
Test status
Simulation time 196418161 ps
CPU time 0.87 seconds
Started Jul 23 06:46:18 PM PDT 24
Finished Jul 23 06:46:20 PM PDT 24
Peak memory 206704 kb
Host smart-a25469d9-b341-4705-aef9-afcdcd8f0e57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11639
16821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.1163916821
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.3995282406
Short name T104
Test name
Test status
Simulation time 169337483 ps
CPU time 0.83 seconds
Started Jul 23 06:46:25 PM PDT 24
Finished Jul 23 06:46:28 PM PDT 24
Peak memory 206780 kb
Host smart-f95e5a43-a5f6-4db4-9764-e73f49c5a34b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39952
82406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.3995282406
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.1598139430
Short name T856
Test name
Test status
Simulation time 162407252 ps
CPU time 0.78 seconds
Started Jul 23 06:46:32 PM PDT 24
Finished Jul 23 06:46:39 PM PDT 24
Peak memory 206740 kb
Host smart-ab352238-0e46-4161-afa2-5b6e9169f440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15981
39430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.1598139430
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.115170232
Short name T955
Test name
Test status
Simulation time 173594667 ps
CPU time 0.81 seconds
Started Jul 23 06:46:22 PM PDT 24
Finished Jul 23 06:46:25 PM PDT 24
Peak memory 206712 kb
Host smart-87e5b1b4-cb56-4685-bc52-d425fecdddd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11517
0232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.115170232
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.4130296510
Short name T1598
Test name
Test status
Simulation time 187517580 ps
CPU time 0.77 seconds
Started Jul 23 06:46:30 PM PDT 24
Finished Jul 23 06:46:38 PM PDT 24
Peak memory 206584 kb
Host smart-5e388591-a85a-40ad-a2e4-3da738b821cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41302
96510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.4130296510
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.258226380
Short name T392
Test name
Test status
Simulation time 248185299 ps
CPU time 0.99 seconds
Started Jul 23 06:46:33 PM PDT 24
Finished Jul 23 06:46:40 PM PDT 24
Peak memory 206760 kb
Host smart-1711f54f-5610-433d-a230-0a986f0c4ffa
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=258226380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.258226380
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.560444472
Short name T1958
Test name
Test status
Simulation time 180674199 ps
CPU time 0.79 seconds
Started Jul 23 06:46:29 PM PDT 24
Finished Jul 23 06:46:37 PM PDT 24
Peak memory 206760 kb
Host smart-6f8901eb-80c4-4e59-b900-6e4fb94072bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56044
4472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.560444472
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.3182995903
Short name T827
Test name
Test status
Simulation time 83452725 ps
CPU time 0.71 seconds
Started Jul 23 06:46:29 PM PDT 24
Finished Jul 23 06:46:37 PM PDT 24
Peak memory 206736 kb
Host smart-0b486a57-dd56-49a4-8f94-501990951684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31829
95903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.3182995903
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.2786957834
Short name T2615
Test name
Test status
Simulation time 13986446682 ps
CPU time 30.39 seconds
Started Jul 23 06:46:27 PM PDT 24
Finished Jul 23 06:47:02 PM PDT 24
Peak memory 215116 kb
Host smart-132849f5-c3ca-4f9b-b31b-0146d561ccee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27869
57834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.2786957834
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.4148193718
Short name T942
Test name
Test status
Simulation time 227107462 ps
CPU time 0.9 seconds
Started Jul 23 06:46:26 PM PDT 24
Finished Jul 23 06:46:30 PM PDT 24
Peak memory 206720 kb
Host smart-d517bf13-216c-4e05-aeff-ac2298dcfc97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41481
93718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.4148193718
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.2528319272
Short name T1362
Test name
Test status
Simulation time 255079020 ps
CPU time 0.88 seconds
Started Jul 23 06:46:32 PM PDT 24
Finished Jul 23 06:46:39 PM PDT 24
Peak memory 206740 kb
Host smart-576e80e3-ab2e-40aa-bf4c-e2e595278c40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25283
19272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.2528319272
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.675213443
Short name T1321
Test name
Test status
Simulation time 195940607 ps
CPU time 0.85 seconds
Started Jul 23 06:46:28 PM PDT 24
Finished Jul 23 06:46:35 PM PDT 24
Peak memory 206764 kb
Host smart-dfc981a9-12e6-4130-a126-e6cab5a7e96b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67521
3443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.675213443
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.2851187514
Short name T2687
Test name
Test status
Simulation time 163736709 ps
CPU time 0.83 seconds
Started Jul 23 06:46:30 PM PDT 24
Finished Jul 23 06:46:38 PM PDT 24
Peak memory 206724 kb
Host smart-3c5c0efd-a6f1-4944-8968-eda2ff51838e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28511
87514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.2851187514
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.2893339132
Short name T2088
Test name
Test status
Simulation time 152098387 ps
CPU time 0.79 seconds
Started Jul 23 06:46:26 PM PDT 24
Finished Jul 23 06:46:32 PM PDT 24
Peak memory 206756 kb
Host smart-8bd6f8e9-bf35-4e87-bf78-ce9d01558061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28933
39132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.2893339132
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.3699639822
Short name T674
Test name
Test status
Simulation time 153422714 ps
CPU time 0.76 seconds
Started Jul 23 06:46:24 PM PDT 24
Finished Jul 23 06:46:28 PM PDT 24
Peak memory 206752 kb
Host smart-9da2da71-83f8-475b-bc86-4c47d1f63cde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36996
39822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.3699639822
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.3502073661
Short name T1933
Test name
Test status
Simulation time 159091593 ps
CPU time 0.8 seconds
Started Jul 23 06:46:38 PM PDT 24
Finished Jul 23 06:46:51 PM PDT 24
Peak memory 206752 kb
Host smart-de4271c9-8851-447a-8567-44cc0c9b1907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35020
73661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.3502073661
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.2683896960
Short name T471
Test name
Test status
Simulation time 224437549 ps
CPU time 0.89 seconds
Started Jul 23 06:46:20 PM PDT 24
Finished Jul 23 06:46:23 PM PDT 24
Peak memory 206788 kb
Host smart-7ea9eec0-be35-4a70-b3bc-36810b5ab125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26838
96960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.2683896960
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.3669052471
Short name T2505
Test name
Test status
Simulation time 4617904327 ps
CPU time 120.35 seconds
Started Jul 23 06:46:29 PM PDT 24
Finished Jul 23 06:48:36 PM PDT 24
Peak memory 206908 kb
Host smart-254ccdd9-8df3-488d-8746-7176e9e60e54
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3669052471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.3669052471
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.2360840078
Short name T1527
Test name
Test status
Simulation time 150046939 ps
CPU time 0.78 seconds
Started Jul 23 06:46:25 PM PDT 24
Finished Jul 23 06:46:28 PM PDT 24
Peak memory 206736 kb
Host smart-483d9d56-0464-41a5-bf8f-631264271acf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23608
40078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.2360840078
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.3887828046
Short name T1561
Test name
Test status
Simulation time 166204108 ps
CPU time 0.79 seconds
Started Jul 23 06:46:30 PM PDT 24
Finished Jul 23 06:46:37 PM PDT 24
Peak memory 206740 kb
Host smart-eb37f8a8-f98b-44b7-9d42-c0f132f07f95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38878
28046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.3887828046
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.3549010315
Short name T2588
Test name
Test status
Simulation time 822892215 ps
CPU time 1.85 seconds
Started Jul 23 06:46:27 PM PDT 24
Finished Jul 23 06:46:34 PM PDT 24
Peak memory 206904 kb
Host smart-2527a977-6665-4bf5-82b0-c5fb3ad99ed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35490
10315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.3549010315
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.998619800
Short name T1619
Test name
Test status
Simulation time 5430381153 ps
CPU time 148.7 seconds
Started Jul 23 06:46:23 PM PDT 24
Finished Jul 23 06:48:53 PM PDT 24
Peak memory 206896 kb
Host smart-d9d16840-84f8-469b-ac34-50bc83c32661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99861
9800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.998619800
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.2967356211
Short name T2044
Test name
Test status
Simulation time 44551371 ps
CPU time 0.68 seconds
Started Jul 23 06:46:39 PM PDT 24
Finished Jul 23 06:46:46 PM PDT 24
Peak memory 206748 kb
Host smart-de5f361b-b8fb-4669-a8ed-465e9cfb3f18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2967356211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.2967356211
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.2984170218
Short name T1945
Test name
Test status
Simulation time 4003840135 ps
CPU time 5.95 seconds
Started Jul 23 06:46:28 PM PDT 24
Finished Jul 23 06:46:39 PM PDT 24
Peak memory 206832 kb
Host smart-eb861fd9-6417-4635-b6ce-74e944cdeb01
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2984170218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.2984170218
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.930370617
Short name T764
Test name
Test status
Simulation time 13400876032 ps
CPU time 14.06 seconds
Started Jul 23 06:46:32 PM PDT 24
Finished Jul 23 06:46:53 PM PDT 24
Peak memory 206940 kb
Host smart-b50ec563-0d10-4eb9-8b0f-6e574db995ec
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=930370617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.930370617
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.1333580221
Short name T182
Test name
Test status
Simulation time 23372570138 ps
CPU time 22.42 seconds
Started Jul 23 06:46:31 PM PDT 24
Finished Jul 23 06:47:00 PM PDT 24
Peak memory 206812 kb
Host smart-fe464ace-78a6-4e5d-91f0-75d1f9b4cc2e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1333580221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.1333580221
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.4065338545
Short name T904
Test name
Test status
Simulation time 172431030 ps
CPU time 0.78 seconds
Started Jul 23 06:46:29 PM PDT 24
Finished Jul 23 06:46:36 PM PDT 24
Peak memory 206760 kb
Host smart-68f580c7-681d-4202-98a8-0b0c06806df3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40653
38545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.4065338545
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.4078264538
Short name T1969
Test name
Test status
Simulation time 141808868 ps
CPU time 0.77 seconds
Started Jul 23 06:46:38 PM PDT 24
Finished Jul 23 06:46:45 PM PDT 24
Peak memory 206780 kb
Host smart-d99073c4-905f-47a3-9753-d39b97548298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40782
64538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.4078264538
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.2643266142
Short name T981
Test name
Test status
Simulation time 533803626 ps
CPU time 1.69 seconds
Started Jul 23 06:46:29 PM PDT 24
Finished Jul 23 06:46:36 PM PDT 24
Peak memory 206824 kb
Host smart-acc60c4d-4ea8-4f1e-adcc-e7f96e32e2ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26432
66142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.2643266142
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.3921672435
Short name T1371
Test name
Test status
Simulation time 673281124 ps
CPU time 1.52 seconds
Started Jul 23 06:46:31 PM PDT 24
Finished Jul 23 06:46:39 PM PDT 24
Peak memory 206772 kb
Host smart-9dbee2e2-217d-4bbe-b159-099cd493943d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39216
72435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.3921672435
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.4139493930
Short name T2477
Test name
Test status
Simulation time 438915854 ps
CPU time 1.22 seconds
Started Jul 23 06:46:38 PM PDT 24
Finished Jul 23 06:46:46 PM PDT 24
Peak memory 206740 kb
Host smart-4a5714e4-f101-4e38-925d-e9b61bd5f231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41394
93930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.4139493930
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.2260907002
Short name T323
Test name
Test status
Simulation time 150497561 ps
CPU time 0.78 seconds
Started Jul 23 06:46:29 PM PDT 24
Finished Jul 23 06:46:36 PM PDT 24
Peak memory 206760 kb
Host smart-875d75a2-08a4-4553-9b20-ebe13ad49499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22609
07002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.2260907002
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.4173459923
Short name T2682
Test name
Test status
Simulation time 45501646 ps
CPU time 0.66 seconds
Started Jul 23 06:46:45 PM PDT 24
Finished Jul 23 06:46:52 PM PDT 24
Peak memory 206740 kb
Host smart-d9755b80-2b4f-4926-91fd-d05949bc096f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41734
59923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.4173459923
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.2259819422
Short name T519
Test name
Test status
Simulation time 1015154090 ps
CPU time 2.27 seconds
Started Jul 23 06:46:36 PM PDT 24
Finished Jul 23 06:46:44 PM PDT 24
Peak memory 206896 kb
Host smart-b6c4e174-db62-4db2-9394-a1d5c1c4a906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22598
19422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.2259819422
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.3101788277
Short name T1461
Test name
Test status
Simulation time 230436761 ps
CPU time 1.52 seconds
Started Jul 23 06:46:33 PM PDT 24
Finished Jul 23 06:46:42 PM PDT 24
Peak memory 206804 kb
Host smart-b96831c0-3639-4c1b-99b9-e92dfaf7f12b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31017
88277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.3101788277
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.351512748
Short name T2356
Test name
Test status
Simulation time 205013596 ps
CPU time 0.91 seconds
Started Jul 23 06:46:31 PM PDT 24
Finished Jul 23 06:46:39 PM PDT 24
Peak memory 206764 kb
Host smart-6e61e551-f325-47c1-b435-52ac2395d15e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35151
2748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.351512748
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.1955897850
Short name T580
Test name
Test status
Simulation time 183780652 ps
CPU time 0.77 seconds
Started Jul 23 06:46:32 PM PDT 24
Finished Jul 23 06:46:39 PM PDT 24
Peak memory 206760 kb
Host smart-0d9a3ee8-9a72-4535-88e1-da8c43b44b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19558
97850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.1955897850
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.1098977527
Short name T945
Test name
Test status
Simulation time 202382782 ps
CPU time 0.85 seconds
Started Jul 23 06:46:34 PM PDT 24
Finished Jul 23 06:46:42 PM PDT 24
Peak memory 206776 kb
Host smart-44fa0346-c1f3-4d4f-a8ec-d8cc0ec9afd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10989
77527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.1098977527
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.3853917222
Short name T2028
Test name
Test status
Simulation time 9641186566 ps
CPU time 275.06 seconds
Started Jul 23 06:46:37 PM PDT 24
Finished Jul 23 06:51:18 PM PDT 24
Peak memory 206896 kb
Host smart-6e766c4d-758a-4e33-b509-bb2971ac9327
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3853917222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.3853917222
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_iso_retraction.4242890011
Short name T803
Test name
Test status
Simulation time 4029625602 ps
CPU time 37.38 seconds
Started Jul 23 06:46:32 PM PDT 24
Finished Jul 23 06:47:17 PM PDT 24
Peak memory 206812 kb
Host smart-f245f415-003c-4d6d-bb9f-086b7d50b167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42428
90011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_iso_retraction.4242890011
Directory /workspace/42.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.1254450562
Short name T441
Test name
Test status
Simulation time 194018846 ps
CPU time 0.82 seconds
Started Jul 23 06:46:46 PM PDT 24
Finished Jul 23 06:46:54 PM PDT 24
Peak memory 206768 kb
Host smart-d1a161b2-458e-404d-865d-bd4a89e7aa96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12544
50562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.1254450562
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.482698476
Short name T2692
Test name
Test status
Simulation time 23303094815 ps
CPU time 23.06 seconds
Started Jul 23 06:46:36 PM PDT 24
Finished Jul 23 06:47:05 PM PDT 24
Peak memory 206808 kb
Host smart-9fda8237-a812-4ce9-a2e3-e62fd506fb7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48269
8476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.482698476
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.1407528772
Short name T1687
Test name
Test status
Simulation time 3334314621 ps
CPU time 4.29 seconds
Started Jul 23 06:46:32 PM PDT 24
Finished Jul 23 06:46:43 PM PDT 24
Peak memory 206808 kb
Host smart-97fe828f-95b4-4576-9f73-a8ab1babae78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14075
28772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.1407528772
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.2372829070
Short name T1073
Test name
Test status
Simulation time 13985242978 ps
CPU time 395.71 seconds
Started Jul 23 06:46:31 PM PDT 24
Finished Jul 23 06:53:14 PM PDT 24
Peak memory 206988 kb
Host smart-d77aea88-e389-433f-9527-12dcef5307c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23728
29070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.2372829070
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.2850086557
Short name T1749
Test name
Test status
Simulation time 6674124809 ps
CPU time 47.15 seconds
Started Jul 23 06:46:31 PM PDT 24
Finished Jul 23 06:47:25 PM PDT 24
Peak memory 206960 kb
Host smart-a0097eea-c599-49fe-927e-37a9a4fa9a3a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2850086557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.2850086557
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.2294042234
Short name T1775
Test name
Test status
Simulation time 244397921 ps
CPU time 0.92 seconds
Started Jul 23 06:46:38 PM PDT 24
Finished Jul 23 06:46:46 PM PDT 24
Peak memory 206784 kb
Host smart-1afad937-3ee0-436e-bfd8-1b1d9cc5e6e9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2294042234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.2294042234
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.2619325664
Short name T529
Test name
Test status
Simulation time 195494654 ps
CPU time 0.91 seconds
Started Jul 23 06:46:32 PM PDT 24
Finished Jul 23 06:46:40 PM PDT 24
Peak memory 206688 kb
Host smart-7198d06b-4b81-4f34-97df-450a43cc3937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26193
25664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.2619325664
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.2377361849
Short name T2534
Test name
Test status
Simulation time 6069904121 ps
CPU time 158.6 seconds
Started Jul 23 06:46:38 PM PDT 24
Finished Jul 23 06:49:22 PM PDT 24
Peak memory 206936 kb
Host smart-a0d18318-06cf-48f7-ace2-2d75b282003f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23773
61849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.2377361849
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.118936769
Short name T597
Test name
Test status
Simulation time 7990167039 ps
CPU time 58.83 seconds
Started Jul 23 06:46:34 PM PDT 24
Finished Jul 23 06:47:40 PM PDT 24
Peak memory 206960 kb
Host smart-ca1295f3-617b-48cd-a1bb-637bced53a70
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=118936769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.118936769
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.3495001543
Short name T799
Test name
Test status
Simulation time 167812671 ps
CPU time 0.79 seconds
Started Jul 23 06:46:33 PM PDT 24
Finished Jul 23 06:46:41 PM PDT 24
Peak memory 206740 kb
Host smart-cf5d281c-c535-439d-a86d-2a2fba405de3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3495001543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.3495001543
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.2510712062
Short name T2287
Test name
Test status
Simulation time 147296212 ps
CPU time 0.77 seconds
Started Jul 23 06:46:30 PM PDT 24
Finished Jul 23 06:46:37 PM PDT 24
Peak memory 206680 kb
Host smart-da42a84d-2364-4db8-8cd3-2dda80d9e73b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25107
12062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.2510712062
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.324012990
Short name T1980
Test name
Test status
Simulation time 236299832 ps
CPU time 0.92 seconds
Started Jul 23 06:46:45 PM PDT 24
Finished Jul 23 06:46:52 PM PDT 24
Peak memory 206780 kb
Host smart-be6ee652-3863-41a6-be53-b23cff16e046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32401
2990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.324012990
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.378254280
Short name T1960
Test name
Test status
Simulation time 159553120 ps
CPU time 0.78 seconds
Started Jul 23 06:46:38 PM PDT 24
Finished Jul 23 06:46:45 PM PDT 24
Peak memory 206736 kb
Host smart-1801d151-fe75-4018-834e-a693269b7f9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37825
4280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.378254280
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.3959624302
Short name T268
Test name
Test status
Simulation time 185567465 ps
CPU time 0.88 seconds
Started Jul 23 06:46:38 PM PDT 24
Finished Jul 23 06:46:44 PM PDT 24
Peak memory 206752 kb
Host smart-dcbd8c15-850f-4891-98c9-449fbd695a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39596
24302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.3959624302
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.1269743374
Short name T1423
Test name
Test status
Simulation time 164952648 ps
CPU time 0.8 seconds
Started Jul 23 06:46:41 PM PDT 24
Finished Jul 23 06:46:48 PM PDT 24
Peak memory 206584 kb
Host smart-2241b8bf-4073-4eaf-945b-618c458843b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12697
43374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.1269743374
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.1878153389
Short name T1676
Test name
Test status
Simulation time 171528043 ps
CPU time 0.84 seconds
Started Jul 23 06:46:40 PM PDT 24
Finished Jul 23 06:46:47 PM PDT 24
Peak memory 206760 kb
Host smart-a2d9a447-2f77-452d-bc93-ec23f7755c62
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1878153389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.1878153389
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.1062076072
Short name T909
Test name
Test status
Simulation time 140706547 ps
CPU time 0.76 seconds
Started Jul 23 06:46:42 PM PDT 24
Finished Jul 23 06:46:49 PM PDT 24
Peak memory 206652 kb
Host smart-afc12f50-3798-43fd-b0aa-9076bfe60a3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10620
76072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.1062076072
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.188480852
Short name T26
Test name
Test status
Simulation time 53957266 ps
CPU time 0.68 seconds
Started Jul 23 06:46:40 PM PDT 24
Finished Jul 23 06:46:47 PM PDT 24
Peak memory 206744 kb
Host smart-c22f5309-675a-4f08-901b-7cecbfc5c4ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18848
0852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.188480852
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.3758339262
Short name T2213
Test name
Test status
Simulation time 19982874014 ps
CPU time 44.44 seconds
Started Jul 23 06:46:44 PM PDT 24
Finished Jul 23 06:47:35 PM PDT 24
Peak memory 206980 kb
Host smart-43232bd7-c51d-4656-ad1e-c32e11c15a9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37583
39262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.3758339262
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.2236280601
Short name T345
Test name
Test status
Simulation time 208527622 ps
CPU time 0.86 seconds
Started Jul 23 06:46:42 PM PDT 24
Finished Jul 23 06:46:49 PM PDT 24
Peak memory 206748 kb
Host smart-9e7b099f-d25a-4d9f-8a39-6e14d2b23bdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22362
80601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.2236280601
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.605423760
Short name T661
Test name
Test status
Simulation time 162677819 ps
CPU time 0.82 seconds
Started Jul 23 06:46:38 PM PDT 24
Finished Jul 23 06:46:44 PM PDT 24
Peak memory 206760 kb
Host smart-15ad5201-3186-4064-8a00-02fa6945bacb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60542
3760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.605423760
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.918215935
Short name T1041
Test name
Test status
Simulation time 227310413 ps
CPU time 0.89 seconds
Started Jul 23 06:46:38 PM PDT 24
Finished Jul 23 06:46:45 PM PDT 24
Peak memory 206756 kb
Host smart-6bdc7ddc-06ae-46bb-b4f0-a266dd57507b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91821
5935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.918215935
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.3604353616
Short name T2200
Test name
Test status
Simulation time 163394769 ps
CPU time 0.81 seconds
Started Jul 23 06:46:38 PM PDT 24
Finished Jul 23 06:46:44 PM PDT 24
Peak memory 206740 kb
Host smart-bc13964f-206e-451e-ad88-7434d51b4f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36043
53616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.3604353616
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.634639639
Short name T2053
Test name
Test status
Simulation time 196145066 ps
CPU time 0.84 seconds
Started Jul 23 06:46:38 PM PDT 24
Finished Jul 23 06:46:45 PM PDT 24
Peak memory 206720 kb
Host smart-e31dcba7-8073-406e-9a02-5852f409b9e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63463
9639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.634639639
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.768423084
Short name T2352
Test name
Test status
Simulation time 167302456 ps
CPU time 0.77 seconds
Started Jul 23 06:46:42 PM PDT 24
Finished Jul 23 06:46:49 PM PDT 24
Peak memory 206756 kb
Host smart-c374c814-bef2-4bf2-9976-f01875cb9007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76842
3084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.768423084
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.290575014
Short name T346
Test name
Test status
Simulation time 151787943 ps
CPU time 0.78 seconds
Started Jul 23 06:46:38 PM PDT 24
Finished Jul 23 06:46:45 PM PDT 24
Peak memory 206756 kb
Host smart-51506c6c-3702-414c-a25a-fb5846d06340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29057
5014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.290575014
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.1668345330
Short name T2317
Test name
Test status
Simulation time 285807382 ps
CPU time 1 seconds
Started Jul 23 06:46:38 PM PDT 24
Finished Jul 23 06:46:45 PM PDT 24
Peak memory 206776 kb
Host smart-babe0231-39a1-42b1-be5d-c0b6a742438c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16683
45330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.1668345330
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.1266440590
Short name T1692
Test name
Test status
Simulation time 5118991511 ps
CPU time 132.88 seconds
Started Jul 23 06:46:38 PM PDT 24
Finished Jul 23 06:48:57 PM PDT 24
Peak memory 206812 kb
Host smart-bca893c8-e5d7-40b2-931f-3409ce2a7ecf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1266440590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.1266440590
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.2702042096
Short name T2681
Test name
Test status
Simulation time 176351954 ps
CPU time 0.8 seconds
Started Jul 23 06:46:40 PM PDT 24
Finished Jul 23 06:46:47 PM PDT 24
Peak memory 206752 kb
Host smart-fd6bd47e-4593-4f85-a295-ef332d18a3c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27020
42096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.2702042096
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.2709904244
Short name T1011
Test name
Test status
Simulation time 182171885 ps
CPU time 0.79 seconds
Started Jul 23 06:46:41 PM PDT 24
Finished Jul 23 06:46:48 PM PDT 24
Peak memory 206752 kb
Host smart-5fd03598-e108-489f-b6b2-56e0ee2d4033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27099
04244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.2709904244
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.1676221254
Short name T1172
Test name
Test status
Simulation time 693255292 ps
CPU time 1.58 seconds
Started Jul 23 06:46:39 PM PDT 24
Finished Jul 23 06:46:47 PM PDT 24
Peak memory 206892 kb
Host smart-12e9c45c-23f9-442f-b0df-d178d58f39ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16762
21254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.1676221254
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.2872392982
Short name T1733
Test name
Test status
Simulation time 5007607803 ps
CPU time 141.92 seconds
Started Jul 23 06:46:38 PM PDT 24
Finished Jul 23 06:49:06 PM PDT 24
Peak memory 206908 kb
Host smart-b0c2c836-ee00-4c51-a5a7-a192ef39a748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28723
92982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.2872392982
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.1388136250
Short name T2250
Test name
Test status
Simulation time 56241854 ps
CPU time 0.7 seconds
Started Jul 23 06:47:03 PM PDT 24
Finished Jul 23 06:47:07 PM PDT 24
Peak memory 206744 kb
Host smart-67951a8a-f706-4109-a5dc-24d33c364dd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1388136250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.1388136250
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.2154400268
Short name T1609
Test name
Test status
Simulation time 4166438272 ps
CPU time 5.72 seconds
Started Jul 23 06:46:46 PM PDT 24
Finished Jul 23 06:46:58 PM PDT 24
Peak memory 206828 kb
Host smart-09d3d747-7383-45ab-8f3c-48519332eb8b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2154400268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.2154400268
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.2431302994
Short name T183
Test name
Test status
Simulation time 13357275720 ps
CPU time 13.66 seconds
Started Jul 23 06:46:48 PM PDT 24
Finished Jul 23 06:47:07 PM PDT 24
Peak memory 206760 kb
Host smart-e57b3465-6d4c-4c7d-af7c-316caf55ebee
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2431302994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.2431302994
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.3533138361
Short name T1614
Test name
Test status
Simulation time 23349683073 ps
CPU time 22.37 seconds
Started Jul 23 06:46:45 PM PDT 24
Finished Jul 23 06:47:13 PM PDT 24
Peak memory 206908 kb
Host smart-7b4226f7-ab62-4363-9ac6-87df02cfc66b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3533138361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.3533138361
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.337262375
Short name T1326
Test name
Test status
Simulation time 157787902 ps
CPU time 0.81 seconds
Started Jul 23 06:46:43 PM PDT 24
Finished Jul 23 06:46:50 PM PDT 24
Peak memory 206728 kb
Host smart-ae73c52a-7813-4cc2-a132-27d073e3c925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33726
2375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.337262375
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.3676913236
Short name T735
Test name
Test status
Simulation time 165821931 ps
CPU time 0.79 seconds
Started Jul 23 06:46:48 PM PDT 24
Finished Jul 23 06:46:54 PM PDT 24
Peak memory 206720 kb
Host smart-bcb0109a-4ab8-4526-be8a-869cf4b3a1e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36769
13236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.3676913236
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.1967289569
Short name T2274
Test name
Test status
Simulation time 634296736 ps
CPU time 1.75 seconds
Started Jul 23 06:46:50 PM PDT 24
Finished Jul 23 06:46:57 PM PDT 24
Peak memory 206836 kb
Host smart-3ff0d5ed-31c0-483f-aea1-7e532371ae34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19672
89569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.1967289569
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.2082737235
Short name T1845
Test name
Test status
Simulation time 985399349 ps
CPU time 2.2 seconds
Started Jul 23 06:46:46 PM PDT 24
Finished Jul 23 06:46:55 PM PDT 24
Peak memory 206860 kb
Host smart-7fbb9299-f317-4f5f-bdd1-d1a9e44ea9dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20827
37235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.2082737235
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.2141804193
Short name T1656
Test name
Test status
Simulation time 20936532535 ps
CPU time 39.65 seconds
Started Jul 23 06:46:46 PM PDT 24
Finished Jul 23 06:47:32 PM PDT 24
Peak memory 206932 kb
Host smart-80c26ba3-8f61-495d-bf2f-878800e8713a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21418
04193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.2141804193
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.783357034
Short name T556
Test name
Test status
Simulation time 377565169 ps
CPU time 1.24 seconds
Started Jul 23 06:46:51 PM PDT 24
Finished Jul 23 06:46:58 PM PDT 24
Peak memory 206764 kb
Host smart-be84822b-92d1-4882-a3d4-34ee59b2a464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78335
7034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.783357034
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.553291043
Short name T1100
Test name
Test status
Simulation time 156661502 ps
CPU time 0.79 seconds
Started Jul 23 06:46:44 PM PDT 24
Finished Jul 23 06:46:52 PM PDT 24
Peak memory 206760 kb
Host smart-17e4d077-d284-4b22-98a2-1ec11e1bf0b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55329
1043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.553291043
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.505507421
Short name T2327
Test name
Test status
Simulation time 34963030 ps
CPU time 0.67 seconds
Started Jul 23 06:46:49 PM PDT 24
Finished Jul 23 06:46:56 PM PDT 24
Peak memory 206756 kb
Host smart-4cb612bf-6cb8-4a8b-b7ad-5ea5384d0f66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50550
7421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.505507421
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.184838477
Short name T82
Test name
Test status
Simulation time 1000682039 ps
CPU time 2.35 seconds
Started Jul 23 06:46:46 PM PDT 24
Finished Jul 23 06:46:54 PM PDT 24
Peak memory 206900 kb
Host smart-dd0b03cc-0134-43b1-844a-7dda59fd4d8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18483
8477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.184838477
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.156403484
Short name T1436
Test name
Test status
Simulation time 315146934 ps
CPU time 2.24 seconds
Started Jul 23 06:46:45 PM PDT 24
Finished Jul 23 06:46:54 PM PDT 24
Peak memory 206884 kb
Host smart-52908ca9-d242-4482-bc90-d4be686398a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15640
3484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.156403484
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.4037257388
Short name T672
Test name
Test status
Simulation time 201145976 ps
CPU time 0.87 seconds
Started Jul 23 06:46:52 PM PDT 24
Finished Jul 23 06:46:58 PM PDT 24
Peak memory 206752 kb
Host smart-a8c9ffcf-0065-41bd-9b38-83f68d1faa2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40372
57388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.4037257388
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.296318940
Short name T213
Test name
Test status
Simulation time 148507618 ps
CPU time 0.81 seconds
Started Jul 23 06:46:46 PM PDT 24
Finished Jul 23 06:46:53 PM PDT 24
Peak memory 206680 kb
Host smart-73462d69-7b58-4295-8612-2b48b072d9d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29631
8940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.296318940
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.4158469883
Short name T369
Test name
Test status
Simulation time 196074994 ps
CPU time 0.85 seconds
Started Jul 23 06:46:46 PM PDT 24
Finished Jul 23 06:46:54 PM PDT 24
Peak memory 206760 kb
Host smart-048a9e55-fb44-4a35-9d68-3acfa5f1df4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41584
69883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.4158469883
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.3499110091
Short name T1832
Test name
Test status
Simulation time 7486398041 ps
CPU time 207.39 seconds
Started Jul 23 06:46:48 PM PDT 24
Finished Jul 23 06:50:22 PM PDT 24
Peak memory 206884 kb
Host smart-39ae180a-cd7a-4e22-a484-6e94fb43270a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3499110091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.3499110091
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_iso_retraction.1556153615
Short name T1414
Test name
Test status
Simulation time 6350541119 ps
CPU time 23.28 seconds
Started Jul 23 06:46:45 PM PDT 24
Finished Jul 23 06:47:15 PM PDT 24
Peak memory 206932 kb
Host smart-5e181324-a5bf-4632-8f43-c297139f7f75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15561
53615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_iso_retraction.1556153615
Directory /workspace/43.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.1045255402
Short name T2555
Test name
Test status
Simulation time 209347060 ps
CPU time 0.85 seconds
Started Jul 23 06:46:46 PM PDT 24
Finished Jul 23 06:46:53 PM PDT 24
Peak memory 206784 kb
Host smart-cf6e5821-0585-41aa-b210-86f81ae82d12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10452
55402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.1045255402
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.399150413
Short name T1203
Test name
Test status
Simulation time 23305418542 ps
CPU time 23.82 seconds
Started Jul 23 06:46:47 PM PDT 24
Finished Jul 23 06:47:17 PM PDT 24
Peak memory 206796 kb
Host smart-e09254bb-fd76-4337-b4ff-e21cffc2d9c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39915
0413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.399150413
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.3087300279
Short name T321
Test name
Test status
Simulation time 3373444559 ps
CPU time 4.27 seconds
Started Jul 23 06:46:52 PM PDT 24
Finished Jul 23 06:47:02 PM PDT 24
Peak memory 206788 kb
Host smart-b02fb60a-5915-4541-a1a5-deb8dfd57eb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30873
00279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.3087300279
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.657175172
Short name T698
Test name
Test status
Simulation time 10026785730 ps
CPU time 100.23 seconds
Started Jul 23 06:46:49 PM PDT 24
Finished Jul 23 06:48:36 PM PDT 24
Peak memory 206980 kb
Host smart-01d8a4cd-2e45-4f2a-80aa-9fb11ff66168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65717
5172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.657175172
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.2473023846
Short name T1957
Test name
Test status
Simulation time 7000596953 ps
CPU time 48.04 seconds
Started Jul 23 06:46:51 PM PDT 24
Finished Jul 23 06:47:45 PM PDT 24
Peak memory 206916 kb
Host smart-f2c1c6fa-9eef-446d-8aa4-f2ed19f2870f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2473023846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.2473023846
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.2750667599
Short name T1077
Test name
Test status
Simulation time 239149154 ps
CPU time 0.96 seconds
Started Jul 23 06:46:48 PM PDT 24
Finished Jul 23 06:46:55 PM PDT 24
Peak memory 206748 kb
Host smart-ad7660d8-faed-4aac-b672-4f17043a8ef9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2750667599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.2750667599
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.1218957077
Short name T1194
Test name
Test status
Simulation time 206824876 ps
CPU time 0.9 seconds
Started Jul 23 06:46:57 PM PDT 24
Finished Jul 23 06:47:02 PM PDT 24
Peak memory 206744 kb
Host smart-48d21dec-4147-4901-97b6-6dd558d8fdab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12189
57077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.1218957077
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.401947482
Short name T2671
Test name
Test status
Simulation time 4848530713 ps
CPU time 33 seconds
Started Jul 23 06:47:00 PM PDT 24
Finished Jul 23 06:47:37 PM PDT 24
Peak memory 206964 kb
Host smart-04880531-30ae-4246-9278-2a29a9db68a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40194
7482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.401947482
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.214317104
Short name T423
Test name
Test status
Simulation time 4983286692 ps
CPU time 134.11 seconds
Started Jul 23 06:46:50 PM PDT 24
Finished Jul 23 06:49:10 PM PDT 24
Peak memory 206872 kb
Host smart-f9380c2a-91b3-4d45-92b7-88bc87508611
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=214317104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.214317104
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.4089816098
Short name T2012
Test name
Test status
Simulation time 162701888 ps
CPU time 0.82 seconds
Started Jul 23 06:46:52 PM PDT 24
Finished Jul 23 06:46:58 PM PDT 24
Peak memory 206768 kb
Host smart-1caeec2c-df6d-4f2d-8723-d47addc37cae
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4089816098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.4089816098
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.3744333285
Short name T870
Test name
Test status
Simulation time 145675844 ps
CPU time 0.8 seconds
Started Jul 23 06:47:07 PM PDT 24
Finished Jul 23 06:47:11 PM PDT 24
Peak memory 206744 kb
Host smart-8d36a3c4-7054-4107-b94a-e17c067843c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37443
33285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.3744333285
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.247862849
Short name T124
Test name
Test status
Simulation time 192259969 ps
CPU time 0.84 seconds
Started Jul 23 06:46:51 PM PDT 24
Finished Jul 23 06:46:57 PM PDT 24
Peak memory 206760 kb
Host smart-aecf1147-05e5-463e-8d01-2a21437b1b20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24786
2849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.247862849
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.536729748
Short name T2251
Test name
Test status
Simulation time 214223881 ps
CPU time 0.9 seconds
Started Jul 23 06:46:56 PM PDT 24
Finished Jul 23 06:47:01 PM PDT 24
Peak memory 206724 kb
Host smart-8446fcd4-7f57-41ff-8bc4-6486f4aba2da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53672
9748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.536729748
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.4061485693
Short name T2602
Test name
Test status
Simulation time 177051754 ps
CPU time 0.85 seconds
Started Jul 23 06:47:02 PM PDT 24
Finished Jul 23 06:47:06 PM PDT 24
Peak memory 206716 kb
Host smart-f59624b9-cb02-405c-abc6-6b18133362ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40614
85693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.4061485693
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.1391684998
Short name T2070
Test name
Test status
Simulation time 200523613 ps
CPU time 0.87 seconds
Started Jul 23 06:46:52 PM PDT 24
Finished Jul 23 06:46:58 PM PDT 24
Peak memory 206720 kb
Host smart-46803ac4-a798-4dfc-bb53-a38879821a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13916
84998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.1391684998
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.3393133940
Short name T2346
Test name
Test status
Simulation time 148887851 ps
CPU time 0.78 seconds
Started Jul 23 06:46:54 PM PDT 24
Finished Jul 23 06:47:00 PM PDT 24
Peak memory 206760 kb
Host smart-6d8ad6f4-b3c7-465e-a44a-0fe867dc19c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33931
33940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.3393133940
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.2702721353
Short name T1252
Test name
Test status
Simulation time 285981250 ps
CPU time 1.06 seconds
Started Jul 23 06:47:00 PM PDT 24
Finished Jul 23 06:47:05 PM PDT 24
Peak memory 206772 kb
Host smart-de2e6a9f-ea0a-4016-99d2-12fe742baf02
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2702721353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.2702721353
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.915292529
Short name T697
Test name
Test status
Simulation time 168304323 ps
CPU time 0.79 seconds
Started Jul 23 06:47:01 PM PDT 24
Finished Jul 23 06:47:06 PM PDT 24
Peak memory 206776 kb
Host smart-4bb37518-468a-4cb5-9343-593c17f50176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91529
2529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.915292529
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.3210991662
Short name T1180
Test name
Test status
Simulation time 34328225 ps
CPU time 0.7 seconds
Started Jul 23 06:47:00 PM PDT 24
Finished Jul 23 06:47:04 PM PDT 24
Peak memory 206708 kb
Host smart-44bc81b6-c58b-4611-88ea-ba21f08bc1a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32109
91662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.3210991662
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.1424294707
Short name T1094
Test name
Test status
Simulation time 18727000038 ps
CPU time 44.73 seconds
Started Jul 23 06:47:09 PM PDT 24
Finished Jul 23 06:47:56 PM PDT 24
Peak memory 206936 kb
Host smart-4eba6eae-4a09-4aa1-aee0-a5257192db66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14242
94707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.1424294707
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.1320005407
Short name T1864
Test name
Test status
Simulation time 207268595 ps
CPU time 0.9 seconds
Started Jul 23 06:47:00 PM PDT 24
Finished Jul 23 06:47:04 PM PDT 24
Peak memory 206656 kb
Host smart-aed73c44-5c6c-4726-8214-58bcd6e2e3e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13200
05407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.1320005407
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.3109723222
Short name T2176
Test name
Test status
Simulation time 291873867 ps
CPU time 0.98 seconds
Started Jul 23 06:46:53 PM PDT 24
Finished Jul 23 06:46:59 PM PDT 24
Peak memory 206756 kb
Host smart-b32094ea-44f9-42d2-8026-763e3b77ab32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31097
23222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3109723222
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.9816387
Short name T2448
Test name
Test status
Simulation time 224803678 ps
CPU time 0.85 seconds
Started Jul 23 06:47:08 PM PDT 24
Finished Jul 23 06:47:11 PM PDT 24
Peak memory 206772 kb
Host smart-a6d04514-8341-4fe7-afc4-4aa1aefad67c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98163
87 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.9816387
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.3305424707
Short name T1809
Test name
Test status
Simulation time 154652776 ps
CPU time 0.81 seconds
Started Jul 23 06:46:51 PM PDT 24
Finished Jul 23 06:46:57 PM PDT 24
Peak memory 206680 kb
Host smart-15664a9e-78a4-43cc-b5bb-db1e7a606cde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33054
24707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.3305424707
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.3443511084
Short name T2244
Test name
Test status
Simulation time 142686838 ps
CPU time 0.76 seconds
Started Jul 23 06:47:00 PM PDT 24
Finished Jul 23 06:47:04 PM PDT 24
Peak memory 206636 kb
Host smart-cf36856e-4078-4a2b-b57c-0ee477a33ed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34435
11084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.3443511084
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.1468291966
Short name T1346
Test name
Test status
Simulation time 154368038 ps
CPU time 0.81 seconds
Started Jul 23 06:46:53 PM PDT 24
Finished Jul 23 06:46:59 PM PDT 24
Peak memory 206724 kb
Host smart-6e925e3b-1ac8-486f-af94-53a0269a548c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14682
91966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.1468291966
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.1058866999
Short name T1040
Test name
Test status
Simulation time 161107442 ps
CPU time 0.82 seconds
Started Jul 23 06:46:52 PM PDT 24
Finished Jul 23 06:46:58 PM PDT 24
Peak memory 206764 kb
Host smart-8d654790-b6b4-4235-a99a-b3bdb4e7b40f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10588
66999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.1058866999
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.520692596
Short name T1787
Test name
Test status
Simulation time 195279672 ps
CPU time 0.83 seconds
Started Jul 23 06:46:55 PM PDT 24
Finished Jul 23 06:47:00 PM PDT 24
Peak memory 206776 kb
Host smart-44236a8a-2299-4f83-b924-b5f67aedc9d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52069
2596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.520692596
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.4146118285
Short name T2718
Test name
Test status
Simulation time 6218778500 ps
CPU time 160.04 seconds
Started Jul 23 06:46:52 PM PDT 24
Finished Jul 23 06:49:37 PM PDT 24
Peak memory 206884 kb
Host smart-c770f110-4481-4ed5-9b72-bc63c044dd6a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4146118285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.4146118285
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.414901879
Short name T404
Test name
Test status
Simulation time 172499823 ps
CPU time 0.87 seconds
Started Jul 23 06:46:54 PM PDT 24
Finished Jul 23 06:46:59 PM PDT 24
Peak memory 206752 kb
Host smart-8df8c870-fc7d-46fd-a8dc-8b96ac71d7a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41490
1879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.414901879
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.2767282666
Short name T1866
Test name
Test status
Simulation time 166989408 ps
CPU time 0.81 seconds
Started Jul 23 06:46:57 PM PDT 24
Finished Jul 23 06:47:02 PM PDT 24
Peak memory 206664 kb
Host smart-cd1b12f1-49fd-43bd-b8c8-b5b69cbc13a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27672
82666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.2767282666
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.3254040127
Short name T2078
Test name
Test status
Simulation time 853399273 ps
CPU time 2.1 seconds
Started Jul 23 06:47:00 PM PDT 24
Finished Jul 23 06:47:05 PM PDT 24
Peak memory 206784 kb
Host smart-7d6db91f-f772-4502-923e-fe9e0ec804c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32540
40127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.3254040127
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.3399659114
Short name T1285
Test name
Test status
Simulation time 4373417928 ps
CPU time 31.56 seconds
Started Jul 23 06:47:02 PM PDT 24
Finished Jul 23 06:47:38 PM PDT 24
Peak memory 206984 kb
Host smart-32b11578-da6e-4552-82fc-f75b2b43b698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33996
59114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.3399659114
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.281808227
Short name T2309
Test name
Test status
Simulation time 34468141 ps
CPU time 0.67 seconds
Started Jul 23 06:47:20 PM PDT 24
Finished Jul 23 06:47:26 PM PDT 24
Peak memory 206756 kb
Host smart-6b74206e-188c-4179-a776-90c581c5e755
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=281808227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.281808227
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.2469679967
Short name T599
Test name
Test status
Simulation time 4139422420 ps
CPU time 5.26 seconds
Started Jul 23 06:46:58 PM PDT 24
Finished Jul 23 06:47:07 PM PDT 24
Peak memory 206816 kb
Host smart-641472c3-6889-45cd-86a6-fd1c9b23473c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2469679967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.2469679967
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.3634933622
Short name T1612
Test name
Test status
Simulation time 13359090149 ps
CPU time 15.36 seconds
Started Jul 23 06:47:01 PM PDT 24
Finished Jul 23 06:47:20 PM PDT 24
Peak memory 206832 kb
Host smart-5e7fcf93-95c9-4106-a44e-10bc4e4a5c00
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3634933622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.3634933622
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.3376783087
Short name T1137
Test name
Test status
Simulation time 23340837277 ps
CPU time 25.56 seconds
Started Jul 23 06:46:59 PM PDT 24
Finished Jul 23 06:47:28 PM PDT 24
Peak memory 206820 kb
Host smart-2201e0ad-4d38-4b1f-91f7-8df78d3733e2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3376783087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.3376783087
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.4052192237
Short name T343
Test name
Test status
Simulation time 170743833 ps
CPU time 0.9 seconds
Started Jul 23 06:46:59 PM PDT 24
Finished Jul 23 06:47:03 PM PDT 24
Peak memory 206772 kb
Host smart-2e961b74-f272-418b-8770-57332f62797a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40521
92237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.4052192237
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.2459762587
Short name T2654
Test name
Test status
Simulation time 146203721 ps
CPU time 0.83 seconds
Started Jul 23 06:47:14 PM PDT 24
Finished Jul 23 06:47:17 PM PDT 24
Peak memory 206744 kb
Host smart-e3815f7e-0b8c-4bb6-b27e-562f1248e613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24597
62587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.2459762587
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.3909128263
Short name T1627
Test name
Test status
Simulation time 583083319 ps
CPU time 1.67 seconds
Started Jul 23 06:47:00 PM PDT 24
Finished Jul 23 06:47:06 PM PDT 24
Peak memory 206900 kb
Host smart-a938fa60-a729-4467-a7b4-2b250838c7f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39091
28263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.3909128263
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.1384587268
Short name T2184
Test name
Test status
Simulation time 1011246185 ps
CPU time 2.37 seconds
Started Jul 23 06:47:13 PM PDT 24
Finished Jul 23 06:47:17 PM PDT 24
Peak memory 206888 kb
Host smart-a942ecc1-feb1-4a84-97c4-ba907a4d6c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13845
87268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.1384587268
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.2134480391
Short name T520
Test name
Test status
Simulation time 20215658433 ps
CPU time 39.87 seconds
Started Jul 23 06:47:02 PM PDT 24
Finished Jul 23 06:47:46 PM PDT 24
Peak memory 206876 kb
Host smart-1be3e8a6-d7b0-4efc-9e63-5dc8c1b7f910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21344
80391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.2134480391
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.2079401013
Short name T658
Test name
Test status
Simulation time 421811255 ps
CPU time 1.34 seconds
Started Jul 23 06:47:14 PM PDT 24
Finished Jul 23 06:47:17 PM PDT 24
Peak memory 206732 kb
Host smart-8a397819-cf9b-4a36-9d62-6b09acb4a70f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20794
01013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.2079401013
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.136851481
Short name T2378
Test name
Test status
Simulation time 158388159 ps
CPU time 0.85 seconds
Started Jul 23 06:47:09 PM PDT 24
Finished Jul 23 06:47:12 PM PDT 24
Peak memory 206728 kb
Host smart-2facfbee-0e13-48c8-9410-32f45bdef79e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13685
1481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.136851481
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.1988491984
Short name T1140
Test name
Test status
Simulation time 36830223 ps
CPU time 0.67 seconds
Started Jul 23 06:47:14 PM PDT 24
Finished Jul 23 06:47:16 PM PDT 24
Peak memory 206760 kb
Host smart-bfcbfb6b-2e38-410f-95ed-bfaaeeef5396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19884
91984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.1988491984
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.2423390869
Short name T1858
Test name
Test status
Simulation time 989754827 ps
CPU time 2.17 seconds
Started Jul 23 06:47:06 PM PDT 24
Finished Jul 23 06:47:12 PM PDT 24
Peak memory 206888 kb
Host smart-b8e97272-f997-43ec-852a-2ed9117563d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24233
90869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.2423390869
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.630897897
Short name T1372
Test name
Test status
Simulation time 147779607 ps
CPU time 1.11 seconds
Started Jul 23 06:47:19 PM PDT 24
Finished Jul 23 06:47:25 PM PDT 24
Peak memory 206796 kb
Host smart-7930df41-b979-48d9-9d45-5e0137b8e0f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63089
7897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.630897897
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.4053240404
Short name T316
Test name
Test status
Simulation time 196035804 ps
CPU time 0.83 seconds
Started Jul 23 06:47:04 PM PDT 24
Finished Jul 23 06:47:08 PM PDT 24
Peak memory 206760 kb
Host smart-b1bfa832-16c1-4f41-aaae-3a61543d454e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40532
40404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.4053240404
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.2942665468
Short name T653
Test name
Test status
Simulation time 147673416 ps
CPU time 0.77 seconds
Started Jul 23 06:47:05 PM PDT 24
Finished Jul 23 06:47:09 PM PDT 24
Peak memory 206760 kb
Host smart-6d0941f9-3348-424d-a7ad-8134448fad0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29426
65468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.2942665468
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.745279986
Short name T88
Test name
Test status
Simulation time 189184428 ps
CPU time 0.84 seconds
Started Jul 23 06:47:13 PM PDT 24
Finished Jul 23 06:47:16 PM PDT 24
Peak memory 206764 kb
Host smart-e16e8c67-7e21-418d-b47a-8acb7b35cc9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74527
9986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.745279986
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_iso_retraction.2186414596
Short name T2564
Test name
Test status
Simulation time 4537132056 ps
CPU time 37.16 seconds
Started Jul 23 06:47:07 PM PDT 24
Finished Jul 23 06:47:47 PM PDT 24
Peak memory 206896 kb
Host smart-fac7392c-a328-4d51-b10b-8d5000e29253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21864
14596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_iso_retraction.2186414596
Directory /workspace/44.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.2860523216
Short name T1889
Test name
Test status
Simulation time 227943241 ps
CPU time 0.88 seconds
Started Jul 23 06:47:21 PM PDT 24
Finished Jul 23 06:47:28 PM PDT 24
Peak memory 206744 kb
Host smart-5b2c09c9-6333-4e41-9d16-cf2934fa40ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28605
23216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.2860523216
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.165075578
Short name T2458
Test name
Test status
Simulation time 23337866281 ps
CPU time 24.47 seconds
Started Jul 23 06:47:09 PM PDT 24
Finished Jul 23 06:47:36 PM PDT 24
Peak memory 206816 kb
Host smart-9c2100c1-3e87-4964-a736-e3b0722e55db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16507
5578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.165075578
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.1319910127
Short name T1207
Test name
Test status
Simulation time 3387979411 ps
CPU time 4.5 seconds
Started Jul 23 06:47:09 PM PDT 24
Finished Jul 23 06:47:15 PM PDT 24
Peak memory 206820 kb
Host smart-961543b8-a10c-400d-a06c-ba1779400aed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13199
10127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.1319910127
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.2877263574
Short name T969
Test name
Test status
Simulation time 11226837305 ps
CPU time 319.25 seconds
Started Jul 23 06:47:11 PM PDT 24
Finished Jul 23 06:52:32 PM PDT 24
Peak memory 206984 kb
Host smart-4b99d21b-fb9a-45cf-bb34-0b0595850799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28772
63574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.2877263574
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.1257539805
Short name T987
Test name
Test status
Simulation time 4207562499 ps
CPU time 109.72 seconds
Started Jul 23 06:47:05 PM PDT 24
Finished Jul 23 06:48:58 PM PDT 24
Peak memory 206848 kb
Host smart-a19e0f37-1e2b-474e-9be3-dee7764f7af8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1257539805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.1257539805
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.2978140969
Short name T1003
Test name
Test status
Simulation time 241585444 ps
CPU time 0.91 seconds
Started Jul 23 06:47:05 PM PDT 24
Finished Jul 23 06:47:09 PM PDT 24
Peak memory 206792 kb
Host smart-c89bfef1-3c8b-4778-838a-831a38056b38
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2978140969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.2978140969
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.2244376356
Short name T1141
Test name
Test status
Simulation time 185821130 ps
CPU time 0.87 seconds
Started Jul 23 06:47:25 PM PDT 24
Finished Jul 23 06:47:36 PM PDT 24
Peak memory 206728 kb
Host smart-34df2d5b-00ab-4b93-b980-41206c6d694e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22443
76356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.2244376356
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.3559556080
Short name T2326
Test name
Test status
Simulation time 5749796142 ps
CPU time 151.61 seconds
Started Jul 23 06:47:22 PM PDT 24
Finished Jul 23 06:50:01 PM PDT 24
Peak memory 206908 kb
Host smart-c50b3ad7-4746-427d-926a-4ef55f2cb65d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35595
56080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.3559556080
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.3624203564
Short name T1637
Test name
Test status
Simulation time 4313428883 ps
CPU time 32.42 seconds
Started Jul 23 06:47:19 PM PDT 24
Finished Jul 23 06:47:56 PM PDT 24
Peak memory 206892 kb
Host smart-e9c3f43b-4a01-4c4f-9d93-8f9e8aead01c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3624203564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.3624203564
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.158077399
Short name T1035
Test name
Test status
Simulation time 163429752 ps
CPU time 0.84 seconds
Started Jul 23 06:47:15 PM PDT 24
Finished Jul 23 06:47:18 PM PDT 24
Peak memory 206760 kb
Host smart-46993fda-93b4-43d0-8bec-8f83789c9f19
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=158077399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.158077399
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.3995433783
Short name T1342
Test name
Test status
Simulation time 208519966 ps
CPU time 0.91 seconds
Started Jul 23 06:47:15 PM PDT 24
Finished Jul 23 06:47:18 PM PDT 24
Peak memory 206708 kb
Host smart-39e0e563-47e0-48e4-9292-e5ebd5419463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39954
33783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.3995433783
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.3436756202
Short name T1339
Test name
Test status
Simulation time 202701739 ps
CPU time 0.91 seconds
Started Jul 23 06:47:13 PM PDT 24
Finished Jul 23 06:47:16 PM PDT 24
Peak memory 206752 kb
Host smart-d2e7b5a2-31fc-4737-b637-76174f1a629f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34367
56202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.3436756202
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.2741459978
Short name T2643
Test name
Test status
Simulation time 176401310 ps
CPU time 0.85 seconds
Started Jul 23 06:47:12 PM PDT 24
Finished Jul 23 06:47:15 PM PDT 24
Peak memory 206740 kb
Host smart-727e003e-1f59-4986-95ef-676678dedd45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27414
59978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.2741459978
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.1975905664
Short name T2596
Test name
Test status
Simulation time 173477836 ps
CPU time 0.77 seconds
Started Jul 23 06:47:26 PM PDT 24
Finished Jul 23 06:47:38 PM PDT 24
Peak memory 206720 kb
Host smart-c5aa1a8e-f221-484e-85d7-e18fb18af873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19759
05664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.1975905664
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.496419746
Short name T159
Test name
Test status
Simulation time 156108654 ps
CPU time 0.8 seconds
Started Jul 23 06:47:17 PM PDT 24
Finished Jul 23 06:47:21 PM PDT 24
Peak memory 206748 kb
Host smart-b5473d35-b7bd-4920-a503-76fe1149f879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49641
9746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.496419746
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.1117154648
Short name T2413
Test name
Test status
Simulation time 202063725 ps
CPU time 0.98 seconds
Started Jul 23 06:47:15 PM PDT 24
Finished Jul 23 06:47:19 PM PDT 24
Peak memory 206764 kb
Host smart-5b1d8637-f88d-4c24-8f78-c64a19bc14c0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1117154648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.1117154648
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.1689968369
Short name T2218
Test name
Test status
Simulation time 139575936 ps
CPU time 0.76 seconds
Started Jul 23 06:47:21 PM PDT 24
Finished Jul 23 06:47:29 PM PDT 24
Peak memory 206768 kb
Host smart-c78ead56-ec5b-4272-81b9-82130f2cf53e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16899
68369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.1689968369
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.3991874901
Short name T2418
Test name
Test status
Simulation time 41628642 ps
CPU time 0.67 seconds
Started Jul 23 06:47:17 PM PDT 24
Finished Jul 23 06:47:21 PM PDT 24
Peak memory 206580 kb
Host smart-f5ba99f8-eaa2-40c1-9286-17219a9a05ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39918
74901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.3991874901
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.357302008
Short name T2207
Test name
Test status
Simulation time 6480764566 ps
CPU time 15.69 seconds
Started Jul 23 06:47:21 PM PDT 24
Finished Jul 23 06:47:44 PM PDT 24
Peak memory 207000 kb
Host smart-6feea7c3-69b1-4fbf-946d-913f9de592f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35730
2008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.357302008
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.1088367132
Short name T963
Test name
Test status
Simulation time 157877548 ps
CPU time 0.94 seconds
Started Jul 23 06:47:21 PM PDT 24
Finished Jul 23 06:47:28 PM PDT 24
Peak memory 206772 kb
Host smart-12e179a3-0ab0-498f-b263-4ee4f7ef8fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10883
67132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.1088367132
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.3886478132
Short name T2308
Test name
Test status
Simulation time 241783997 ps
CPU time 0.89 seconds
Started Jul 23 06:47:26 PM PDT 24
Finished Jul 23 06:47:37 PM PDT 24
Peak memory 206764 kb
Host smart-60553079-e67f-4649-99da-23743ee07f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38864
78132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.3886478132
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.1408915344
Short name T513
Test name
Test status
Simulation time 223477768 ps
CPU time 0.88 seconds
Started Jul 23 06:47:24 PM PDT 24
Finished Jul 23 06:47:34 PM PDT 24
Peak memory 206748 kb
Host smart-affcfc23-7b7a-4837-80b6-810120032141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14089
15344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.1408915344
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.3806563180
Short name T933
Test name
Test status
Simulation time 177315752 ps
CPU time 0.87 seconds
Started Jul 23 06:47:20 PM PDT 24
Finished Jul 23 06:47:26 PM PDT 24
Peak memory 206740 kb
Host smart-51c991a8-2c58-44cf-9e87-991623bd356b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38065
63180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.3806563180
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.3346685932
Short name T447
Test name
Test status
Simulation time 165297340 ps
CPU time 0.78 seconds
Started Jul 23 06:47:26 PM PDT 24
Finished Jul 23 06:47:37 PM PDT 24
Peak memory 206772 kb
Host smart-9a69c763-5025-48ae-bbdb-4d1d9b12c468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33466
85932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.3346685932
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.1077936932
Short name T297
Test name
Test status
Simulation time 165537653 ps
CPU time 0.73 seconds
Started Jul 23 06:47:29 PM PDT 24
Finished Jul 23 06:47:40 PM PDT 24
Peak memory 206748 kb
Host smart-b4c938b6-fd86-4b72-babd-3bb5cf72dbf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10779
36932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.1077936932
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.2219099248
Short name T2095
Test name
Test status
Simulation time 154214426 ps
CPU time 0.8 seconds
Started Jul 23 06:47:24 PM PDT 24
Finished Jul 23 06:47:34 PM PDT 24
Peak memory 206748 kb
Host smart-9de0bc3c-e2ac-4bba-8b58-6fa317ea1e0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22190
99248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.2219099248
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.937147846
Short name T2434
Test name
Test status
Simulation time 222727428 ps
CPU time 0.88 seconds
Started Jul 23 06:47:24 PM PDT 24
Finished Jul 23 06:47:35 PM PDT 24
Peak memory 206752 kb
Host smart-e973bb23-ffea-469d-a654-041d37d96bba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93714
7846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.937147846
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.4062305945
Short name T1274
Test name
Test status
Simulation time 3418717829 ps
CPU time 32.48 seconds
Started Jul 23 06:47:27 PM PDT 24
Finished Jul 23 06:48:10 PM PDT 24
Peak memory 206956 kb
Host smart-07a75e4a-6704-4a46-ab1c-6ecf6a638dcf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4062305945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.4062305945
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.2940511364
Short name T1483
Test name
Test status
Simulation time 148831265 ps
CPU time 0.78 seconds
Started Jul 23 06:47:20 PM PDT 24
Finished Jul 23 06:47:27 PM PDT 24
Peak memory 206740 kb
Host smart-88df44af-5ee3-438d-8e11-ba55f3598ab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29405
11364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.2940511364
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.3319365755
Short name T1330
Test name
Test status
Simulation time 182922797 ps
CPU time 0.89 seconds
Started Jul 23 06:47:19 PM PDT 24
Finished Jul 23 06:47:23 PM PDT 24
Peak memory 206692 kb
Host smart-ad46c21f-7d33-44c8-af28-a8346ea3e20c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33193
65755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.3319365755
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.2173689144
Short name T1533
Test name
Test status
Simulation time 1284740331 ps
CPU time 2.55 seconds
Started Jul 23 06:47:21 PM PDT 24
Finished Jul 23 06:47:31 PM PDT 24
Peak memory 206900 kb
Host smart-9a37a86d-035c-4bb9-98c6-19d1d74dc606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21736
89144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.2173689144
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.4019871037
Short name T1765
Test name
Test status
Simulation time 3866785042 ps
CPU time 107.59 seconds
Started Jul 23 06:47:23 PM PDT 24
Finished Jul 23 06:49:19 PM PDT 24
Peak memory 206920 kb
Host smart-bf0a2c59-98c4-42cc-ac89-cec3f3ef17c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40198
71037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.4019871037
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.509944618
Short name T857
Test name
Test status
Simulation time 36774382 ps
CPU time 0.64 seconds
Started Jul 23 06:47:53 PM PDT 24
Finished Jul 23 06:47:57 PM PDT 24
Peak memory 206732 kb
Host smart-eeeb4080-f542-4965-8e71-890c1fec991e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=509944618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.509944618
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.1944144335
Short name T2114
Test name
Test status
Simulation time 3744358544 ps
CPU time 4.07 seconds
Started Jul 23 06:47:26 PM PDT 24
Finished Jul 23 06:47:40 PM PDT 24
Peak memory 206912 kb
Host smart-b9024f33-95d6-46d4-aaf1-23dae364d9b6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1944144335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.1944144335
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.752485321
Short name T2648
Test name
Test status
Simulation time 13428359474 ps
CPU time 12.99 seconds
Started Jul 23 06:47:25 PM PDT 24
Finished Jul 23 06:47:47 PM PDT 24
Peak memory 206772 kb
Host smart-63c2726d-b63f-4d0b-94c7-9408334f0a53
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=752485321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.752485321
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.872307237
Short name T797
Test name
Test status
Simulation time 23379936182 ps
CPU time 28.67 seconds
Started Jul 23 06:47:23 PM PDT 24
Finished Jul 23 06:48:00 PM PDT 24
Peak memory 206888 kb
Host smart-a6fe7cbd-fcac-475d-b88b-fa88eb754a2b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=872307237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.872307237
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.15663850
Short name T675
Test name
Test status
Simulation time 203816403 ps
CPU time 0.81 seconds
Started Jul 23 06:47:21 PM PDT 24
Finished Jul 23 06:47:29 PM PDT 24
Peak memory 206772 kb
Host smart-620bf6f1-04b8-4478-8eab-270a13e4dee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15663
850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.15663850
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.2175138390
Short name T62
Test name
Test status
Simulation time 147705384 ps
CPU time 0.77 seconds
Started Jul 23 06:47:23 PM PDT 24
Finished Jul 23 06:47:32 PM PDT 24
Peak memory 206796 kb
Host smart-4a08ef25-91f5-4061-8954-7d149908cc48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21751
38390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.2175138390
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.1915164641
Short name T1428
Test name
Test status
Simulation time 515603008 ps
CPU time 1.6 seconds
Started Jul 23 06:47:22 PM PDT 24
Finished Jul 23 06:47:31 PM PDT 24
Peak memory 206808 kb
Host smart-76b11ce2-1f12-4c73-8948-fb89819d05b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19151
64641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.1915164641
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.1717870126
Short name T1250
Test name
Test status
Simulation time 1116698209 ps
CPU time 2.5 seconds
Started Jul 23 06:47:22 PM PDT 24
Finished Jul 23 06:47:32 PM PDT 24
Peak memory 207080 kb
Host smart-a49baaef-7b2a-4a72-8e07-8c73e0df30b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17178
70126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.1717870126
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.987162512
Short name T111
Test name
Test status
Simulation time 8081747219 ps
CPU time 13.88 seconds
Started Jul 23 06:47:22 PM PDT 24
Finished Jul 23 06:47:44 PM PDT 24
Peak memory 206896 kb
Host smart-fbbd2633-c3e4-4b1a-84e3-79f2c19da18a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98716
2512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.987162512
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.4148108164
Short name T496
Test name
Test status
Simulation time 488294326 ps
CPU time 1.42 seconds
Started Jul 23 06:47:26 PM PDT 24
Finished Jul 23 06:47:37 PM PDT 24
Peak memory 206772 kb
Host smart-8b8b6a62-9e88-46bc-a358-ba426c96ad79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41481
08164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.4148108164
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.2555893121
Short name T339
Test name
Test status
Simulation time 158523314 ps
CPU time 0.79 seconds
Started Jul 23 06:47:24 PM PDT 24
Finished Jul 23 06:47:35 PM PDT 24
Peak memory 206880 kb
Host smart-82805b9e-1530-4b78-b2e0-711508b6a44d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25558
93121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.2555893121
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.600614095
Short name T315
Test name
Test status
Simulation time 42437381 ps
CPU time 0.66 seconds
Started Jul 23 06:47:32 PM PDT 24
Finished Jul 23 06:47:44 PM PDT 24
Peak memory 206724 kb
Host smart-b3548dd2-a384-40d4-83c8-5861eaf59161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60061
4095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.600614095
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.3839048410
Short name T1906
Test name
Test status
Simulation time 834929222 ps
CPU time 1.93 seconds
Started Jul 23 06:47:26 PM PDT 24
Finished Jul 23 06:47:39 PM PDT 24
Peak memory 206904 kb
Host smart-7244235e-9881-40f9-b1dc-ccc4d0cfb539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38390
48410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.3839048410
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.1353930483
Short name T673
Test name
Test status
Simulation time 324952896 ps
CPU time 2.34 seconds
Started Jul 23 06:47:23 PM PDT 24
Finished Jul 23 06:47:33 PM PDT 24
Peak memory 206796 kb
Host smart-29e2d05d-a878-4386-9e37-9697637126eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13539
30483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.1353930483
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.2430593206
Short name T2194
Test name
Test status
Simulation time 210834667 ps
CPU time 0.84 seconds
Started Jul 23 06:47:31 PM PDT 24
Finished Jul 23 06:47:42 PM PDT 24
Peak memory 206748 kb
Host smart-71db0eae-e2e3-45ec-8d61-312cd4199621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24305
93206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.2430593206
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.3015029976
Short name T1392
Test name
Test status
Simulation time 168482921 ps
CPU time 0.81 seconds
Started Jul 23 06:47:25 PM PDT 24
Finished Jul 23 06:47:36 PM PDT 24
Peak memory 206736 kb
Host smart-ae2b61eb-3810-426d-8a24-4fbb73b0f11e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30150
29976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.3015029976
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.764729991
Short name T2719
Test name
Test status
Simulation time 246419384 ps
CPU time 0.98 seconds
Started Jul 23 06:47:24 PM PDT 24
Finished Jul 23 06:47:35 PM PDT 24
Peak memory 206772 kb
Host smart-3639290c-44ac-4795-8b97-70c3651a2a9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76472
9991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.764729991
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.2961045522
Short name T929
Test name
Test status
Simulation time 5521566076 ps
CPU time 152.36 seconds
Started Jul 23 06:47:26 PM PDT 24
Finished Jul 23 06:50:08 PM PDT 24
Peak memory 206888 kb
Host smart-1239366e-3b8f-4f67-9e5c-7a0f4a74082f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2961045522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.2961045522
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_iso_retraction.873268079
Short name T1108
Test name
Test status
Simulation time 8339059863 ps
CPU time 32.69 seconds
Started Jul 23 06:47:25 PM PDT 24
Finished Jul 23 06:48:08 PM PDT 24
Peak memory 206956 kb
Host smart-fd470209-ace1-434a-a546-816039322664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87326
8079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_iso_retraction.873268079
Directory /workspace/45.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.1213756105
Short name T309
Test name
Test status
Simulation time 218239508 ps
CPU time 0.89 seconds
Started Jul 23 06:47:25 PM PDT 24
Finished Jul 23 06:47:36 PM PDT 24
Peak memory 206744 kb
Host smart-656cb2a8-0f85-4b39-bda0-38cb7fae0273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12137
56105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.1213756105
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.487515097
Short name T1542
Test name
Test status
Simulation time 23309106293 ps
CPU time 22.54 seconds
Started Jul 23 06:47:28 PM PDT 24
Finished Jul 23 06:48:02 PM PDT 24
Peak memory 206812 kb
Host smart-ce5f5a27-57db-4eeb-895e-2ecbd748ed72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48751
5097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.487515097
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.1631588711
Short name T511
Test name
Test status
Simulation time 3318114652 ps
CPU time 4.19 seconds
Started Jul 23 06:47:30 PM PDT 24
Finished Jul 23 06:47:45 PM PDT 24
Peak memory 206484 kb
Host smart-d17320bc-91be-4725-8ea5-9439155379ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16315
88711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.1631588711
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.1399211058
Short name T2126
Test name
Test status
Simulation time 10694749297 ps
CPU time 98.74 seconds
Started Jul 23 06:47:24 PM PDT 24
Finished Jul 23 06:49:11 PM PDT 24
Peak memory 206952 kb
Host smart-90c5742b-7896-464c-8646-830497c9b9a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13992
11058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.1399211058
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.3072463293
Short name T2128
Test name
Test status
Simulation time 3844491285 ps
CPU time 28.5 seconds
Started Jul 23 06:47:28 PM PDT 24
Finished Jul 23 06:48:07 PM PDT 24
Peak memory 206944 kb
Host smart-f80ffcf2-c913-453a-a9e4-20af844ffae3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3072463293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.3072463293
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.3478408972
Short name T1452
Test name
Test status
Simulation time 237588140 ps
CPU time 0.9 seconds
Started Jul 23 06:47:26 PM PDT 24
Finished Jul 23 06:47:38 PM PDT 24
Peak memory 206872 kb
Host smart-23171b98-9c2f-4c81-9512-eac30cc159e2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3478408972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.3478408972
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.1192836414
Short name T1049
Test name
Test status
Simulation time 196127806 ps
CPU time 0.86 seconds
Started Jul 23 06:47:29 PM PDT 24
Finished Jul 23 06:47:40 PM PDT 24
Peak memory 206768 kb
Host smart-939c0053-13af-4738-a844-46a810934611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11928
36414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.1192836414
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.3407213771
Short name T609
Test name
Test status
Simulation time 5450400275 ps
CPU time 49.42 seconds
Started Jul 23 06:47:26 PM PDT 24
Finished Jul 23 06:48:26 PM PDT 24
Peak memory 206952 kb
Host smart-6076c05d-03f5-45f0-90c1-d4283b73f230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34072
13771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.3407213771
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.3468057391
Short name T2072
Test name
Test status
Simulation time 5334537170 ps
CPU time 47.69 seconds
Started Jul 23 06:47:58 PM PDT 24
Finished Jul 23 06:48:47 PM PDT 24
Peak memory 206896 kb
Host smart-72830594-3645-4c16-8312-9009f2e6add0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3468057391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.3468057391
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.3034679010
Short name T1833
Test name
Test status
Simulation time 165918788 ps
CPU time 0.79 seconds
Started Jul 23 06:47:27 PM PDT 24
Finished Jul 23 06:47:39 PM PDT 24
Peak memory 206884 kb
Host smart-1dba806f-c94b-4a07-8147-5c6d04479a41
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3034679010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.3034679010
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.276036549
Short name T907
Test name
Test status
Simulation time 145247854 ps
CPU time 0.75 seconds
Started Jul 23 06:47:29 PM PDT 24
Finished Jul 23 06:47:41 PM PDT 24
Peak memory 206756 kb
Host smart-0d337cf7-f553-42e7-bcb4-76afd4373c58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27603
6549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.276036549
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.3920140893
Short name T2676
Test name
Test status
Simulation time 171790029 ps
CPU time 0.8 seconds
Started Jul 23 06:47:30 PM PDT 24
Finished Jul 23 06:47:42 PM PDT 24
Peak memory 206580 kb
Host smart-835cd862-e844-4e90-8d27-bf58d96af360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39201
40893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.3920140893
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.4161621303
Short name T395
Test name
Test status
Simulation time 159428521 ps
CPU time 0.83 seconds
Started Jul 23 06:47:28 PM PDT 24
Finished Jul 23 06:47:40 PM PDT 24
Peak memory 206748 kb
Host smart-fb00608c-ac4a-4310-8221-5f5256e694dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41616
21303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.4161621303
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.494601144
Short name T1924
Test name
Test status
Simulation time 177381051 ps
CPU time 0.8 seconds
Started Jul 23 06:47:32 PM PDT 24
Finished Jul 23 06:47:50 PM PDT 24
Peak memory 206520 kb
Host smart-6f418508-a312-484a-beeb-5a0da9bc11a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49460
1144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.494601144
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.2183338568
Short name T1473
Test name
Test status
Simulation time 167132730 ps
CPU time 0.88 seconds
Started Jul 23 06:47:37 PM PDT 24
Finished Jul 23 06:47:48 PM PDT 24
Peak memory 206744 kb
Host smart-c72502fe-a674-4979-a4dd-a4e663900aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21833
38568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.2183338568
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.1197529048
Short name T522
Test name
Test status
Simulation time 184442171 ps
CPU time 0.78 seconds
Started Jul 23 06:47:35 PM PDT 24
Finished Jul 23 06:47:47 PM PDT 24
Peak memory 206768 kb
Host smart-ebf63b71-6e5f-437f-869b-2ae119710cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11975
29048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.1197529048
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.85056481
Short name T81
Test name
Test status
Simulation time 197406735 ps
CPU time 0.91 seconds
Started Jul 23 06:47:31 PM PDT 24
Finished Jul 23 06:47:44 PM PDT 24
Peak memory 206772 kb
Host smart-d0c93cca-c647-41c2-aa20-8fdc9ed36064
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=85056481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.85056481
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.4038477742
Short name T2558
Test name
Test status
Simulation time 181671575 ps
CPU time 0.83 seconds
Started Jul 23 06:47:32 PM PDT 24
Finished Jul 23 06:47:44 PM PDT 24
Peak memory 206540 kb
Host smart-0f54293e-9ea6-4836-98bd-55beb90ea6b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40384
77742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.4038477742
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.1569753659
Short name T758
Test name
Test status
Simulation time 61657676 ps
CPU time 0.67 seconds
Started Jul 23 06:47:32 PM PDT 24
Finished Jul 23 06:47:43 PM PDT 24
Peak memory 206744 kb
Host smart-205844f5-a2a8-49e5-b3ca-9017aa24ca08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15697
53659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.1569753659
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.2680578277
Short name T1472
Test name
Test status
Simulation time 10001696461 ps
CPU time 21.15 seconds
Started Jul 23 06:47:40 PM PDT 24
Finished Jul 23 06:48:10 PM PDT 24
Peak memory 206992 kb
Host smart-e597bd04-851f-44ff-b80a-4045cf050da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26805
78277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.2680578277
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.15874821
Short name T765
Test name
Test status
Simulation time 223606914 ps
CPU time 0.88 seconds
Started Jul 23 06:47:33 PM PDT 24
Finished Jul 23 06:47:44 PM PDT 24
Peak memory 206756 kb
Host smart-ed3ff8df-8e99-4dde-9dc3-64c9138859f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15874
821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.15874821
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.208662935
Short name T2463
Test name
Test status
Simulation time 225712663 ps
CPU time 0.89 seconds
Started Jul 23 06:47:33 PM PDT 24
Finished Jul 23 06:47:45 PM PDT 24
Peak memory 206744 kb
Host smart-15922336-61ae-4dd0-a671-fb6605acf64d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20866
2935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.208662935
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.3378747979
Short name T2431
Test name
Test status
Simulation time 299973858 ps
CPU time 0.94 seconds
Started Jul 23 06:47:43 PM PDT 24
Finished Jul 23 06:47:50 PM PDT 24
Peak memory 206752 kb
Host smart-9059adb4-9e4a-438c-a0a7-a781ca83a5a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33787
47979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.3378747979
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.951675820
Short name T2135
Test name
Test status
Simulation time 169869148 ps
CPU time 0.83 seconds
Started Jul 23 06:47:32 PM PDT 24
Finished Jul 23 06:47:44 PM PDT 24
Peak memory 206752 kb
Host smart-2b0397e5-d79c-4d5e-8073-02cb6a2f5b57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95167
5820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.951675820
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.4255009831
Short name T325
Test name
Test status
Simulation time 167691871 ps
CPU time 0.83 seconds
Started Jul 23 06:47:34 PM PDT 24
Finished Jul 23 06:47:46 PM PDT 24
Peak memory 206676 kb
Host smart-2f35f5e2-a31f-4147-bf64-1c8b87e68419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42550
09831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.4255009831
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.3805685038
Short name T439
Test name
Test status
Simulation time 151374434 ps
CPU time 0.77 seconds
Started Jul 23 06:47:40 PM PDT 24
Finished Jul 23 06:47:49 PM PDT 24
Peak memory 206768 kb
Host smart-f394b919-f1ac-4d9d-9b2c-ffc099b5f606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38056
85038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.3805685038
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.980252635
Short name T48
Test name
Test status
Simulation time 146998234 ps
CPU time 0.75 seconds
Started Jul 23 06:47:48 PM PDT 24
Finished Jul 23 06:47:54 PM PDT 24
Peak memory 206748 kb
Host smart-61f2a34e-ae59-4fb8-9ad5-01988c35c0ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98025
2635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.980252635
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.3574346295
Short name T495
Test name
Test status
Simulation time 191944117 ps
CPU time 0.83 seconds
Started Jul 23 06:47:44 PM PDT 24
Finished Jul 23 06:47:51 PM PDT 24
Peak memory 206752 kb
Host smart-c7b2d080-aaff-42ff-ab24-012ee703e2db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35743
46295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.3574346295
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.1400647280
Short name T1176
Test name
Test status
Simulation time 5763904736 ps
CPU time 149.57 seconds
Started Jul 23 06:47:34 PM PDT 24
Finished Jul 23 06:50:14 PM PDT 24
Peak memory 206808 kb
Host smart-9830bc8c-97bb-4936-80a2-3b5ae99f6dff
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1400647280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.1400647280
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.2814343026
Short name T680
Test name
Test status
Simulation time 147896770 ps
CPU time 0.77 seconds
Started Jul 23 06:47:33 PM PDT 24
Finished Jul 23 06:47:45 PM PDT 24
Peak memory 206744 kb
Host smart-5d0bdb51-300f-48bc-8f7d-329ba97bbcd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28143
43026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.2814343026
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.3986407063
Short name T664
Test name
Test status
Simulation time 203620546 ps
CPU time 0.84 seconds
Started Jul 23 06:47:38 PM PDT 24
Finished Jul 23 06:47:48 PM PDT 24
Peak memory 206716 kb
Host smart-0396910a-634a-4a68-a085-53da2f050287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39864
07063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.3986407063
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.4181876171
Short name T359
Test name
Test status
Simulation time 617635799 ps
CPU time 1.48 seconds
Started Jul 23 06:47:52 PM PDT 24
Finished Jul 23 06:47:56 PM PDT 24
Peak memory 206752 kb
Host smart-9957e060-b0b9-4d2d-9f2a-96e74b7efa95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41818
76171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.4181876171
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.1932030789
Short name T2245
Test name
Test status
Simulation time 4008437548 ps
CPU time 29.82 seconds
Started Jul 23 06:47:33 PM PDT 24
Finished Jul 23 06:48:14 PM PDT 24
Peak memory 206956 kb
Host smart-7730f520-2076-4be3-ad38-cb8c8ad26bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19320
30789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.1932030789
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.2073281743
Short name T2033
Test name
Test status
Simulation time 59154896 ps
CPU time 0.71 seconds
Started Jul 23 06:47:55 PM PDT 24
Finished Jul 23 06:47:59 PM PDT 24
Peak memory 206696 kb
Host smart-1db7aab6-d242-4139-9719-92321ff995d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2073281743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.2073281743
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.2272568227
Short name T222
Test name
Test status
Simulation time 3881207074 ps
CPU time 4.67 seconds
Started Jul 23 06:47:36 PM PDT 24
Finished Jul 23 06:47:50 PM PDT 24
Peak memory 206848 kb
Host smart-573c9b32-c935-4523-8934-b880bbb7fea5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2272568227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.2272568227
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.1036944536
Short name T699
Test name
Test status
Simulation time 13463307391 ps
CPU time 13.02 seconds
Started Jul 23 06:47:33 PM PDT 24
Finished Jul 23 06:47:57 PM PDT 24
Peak memory 206952 kb
Host smart-7e0146de-025d-4543-825e-fc9dea299ec2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1036944536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.1036944536
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.1721243345
Short name T2211
Test name
Test status
Simulation time 23367814296 ps
CPU time 24.2 seconds
Started Jul 23 06:47:34 PM PDT 24
Finished Jul 23 06:48:09 PM PDT 24
Peak memory 206892 kb
Host smart-43fb5a94-295f-465c-9271-7d44879a859a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1721243345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.1721243345
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.1186745397
Short name T2080
Test name
Test status
Simulation time 174256783 ps
CPU time 0.82 seconds
Started Jul 23 06:47:55 PM PDT 24
Finished Jul 23 06:47:59 PM PDT 24
Peak memory 206740 kb
Host smart-074b0c93-b605-4907-97c6-1be542b314a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11867
45397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.1186745397
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.2651458382
Short name T1948
Test name
Test status
Simulation time 228761656 ps
CPU time 0.91 seconds
Started Jul 23 06:47:42 PM PDT 24
Finished Jul 23 06:47:50 PM PDT 24
Peak memory 206752 kb
Host smart-04154ef9-0c4c-4a12-afdc-944aa2203e2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26514
58382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.2651458382
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.3785342147
Short name T902
Test name
Test status
Simulation time 541571585 ps
CPU time 1.75 seconds
Started Jul 23 06:47:44 PM PDT 24
Finished Jul 23 06:47:53 PM PDT 24
Peak memory 206832 kb
Host smart-a9108114-0f40-4e17-a99c-578e0b55963f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37853
42147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.3785342147
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.3470159159
Short name T2422
Test name
Test status
Simulation time 318825832 ps
CPU time 1.04 seconds
Started Jul 23 06:47:40 PM PDT 24
Finished Jul 23 06:47:49 PM PDT 24
Peak memory 206764 kb
Host smart-aeb124c9-1dc6-478b-ae2e-a1741e8b507b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34701
59159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.3470159159
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.3908194593
Short name T175
Test name
Test status
Simulation time 20404381364 ps
CPU time 37.3 seconds
Started Jul 23 06:47:37 PM PDT 24
Finished Jul 23 06:48:24 PM PDT 24
Peak memory 206888 kb
Host smart-b1566fb8-badd-478b-86dc-1da9b5a586c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39081
94593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.3908194593
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.2695681395
Short name T761
Test name
Test status
Simulation time 406394391 ps
CPU time 1.33 seconds
Started Jul 23 06:47:58 PM PDT 24
Finished Jul 23 06:48:01 PM PDT 24
Peak memory 206744 kb
Host smart-14ffef85-c7a3-4d89-a420-02587ad290d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26956
81395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.2695681395
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.1375381153
Short name T333
Test name
Test status
Simulation time 140093891 ps
CPU time 0.73 seconds
Started Jul 23 06:47:39 PM PDT 24
Finished Jul 23 06:47:48 PM PDT 24
Peak memory 206772 kb
Host smart-7f891aba-50d3-4b65-b31c-0a1944a693d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13753
81153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.1375381153
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.728407023
Short name T2085
Test name
Test status
Simulation time 74768427 ps
CPU time 0.71 seconds
Started Jul 23 06:47:39 PM PDT 24
Finished Jul 23 06:47:48 PM PDT 24
Peak memory 206756 kb
Host smart-df53dc38-86a7-45bd-bf5a-b4217b1af67f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72840
7023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.728407023
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.3057990779
Short name T2606
Test name
Test status
Simulation time 912513656 ps
CPU time 2.3 seconds
Started Jul 23 06:47:38 PM PDT 24
Finished Jul 23 06:47:49 PM PDT 24
Peak memory 206840 kb
Host smart-99e2b349-0f01-49a1-85e5-11649c1d8915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30579
90779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.3057990779
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.3954384470
Short name T1217
Test name
Test status
Simulation time 307463016 ps
CPU time 2.14 seconds
Started Jul 23 06:47:41 PM PDT 24
Finished Jul 23 06:47:51 PM PDT 24
Peak memory 206872 kb
Host smart-9b42a680-c432-4b3d-b922-c6247a1a52e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39543
84470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.3954384470
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.1760291982
Short name T1345
Test name
Test status
Simulation time 173116284 ps
CPU time 0.83 seconds
Started Jul 23 06:47:48 PM PDT 24
Finished Jul 23 06:47:54 PM PDT 24
Peak memory 206744 kb
Host smart-b5333959-6c01-4ba0-a987-1295151d271e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17602
91982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.1760291982
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.1514443575
Short name T407
Test name
Test status
Simulation time 169793983 ps
CPU time 0.83 seconds
Started Jul 23 06:47:40 PM PDT 24
Finished Jul 23 06:47:49 PM PDT 24
Peak memory 206752 kb
Host smart-4b6fbbef-9f89-45fd-b8d6-db3b4db536e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15144
43575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.1514443575
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.136575044
Short name T2252
Test name
Test status
Simulation time 212680026 ps
CPU time 0.94 seconds
Started Jul 23 06:47:47 PM PDT 24
Finished Jul 23 06:47:54 PM PDT 24
Peak memory 206748 kb
Host smart-03f1b9d9-d6c9-4ed4-8f97-2afcc501b86c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13657
5044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.136575044
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_iso_retraction.2831721831
Short name T979
Test name
Test status
Simulation time 7118671851 ps
CPU time 64.37 seconds
Started Jul 23 06:47:40 PM PDT 24
Finished Jul 23 06:48:53 PM PDT 24
Peak memory 206892 kb
Host smart-33bb2cb2-fb60-4e33-b1a1-7e5d811c5364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28317
21831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.2831721831
Directory /workspace/46.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.2070642508
Short name T2357
Test name
Test status
Simulation time 212462240 ps
CPU time 0.86 seconds
Started Jul 23 06:47:49 PM PDT 24
Finished Jul 23 06:47:54 PM PDT 24
Peak memory 206744 kb
Host smart-ad322d76-29f9-4740-96da-980014f81c93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20706
42508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.2070642508
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.4138984511
Short name T2224
Test name
Test status
Simulation time 23283176734 ps
CPU time 27.51 seconds
Started Jul 23 06:47:40 PM PDT 24
Finished Jul 23 06:48:16 PM PDT 24
Peak memory 206844 kb
Host smart-23c74010-a011-4f0c-82dc-50f03156e5d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41389
84511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.4138984511
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.633869785
Short name T1381
Test name
Test status
Simulation time 3285487677 ps
CPU time 3.53 seconds
Started Jul 23 06:47:42 PM PDT 24
Finished Jul 23 06:47:52 PM PDT 24
Peak memory 206820 kb
Host smart-2ef7f25c-102e-4f91-8602-dc4b35fd1abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63386
9785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.633869785
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.424384832
Short name T1238
Test name
Test status
Simulation time 8112587766 ps
CPU time 221.08 seconds
Started Jul 23 06:47:45 PM PDT 24
Finished Jul 23 06:51:32 PM PDT 24
Peak memory 206976 kb
Host smart-034a94cd-a523-45f3-a19f-2da45d29448e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42438
4832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.424384832
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.3172810790
Short name T1227
Test name
Test status
Simulation time 5040718917 ps
CPU time 36.16 seconds
Started Jul 23 06:48:00 PM PDT 24
Finished Jul 23 06:48:38 PM PDT 24
Peak memory 206888 kb
Host smart-57b94d96-41f1-40d4-be10-37d40657f44b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3172810790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.3172810790
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.2059920420
Short name T822
Test name
Test status
Simulation time 246543234 ps
CPU time 1.02 seconds
Started Jul 23 06:47:53 PM PDT 24
Finished Jul 23 06:47:57 PM PDT 24
Peak memory 206728 kb
Host smart-d6226e9c-461b-44d0-8c13-4cd1e50a31ec
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2059920420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.2059920420
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.65543696
Short name T1890
Test name
Test status
Simulation time 201768050 ps
CPU time 0.87 seconds
Started Jul 23 06:47:50 PM PDT 24
Finished Jul 23 06:47:55 PM PDT 24
Peak memory 206772 kb
Host smart-144ca7e4-81be-4316-960f-ebac0b1019dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65543
696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.65543696
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.569633208
Short name T1872
Test name
Test status
Simulation time 4365028169 ps
CPU time 32.65 seconds
Started Jul 23 06:47:54 PM PDT 24
Finished Jul 23 06:48:29 PM PDT 24
Peak memory 206932 kb
Host smart-c3c432c0-f6a9-443a-839e-4bb4009fcc7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56963
3208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.569633208
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.3157051625
Short name T1188
Test name
Test status
Simulation time 5930651611 ps
CPU time 167.31 seconds
Started Jul 23 06:47:48 PM PDT 24
Finished Jul 23 06:50:40 PM PDT 24
Peak memory 206796 kb
Host smart-86504df2-b454-44b5-8bfc-f71963b41766
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3157051625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.3157051625
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.4006926535
Short name T2370
Test name
Test status
Simulation time 183944566 ps
CPU time 0.85 seconds
Started Jul 23 06:47:58 PM PDT 24
Finished Jul 23 06:48:01 PM PDT 24
Peak memory 206668 kb
Host smart-87b3c090-8ddb-4646-9f73-f528aa451ac6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4006926535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.4006926535
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.2804705030
Short name T543
Test name
Test status
Simulation time 144922388 ps
CPU time 0.77 seconds
Started Jul 23 06:47:50 PM PDT 24
Finished Jul 23 06:47:54 PM PDT 24
Peak memory 206652 kb
Host smart-6e51dc3a-c08c-4942-8c45-67b667167cd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28047
05030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.2804705030
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.864001191
Short name T1557
Test name
Test status
Simulation time 239735761 ps
CPU time 1.02 seconds
Started Jul 23 06:47:59 PM PDT 24
Finished Jul 23 06:48:02 PM PDT 24
Peak memory 206736 kb
Host smart-45e26a4f-d991-4e13-a141-5456f6edc879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86400
1191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.864001191
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.3299872887
Short name T2399
Test name
Test status
Simulation time 191925976 ps
CPU time 0.93 seconds
Started Jul 23 06:47:58 PM PDT 24
Finished Jul 23 06:48:01 PM PDT 24
Peak memory 206772 kb
Host smart-e76bb1b6-6df2-430c-bb3c-7f8694d0f298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32998
72887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.3299872887
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.2821789190
Short name T2074
Test name
Test status
Simulation time 157435203 ps
CPU time 0.76 seconds
Started Jul 23 06:47:43 PM PDT 24
Finished Jul 23 06:47:51 PM PDT 24
Peak memory 206760 kb
Host smart-424a98a5-10d9-450e-b2ab-7f455bfdbfd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28217
89190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.2821789190
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.2977376920
Short name T982
Test name
Test status
Simulation time 178006820 ps
CPU time 0.79 seconds
Started Jul 23 06:48:01 PM PDT 24
Finished Jul 23 06:48:04 PM PDT 24
Peak memory 206760 kb
Host smart-cd21c645-f331-425e-82be-f7c5c4be5fae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29773
76920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.2977376920
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.3117534766
Short name T2017
Test name
Test status
Simulation time 153888199 ps
CPU time 0.77 seconds
Started Jul 23 06:47:51 PM PDT 24
Finished Jul 23 06:47:55 PM PDT 24
Peak memory 206584 kb
Host smart-73af6d74-bcb4-4c62-a865-29e9a3a065c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31175
34766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.3117534766
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.2911191962
Short name T209
Test name
Test status
Simulation time 256132318 ps
CPU time 0.91 seconds
Started Jul 23 06:47:44 PM PDT 24
Finished Jul 23 06:47:52 PM PDT 24
Peak memory 206772 kb
Host smart-b44bd344-2307-43a2-a3e7-974cd4fd7e0c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2911191962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.2911191962
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.2151758196
Short name T723
Test name
Test status
Simulation time 174146259 ps
CPU time 0.81 seconds
Started Jul 23 06:47:44 PM PDT 24
Finished Jul 23 06:47:51 PM PDT 24
Peak memory 206708 kb
Host smart-cff709c4-25cd-4fe0-8035-656748120bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21517
58196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.2151758196
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.3473696574
Short name T1479
Test name
Test status
Simulation time 57377645 ps
CPU time 0.66 seconds
Started Jul 23 06:47:57 PM PDT 24
Finished Jul 23 06:48:00 PM PDT 24
Peak memory 206580 kb
Host smart-d7ea0330-d4bd-426e-9468-8017e8dc6e4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34736
96574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.3473696574
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.3577873505
Short name T2077
Test name
Test status
Simulation time 7585827648 ps
CPU time 16.74 seconds
Started Jul 23 06:47:45 PM PDT 24
Finished Jul 23 06:48:08 PM PDT 24
Peak memory 206920 kb
Host smart-7a3a1cef-6561-45ff-9ecc-54de3bfb8383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35778
73505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.3577873505
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.3173007173
Short name T705
Test name
Test status
Simulation time 165212378 ps
CPU time 0.86 seconds
Started Jul 23 06:47:45 PM PDT 24
Finished Jul 23 06:47:53 PM PDT 24
Peak memory 206768 kb
Host smart-6568ecc1-b4e4-4454-b337-dc0a3fdd7058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31730
07173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.3173007173
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.4175805797
Short name T708
Test name
Test status
Simulation time 230820904 ps
CPU time 0.95 seconds
Started Jul 23 06:47:45 PM PDT 24
Finished Jul 23 06:47:52 PM PDT 24
Peak memory 206768 kb
Host smart-9fce13f2-0442-4d1b-b856-f88c5abe5be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41758
05797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.4175805797
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.3143339767
Short name T2698
Test name
Test status
Simulation time 234062509 ps
CPU time 0.98 seconds
Started Jul 23 06:48:07 PM PDT 24
Finished Jul 23 06:48:11 PM PDT 24
Peak memory 206748 kb
Host smart-ea23b5cd-a801-42e6-a56e-1d7f36b04d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31433
39767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.3143339767
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.959084530
Short name T2310
Test name
Test status
Simulation time 209599943 ps
CPU time 0.89 seconds
Started Jul 23 06:47:54 PM PDT 24
Finished Jul 23 06:47:58 PM PDT 24
Peak memory 206772 kb
Host smart-cd6d3f27-50b5-4909-be1c-e6cc5ac562a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95908
4530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.959084530
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.569985084
Short name T1289
Test name
Test status
Simulation time 157036234 ps
CPU time 0.86 seconds
Started Jul 23 06:47:44 PM PDT 24
Finished Jul 23 06:47:52 PM PDT 24
Peak memory 206752 kb
Host smart-0c8165f5-c6c9-4b5b-8788-37af5ce5b59c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56998
5084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.569985084
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.1375746648
Short name T777
Test name
Test status
Simulation time 150264843 ps
CPU time 0.75 seconds
Started Jul 23 06:47:52 PM PDT 24
Finished Jul 23 06:47:55 PM PDT 24
Peak memory 206792 kb
Host smart-e95a1bf4-4136-4cad-aeb7-e83f03cc39ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13757
46648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.1375746648
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.3458838114
Short name T1999
Test name
Test status
Simulation time 144130750 ps
CPU time 0.84 seconds
Started Jul 23 06:48:01 PM PDT 24
Finished Jul 23 06:48:04 PM PDT 24
Peak memory 206928 kb
Host smart-d5474db8-2a12-439d-9ec2-85e2c717eefa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34588
38114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.3458838114
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.3820866752
Short name T415
Test name
Test status
Simulation time 232781953 ps
CPU time 1.04 seconds
Started Jul 23 06:47:53 PM PDT 24
Finished Jul 23 06:47:57 PM PDT 24
Peak memory 206764 kb
Host smart-b3d318f2-03cd-42cd-9f4f-ba446156a051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38208
66752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.3820866752
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.778872408
Short name T640
Test name
Test status
Simulation time 4158050111 ps
CPU time 113.9 seconds
Started Jul 23 06:48:06 PM PDT 24
Finished Jul 23 06:50:02 PM PDT 24
Peak memory 206904 kb
Host smart-e9ae375e-aec9-4c19-b2ee-d2779890797c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=778872408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.778872408
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.232532758
Short name T2433
Test name
Test status
Simulation time 203389879 ps
CPU time 0.92 seconds
Started Jul 23 06:48:01 PM PDT 24
Finished Jul 23 06:48:04 PM PDT 24
Peak memory 206764 kb
Host smart-a62e679b-ef68-4fdd-b744-1c9bd64496d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23253
2758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.232532758
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.1923426835
Short name T869
Test name
Test status
Simulation time 183663077 ps
CPU time 0.79 seconds
Started Jul 23 06:48:00 PM PDT 24
Finished Jul 23 06:48:03 PM PDT 24
Peak memory 206748 kb
Host smart-f2419f53-5b81-4ff9-8257-5667cbd1c42c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19234
26835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.1923426835
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.4273013836
Short name T555
Test name
Test status
Simulation time 391263487 ps
CPU time 1.24 seconds
Started Jul 23 06:48:05 PM PDT 24
Finished Jul 23 06:48:09 PM PDT 24
Peak memory 206728 kb
Host smart-fa2004ef-209d-4df5-96ab-95a9cdbd4196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42730
13836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.4273013836
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.3636821814
Short name T1092
Test name
Test status
Simulation time 4522842767 ps
CPU time 34.11 seconds
Started Jul 23 06:47:51 PM PDT 24
Finished Jul 23 06:48:28 PM PDT 24
Peak memory 206980 kb
Host smart-07c257f1-3beb-4404-98cb-b0ff871c2bab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36368
21814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.3636821814
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.3538959873
Short name T2618
Test name
Test status
Simulation time 76844002 ps
CPU time 0.71 seconds
Started Jul 23 06:48:07 PM PDT 24
Finished Jul 23 06:48:11 PM PDT 24
Peak memory 206692 kb
Host smart-c665aec3-90dc-4152-bb40-5b6000a37f09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3538959873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.3538959873
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.789651789
Short name T1587
Test name
Test status
Simulation time 3360317827 ps
CPU time 4.21 seconds
Started Jul 23 06:48:04 PM PDT 24
Finished Jul 23 06:48:10 PM PDT 24
Peak memory 206796 kb
Host smart-69c3229f-2db3-438b-a07a-43983299982f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=789651789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.789651789
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.626285776
Short name T574
Test name
Test status
Simulation time 13320991848 ps
CPU time 13.81 seconds
Started Jul 23 06:47:59 PM PDT 24
Finished Jul 23 06:48:15 PM PDT 24
Peak memory 206896 kb
Host smart-ffb7ac35-71b1-43e1-b0bf-915ce4de58ae
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=626285776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.626285776
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.2767627252
Short name T1588
Test name
Test status
Simulation time 23460692227 ps
CPU time 30.54 seconds
Started Jul 23 06:48:06 PM PDT 24
Finished Jul 23 06:48:39 PM PDT 24
Peak memory 206956 kb
Host smart-3b8d0c50-4494-43e4-be38-7bc9dc7e8d45
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2767627252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.2767627252
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.1038417078
Short name T1000
Test name
Test status
Simulation time 157227842 ps
CPU time 0.77 seconds
Started Jul 23 06:47:52 PM PDT 24
Finished Jul 23 06:47:56 PM PDT 24
Peak memory 206756 kb
Host smart-a1f0d58a-fc4a-44a2-a988-eb898683a4b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10384
17078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.1038417078
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.2195306438
Short name T1051
Test name
Test status
Simulation time 140679328 ps
CPU time 0.75 seconds
Started Jul 23 06:47:51 PM PDT 24
Finished Jul 23 06:47:55 PM PDT 24
Peak memory 206740 kb
Host smart-46b20878-d132-4e20-a5cc-3da21fe01164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21953
06438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.2195306438
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.2135570006
Short name T2641
Test name
Test status
Simulation time 375044929 ps
CPU time 1.23 seconds
Started Jul 23 06:47:50 PM PDT 24
Finished Jul 23 06:47:55 PM PDT 24
Peak memory 206664 kb
Host smart-c5f721ee-dae5-4154-ad7c-4e46b742a374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21355
70006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.2135570006
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.2805800853
Short name T1219
Test name
Test status
Simulation time 1139190559 ps
CPU time 2.48 seconds
Started Jul 23 06:47:53 PM PDT 24
Finished Jul 23 06:47:58 PM PDT 24
Peak memory 206932 kb
Host smart-94488ebb-a754-49e7-8654-c67e03ec47bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28058
00853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.2805800853
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.1577791277
Short name T1776
Test name
Test status
Simulation time 10037150881 ps
CPU time 17.79 seconds
Started Jul 23 06:47:49 PM PDT 24
Finished Jul 23 06:48:11 PM PDT 24
Peak memory 206952 kb
Host smart-0a8df7fb-5130-4ef6-b5af-b44c6708f7eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15777
91277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.1577791277
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.3908644218
Short name T1813
Test name
Test status
Simulation time 523721322 ps
CPU time 1.54 seconds
Started Jul 23 06:47:56 PM PDT 24
Finished Jul 23 06:48:00 PM PDT 24
Peak memory 206740 kb
Host smart-423ede22-791a-441b-a851-81e3f00a25e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39086
44218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.3908644218
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.1550179562
Short name T704
Test name
Test status
Simulation time 206044223 ps
CPU time 0.81 seconds
Started Jul 23 06:48:03 PM PDT 24
Finished Jul 23 06:48:05 PM PDT 24
Peak memory 206720 kb
Host smart-403169f0-1b5d-4130-b5be-d6b0dcd691d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15501
79562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.1550179562
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.3064227430
Short name T357
Test name
Test status
Simulation time 35968423 ps
CPU time 0.68 seconds
Started Jul 23 06:47:54 PM PDT 24
Finished Jul 23 06:47:58 PM PDT 24
Peak memory 206744 kb
Host smart-848b27c1-f8c0-4b2b-9ec5-b1a455aa1f11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30642
27430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.3064227430
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.625150944
Short name T488
Test name
Test status
Simulation time 1035400546 ps
CPU time 2.16 seconds
Started Jul 23 06:48:06 PM PDT 24
Finished Jul 23 06:48:11 PM PDT 24
Peak memory 206676 kb
Host smart-b4dfebdb-b4b1-4565-beb8-ac80081570fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62515
0944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.625150944
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.2564535028
Short name T2217
Test name
Test status
Simulation time 331918313 ps
CPU time 2.3 seconds
Started Jul 23 06:48:17 PM PDT 24
Finished Jul 23 06:48:23 PM PDT 24
Peak memory 206892 kb
Host smart-a6aaae8d-ab43-4020-a00e-330852be327e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25645
35028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.2564535028
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.2174873913
Short name T667
Test name
Test status
Simulation time 244481192 ps
CPU time 0.93 seconds
Started Jul 23 06:48:06 PM PDT 24
Finished Jul 23 06:48:10 PM PDT 24
Peak memory 206768 kb
Host smart-82d11778-2aed-4913-9202-89926d719ada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21748
73913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.2174873913
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.2207055739
Short name T1340
Test name
Test status
Simulation time 149232495 ps
CPU time 0.74 seconds
Started Jul 23 06:47:54 PM PDT 24
Finished Jul 23 06:47:58 PM PDT 24
Peak memory 206760 kb
Host smart-d7df9454-a9ed-4a32-b2af-a88177ce2e8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22070
55739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.2207055739
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.3657592775
Short name T2578
Test name
Test status
Simulation time 215687911 ps
CPU time 0.86 seconds
Started Jul 23 06:47:55 PM PDT 24
Finished Jul 23 06:47:59 PM PDT 24
Peak memory 206784 kb
Host smart-41ce1e22-715f-4486-8885-cdaaaf95a3ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36575
92775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.3657592775
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_iso_retraction.1177110095
Short name T1992
Test name
Test status
Simulation time 12081367399 ps
CPU time 108.68 seconds
Started Jul 23 06:48:00 PM PDT 24
Finished Jul 23 06:49:51 PM PDT 24
Peak memory 206904 kb
Host smart-976a11a8-c4c3-472b-9215-908e2a495b72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11771
10095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.1177110095
Directory /workspace/47.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.3955865092
Short name T299
Test name
Test status
Simulation time 234758413 ps
CPU time 0.89 seconds
Started Jul 23 06:47:56 PM PDT 24
Finished Jul 23 06:48:00 PM PDT 24
Peak memory 206684 kb
Host smart-d15a4de0-7a7d-4662-8530-c17e002fb565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39558
65092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.3955865092
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.1459279340
Short name T1157
Test name
Test status
Simulation time 23276357779 ps
CPU time 22.2 seconds
Started Jul 23 06:48:07 PM PDT 24
Finished Jul 23 06:48:33 PM PDT 24
Peak memory 206828 kb
Host smart-0f9d8694-8b5b-4530-a093-c4941f88df3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14592
79340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.1459279340
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.1734726310
Short name T20
Test name
Test status
Simulation time 3331093005 ps
CPU time 4.05 seconds
Started Jul 23 06:47:58 PM PDT 24
Finished Jul 23 06:48:04 PM PDT 24
Peak memory 206760 kb
Host smart-49a26305-6c21-4843-a54e-3701a92a1b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17347
26310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.1734726310
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.3480862790
Short name T2546
Test name
Test status
Simulation time 9235052604 ps
CPU time 88.73 seconds
Started Jul 23 06:47:54 PM PDT 24
Finished Jul 23 06:49:26 PM PDT 24
Peak memory 206960 kb
Host smart-492d83df-c121-4992-a2f4-05dbe115a7d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34808
62790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.3480862790
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.2211000178
Short name T1208
Test name
Test status
Simulation time 5449471198 ps
CPU time 35.85 seconds
Started Jul 23 06:48:16 PM PDT 24
Finished Jul 23 06:48:55 PM PDT 24
Peak memory 206908 kb
Host smart-7cb57d78-f2ce-41ca-a0bd-4c3f763f2dcb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2211000178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.2211000178
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.266736993
Short name T1672
Test name
Test status
Simulation time 231591718 ps
CPU time 0.87 seconds
Started Jul 23 06:48:05 PM PDT 24
Finished Jul 23 06:48:09 PM PDT 24
Peak memory 206736 kb
Host smart-d4daa8b4-3b6c-467a-a5cb-bd63448cd6ec
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=266736993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.266736993
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.4012545342
Short name T347
Test name
Test status
Simulation time 186613272 ps
CPU time 0.87 seconds
Started Jul 23 06:48:05 PM PDT 24
Finished Jul 23 06:48:08 PM PDT 24
Peak memory 206740 kb
Host smart-f4d1fa94-9b48-4e4c-b693-7f339b1f1d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40125
45342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.4012545342
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.2115481871
Short name T158
Test name
Test status
Simulation time 3249084230 ps
CPU time 22.41 seconds
Started Jul 23 06:47:56 PM PDT 24
Finished Jul 23 06:48:21 PM PDT 24
Peak memory 206896 kb
Host smart-ebc44af2-4168-4a49-8456-6affd085577e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21154
81871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.2115481871
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.498944825
Short name T1441
Test name
Test status
Simulation time 4380867606 ps
CPU time 40.03 seconds
Started Jul 23 06:48:15 PM PDT 24
Finished Jul 23 06:48:58 PM PDT 24
Peak memory 206880 kb
Host smart-3c3bcd99-5a1f-4bb7-ad2e-688a39106499
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=498944825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.498944825
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.2199008194
Short name T300
Test name
Test status
Simulation time 167486948 ps
CPU time 0.83 seconds
Started Jul 23 06:48:03 PM PDT 24
Finished Jul 23 06:48:06 PM PDT 24
Peak memory 206768 kb
Host smart-57d0d444-4a0b-4d36-baa5-b2cd40b50889
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2199008194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.2199008194
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.3599515844
Short name T1178
Test name
Test status
Simulation time 144682960 ps
CPU time 0.8 seconds
Started Jul 23 06:48:17 PM PDT 24
Finished Jul 23 06:48:22 PM PDT 24
Peak memory 206744 kb
Host smart-788c4492-82dc-49df-b490-68fd9144f240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35995
15844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.3599515844
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.2481010046
Short name T128
Test name
Test status
Simulation time 204269525 ps
CPU time 0.91 seconds
Started Jul 23 06:48:01 PM PDT 24
Finished Jul 23 06:48:04 PM PDT 24
Peak memory 206764 kb
Host smart-2dd464ab-c31c-4179-914d-ae72bb7ea445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24810
10046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.2481010046
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.60578705
Short name T806
Test name
Test status
Simulation time 176075344 ps
CPU time 0.89 seconds
Started Jul 23 06:48:05 PM PDT 24
Finished Jul 23 06:48:09 PM PDT 24
Peak memory 206712 kb
Host smart-cf75634c-f486-4689-a4ee-9ab4f92edde6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60578
705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.60578705
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.1717026644
Short name T468
Test name
Test status
Simulation time 151741206 ps
CPU time 0.81 seconds
Started Jul 23 06:48:01 PM PDT 24
Finished Jul 23 06:48:04 PM PDT 24
Peak memory 206692 kb
Host smart-afe5a408-3130-4d1c-922c-d5af192feb98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17170
26644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.1717026644
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.3108061698
Short name T1383
Test name
Test status
Simulation time 161418453 ps
CPU time 0.76 seconds
Started Jul 23 06:48:16 PM PDT 24
Finished Jul 23 06:48:20 PM PDT 24
Peak memory 206744 kb
Host smart-a53aed27-d0fd-49f0-a3f5-8e8429ecb3a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31080
61698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.3108061698
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.559494825
Short name T2139
Test name
Test status
Simulation time 149559233 ps
CPU time 0.77 seconds
Started Jul 23 06:48:02 PM PDT 24
Finished Jul 23 06:48:05 PM PDT 24
Peak memory 206696 kb
Host smart-abc96959-e574-49c8-80e7-198002dca046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55949
4825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.559494825
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.2161852668
Short name T2519
Test name
Test status
Simulation time 261302559 ps
CPU time 0.99 seconds
Started Jul 23 06:48:07 PM PDT 24
Finished Jul 23 06:48:11 PM PDT 24
Peak memory 206768 kb
Host smart-80da06af-9aa2-44a6-b972-ee45576d1f12
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2161852668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.2161852668
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.3853643237
Short name T1655
Test name
Test status
Simulation time 146791337 ps
CPU time 0.83 seconds
Started Jul 23 06:48:12 PM PDT 24
Finished Jul 23 06:48:14 PM PDT 24
Peak memory 206752 kb
Host smart-db955a54-754c-4564-9136-c86e6249f7ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38536
43237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.3853643237
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.419054153
Short name T31
Test name
Test status
Simulation time 85445473 ps
CPU time 0.71 seconds
Started Jul 23 06:48:13 PM PDT 24
Finished Jul 23 06:48:16 PM PDT 24
Peak memory 206768 kb
Host smart-6eb7a4e3-7ad2-4b42-9fae-4a6862e46eac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41905
4153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.419054153
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.4136043539
Short name T1893
Test name
Test status
Simulation time 12380633306 ps
CPU time 25.52 seconds
Started Jul 23 06:48:14 PM PDT 24
Finished Jul 23 06:48:42 PM PDT 24
Peak memory 206976 kb
Host smart-83a64e10-ca14-4c00-a506-3b6222a697ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41360
43539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.4136043539
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.503842124
Short name T2735
Test name
Test status
Simulation time 165687318 ps
CPU time 0.86 seconds
Started Jul 23 06:48:05 PM PDT 24
Finished Jul 23 06:48:09 PM PDT 24
Peak memory 206708 kb
Host smart-490ea23a-fe76-46b8-bb4a-c679c05dfa9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50384
2124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.503842124
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.4232263970
Short name T1649
Test name
Test status
Simulation time 252620907 ps
CPU time 0.93 seconds
Started Jul 23 06:48:14 PM PDT 24
Finished Jul 23 06:48:17 PM PDT 24
Peak memory 206744 kb
Host smart-c59b4825-68ef-4f36-8291-d9f77ad56991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42322
63970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.4232263970
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.2391024028
Short name T2734
Test name
Test status
Simulation time 223744576 ps
CPU time 0.88 seconds
Started Jul 23 06:48:02 PM PDT 24
Finished Jul 23 06:48:05 PM PDT 24
Peak memory 206752 kb
Host smart-c6804b8a-2712-401b-9fd1-350d2a2d813e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23910
24028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.2391024028
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.1220335946
Short name T328
Test name
Test status
Simulation time 210156913 ps
CPU time 0.86 seconds
Started Jul 23 06:48:07 PM PDT 24
Finished Jul 23 06:48:11 PM PDT 24
Peak memory 206756 kb
Host smart-53c6cfd9-1a5a-4729-ae0e-67f26aef7886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12203
35946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.1220335946
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.1784940118
Short name T1484
Test name
Test status
Simulation time 132771454 ps
CPU time 0.84 seconds
Started Jul 23 06:48:06 PM PDT 24
Finished Jul 23 06:48:10 PM PDT 24
Peak memory 206736 kb
Host smart-7b88cb60-09f2-47d9-830a-7f04a7bdbbaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17849
40118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.1784940118
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.3459241970
Short name T440
Test name
Test status
Simulation time 208193588 ps
CPU time 0.89 seconds
Started Jul 23 06:48:06 PM PDT 24
Finished Jul 23 06:48:09 PM PDT 24
Peak memory 206764 kb
Host smart-be21cb80-2633-4c08-99e0-0d2944eaa204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34592
41970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.3459241970
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.3453985927
Short name T1523
Test name
Test status
Simulation time 215062837 ps
CPU time 0.84 seconds
Started Jul 23 06:48:03 PM PDT 24
Finished Jul 23 06:48:06 PM PDT 24
Peak memory 206768 kb
Host smart-f7c85848-065c-4116-a5d2-0e7aff510ec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34539
85927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.3453985927
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.237439761
Short name T2293
Test name
Test status
Simulation time 297334981 ps
CPU time 0.98 seconds
Started Jul 23 06:48:20 PM PDT 24
Finished Jul 23 06:48:25 PM PDT 24
Peak memory 206748 kb
Host smart-4582770e-30ac-41e6-9397-c8e8d9e10c93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23743
9761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.237439761
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.3341546086
Short name T1916
Test name
Test status
Simulation time 3884281705 ps
CPU time 108.82 seconds
Started Jul 23 06:48:06 PM PDT 24
Finished Jul 23 06:49:57 PM PDT 24
Peak memory 206888 kb
Host smart-a7e7982f-ee88-4f6c-ba19-4db754c8872b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3341546086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.3341546086
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.639591561
Short name T2089
Test name
Test status
Simulation time 225760072 ps
CPU time 0.92 seconds
Started Jul 23 06:48:08 PM PDT 24
Finished Jul 23 06:48:12 PM PDT 24
Peak memory 206756 kb
Host smart-30317c41-f67f-44b0-80fc-bc037ea7799a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63959
1561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.639591561
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.1763430657
Short name T2707
Test name
Test status
Simulation time 195548064 ps
CPU time 0.95 seconds
Started Jul 23 06:48:08 PM PDT 24
Finished Jul 23 06:48:12 PM PDT 24
Peak memory 206760 kb
Host smart-a96adc04-02c3-4898-8538-649b85a02e38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17634
30657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.1763430657
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.74049173
Short name T2111
Test name
Test status
Simulation time 526551855 ps
CPU time 1.27 seconds
Started Jul 23 06:48:17 PM PDT 24
Finished Jul 23 06:48:22 PM PDT 24
Peak memory 206760 kb
Host smart-76c8dd28-258b-4bcb-adf9-17bb764bb520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74049
173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.74049173
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.251117631
Short name T1624
Test name
Test status
Simulation time 5689903951 ps
CPU time 51.23 seconds
Started Jul 23 06:48:11 PM PDT 24
Finished Jul 23 06:49:04 PM PDT 24
Peak memory 206736 kb
Host smart-3fbdd165-e125-4833-b46e-95cf047e5b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25111
7631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.251117631
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.436143331
Short name T1673
Test name
Test status
Simulation time 37029133 ps
CPU time 0.69 seconds
Started Jul 23 06:48:18 PM PDT 24
Finished Jul 23 06:48:23 PM PDT 24
Peak memory 206692 kb
Host smart-7a1a7b48-8bf4-4c1c-aabe-cf1b72ae538a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=436143331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.436143331
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.1183629755
Short name T2695
Test name
Test status
Simulation time 3877243392 ps
CPU time 4.17 seconds
Started Jul 23 06:48:12 PM PDT 24
Finished Jul 23 06:48:18 PM PDT 24
Peak memory 206820 kb
Host smart-82ad2d96-ec50-4541-9bb4-e9287b26a965
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1183629755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.1183629755
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.1676153156
Short name T2513
Test name
Test status
Simulation time 13328685424 ps
CPU time 14.16 seconds
Started Jul 23 06:48:19 PM PDT 24
Finished Jul 23 06:48:38 PM PDT 24
Peak memory 206816 kb
Host smart-911e48f1-a313-496e-a58a-a0268d3930bc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1676153156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.1676153156
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.3598977873
Short name T656
Test name
Test status
Simulation time 23396559450 ps
CPU time 30.1 seconds
Started Jul 23 06:48:11 PM PDT 24
Finished Jul 23 06:48:43 PM PDT 24
Peak memory 206824 kb
Host smart-7d9f04b5-ce63-4982-9385-b8e729a61a1b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3598977873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.3598977873
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.900197878
Short name T462
Test name
Test status
Simulation time 185104216 ps
CPU time 0.84 seconds
Started Jul 23 06:48:14 PM PDT 24
Finished Jul 23 06:48:18 PM PDT 24
Peak memory 206764 kb
Host smart-185636c5-8460-41dc-a004-4837db2c2c27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90019
7878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.900197878
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.2571304640
Short name T1397
Test name
Test status
Simulation time 155193074 ps
CPU time 0.78 seconds
Started Jul 23 06:48:09 PM PDT 24
Finished Jul 23 06:48:12 PM PDT 24
Peak memory 206764 kb
Host smart-46291f53-68cc-4483-b1f6-459cfe2baf16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25713
04640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.2571304640
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.680533374
Short name T1521
Test name
Test status
Simulation time 334801645 ps
CPU time 1.15 seconds
Started Jul 23 06:48:10 PM PDT 24
Finished Jul 23 06:48:13 PM PDT 24
Peak memory 206772 kb
Host smart-d947a77c-69da-4922-94e3-cf7eb68b3d6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68053
3374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.680533374
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.441728500
Short name T592
Test name
Test status
Simulation time 928448312 ps
CPU time 2.46 seconds
Started Jul 23 06:48:14 PM PDT 24
Finished Jul 23 06:48:19 PM PDT 24
Peak memory 206844 kb
Host smart-4bd6a1d6-60ad-475c-8258-2c34fa3c5b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44172
8500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.441728500
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.4174779537
Short name T1284
Test name
Test status
Simulation time 12469450300 ps
CPU time 25.49 seconds
Started Jul 23 06:48:16 PM PDT 24
Finished Jul 23 06:48:44 PM PDT 24
Peak memory 206932 kb
Host smart-0c074414-449c-4c14-a02f-b4fc3bc116e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41747
79537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.4174779537
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.3417342947
Short name T2220
Test name
Test status
Simulation time 407392136 ps
CPU time 1.28 seconds
Started Jul 23 06:48:11 PM PDT 24
Finished Jul 23 06:48:14 PM PDT 24
Peak memory 206760 kb
Host smart-eba63c7a-c857-4653-b142-9b7b17ba1f4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34173
42947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.3417342947
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.682589495
Short name T2338
Test name
Test status
Simulation time 135661535 ps
CPU time 0.74 seconds
Started Jul 23 06:48:18 PM PDT 24
Finished Jul 23 06:48:23 PM PDT 24
Peak memory 206760 kb
Host smart-085f1585-43f8-48ee-b340-aa2e17e8644f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68258
9495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.682589495
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.3102750901
Short name T2023
Test name
Test status
Simulation time 45757094 ps
CPU time 0.68 seconds
Started Jul 23 06:48:08 PM PDT 24
Finished Jul 23 06:48:11 PM PDT 24
Peak memory 206752 kb
Host smart-4aa1727b-1058-4d68-82d8-0ab4193e765c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31027
50901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.3102750901
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.974374280
Short name T741
Test name
Test status
Simulation time 916919587 ps
CPU time 2.15 seconds
Started Jul 23 06:48:11 PM PDT 24
Finished Jul 23 06:48:15 PM PDT 24
Peak memory 206844 kb
Host smart-f646f506-c3fd-4520-8533-e66dad5ffb91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97437
4280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.974374280
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.3672045843
Short name T2189
Test name
Test status
Simulation time 202620612 ps
CPU time 2.11 seconds
Started Jul 23 06:48:14 PM PDT 24
Finished Jul 23 06:48:19 PM PDT 24
Peak memory 206844 kb
Host smart-409dde85-0a5d-4c27-81fc-2614108018b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36720
45843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.3672045843
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.4118779488
Short name T453
Test name
Test status
Simulation time 214516779 ps
CPU time 0.89 seconds
Started Jul 23 06:48:14 PM PDT 24
Finished Jul 23 06:48:17 PM PDT 24
Peak memory 206768 kb
Host smart-51765ca7-4894-476e-9df4-1ca5b6ff4869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41187
79488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.4118779488
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.4015640475
Short name T2258
Test name
Test status
Simulation time 167006306 ps
CPU time 0.79 seconds
Started Jul 23 06:48:15 PM PDT 24
Finished Jul 23 06:48:19 PM PDT 24
Peak memory 206744 kb
Host smart-88bd15f6-5fd4-441b-85b3-0b57cd6adbc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40156
40475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.4015640475
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.1452473937
Short name T1465
Test name
Test status
Simulation time 168028460 ps
CPU time 0.83 seconds
Started Jul 23 06:48:15 PM PDT 24
Finished Jul 23 06:48:18 PM PDT 24
Peak memory 206696 kb
Host smart-aef5866e-a846-4791-8f28-4e843936f684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14524
73937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.1452473937
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.1165980082
Short name T217
Test name
Test status
Simulation time 10567729037 ps
CPU time 290.34 seconds
Started Jul 23 06:48:17 PM PDT 24
Finished Jul 23 06:53:11 PM PDT 24
Peak memory 206892 kb
Host smart-bedc66e0-9d6e-4003-8e9e-6a5a9b1b1875
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1165980082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.1165980082
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_iso_retraction.4131798125
Short name T1617
Test name
Test status
Simulation time 10915274607 ps
CPU time 43.5 seconds
Started Jul 23 06:48:17 PM PDT 24
Finished Jul 23 06:49:05 PM PDT 24
Peak memory 206980 kb
Host smart-1944fafe-745b-4103-95cb-9d06a6e5d554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41317
98125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_iso_retraction.4131798125
Directory /workspace/48.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.1892693760
Short name T810
Test name
Test status
Simulation time 189594506 ps
CPU time 0.82 seconds
Started Jul 23 06:48:17 PM PDT 24
Finished Jul 23 06:48:22 PM PDT 24
Peak memory 206764 kb
Host smart-e76e7e1a-4925-470d-9ef4-2131f46f915c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18926
93760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.1892693760
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.1459185210
Short name T1731
Test name
Test status
Simulation time 23337850134 ps
CPU time 30.82 seconds
Started Jul 23 06:48:17 PM PDT 24
Finished Jul 23 06:48:52 PM PDT 24
Peak memory 206816 kb
Host smart-607d805c-2e46-4896-befc-aa0834fd2c9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14591
85210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.1459185210
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.3777766924
Short name T2580
Test name
Test status
Simulation time 3301299119 ps
CPU time 3.94 seconds
Started Jul 23 06:48:22 PM PDT 24
Finished Jul 23 06:48:32 PM PDT 24
Peak memory 206812 kb
Host smart-804042d1-c804-4fd2-bc56-349d9f356062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37777
66924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.3777766924
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.1666371447
Short name T2704
Test name
Test status
Simulation time 5958865717 ps
CPU time 56.09 seconds
Started Jul 23 06:48:12 PM PDT 24
Finished Jul 23 06:49:10 PM PDT 24
Peak memory 206936 kb
Host smart-69c53bee-fe0b-4974-898a-3e9a527338da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16663
71447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.1666371447
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.4113581651
Short name T1895
Test name
Test status
Simulation time 3284147435 ps
CPU time 29.85 seconds
Started Jul 23 06:48:14 PM PDT 24
Finished Jul 23 06:48:47 PM PDT 24
Peak memory 206896 kb
Host smart-8da78977-ff86-4612-ad6f-f57ed4f61980
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4113581651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.4113581651
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.2234619344
Short name T2092
Test name
Test status
Simulation time 276722689 ps
CPU time 0.9 seconds
Started Jul 23 06:48:14 PM PDT 24
Finished Jul 23 06:48:18 PM PDT 24
Peak memory 206872 kb
Host smart-23faa5d4-a73e-4614-b2fb-f721a9d2f4fe
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2234619344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.2234619344
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.1594758719
Short name T2246
Test name
Test status
Simulation time 227712912 ps
CPU time 0.86 seconds
Started Jul 23 06:48:22 PM PDT 24
Finished Jul 23 06:48:29 PM PDT 24
Peak memory 206768 kb
Host smart-12c42489-4355-4c80-a869-70c07ab7e98a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15947
58719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.1594758719
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.3689808962
Short name T1531
Test name
Test status
Simulation time 5884341942 ps
CPU time 41.64 seconds
Started Jul 23 06:48:22 PM PDT 24
Finished Jul 23 06:49:10 PM PDT 24
Peak memory 206896 kb
Host smart-bc8dcb48-ab7b-4790-bd79-60fd4490a07a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36898
08962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.3689808962
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.861934949
Short name T171
Test name
Test status
Simulation time 4787440226 ps
CPU time 130.72 seconds
Started Jul 23 06:48:22 PM PDT 24
Finished Jul 23 06:50:40 PM PDT 24
Peak memory 206916 kb
Host smart-100cc313-3275-4971-bd99-84e9e629f11d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=861934949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.861934949
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.92089362
Short name T1426
Test name
Test status
Simulation time 148928475 ps
CPU time 0.76 seconds
Started Jul 23 06:48:21 PM PDT 24
Finished Jul 23 06:48:27 PM PDT 24
Peak memory 206752 kb
Host smart-70b5feed-d357-498e-a5ef-088427883478
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=92089362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.92089362
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.3463927536
Short name T2330
Test name
Test status
Simulation time 152382735 ps
CPU time 0.76 seconds
Started Jul 23 06:48:17 PM PDT 24
Finished Jul 23 06:48:21 PM PDT 24
Peak memory 206768 kb
Host smart-033d1c34-7aa7-4fe1-abeb-e5243455617f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34639
27536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.3463927536
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.3569630141
Short name T2385
Test name
Test status
Simulation time 193897412 ps
CPU time 0.84 seconds
Started Jul 23 06:48:14 PM PDT 24
Finished Jul 23 06:48:17 PM PDT 24
Peak memory 206776 kb
Host smart-eae4dcd2-60d1-4461-a84d-b5614729739c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35696
30141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.3569630141
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.1622033809
Short name T935
Test name
Test status
Simulation time 224822837 ps
CPU time 0.98 seconds
Started Jul 23 06:48:16 PM PDT 24
Finished Jul 23 06:48:21 PM PDT 24
Peak memory 206764 kb
Host smart-79ab2a34-ec3e-43a5-82bc-7db47ad0a76c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16220
33809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.1622033809
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.783462040
Short name T1469
Test name
Test status
Simulation time 170676788 ps
CPU time 0.8 seconds
Started Jul 23 06:48:14 PM PDT 24
Finished Jul 23 06:48:17 PM PDT 24
Peak memory 206768 kb
Host smart-f129eaf5-59dd-4488-9c93-44db98a46b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78346
2040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.783462040
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.3492412733
Short name T2565
Test name
Test status
Simulation time 153722076 ps
CPU time 0.83 seconds
Started Jul 23 06:48:21 PM PDT 24
Finished Jul 23 06:48:27 PM PDT 24
Peak memory 206712 kb
Host smart-4099cca6-8c5d-470e-ba6d-b3694fb516f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34924
12733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.3492412733
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.614843509
Short name T1586
Test name
Test status
Simulation time 165497982 ps
CPU time 0.83 seconds
Started Jul 23 06:48:16 PM PDT 24
Finished Jul 23 06:48:20 PM PDT 24
Peak memory 206768 kb
Host smart-9ab13dbb-6b92-4b44-b7b5-644969068a1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61484
3509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.614843509
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.599300180
Short name T1343
Test name
Test status
Simulation time 227168730 ps
CPU time 0.92 seconds
Started Jul 23 06:48:14 PM PDT 24
Finished Jul 23 06:48:17 PM PDT 24
Peak memory 206752 kb
Host smart-e4938ecf-3ddf-40fd-9684-e503c18addf3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=599300180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.599300180
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.2028492458
Short name T650
Test name
Test status
Simulation time 156252799 ps
CPU time 0.79 seconds
Started Jul 23 06:48:15 PM PDT 24
Finished Jul 23 06:48:19 PM PDT 24
Peak memory 206692 kb
Host smart-42058412-5bb0-48ed-869c-ff4ecbb017e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20284
92458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.2028492458
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.2197244366
Short name T2305
Test name
Test status
Simulation time 33199589 ps
CPU time 0.68 seconds
Started Jul 23 06:48:13 PM PDT 24
Finished Jul 23 06:48:15 PM PDT 24
Peak memory 206748 kb
Host smart-ccab3ae4-6507-4a48-ae5c-c06b97485ae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21972
44366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.2197244366
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.2449593641
Short name T1558
Test name
Test status
Simulation time 18594537161 ps
CPU time 42.88 seconds
Started Jul 23 06:48:23 PM PDT 24
Finished Jul 23 06:49:12 PM PDT 24
Peak memory 206940 kb
Host smart-ee9f248d-73e7-400f-a3a1-d853da439e20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24495
93641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.2449593641
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.2196603540
Short name T2372
Test name
Test status
Simulation time 147780246 ps
CPU time 0.84 seconds
Started Jul 23 06:48:23 PM PDT 24
Finished Jul 23 06:48:31 PM PDT 24
Peak memory 206772 kb
Host smart-d033cd5e-b360-40cc-8961-d6eb7d74dbc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21966
03540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.2196603540
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.3158135478
Short name T2279
Test name
Test status
Simulation time 159633319 ps
CPU time 0.83 seconds
Started Jul 23 06:48:15 PM PDT 24
Finished Jul 23 06:48:19 PM PDT 24
Peak memory 206796 kb
Host smart-87ac8bbf-a6a7-4dfb-a2f5-f38c2d2102ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31581
35478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.3158135478
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.139324366
Short name T2204
Test name
Test status
Simulation time 187247137 ps
CPU time 0.83 seconds
Started Jul 23 06:48:20 PM PDT 24
Finished Jul 23 06:48:27 PM PDT 24
Peak memory 206752 kb
Host smart-90a7f7b4-4691-4506-bb71-4b85f722b472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13932
4366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.139324366
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.1525333656
Short name T396
Test name
Test status
Simulation time 195453670 ps
CPU time 0.89 seconds
Started Jul 23 06:48:15 PM PDT 24
Finished Jul 23 06:48:18 PM PDT 24
Peak memory 206880 kb
Host smart-36b5c45a-9223-43dd-abc6-c2c5aaa163b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15253
33656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.1525333656
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.597116677
Short name T19
Test name
Test status
Simulation time 189312481 ps
CPU time 0.84 seconds
Started Jul 23 06:48:16 PM PDT 24
Finished Jul 23 06:48:20 PM PDT 24
Peak memory 206744 kb
Host smart-d7e8301c-2f6e-4ae2-9dcd-e03f3f693ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59711
6677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.597116677
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.3910135470
Short name T2514
Test name
Test status
Simulation time 159328155 ps
CPU time 0.79 seconds
Started Jul 23 06:48:15 PM PDT 24
Finished Jul 23 06:48:18 PM PDT 24
Peak memory 206768 kb
Host smart-236f8d14-a3cf-4306-b03a-de897f6d82a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39101
35470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.3910135470
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.2152761034
Short name T652
Test name
Test status
Simulation time 151315867 ps
CPU time 0.79 seconds
Started Jul 23 06:48:22 PM PDT 24
Finished Jul 23 06:48:29 PM PDT 24
Peak memory 206732 kb
Host smart-fe70dec4-d02e-46a7-8139-669f3539c8ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21527
61034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.2152761034
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.1090275433
Short name T1896
Test name
Test status
Simulation time 219983421 ps
CPU time 0.94 seconds
Started Jul 23 06:48:22 PM PDT 24
Finished Jul 23 06:48:30 PM PDT 24
Peak memory 206740 kb
Host smart-58477d7a-25fe-4e1d-94f4-eeaaecad17b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10902
75433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1090275433
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.3605511369
Short name T1458
Test name
Test status
Simulation time 4321215195 ps
CPU time 114.7 seconds
Started Jul 23 06:48:21 PM PDT 24
Finished Jul 23 06:50:21 PM PDT 24
Peak memory 206872 kb
Host smart-bd3ff555-6bd6-4d0c-b1f0-eaeb5b6820e1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3605511369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.3605511369
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.1162799215
Short name T1265
Test name
Test status
Simulation time 182715017 ps
CPU time 0.79 seconds
Started Jul 23 06:48:18 PM PDT 24
Finished Jul 23 06:48:23 PM PDT 24
Peak memory 206732 kb
Host smart-a80ccf3d-6572-447c-b7fc-3754e1723b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11627
99215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.1162799215
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.1152026352
Short name T1186
Test name
Test status
Simulation time 188969190 ps
CPU time 0.85 seconds
Started Jul 23 06:48:18 PM PDT 24
Finished Jul 23 06:48:23 PM PDT 24
Peak memory 206756 kb
Host smart-afe96163-9ccb-4e9c-8abe-4cb6132165b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11520
26352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.1152026352
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.2744493514
Short name T434
Test name
Test status
Simulation time 1203133460 ps
CPU time 2.54 seconds
Started Jul 23 06:48:23 PM PDT 24
Finished Jul 23 06:48:33 PM PDT 24
Peak memory 206924 kb
Host smart-667ed209-126d-46b8-a863-562fdb9472ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27444
93514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.2744493514
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.1720176866
Short name T1216
Test name
Test status
Simulation time 4408207894 ps
CPU time 119.48 seconds
Started Jul 23 06:48:24 PM PDT 24
Finished Jul 23 06:50:32 PM PDT 24
Peak memory 206908 kb
Host smart-e8eae319-3297-401d-ab67-d8dbb6810686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17201
76866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.1720176866
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.1883595585
Short name T2102
Test name
Test status
Simulation time 103234458 ps
CPU time 0.74 seconds
Started Jul 23 06:48:23 PM PDT 24
Finished Jul 23 06:48:32 PM PDT 24
Peak memory 206756 kb
Host smart-b26e4a71-f252-46dc-9ecc-5a4ec4ed333e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1883595585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.1883595585
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.1288911107
Short name T1726
Test name
Test status
Simulation time 3445621619 ps
CPU time 3.85 seconds
Started Jul 23 06:48:17 PM PDT 24
Finished Jul 23 06:48:25 PM PDT 24
Peak memory 206952 kb
Host smart-53c86376-aa67-4f96-9c9d-98a88e21489c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1288911107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.1288911107
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.2361982344
Short name T839
Test name
Test status
Simulation time 13350759871 ps
CPU time 12.61 seconds
Started Jul 23 06:48:22 PM PDT 24
Finished Jul 23 06:48:41 PM PDT 24
Peak memory 206976 kb
Host smart-bf5f8986-eb08-4e20-a349-71cd34090314
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2361982344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.2361982344
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.381419724
Short name T1640
Test name
Test status
Simulation time 23370228105 ps
CPU time 27.11 seconds
Started Jul 23 06:48:20 PM PDT 24
Finished Jul 23 06:48:52 PM PDT 24
Peak memory 206824 kb
Host smart-513abf98-c204-4c6c-a979-9648570e1109
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=381419724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.381419724
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.1096107455
Short name T1920
Test name
Test status
Simulation time 179049851 ps
CPU time 0.82 seconds
Started Jul 23 06:48:23 PM PDT 24
Finished Jul 23 06:48:32 PM PDT 24
Peak memory 206740 kb
Host smart-53a3c93a-2d34-4932-92d9-cb0161f5a9f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10961
07455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.1096107455
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.2404598458
Short name T1260
Test name
Test status
Simulation time 168208328 ps
CPU time 0.79 seconds
Started Jul 23 06:48:22 PM PDT 24
Finished Jul 23 06:48:29 PM PDT 24
Peak memory 206760 kb
Host smart-9d832b01-1161-4091-990d-0133bf02f865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24045
98458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.2404598458
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.3488527675
Short name T999
Test name
Test status
Simulation time 233169309 ps
CPU time 1.02 seconds
Started Jul 23 06:48:26 PM PDT 24
Finished Jul 23 06:48:37 PM PDT 24
Peak memory 206716 kb
Host smart-be5f29ca-a8d9-4062-b3e7-d09856c900ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34885
27675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.3488527675
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.2059804918
Short name T1764
Test name
Test status
Simulation time 857576418 ps
CPU time 2 seconds
Started Jul 23 06:48:20 PM PDT 24
Finished Jul 23 06:48:26 PM PDT 24
Peak memory 206864 kb
Host smart-54193d67-2b23-4925-a3aa-7989b5248797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20598
04918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.2059804918
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.1541615279
Short name T2047
Test name
Test status
Simulation time 8839617098 ps
CPU time 16.36 seconds
Started Jul 23 06:48:19 PM PDT 24
Finished Jul 23 06:48:41 PM PDT 24
Peak memory 206936 kb
Host smart-b4c820ee-7b66-4f4d-8b85-ae0a83adaf5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15416
15279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.1541615279
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.3585755689
Short name T1229
Test name
Test status
Simulation time 351188795 ps
CPU time 1.17 seconds
Started Jul 23 06:48:24 PM PDT 24
Finished Jul 23 06:48:33 PM PDT 24
Peak memory 206768 kb
Host smart-2ce9dc91-f852-4318-8467-984c9d984b4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35857
55689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.3585755689
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.1563166554
Short name T1236
Test name
Test status
Simulation time 138023242 ps
CPU time 0.75 seconds
Started Jul 23 06:48:17 PM PDT 24
Finished Jul 23 06:48:21 PM PDT 24
Peak memory 206764 kb
Host smart-e3c31a9b-b960-4be2-b6c9-916fb2701b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15631
66554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.1563166554
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.2950105902
Short name T2520
Test name
Test status
Simulation time 37020394 ps
CPU time 0.7 seconds
Started Jul 23 06:48:22 PM PDT 24
Finished Jul 23 06:48:30 PM PDT 24
Peak memory 206748 kb
Host smart-96516e1a-7bf0-46ef-8b56-eabf655f62bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29501
05902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.2950105902
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.1413766079
Short name T1060
Test name
Test status
Simulation time 889883230 ps
CPU time 2.07 seconds
Started Jul 23 06:48:23 PM PDT 24
Finished Jul 23 06:48:33 PM PDT 24
Peak memory 206896 kb
Host smart-cb92c9ab-b7b0-440d-aaec-534e6d746326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14137
66079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.1413766079
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.46074173
Short name T1605
Test name
Test status
Simulation time 368113489 ps
CPU time 2.39 seconds
Started Jul 23 06:48:22 PM PDT 24
Finished Jul 23 06:48:31 PM PDT 24
Peak memory 206900 kb
Host smart-8feabfaa-9dce-47eb-856e-f07f3988cd48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46074
173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.46074173
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.4033074953
Short name T695
Test name
Test status
Simulation time 226984851 ps
CPU time 0.92 seconds
Started Jul 23 06:48:21 PM PDT 24
Finished Jul 23 06:48:29 PM PDT 24
Peak memory 206752 kb
Host smart-9256813d-f129-4241-a991-c9a142e7f1e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40330
74953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.4033074953
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.2963440113
Short name T831
Test name
Test status
Simulation time 142886552 ps
CPU time 0.74 seconds
Started Jul 23 06:48:20 PM PDT 24
Finished Jul 23 06:48:27 PM PDT 24
Peak memory 206884 kb
Host smart-59d28d4f-6941-4d0f-9504-ef517bf0f10e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29634
40113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.2963440113
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.2529971372
Short name T1885
Test name
Test status
Simulation time 220377592 ps
CPU time 0.89 seconds
Started Jul 23 06:48:36 PM PDT 24
Finished Jul 23 06:48:44 PM PDT 24
Peak memory 206728 kb
Host smart-0a7b823d-4874-41c1-8217-08b40f77c00a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25299
71372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.2529971372
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_iso_retraction.1833340837
Short name T819
Test name
Test status
Simulation time 10726140907 ps
CPU time 91.66 seconds
Started Jul 23 06:48:21 PM PDT 24
Finished Jul 23 06:50:06 PM PDT 24
Peak memory 207032 kb
Host smart-16172df0-6000-40ff-85c2-15995fba684e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18333
40837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_iso_retraction.1833340837
Directory /workspace/49.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.2012612792
Short name T1239
Test name
Test status
Simulation time 172924478 ps
CPU time 0.78 seconds
Started Jul 23 06:48:34 PM PDT 24
Finished Jul 23 06:48:43 PM PDT 24
Peak memory 206700 kb
Host smart-90b23f58-855a-4a0c-960c-62de778e6f1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20126
12792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.2012612792
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.4155356076
Short name T409
Test name
Test status
Simulation time 23340491523 ps
CPU time 22.7 seconds
Started Jul 23 06:48:34 PM PDT 24
Finished Jul 23 06:49:04 PM PDT 24
Peak memory 206760 kb
Host smart-5ea68e09-9827-47b8-8017-7b4b59f97d93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41553
56076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.4155356076
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.2465232208
Short name T1202
Test name
Test status
Simulation time 3376663090 ps
CPU time 3.96 seconds
Started Jul 23 06:48:34 PM PDT 24
Finished Jul 23 06:48:46 PM PDT 24
Peak memory 206792 kb
Host smart-f02b86cd-be3f-4bd2-9770-bf75a901ae70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24652
32208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.2465232208
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.566197201
Short name T2341
Test name
Test status
Simulation time 5429778536 ps
CPU time 40.3 seconds
Started Jul 23 06:48:20 PM PDT 24
Finished Jul 23 06:49:06 PM PDT 24
Peak memory 206988 kb
Host smart-2bb4bce7-5138-4d25-9934-31988757dfb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56619
7201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.566197201
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.405537372
Short name T2371
Test name
Test status
Simulation time 5149314630 ps
CPU time 36.67 seconds
Started Jul 23 06:48:21 PM PDT 24
Finished Jul 23 06:49:04 PM PDT 24
Peak memory 206872 kb
Host smart-cf68f6ba-56b3-4704-b6d4-3ca92eeef2f9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=405537372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.405537372
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.2602273998
Short name T2420
Test name
Test status
Simulation time 240919067 ps
CPU time 0.93 seconds
Started Jul 23 06:48:37 PM PDT 24
Finished Jul 23 06:48:44 PM PDT 24
Peak memory 206720 kb
Host smart-58245f53-99e3-4502-8f7d-eb7b2bd0b617
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2602273998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.2602273998
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.3083611008
Short name T598
Test name
Test status
Simulation time 199511718 ps
CPU time 0.85 seconds
Started Jul 23 06:48:26 PM PDT 24
Finished Jul 23 06:48:37 PM PDT 24
Peak memory 206752 kb
Host smart-d251a0dd-ca08-45fc-bcc1-841bfcfecb28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30836
11008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.3083611008
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.1315004158
Short name T1700
Test name
Test status
Simulation time 4065866239 ps
CPU time 109.32 seconds
Started Jul 23 06:48:25 PM PDT 24
Finished Jul 23 06:50:23 PM PDT 24
Peak memory 206940 kb
Host smart-0ec87c83-db9c-4a33-9214-d23ce81d36c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13150
04158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.1315004158
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.1290817856
Short name T368
Test name
Test status
Simulation time 4831447726 ps
CPU time 128.63 seconds
Started Jul 23 06:48:34 PM PDT 24
Finished Jul 23 06:50:50 PM PDT 24
Peak memory 206872 kb
Host smart-31e26a6f-067f-4314-aebb-52f657acaa30
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1290817856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.1290817856
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.2787116962
Short name T1651
Test name
Test status
Simulation time 163759172 ps
CPU time 0.77 seconds
Started Jul 23 06:48:34 PM PDT 24
Finished Jul 23 06:48:43 PM PDT 24
Peak memory 206672 kb
Host smart-53df7d85-080e-474a-bea5-a56dbfefc16b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2787116962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.2787116962
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.521883350
Short name T331
Test name
Test status
Simulation time 163159178 ps
CPU time 0.8 seconds
Started Jul 23 06:48:22 PM PDT 24
Finished Jul 23 06:48:30 PM PDT 24
Peak memory 206760 kb
Host smart-670dc2c5-9106-4525-b023-5a025a3caddd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52188
3350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.521883350
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.766992578
Short name T135
Test name
Test status
Simulation time 189652754 ps
CPU time 0.81 seconds
Started Jul 23 06:48:21 PM PDT 24
Finished Jul 23 06:48:27 PM PDT 24
Peak memory 206744 kb
Host smart-1e5dfa4e-7f85-421c-b5aa-a2e6e3c1be3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76699
2578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.766992578
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.3742038143
Short name T683
Test name
Test status
Simulation time 211440774 ps
CPU time 0.86 seconds
Started Jul 23 06:48:22 PM PDT 24
Finished Jul 23 06:48:29 PM PDT 24
Peak memory 206768 kb
Host smart-bad1c8cb-90c7-41a0-b3c1-7ae92d44118e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37420
38143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.3742038143
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.1167736749
Short name T662
Test name
Test status
Simulation time 173648055 ps
CPU time 0.81 seconds
Started Jul 23 06:48:25 PM PDT 24
Finished Jul 23 06:48:35 PM PDT 24
Peak memory 206752 kb
Host smart-07b34608-7940-4c9e-8cdd-10e09d8ed40b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11677
36749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.1167736749
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.309350725
Short name T291
Test name
Test status
Simulation time 162152125 ps
CPU time 0.79 seconds
Started Jul 23 06:48:30 PM PDT 24
Finished Jul 23 06:48:40 PM PDT 24
Peak memory 206756 kb
Host smart-0bb6a562-927d-4ec0-84c5-3841c539139e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30935
0725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.309350725
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.1460581270
Short name T1628
Test name
Test status
Simulation time 165917027 ps
CPU time 0.87 seconds
Started Jul 23 06:48:23 PM PDT 24
Finished Jul 23 06:48:32 PM PDT 24
Peak memory 206772 kb
Host smart-a80c9b78-7c05-40ab-a9f8-ea248bda9c57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14605
81270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.1460581270
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.2608627096
Short name T341
Test name
Test status
Simulation time 231772767 ps
CPU time 0.87 seconds
Started Jul 23 06:48:34 PM PDT 24
Finished Jul 23 06:48:43 PM PDT 24
Peak memory 206660 kb
Host smart-962dfdf3-4b55-4011-9eee-830c90d3ed3c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2608627096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.2608627096
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.1493397577
Short name T1067
Test name
Test status
Simulation time 146133834 ps
CPU time 0.8 seconds
Started Jul 23 06:48:22 PM PDT 24
Finished Jul 23 06:48:29 PM PDT 24
Peak memory 206772 kb
Host smart-9f169bd5-df7f-4128-8056-44c825ee6049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14933
97577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.1493397577
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.583768369
Short name T1993
Test name
Test status
Simulation time 32327021 ps
CPU time 0.66 seconds
Started Jul 23 06:48:23 PM PDT 24
Finished Jul 23 06:48:32 PM PDT 24
Peak memory 206748 kb
Host smart-0800aad5-0fa3-4b0c-baae-c24cf7b57aeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58376
8369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.583768369
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.3397464734
Short name T1513
Test name
Test status
Simulation time 18823698840 ps
CPU time 49.45 seconds
Started Jul 23 06:48:26 PM PDT 24
Finished Jul 23 06:49:26 PM PDT 24
Peak memory 206960 kb
Host smart-f7b616df-ec9c-4f2a-a73b-5d4516b255cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33974
64734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.3397464734
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.3662738671
Short name T1468
Test name
Test status
Simulation time 173803914 ps
CPU time 0.87 seconds
Started Jul 23 06:48:24 PM PDT 24
Finished Jul 23 06:48:33 PM PDT 24
Peak memory 206756 kb
Host smart-537fc09b-50a1-4579-ac4b-4829198abfc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36627
38671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.3662738671
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.787014411
Short name T298
Test name
Test status
Simulation time 240977193 ps
CPU time 0.9 seconds
Started Jul 23 06:48:23 PM PDT 24
Finished Jul 23 06:48:32 PM PDT 24
Peak memory 206768 kb
Host smart-3b5ffed1-a291-420d-97e3-2772f648ad64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78701
4411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.787014411
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.3697860414
Short name T1408
Test name
Test status
Simulation time 164826745 ps
CPU time 0.82 seconds
Started Jul 23 06:48:23 PM PDT 24
Finished Jul 23 06:48:31 PM PDT 24
Peak memory 206764 kb
Host smart-30a8b797-0f05-4e09-92f1-3ee31c1c6680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36978
60414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.3697860414
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.1187795372
Short name T1922
Test name
Test status
Simulation time 181344382 ps
CPU time 0.83 seconds
Started Jul 23 06:48:19 PM PDT 24
Finished Jul 23 06:48:25 PM PDT 24
Peak memory 206736 kb
Host smart-279ba8df-1b4a-407c-aa03-8ac191f57316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11877
95372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.1187795372
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.4232473538
Short name T938
Test name
Test status
Simulation time 134331151 ps
CPU time 0.7 seconds
Started Jul 23 06:48:20 PM PDT 24
Finished Jul 23 06:48:25 PM PDT 24
Peak memory 206632 kb
Host smart-534c3d32-44d7-4d50-b5d6-731f040b3596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42324
73538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.4232473538
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.4152891309
Short name T853
Test name
Test status
Simulation time 153757900 ps
CPU time 0.8 seconds
Started Jul 23 06:48:30 PM PDT 24
Finished Jul 23 06:48:40 PM PDT 24
Peak memory 206752 kb
Host smart-718a83ff-48ce-43a7-9376-669782819702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41528
91309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.4152891309
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.84024800
Short name T2248
Test name
Test status
Simulation time 172863173 ps
CPU time 0.85 seconds
Started Jul 23 06:48:26 PM PDT 24
Finished Jul 23 06:48:37 PM PDT 24
Peak memory 206760 kb
Host smart-4e763425-e39b-4e7e-afb0-2656d4691659
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84024
800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.84024800
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.4167605301
Short name T617
Test name
Test status
Simulation time 229746541 ps
CPU time 0.92 seconds
Started Jul 23 06:48:23 PM PDT 24
Finished Jul 23 06:48:32 PM PDT 24
Peak memory 206648 kb
Host smart-6cb614a6-5118-4519-962c-3147bf513627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41676
05301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.4167605301
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.1429236440
Short name T960
Test name
Test status
Simulation time 6027865846 ps
CPU time 53.32 seconds
Started Jul 23 06:48:26 PM PDT 24
Finished Jul 23 06:49:29 PM PDT 24
Peak memory 206968 kb
Host smart-f1c090d8-46c5-44be-acdf-6d778f66b4d0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1429236440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.1429236440
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.3042734407
Short name T1541
Test name
Test status
Simulation time 185670352 ps
CPU time 0.81 seconds
Started Jul 23 06:48:23 PM PDT 24
Finished Jul 23 06:48:32 PM PDT 24
Peak memory 206736 kb
Host smart-adf06db2-83e9-4e94-bef8-9b61cd1b89df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30427
34407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.3042734407
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.1508022811
Short name T435
Test name
Test status
Simulation time 157992822 ps
CPU time 0.79 seconds
Started Jul 23 06:48:24 PM PDT 24
Finished Jul 23 06:48:33 PM PDT 24
Peak memory 206708 kb
Host smart-0320c30c-4f1c-4a41-8333-b59bbd9f16f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15080
22811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.1508022811
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.3620790666
Short name T1606
Test name
Test status
Simulation time 333550132 ps
CPU time 0.99 seconds
Started Jul 23 06:48:28 PM PDT 24
Finished Jul 23 06:48:39 PM PDT 24
Peak memory 206772 kb
Host smart-61e5f4da-4860-41ec-8f3b-2afabacea862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36207
90666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.3620790666
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.4197370822
Short name T363
Test name
Test status
Simulation time 3277450296 ps
CPU time 94.53 seconds
Started Jul 23 06:48:31 PM PDT 24
Finished Jul 23 06:50:14 PM PDT 24
Peak memory 206908 kb
Host smart-affc7901-5758-4aca-8542-98b12938bcbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41973
70822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.4197370822
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.4027028764
Short name T318
Test name
Test status
Simulation time 33239646 ps
CPU time 0.67 seconds
Started Jul 23 06:38:48 PM PDT 24
Finished Jul 23 06:38:50 PM PDT 24
Peak memory 206740 kb
Host smart-2e57d26c-cc2b-4f8e-8911-5f72409a09d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4027028764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.4027028764
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.1939649383
Short name T2271
Test name
Test status
Simulation time 3530953799 ps
CPU time 4.2 seconds
Started Jul 23 06:38:29 PM PDT 24
Finished Jul 23 06:38:36 PM PDT 24
Peak memory 206928 kb
Host smart-10a3d906-4781-49be-bed4-d9e4ec4390da
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1939649383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.1939649383
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.3335182641
Short name T223
Test name
Test status
Simulation time 13406407967 ps
CPU time 16.12 seconds
Started Jul 23 06:38:31 PM PDT 24
Finished Jul 23 06:38:49 PM PDT 24
Peak memory 206928 kb
Host smart-a1833e26-a952-493d-bcca-0d84c487d4ce
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3335182641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.3335182641
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.2731739962
Short name T45
Test name
Test status
Simulation time 23449665145 ps
CPU time 24.1 seconds
Started Jul 23 06:38:29 PM PDT 24
Finished Jul 23 06:38:55 PM PDT 24
Peak memory 206924 kb
Host smart-f918cfc3-ef1c-4d8e-90da-7a464052a443
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2731739962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.2731739962
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.913269146
Short name T417
Test name
Test status
Simulation time 160477906 ps
CPU time 0.81 seconds
Started Jul 23 06:38:30 PM PDT 24
Finished Jul 23 06:38:33 PM PDT 24
Peak memory 206752 kb
Host smart-44ce01f4-1f0b-4b19-92a8-4cf863da2b4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91326
9146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.913269146
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.3356873471
Short name T1838
Test name
Test status
Simulation time 161200289 ps
CPU time 0.77 seconds
Started Jul 23 06:38:35 PM PDT 24
Finished Jul 23 06:38:37 PM PDT 24
Peak memory 206724 kb
Host smart-85ad49fd-2077-41be-b44b-0df5a65a863d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33568
73471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.3356873471
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.3130964189
Short name T1464
Test name
Test status
Simulation time 478385129 ps
CPU time 1.45 seconds
Started Jul 23 06:38:36 PM PDT 24
Finished Jul 23 06:38:40 PM PDT 24
Peak memory 206760 kb
Host smart-7d35e42b-245a-4528-9c08-f9c127b0c029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31309
64189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.3130964189
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.448591848
Short name T1977
Test name
Test status
Simulation time 1329122270 ps
CPU time 2.73 seconds
Started Jul 23 06:38:34 PM PDT 24
Finished Jul 23 06:38:39 PM PDT 24
Peak memory 206880 kb
Host smart-39bee8be-7cf7-429a-b16e-ff02a3a9b491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44859
1848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.448591848
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.296635812
Short name T2576
Test name
Test status
Simulation time 17061775219 ps
CPU time 36.18 seconds
Started Jul 23 06:38:36 PM PDT 24
Finished Jul 23 06:39:15 PM PDT 24
Peak memory 206892 kb
Host smart-bc6c384a-838d-4336-af58-1417f1b7daad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29663
5812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.296635812
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.3601547054
Short name T647
Test name
Test status
Simulation time 376668807 ps
CPU time 1.24 seconds
Started Jul 23 06:38:35 PM PDT 24
Finished Jul 23 06:38:38 PM PDT 24
Peak memory 206772 kb
Host smart-ee2e2d45-7fca-4cd1-8996-dd1b0e44e31d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36015
47054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.3601547054
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.1466967548
Short name T1658
Test name
Test status
Simulation time 149428578 ps
CPU time 0.79 seconds
Started Jul 23 06:38:34 PM PDT 24
Finished Jul 23 06:38:36 PM PDT 24
Peak memory 206736 kb
Host smart-5c91ecce-47fc-479d-8950-3c0534b3222a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14669
67548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.1466967548
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.889885435
Short name T1012
Test name
Test status
Simulation time 37555386 ps
CPU time 0.64 seconds
Started Jul 23 06:38:35 PM PDT 24
Finished Jul 23 06:38:37 PM PDT 24
Peak memory 206748 kb
Host smart-5302ea69-39bf-40f8-9baa-0ad8d7ab6232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88988
5435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.889885435
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.2188910363
Short name T1017
Test name
Test status
Simulation time 965178836 ps
CPU time 2.21 seconds
Started Jul 23 06:38:37 PM PDT 24
Finished Jul 23 06:38:42 PM PDT 24
Peak memory 206828 kb
Host smart-96581475-0871-4329-bf8b-c4040a2a0c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21889
10363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.2188910363
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.1923645665
Short name T725
Test name
Test status
Simulation time 158258800 ps
CPU time 1.46 seconds
Started Jul 23 06:38:34 PM PDT 24
Finished Jul 23 06:38:37 PM PDT 24
Peak memory 206740 kb
Host smart-cd02300d-d539-4d79-9985-a6a5c5c26ce1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19236
45665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.1923645665
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.3423038380
Short name T1917
Test name
Test status
Simulation time 268663489 ps
CPU time 0.88 seconds
Started Jul 23 06:38:36 PM PDT 24
Finished Jul 23 06:38:39 PM PDT 24
Peak memory 206732 kb
Host smart-de89fa24-7c1d-4e32-9107-4afb59b5b4bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34230
38380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.3423038380
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.2862702469
Short name T1761
Test name
Test status
Simulation time 183173384 ps
CPU time 0.77 seconds
Started Jul 23 06:38:35 PM PDT 24
Finished Jul 23 06:38:38 PM PDT 24
Peak memory 206772 kb
Host smart-d402b6c0-0b50-48a4-acf4-777953f42d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28627
02469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.2862702469
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.1104041491
Short name T795
Test name
Test status
Simulation time 171888818 ps
CPU time 0.83 seconds
Started Jul 23 06:38:34 PM PDT 24
Finished Jul 23 06:38:37 PM PDT 24
Peak memory 206772 kb
Host smart-b6c40a1d-e593-4d11-9682-ad102fbfb5cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11040
41491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.1104041491
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.2269554171
Short name T76
Test name
Test status
Simulation time 7714586974 ps
CPU time 222.34 seconds
Started Jul 23 06:38:34 PM PDT 24
Finished Jul 23 06:42:19 PM PDT 24
Peak memory 206876 kb
Host smart-14819d1c-a44b-4a81-b54f-d22abacf0bfa
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2269554171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.2269554171
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.3616477572
Short name T2700
Test name
Test status
Simulation time 229720411 ps
CPU time 0.96 seconds
Started Jul 23 06:38:39 PM PDT 24
Finished Jul 23 06:38:42 PM PDT 24
Peak memory 206732 kb
Host smart-4fbdd9ff-10f4-42d3-8376-62d30b057c2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36164
77572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.3616477572
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.3868046501
Short name T41
Test name
Test status
Simulation time 23309171935 ps
CPU time 27.66 seconds
Started Jul 23 06:38:39 PM PDT 24
Finished Jul 23 06:39:08 PM PDT 24
Peak memory 206792 kb
Host smart-a5d316e0-1d02-4c0b-8adc-44dc44c942c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38680
46501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.3868046501
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.2652915525
Short name T2048
Test name
Test status
Simulation time 3282220592 ps
CPU time 3.56 seconds
Started Jul 23 06:38:41 PM PDT 24
Finished Jul 23 06:38:46 PM PDT 24
Peak memory 206820 kb
Host smart-d5eddd44-f4b3-4afd-9f59-2ef0e83a4f00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26529
15525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.2652915525
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.291668233
Short name T1286
Test name
Test status
Simulation time 8077805181 ps
CPU time 223.12 seconds
Started Jul 23 06:38:40 PM PDT 24
Finished Jul 23 06:42:25 PM PDT 24
Peak memory 206980 kb
Host smart-f9ac12ab-fab4-4dd0-bfde-cbbd9406118c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29166
8233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.291668233
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.3987036515
Short name T2667
Test name
Test status
Simulation time 4865567045 ps
CPU time 43.23 seconds
Started Jul 23 06:38:40 PM PDT 24
Finished Jul 23 06:39:25 PM PDT 24
Peak memory 206912 kb
Host smart-e2105247-2c52-490c-bdf1-8c8574e4ab37
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3987036515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.3987036515
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.2454080063
Short name T625
Test name
Test status
Simulation time 257489052 ps
CPU time 0.91 seconds
Started Jul 23 06:38:46 PM PDT 24
Finished Jul 23 06:38:49 PM PDT 24
Peak memory 206756 kb
Host smart-9bbe2d4d-0bdc-4f2f-bae5-8de997efdbca
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2454080063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.2454080063
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.3892610427
Short name T2311
Test name
Test status
Simulation time 189282135 ps
CPU time 0.88 seconds
Started Jul 23 06:38:41 PM PDT 24
Finished Jul 23 06:38:44 PM PDT 24
Peak memory 206768 kb
Host smart-70e15f1f-1057-40a4-ad8c-1e1845f3eae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38926
10427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.3892610427
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.1954611763
Short name T2712
Test name
Test status
Simulation time 4857168048 ps
CPU time 35.97 seconds
Started Jul 23 06:38:46 PM PDT 24
Finished Jul 23 06:39:24 PM PDT 24
Peak memory 206900 kb
Host smart-241822d2-34d6-421c-8dae-8d55f6a322c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19546
11763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.1954611763
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.1742304702
Short name T306
Test name
Test status
Simulation time 7718157475 ps
CPU time 207.36 seconds
Started Jul 23 06:38:46 PM PDT 24
Finished Jul 23 06:42:16 PM PDT 24
Peak memory 206908 kb
Host smart-c5c8d5f0-c09f-429f-9ddc-c07eaa2caa71
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1742304702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.1742304702
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.2179582010
Short name T594
Test name
Test status
Simulation time 195026856 ps
CPU time 0.81 seconds
Started Jul 23 06:38:43 PM PDT 24
Finished Jul 23 06:38:45 PM PDT 24
Peak memory 206748 kb
Host smart-9bfbc3a3-8c29-4cef-8a17-4f9388b1232f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2179582010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.2179582010
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.4273886991
Short name T1164
Test name
Test status
Simulation time 169657344 ps
CPU time 0.79 seconds
Started Jul 23 06:38:39 PM PDT 24
Finished Jul 23 06:38:42 PM PDT 24
Peak memory 206752 kb
Host smart-8be5d7a9-6da9-4b6f-9ead-9a328f3ff5eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42738
86991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.4273886991
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.4128143624
Short name T1599
Test name
Test status
Simulation time 212572433 ps
CPU time 1.01 seconds
Started Jul 23 06:38:45 PM PDT 24
Finished Jul 23 06:38:48 PM PDT 24
Peak memory 206756 kb
Host smart-310bb33f-bbab-42a6-b045-35cd7eeeda3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41281
43624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.4128143624
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.725339098
Short name T2545
Test name
Test status
Simulation time 193319272 ps
CPU time 0.84 seconds
Started Jul 23 06:38:43 PM PDT 24
Finished Jul 23 06:38:46 PM PDT 24
Peak memory 206736 kb
Host smart-e282fadc-7d38-4262-9472-1f93f3941ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72533
9098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.725339098
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.691055591
Short name T2382
Test name
Test status
Simulation time 152822886 ps
CPU time 0.75 seconds
Started Jul 23 06:38:46 PM PDT 24
Finished Jul 23 06:38:48 PM PDT 24
Peak memory 206764 kb
Host smart-93ea07d4-f70f-40cb-9ec1-fbe0e4aa0222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69105
5591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.691055591
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.4022621404
Short name T619
Test name
Test status
Simulation time 180862475 ps
CPU time 0.79 seconds
Started Jul 23 06:38:39 PM PDT 24
Finished Jul 23 06:38:41 PM PDT 24
Peak memory 206756 kb
Host smart-22a0bfc1-acc0-416a-99d2-c7346c564adc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40226
21404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.4022621404
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.3739880901
Short name T412
Test name
Test status
Simulation time 153228624 ps
CPU time 0.78 seconds
Started Jul 23 06:38:43 PM PDT 24
Finished Jul 23 06:38:45 PM PDT 24
Peak memory 206744 kb
Host smart-11133c2f-e86a-4c8d-9bb0-bb816e6a14f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37398
80901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.3739880901
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.1572974944
Short name T1604
Test name
Test status
Simulation time 241949637 ps
CPU time 0.94 seconds
Started Jul 23 06:38:40 PM PDT 24
Finished Jul 23 06:38:43 PM PDT 24
Peak memory 206772 kb
Host smart-c82feae5-6e86-4988-85e9-8b4ddd7d8d6a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1572974944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.1572974944
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.726154045
Short name T1629
Test name
Test status
Simulation time 172587919 ps
CPU time 0.75 seconds
Started Jul 23 06:38:40 PM PDT 24
Finished Jul 23 06:38:43 PM PDT 24
Peak memory 206740 kb
Host smart-c8214351-06a7-4175-94e6-44741d76a584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72615
4045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.726154045
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.1449125282
Short name T1915
Test name
Test status
Simulation time 60076349 ps
CPU time 0.67 seconds
Started Jul 23 06:38:42 PM PDT 24
Finished Jul 23 06:38:44 PM PDT 24
Peak memory 206748 kb
Host smart-2f523985-efdb-4175-8199-d3a1df30ee5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14491
25282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.1449125282
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.3889686930
Short name T87
Test name
Test status
Simulation time 11936019420 ps
CPU time 28.82 seconds
Started Jul 23 06:38:40 PM PDT 24
Finished Jul 23 06:39:11 PM PDT 24
Peak memory 206948 kb
Host smart-3bbad535-a7fc-4921-8ee6-a6b989f0549c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38896
86930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.3889686930
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.1743325100
Short name T679
Test name
Test status
Simulation time 172384809 ps
CPU time 0.82 seconds
Started Jul 23 06:38:42 PM PDT 24
Finished Jul 23 06:38:44 PM PDT 24
Peak memory 206756 kb
Host smart-2adc07d7-455e-4b0c-8dd9-aaaeaccd1e9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17433
25100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.1743325100
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.2727649529
Short name T2613
Test name
Test status
Simulation time 204262629 ps
CPU time 0.86 seconds
Started Jul 23 06:38:39 PM PDT 24
Finished Jul 23 06:38:42 PM PDT 24
Peak memory 206764 kb
Host smart-34131339-c707-4e0a-9e59-9ab36e5c7d50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27276
49529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.2727649529
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.524142670
Short name T1520
Test name
Test status
Simulation time 12457353992 ps
CPU time 246.97 seconds
Started Jul 23 06:38:46 PM PDT 24
Finished Jul 23 06:42:55 PM PDT 24
Peak memory 206864 kb
Host smart-9383e8a9-4d34-445b-a059-29b8e3aea7a8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=524142670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.524142670
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.2564350718
Short name T165
Test name
Test status
Simulation time 6410347929 ps
CPU time 60.95 seconds
Started Jul 23 06:38:46 PM PDT 24
Finished Jul 23 06:39:49 PM PDT 24
Peak memory 206968 kb
Host smart-7547bcba-cc77-4ee9-aa76-7c9a80683332
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2564350718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.2564350718
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.3783270429
Short name T2318
Test name
Test status
Simulation time 16247475783 ps
CPU time 354.01 seconds
Started Jul 23 06:38:47 PM PDT 24
Finished Jul 23 06:44:43 PM PDT 24
Peak memory 206948 kb
Host smart-02057c78-6308-4674-91b4-2f7fb4494798
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3783270429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.3783270429
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.1547410215
Short name T1347
Test name
Test status
Simulation time 255268060 ps
CPU time 0.92 seconds
Started Jul 23 06:38:40 PM PDT 24
Finished Jul 23 06:38:43 PM PDT 24
Peak memory 206772 kb
Host smart-36e85d2b-08a2-45b1-a14c-1d636a06e71d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15474
10215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.1547410215
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.3815033158
Short name T1918
Test name
Test status
Simulation time 199985240 ps
CPU time 0.85 seconds
Started Jul 23 06:38:47 PM PDT 24
Finished Jul 23 06:38:50 PM PDT 24
Peak memory 206708 kb
Host smart-bfc2377d-b927-4fdd-8af3-8f5ba94b2248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38150
33158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.3815033158
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.1373355815
Short name T660
Test name
Test status
Simulation time 167061112 ps
CPU time 0.77 seconds
Started Jul 23 06:38:48 PM PDT 24
Finished Jul 23 06:38:50 PM PDT 24
Peak memory 206772 kb
Host smart-302478ca-336b-4b90-913a-740475f92d20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13733
55815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.1373355815
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.2683756106
Short name T1534
Test name
Test status
Simulation time 214869860 ps
CPU time 0.88 seconds
Started Jul 23 06:38:47 PM PDT 24
Finished Jul 23 06:38:50 PM PDT 24
Peak memory 206764 kb
Host smart-f4788b77-99e1-4d88-94ec-df43b9c5d8db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26837
56106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.2683756106
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.3830358159
Short name T1518
Test name
Test status
Simulation time 151814038 ps
CPU time 0.83 seconds
Started Jul 23 06:38:48 PM PDT 24
Finished Jul 23 06:38:51 PM PDT 24
Peak memory 206784 kb
Host smart-d1159c76-50d2-4269-b5f9-f841393b6bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38303
58159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.3830358159
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.1607722781
Short name T2590
Test name
Test status
Simulation time 261265681 ps
CPU time 1.06 seconds
Started Jul 23 06:38:48 PM PDT 24
Finished Jul 23 06:38:51 PM PDT 24
Peak memory 206748 kb
Host smart-cfbc8c81-46e0-4314-a7f4-6c0e798d9ea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16077
22781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.1607722781
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.3899954921
Short name T2467
Test name
Test status
Simulation time 6369838793 ps
CPU time 41.91 seconds
Started Jul 23 06:38:46 PM PDT 24
Finished Jul 23 06:39:30 PM PDT 24
Peak memory 206828 kb
Host smart-7cfe6cba-75eb-45e1-98f3-b68bbfcf0ffd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3899954921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.3899954921
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.1818315681
Short name T890
Test name
Test status
Simulation time 186189829 ps
CPU time 0.88 seconds
Started Jul 23 06:38:45 PM PDT 24
Finished Jul 23 06:38:48 PM PDT 24
Peak memory 206764 kb
Host smart-604271a1-16aa-4392-8d59-4f722893b00b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18183
15681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.1818315681
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.2867950500
Short name T239
Test name
Test status
Simulation time 180767604 ps
CPU time 0.84 seconds
Started Jul 23 06:38:45 PM PDT 24
Finished Jul 23 06:38:47 PM PDT 24
Peak memory 206748 kb
Host smart-ef996b98-7d4b-431e-bd01-c940e2ab00c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28679
50500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.2867950500
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.2904321559
Short name T1698
Test name
Test status
Simulation time 1027545193 ps
CPU time 2.23 seconds
Started Jul 23 06:38:46 PM PDT 24
Finished Jul 23 06:38:50 PM PDT 24
Peak memory 206804 kb
Host smart-9f5aeb0f-eecc-4bfa-a514-5c5ba2fbc06d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29043
21559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.2904321559
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.3612555723
Short name T426
Test name
Test status
Simulation time 3370774040 ps
CPU time 32.11 seconds
Started Jul 23 06:38:45 PM PDT 24
Finished Jul 23 06:39:19 PM PDT 24
Peak memory 206908 kb
Host smart-7ea930fc-2d5f-48a0-aaa6-82c7427e54d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36125
55723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.3612555723
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.1283569872
Short name T843
Test name
Test status
Simulation time 89062931 ps
CPU time 0.74 seconds
Started Jul 23 06:39:02 PM PDT 24
Finished Jul 23 06:39:05 PM PDT 24
Peak memory 206768 kb
Host smart-fcab911c-ab1b-4aaa-90cb-ddbcf14cdfae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1283569872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.1283569872
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.3628100984
Short name T1459
Test name
Test status
Simulation time 3870683568 ps
CPU time 4.41 seconds
Started Jul 23 06:38:48 PM PDT 24
Finished Jul 23 06:38:54 PM PDT 24
Peak memory 206816 kb
Host smart-5be61fb9-7d8b-481a-bb3c-604d4792f875
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3628100984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.3628100984
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.3555880502
Short name T1981
Test name
Test status
Simulation time 13396581494 ps
CPU time 12.93 seconds
Started Jul 23 06:38:45 PM PDT 24
Finished Jul 23 06:38:59 PM PDT 24
Peak memory 206944 kb
Host smart-0ef32132-0edf-4339-a285-c7ab6b7a6100
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3555880502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.3555880502
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.2533410545
Short name T925
Test name
Test status
Simulation time 23328049667 ps
CPU time 22.28 seconds
Started Jul 23 06:38:46 PM PDT 24
Finished Jul 23 06:39:10 PM PDT 24
Peak memory 206796 kb
Host smart-9c4e7161-83cf-4a19-835c-3d87b541f917
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2533410545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.2533410545
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.1650798272
Short name T1400
Test name
Test status
Simulation time 162187131 ps
CPU time 0.81 seconds
Started Jul 23 06:38:51 PM PDT 24
Finished Jul 23 06:38:53 PM PDT 24
Peak memory 206756 kb
Host smart-aba28e66-a8f8-463a-859a-48bb32b302c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16507
98272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.1650798272
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.804204435
Short name T742
Test name
Test status
Simulation time 142393174 ps
CPU time 0.75 seconds
Started Jul 23 06:38:50 PM PDT 24
Finished Jul 23 06:38:52 PM PDT 24
Peak memory 206768 kb
Host smart-bf799893-43af-45bc-b960-3d0355b0f57b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80420
4435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.804204435
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.4237806343
Short name T1797
Test name
Test status
Simulation time 360294561 ps
CPU time 1.16 seconds
Started Jul 23 06:38:51 PM PDT 24
Finished Jul 23 06:38:53 PM PDT 24
Peak memory 206748 kb
Host smart-c8653003-ab41-4da9-814f-1a6b99dccbe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42378
06343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.4237806343
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.3044714058
Short name T793
Test name
Test status
Simulation time 1046102589 ps
CPU time 2.41 seconds
Started Jul 23 06:38:50 PM PDT 24
Finished Jul 23 06:38:54 PM PDT 24
Peak memory 206908 kb
Host smart-4ece154d-2541-4a0c-9ef2-a0a9ca01f452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30447
14058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.3044714058
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_timeout.2370475489
Short name T2312
Test name
Test status
Simulation time 154065220 ps
CPU time 0.86 seconds
Started Jul 23 06:38:51 PM PDT 24
Finished Jul 23 06:38:53 PM PDT 24
Peak memory 206772 kb
Host smart-2ed833ab-df2d-4a26-a723-2fdd8248d21b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23704
75489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_timeout.2370475489
Directory /workspace/6.usbdev_device_timeout/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.865606450
Short name T1057
Test name
Test status
Simulation time 349685304 ps
CPU time 1.09 seconds
Started Jul 23 06:38:50 PM PDT 24
Finished Jul 23 06:38:53 PM PDT 24
Peak memory 206728 kb
Host smart-b2bd2ae7-afd4-48ca-afd1-cfd61b642ebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86560
6450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.865606450
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.3649632453
Short name T626
Test name
Test status
Simulation time 139359750 ps
CPU time 0.77 seconds
Started Jul 23 06:38:50 PM PDT 24
Finished Jul 23 06:38:53 PM PDT 24
Peak memory 206780 kb
Host smart-f7f3bf09-393c-4a42-be26-11a5da040c60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36496
32453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.3649632453
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.1701915428
Short name T336
Test name
Test status
Simulation time 37619287 ps
CPU time 0.64 seconds
Started Jul 23 06:38:50 PM PDT 24
Finished Jul 23 06:38:52 PM PDT 24
Peak memory 206748 kb
Host smart-5c6e6aed-830b-4617-96ae-653c3b666001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17019
15428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.1701915428
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.3584810612
Short name T1403
Test name
Test status
Simulation time 774370651 ps
CPU time 2.2 seconds
Started Jul 23 06:38:49 PM PDT 24
Finished Jul 23 06:38:53 PM PDT 24
Peak memory 206892 kb
Host smart-4d4a4b2f-02cc-4626-96df-2a608f7cfd12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35848
10612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.3584810612
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.904691593
Short name T681
Test name
Test status
Simulation time 406505595 ps
CPU time 2.56 seconds
Started Jul 23 06:38:49 PM PDT 24
Finished Jul 23 06:38:54 PM PDT 24
Peak memory 206844 kb
Host smart-5503d6d1-c5a2-4b97-bbaa-555685657ec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90469
1593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.904691593
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.3352887674
Short name T610
Test name
Test status
Simulation time 193203139 ps
CPU time 0.84 seconds
Started Jul 23 06:38:50 PM PDT 24
Finished Jul 23 06:38:52 PM PDT 24
Peak memory 206740 kb
Host smart-c4d8ac87-62ea-4242-af40-44fedfdeeca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33528
87674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.3352887674
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.1382737252
Short name T2342
Test name
Test status
Simulation time 174990433 ps
CPU time 0.81 seconds
Started Jul 23 06:38:54 PM PDT 24
Finished Jul 23 06:38:55 PM PDT 24
Peak memory 206748 kb
Host smart-ca95266a-bd22-4287-939e-0da4a2770cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13827
37252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.1382737252
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.3318048623
Short name T728
Test name
Test status
Simulation time 232570406 ps
CPU time 0.87 seconds
Started Jul 23 06:38:50 PM PDT 24
Finished Jul 23 06:38:53 PM PDT 24
Peak memory 206760 kb
Host smart-9562e917-c3d2-4302-b3fe-da0fcf903a02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33180
48623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.3318048623
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_iso_retraction.2889161819
Short name T2178
Test name
Test status
Simulation time 3817023341 ps
CPU time 14.43 seconds
Started Jul 23 06:38:49 PM PDT 24
Finished Jul 23 06:39:06 PM PDT 24
Peak memory 206932 kb
Host smart-0279c5c8-8c5a-43de-8905-e4e8d3cca2a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28891
61819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_iso_retraction.2889161819
Directory /workspace/6.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.4034247727
Short name T1936
Test name
Test status
Simulation time 159322385 ps
CPU time 0.8 seconds
Started Jul 23 06:38:50 PM PDT 24
Finished Jul 23 06:38:53 PM PDT 24
Peak memory 206732 kb
Host smart-788294c9-94f3-438a-8a44-413aeaf104f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40342
47727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.4034247727
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.461092373
Short name T40
Test name
Test status
Simulation time 23302791048 ps
CPU time 22.44 seconds
Started Jul 23 06:38:56 PM PDT 24
Finished Jul 23 06:39:19 PM PDT 24
Peak memory 206780 kb
Host smart-e2fac8c2-6503-4da3-b9b5-b0c18fdf16c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46109
2373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.461092373
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.770684842
Short name T2572
Test name
Test status
Simulation time 3347885062 ps
CPU time 3.75 seconds
Started Jul 23 06:38:56 PM PDT 24
Finished Jul 23 06:39:00 PM PDT 24
Peak memory 206852 kb
Host smart-08fd729f-e150-45f2-a74e-564d95305f5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77068
4842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.770684842
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.4201092424
Short name T5
Test name
Test status
Simulation time 8258882244 ps
CPU time 80.04 seconds
Started Jul 23 06:39:02 PM PDT 24
Finished Jul 23 06:40:24 PM PDT 24
Peak memory 206968 kb
Host smart-850a3504-ce8f-473c-9948-10ba5d740616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42010
92424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.4201092424
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.1109380166
Short name T362
Test name
Test status
Simulation time 3000595453 ps
CPU time 76.65 seconds
Started Jul 23 06:38:56 PM PDT 24
Finished Jul 23 06:40:14 PM PDT 24
Peak memory 206872 kb
Host smart-b862fd34-935e-4674-97fb-009555874779
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1109380166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.1109380166
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.422254302
Short name T576
Test name
Test status
Simulation time 273587369 ps
CPU time 0.97 seconds
Started Jul 23 06:38:58 PM PDT 24
Finished Jul 23 06:39:00 PM PDT 24
Peak memory 206876 kb
Host smart-1bf11cd1-8a69-4365-87be-705b2f82f50b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=422254302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.422254302
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.1946778662
Short name T903
Test name
Test status
Simulation time 217851328 ps
CPU time 0.89 seconds
Started Jul 23 06:38:57 PM PDT 24
Finished Jul 23 06:38:59 PM PDT 24
Peak memory 206708 kb
Host smart-251c2a7d-eaf4-4ebf-b866-fcc58c4419f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19467
78662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.1946778662
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.3003571464
Short name T2192
Test name
Test status
Simulation time 4993553665 ps
CPU time 45.23 seconds
Started Jul 23 06:39:03 PM PDT 24
Finished Jul 23 06:39:50 PM PDT 24
Peak memory 206892 kb
Host smart-433bc70b-34b6-4980-9c27-9575e7b4d21d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30035
71464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.3003571464
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.4243443048
Short name T991
Test name
Test status
Simulation time 3175573507 ps
CPU time 23.05 seconds
Started Jul 23 06:38:55 PM PDT 24
Finished Jul 23 06:39:18 PM PDT 24
Peak memory 206908 kb
Host smart-20ddeed2-e193-48e2-9cef-2c7b25235a7c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4243443048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.4243443048
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.1271243875
Short name T1001
Test name
Test status
Simulation time 170621238 ps
CPU time 0.78 seconds
Started Jul 23 06:38:58 PM PDT 24
Finished Jul 23 06:39:00 PM PDT 24
Peak memory 206880 kb
Host smart-c398e8b0-05cd-4ea3-8675-902c4bb4c585
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1271243875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.1271243875
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.442548305
Short name T916
Test name
Test status
Simulation time 148297343 ps
CPU time 0.83 seconds
Started Jul 23 06:38:56 PM PDT 24
Finished Jul 23 06:38:58 PM PDT 24
Peak memory 206752 kb
Host smart-71d538c1-0953-42e1-9270-ae75245ad484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44254
8305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.442548305
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.2205269363
Short name T2630
Test name
Test status
Simulation time 233523780 ps
CPU time 0.88 seconds
Started Jul 23 06:39:01 PM PDT 24
Finished Jul 23 06:39:04 PM PDT 24
Peak memory 206756 kb
Host smart-7eda23cd-a4b2-4abf-a79f-92af260e1d42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22052
69363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.2205269363
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.2643393496
Short name T1849
Test name
Test status
Simulation time 185314186 ps
CPU time 0.79 seconds
Started Jul 23 06:38:58 PM PDT 24
Finished Jul 23 06:39:00 PM PDT 24
Peak memory 206872 kb
Host smart-3d7fe336-5043-4fe5-86e5-89a5f6972762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26433
93496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.2643393496
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.2941890356
Short name T1630
Test name
Test status
Simulation time 162073155 ps
CPU time 0.83 seconds
Started Jul 23 06:38:57 PM PDT 24
Finished Jul 23 06:38:58 PM PDT 24
Peak memory 206788 kb
Host smart-2e392b8f-c236-46d2-aed4-a18b9b773c7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29418
90356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.2941890356
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.2993335630
Short name T1474
Test name
Test status
Simulation time 150033447 ps
CPU time 0.82 seconds
Started Jul 23 06:38:55 PM PDT 24
Finished Jul 23 06:38:57 PM PDT 24
Peak memory 206740 kb
Host smart-d47df9da-1aef-41e6-993a-fb05d4a7562e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29933
35630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.2993335630
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.1975310069
Short name T1734
Test name
Test status
Simulation time 163041014 ps
CPU time 0.77 seconds
Started Jul 23 06:39:03 PM PDT 24
Finished Jul 23 06:39:05 PM PDT 24
Peak memory 206756 kb
Host smart-8f44dfac-40dd-4850-9183-d80b1f8d8db1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19753
10069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.1975310069
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.848982169
Short name T1786
Test name
Test status
Simulation time 208130740 ps
CPU time 0.85 seconds
Started Jul 23 06:39:14 PM PDT 24
Finished Jul 23 06:39:16 PM PDT 24
Peak memory 206776 kb
Host smart-f0263a3c-d31c-47e8-bf18-84097879e9e6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=848982169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.848982169
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.180880094
Short name T1103
Test name
Test status
Simulation time 144293929 ps
CPU time 0.82 seconds
Started Jul 23 06:39:01 PM PDT 24
Finished Jul 23 06:39:04 PM PDT 24
Peak memory 206760 kb
Host smart-6426d991-31b6-4648-9218-4e079f576f25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18088
0094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.180880094
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.4275230948
Short name T34
Test name
Test status
Simulation time 43224204 ps
CPU time 0.66 seconds
Started Jul 23 06:39:14 PM PDT 24
Finished Jul 23 06:39:16 PM PDT 24
Peak memory 206748 kb
Host smart-450dc25c-446e-4cb0-84f5-7d24ad22044f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42752
30948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.4275230948
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.1403016867
Short name T269
Test name
Test status
Simulation time 11076275272 ps
CPU time 25.91 seconds
Started Jul 23 06:39:02 PM PDT 24
Finished Jul 23 06:39:30 PM PDT 24
Peak memory 206912 kb
Host smart-93de3361-0822-48f4-a143-011b528302e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14030
16867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.1403016867
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.1786310955
Short name T771
Test name
Test status
Simulation time 187979076 ps
CPU time 0.9 seconds
Started Jul 23 06:39:01 PM PDT 24
Finished Jul 23 06:39:03 PM PDT 24
Peak memory 206756 kb
Host smart-92fa05a3-1b09-4896-86b8-686f423ca228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17863
10955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.1786310955
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.1202474675
Short name T1902
Test name
Test status
Simulation time 176975433 ps
CPU time 0.81 seconds
Started Jul 23 06:39:15 PM PDT 24
Finished Jul 23 06:39:17 PM PDT 24
Peak memory 206764 kb
Host smart-96779d51-8131-4f0d-b3bd-bfbfc50b1656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12024
74675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.1202474675
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.3647779841
Short name T2086
Test name
Test status
Simulation time 11968229164 ps
CPU time 222.51 seconds
Started Jul 23 06:39:14 PM PDT 24
Finished Jul 23 06:42:58 PM PDT 24
Peak memory 206928 kb
Host smart-54fdff01-7232-4c23-9f67-f06f2d153583
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3647779841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.3647779841
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.2809002071
Short name T166
Test name
Test status
Simulation time 8443068948 ps
CPU time 35.21 seconds
Started Jul 23 06:39:15 PM PDT 24
Finished Jul 23 06:39:51 PM PDT 24
Peak memory 206984 kb
Host smart-212210dc-20d6-4d8b-9ae6-2efdd7ef96c7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2809002071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.2809002071
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.2445892215
Short name T2265
Test name
Test status
Simulation time 12442323492 ps
CPU time 90.47 seconds
Started Jul 23 06:39:00 PM PDT 24
Finished Jul 23 06:40:31 PM PDT 24
Peak memory 206968 kb
Host smart-99cdd404-9e44-47df-a9ad-5186acb71ff3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2445892215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.2445892215
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.1690425551
Short name T2684
Test name
Test status
Simulation time 204095079 ps
CPU time 0.86 seconds
Started Jul 23 06:39:02 PM PDT 24
Finished Jul 23 06:39:05 PM PDT 24
Peak memory 206768 kb
Host smart-868d2df2-2910-4d36-822d-c7b3cd86ea2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16904
25551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.1690425551
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.3809925923
Short name T936
Test name
Test status
Simulation time 185409828 ps
CPU time 0.88 seconds
Started Jul 23 06:39:01 PM PDT 24
Finished Jul 23 06:39:04 PM PDT 24
Peak memory 206772 kb
Host smart-afc29f20-f034-4803-bb4f-fce55cd028c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38099
25923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.3809925923
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.3481808760
Short name T815
Test name
Test status
Simulation time 170731467 ps
CPU time 0.77 seconds
Started Jul 23 06:39:00 PM PDT 24
Finished Jul 23 06:39:02 PM PDT 24
Peak memory 206752 kb
Host smart-a76c7e43-373c-4615-869f-10a5b4a8c0ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34818
08760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.3481808760
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.2375476565
Short name T848
Test name
Test status
Simulation time 197833861 ps
CPU time 0.81 seconds
Started Jul 23 06:39:00 PM PDT 24
Finished Jul 23 06:39:02 PM PDT 24
Peak memory 206740 kb
Host smart-09d95453-72b5-49f0-a194-6a5560938a46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23754
76565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.2375476565
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.4056577221
Short name T473
Test name
Test status
Simulation time 167017519 ps
CPU time 0.83 seconds
Started Jul 23 06:39:01 PM PDT 24
Finished Jul 23 06:39:03 PM PDT 24
Peak memory 206740 kb
Host smart-e89b3b09-b612-4193-a541-13e49dbf28f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40565
77221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.4056577221
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.3351821606
Short name T2030
Test name
Test status
Simulation time 263246054 ps
CPU time 1.08 seconds
Started Jul 23 06:39:02 PM PDT 24
Finished Jul 23 06:39:05 PM PDT 24
Peak memory 206740 kb
Host smart-ec32b0e4-c064-49dd-9d24-261feadf161a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33518
21606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.3351821606
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.2781006269
Short name T2722
Test name
Test status
Simulation time 4881227853 ps
CPU time 37.16 seconds
Started Jul 23 06:39:01 PM PDT 24
Finished Jul 23 06:39:39 PM PDT 24
Peak memory 206968 kb
Host smart-78ac3fd6-a301-47f1-a286-5adedd365ca7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2781006269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.2781006269
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.1729674643
Short name T1986
Test name
Test status
Simulation time 214310433 ps
CPU time 0.88 seconds
Started Jul 23 06:39:00 PM PDT 24
Finished Jul 23 06:39:01 PM PDT 24
Peak memory 206696 kb
Host smart-28e9448f-8617-4b8e-9b10-88eccdfc7f35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17296
74643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.1729674643
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.3575197586
Short name T876
Test name
Test status
Simulation time 160902050 ps
CPU time 0.79 seconds
Started Jul 23 06:39:01 PM PDT 24
Finished Jul 23 06:39:03 PM PDT 24
Peak memory 206740 kb
Host smart-1cc85e68-bb5b-440f-97d8-70882e8e7133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35751
97586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.3575197586
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.2869868366
Short name T1682
Test name
Test status
Simulation time 1378948185 ps
CPU time 2.89 seconds
Started Jul 23 06:39:01 PM PDT 24
Finished Jul 23 06:39:05 PM PDT 24
Peak memory 206888 kb
Host smart-85036ba7-0c03-4c9d-83eb-3c5139c9f24d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28698
68366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.2869868366
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.1371493244
Short name T2233
Test name
Test status
Simulation time 4465510512 ps
CPU time 41.64 seconds
Started Jul 23 06:39:01 PM PDT 24
Finished Jul 23 06:39:44 PM PDT 24
Peak memory 206892 kb
Host smart-90d47205-64a5-44a1-9e86-4cd22e818b39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13714
93244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.1371493244
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.4048535825
Short name T1412
Test name
Test status
Simulation time 59944448 ps
CPU time 0.7 seconds
Started Jul 23 06:39:17 PM PDT 24
Finished Jul 23 06:39:19 PM PDT 24
Peak memory 206900 kb
Host smart-f40b089c-d977-4a9b-94ff-f7685b00c6a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4048535825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.4048535825
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.662982100
Short name T1306
Test name
Test status
Simulation time 3862769050 ps
CPU time 5.58 seconds
Started Jul 23 06:39:03 PM PDT 24
Finished Jul 23 06:39:10 PM PDT 24
Peak memory 206900 kb
Host smart-a37ce594-40b9-4861-852d-5ae0d791c4d2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=662982100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.662982100
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.1442791415
Short name T2619
Test name
Test status
Simulation time 13345846083 ps
CPU time 12.02 seconds
Started Jul 23 06:39:15 PM PDT 24
Finished Jul 23 06:39:28 PM PDT 24
Peak memory 206836 kb
Host smart-7f8fbefd-137d-4ada-b8f8-cb4e2f9deabc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1442791415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.1442791415
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.3003781756
Short name T2083
Test name
Test status
Simulation time 23323130529 ps
CPU time 24.41 seconds
Started Jul 23 06:39:01 PM PDT 24
Finished Jul 23 06:39:27 PM PDT 24
Peak memory 206844 kb
Host smart-9b7841b9-5bee-4ee1-875b-6ba72b5a9d78
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3003781756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.3003781756
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.2723616364
Short name T2020
Test name
Test status
Simulation time 159359787 ps
CPU time 0.8 seconds
Started Jul 23 06:39:00 PM PDT 24
Finished Jul 23 06:39:02 PM PDT 24
Peak memory 206764 kb
Host smart-c8a4734c-5d4f-4cc4-a481-57e3232e4f10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27236
16364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2723616364
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.1487908483
Short name T1480
Test name
Test status
Simulation time 148141421 ps
CPU time 0.78 seconds
Started Jul 23 06:39:02 PM PDT 24
Finished Jul 23 06:39:04 PM PDT 24
Peak memory 206756 kb
Host smart-4112a9e1-6bd2-4d3f-8f53-80275b60cd93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14879
08483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.1487908483
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.370793905
Short name T393
Test name
Test status
Simulation time 206563035 ps
CPU time 0.84 seconds
Started Jul 23 06:39:15 PM PDT 24
Finished Jul 23 06:39:18 PM PDT 24
Peak memory 206772 kb
Host smart-25432693-cf90-471c-a253-f53ed219193e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37079
3905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.370793905
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.1230396853
Short name T1701
Test name
Test status
Simulation time 748560564 ps
CPU time 1.75 seconds
Started Jul 23 06:39:09 PM PDT 24
Finished Jul 23 06:39:12 PM PDT 24
Peak memory 206908 kb
Host smart-b451a555-4732-40ff-9bce-19b1d5592886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12303
96853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.1230396853
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.1578405078
Short name T2043
Test name
Test status
Simulation time 6224799573 ps
CPU time 11.84 seconds
Started Jul 23 06:39:08 PM PDT 24
Finished Jul 23 06:39:21 PM PDT 24
Peak memory 206932 kb
Host smart-586989f6-5cc7-4161-bfb9-7994b4910216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15784
05078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.1578405078
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.3757946416
Short name T1857
Test name
Test status
Simulation time 460421497 ps
CPU time 1.36 seconds
Started Jul 23 06:39:05 PM PDT 24
Finished Jul 23 06:39:07 PM PDT 24
Peak memory 206760 kb
Host smart-d37bb5c4-5e48-4bdb-bd12-2061f2b1fdf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37579
46416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.3757946416
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.1190323007
Short name T2158
Test name
Test status
Simulation time 136264558 ps
CPU time 0.78 seconds
Started Jul 23 06:39:08 PM PDT 24
Finished Jul 23 06:39:10 PM PDT 24
Peak memory 206776 kb
Host smart-eb65826b-4564-4a61-9b81-c87d110c5db3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11903
23007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.1190323007
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.283612635
Short name T1815
Test name
Test status
Simulation time 39932310 ps
CPU time 0.7 seconds
Started Jul 23 06:39:06 PM PDT 24
Finished Jul 23 06:39:08 PM PDT 24
Peak memory 206728 kb
Host smart-d9597447-8f79-4a83-adca-6b64743eee7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28361
2635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.283612635
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.2228309613
Short name T974
Test name
Test status
Simulation time 885518969 ps
CPU time 2.03 seconds
Started Jul 23 06:39:06 PM PDT 24
Finished Jul 23 06:39:09 PM PDT 24
Peak memory 206812 kb
Host smart-698ecc04-e78b-4f9c-bd4f-1e577c227547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22283
09613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.2228309613
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.1923017402
Short name T421
Test name
Test status
Simulation time 237885718 ps
CPU time 1.68 seconds
Started Jul 23 06:39:07 PM PDT 24
Finished Jul 23 06:39:09 PM PDT 24
Peak memory 206772 kb
Host smart-76b920b2-85a4-42e7-930f-59d2bbf55150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19230
17402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.1923017402
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.2062862140
Short name T635
Test name
Test status
Simulation time 197677960 ps
CPU time 0.84 seconds
Started Jul 23 06:39:07 PM PDT 24
Finished Jul 23 06:39:09 PM PDT 24
Peak memory 206752 kb
Host smart-4f718d07-1b04-44a8-895e-910a3aba0850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20628
62140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.2062862140
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.1415048990
Short name T2322
Test name
Test status
Simulation time 140116034 ps
CPU time 0.76 seconds
Started Jul 23 06:39:15 PM PDT 24
Finished Jul 23 06:39:18 PM PDT 24
Peak memory 206772 kb
Host smart-5e2d162b-caaa-4f48-b87c-2003b423af3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14150
48990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.1415048990
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.4234321584
Short name T1079
Test name
Test status
Simulation time 246327394 ps
CPU time 0.95 seconds
Started Jul 23 06:39:06 PM PDT 24
Finished Jul 23 06:39:07 PM PDT 24
Peak memory 206784 kb
Host smart-d06db6bb-06a6-4bb1-928d-998e6687fa30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42343
21584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.4234321584
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_iso_retraction.1927855165
Short name T1554
Test name
Test status
Simulation time 14232855054 ps
CPU time 44.72 seconds
Started Jul 23 06:39:15 PM PDT 24
Finished Jul 23 06:40:01 PM PDT 24
Peak memory 206668 kb
Host smart-20dfdfff-ae7b-4a2e-9e4d-9104fa81e428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19278
55165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.1927855165
Directory /workspace/7.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.818962960
Short name T636
Test name
Test status
Simulation time 252226299 ps
CPU time 0.89 seconds
Started Jul 23 06:39:16 PM PDT 24
Finished Jul 23 06:39:18 PM PDT 24
Peak memory 206744 kb
Host smart-5bc36de2-79a2-4402-a49d-1913b427eb97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81896
2960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.818962960
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.1767697739
Short name T1221
Test name
Test status
Simulation time 23279547128 ps
CPU time 24.32 seconds
Started Jul 23 06:39:06 PM PDT 24
Finished Jul 23 06:39:31 PM PDT 24
Peak memory 206808 kb
Host smart-e691cc6f-cdd7-4a72-bf4c-9f18dfd54c64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17676
97739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.1767697739
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.807438401
Short name T608
Test name
Test status
Simulation time 3334272403 ps
CPU time 3.59 seconds
Started Jul 23 06:39:10 PM PDT 24
Finished Jul 23 06:39:14 PM PDT 24
Peak memory 206828 kb
Host smart-64c234a5-2784-4c42-8dff-6964aa6b8a10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80743
8401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.807438401
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.2275337241
Short name T1104
Test name
Test status
Simulation time 9534388549 ps
CPU time 91.23 seconds
Started Jul 23 06:39:08 PM PDT 24
Finished Jul 23 06:40:40 PM PDT 24
Peak memory 206984 kb
Host smart-b96d7a38-5bc0-4f09-876b-3836232b005f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22753
37241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.2275337241
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.4128082710
Short name T1677
Test name
Test status
Simulation time 4844146680 ps
CPU time 138.93 seconds
Started Jul 23 06:39:14 PM PDT 24
Finished Jul 23 06:41:34 PM PDT 24
Peak memory 206860 kb
Host smart-fcff4ec1-2f8d-4657-b9a2-5bc4083e4f28
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4128082710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.4128082710
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.1820757974
Short name T1801
Test name
Test status
Simulation time 237320633 ps
CPU time 0.92 seconds
Started Jul 23 06:39:11 PM PDT 24
Finished Jul 23 06:39:12 PM PDT 24
Peak memory 206772 kb
Host smart-b8c39955-d816-4dc0-8049-5d71b26f9321
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1820757974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.1820757974
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.3308282177
Short name T813
Test name
Test status
Simulation time 193814690 ps
CPU time 0.85 seconds
Started Jul 23 06:39:11 PM PDT 24
Finished Jul 23 06:39:12 PM PDT 24
Peak memory 206760 kb
Host smart-2c7c819c-0db8-4239-9b2d-be1e0b1068bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33082
82177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.3308282177
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.3059356944
Short name T1279
Test name
Test status
Simulation time 4711364871 ps
CPU time 30.69 seconds
Started Jul 23 06:39:27 PM PDT 24
Finished Jul 23 06:39:59 PM PDT 24
Peak memory 206748 kb
Host smart-315ca95c-0f7e-419b-b41a-ad0311c1e0bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30593
56944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.3059356944
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.4181013202
Short name T845
Test name
Test status
Simulation time 4599556805 ps
CPU time 42.96 seconds
Started Jul 23 06:39:12 PM PDT 24
Finished Jul 23 06:39:56 PM PDT 24
Peak memory 206900 kb
Host smart-013ac00c-170b-4930-b6b6-6df1c1378407
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4181013202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.4181013202
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.1850481642
Short name T1989
Test name
Test status
Simulation time 177963916 ps
CPU time 0.79 seconds
Started Jul 23 06:39:12 PM PDT 24
Finished Jul 23 06:39:13 PM PDT 24
Peak memory 206772 kb
Host smart-5cbc3ee8-d126-4fc4-bda9-6aef986d06d6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1850481642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.1850481642
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.2725213730
Short name T2730
Test name
Test status
Simulation time 145783369 ps
CPU time 0.89 seconds
Started Jul 23 06:39:13 PM PDT 24
Finished Jul 23 06:39:15 PM PDT 24
Peak memory 206748 kb
Host smart-b6f92f6e-3ee9-4e2a-9104-6d0711d9b47d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27252
13730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.2725213730
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.1519433164
Short name T130
Test name
Test status
Simulation time 216036539 ps
CPU time 0.89 seconds
Started Jul 23 06:39:14 PM PDT 24
Finished Jul 23 06:39:16 PM PDT 24
Peak memory 206720 kb
Host smart-c05a6ddf-b10a-4b08-b3f3-98539c86df2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15194
33164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.1519433164
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.2773759980
Short name T1869
Test name
Test status
Simulation time 177378418 ps
CPU time 0.78 seconds
Started Jul 23 06:39:26 PM PDT 24
Finished Jul 23 06:39:28 PM PDT 24
Peak memory 206512 kb
Host smart-bedf2c29-545a-4976-b19f-70bfd5f1942e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27737
59980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.2773759980
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.2609861915
Short name T2645
Test name
Test status
Simulation time 152780084 ps
CPU time 0.82 seconds
Started Jul 23 06:39:27 PM PDT 24
Finished Jul 23 06:39:29 PM PDT 24
Peak memory 206516 kb
Host smart-bdc0965f-f34a-4ad1-8826-0aac3240382d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26098
61915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2609861915
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.2080413644
Short name T1663
Test name
Test status
Simulation time 168194249 ps
CPU time 0.82 seconds
Started Jul 23 06:39:11 PM PDT 24
Finished Jul 23 06:39:13 PM PDT 24
Peak memory 206768 kb
Host smart-e270636e-d9bd-44bd-9aa8-7e68fe292165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20804
13644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.2080413644
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.2021677542
Short name T1257
Test name
Test status
Simulation time 172767869 ps
CPU time 0.78 seconds
Started Jul 23 06:39:27 PM PDT 24
Finished Jul 23 06:39:31 PM PDT 24
Peak memory 206516 kb
Host smart-ff8a0a47-f8aa-428c-a2f2-f797221814fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20216
77542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.2021677542
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.3085173689
Short name T2037
Test name
Test status
Simulation time 201131186 ps
CPU time 0.83 seconds
Started Jul 23 06:39:26 PM PDT 24
Finished Jul 23 06:39:28 PM PDT 24
Peak memory 206384 kb
Host smart-325061c8-1e16-422c-85f4-34fe39f747b8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3085173689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.3085173689
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.2618896009
Short name T185
Test name
Test status
Simulation time 141846000 ps
CPU time 0.81 seconds
Started Jul 23 06:39:14 PM PDT 24
Finished Jul 23 06:39:16 PM PDT 24
Peak memory 206748 kb
Host smart-16fb2c03-8bf2-4cf2-9f99-4d7e2ca61637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26188
96009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.2618896009
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.2270711266
Short name T655
Test name
Test status
Simulation time 84212591 ps
CPU time 0.73 seconds
Started Jul 23 06:39:13 PM PDT 24
Finished Jul 23 06:39:14 PM PDT 24
Peak memory 206768 kb
Host smart-27fba37e-edb0-49a6-874e-9ae827ac3671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22707
11266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.2270711266
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.2186230299
Short name T665
Test name
Test status
Simulation time 20437594467 ps
CPU time 43.43 seconds
Started Jul 23 06:39:27 PM PDT 24
Finished Jul 23 06:40:13 PM PDT 24
Peak memory 206760 kb
Host smart-0b8d5090-054c-4852-861c-23e5c7e4b177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21862
30299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.2186230299
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.3131015755
Short name T2009
Test name
Test status
Simulation time 248686990 ps
CPU time 0.89 seconds
Started Jul 23 06:39:14 PM PDT 24
Finished Jul 23 06:39:16 PM PDT 24
Peak memory 206772 kb
Host smart-1a33cdf7-ab61-4d62-977c-8eaa5454960e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31310
15755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.3131015755
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.923922195
Short name T911
Test name
Test status
Simulation time 186907130 ps
CPU time 0.86 seconds
Started Jul 23 06:39:13 PM PDT 24
Finished Jul 23 06:39:15 PM PDT 24
Peak memory 206748 kb
Host smart-72adb5da-6998-4272-8ad4-2459b3106154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92392
2195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.923922195
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.1420372688
Short name T2348
Test name
Test status
Simulation time 13013271305 ps
CPU time 117.14 seconds
Started Jul 23 06:39:13 PM PDT 24
Finished Jul 23 06:41:11 PM PDT 24
Peak memory 207012 kb
Host smart-104f00e3-e7e6-4bfc-8788-4e8905c97c0a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1420372688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.1420372688
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.2971796659
Short name T163
Test name
Test status
Simulation time 8057428093 ps
CPU time 182.61 seconds
Started Jul 23 06:39:26 PM PDT 24
Finished Jul 23 06:42:30 PM PDT 24
Peak memory 206696 kb
Host smart-fe28ee95-69c9-4aa3-8e52-f75002a40f57
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2971796659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.2971796659
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.742778958
Short name T542
Test name
Test status
Simulation time 21348231102 ps
CPU time 117.03 seconds
Started Jul 23 06:39:27 PM PDT 24
Finished Jul 23 06:41:26 PM PDT 24
Peak memory 206708 kb
Host smart-6e3dbffa-ff6b-46f5-8eae-93b8251d6ddd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=742778958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.742778958
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.3011051533
Short name T546
Test name
Test status
Simulation time 163877801 ps
CPU time 0.82 seconds
Started Jul 23 06:39:11 PM PDT 24
Finished Jul 23 06:39:13 PM PDT 24
Peak memory 206784 kb
Host smart-05f56d47-8b04-4f4b-b421-24cba14c71da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30110
51533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.3011051533
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.3742844590
Short name T1721
Test name
Test status
Simulation time 159585890 ps
CPU time 0.83 seconds
Started Jul 23 06:39:13 PM PDT 24
Finished Jul 23 06:39:15 PM PDT 24
Peak memory 206744 kb
Host smart-7d8fdf93-c059-499e-b7e6-678493e2db7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37428
44590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.3742844590
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.1826457408
Short name T727
Test name
Test status
Simulation time 175964312 ps
CPU time 0.84 seconds
Started Jul 23 06:39:12 PM PDT 24
Finished Jul 23 06:39:14 PM PDT 24
Peak memory 206740 kb
Host smart-7d76439e-c6b3-4ba8-ac26-ec82272b42ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18264
57408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.1826457408
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.1321856377
Short name T918
Test name
Test status
Simulation time 153285745 ps
CPU time 0.78 seconds
Started Jul 23 06:39:27 PM PDT 24
Finished Jul 23 06:39:30 PM PDT 24
Peak memory 206512 kb
Host smart-e776478a-a7c2-49c5-9ce8-ddc16c1cd735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13218
56377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.1321856377
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.3623837348
Short name T2577
Test name
Test status
Simulation time 153027900 ps
CPU time 0.75 seconds
Started Jul 23 06:39:26 PM PDT 24
Finished Jul 23 06:39:28 PM PDT 24
Peak memory 206404 kb
Host smart-9aff55a4-a24a-4bf4-bcac-eecc1ae5a917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36238
37348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.3623837348
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.4186213345
Short name T776
Test name
Test status
Simulation time 259092125 ps
CPU time 0.99 seconds
Started Jul 23 06:39:20 PM PDT 24
Finished Jul 23 06:39:21 PM PDT 24
Peak memory 206764 kb
Host smart-0554e819-b3cd-4451-9480-8291789e06ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41862
13345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.4186213345
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.3518733372
Short name T554
Test name
Test status
Simulation time 5365646854 ps
CPU time 52.24 seconds
Started Jul 23 06:39:18 PM PDT 24
Finished Jul 23 06:40:12 PM PDT 24
Peak memory 206988 kb
Host smart-ae2b4d8e-a666-4aad-a0bb-9c95dde25878
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3518733372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.3518733372
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.3993963761
Short name T985
Test name
Test status
Simulation time 165490884 ps
CPU time 0.79 seconds
Started Jul 23 06:39:18 PM PDT 24
Finished Jul 23 06:39:19 PM PDT 24
Peak memory 206760 kb
Host smart-3331d3c0-e93e-4e4e-aca4-ab9d9c1b1387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39939
63761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.3993963761
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.4062728180
Short name T1190
Test name
Test status
Simulation time 155060850 ps
CPU time 0.84 seconds
Started Jul 23 06:39:21 PM PDT 24
Finished Jul 23 06:39:22 PM PDT 24
Peak memory 206708 kb
Host smart-e9d16f6a-14ce-41c7-9d49-4649b9b2f1e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40627
28180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.4062728180
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.871028156
Short name T430
Test name
Test status
Simulation time 1319276532 ps
CPU time 2.69 seconds
Started Jul 23 06:39:18 PM PDT 24
Finished Jul 23 06:39:22 PM PDT 24
Peak memory 206812 kb
Host smart-1b41f885-c7e6-49eb-ba50-f75aac8260d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87102
8156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.871028156
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.1610497557
Short name T2412
Test name
Test status
Simulation time 6784344204 ps
CPU time 182.64 seconds
Started Jul 23 06:39:17 PM PDT 24
Finished Jul 23 06:42:20 PM PDT 24
Peak memory 206892 kb
Host smart-4395bd3a-5c02-4a12-a188-9db0a6ad956e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16104
97557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.1610497557
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.3177386602
Short name T422
Test name
Test status
Simulation time 100287875 ps
CPU time 0.71 seconds
Started Jul 23 06:39:35 PM PDT 24
Finished Jul 23 06:39:38 PM PDT 24
Peak memory 206744 kb
Host smart-72ed444e-5771-4860-91e5-ad61da69c333
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3177386602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.3177386602
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.1073323777
Short name T2299
Test name
Test status
Simulation time 4273220582 ps
CPU time 5.33 seconds
Started Jul 23 06:39:17 PM PDT 24
Finished Jul 23 06:39:24 PM PDT 24
Peak memory 206844 kb
Host smart-ca00b9f8-02bd-46c7-8ac0-ce23d74f5f88
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1073323777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.1073323777
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.1784205288
Short name T2084
Test name
Test status
Simulation time 13316602715 ps
CPU time 13.27 seconds
Started Jul 23 06:39:18 PM PDT 24
Finished Jul 23 06:39:33 PM PDT 24
Peak memory 206780 kb
Host smart-8b21c305-b638-4b91-aaa7-f85fbeadb0cc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1784205288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.1784205288
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.4132731579
Short name T10
Test name
Test status
Simulation time 23365892555 ps
CPU time 24.92 seconds
Started Jul 23 06:39:19 PM PDT 24
Finished Jul 23 06:39:45 PM PDT 24
Peak memory 206716 kb
Host smart-51023174-c08c-495e-a083-4b783f745f97
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4132731579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.4132731579
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.3790347096
Short name T2403
Test name
Test status
Simulation time 207967065 ps
CPU time 0.84 seconds
Started Jul 23 06:39:20 PM PDT 24
Finished Jul 23 06:39:21 PM PDT 24
Peak memory 206760 kb
Host smart-6b9d5e4b-2e85-4b66-93c4-54fb5fa3316b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37903
47096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.3790347096
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.3815308216
Short name T1313
Test name
Test status
Simulation time 144659209 ps
CPU time 0.8 seconds
Started Jul 23 06:39:16 PM PDT 24
Finished Jul 23 06:39:18 PM PDT 24
Peak memory 206736 kb
Host smart-55b7005d-353f-42b9-ae7d-9862f9099a71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38153
08216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.3815308216
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.393061150
Short name T1576
Test name
Test status
Simulation time 233667452 ps
CPU time 0.98 seconds
Started Jul 23 06:39:18 PM PDT 24
Finished Jul 23 06:39:20 PM PDT 24
Peak memory 206772 kb
Host smart-d23dc94d-4983-4814-8382-0943dabdc12d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39306
1150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.393061150
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.2775514765
Short name T2737
Test name
Test status
Simulation time 1090391603 ps
CPU time 2.35 seconds
Started Jul 23 06:40:18 PM PDT 24
Finished Jul 23 06:40:23 PM PDT 24
Peak memory 205916 kb
Host smart-0d9d0282-9051-4201-9e28-ca50b0542632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27755
14765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.2775514765
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.4157845539
Short name T437
Test name
Test status
Simulation time 22707832576 ps
CPU time 41.69 seconds
Started Jul 23 06:39:18 PM PDT 24
Finished Jul 23 06:40:01 PM PDT 24
Peak memory 206932 kb
Host smart-05e0f6d3-834b-418c-8f7d-4b62d834a553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41578
45539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.4157845539
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.2283636578
Short name T93
Test name
Test status
Simulation time 408418319 ps
CPU time 1.23 seconds
Started Jul 23 06:39:18 PM PDT 24
Finished Jul 23 06:39:21 PM PDT 24
Peak memory 206724 kb
Host smart-fe352559-f0fe-4aba-b7b7-5b072d6b2300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22836
36578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.2283636578
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.2772083059
Short name T1528
Test name
Test status
Simulation time 163423577 ps
CPU time 0.78 seconds
Started Jul 23 06:39:18 PM PDT 24
Finished Jul 23 06:39:19 PM PDT 24
Peak memory 206752 kb
Host smart-55e1f717-dda0-40c5-be2f-158c918623d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27720
83059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.2772083059
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.1036845514
Short name T1485
Test name
Test status
Simulation time 38972555 ps
CPU time 0.68 seconds
Started Jul 23 06:39:27 PM PDT 24
Finished Jul 23 06:39:30 PM PDT 24
Peak memory 206728 kb
Host smart-4daa537b-b26a-49bb-b7e5-b979deaaf251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10368
45514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.1036845514
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.2395326849
Short name T1029
Test name
Test status
Simulation time 888979951 ps
CPU time 2.07 seconds
Started Jul 23 06:39:24 PM PDT 24
Finished Jul 23 06:39:27 PM PDT 24
Peak memory 206928 kb
Host smart-51292cb2-fa37-4598-aac3-73f97572898e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23953
26849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.2395326849
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.2626506650
Short name T1419
Test name
Test status
Simulation time 199784496 ps
CPU time 1.29 seconds
Started Jul 23 06:39:23 PM PDT 24
Finished Jul 23 06:39:25 PM PDT 24
Peak memory 206884 kb
Host smart-58b09631-5933-419e-aeed-a3971f482d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26265
06650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.2626506650
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.256420768
Short name T2344
Test name
Test status
Simulation time 156551149 ps
CPU time 0.81 seconds
Started Jul 23 06:39:24 PM PDT 24
Finished Jul 23 06:39:27 PM PDT 24
Peak memory 206740 kb
Host smart-d3086e22-08a9-446e-84d5-11be3c976e30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25642
0768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.256420768
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.3638162634
Short name T579
Test name
Test status
Simulation time 155053402 ps
CPU time 0.8 seconds
Started Jul 23 06:39:23 PM PDT 24
Finished Jul 23 06:39:25 PM PDT 24
Peak memory 206736 kb
Host smart-a3f9e1d9-b02c-493b-9c22-9e03253fbe54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36381
62634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.3638162634
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.3218531668
Short name T534
Test name
Test status
Simulation time 231779113 ps
CPU time 0.93 seconds
Started Jul 23 06:39:23 PM PDT 24
Finished Jul 23 06:39:25 PM PDT 24
Peak memory 206752 kb
Host smart-3f83e136-1006-437e-9eaa-64bd076d105f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32185
31668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.3218531668
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.3353775245
Short name T849
Test name
Test status
Simulation time 250469919 ps
CPU time 0.88 seconds
Started Jul 23 06:39:22 PM PDT 24
Finished Jul 23 06:39:24 PM PDT 24
Peak memory 206740 kb
Host smart-d8954cdc-2fd5-454f-8e83-93ef56a8ce4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33537
75245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.3353775245
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.2085975260
Short name T1199
Test name
Test status
Simulation time 23290039141 ps
CPU time 21.68 seconds
Started Jul 23 06:39:23 PM PDT 24
Finished Jul 23 06:39:47 PM PDT 24
Peak memory 206796 kb
Host smart-b6043549-d017-42e9-acb0-b18f0eb24bf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20859
75260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.2085975260
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.3762054229
Short name T558
Test name
Test status
Simulation time 3304193627 ps
CPU time 3.64 seconds
Started Jul 23 06:39:23 PM PDT 24
Finished Jul 23 06:39:28 PM PDT 24
Peak memory 206832 kb
Host smart-9abe8b86-7a00-4eec-a85a-adc8b141b70d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37620
54229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.3762054229
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.3665473269
Short name T1333
Test name
Test status
Simulation time 11996999504 ps
CPU time 113.64 seconds
Started Jul 23 06:39:22 PM PDT 24
Finished Jul 23 06:41:17 PM PDT 24
Peak memory 206980 kb
Host smart-7301e39c-6d88-46f6-aba0-88563dce1b83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36654
73269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.3665473269
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.1226750806
Short name T701
Test name
Test status
Simulation time 5832619947 ps
CPU time 165.46 seconds
Started Jul 23 06:39:25 PM PDT 24
Finished Jul 23 06:42:12 PM PDT 24
Peak memory 206904 kb
Host smart-aaac6f71-4445-468b-b36d-5106faf81f5c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1226750806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.1226750806
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.1240295663
Short name T1121
Test name
Test status
Simulation time 239513023 ps
CPU time 0.9 seconds
Started Jul 23 06:39:26 PM PDT 24
Finished Jul 23 06:39:29 PM PDT 24
Peak memory 206772 kb
Host smart-30143188-b6a5-4d50-8f5a-cbf5838ffb63
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1240295663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.1240295663
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.4069632920
Short name T2598
Test name
Test status
Simulation time 205259154 ps
CPU time 0.91 seconds
Started Jul 23 06:39:24 PM PDT 24
Finished Jul 23 06:39:26 PM PDT 24
Peak memory 206752 kb
Host smart-c4b11203-c2ed-4e35-b62d-ba79dcffaf1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40696
32920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.4069632920
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.4062590026
Short name T1046
Test name
Test status
Simulation time 5320217943 ps
CPU time 50.86 seconds
Started Jul 23 06:39:25 PM PDT 24
Finished Jul 23 06:40:17 PM PDT 24
Peak memory 206908 kb
Host smart-11f3acb8-45af-48a5-b931-db78447c50e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40625
90026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.4062590026
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.2234812477
Short name T1357
Test name
Test status
Simulation time 6994938611 ps
CPU time 67.19 seconds
Started Jul 23 06:39:24 PM PDT 24
Finished Jul 23 06:40:33 PM PDT 24
Peak memory 206988 kb
Host smart-408f9950-c495-4693-83e6-7aeb1495d7e2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2234812477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.2234812477
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.1260960218
Short name T1249
Test name
Test status
Simulation time 171204534 ps
CPU time 0.79 seconds
Started Jul 23 06:39:23 PM PDT 24
Finished Jul 23 06:39:25 PM PDT 24
Peak memory 206668 kb
Host smart-14eca996-5dfd-406b-866d-215e895368d9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1260960218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.1260960218
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.243368411
Short name T2556
Test name
Test status
Simulation time 142176964 ps
CPU time 0.77 seconds
Started Jul 23 06:39:26 PM PDT 24
Finished Jul 23 06:39:28 PM PDT 24
Peak memory 206744 kb
Host smart-5c9eb1e7-d235-4322-8fed-7b5874b140ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24336
8411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.243368411
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.2593411146
Short name T145
Test name
Test status
Simulation time 258993576 ps
CPU time 0.94 seconds
Started Jul 23 06:39:24 PM PDT 24
Finished Jul 23 06:39:26 PM PDT 24
Peak memory 206728 kb
Host smart-0da4e7dd-13d1-4eeb-91fb-0b1250fba702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25934
11146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.2593411146
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.4069604805
Short name T2071
Test name
Test status
Simulation time 178915845 ps
CPU time 0.83 seconds
Started Jul 23 06:39:23 PM PDT 24
Finished Jul 23 06:39:25 PM PDT 24
Peak memory 206752 kb
Host smart-15faa94f-c246-4412-b62f-e15cd959640b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40696
04805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.4069604805
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.3223153563
Short name T1074
Test name
Test status
Simulation time 202501802 ps
CPU time 0.82 seconds
Started Jul 23 06:39:28 PM PDT 24
Finished Jul 23 06:39:32 PM PDT 24
Peak memory 206752 kb
Host smart-8c62204b-cb3f-428e-87e8-d8032a3f5f23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32231
53563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.3223153563
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.1895033286
Short name T921
Test name
Test status
Simulation time 156065405 ps
CPU time 0.77 seconds
Started Jul 23 06:39:29 PM PDT 24
Finished Jul 23 06:39:32 PM PDT 24
Peak memory 206636 kb
Host smart-d82e55fb-c156-40d1-9b7c-c122d8be3e67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18950
33286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.1895033286
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.1319897446
Short name T1462
Test name
Test status
Simulation time 146556573 ps
CPU time 0.8 seconds
Started Jul 23 06:39:28 PM PDT 24
Finished Jul 23 06:39:32 PM PDT 24
Peak memory 206772 kb
Host smart-04aea8a4-e40d-427f-8713-1deae5eb5f2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13198
97446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.1319897446
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.2193565230
Short name T1421
Test name
Test status
Simulation time 191450222 ps
CPU time 0.86 seconds
Started Jul 23 06:39:27 PM PDT 24
Finished Jul 23 06:39:31 PM PDT 24
Peak memory 206764 kb
Host smart-98b25644-ecde-4e83-8fc9-b18a5ecafae2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2193565230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.2193565230
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.2892202014
Short name T622
Test name
Test status
Simulation time 158968755 ps
CPU time 0.82 seconds
Started Jul 23 06:39:30 PM PDT 24
Finished Jul 23 06:39:33 PM PDT 24
Peak memory 206748 kb
Host smart-391be41a-314c-4c55-bf43-da85aff1487f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28922
02014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.2892202014
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.2981192319
Short name T1193
Test name
Test status
Simulation time 37519347 ps
CPU time 0.67 seconds
Started Jul 23 06:39:27 PM PDT 24
Finished Jul 23 06:39:30 PM PDT 24
Peak memory 206716 kb
Host smart-0099579b-09f5-4dd4-b9f1-7ba12cb0e44e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29811
92319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.2981192319
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.2638320738
Short name T245
Test name
Test status
Simulation time 8395285722 ps
CPU time 18.02 seconds
Started Jul 23 06:39:28 PM PDT 24
Finished Jul 23 06:39:48 PM PDT 24
Peak memory 206964 kb
Host smart-a8fe43bf-70cd-4eaf-94ea-904d19ba7483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26383
20738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.2638320738
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.1928473012
Short name T2337
Test name
Test status
Simulation time 187542607 ps
CPU time 0.88 seconds
Started Jul 23 06:39:33 PM PDT 24
Finished Jul 23 06:39:36 PM PDT 24
Peak memory 206740 kb
Host smart-12476c11-1cfd-47b7-a050-f85e7620e5a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19284
73012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.1928473012
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.35860456
Short name T541
Test name
Test status
Simulation time 209222524 ps
CPU time 0.93 seconds
Started Jul 23 06:39:28 PM PDT 24
Finished Jul 23 06:39:31 PM PDT 24
Peak memory 206764 kb
Host smart-ecdc98bb-cf52-4ed3-bfc3-bc7f60681bce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35860
456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.35860456
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.1816817093
Short name T1443
Test name
Test status
Simulation time 11633674705 ps
CPU time 84.26 seconds
Started Jul 23 06:39:27 PM PDT 24
Finished Jul 23 06:40:54 PM PDT 24
Peak memory 206952 kb
Host smart-687f846a-0b79-4efd-98f8-8787f58b8a36
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1816817093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.1816817093
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.3242842115
Short name T1153
Test name
Test status
Simulation time 9995642036 ps
CPU time 87.34 seconds
Started Jul 23 06:39:30 PM PDT 24
Finished Jul 23 06:40:59 PM PDT 24
Peak memory 206872 kb
Host smart-accb0fa8-01a5-47b4-a617-e8e3fdadeb02
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3242842115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.3242842115
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.3178713101
Short name T1921
Test name
Test status
Simulation time 15976265647 ps
CPU time 343.42 seconds
Started Jul 23 06:39:31 PM PDT 24
Finished Jul 23 06:45:16 PM PDT 24
Peak memory 206908 kb
Host smart-c0aab6e2-904b-482e-ab54-f1b05eb4e43f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3178713101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.3178713101
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.658384897
Short name T371
Test name
Test status
Simulation time 190678589 ps
CPU time 0.86 seconds
Started Jul 23 06:39:30 PM PDT 24
Finished Jul 23 06:39:33 PM PDT 24
Peak memory 206756 kb
Host smart-e0656abf-c2d9-416b-a0f5-5afc3dfc2c31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65838
4897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.658384897
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.3259931122
Short name T637
Test name
Test status
Simulation time 161298013 ps
CPU time 0.8 seconds
Started Jul 23 06:39:33 PM PDT 24
Finished Jul 23 06:39:36 PM PDT 24
Peak memory 206732 kb
Host smart-0484b2fa-2bbe-4587-b3c5-3adc15eb7475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32599
31122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.3259931122
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.1856165689
Short name T470
Test name
Test status
Simulation time 203657929 ps
CPU time 0.83 seconds
Started Jul 23 06:39:28 PM PDT 24
Finished Jul 23 06:39:31 PM PDT 24
Peak memory 206760 kb
Host smart-23809b8b-8b0b-421c-a83b-cf795f301557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18561
65689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.1856165689
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.2688668074
Short name T1356
Test name
Test status
Simulation time 156489707 ps
CPU time 0.8 seconds
Started Jul 23 06:39:33 PM PDT 24
Finished Jul 23 06:39:37 PM PDT 24
Peak memory 206736 kb
Host smart-cfea15f2-d3fc-43e6-a7a4-ecdd98aef47a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26886
68074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.2688668074
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.396356735
Short name T375
Test name
Test status
Simulation time 148781037 ps
CPU time 0.77 seconds
Started Jul 23 06:39:28 PM PDT 24
Finished Jul 23 06:39:32 PM PDT 24
Peak memory 206664 kb
Host smart-a3142f30-ce3e-4158-b47d-cb0a0b8a3a7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39635
6735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.396356735
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.3029184609
Short name T1847
Test name
Test status
Simulation time 199381276 ps
CPU time 0.88 seconds
Started Jul 23 06:39:31 PM PDT 24
Finished Jul 23 06:39:33 PM PDT 24
Peak memory 206728 kb
Host smart-02b0d307-3e7b-400d-8b47-bd083f912ec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30291
84609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.3029184609
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.915661263
Short name T1071
Test name
Test status
Simulation time 5071438211 ps
CPU time 142.67 seconds
Started Jul 23 06:39:28 PM PDT 24
Finished Jul 23 06:41:53 PM PDT 24
Peak memory 206904 kb
Host smart-8fbd6402-6383-4689-85a9-af556a3f1ed8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=915661263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.915661263
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.4198213688
Short name T772
Test name
Test status
Simulation time 149702548 ps
CPU time 0.84 seconds
Started Jul 23 06:39:28 PM PDT 24
Finished Jul 23 06:39:31 PM PDT 24
Peak memory 206752 kb
Host smart-b7f74d3a-02a8-49c5-9ab1-334b04adc0ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41982
13688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.4198213688
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.3093202798
Short name T1061
Test name
Test status
Simulation time 188238666 ps
CPU time 0.77 seconds
Started Jul 23 06:39:27 PM PDT 24
Finished Jul 23 06:39:30 PM PDT 24
Peak memory 206740 kb
Host smart-4d55db37-0427-4921-8a39-67029e352709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30932
02798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.3093202798
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.1216158359
Short name T2152
Test name
Test status
Simulation time 1213223033 ps
CPU time 2.62 seconds
Started Jul 23 06:39:37 PM PDT 24
Finished Jul 23 06:39:41 PM PDT 24
Peak memory 206920 kb
Host smart-d93d7b6c-dbf0-45fd-ba7e-8291e88d9606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12161
58359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.1216158359
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.3517161944
Short name T539
Test name
Test status
Simulation time 4770123449 ps
CPU time 132.28 seconds
Started Jul 23 06:39:31 PM PDT 24
Finished Jul 23 06:41:44 PM PDT 24
Peak memory 206900 kb
Host smart-95d393ba-d2e2-433b-a517-9913991aee6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35171
61944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.3517161944
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.1447859949
Short name T2113
Test name
Test status
Simulation time 77485216 ps
CPU time 0.71 seconds
Started Jul 23 06:39:51 PM PDT 24
Finished Jul 23 06:39:54 PM PDT 24
Peak memory 206756 kb
Host smart-6388dfed-af2c-44d6-9a2e-c12a7e117643
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1447859949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.1447859949
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.2435881110
Short name T700
Test name
Test status
Simulation time 13297191777 ps
CPU time 11.77 seconds
Started Jul 23 06:39:34 PM PDT 24
Finished Jul 23 06:39:48 PM PDT 24
Peak memory 206944 kb
Host smart-8e6c971f-f51e-4840-ad4a-674d73fe46fe
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2435881110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.2435881110
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.2169395994
Short name T2708
Test name
Test status
Simulation time 23366926835 ps
CPU time 30.05 seconds
Started Jul 23 06:39:35 PM PDT 24
Finished Jul 23 06:40:07 PM PDT 24
Peak memory 206820 kb
Host smart-f6bd5926-77bc-4774-be0f-4e09e3618766
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2169395994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.2169395994
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.3607023050
Short name T855
Test name
Test status
Simulation time 173946929 ps
CPU time 0.84 seconds
Started Jul 23 06:39:35 PM PDT 24
Finished Jul 23 06:39:38 PM PDT 24
Peak memory 206788 kb
Host smart-8e827668-6e12-4585-82fe-38fea3388fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36070
23050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.3607023050
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.4180440491
Short name T643
Test name
Test status
Simulation time 166803323 ps
CPU time 0.8 seconds
Started Jul 23 06:39:35 PM PDT 24
Finished Jul 23 06:39:38 PM PDT 24
Peak memory 206780 kb
Host smart-1e94a513-aa10-46bf-93fc-254f45da47a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41804
40491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.4180440491
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.2734879196
Short name T2052
Test name
Test status
Simulation time 186405995 ps
CPU time 0.84 seconds
Started Jul 23 06:39:35 PM PDT 24
Finished Jul 23 06:39:38 PM PDT 24
Peak memory 206752 kb
Host smart-74d17143-f852-4114-bbe5-bf6e77194989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27348
79196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.2734879196
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.2165194541
Short name T553
Test name
Test status
Simulation time 1039024422 ps
CPU time 2.47 seconds
Started Jul 23 06:39:35 PM PDT 24
Finished Jul 23 06:39:40 PM PDT 24
Peak memory 206880 kb
Host smart-700ca590-f932-4a74-a471-805d8d0d8547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21651
94541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.2165194541
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.241338057
Short name T474
Test name
Test status
Simulation time 20909102004 ps
CPU time 37.91 seconds
Started Jul 23 06:39:35 PM PDT 24
Finished Jul 23 06:40:15 PM PDT 24
Peak memory 206888 kb
Host smart-2dadebdd-928e-4a61-8999-d96d59cc2fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24133
8057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.241338057
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.1077702738
Short name T2550
Test name
Test status
Simulation time 472148180 ps
CPU time 1.28 seconds
Started Jul 23 06:39:35 PM PDT 24
Finished Jul 23 06:39:39 PM PDT 24
Peak memory 206656 kb
Host smart-43d9a717-4dcf-4ef4-8296-1912a0421f7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10777
02738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.1077702738
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.2763243646
Short name T1200
Test name
Test status
Simulation time 146315660 ps
CPU time 0.79 seconds
Started Jul 23 06:39:42 PM PDT 24
Finished Jul 23 06:39:45 PM PDT 24
Peak memory 206780 kb
Host smart-997d0c0d-08e5-4a79-b71f-d4ae9feaddef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27632
43646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.2763243646
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.352522251
Short name T1950
Test name
Test status
Simulation time 46845085 ps
CPU time 0.66 seconds
Started Jul 23 06:39:40 PM PDT 24
Finished Jul 23 06:39:42 PM PDT 24
Peak memory 206748 kb
Host smart-81d430a9-f6d8-48ee-a6ba-119a3129cd79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35252
2251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.352522251
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.3042267326
Short name T1034
Test name
Test status
Simulation time 817750233 ps
CPU time 1.94 seconds
Started Jul 23 06:39:40 PM PDT 24
Finished Jul 23 06:39:44 PM PDT 24
Peak memory 206864 kb
Host smart-8b4761b9-ca5a-446e-b07e-378f0b367f49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30422
67326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.3042267326
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.1043449158
Short name T2670
Test name
Test status
Simulation time 168185026 ps
CPU time 1.59 seconds
Started Jul 23 06:39:40 PM PDT 24
Finished Jul 23 06:39:43 PM PDT 24
Peak memory 206784 kb
Host smart-22efed8b-b945-4925-93f4-4b3f26eaac6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10434
49158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.1043449158
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.1602706103
Short name T551
Test name
Test status
Simulation time 266237484 ps
CPU time 0.96 seconds
Started Jul 23 06:39:43 PM PDT 24
Finished Jul 23 06:39:46 PM PDT 24
Peak memory 206764 kb
Host smart-a7e06256-4291-41b3-89e8-eb6947cd2caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16027
06103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.1602706103
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.1984915557
Short name T1984
Test name
Test status
Simulation time 143836977 ps
CPU time 0.74 seconds
Started Jul 23 06:39:40 PM PDT 24
Finished Jul 23 06:39:43 PM PDT 24
Peak memory 206764 kb
Host smart-c55fe329-41f5-429d-b86a-aaf265ff1230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19849
15557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.1984915557
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.1549625499
Short name T1877
Test name
Test status
Simulation time 221587523 ps
CPU time 0.92 seconds
Started Jul 23 06:39:40 PM PDT 24
Finished Jul 23 06:39:42 PM PDT 24
Peak memory 206712 kb
Host smart-6779d536-1a5c-4d34-a16f-c1202e830e03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15496
25499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.1549625499
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_iso_retraction.3529207382
Short name T2414
Test name
Test status
Simulation time 3606628367 ps
CPU time 31.67 seconds
Started Jul 23 06:39:40 PM PDT 24
Finished Jul 23 06:40:14 PM PDT 24
Peak memory 206988 kb
Host smart-fc646ac0-d3e8-497e-8e0d-3b91ccdee0b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35292
07382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.3529207382
Directory /workspace/9.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.1959911263
Short name T1938
Test name
Test status
Simulation time 188695996 ps
CPU time 0.83 seconds
Started Jul 23 06:39:41 PM PDT 24
Finished Jul 23 06:39:45 PM PDT 24
Peak memory 206752 kb
Host smart-fd95984d-8611-411d-9ff1-14f1d484b645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19599
11263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.1959911263
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.4179890314
Short name T324
Test name
Test status
Simulation time 23332029386 ps
CPU time 23.05 seconds
Started Jul 23 06:39:43 PM PDT 24
Finished Jul 23 06:40:08 PM PDT 24
Peak memory 206824 kb
Host smart-88cc9c93-73b1-4b06-8c6a-975d3d368c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41798
90314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.4179890314
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.105851829
Short name T354
Test name
Test status
Simulation time 3371925947 ps
CPU time 3.84 seconds
Started Jul 23 06:39:41 PM PDT 24
Finished Jul 23 06:39:47 PM PDT 24
Peak memory 206804 kb
Host smart-16f15c01-7d69-43f5-b871-f279933cc9ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10585
1829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.105851829
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.2405332695
Short name T1282
Test name
Test status
Simulation time 6346312116 ps
CPU time 173.14 seconds
Started Jul 23 06:39:41 PM PDT 24
Finished Jul 23 06:42:37 PM PDT 24
Peak memory 206904 kb
Host smart-22470579-9911-4400-85b0-e6e343170f55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24053
32695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.2405332695
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.3746910887
Short name T482
Test name
Test status
Simulation time 4742436643 ps
CPU time 130.17 seconds
Started Jul 23 06:39:40 PM PDT 24
Finished Jul 23 06:41:53 PM PDT 24
Peak memory 206912 kb
Host smart-a1a7dd45-3a2a-42b1-95d5-8121b8f6edc4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3746910887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.3746910887
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.299052925
Short name T2507
Test name
Test status
Simulation time 248471624 ps
CPU time 0.89 seconds
Started Jul 23 06:39:40 PM PDT 24
Finished Jul 23 06:39:42 PM PDT 24
Peak memory 206772 kb
Host smart-1db59047-ecc7-4ec4-ad4d-8ee5fcd71456
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=299052925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.299052925
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.2014078579
Short name T1633
Test name
Test status
Simulation time 195305447 ps
CPU time 0.9 seconds
Started Jul 23 06:39:40 PM PDT 24
Finished Jul 23 06:39:43 PM PDT 24
Peak memory 206752 kb
Host smart-6ef9be91-e1e1-41a9-803c-d8d67dc365a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20140
78579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.2014078579
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.3853691549
Short name T1718
Test name
Test status
Simulation time 3386435459 ps
CPU time 23.24 seconds
Started Jul 23 06:39:41 PM PDT 24
Finished Jul 23 06:40:07 PM PDT 24
Peak memory 206964 kb
Host smart-ce26ecb1-744a-4354-b33d-7972ade1dcbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38536
91549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.3853691549
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.2541832197
Short name T2081
Test name
Test status
Simulation time 5262044920 ps
CPU time 49.64 seconds
Started Jul 23 06:39:41 PM PDT 24
Finished Jul 23 06:40:33 PM PDT 24
Peak memory 206972 kb
Host smart-bfdd45c3-cf0a-4b44-9132-9c789417d0fa
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2541832197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.2541832197
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.3041815135
Short name T240
Test name
Test status
Simulation time 154353778 ps
CPU time 0.81 seconds
Started Jul 23 06:39:41 PM PDT 24
Finished Jul 23 06:39:44 PM PDT 24
Peak memory 206760 kb
Host smart-d73b7b7f-c385-43b6-a7a2-c427a45328b0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3041815135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.3041815135
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.269642297
Short name T1946
Test name
Test status
Simulation time 172818506 ps
CPU time 0.83 seconds
Started Jul 23 06:39:42 PM PDT 24
Finished Jul 23 06:39:46 PM PDT 24
Peak memory 206764 kb
Host smart-355e4f68-40fe-4246-acf0-1b10253cb36c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26964
2297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.269642297
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.2339598109
Short name T129
Test name
Test status
Simulation time 168763355 ps
CPU time 0.9 seconds
Started Jul 23 06:39:41 PM PDT 24
Finished Jul 23 06:39:44 PM PDT 24
Peak memory 206772 kb
Host smart-f94f2b38-19fc-4daa-bbb7-df8f35312fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23395
98109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.2339598109
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.3421905281
Short name T1370
Test name
Test status
Simulation time 216508139 ps
CPU time 0.88 seconds
Started Jul 23 06:39:41 PM PDT 24
Finished Jul 23 06:39:45 PM PDT 24
Peak memory 206744 kb
Host smart-2bf6ce9f-5113-485d-bbed-56dba81f8819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34219
05281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.3421905281
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.3925847306
Short name T557
Test name
Test status
Simulation time 152958230 ps
CPU time 0.77 seconds
Started Jul 23 06:39:40 PM PDT 24
Finished Jul 23 06:39:43 PM PDT 24
Peak memory 206724 kb
Host smart-a35027a4-a417-46ba-828a-ded0a06a9014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39258
47306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.3925847306
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.1440491514
Short name T2056
Test name
Test status
Simulation time 145137597 ps
CPU time 0.79 seconds
Started Jul 23 06:39:40 PM PDT 24
Finished Jul 23 06:39:43 PM PDT 24
Peak memory 206740 kb
Host smart-d602bf50-ea8c-4763-93ee-3dd37091c6e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14404
91514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.1440491514
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.1839855044
Short name T1270
Test name
Test status
Simulation time 177413319 ps
CPU time 0.8 seconds
Started Jul 23 06:39:41 PM PDT 24
Finished Jul 23 06:39:45 PM PDT 24
Peak memory 206748 kb
Host smart-f402985e-cdc9-417e-b1f4-6b289954fae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18398
55044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.1839855044
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.105033825
Short name T577
Test name
Test status
Simulation time 213292928 ps
CPU time 0.88 seconds
Started Jul 23 06:39:47 PM PDT 24
Finished Jul 23 06:39:51 PM PDT 24
Peak memory 206776 kb
Host smart-03d6ae26-b803-4e9a-b6d0-77569e0168fb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=105033825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.105033825
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.2762209159
Short name T1702
Test name
Test status
Simulation time 143932693 ps
CPU time 0.79 seconds
Started Jul 23 06:39:48 PM PDT 24
Finished Jul 23 06:39:51 PM PDT 24
Peak memory 206736 kb
Host smart-51a5b7af-70b1-4176-86c7-d878f9ebfe60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27622
09159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.2762209159
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.1218240301
Short name T2549
Test name
Test status
Simulation time 30477412 ps
CPU time 0.66 seconds
Started Jul 23 06:39:45 PM PDT 24
Finished Jul 23 06:39:47 PM PDT 24
Peak memory 206916 kb
Host smart-5e400e0c-5dd6-4895-ab2a-1dbf0bf6d350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12182
40301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.1218240301
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.371366057
Short name T2586
Test name
Test status
Simulation time 18796162477 ps
CPU time 41.73 seconds
Started Jul 23 06:39:47 PM PDT 24
Finished Jul 23 06:40:31 PM PDT 24
Peak memory 206952 kb
Host smart-9a62fa00-e7dc-498e-a13e-82f9313efa8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37136
6057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.371366057
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.4093538553
Short name T2474
Test name
Test status
Simulation time 155201763 ps
CPU time 0.8 seconds
Started Jul 23 06:39:45 PM PDT 24
Finished Jul 23 06:39:47 PM PDT 24
Peak memory 206760 kb
Host smart-d8ff8936-9abd-4724-9ae2-45fdbd4f3861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40935
38553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.4093538553
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.3749297882
Short name T1297
Test name
Test status
Simulation time 188663441 ps
CPU time 0.82 seconds
Started Jul 23 06:39:47 PM PDT 24
Finished Jul 23 06:39:50 PM PDT 24
Peak memory 206712 kb
Host smart-ab359ddf-057a-436b-8d54-5bfbc68c72bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37492
97882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.3749297882
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.948113662
Short name T2029
Test name
Test status
Simulation time 15990958626 ps
CPU time 104.91 seconds
Started Jul 23 06:39:46 PM PDT 24
Finished Jul 23 06:41:33 PM PDT 24
Peak memory 206848 kb
Host smart-8b777bb5-5cb3-4845-b256-71ae43dd56e7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=948113662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.948113662
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.3067680534
Short name T173
Test name
Test status
Simulation time 10732873595 ps
CPU time 96.22 seconds
Started Jul 23 06:39:46 PM PDT 24
Finished Jul 23 06:41:23 PM PDT 24
Peak memory 206944 kb
Host smart-dabaf43c-6a32-442b-bb7b-e71821cd1220
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3067680534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.3067680534
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.720736163
Short name T1384
Test name
Test status
Simulation time 14688700977 ps
CPU time 325.89 seconds
Started Jul 23 06:39:46 PM PDT 24
Finished Jul 23 06:45:15 PM PDT 24
Peak memory 206940 kb
Host smart-91658ef8-917a-47e5-ae18-08a6c9afa6b7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=720736163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.720736163
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.3844091618
Short name T2543
Test name
Test status
Simulation time 228589599 ps
CPU time 0.87 seconds
Started Jul 23 06:39:45 PM PDT 24
Finished Jul 23 06:39:47 PM PDT 24
Peak memory 206760 kb
Host smart-500dcf6c-b728-4d3a-b526-3a537025f848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38440
91618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.3844091618
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.1859002057
Short name T1161
Test name
Test status
Simulation time 177672282 ps
CPU time 0.87 seconds
Started Jul 23 06:39:47 PM PDT 24
Finished Jul 23 06:39:50 PM PDT 24
Peak memory 206736 kb
Host smart-469b1441-c9f1-469f-a039-5084c04fbedc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18590
02057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.1859002057
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.2245883420
Short name T3
Test name
Test status
Simulation time 168376226 ps
CPU time 0.79 seconds
Started Jul 23 06:39:45 PM PDT 24
Finished Jul 23 06:39:47 PM PDT 24
Peak memory 206676 kb
Host smart-3e23bfac-64b8-4810-8586-72ea6d851e4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22458
83420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.2245883420
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.1092029975
Short name T1493
Test name
Test status
Simulation time 151157715 ps
CPU time 0.84 seconds
Started Jul 23 06:39:48 PM PDT 24
Finished Jul 23 06:39:51 PM PDT 24
Peak memory 206708 kb
Host smart-4cab6a6c-a9b4-421e-8a58-fa8c12f2efa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10920
29975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.1092029975
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.1423295834
Short name T360
Test name
Test status
Simulation time 153418896 ps
CPU time 0.82 seconds
Started Jul 23 06:39:47 PM PDT 24
Finished Jul 23 06:39:50 PM PDT 24
Peak memory 206760 kb
Host smart-e999259c-72c5-48fc-b65d-17d783a6ac20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14232
95834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.1423295834
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.24081563
Short name T1723
Test name
Test status
Simulation time 261896957 ps
CPU time 0.98 seconds
Started Jul 23 06:39:46 PM PDT 24
Finished Jul 23 06:39:48 PM PDT 24
Peak memory 206752 kb
Host smart-6e161539-6000-48f1-a6fc-c4e20ef87f2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24081
563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.24081563
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.3764030727
Short name T2140
Test name
Test status
Simulation time 3869783815 ps
CPU time 26.8 seconds
Started Jul 23 06:39:46 PM PDT 24
Finished Jul 23 06:40:14 PM PDT 24
Peak memory 206964 kb
Host smart-5890b214-ebd7-4f89-84a9-7a9d82e08ec9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3764030727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.3764030727
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.1715012238
Short name T1788
Test name
Test status
Simulation time 183550370 ps
CPU time 0.83 seconds
Started Jul 23 06:39:47 PM PDT 24
Finished Jul 23 06:39:50 PM PDT 24
Peak memory 206752 kb
Host smart-a43dc760-33ed-4a72-9034-5f00c2744a60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17150
12238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.1715012238
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.4090383518
Short name T886
Test name
Test status
Simulation time 173149902 ps
CPU time 0.84 seconds
Started Jul 23 06:39:47 PM PDT 24
Finished Jul 23 06:39:50 PM PDT 24
Peak memory 206780 kb
Host smart-95071e58-372f-4d49-a532-18919d4001ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40903
83518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.4090383518
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.2893895609
Short name T2115
Test name
Test status
Simulation time 499710834 ps
CPU time 1.49 seconds
Started Jul 23 06:39:50 PM PDT 24
Finished Jul 23 06:39:53 PM PDT 24
Peak memory 206764 kb
Host smart-5c062d2d-0d5a-4ae3-a698-78cc47480492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28938
95609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.2893895609
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.3703868259
Short name T1063
Test name
Test status
Simulation time 3421391421 ps
CPU time 23.07 seconds
Started Jul 23 06:39:47 PM PDT 24
Finished Jul 23 06:40:12 PM PDT 24
Peak memory 206896 kb
Host smart-99a5bd68-a07d-4958-ab88-1d25a11d5b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37038
68259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.3703868259
Directory /workspace/9.usbdev_streaming_out/latest
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