Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	167106	1		T1	2		T2	4		T3	4
all_values[1]	167106	1		T1	2		T2	4		T3	4
all_values[2]	167106	1		T1	2		T2	4		T3	4
all_values[3]	167106	1		T1	2		T2	4		T3	4
all_values[4]	167106	1		T1	2		T2	4		T3	4
all_values[5]	167106	1		T1	2		T2	4		T3	4
all_values[6]	167106	1		T1	2		T2	4		T3	4
all_values[7]	167106	1		T1	2		T2	4		T3	4
all_values[8]	167106	1		T1	2		T2	4		T3	4
all_values[9]	167106	1		T1	2		T2	4		T3	4
all_values[10]	167106	1		T1	2		T2	4		T3	4
all_values[11]	167106	1		T1	2		T2	4		T3	4
all_values[12]	167106	1		T1	2		T2	4		T3	4
all_values[13]	167106	1		T1	2		T2	4		T3	4
all_values[14]	167106	1		T1	2		T2	4		T3	4
all_values[15]	167106	1		T1	2		T2	4		T3	4
all_values[16]	167106	1		T1	2		T2	4		T3	4
all_values[17]	167106	1		T1	2		T2	4		T3	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3001159	1		T1	36		T2	70		T3	70
auto[1]	6749	1		T2	2		T3	2		T17	2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3003189	1		T1	36		T2	72		T3	72
auto[1]	4719	1		T192	75		T195	78		T193	76

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	166148	1		T1	2		T2	4		T3	4
all_values[0]	auto[0]	auto[1]	131	1		T192	1		T196	6		T194	4
all_values[0]	auto[1]	auto[0]	701	1		T40	3		T41	3		T42	4
all_values[0]	auto[1]	auto[1]	126	1		T192	3		T195	5		T193	4
all_values[1]	auto[0]	auto[0]	165314	1		T1	2		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	160	1		T192	4		T195	4		T193	1
all_values[1]	auto[1]	auto[0]	1522	1		T2	2		T3	2		T18	2
all_values[1]	auto[1]	auto[1]	110	1		T192	1		T195	1		T193	4
all_values[2]	auto[0]	auto[0]	166713	1		T1	2		T2	4		T3	4
all_values[2]	auto[0]	auto[1]	135	1		T192	3		T195	4		T193	2
all_values[2]	auto[1]	auto[0]	131	1		T17	2		T34	2		T35	2
all_values[2]	auto[1]	auto[1]	127	1		T192	1		T195	1		T193	3
all_values[3]	auto[0]	auto[0]	165324	1		T1	2		T2	4		T3	4
all_values[3]	auto[0]	auto[1]	117	1		T192	1		T195	1		T196	6
all_values[3]	auto[1]	auto[0]	1504	1		T57	1485		T195	1		T275	4
all_values[3]	auto[1]	auto[1]	161	1		T192	4		T195	3		T193	4
all_values[4]	auto[0]	auto[0]	166834	1		T1	2		T2	4		T3	4
all_values[4]	auto[0]	auto[1]	121	1		T195	3		T193	1		T196	5
all_values[4]	auto[1]	auto[0]	29	1		T58	2		T196	1		T276	2
all_values[4]	auto[1]	auto[1]	122	1		T195	1		T193	3		T196	2
all_values[5]	auto[0]	auto[0]	166822	1		T1	2		T2	4		T3	4
all_values[5]	auto[0]	auto[1]	131	1		T192	1		T195	2		T196	6
all_values[5]	auto[1]	auto[0]	19	1		T271	1		T274	2		T277	1
all_values[5]	auto[1]	auto[1]	134	1		T192	4		T195	3		T196	2
all_values[6]	auto[0]	auto[0]	166815	1		T1	2		T2	4		T3	4
all_values[6]	auto[0]	auto[1]	143	1		T192	2		T195	3		T196	5
all_values[6]	auto[1]	auto[0]	22	1		T193	1		T194	2		T275	2
all_values[6]	auto[1]	auto[1]	126	1		T192	3		T195	2		T193	3
all_values[7]	auto[0]	auto[0]	166813	1		T1	2		T2	4		T3	4
all_values[7]	auto[0]	auto[1]	146	1		T192	1		T195	1		T193	4
all_values[7]	auto[1]	auto[0]	36	1		T43	2		T44	2		T45	2
all_values[7]	auto[1]	auto[1]	111	1		T192	3		T195	4		T193	1
all_values[8]	auto[0]	auto[0]	166801	1		T1	2		T2	4		T3	4
all_values[8]	auto[0]	auto[1]	100	1		T192	3		T195	1		T193	5
all_values[8]	auto[1]	auto[0]	37	1		T48	11		T276	3		T278	2
all_values[8]	auto[1]	auto[1]	168	1		T192	2		T195	4		T196	5
all_values[9]	auto[0]	auto[0]	166795	1		T1	2		T2	4		T3	4
all_values[9]	auto[0]	auto[1]	121	1		T195	2		T193	3		T196	3
all_values[9]	auto[1]	auto[0]	56	1		T39	5		T55	5		T56	5
all_values[9]	auto[1]	auto[1]	134	1		T192	4		T195	3		T193	1
all_values[10]	auto[0]	auto[0]	166815	1		T1	2		T2	4		T3	4
all_values[10]	auto[0]	auto[1]	151	1		T192	3		T195	5		T193	4
all_values[10]	auto[1]	auto[0]	18	1		T279	1		T272	1		T280	2
all_values[10]	auto[1]	auto[1]	122	1		T192	2		T193	1		T196	3
all_values[11]	auto[0]	auto[0]	166726	1		T1	2		T2	4		T3	4
all_values[11]	auto[0]	auto[1]	110	1		T196	2		T276	1		T279	3
all_values[11]	auto[1]	auto[0]	131	1		T38	2		T63	2		T64	2
all_values[11]	auto[1]	auto[1]	139	1		T192	4		T195	3		T193	5
all_values[12]	auto[0]	auto[0]	166796	1		T1	2		T2	4		T3	4
all_values[12]	auto[0]	auto[1]	155	1		T192	1		T195	1		T193	5
all_values[12]	auto[1]	auto[0]	44	1		T68	3		T69	3		T70	3
all_values[12]	auto[1]	auto[1]	111	1		T192	4		T195	3		T196	2
all_values[13]	auto[0]	auto[0]	166822	1		T1	2		T2	4		T3	4
all_values[13]	auto[0]	auto[1]	137	1		T192	1		T195	4		T193	4
all_values[13]	auto[1]	auto[0]	19	1		T196	1		T271	1		T272	1
all_values[13]	auto[1]	auto[1]	128	1		T192	4		T196	1		T194	4
all_values[14]	auto[0]	auto[0]	166825	1		T1	2		T2	4		T3	4
all_values[14]	auto[0]	auto[1]	115	1		T195	2		T193	3		T194	1
all_values[14]	auto[1]	auto[0]	28	1		T192	1		T196	1		T279	2
all_values[14]	auto[1]	auto[1]	138	1		T195	3		T193	2		T196	3
all_values[15]	auto[0]	auto[0]	166822	1		T1	2		T2	4		T3	4
all_values[15]	auto[0]	auto[1]	125	1		T192	1		T193	4		T194	1
all_values[15]	auto[1]	auto[0]	30	1		T195	3		T196	2		T276	2
all_values[15]	auto[1]	auto[1]	129	1		T192	4		T193	1		T194	4
all_values[16]	auto[0]	auto[0]	166803	1		T1	2		T2	4		T3	4
all_values[16]	auto[0]	auto[1]	122	1		T192	3		T196	8		T276	4
all_values[16]	auto[1]	auto[0]	50	1		T60	8		T61	8		T62	8
all_values[16]	auto[1]	auto[1]	131	1		T192	2		T195	4		T193	4
all_values[17]	auto[0]	auto[0]	166811	1		T1	2		T2	4		T3	4
all_values[17]	auto[0]	auto[1]	140	1		T192	1		T195	2		T193	4
all_values[17]	auto[1]	auto[0]	13	1		T50	2		T276	2		T281	1
all_values[17]	auto[1]	auto[1]	142	1		T192	4		T195	3		T196	6