Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	167106	1		T1	2		T2	4		T3	4
all_pins[1]	167106	1		T1	2		T2	4		T3	4
all_pins[2]	167106	1		T1	2		T2	4		T3	4
all_pins[3]	167106	1		T1	2		T2	4		T3	4
all_pins[4]	167106	1		T1	2		T2	4		T3	4
all_pins[5]	167106	1		T1	2		T2	4		T3	4
all_pins[6]	167106	1		T1	2		T2	4		T3	4
all_pins[7]	167106	1		T1	2		T2	4		T3	4
all_pins[8]	167106	1		T1	2		T2	4		T3	4
all_pins[9]	167106	1		T1	2		T2	4		T3	4
all_pins[10]	167106	1		T1	2		T2	4		T3	4
all_pins[11]	167106	1		T1	2		T2	4		T3	4
all_pins[12]	167106	1		T1	2		T2	4		T3	4
all_pins[13]	167106	1		T1	2		T2	4		T3	4
all_pins[14]	167106	1		T1	2		T2	4		T3	4
all_pins[15]	167106	1		T1	2		T2	4		T3	4
all_pins[16]	167106	1		T1	2		T2	4		T3	4
all_pins[17]	167106	1		T1	2		T2	4		T3	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	3005635	1		T1	36		T2	71		T3	71
values[0x1]	2273	1		T2	1		T3	1		T17	1
transitions[0x0=>0x1]	1976	1		T2	1		T3	1		T17	1
transitions[0x1=>0x0]	1986	1		T2	1		T3	1		T17	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	167002	1		T1	2		T2	4		T3	4
all_pins[0]	values[0x1]	104	1		T42	1		T282	1		T234	1
all_pins[0]	transitions[0x0=>0x1]	88	1		T42	1		T282	1		T234	1
all_pins[0]	transitions[0x1=>0x0]	985	1		T2	1		T3	1		T18	1
all_pins[1]	values[0x0]	166105	1		T1	2		T2	3		T3	3
all_pins[1]	values[0x1]	1001	1		T2	1		T3	1		T18	1
all_pins[1]	transitions[0x0=>0x1]	979	1		T2	1		T3	1		T18	1
all_pins[1]	transitions[0x1=>0x0]	114	1		T17	1		T34	1		T35	1
all_pins[2]	values[0x0]	166970	1		T1	2		T2	4		T3	4
all_pins[2]	values[0x1]	136	1		T17	1		T34	1		T35	1
all_pins[2]	transitions[0x0=>0x1]	108	1		T17	1		T34	1		T35	1
all_pins[2]	transitions[0x1=>0x0]	53	1		T57	1		T192	1		T193	1
all_pins[3]	values[0x0]	167025	1		T1	2		T2	4		T3	4
all_pins[3]	values[0x1]	81	1		T57	1		T192	1		T193	3
all_pins[3]	transitions[0x0=>0x1]	60	1		T57	1		T192	1		T193	3
all_pins[3]	transitions[0x1=>0x0]	45	1		T58	1		T195	1		T196	1
all_pins[4]	values[0x0]	167040	1		T1	2		T2	4		T3	4
all_pins[4]	values[0x1]	66	1		T58	1		T195	1		T196	1
all_pins[4]	transitions[0x0=>0x1]	50	1		T58	1		T195	1		T196	1
all_pins[4]	transitions[0x1=>0x0]	41	1		T192	1		T194	1		T276	1
all_pins[5]	values[0x0]	167049	1		T1	2		T2	4		T3	4
all_pins[5]	values[0x1]	57	1		T192	1		T194	1		T276	1
all_pins[5]	transitions[0x0=>0x1]	46	1		T192	1		T194	1		T279	3
all_pins[5]	transitions[0x1=>0x0]	45	1		T195	1		T193	2		T196	3
all_pins[6]	values[0x0]	167050	1		T1	2		T2	4		T3	4
all_pins[6]	values[0x1]	56	1		T195	1		T193	2		T196	3
all_pins[6]	transitions[0x0=>0x1]	51	1		T195	1		T193	2		T196	2
all_pins[6]	transitions[0x1=>0x0]	46	1		T43	1		T44	1		T45	1
all_pins[7]	values[0x0]	167055	1		T1	2		T2	4		T3	4
all_pins[7]	values[0x1]	51	1		T43	1		T44	1		T45	1
all_pins[7]	transitions[0x0=>0x1]	37	1		T43	1		T44	1		T45	1
all_pins[7]	transitions[0x1=>0x0]	51	1		T48	1		T192	2		T196	1
all_pins[8]	values[0x0]	167041	1		T1	2		T2	4		T3	4
all_pins[8]	values[0x1]	65	1		T48	1		T192	2		T195	1
all_pins[8]	transitions[0x0=>0x1]	48	1		T48	1		T192	1		T195	1
all_pins[8]	transitions[0x1=>0x0]	63	1		T39	2		T55	2		T56	2
all_pins[9]	values[0x0]	167026	1		T1	2		T2	4		T3	4
all_pins[9]	values[0x1]	80	1		T39	2		T55	2		T56	2
all_pins[9]	transitions[0x0=>0x1]	65	1		T39	2		T55	2		T56	2
all_pins[9]	transitions[0x1=>0x0]	52	1		T192	1		T193	1		T196	3
all_pins[10]	values[0x0]	167039	1		T1	2		T2	4		T3	4
all_pins[10]	values[0x1]	67	1		T192	2		T193	1		T196	3
all_pins[10]	transitions[0x0=>0x1]	44	1		T192	2		T196	2		T194	2
all_pins[10]	transitions[0x1=>0x0]	103	1		T38	1		T63	1		T64	1
all_pins[11]	values[0x0]	166980	1		T1	2		T2	4		T3	4
all_pins[11]	values[0x1]	126	1		T38	1		T63	1		T64	1
all_pins[11]	transitions[0x0=>0x1]	112	1		T38	1		T63	1		T64	1
all_pins[11]	transitions[0x1=>0x0]	39	1		T68	1		T69	1		T70	1
all_pins[12]	values[0x0]	167053	1		T1	2		T2	4		T3	4
all_pins[12]	values[0x1]	53	1		T68	1		T69	1		T70	1
all_pins[12]	transitions[0x0=>0x1]	41	1		T68	1		T69	1		T70	1
all_pins[12]	transitions[0x1=>0x0]	53	1		T192	1		T196	1		T279	1
all_pins[13]	values[0x0]	167041	1		T1	2		T2	4		T3	4
all_pins[13]	values[0x1]	65	1		T192	1		T196	1		T194	3
all_pins[13]	transitions[0x0=>0x1]	46	1		T192	1		T196	1		T194	3
all_pins[13]	transitions[0x1=>0x0]	54	1		T195	2		T193	2		T196	2
all_pins[14]	values[0x0]	167033	1		T1	2		T2	4		T3	4
all_pins[14]	values[0x1]	73	1		T195	2		T193	2		T196	2
all_pins[14]	transitions[0x0=>0x1]	50	1		T195	2		T193	1		T196	2
all_pins[14]	transitions[0x1=>0x0]	43	1		T192	3		T194	1		T276	1
all_pins[15]	values[0x0]	167040	1		T1	2		T2	4		T3	4
all_pins[15]	values[0x1]	66	1		T192	3		T193	1		T194	1
all_pins[15]	transitions[0x0=>0x1]	58	1		T192	2		T193	1		T194	1
all_pins[15]	transitions[0x1=>0x0]	66	1		T60	4		T61	4		T62	4
all_pins[16]	values[0x0]	167032	1		T1	2		T2	4		T3	4
all_pins[16]	values[0x1]	74	1		T60	4		T61	4		T62	4
all_pins[16]	transitions[0x0=>0x1]	63	1		T60	4		T61	4		T62	4
all_pins[16]	transitions[0x1=>0x0]	41	1		T50	1		T196	1		T194	2
all_pins[17]	values[0x0]	167054	1		T1	2		T2	4		T3	4
all_pins[17]	values[0x1]	52	1		T50	1		T196	1		T194	2
all_pins[17]	transitions[0x0=>0x1]	30	1		T50	1		T196	1		T194	1
all_pins[17]	transitions[0x1=>0x0]	92	1		T42	1		T282	1		T234	1