Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	263	1		T192	4		T195	4		T193	4
all_values[1]	263	1		T192	4		T195	4		T193	4
all_values[2]	263	1		T192	4		T195	4		T193	4
all_values[3]	263	1		T192	4		T195	4		T193	4
all_values[4]	263	1		T192	4		T195	4		T193	4
all_values[5]	263	1		T192	4		T195	4		T193	4
all_values[6]	263	1		T192	4		T195	4		T193	4
all_values[7]	263	1		T192	4		T195	4		T193	4
all_values[8]	263	1		T192	4		T195	4		T193	4
all_values[9]	263	1		T192	4		T195	4		T193	4
all_values[10]	263	1		T192	4		T195	4		T193	4
all_values[11]	263	1		T192	4		T195	4		T193	4
all_values[12]	263	1		T192	4		T195	4		T193	4
all_values[13]	263	1		T192	4		T195	4		T193	4
all_values[14]	263	1		T192	4		T195	4		T193	4
all_values[15]	263	1		T192	4		T195	4		T193	4
all_values[16]	263	1		T192	4		T195	4		T193	4
all_values[17]	263	1		T192	4		T195	4		T193	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2577	1		T192	39		T195	36		T193	43
auto[1]	2157	1		T192	33		T195	36		T193	29

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	855	1		T192	13		T195	11		T193	13
auto[1]	3879	1		T192	59		T195	61		T193	59

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2814	1		T192	48		T195	40		T193	44
auto[1]	1920	1		T192	24		T195	32		T193	28

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	32	1		T192	1		T279	1		T275	1
all_values[0]	auto[0]	auto[0]	auto[1]	54	1		T192	1		T196	4		T194	1
all_values[0]	auto[0]	auto[1]	auto[0]	20	1		T193	1		T281	3		T283	2
all_values[0]	auto[0]	auto[1]	auto[1]	54	1		T192	1		T195	2		T193	2
all_values[0]	auto[1]	auto[0]	auto[1]	54	1		T192	1		T196	2		T194	1
all_values[0]	auto[1]	auto[1]	auto[1]	49	1		T195	2		T193	1		T196	1
all_values[1]	auto[0]	auto[0]	auto[0]	24	1		T196	1		T276	2		T279	4
all_values[1]	auto[0]	auto[0]	auto[1]	66	1		T192	1		T195	2		T196	2
all_values[1]	auto[0]	auto[1]	auto[0]	17	1		T194	1		T279	1		T273	2
all_values[1]	auto[0]	auto[1]	auto[1]	44	1		T192	1		T193	2		T196	1
all_values[1]	auto[1]	auto[0]	auto[1]	71	1		T192	1		T195	2		T193	1
all_values[1]	auto[1]	auto[1]	auto[1]	41	1		T192	1		T193	1		T196	1
all_values[2]	auto[0]	auto[0]	auto[0]	26	1		T192	1		T196	5		T276	1
all_values[2]	auto[0]	auto[0]	auto[1]	49	1		T192	1		T195	1		T193	1
all_values[2]	auto[0]	auto[1]	auto[0]	22	1		T196	2		T194	1		T276	2
all_values[2]	auto[0]	auto[1]	auto[1]	54	1		T193	1		T194	1		T276	2
all_values[2]	auto[1]	auto[0]	auto[1]	56	1		T195	3		T193	2		T279	1
all_values[2]	auto[1]	auto[1]	auto[1]	56	1		T192	2		T194	1		T276	2
all_values[3]	auto[0]	auto[0]	auto[0]	17	1		T193	1		T275	1		T271	1
all_values[3]	auto[0]	auto[0]	auto[1]	52	1		T196	2		T194	2		T276	1
all_values[3]	auto[0]	auto[1]	auto[0]	16	1		T195	1		T275	3		T273	2
all_values[3]	auto[0]	auto[1]	auto[1]	68	1		T192	3		T195	2		T193	2
all_values[3]	auto[1]	auto[0]	auto[1]	50	1		T192	1		T196	2		T194	1
all_values[3]	auto[1]	auto[1]	auto[1]	60	1		T195	1		T193	1		T196	1
all_values[4]	auto[0]	auto[0]	auto[0]	47	1		T192	4		T195	1		T193	1
all_values[4]	auto[0]	auto[0]	auto[1]	47	1		T195	1		T193	1		T196	3
all_values[4]	auto[0]	auto[1]	auto[0]	17	1		T276	2		T281	1		T271	1
all_values[4]	auto[0]	auto[1]	auto[1]	46	1		T193	1		T196	1		T194	1
all_values[4]	auto[1]	auto[0]	auto[1]	54	1		T195	2		T193	1		T196	1
all_values[4]	auto[1]	auto[1]	auto[1]	52	1		T196	1		T276	1		T279	2
all_values[5]	auto[0]	auto[0]	auto[0]	31	1		T193	4		T271	1		T272	4
all_values[5]	auto[0]	auto[0]	auto[1]	53	1		T192	2		T196	3		T194	2
all_values[5]	auto[0]	auto[1]	auto[0]	14	1		T271	1		T274	3		T277	1
all_values[5]	auto[0]	auto[1]	auto[1]	54	1		T192	1		T195	1		T196	1
all_values[5]	auto[1]	auto[0]	auto[1]	56	1		T192	1		T195	2		T196	3
all_values[5]	auto[1]	auto[1]	auto[1]	55	1		T195	1		T194	1		T276	1
all_values[6]	auto[0]	auto[0]	auto[0]	23	1		T193	1		T194	1		T275	3
all_values[6]	auto[0]	auto[0]	auto[1]	57	1		T192	2		T195	2		T196	3
all_values[6]	auto[0]	auto[1]	auto[0]	18	1		T193	1		T194	3		T275	1
all_values[6]	auto[0]	auto[1]	auto[1]	54	1		T192	1		T193	1		T276	1
all_values[6]	auto[1]	auto[0]	auto[1]	72	1		T192	1		T193	1		T196	2
all_values[6]	auto[1]	auto[1]	auto[1]	39	1		T195	2		T196	2		T276	1
all_values[7]	auto[0]	auto[0]	auto[0]	34	1		T192	1		T283	2		T272	2
all_values[7]	auto[0]	auto[0]	auto[1]	62	1		T193	1		T196	1		T194	3
all_values[7]	auto[0]	auto[1]	auto[0]	17	1		T283	5		T272	2		T284	2
all_values[7]	auto[0]	auto[1]	auto[1]	46	1		T192	1		T195	3		T196	3
all_values[7]	auto[1]	auto[0]	auto[1]	69	1		T192	2		T193	2		T196	2
all_values[7]	auto[1]	auto[1]	auto[1]	35	1		T195	1		T193	1		T196	1
all_values[8]	auto[0]	auto[0]	auto[0]	23	1		T196	1		T194	1		T276	2
all_values[8]	auto[0]	auto[0]	auto[1]	43	1		T192	1		T193	2		T196	1
all_values[8]	auto[0]	auto[1]	auto[0]	19	1		T276	3		T278	2		T285	4
all_values[8]	auto[0]	auto[1]	auto[1]	67	1		T195	2		T196	2		T194	1
all_values[8]	auto[1]	auto[0]	auto[1]	58	1		T192	1		T193	2		T196	1
all_values[8]	auto[1]	auto[1]	auto[1]	53	1		T192	2		T195	2		T196	2
all_values[9]	auto[0]	auto[0]	auto[0]	30	1		T192	1		T193	1		T196	3
all_values[9]	auto[0]	auto[0]	auto[1]	49	1		T193	1		T196	2		T276	4
all_values[9]	auto[0]	auto[1]	auto[0]	22	1		T271	1		T272	1		T273	1
all_values[9]	auto[0]	auto[1]	auto[1]	60	1		T192	1		T195	1		T194	2
all_values[9]	auto[1]	auto[0]	auto[1]	48	1		T195	2		T196	1		T276	2
all_values[9]	auto[1]	auto[1]	auto[1]	54	1		T192	2		T195	1		T193	2
all_values[10]	auto[0]	auto[0]	auto[0]	26	1		T279	1		T275	1		T281	1
all_values[10]	auto[0]	auto[0]	auto[1]	74	1		T192	1		T195	1		T193	3
all_values[10]	auto[0]	auto[1]	auto[0]	13	1		T279	1		T280	1		T278	2
all_values[10]	auto[0]	auto[1]	auto[1]	44	1		T192	1		T196	3		T194	1
all_values[10]	auto[1]	auto[0]	auto[1]	62	1		T192	1		T195	3		T196	2
all_values[10]	auto[1]	auto[1]	auto[1]	44	1		T192	1		T193	1		T196	1
all_values[11]	auto[0]	auto[0]	auto[0]	35	1		T192	1		T195	2		T194	2
all_values[11]	auto[0]	auto[0]	auto[1]	52	1		T196	1		T276	1		T279	1
all_values[11]	auto[0]	auto[1]	auto[0]	23	1		T194	2		T279	1		T273	4
all_values[11]	auto[0]	auto[1]	auto[1]	60	1		T192	2		T195	1		T193	3
all_values[11]	auto[1]	auto[0]	auto[1]	47	1		T196	1		T279	1		T281	1
all_values[11]	auto[1]	auto[1]	auto[1]	46	1		T192	1		T195	1		T193	1
all_values[12]	auto[0]	auto[0]	auto[0]	24	1		T195	1		T196	1		T276	1
all_values[12]	auto[0]	auto[0]	auto[1]	61	1		T192	2		T193	1		T196	4
all_values[12]	auto[0]	auto[1]	auto[0]	21	1		T275	2		T273	5		T286	1
all_values[12]	auto[0]	auto[1]	auto[1]	47	1		T192	1		T195	2		T196	1
all_values[12]	auto[1]	auto[0]	auto[1]	69	1		T192	1		T195	1		T193	3
all_values[12]	auto[1]	auto[1]	auto[1]	41	1		T196	1		T194	2		T276	3
all_values[13]	auto[0]	auto[0]	auto[0]	34	1		T195	1		T193	1		T196	2
all_values[13]	auto[0]	auto[0]	auto[1]	64	1		T195	2		T193	2		T196	2
all_values[13]	auto[0]	auto[1]	auto[0]	13	1		T196	1		T271	1		T272	1
all_values[13]	auto[0]	auto[1]	auto[1]	45	1		T192	2		T194	1		T279	1
all_values[13]	auto[1]	auto[0]	auto[1]	62	1		T192	1		T195	1		T193	1
all_values[13]	auto[1]	auto[1]	auto[1]	45	1		T192	1		T194	1		T276	2
all_values[14]	auto[0]	auto[0]	auto[0]	37	1		T192	2		T196	5		T279	3
all_values[14]	auto[0]	auto[0]	auto[1]	44	1		T195	1		T193	1		T276	2
all_values[14]	auto[0]	auto[1]	auto[0]	18	1		T192	2		T279	2		T271	1
all_values[14]	auto[0]	auto[1]	auto[1]	57	1		T195	1		T193	2		T196	1
all_values[14]	auto[1]	auto[0]	auto[1]	59	1		T195	1		T194	1		T276	3
all_values[14]	auto[1]	auto[1]	auto[1]	48	1		T195	1		T193	1		T196	1
all_values[15]	auto[0]	auto[0]	auto[0]	32	1		T195	2		T196	6		T276	1
all_values[15]	auto[0]	auto[0]	auto[1]	56	1		T192	2		T193	2		T276	1
all_values[15]	auto[0]	auto[1]	auto[0]	23	1		T195	2		T196	1		T276	2
all_values[15]	auto[0]	auto[1]	auto[1]	50	1		T192	1		T194	1		T279	1
all_values[15]	auto[1]	auto[0]	auto[1]	56	1		T192	1		T193	1		T194	2
all_values[15]	auto[1]	auto[1]	auto[1]	46	1		T193	1		T194	1		T276	1
all_values[16]	auto[0]	auto[0]	auto[0]	32	1		T193	1		T194	2		T281	2
all_values[16]	auto[0]	auto[0]	auto[1]	48	1		T192	1		T196	4		T276	2
all_values[16]	auto[0]	auto[1]	auto[0]	24	1		T195	1		T194	2		T271	1
all_values[16]	auto[0]	auto[1]	auto[1]	56	1		T192	2		T195	1		T193	1
all_values[16]	auto[1]	auto[0]	auto[1]	54	1		T192	1		T196	3		T276	1
all_values[16]	auto[1]	auto[1]	auto[1]	49	1		T195	2		T193	2		T276	1
all_values[17]	auto[0]	auto[0]	auto[0]	22	1		T193	1		T276	3		T287	1
all_values[17]	auto[0]	auto[0]	auto[1]	50	1		T195	1		T193	1		T276	1
all_values[17]	auto[0]	auto[1]	auto[0]	9	1		T276	1		T281	1		T283	3
all_values[17]	auto[0]	auto[1]	auto[1]	72	1		T192	3		T195	2		T196	4
all_values[17]	auto[1]	auto[0]	auto[1]	70	1		T192	1		T195	1		T193	2
all_values[17]	auto[1]	auto[1]	auto[1]	40	1		T196	2		T194	1		T276	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal