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 LINE       9288
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T32,T78
1	1	0	Covered	T187,T213,T216
1	1	1	Covered	T51,T52,T98

 LINE       9293
 EXPRESSION (addr_hit[33] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T22
1	1	0	Not Covered
1	1	1	Covered	T22,T25,T23

 LINE       9294
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T19,T4,T32
1	1	0	Covered	T213,T216,T221
1	1	1	Covered	T22,T25,T23

 LINE       9313
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T187,T213,T214
1	1	1	Covered	T1,T2,T3

 LINE       9326
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T213,T214,T216
1	1	1	Covered	T2,T3,T6

 LINE       9329
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T4,T32
1	1	0	Covered	T187,T213,T214
1	1	1	Covered	T1,T32,T85

 LINE       9336
 EXPRESSION (addr_hit[39] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T32
1	1	0	Not Covered
1	1	1	Covered	T185,T186,T209

 LINE       9337
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T32
1	1	0	Covered	T187,T213,T214
1	1	1	Covered	T185,T186,T209

 LINE       9350
 EXPRESSION (addr_hit[40] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T32
1	1	0	Not Covered
1	1	1	Covered	T185,T186,T209

 LINE       9351
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T32
1	1	0	Covered	T187,T213,T219
1	1	1	Covered	T185,T186,T209

 LINE       9362
 EXPRESSION (addr_hit[41] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T32,T78
1	1	0	Not Covered
1	1	1	Covered	T185,T186,T209

 LINE       9363
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T32,T78
1	1	0	Covered	T187,T214,T217
1	1	1	Covered	T185,T186,T209

 LINE       9368
 EXPRESSION (addr_hit[42] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T32
1	1	0	Not Covered
1	1	1	Covered	T185,T186,T209

 LINE       9369
 EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T32
1	1	0	Covered	T187,T217,T216
1	1	1	Covered	T185,T186,T209

 LINE       9881
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T2,T3,T6