Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.58 97.84 93.76 97.44 75.00 96.26 98.17 96.58


Total test records in report: 2857
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T253 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2895122480 Jul 24 05:09:31 PM PDT 24 Jul 24 05:09:32 PM PDT 24 55401477 ps
T219 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3403893642 Jul 24 05:09:27 PM PDT 24 Jul 24 05:09:30 PM PDT 24 118883899 ps
T269 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2245824001 Jul 24 05:09:24 PM PDT 24 Jul 24 05:09:25 PM PDT 24 206300452 ps
T2763 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.3613679734 Jul 24 05:09:28 PM PDT 24 Jul 24 05:09:29 PM PDT 24 50982793 ps
T2764 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3417700629 Jul 24 05:09:19 PM PDT 24 Jul 24 05:09:20 PM PDT 24 77388255 ps
T2765 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3918756557 Jul 24 05:09:11 PM PDT 24 Jul 24 05:09:13 PM PDT 24 100408222 ps
T2766 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.432163736 Jul 24 05:09:33 PM PDT 24 Jul 24 05:09:34 PM PDT 24 111251279 ps
T2767 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3912354381 Jul 24 05:09:29 PM PDT 24 Jul 24 05:09:30 PM PDT 24 44284327 ps
T2768 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1461723756 Jul 24 05:09:07 PM PDT 24 Jul 24 05:09:08 PM PDT 24 177746435 ps
T2769 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1798841543 Jul 24 05:09:18 PM PDT 24 Jul 24 05:09:21 PM PDT 24 105147549 ps
T2770 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.747819010 Jul 24 05:09:38 PM PDT 24 Jul 24 05:09:40 PM PDT 24 143227064 ps
T2771 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2659162106 Jul 24 05:09:24 PM PDT 24 Jul 24 05:09:25 PM PDT 24 61765347 ps
T293 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1481065858 Jul 24 05:09:25 PM PDT 24 Jul 24 05:09:28 PM PDT 24 919707876 ps
T2772 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.900878424 Jul 24 05:09:26 PM PDT 24 Jul 24 05:09:27 PM PDT 24 47089664 ps
T2773 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.4115734112 Jul 24 05:10:08 PM PDT 24 Jul 24 05:10:09 PM PDT 24 111293458 ps
T254 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.630560457 Jul 24 05:09:25 PM PDT 24 Jul 24 05:09:27 PM PDT 24 121084268 ps
T2774 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1908303176 Jul 24 05:09:31 PM PDT 24 Jul 24 05:09:37 PM PDT 24 75535872 ps
T2775 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3527391410 Jul 24 05:09:39 PM PDT 24 Jul 24 05:09:42 PM PDT 24 35600054 ps
T255 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3126636714 Jul 24 05:09:30 PM PDT 24 Jul 24 05:09:35 PM PDT 24 103169227 ps
T2776 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3816240225 Jul 24 05:09:38 PM PDT 24 Jul 24 05:09:40 PM PDT 24 155330290 ps
T2777 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3377664494 Jul 24 05:09:29 PM PDT 24 Jul 24 05:09:30 PM PDT 24 71339348 ps
T2778 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1014800233 Jul 24 05:09:32 PM PDT 24 Jul 24 05:09:35 PM PDT 24 85440202 ps
T2779 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3120617448 Jul 24 05:09:18 PM PDT 24 Jul 24 05:09:20 PM PDT 24 75494774 ps
T2780 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.655620975 Jul 24 05:09:11 PM PDT 24 Jul 24 05:09:12 PM PDT 24 129656589 ps
T2781 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.949887544 Jul 24 05:09:52 PM PDT 24 Jul 24 05:09:56 PM PDT 24 301034932 ps
T2782 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1792724866 Jul 24 05:09:42 PM PDT 24 Jul 24 05:09:45 PM PDT 24 494784625 ps
T2783 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2177976062 Jul 24 05:09:17 PM PDT 24 Jul 24 05:09:21 PM PDT 24 121095362 ps
T2784 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.1242286768 Jul 24 05:09:26 PM PDT 24 Jul 24 05:09:28 PM PDT 24 235131069 ps
T284 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2906776120 Jul 24 05:09:41 PM PDT 24 Jul 24 05:09:42 PM PDT 24 66142537 ps
T2785 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3363138068 Jul 24 05:09:17 PM PDT 24 Jul 24 05:09:19 PM PDT 24 178658897 ps
T2786 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.853239174 Jul 24 05:09:26 PM PDT 24 Jul 24 05:09:28 PM PDT 24 127766996 ps
T2787 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.538300584 Jul 24 05:09:14 PM PDT 24 Jul 24 05:09:19 PM PDT 24 1332994019 ps
T2788 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3763990483 Jul 24 05:09:25 PM PDT 24 Jul 24 05:09:26 PM PDT 24 60009163 ps
T2789 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2529471484 Jul 24 05:09:27 PM PDT 24 Jul 24 05:09:28 PM PDT 24 39592039 ps
T2790 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2677499648 Jul 24 05:09:22 PM PDT 24 Jul 24 05:09:24 PM PDT 24 218058401 ps
T2791 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.3299411681 Jul 24 05:09:25 PM PDT 24 Jul 24 05:09:26 PM PDT 24 51800016 ps
T2792 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.128359637 Jul 24 05:09:32 PM PDT 24 Jul 24 05:09:35 PM PDT 24 315112962 ps
T2793 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3374370061 Jul 24 05:09:37 PM PDT 24 Jul 24 05:09:38 PM PDT 24 36875730 ps
T290 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3707586038 Jul 24 05:09:37 PM PDT 24 Jul 24 05:09:41 PM PDT 24 593418841 ps
T2794 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1882703831 Jul 24 05:09:45 PM PDT 24 Jul 24 05:09:47 PM PDT 24 104927549 ps
T2795 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1679000947 Jul 24 05:09:45 PM PDT 24 Jul 24 05:09:46 PM PDT 24 84806685 ps
T2796 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1881118149 Jul 24 05:09:25 PM PDT 24 Jul 24 05:09:26 PM PDT 24 98307221 ps
T2797 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2634410808 Jul 24 05:09:28 PM PDT 24 Jul 24 05:09:31 PM PDT 24 181350777 ps
T2798 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.445539011 Jul 24 05:09:24 PM PDT 24 Jul 24 05:09:26 PM PDT 24 96942537 ps
T291 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3415503848 Jul 24 05:09:46 PM PDT 24 Jul 24 05:09:48 PM PDT 24 283780464 ps
T2799 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1451492623 Jul 24 05:09:34 PM PDT 24 Jul 24 05:09:37 PM PDT 24 483981226 ps
T2800 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1693597053 Jul 24 05:09:25 PM PDT 24 Jul 24 05:09:26 PM PDT 24 59993494 ps
T2801 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.3706257189 Jul 24 05:09:39 PM PDT 24 Jul 24 05:09:40 PM PDT 24 37209425 ps
T2802 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1862175020 Jul 24 05:09:22 PM PDT 24 Jul 24 05:09:23 PM PDT 24 118955080 ps
T2803 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3418127441 Jul 24 05:09:22 PM PDT 24 Jul 24 05:09:26 PM PDT 24 177197619 ps
T2804 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1141560196 Jul 24 05:09:28 PM PDT 24 Jul 24 05:09:30 PM PDT 24 119545061 ps
T2805 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.679487581 Jul 24 05:09:53 PM PDT 24 Jul 24 05:09:57 PM PDT 24 270450402 ps
T2806 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3081985009 Jul 24 05:09:18 PM PDT 24 Jul 24 05:09:24 PM PDT 24 81055698 ps
T2807 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1624675580 Jul 24 05:09:15 PM PDT 24 Jul 24 05:09:17 PM PDT 24 61292497 ps
T2808 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.4208480036 Jul 24 05:09:26 PM PDT 24 Jul 24 05:09:29 PM PDT 24 106060355 ps
T2809 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1594167997 Jul 24 05:09:25 PM PDT 24 Jul 24 05:09:27 PM PDT 24 90465573 ps
T2810 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.834369629 Jul 24 05:09:36 PM PDT 24 Jul 24 05:09:37 PM PDT 24 30870679 ps
T285 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2052197678 Jul 24 05:09:52 PM PDT 24 Jul 24 05:09:53 PM PDT 24 50049356 ps
T2811 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3545737616 Jul 24 05:09:28 PM PDT 24 Jul 24 05:09:30 PM PDT 24 279943684 ps
T2812 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3368722444 Jul 24 05:09:31 PM PDT 24 Jul 24 05:09:31 PM PDT 24 39935829 ps
T2813 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2958526170 Jul 24 05:09:36 PM PDT 24 Jul 24 05:09:37 PM PDT 24 66171826 ps
T2814 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2266303038 Jul 24 05:09:24 PM PDT 24 Jul 24 05:09:27 PM PDT 24 401949687 ps
T2815 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2291126447 Jul 24 05:09:30 PM PDT 24 Jul 24 05:09:31 PM PDT 24 119634880 ps
T2816 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3116198052 Jul 24 05:09:41 PM PDT 24 Jul 24 05:09:42 PM PDT 24 32391643 ps
T2817 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.573513181 Jul 24 05:09:10 PM PDT 24 Jul 24 05:09:11 PM PDT 24 96663000 ps
T2818 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1742390334 Jul 24 05:09:23 PM PDT 24 Jul 24 05:09:25 PM PDT 24 195683203 ps
T2819 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.1534597192 Jul 24 05:10:12 PM PDT 24 Jul 24 05:10:13 PM PDT 24 96163704 ps
T2820 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.469817205 Jul 24 05:09:46 PM PDT 24 Jul 24 05:09:46 PM PDT 24 41619567 ps
T2821 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3109377490 Jul 24 05:09:09 PM PDT 24 Jul 24 05:09:14 PM PDT 24 583487851 ps
T2822 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3608362729 Jul 24 05:09:34 PM PDT 24 Jul 24 05:09:35 PM PDT 24 48303024 ps
T2823 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2620643232 Jul 24 05:09:33 PM PDT 24 Jul 24 05:09:36 PM PDT 24 908737958 ps
T2824 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2157468551 Jul 24 05:09:30 PM PDT 24 Jul 24 05:09:33 PM PDT 24 116100790 ps
T2825 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3473302124 Jul 24 05:09:11 PM PDT 24 Jul 24 05:09:13 PM PDT 24 53939236 ps
T2826 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3383682494 Jul 24 05:09:25 PM PDT 24 Jul 24 05:09:28 PM PDT 24 400372470 ps
T2827 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.740936419 Jul 24 05:09:28 PM PDT 24 Jul 24 05:09:31 PM PDT 24 513336336 ps
T2828 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1093214078 Jul 24 05:09:12 PM PDT 24 Jul 24 05:09:19 PM PDT 24 900918372 ps
T2829 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1617099228 Jul 24 05:09:19 PM PDT 24 Jul 24 05:09:20 PM PDT 24 151841438 ps
T2830 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1134499698 Jul 24 05:09:38 PM PDT 24 Jul 24 05:09:39 PM PDT 24 53429407 ps
T2831 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.8866957 Jul 24 05:09:44 PM PDT 24 Jul 24 05:09:49 PM PDT 24 640295409 ps
T2832 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3475777820 Jul 24 05:09:27 PM PDT 24 Jul 24 05:09:28 PM PDT 24 40887813 ps
T2833 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3936605047 Jul 24 05:09:29 PM PDT 24 Jul 24 05:09:30 PM PDT 24 61808000 ps
T2834 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.241068301 Jul 24 05:09:25 PM PDT 24 Jul 24 05:09:27 PM PDT 24 149810343 ps
T2835 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.203028300 Jul 24 05:09:36 PM PDT 24 Jul 24 05:09:38 PM PDT 24 62576585 ps
T2836 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.735450163 Jul 24 05:09:39 PM PDT 24 Jul 24 05:09:43 PM PDT 24 379721724 ps
T2837 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.979834256 Jul 24 05:09:31 PM PDT 24 Jul 24 05:09:32 PM PDT 24 40363044 ps
T294 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2358854590 Jul 24 05:09:24 PM PDT 24 Jul 24 05:09:29 PM PDT 24 712057684 ps
T2838 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2729173675 Jul 24 05:09:29 PM PDT 24 Jul 24 05:09:31 PM PDT 24 271954761 ps
T2839 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1089599245 Jul 24 05:09:25 PM PDT 24 Jul 24 05:09:26 PM PDT 24 124342304 ps
T2840 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1284291428 Jul 24 05:10:00 PM PDT 24 Jul 24 05:10:03 PM PDT 24 92646756 ps
T2841 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3076568695 Jul 24 05:09:11 PM PDT 24 Jul 24 05:09:12 PM PDT 24 201063475 ps
T2842 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1635004612 Jul 24 05:09:28 PM PDT 24 Jul 24 05:09:35 PM PDT 24 525069820 ps
T2843 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.3455123101 Jul 24 05:09:30 PM PDT 24 Jul 24 05:09:31 PM PDT 24 49109017 ps
T2844 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.863797748 Jul 24 05:09:09 PM PDT 24 Jul 24 05:09:10 PM PDT 24 63221385 ps
T288 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.305910409 Jul 24 05:09:26 PM PDT 24 Jul 24 05:09:29 PM PDT 24 425790269 ps
T2845 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.249321189 Jul 24 05:09:27 PM PDT 24 Jul 24 05:09:28 PM PDT 24 36845112 ps
T2846 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.261038363 Jul 24 05:09:39 PM PDT 24 Jul 24 05:09:42 PM PDT 24 237354369 ps
T2847 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1699732998 Jul 24 05:09:26 PM PDT 24 Jul 24 05:09:27 PM PDT 24 55791161 ps
T2848 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3997252494 Jul 24 05:09:12 PM PDT 24 Jul 24 05:09:14 PM PDT 24 119871802 ps
T2849 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3316254944 Jul 24 05:09:18 PM PDT 24 Jul 24 05:09:20 PM PDT 24 162500701 ps
T2850 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.529754478 Jul 24 05:09:54 PM PDT 24 Jul 24 05:09:55 PM PDT 24 31802400 ps
T2851 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3888452380 Jul 24 05:09:36 PM PDT 24 Jul 24 05:09:37 PM PDT 24 42817239 ps
T2852 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.4136560537 Jul 24 05:09:26 PM PDT 24 Jul 24 05:09:28 PM PDT 24 134859351 ps
T2853 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3125186302 Jul 24 05:09:23 PM PDT 24 Jul 24 05:09:27 PM PDT 24 479400835 ps
T2854 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.4169291373 Jul 24 05:09:26 PM PDT 24 Jul 24 05:09:27 PM PDT 24 72516419 ps
T2855 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3973027501 Jul 24 05:09:37 PM PDT 24 Jul 24 05:09:38 PM PDT 24 49432160 ps
T2856 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2234315270 Jul 24 05:09:25 PM PDT 24 Jul 24 05:09:30 PM PDT 24 683820863 ps
T2857 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.426107022 Jul 24 05:09:40 PM PDT 24 Jul 24 05:09:49 PM PDT 24 1472929466 ps

Test location /workspace/coverage/default/29.usbdev_endpoint_access.3750329807
Short name T19
Test name
Test status
Simulation time 900534710 ps
CPU time 2.09 seconds
Started Jul 24 05:27:31 PM PDT 24
Finished Jul 24 05:27:33 PM PDT 24
Peak memory 206696 kb
Host smart-2bcf5749-1b3d-4a31-9a12-9dc1730727b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37503
29807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.3750329807
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3582073796
Short name T276
Test name
Test status
Simulation time 43328823 ps
CPU time 0.69 seconds
Started Jul 24 05:09:15 PM PDT 24
Finished Jul 24 05:09:16 PM PDT 24
Peak memory 206116 kb
Host smart-83dacedb-daad-46ef-80e3-a53be9977709
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3582073796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.3582073796
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.4054901556
Short name T2
Test name
Test status
Simulation time 3579799721 ps
CPU time 4.53 seconds
Started Jul 24 05:28:25 PM PDT 24
Finished Jul 24 05:28:29 PM PDT 24
Peak memory 206888 kb
Host smart-d1647ac3-492f-4508-909f-7cf531db8fc3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4054901556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.4054901556
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_device_address.1081256002
Short name T32
Test name
Test status
Simulation time 7217523579 ps
CPU time 12.79 seconds
Started Jul 24 05:27:19 PM PDT 24
Finished Jul 24 05:27:32 PM PDT 24
Peak memory 206784 kb
Host smart-48ea75c2-f25b-4ec8-bee2-7df780a2a896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10812
56002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.1081256002
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3983145243
Short name T185
Test name
Test status
Simulation time 620056546 ps
CPU time 2.9 seconds
Started Jul 24 05:09:30 PM PDT 24
Finished Jul 24 05:09:33 PM PDT 24
Peak memory 206536 kb
Host smart-1b62e561-3ecb-413a-a87c-db41d4cfb9cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3983145243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.3983145243
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.1132525123
Short name T91
Test name
Test status
Simulation time 189599256 ps
CPU time 0.86 seconds
Started Jul 24 05:24:02 PM PDT 24
Finished Jul 24 05:24:03 PM PDT 24
Peak memory 206560 kb
Host smart-704de83b-7673-48ab-a562-cb44b7217e59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11325
25123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.1132525123
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.403963756
Short name T7
Test name
Test status
Simulation time 13296634652 ps
CPU time 12.11 seconds
Started Jul 24 05:28:36 PM PDT 24
Finished Jul 24 05:28:48 PM PDT 24
Peak memory 206736 kb
Host smart-9a6642f9-6fdd-4416-a6b4-c4b2e95469bf
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=403963756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.403963756
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.459729706
Short name T279
Test name
Test status
Simulation time 42948045 ps
CPU time 0.67 seconds
Started Jul 24 05:09:32 PM PDT 24
Finished Jul 24 05:09:32 PM PDT 24
Peak memory 206328 kb
Host smart-917cc05a-74d7-4f1b-b03b-b7634433270b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=459729706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.459729706
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/default/14.usbdev_iso_retraction.4288396725
Short name T1
Test name
Test status
Simulation time 7606498833 ps
CPU time 29.14 seconds
Started Jul 24 05:25:59 PM PDT 24
Finished Jul 24 05:26:29 PM PDT 24
Peak memory 206988 kb
Host smart-6d7a141b-3831-4e3b-991d-9f973be461ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42883
96725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.4288396725
Directory /workspace/14.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.2596230509
Short name T17
Test name
Test status
Simulation time 160232124 ps
CPU time 0.78 seconds
Started Jul 24 05:26:31 PM PDT 24
Finished Jul 24 05:26:32 PM PDT 24
Peak memory 206576 kb
Host smart-09ecfb32-59e8-4ae8-804f-9531a6ba2a7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25962
30509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.2596230509
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.81797263
Short name T187
Test name
Test status
Simulation time 189237571 ps
CPU time 1.96 seconds
Started Jul 24 05:09:26 PM PDT 24
Finished Jul 24 05:09:28 PM PDT 24
Peak memory 222104 kb
Host smart-912dba3f-24e1-4f6f-86d0-f1e58c790dec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=81797263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.81797263
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.3775662491
Short name T182
Test name
Test status
Simulation time 522416650 ps
CPU time 1.38 seconds
Started Jul 24 05:24:19 PM PDT 24
Finished Jul 24 05:24:20 PM PDT 24
Peak memory 224316 kb
Host smart-86c85d30-40d8-4074-a63b-c3ad04db47ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3775662491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.3775662491
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.1616022325
Short name T320
Test name
Test status
Simulation time 229147145 ps
CPU time 0.82 seconds
Started Jul 24 05:24:40 PM PDT 24
Finished Jul 24 05:24:41 PM PDT 24
Peak memory 206576 kb
Host smart-3a0e2a7b-d321-4285-8be3-9353b1ae4bfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16160
22325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.1616022325
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.2382206288
Short name T106
Test name
Test status
Simulation time 413247972 ps
CPU time 1.33 seconds
Started Jul 24 05:26:20 PM PDT 24
Finished Jul 24 05:26:21 PM PDT 24
Peak memory 206576 kb
Host smart-f7bdeee4-92b6-4795-a027-8c45eb13459e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23822
06288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.2382206288
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.260863027
Short name T22
Test name
Test status
Simulation time 36615857 ps
CPU time 0.64 seconds
Started Jul 24 05:25:59 PM PDT 24
Finished Jul 24 05:26:00 PM PDT 24
Peak memory 206580 kb
Host smart-1d7a9a22-5d0d-4443-a7b4-f165a5050f0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26086
3027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.260863027
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.2520837301
Short name T63
Test name
Test status
Simulation time 158785227 ps
CPU time 0.8 seconds
Started Jul 24 05:24:54 PM PDT 24
Finished Jul 24 05:24:55 PM PDT 24
Peak memory 206776 kb
Host smart-501dc9ee-40fb-4295-9dc3-dc54b1fd42a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25208
37301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.2520837301
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.208929289
Short name T271
Test name
Test status
Simulation time 36283864 ps
CPU time 0.64 seconds
Started Jul 24 05:09:33 PM PDT 24
Finished Jul 24 05:09:34 PM PDT 24
Peak memory 206120 kb
Host smart-0e00f409-f3ac-4db2-9bb4-bb090ccf7715
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=208929289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.208929289
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.998212923
Short name T71
Test name
Test status
Simulation time 306091170 ps
CPU time 0.92 seconds
Started Jul 24 05:23:44 PM PDT 24
Finished Jul 24 05:23:45 PM PDT 24
Peak memory 206528 kb
Host smart-52954641-7560-4b13-bc70-b5c749c030ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99821
2923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.998212923
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.2874928961
Short name T36
Test name
Test status
Simulation time 22475977225 ps
CPU time 125.66 seconds
Started Jul 24 05:24:35 PM PDT 24
Finished Jul 24 05:26:41 PM PDT 24
Peak memory 206956 kb
Host smart-5adf67f3-98aa-434a-9ffa-18f7b79be90a
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2874928961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.2874928961
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.3998968462
Short name T37
Test name
Test status
Simulation time 20177163418 ps
CPU time 22.46 seconds
Started Jul 24 05:23:47 PM PDT 24
Finished Jul 24 05:24:10 PM PDT 24
Peak memory 206736 kb
Host smart-18495fce-685b-433b-a21d-261b3ab94b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39989
68462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.3998968462
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1250167089
Short name T283
Test name
Test status
Simulation time 40860026 ps
CPU time 0.68 seconds
Started Jul 24 05:09:26 PM PDT 24
Finished Jul 24 05:09:27 PM PDT 24
Peak memory 206072 kb
Host smart-317d3b61-b1e7-4b88-b61b-de7bc78c266d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1250167089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.1250167089
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2267756185
Short name T245
Test name
Test status
Simulation time 93337107 ps
CPU time 1.03 seconds
Started Jul 24 05:09:30 PM PDT 24
Finished Jul 24 05:09:32 PM PDT 24
Peak memory 206364 kb
Host smart-e34725aa-f8fa-459b-bcd5-805840ad98be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2267756185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.2267756185
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.3980218965
Short name T156
Test name
Test status
Simulation time 10080967688 ps
CPU time 55.14 seconds
Started Jul 24 05:24:00 PM PDT 24
Finished Jul 24 05:25:00 PM PDT 24
Peak memory 206820 kb
Host smart-b6b4e827-e0de-4fa2-8a18-12bb6605cb64
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3980218965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.3980218965
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.1254457055
Short name T101
Test name
Test status
Simulation time 1233717350 ps
CPU time 2.74 seconds
Started Jul 24 05:24:41 PM PDT 24
Finished Jul 24 05:24:44 PM PDT 24
Peak memory 206812 kb
Host smart-f4159bd3-cd02-42a8-96d5-384f98521d11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12544
57055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.1254457055
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.4117298038
Short name T42
Test name
Test status
Simulation time 185275726 ps
CPU time 0.79 seconds
Started Jul 24 05:25:27 PM PDT 24
Finished Jul 24 05:25:28 PM PDT 24
Peak memory 206548 kb
Host smart-ff50475c-8dea-4597-88df-087cedb97f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41172
98038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.4117298038
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.4209242930
Short name T289
Test name
Test status
Simulation time 803323093 ps
CPU time 4.43 seconds
Started Jul 24 05:09:28 PM PDT 24
Finished Jul 24 05:09:37 PM PDT 24
Peak memory 206372 kb
Host smart-6b7753e3-69f6-4583-a52f-1f97f1cef9d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4209242930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.4209242930
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3727112220
Short name T275
Test name
Test status
Simulation time 71774861 ps
CPU time 0.68 seconds
Started Jul 24 05:09:41 PM PDT 24
Finished Jul 24 05:09:42 PM PDT 24
Peak memory 206184 kb
Host smart-4e595cf5-0bfb-417f-b4d6-27973250e221
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3727112220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.3727112220
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.496368472
Short name T78
Test name
Test status
Simulation time 6875598286 ps
CPU time 184 seconds
Started Jul 24 05:29:52 PM PDT 24
Finished Jul 24 05:32:56 PM PDT 24
Peak memory 206956 kb
Host smart-9db1dd7b-664d-48fd-89b8-dce4c01ece2d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=496368472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.496368472
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.867934811
Short name T158
Test name
Test status
Simulation time 8280280894 ps
CPU time 219.83 seconds
Started Jul 24 05:23:42 PM PDT 24
Finished Jul 24 05:27:22 PM PDT 24
Peak memory 206940 kb
Host smart-348ef4f5-5202-4d43-bfdf-02663e1324a2
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=867934811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.867934811
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.370492212
Short name T39
Test name
Test status
Simulation time 142971423 ps
CPU time 0.73 seconds
Started Jul 24 05:23:39 PM PDT 24
Finished Jul 24 05:23:40 PM PDT 24
Peak memory 206604 kb
Host smart-bcc52a56-88b7-47cf-896e-a87d0ed019c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37049
2212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.370492212
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.170259944
Short name T53
Test name
Test status
Simulation time 145927065 ps
CPU time 0.8 seconds
Started Jul 24 05:25:28 PM PDT 24
Finished Jul 24 05:25:29 PM PDT 24
Peak memory 206584 kb
Host smart-d53478ba-c419-44fd-a13c-4145c856bb7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17025
9944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.170259944
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.83331460
Short name T62
Test name
Test status
Simulation time 516438141 ps
CPU time 1.43 seconds
Started Jul 24 05:23:41 PM PDT 24
Finished Jul 24 05:23:43 PM PDT 24
Peak memory 206576 kb
Host smart-bbe83dc3-382d-4db5-a068-3cb768d5fc72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83331
460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.83331460
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.305910409
Short name T288
Test name
Test status
Simulation time 425790269 ps
CPU time 2.45 seconds
Started Jul 24 05:09:26 PM PDT 24
Finished Jul 24 05:09:29 PM PDT 24
Peak memory 206484 kb
Host smart-5705c59f-3ca3-4a58-bf40-d13fd5e8b314
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=305910409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.305910409
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.3482896359
Short name T174
Test name
Test status
Simulation time 48133484 ps
CPU time 0.7 seconds
Started Jul 24 05:25:25 PM PDT 24
Finished Jul 24 05:25:26 PM PDT 24
Peak memory 206496 kb
Host smart-b335fb46-4b48-48f6-8b7c-cf9f543f5d7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3482896359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.3482896359
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1014800233
Short name T2778
Test name
Test status
Simulation time 85440202 ps
CPU time 2.38 seconds
Started Jul 24 05:09:32 PM PDT 24
Finished Jul 24 05:09:35 PM PDT 24
Peak memory 214716 kb
Host smart-7e1bad1d-05d1-48aa-8a79-7e7955750a6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1014800233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.1014800233
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.348115297
Short name T48
Test name
Test status
Simulation time 279949200 ps
CPU time 0.98 seconds
Started Jul 24 05:23:39 PM PDT 24
Finished Jul 24 05:23:41 PM PDT 24
Peak memory 206576 kb
Host smart-b45e31ad-777f-4d85-94c4-89ef8c9ee5c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34811
5297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.348115297
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2906776120
Short name T284
Test name
Test status
Simulation time 66142537 ps
CPU time 0.66 seconds
Started Jul 24 05:09:41 PM PDT 24
Finished Jul 24 05:09:42 PM PDT 24
Peak memory 206136 kb
Host smart-a8d5044a-7733-4e5d-a50c-5807cf60e509
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2906776120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.2906776120
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2694710119
Short name T292
Test name
Test status
Simulation time 776411884 ps
CPU time 4.58 seconds
Started Jul 24 05:09:35 PM PDT 24
Finished Jul 24 05:09:40 PM PDT 24
Peak memory 206508 kb
Host smart-781b117f-c29f-4b99-b2d4-05c2799fdca4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2694710119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.2694710119
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.3390020824
Short name T144
Test name
Test status
Simulation time 8096339970 ps
CPU time 121.18 seconds
Started Jul 24 05:24:06 PM PDT 24
Finished Jul 24 05:26:08 PM PDT 24
Peak memory 206872 kb
Host smart-a0205c5a-db9e-45e0-b43d-59aced991410
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3390020824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.3390020824
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.3219945154
Short name T2203
Test name
Test status
Simulation time 23412217870 ps
CPU time 22.06 seconds
Started Jul 24 05:30:00 PM PDT 24
Finished Jul 24 05:30:22 PM PDT 24
Peak memory 206984 kb
Host smart-1778fcc8-a98f-4a64-b0e6-8e287440da9a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3219945154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.3219945154
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.943212748
Short name T160
Test name
Test status
Simulation time 5596315891 ps
CPU time 31 seconds
Started Jul 24 05:23:52 PM PDT 24
Finished Jul 24 05:24:24 PM PDT 24
Peak memory 206892 kb
Host smart-5e3244e0-11e9-48b9-b7d6-a0da458a2ae5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=943212748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.943212748
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.1612402821
Short name T565
Test name
Test status
Simulation time 27417367 ps
CPU time 0.62 seconds
Started Jul 24 05:26:43 PM PDT 24
Finished Jul 24 05:26:44 PM PDT 24
Peak memory 206552 kb
Host smart-2db47882-c9d9-44b9-9b8d-826a1f940f43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16124
02821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.1612402821
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.1782947962
Short name T467
Test name
Test status
Simulation time 179611156 ps
CPU time 0.78 seconds
Started Jul 24 05:25:39 PM PDT 24
Finished Jul 24 05:25:40 PM PDT 24
Peak memory 206524 kb
Host smart-94663a23-23f5-4672-9f25-4c73eee410f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17829
47962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.1782947962
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.4029035368
Short name T109
Test name
Test status
Simulation time 189192815 ps
CPU time 0.85 seconds
Started Jul 24 05:25:36 PM PDT 24
Finished Jul 24 05:25:37 PM PDT 24
Peak memory 206504 kb
Host smart-c559bc2d-f335-49e3-b704-74e400913103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40290
35368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.4029035368
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.236536615
Short name T56
Test name
Test status
Simulation time 187976582 ps
CPU time 0.85 seconds
Started Jul 24 05:23:57 PM PDT 24
Finished Jul 24 05:23:58 PM PDT 24
Peak memory 206572 kb
Host smart-af0522c3-cd39-4597-9b18-916735d882cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23653
6615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.236536615
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.2652179587
Short name T171
Test name
Test status
Simulation time 327514292 ps
CPU time 1.98 seconds
Started Jul 24 05:25:07 PM PDT 24
Finished Jul 24 05:25:10 PM PDT 24
Peak memory 206708 kb
Host smart-b59f65db-5361-4c6b-82ad-49a5ac884b11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26521
79587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.2652179587
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_invalid_sync.654845370
Short name T65
Test name
Test status
Simulation time 5960754933 ps
CPU time 54.69 seconds
Started Jul 24 05:24:16 PM PDT 24
Finished Jul 24 05:25:11 PM PDT 24
Peak memory 206984 kb
Host smart-1e056ac2-85bc-4f7c-92fe-545b0de14707
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=654845370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.654845370
Directory /workspace/3.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.2128686680
Short name T43
Test name
Test status
Simulation time 181165300 ps
CPU time 0.79 seconds
Started Jul 24 05:23:43 PM PDT 24
Finished Jul 24 05:23:44 PM PDT 24
Peak memory 206644 kb
Host smart-9b9dcfdf-4519-4a73-8924-393e48fb569e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21286
86680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.2128686680
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.1563838310
Short name T57
Test name
Test status
Simulation time 4173405004 ps
CPU time 8.67 seconds
Started Jul 24 05:23:45 PM PDT 24
Finished Jul 24 05:23:59 PM PDT 24
Peak memory 206876 kb
Host smart-64d11516-becd-4a20-bed7-d9285c99d413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15638
38310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.1563838310
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.2473447972
Short name T58
Test name
Test status
Simulation time 165827828 ps
CPU time 0.8 seconds
Started Jul 24 05:23:41 PM PDT 24
Finished Jul 24 05:23:42 PM PDT 24
Peak memory 206492 kb
Host smart-1a2eff62-2902-4b1a-ad78-0d2b32196e1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24734
47972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.2473447972
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.1686674570
Short name T154
Test name
Test status
Simulation time 10233099915 ps
CPU time 166.41 seconds
Started Jul 24 05:23:50 PM PDT 24
Finished Jul 24 05:26:36 PM PDT 24
Peak memory 206980 kb
Host smart-029fcc25-2197-4b7b-a29c-44e7e25511fd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1686674570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.1686674570
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.1431720208
Short name T2573
Test name
Test status
Simulation time 179454443 ps
CPU time 0.86 seconds
Started Jul 24 05:23:45 PM PDT 24
Finished Jul 24 05:23:46 PM PDT 24
Peak memory 206584 kb
Host smart-19914bdf-0ef6-4cae-88c7-d594e4bf9b0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14317
20208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.1431720208
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.2593564028
Short name T50
Test name
Test status
Simulation time 158859036 ps
CPU time 0.81 seconds
Started Jul 24 05:24:19 PM PDT 24
Finished Jul 24 05:24:20 PM PDT 24
Peak memory 206592 kb
Host smart-e5e67529-b2c2-4a3c-bc20-a441fbf89c0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25935
64028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.2593564028
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.3585334519
Short name T444
Test name
Test status
Simulation time 5361941459 ps
CPU time 148 seconds
Started Jul 24 05:23:45 PM PDT 24
Finished Jul 24 05:26:14 PM PDT 24
Peak memory 206860 kb
Host smart-23294c5b-4078-42dd-9597-a7e6d0dbd499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35853
34519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.3585334519
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.4154894870
Short name T123
Test name
Test status
Simulation time 174643946 ps
CPU time 0.82 seconds
Started Jul 24 05:23:38 PM PDT 24
Finished Jul 24 05:23:39 PM PDT 24
Peak memory 206596 kb
Host smart-1e41fdc8-fffc-48e1-a60d-a8c3e3a27815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41548
94870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.4154894870
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.1843242645
Short name T46
Test name
Test status
Simulation time 392079942 ps
CPU time 1.17 seconds
Started Jul 24 05:23:47 PM PDT 24
Finished Jul 24 05:23:48 PM PDT 24
Peak memory 206588 kb
Host smart-3a004552-be44-46de-a866-a44706decfe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18432
42645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.1843242645
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.3874310578
Short name T2284
Test name
Test status
Simulation time 210950556 ps
CPU time 0.85 seconds
Started Jul 24 05:23:45 PM PDT 24
Finished Jul 24 05:23:46 PM PDT 24
Peak memory 206596 kb
Host smart-f58d65bc-411d-4adb-83b8-b54d68b51741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38743
10578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.3874310578
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.1677974155
Short name T125
Test name
Test status
Simulation time 222684677 ps
CPU time 0.87 seconds
Started Jul 24 05:25:13 PM PDT 24
Finished Jul 24 05:25:14 PM PDT 24
Peak memory 206568 kb
Host smart-65acc6a7-2bb4-4c7d-a708-87a6bd7dad12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16779
74155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.1677974155
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.509530701
Short name T131
Test name
Test status
Simulation time 213960983 ps
CPU time 0.88 seconds
Started Jul 24 05:25:13 PM PDT 24
Finished Jul 24 05:25:14 PM PDT 24
Peak memory 206476 kb
Host smart-d304bd16-d6c4-4335-840a-a788f111aa01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50953
0701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.509530701
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.3538003758
Short name T1850
Test name
Test status
Simulation time 223541515 ps
CPU time 0.91 seconds
Started Jul 24 05:25:36 PM PDT 24
Finished Jul 24 05:25:37 PM PDT 24
Peak memory 206596 kb
Host smart-2f57aec1-e22e-4f4a-8947-08920152ac09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35380
03758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.3538003758
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.149209616
Short name T336
Test name
Test status
Simulation time 150291268 ps
CPU time 0.77 seconds
Started Jul 24 05:25:33 PM PDT 24
Finished Jul 24 05:25:34 PM PDT 24
Peak memory 206592 kb
Host smart-c2b079a2-a94c-46af-a0d5-181930b0c9a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14920
9616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.149209616
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.927161455
Short name T132
Test name
Test status
Simulation time 268344200 ps
CPU time 0.98 seconds
Started Jul 24 05:25:51 PM PDT 24
Finished Jul 24 05:25:52 PM PDT 24
Peak memory 206652 kb
Host smart-9b50cbcb-1400-4f56-a4f6-34769e4a1a61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92716
1455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.927161455
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.4285410761
Short name T136
Test name
Test status
Simulation time 223193539 ps
CPU time 0.87 seconds
Started Jul 24 05:26:27 PM PDT 24
Finished Jul 24 05:26:28 PM PDT 24
Peak memory 206552 kb
Host smart-93386f09-be63-48b3-a00d-c9137601b114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42854
10761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.4285410761
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.2107554405
Short name T137
Test name
Test status
Simulation time 223854103 ps
CPU time 0.87 seconds
Started Jul 24 05:26:27 PM PDT 24
Finished Jul 24 05:26:28 PM PDT 24
Peak memory 206540 kb
Host smart-bab52eb0-16e4-4c4b-90cc-6640a418ca4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21075
54405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.2107554405
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.669815131
Short name T120
Test name
Test status
Simulation time 248535772 ps
CPU time 0.87 seconds
Started Jul 24 05:26:54 PM PDT 24
Finished Jul 24 05:26:55 PM PDT 24
Peak memory 206516 kb
Host smart-5d4abdc1-8932-40ee-9c15-b6d857d7cf3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66981
5131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.669815131
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.161494447
Short name T111
Test name
Test status
Simulation time 169012788 ps
CPU time 0.8 seconds
Started Jul 24 05:27:13 PM PDT 24
Finished Jul 24 05:27:14 PM PDT 24
Peak memory 206612 kb
Host smart-0081f9a2-b9ab-4bd4-9756-34caed60bb59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16149
4447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.161494447
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.2655851616
Short name T114
Test name
Test status
Simulation time 181148903 ps
CPU time 0.84 seconds
Started Jul 24 05:28:38 PM PDT 24
Finished Jul 24 05:28:39 PM PDT 24
Peak memory 206544 kb
Host smart-5b3c2b89-6e17-426d-9903-a1d59b8226eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26558
51616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.2655851616
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2634410808
Short name T2797
Test name
Test status
Simulation time 181350777 ps
CPU time 2.04 seconds
Started Jul 24 05:09:28 PM PDT 24
Finished Jul 24 05:09:31 PM PDT 24
Peak memory 206308 kb
Host smart-dc523f0a-d748-463a-8be8-0a1ca6429c94
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2634410808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.2634410808
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1635004612
Short name T2842
Test name
Test status
Simulation time 525069820 ps
CPU time 7.69 seconds
Started Jul 24 05:09:28 PM PDT 24
Finished Jul 24 05:09:35 PM PDT 24
Peak memory 206264 kb
Host smart-fd2712ca-cda7-4a1d-845b-571c3c80104e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1635004612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1635004612
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2895122480
Short name T253
Test name
Test status
Simulation time 55401477 ps
CPU time 0.77 seconds
Started Jul 24 05:09:31 PM PDT 24
Finished Jul 24 05:09:32 PM PDT 24
Peak memory 206212 kb
Host smart-f24a1510-ed92-4a75-845e-301600c10bbe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2895122480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.2895122480
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3245521407
Short name T270
Test name
Test status
Simulation time 161693343 ps
CPU time 1.4 seconds
Started Jul 24 05:09:31 PM PDT 24
Finished Jul 24 05:09:36 PM PDT 24
Peak memory 214688 kb
Host smart-6b150c83-f076-4f6b-b477-b5eab1cd6a82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245521407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.3245521407
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3120617448
Short name T2779
Test name
Test status
Simulation time 75494774 ps
CPU time 0.93 seconds
Started Jul 24 05:09:18 PM PDT 24
Finished Jul 24 05:09:20 PM PDT 24
Peak memory 206324 kb
Host smart-5051d6ae-a2d9-406f-bac0-dc76b3691c69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3120617448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.3120617448
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3763990483
Short name T2788
Test name
Test status
Simulation time 60009163 ps
CPU time 0.68 seconds
Started Jul 24 05:09:25 PM PDT 24
Finished Jul 24 05:09:26 PM PDT 24
Peak memory 206140 kb
Host smart-7df1490e-f6c8-47d8-a228-79731b4f8100
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3763990483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.3763990483
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.298858622
Short name T249
Test name
Test status
Simulation time 92070044 ps
CPU time 2.14 seconds
Started Jul 24 05:09:16 PM PDT 24
Finished Jul 24 05:09:18 PM PDT 24
Peak memory 222880 kb
Host smart-c4b33025-2a1d-48f3-a5c5-6074a19d3a91
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=298858622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.298858622
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3383682494
Short name T2826
Test name
Test status
Simulation time 400372470 ps
CPU time 2.68 seconds
Started Jul 24 05:09:25 PM PDT 24
Finished Jul 24 05:09:28 PM PDT 24
Peak memory 206396 kb
Host smart-bd769593-9bf2-4e13-b8da-3518daf35006
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3383682494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.3383682494
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1461723756
Short name T2768
Test name
Test status
Simulation time 177746435 ps
CPU time 1.09 seconds
Started Jul 24 05:09:07 PM PDT 24
Finished Jul 24 05:09:08 PM PDT 24
Peak memory 206388 kb
Host smart-25491e47-079f-4cb2-b993-284bcbd58eac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1461723756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.1461723756
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.740936419
Short name T2827
Test name
Test status
Simulation time 513336336 ps
CPU time 2.7 seconds
Started Jul 24 05:09:28 PM PDT 24
Finished Jul 24 05:09:31 PM PDT 24
Peak memory 206380 kb
Host smart-bf87a5dd-697f-40d0-94b7-8f25c0a24ac2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=740936419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.740936419
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2177976062
Short name T2783
Test name
Test status
Simulation time 121095362 ps
CPU time 3.31 seconds
Started Jul 24 05:09:17 PM PDT 24
Finished Jul 24 05:09:21 PM PDT 24
Peak memory 206344 kb
Host smart-6f53bd5f-3fe1-432e-acbc-791888809dcb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2177976062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.2177976062
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1093214078
Short name T2828
Test name
Test status
Simulation time 900918372 ps
CPU time 7.24 seconds
Started Jul 24 05:09:12 PM PDT 24
Finished Jul 24 05:09:19 PM PDT 24
Peak memory 206296 kb
Host smart-8f333a08-2b3e-4c26-975a-86e6d6c38fdf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1093214078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.1093214078
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1693597053
Short name T2800
Test name
Test status
Simulation time 59993494 ps
CPU time 0.82 seconds
Started Jul 24 05:09:25 PM PDT 24
Finished Jul 24 05:09:26 PM PDT 24
Peak memory 205968 kb
Host smart-aae30b0f-a7db-4b85-9d2f-5f369b62c3f7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1693597053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.1693597053
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.779565801
Short name T2757
Test name
Test status
Simulation time 52011571 ps
CPU time 1.32 seconds
Started Jul 24 05:09:11 PM PDT 24
Finished Jul 24 05:09:18 PM PDT 24
Peak memory 214732 kb
Host smart-9a076699-1a71-4305-8bb4-ac89a1e5dac3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779565801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev
_csr_mem_rw_with_rand_reset.779565801
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3372547770
Short name T261
Test name
Test status
Simulation time 83284784 ps
CPU time 0.81 seconds
Started Jul 24 05:09:20 PM PDT 24
Finished Jul 24 05:09:21 PM PDT 24
Peak memory 206116 kb
Host smart-5efbc304-05a0-466f-869b-736983c965a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3372547770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.3372547770
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3368722444
Short name T2812
Test name
Test status
Simulation time 39935829 ps
CPU time 0.68 seconds
Started Jul 24 05:09:31 PM PDT 24
Finished Jul 24 05:09:31 PM PDT 24
Peak memory 206064 kb
Host smart-d6642aca-9339-407f-bd30-1d8725137ae7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3368722444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.3368722444
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1042599695
Short name T247
Test name
Test status
Simulation time 229358105 ps
CPU time 2.37 seconds
Started Jul 24 05:09:21 PM PDT 24
Finished Jul 24 05:09:23 PM PDT 24
Peak memory 215828 kb
Host smart-a82c510c-9911-449a-8a93-6e9c8172ab89
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1042599695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.1042599695
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3545737616
Short name T2811
Test name
Test status
Simulation time 279943684 ps
CPU time 2.51 seconds
Started Jul 24 05:09:28 PM PDT 24
Finished Jul 24 05:09:30 PM PDT 24
Peak memory 206368 kb
Host smart-0d1933d8-2616-460e-8846-e9c54305788a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3545737616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.3545737616
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1742390334
Short name T2818
Test name
Test status
Simulation time 195683203 ps
CPU time 1.71 seconds
Started Jul 24 05:09:23 PM PDT 24
Finished Jul 24 05:09:25 PM PDT 24
Peak memory 206500 kb
Host smart-b0517a06-f2f8-4b5e-a0be-c7e49f144df0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1742390334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.1742390334
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3493795097
Short name T214
Test name
Test status
Simulation time 112921906 ps
CPU time 2.41 seconds
Started Jul 24 05:09:20 PM PDT 24
Finished Jul 24 05:09:23 PM PDT 24
Peak memory 206464 kb
Host smart-57258402-984d-432d-b2d5-bff74ece2312
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3493795097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.3493795097
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3816240225
Short name T2776
Test name
Test status
Simulation time 155330290 ps
CPU time 1.75 seconds
Started Jul 24 05:09:38 PM PDT 24
Finished Jul 24 05:09:40 PM PDT 24
Peak memory 214828 kb
Host smart-7f459567-5e5a-471e-99dc-18c2f1ceedfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816240225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.3816240225
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3637739828
Short name T258
Test name
Test status
Simulation time 83874488 ps
CPU time 1.08 seconds
Started Jul 24 05:09:16 PM PDT 24
Finished Jul 24 05:09:18 PM PDT 24
Peak memory 206312 kb
Host smart-6fa7d75e-9fca-465a-833e-b5460b8a3d39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3637739828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.3637739828
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.241068301
Short name T2834
Test name
Test status
Simulation time 149810343 ps
CPU time 1.41 seconds
Started Jul 24 05:09:25 PM PDT 24
Finished Jul 24 05:09:27 PM PDT 24
Peak memory 206484 kb
Host smart-93b46c9c-8093-45ff-979d-afa13d316837
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=241068301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.241068301
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2568796887
Short name T218
Test name
Test status
Simulation time 106632803 ps
CPU time 1.55 seconds
Started Jul 24 05:09:45 PM PDT 24
Finished Jul 24 05:09:47 PM PDT 24
Peak memory 206380 kb
Host smart-4cef9732-973b-4614-b50c-17e5e66213c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2568796887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.2568796887
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2358854590
Short name T294
Test name
Test status
Simulation time 712057684 ps
CPU time 4.63 seconds
Started Jul 24 05:09:24 PM PDT 24
Finished Jul 24 05:09:29 PM PDT 24
Peak memory 206404 kb
Host smart-f69485a0-010c-4bbc-bb66-c1006d331c90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2358854590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.2358854590
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2157468551
Short name T2824
Test name
Test status
Simulation time 116100790 ps
CPU time 2.32 seconds
Started Jul 24 05:09:30 PM PDT 24
Finished Jul 24 05:09:33 PM PDT 24
Peak memory 214628 kb
Host smart-235b95df-df1e-480d-bba4-67d4938553f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157468551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.2157468551
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3577330590
Short name T244
Test name
Test status
Simulation time 77434619 ps
CPU time 0.96 seconds
Started Jul 24 05:09:33 PM PDT 24
Finished Jul 24 05:09:34 PM PDT 24
Peak memory 206396 kb
Host smart-36a77c74-c9db-4881-8fc1-c50717a5b319
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3577330590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3577330590
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3912354381
Short name T2767
Test name
Test status
Simulation time 44284327 ps
CPU time 0.64 seconds
Started Jul 24 05:09:29 PM PDT 24
Finished Jul 24 05:09:30 PM PDT 24
Peak memory 206052 kb
Host smart-952e1958-976e-484b-a745-d1d5523b32f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3912354381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.3912354381
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2913876717
Short name T257
Test name
Test status
Simulation time 192559997 ps
CPU time 1.69 seconds
Started Jul 24 05:09:22 PM PDT 24
Finished Jul 24 05:09:29 PM PDT 24
Peak memory 206520 kb
Host smart-35389d3e-1636-4d92-aae2-c7e5eb27cc80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2913876717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.2913876717
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2234315270
Short name T2856
Test name
Test status
Simulation time 683820863 ps
CPU time 4.38 seconds
Started Jul 24 05:09:25 PM PDT 24
Finished Jul 24 05:09:30 PM PDT 24
Peak memory 206328 kb
Host smart-55553c24-88f5-4b25-b36d-b119fecde355
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2234315270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.2234315270
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2291126447
Short name T2815
Test name
Test status
Simulation time 119634880 ps
CPU time 1.15 seconds
Started Jul 24 05:09:30 PM PDT 24
Finished Jul 24 05:09:31 PM PDT 24
Peak memory 222964 kb
Host smart-874de42b-d5d2-4916-b2b3-69738be1410b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291126447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.2291126447
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.4112158065
Short name T250
Test name
Test status
Simulation time 77715386 ps
CPU time 0.94 seconds
Started Jul 24 05:09:24 PM PDT 24
Finished Jul 24 05:09:25 PM PDT 24
Peak memory 206392 kb
Host smart-ce5f1fb4-702d-4a35-872e-0b9aecbc6e32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4112158065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.4112158065
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.3706257189
Short name T2801
Test name
Test status
Simulation time 37209425 ps
CPU time 0.67 seconds
Started Jul 24 05:09:39 PM PDT 24
Finished Jul 24 05:09:40 PM PDT 24
Peak memory 206168 kb
Host smart-8b95c2a6-abd2-4e6a-b6c3-6ef9be8a68ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3706257189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.3706257189
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.1242286768
Short name T2784
Test name
Test status
Simulation time 235131069 ps
CPU time 1.55 seconds
Started Jul 24 05:09:26 PM PDT 24
Finished Jul 24 05:09:28 PM PDT 24
Peak memory 206536 kb
Host smart-36e99574-8c46-484d-bf3b-b3cc310c2833
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1242286768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.1242286768
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3316254944
Short name T2849
Test name
Test status
Simulation time 162500701 ps
CPU time 2.04 seconds
Started Jul 24 05:09:18 PM PDT 24
Finished Jul 24 05:09:20 PM PDT 24
Peak memory 214748 kb
Host smart-b68ec468-4657-4444-bea1-c6805e22db09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3316254944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.3316254944
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1481065858
Short name T293
Test name
Test status
Simulation time 919707876 ps
CPU time 3.43 seconds
Started Jul 24 05:09:25 PM PDT 24
Finished Jul 24 05:09:28 PM PDT 24
Peak memory 206512 kb
Host smart-76d961e1-655f-4878-ba63-0c972068b4c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1481065858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.1481065858
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.4068459327
Short name T226
Test name
Test status
Simulation time 69157544 ps
CPU time 1.78 seconds
Started Jul 24 05:09:42 PM PDT 24
Finished Jul 24 05:09:44 PM PDT 24
Peak memory 214724 kb
Host smart-d8d23385-4b19-40d4-ac70-e516c8c6ade4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068459327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.4068459327
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.203028300
Short name T2835
Test name
Test status
Simulation time 62576585 ps
CPU time 0.99 seconds
Started Jul 24 05:09:36 PM PDT 24
Finished Jul 24 05:09:38 PM PDT 24
Peak memory 206356 kb
Host smart-852a6220-ba40-4a34-8e4c-3d128af6d10b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=203028300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.203028300
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.283802562
Short name T273
Test name
Test status
Simulation time 51896756 ps
CPU time 0.69 seconds
Started Jul 24 05:09:23 PM PDT 24
Finished Jul 24 05:09:24 PM PDT 24
Peak memory 206184 kb
Host smart-6e824515-b1c7-4cd4-a9c7-0d079f38e422
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=283802562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.283802562
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1437036512
Short name T188
Test name
Test status
Simulation time 229233892 ps
CPU time 1.82 seconds
Started Jul 24 05:10:11 PM PDT 24
Finished Jul 24 05:10:12 PM PDT 24
Peak memory 206280 kb
Host smart-8cc4a170-f272-4c2a-8c2c-e6d9523bbcbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1437036512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.1437036512
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3403893642
Short name T219
Test name
Test status
Simulation time 118883899 ps
CPU time 2.91 seconds
Started Jul 24 05:09:27 PM PDT 24
Finished Jul 24 05:09:30 PM PDT 24
Peak memory 222536 kb
Host smart-af448c40-a8d1-4848-9597-48e82de371ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3403893642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3403893642
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3415503848
Short name T291
Test name
Test status
Simulation time 283780464 ps
CPU time 2.47 seconds
Started Jul 24 05:09:46 PM PDT 24
Finished Jul 24 05:09:48 PM PDT 24
Peak memory 206384 kb
Host smart-5f0e2007-b15c-4b7e-9187-91edd946d2fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3415503848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.3415503848
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1594167997
Short name T2809
Test name
Test status
Simulation time 90465573 ps
CPU time 1.21 seconds
Started Jul 24 05:09:25 PM PDT 24
Finished Jul 24 05:09:27 PM PDT 24
Peak memory 214588 kb
Host smart-f1aa949a-e68d-40d2-8622-199f683842de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594167997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.1594167997
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3377664494
Short name T2777
Test name
Test status
Simulation time 71339348 ps
CPU time 0.83 seconds
Started Jul 24 05:09:29 PM PDT 24
Finished Jul 24 05:09:30 PM PDT 24
Peak memory 205984 kb
Host smart-b295edf7-fc55-423e-a489-c6cec7347e3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3377664494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.3377664494
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1141560196
Short name T2804
Test name
Test status
Simulation time 119545061 ps
CPU time 1.14 seconds
Started Jul 24 05:09:28 PM PDT 24
Finished Jul 24 05:09:30 PM PDT 24
Peak memory 206532 kb
Host smart-d455e109-7af9-4bcb-893b-0a90468efd60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1141560196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.1141560196
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.261038363
Short name T2846
Test name
Test status
Simulation time 237354369 ps
CPU time 2.41 seconds
Started Jul 24 05:09:39 PM PDT 24
Finished Jul 24 05:09:42 PM PDT 24
Peak memory 222392 kb
Host smart-bc4a5191-34c9-4f5c-a656-79056410d1d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=261038363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.261038363
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3507010451
Short name T224
Test name
Test status
Simulation time 534655328 ps
CPU time 4.01 seconds
Started Jul 24 05:10:01 PM PDT 24
Finished Jul 24 05:10:05 PM PDT 24
Peak memory 206488 kb
Host smart-e76612aa-3eed-400e-97e9-526211162462
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3507010451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3507010451
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.853239174
Short name T2786
Test name
Test status
Simulation time 127766996 ps
CPU time 1.74 seconds
Started Jul 24 05:09:26 PM PDT 24
Finished Jul 24 05:09:28 PM PDT 24
Peak memory 214580 kb
Host smart-a85850fb-f3db-4b07-a8df-f4286ed13046
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853239174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbde
v_csr_mem_rw_with_rand_reset.853239174
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3853283628
Short name T259
Test name
Test status
Simulation time 65384191 ps
CPU time 0.82 seconds
Started Jul 24 05:09:26 PM PDT 24
Finished Jul 24 05:09:27 PM PDT 24
Peak memory 205952 kb
Host smart-e9a62ba1-eda4-49ed-806b-bbd9cca0551a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3853283628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.3853283628
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1862175020
Short name T2802
Test name
Test status
Simulation time 118955080 ps
CPU time 0.69 seconds
Started Jul 24 05:09:22 PM PDT 24
Finished Jul 24 05:09:23 PM PDT 24
Peak memory 206100 kb
Host smart-07c92fca-ccad-4afd-b42d-2f02d5d19637
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1862175020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1862175020
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3313327349
Short name T2759
Test name
Test status
Simulation time 108115108 ps
CPU time 1.06 seconds
Started Jul 24 05:09:26 PM PDT 24
Finished Jul 24 05:09:28 PM PDT 24
Peak memory 206444 kb
Host smart-94152bb7-7894-48e3-a457-5b8ff134dfd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3313327349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.3313327349
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.679487581
Short name T2805
Test name
Test status
Simulation time 270450402 ps
CPU time 3.2 seconds
Started Jul 24 05:09:53 PM PDT 24
Finished Jul 24 05:09:57 PM PDT 24
Peak memory 222376 kb
Host smart-d892c0d8-3163-4ded-aaee-fab2e59d7c37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=679487581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.679487581
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1881118149
Short name T2796
Test name
Test status
Simulation time 98307221 ps
CPU time 1.27 seconds
Started Jul 24 05:09:25 PM PDT 24
Finished Jul 24 05:09:26 PM PDT 24
Peak memory 214708 kb
Host smart-c4afc144-7c13-408d-a2ef-973007070c15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881118149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.1881118149
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2205272172
Short name T2761
Test name
Test status
Simulation time 45209720 ps
CPU time 0.8 seconds
Started Jul 24 05:09:25 PM PDT 24
Finished Jul 24 05:09:26 PM PDT 24
Peak memory 206152 kb
Host smart-22feca68-9cd1-4825-b5bc-0861326d15df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2205272172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2205272172
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2529471484
Short name T2789
Test name
Test status
Simulation time 39592039 ps
CPU time 0.65 seconds
Started Jul 24 05:09:27 PM PDT 24
Finished Jul 24 05:09:28 PM PDT 24
Peak memory 206100 kb
Host smart-52d73534-dc0e-4a08-8bc6-a93481269044
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2529471484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.2529471484
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2729173675
Short name T2838
Test name
Test status
Simulation time 271954761 ps
CPU time 1.49 seconds
Started Jul 24 05:09:29 PM PDT 24
Finished Jul 24 05:09:31 PM PDT 24
Peak memory 206436 kb
Host smart-491a1af8-1972-4546-b2f9-3ea84e250f55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2729173675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.2729173675
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2794009673
Short name T213
Test name
Test status
Simulation time 136935912 ps
CPU time 1.66 seconds
Started Jul 24 05:09:32 PM PDT 24
Finished Jul 24 05:09:34 PM PDT 24
Peak memory 206540 kb
Host smart-3ebb60b1-65a3-430f-a044-11ae1ebc7339
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2794009673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.2794009673
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3337762400
Short name T208
Test name
Test status
Simulation time 382651837 ps
CPU time 2.55 seconds
Started Jul 24 05:09:23 PM PDT 24
Finished Jul 24 05:09:26 PM PDT 24
Peak memory 206308 kb
Host smart-28c8093a-3389-4486-9c70-1ce8fb738bbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3337762400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.3337762400
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.524667785
Short name T2760
Test name
Test status
Simulation time 88626138 ps
CPU time 1.24 seconds
Started Jul 24 05:09:50 PM PDT 24
Finished Jul 24 05:09:51 PM PDT 24
Peak memory 222968 kb
Host smart-a7cef4b5-d00a-4204-b872-7db2990577aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524667785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbde
v_csr_mem_rw_with_rand_reset.524667785
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2119844182
Short name T274
Test name
Test status
Simulation time 87161445 ps
CPU time 0.72 seconds
Started Jul 24 05:09:30 PM PDT 24
Finished Jul 24 05:09:31 PM PDT 24
Peak memory 206316 kb
Host smart-2da0740b-fd54-4189-b31b-972017c0f5d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2119844182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.2119844182
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1679000947
Short name T2795
Test name
Test status
Simulation time 84806685 ps
CPU time 1.17 seconds
Started Jul 24 05:09:45 PM PDT 24
Finished Jul 24 05:09:46 PM PDT 24
Peak memory 206432 kb
Host smart-ade5ff52-7212-48e2-a95a-5ae895d3776c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1679000947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.1679000947
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.718415986
Short name T221
Test name
Test status
Simulation time 280593026 ps
CPU time 3.4 seconds
Started Jul 24 05:09:44 PM PDT 24
Finished Jul 24 05:09:48 PM PDT 24
Peak memory 222236 kb
Host smart-c94edb4e-cb6a-4d17-86ae-c3100a1c508b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=718415986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.718415986
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3393465682
Short name T225
Test name
Test status
Simulation time 749337996 ps
CPU time 3.37 seconds
Started Jul 24 05:09:39 PM PDT 24
Finished Jul 24 05:09:43 PM PDT 24
Peak memory 206468 kb
Host smart-57202eb8-b704-4de5-88d6-dfc17910adeb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3393465682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.3393465682
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.747819010
Short name T2770
Test name
Test status
Simulation time 143227064 ps
CPU time 1.4 seconds
Started Jul 24 05:09:38 PM PDT 24
Finished Jul 24 05:09:40 PM PDT 24
Peak memory 214636 kb
Host smart-29a84d55-eba9-4cb0-a93d-c9981add95dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747819010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbde
v_csr_mem_rw_with_rand_reset.747819010
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3467493909
Short name T209
Test name
Test status
Simulation time 50418454 ps
CPU time 0.79 seconds
Started Jul 24 05:09:40 PM PDT 24
Finished Jul 24 05:09:41 PM PDT 24
Peak memory 206180 kb
Host smart-f93fa9dc-3395-4779-bc8b-a75d1c812428
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3467493909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.3467493909
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3374370061
Short name T2793
Test name
Test status
Simulation time 36875730 ps
CPU time 0.65 seconds
Started Jul 24 05:09:37 PM PDT 24
Finished Jul 24 05:09:38 PM PDT 24
Peak memory 205988 kb
Host smart-2149fc7f-e02c-4522-b1e0-271e976af3db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3374370061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.3374370061
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2144522212
Short name T267
Test name
Test status
Simulation time 170004670 ps
CPU time 1.15 seconds
Started Jul 24 05:09:38 PM PDT 24
Finished Jul 24 05:09:39 PM PDT 24
Peak memory 206524 kb
Host smart-2c0b0b73-8993-4639-b416-57bab550d9ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2144522212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.2144522212
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1284291428
Short name T2840
Test name
Test status
Simulation time 92646756 ps
CPU time 2.44 seconds
Started Jul 24 05:10:00 PM PDT 24
Finished Jul 24 05:10:03 PM PDT 24
Peak memory 222368 kb
Host smart-8338ec6c-a57a-4bb0-88ec-286c0bf19aeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1284291428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1284291428
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3707586038
Short name T290
Test name
Test status
Simulation time 593418841 ps
CPU time 4.03 seconds
Started Jul 24 05:09:37 PM PDT 24
Finished Jul 24 05:09:41 PM PDT 24
Peak memory 206452 kb
Host smart-6d8dd0b1-1802-4378-8e1b-92a3854aaf5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3707586038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.3707586038
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.4136560537
Short name T2852
Test name
Test status
Simulation time 134859351 ps
CPU time 2.28 seconds
Started Jul 24 05:09:26 PM PDT 24
Finished Jul 24 05:09:28 PM PDT 24
Peak memory 214724 kb
Host smart-2b421381-6692-40af-83bf-75a9c0f1cf34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136560537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.4136560537
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1908303176
Short name T2774
Test name
Test status
Simulation time 75535872 ps
CPU time 1 seconds
Started Jul 24 05:09:31 PM PDT 24
Finished Jul 24 05:09:37 PM PDT 24
Peak memory 206368 kb
Host smart-d04b37f2-4bbf-446c-bd0f-1b6dbcb834f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1908303176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.1908303176
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.1457706837
Short name T278
Test name
Test status
Simulation time 44193327 ps
CPU time 0.64 seconds
Started Jul 24 05:09:29 PM PDT 24
Finished Jul 24 05:09:30 PM PDT 24
Peak memory 206188 kb
Host smart-c8b97756-f5f9-4f44-9849-024a997ba0f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1457706837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.1457706837
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.4115734112
Short name T2773
Test name
Test status
Simulation time 111293458 ps
CPU time 1.09 seconds
Started Jul 24 05:10:08 PM PDT 24
Finished Jul 24 05:10:09 PM PDT 24
Peak memory 206432 kb
Host smart-2330c458-02f4-4bd4-bf3e-03cc46010a52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4115734112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.4115734112
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1882703831
Short name T2794
Test name
Test status
Simulation time 104927549 ps
CPU time 1.47 seconds
Started Jul 24 05:09:45 PM PDT 24
Finished Jul 24 05:09:47 PM PDT 24
Peak memory 206548 kb
Host smart-b3f31aa2-c707-4675-8bcc-fa175aefcbbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1882703831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.1882703831
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1792724866
Short name T2782
Test name
Test status
Simulation time 494784625 ps
CPU time 2.9 seconds
Started Jul 24 05:09:42 PM PDT 24
Finished Jul 24 05:09:45 PM PDT 24
Peak memory 206400 kb
Host smart-2a2d25ce-966d-4bd7-a437-0c4e73352fbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1792724866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.1792724866
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1274990011
Short name T246
Test name
Test status
Simulation time 144802003 ps
CPU time 3.2 seconds
Started Jul 24 05:09:17 PM PDT 24
Finished Jul 24 05:09:21 PM PDT 24
Peak memory 206308 kb
Host smart-aca90ced-fb16-4414-9abc-0061c8f739ca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1274990011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.1274990011
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3109377490
Short name T2821
Test name
Test status
Simulation time 583487851 ps
CPU time 4.5 seconds
Started Jul 24 05:09:09 PM PDT 24
Finished Jul 24 05:09:14 PM PDT 24
Peak memory 206380 kb
Host smart-71ab736c-9ff0-4791-bd35-c6c039aec061
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3109377490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.3109377490
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1617099228
Short name T2829
Test name
Test status
Simulation time 151841438 ps
CPU time 1.01 seconds
Started Jul 24 05:09:19 PM PDT 24
Finished Jul 24 05:09:20 PM PDT 24
Peak memory 206216 kb
Host smart-ce80ed9a-b2d6-42b6-bccd-38d9681347a8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1617099228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.1617099228
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.4208480036
Short name T2808
Test name
Test status
Simulation time 106060355 ps
CPU time 2.86 seconds
Started Jul 24 05:09:26 PM PDT 24
Finished Jul 24 05:09:29 PM PDT 24
Peak memory 214712 kb
Host smart-21854bf1-0bd5-488f-88bb-4e63958e579f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208480036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.4208480036
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2659162106
Short name T2771
Test name
Test status
Simulation time 61765347 ps
CPU time 0.95 seconds
Started Jul 24 05:09:24 PM PDT 24
Finished Jul 24 05:09:25 PM PDT 24
Peak memory 206412 kb
Host smart-616ef135-e4c0-46f2-8e59-fd449088ed04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2659162106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2659162106
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3475777820
Short name T2832
Test name
Test status
Simulation time 40887813 ps
CPU time 0.64 seconds
Started Jul 24 05:09:27 PM PDT 24
Finished Jul 24 05:09:28 PM PDT 24
Peak memory 206040 kb
Host smart-6851ccd4-2e71-4944-a15d-16d1bbdec78e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3475777820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.3475777820
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.630560457
Short name T254
Test name
Test status
Simulation time 121084268 ps
CPU time 1.49 seconds
Started Jul 24 05:09:25 PM PDT 24
Finished Jul 24 05:09:27 PM PDT 24
Peak memory 214708 kb
Host smart-780d4450-86bd-4757-9c5d-147fd4094966
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=630560457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.630560457
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1798841543
Short name T2769
Test name
Test status
Simulation time 105147549 ps
CPU time 2.26 seconds
Started Jul 24 05:09:18 PM PDT 24
Finished Jul 24 05:09:21 PM PDT 24
Peak memory 206436 kb
Host smart-59a65de6-abda-435b-8fc0-5759ded83539
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1798841543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.1798841543
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3076568695
Short name T2841
Test name
Test status
Simulation time 201063475 ps
CPU time 1.48 seconds
Started Jul 24 05:09:11 PM PDT 24
Finished Jul 24 05:09:12 PM PDT 24
Peak memory 206472 kb
Host smart-4e51fb37-389e-45b7-9a9b-d0c33255d398
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3076568695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.3076568695
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2382057390
Short name T222
Test name
Test status
Simulation time 95039956 ps
CPU time 2.14 seconds
Started Jul 24 05:09:14 PM PDT 24
Finished Jul 24 05:09:17 PM PDT 24
Peak memory 222000 kb
Host smart-43eb28c5-5712-458f-a013-874747ec0943
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2382057390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.2382057390
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3125186302
Short name T2853
Test name
Test status
Simulation time 479400835 ps
CPU time 4.19 seconds
Started Jul 24 05:09:23 PM PDT 24
Finished Jul 24 05:09:27 PM PDT 24
Peak memory 206492 kb
Host smart-1eb1e220-6dad-4056-a2f0-73321f69c068
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3125186302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.3125186302
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3608362729
Short name T2822
Test name
Test status
Simulation time 48303024 ps
CPU time 0.63 seconds
Started Jul 24 05:09:34 PM PDT 24
Finished Jul 24 05:09:35 PM PDT 24
Peak memory 206104 kb
Host smart-1ef6ba61-450c-4e6c-8391-13182e3e9098
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3608362729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.3608362729
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1134499698
Short name T2830
Test name
Test status
Simulation time 53429407 ps
CPU time 0.69 seconds
Started Jul 24 05:09:38 PM PDT 24
Finished Jul 24 05:09:39 PM PDT 24
Peak memory 206104 kb
Host smart-1219bbcc-9a16-4511-829c-f30788a1cc8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1134499698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.1134499698
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.469817205
Short name T2820
Test name
Test status
Simulation time 41619567 ps
CPU time 0.66 seconds
Started Jul 24 05:09:46 PM PDT 24
Finished Jul 24 05:09:46 PM PDT 24
Peak memory 206040 kb
Host smart-12466960-c772-4598-9fc4-7ca76fb4de9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=469817205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.469817205
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2703030669
Short name T2754
Test name
Test status
Simulation time 63850863 ps
CPU time 0.67 seconds
Started Jul 24 05:09:32 PM PDT 24
Finished Jul 24 05:09:33 PM PDT 24
Peak memory 206156 kb
Host smart-dc5e7b45-747e-4a9c-8b75-2d60b06c2141
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2703030669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.2703030669
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.249321189
Short name T2845
Test name
Test status
Simulation time 36845112 ps
CPU time 0.65 seconds
Started Jul 24 05:09:27 PM PDT 24
Finished Jul 24 05:09:28 PM PDT 24
Peak memory 206184 kb
Host smart-15b99cd6-12b3-46c0-97d5-cd2291f7d0ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=249321189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.249321189
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.3455123101
Short name T2843
Test name
Test status
Simulation time 49109017 ps
CPU time 0.68 seconds
Started Jul 24 05:09:30 PM PDT 24
Finished Jul 24 05:09:31 PM PDT 24
Peak memory 206084 kb
Host smart-681aef74-943d-4eab-a239-127dce66ac66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3455123101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.3455123101
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.3613679734
Short name T2763
Test name
Test status
Simulation time 50982793 ps
CPU time 0.64 seconds
Started Jul 24 05:09:28 PM PDT 24
Finished Jul 24 05:09:29 PM PDT 24
Peak memory 206108 kb
Host smart-c3a2d0f2-6a2a-4b05-8684-0410d60d3d51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3613679734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.3613679734
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3527391410
Short name T2775
Test name
Test status
Simulation time 35600054 ps
CPU time 0.67 seconds
Started Jul 24 05:09:39 PM PDT 24
Finished Jul 24 05:09:42 PM PDT 24
Peak memory 206072 kb
Host smart-e5147d13-a299-4c5f-8824-48b10bdafb49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3527391410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.3527391410
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3262301168
Short name T2755
Test name
Test status
Simulation time 38112221 ps
CPU time 0.66 seconds
Started Jul 24 05:09:33 PM PDT 24
Finished Jul 24 05:09:40 PM PDT 24
Peak memory 206000 kb
Host smart-bff5a5a8-37f8-4d76-9d4c-ec9e3acaddce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3262301168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.3262301168
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2050121333
Short name T280
Test name
Test status
Simulation time 84497012 ps
CPU time 0.66 seconds
Started Jul 24 05:09:42 PM PDT 24
Finished Jul 24 05:09:43 PM PDT 24
Peak memory 206104 kb
Host smart-687ad6df-73d3-4433-859e-1e4103f80e58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2050121333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.2050121333
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3363138068
Short name T2785
Test name
Test status
Simulation time 178658897 ps
CPU time 2.06 seconds
Started Jul 24 05:09:17 PM PDT 24
Finished Jul 24 05:09:19 PM PDT 24
Peak memory 206444 kb
Host smart-96ec5d6a-01b7-4b04-ace5-b3d4fb8acb93
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3363138068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3363138068
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.883601181
Short name T252
Test name
Test status
Simulation time 753880758 ps
CPU time 4.56 seconds
Started Jul 24 05:09:11 PM PDT 24
Finished Jul 24 05:09:15 PM PDT 24
Peak memory 206228 kb
Host smart-e0171a33-f080-4dca-b0f9-65fd624f5514
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=883601181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.883601181
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3126636714
Short name T255
Test name
Test status
Simulation time 103169227 ps
CPU time 0.82 seconds
Started Jul 24 05:09:30 PM PDT 24
Finished Jul 24 05:09:35 PM PDT 24
Peak memory 206192 kb
Host smart-e6b4f30a-ea26-4673-bd0c-79396dc3cc03
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3126636714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3126636714
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3997252494
Short name T2848
Test name
Test status
Simulation time 119871802 ps
CPU time 1.44 seconds
Started Jul 24 05:09:12 PM PDT 24
Finished Jul 24 05:09:14 PM PDT 24
Peak memory 214808 kb
Host smart-32284bdb-4434-4299-b8f6-58b693978353
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997252494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.3997252494
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3417700629
Short name T2764
Test name
Test status
Simulation time 77388255 ps
CPU time 0.97 seconds
Started Jul 24 05:09:19 PM PDT 24
Finished Jul 24 05:09:20 PM PDT 24
Peak memory 206296 kb
Host smart-fc5d3c7f-70bf-428d-88d4-ff2522ead926
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3417700629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.3417700629
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3217844459
Short name T281
Test name
Test status
Simulation time 69422014 ps
CPU time 0.7 seconds
Started Jul 24 05:09:28 PM PDT 24
Finished Jul 24 05:09:29 PM PDT 24
Peak memory 206180 kb
Host smart-af78bc26-87e9-44a4-9496-7252da09f796
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3217844459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3217844459
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3473302124
Short name T2825
Test name
Test status
Simulation time 53939236 ps
CPU time 1.4 seconds
Started Jul 24 05:09:11 PM PDT 24
Finished Jul 24 05:09:13 PM PDT 24
Peak memory 214612 kb
Host smart-4c9593d7-c8ad-44d3-80f0-83fb62b03d96
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3473302124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.3473302124
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3418127441
Short name T2803
Test name
Test status
Simulation time 177197619 ps
CPU time 3.97 seconds
Started Jul 24 05:09:22 PM PDT 24
Finished Jul 24 05:09:26 PM PDT 24
Peak memory 206288 kb
Host smart-9acb4934-7759-4c21-a43c-9d9f835cf901
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3418127441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.3418127441
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.655620975
Short name T2780
Test name
Test status
Simulation time 129656589 ps
CPU time 1.2 seconds
Started Jul 24 05:09:11 PM PDT 24
Finished Jul 24 05:09:12 PM PDT 24
Peak memory 206332 kb
Host smart-bd7040c8-9479-43cb-84d9-e9016f362082
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=655620975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.655620975
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2088854376
Short name T216
Test name
Test status
Simulation time 103287529 ps
CPU time 2.71 seconds
Started Jul 24 05:09:24 PM PDT 24
Finished Jul 24 05:09:27 PM PDT 24
Peak memory 222332 kb
Host smart-6d96a9f3-0fce-48cd-a0e8-815ebf455d4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2088854376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2088854376
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2620643232
Short name T2823
Test name
Test status
Simulation time 908737958 ps
CPU time 2.97 seconds
Started Jul 24 05:09:33 PM PDT 24
Finished Jul 24 05:09:36 PM PDT 24
Peak memory 206404 kb
Host smart-fe7814ee-8828-4450-9130-29400c773649
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2620643232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.2620643232
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3973027501
Short name T2855
Test name
Test status
Simulation time 49432160 ps
CPU time 0.65 seconds
Started Jul 24 05:09:37 PM PDT 24
Finished Jul 24 05:09:38 PM PDT 24
Peak memory 206120 kb
Host smart-9ffb8d44-3d40-4935-a0d3-461b36cd7a4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3973027501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.3973027501
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.1534597192
Short name T2819
Test name
Test status
Simulation time 96163704 ps
CPU time 0.73 seconds
Started Jul 24 05:10:12 PM PDT 24
Finished Jul 24 05:10:13 PM PDT 24
Peak memory 206144 kb
Host smart-7d62516e-43d1-471c-8b55-c33d08cedd19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1534597192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.1534597192
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1699732998
Short name T2847
Test name
Test status
Simulation time 55791161 ps
CPU time 0.64 seconds
Started Jul 24 05:09:26 PM PDT 24
Finished Jul 24 05:09:27 PM PDT 24
Peak memory 206320 kb
Host smart-62ab329e-0d7e-4df6-957e-9f785220e5b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1699732998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.1699732998
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3471885260
Short name T195
Test name
Test status
Simulation time 34340201 ps
CPU time 0.68 seconds
Started Jul 24 05:09:27 PM PDT 24
Finished Jul 24 05:09:28 PM PDT 24
Peak memory 206104 kb
Host smart-e7145adf-c3c8-4f36-973d-8b6315f3c84b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3471885260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.3471885260
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1405335206
Short name T287
Test name
Test status
Simulation time 32651666 ps
CPU time 0.72 seconds
Started Jul 24 05:09:49 PM PDT 24
Finished Jul 24 05:09:50 PM PDT 24
Peak memory 206132 kb
Host smart-170b2385-9b30-49f1-98bc-f9c0ace1dd2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1405335206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.1405335206
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.4169291373
Short name T2854
Test name
Test status
Simulation time 72516419 ps
CPU time 0.7 seconds
Started Jul 24 05:09:26 PM PDT 24
Finished Jul 24 05:09:27 PM PDT 24
Peak memory 206136 kb
Host smart-250c240e-fbf0-4915-a4f8-282854232ca6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4169291373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.4169291373
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.979834256
Short name T2837
Test name
Test status
Simulation time 40363044 ps
CPU time 0.66 seconds
Started Jul 24 05:09:31 PM PDT 24
Finished Jul 24 05:09:32 PM PDT 24
Peak memory 206312 kb
Host smart-6d0022b7-4246-49af-b15a-17c1667fb77f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=979834256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.979834256
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.834369629
Short name T2810
Test name
Test status
Simulation time 30870679 ps
CPU time 0.67 seconds
Started Jul 24 05:09:36 PM PDT 24
Finished Jul 24 05:09:37 PM PDT 24
Peak memory 206212 kb
Host smart-e5d88a97-5e5f-4f9d-a164-8b1081b72180
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=834369629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.834369629
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.735450163
Short name T2836
Test name
Test status
Simulation time 379721724 ps
CPU time 3.5 seconds
Started Jul 24 05:09:39 PM PDT 24
Finished Jul 24 05:09:43 PM PDT 24
Peak memory 206288 kb
Host smart-e5425277-d131-43e3-aada-f487cb6b8154
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=735450163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.735450163
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.426107022
Short name T2857
Test name
Test status
Simulation time 1472929466 ps
CPU time 9.03 seconds
Started Jul 24 05:09:40 PM PDT 24
Finished Jul 24 05:09:49 PM PDT 24
Peak memory 206448 kb
Host smart-23439c54-79d6-48f0-ade5-31dc997c3054
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=426107022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.426107022
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1014073214
Short name T268
Test name
Test status
Simulation time 122437915 ps
CPU time 0.95 seconds
Started Jul 24 05:09:15 PM PDT 24
Finished Jul 24 05:09:16 PM PDT 24
Peak memory 206080 kb
Host smart-e003b0f7-bda2-438a-9dc9-adb2801b2e68
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1014073214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.1014073214
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1111431156
Short name T2758
Test name
Test status
Simulation time 80574311 ps
CPU time 1.24 seconds
Started Jul 24 05:09:25 PM PDT 24
Finished Jul 24 05:09:27 PM PDT 24
Peak memory 214656 kb
Host smart-e2db8d24-5d5b-4c20-bba0-cab2581a55a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111431156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.1111431156
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.863797748
Short name T2844
Test name
Test status
Simulation time 63221385 ps
CPU time 0.84 seconds
Started Jul 24 05:09:09 PM PDT 24
Finished Jul 24 05:09:10 PM PDT 24
Peak memory 206080 kb
Host smart-e6e6dfee-2821-4e34-ba7e-ddbed96304f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=863797748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.863797748
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1551320239
Short name T243
Test name
Test status
Simulation time 110385769 ps
CPU time 1.44 seconds
Started Jul 24 05:09:29 PM PDT 24
Finished Jul 24 05:09:31 PM PDT 24
Peak memory 214624 kb
Host smart-0426c6e5-8ceb-4e88-bf9a-6389ed30a1bf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1551320239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.1551320239
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.8866957
Short name T2831
Test name
Test status
Simulation time 640295409 ps
CPU time 4.48 seconds
Started Jul 24 05:09:44 PM PDT 24
Finished Jul 24 05:09:49 PM PDT 24
Peak memory 206384 kb
Host smart-3249d47d-2c11-4c76-b1b7-345209418149
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=8866957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.8866957
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2551313457
Short name T256
Test name
Test status
Simulation time 166966198 ps
CPU time 1.31 seconds
Started Jul 24 05:09:22 PM PDT 24
Finished Jul 24 05:09:24 PM PDT 24
Peak memory 206408 kb
Host smart-3558ab10-6268-4f33-8e54-0f45532b00e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2551313457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.2551313457
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.445539011
Short name T2798
Test name
Test status
Simulation time 96942537 ps
CPU time 1.51 seconds
Started Jul 24 05:09:24 PM PDT 24
Finished Jul 24 05:09:26 PM PDT 24
Peak memory 206432 kb
Host smart-efdd5fc6-da7e-4876-9fc1-d56f73f64eda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=445539011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.445539011
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1863841513
Short name T215
Test name
Test status
Simulation time 1029300329 ps
CPU time 5.14 seconds
Started Jul 24 05:09:16 PM PDT 24
Finished Jul 24 05:09:21 PM PDT 24
Peak memory 206448 kb
Host smart-c8218067-9ffe-42ba-9641-2ca5fa4cc4a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1863841513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.1863841513
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3140600296
Short name T194
Test name
Test status
Simulation time 47907706 ps
CPU time 0.67 seconds
Started Jul 24 05:09:26 PM PDT 24
Finished Jul 24 05:09:27 PM PDT 24
Peak memory 206180 kb
Host smart-0078449c-a95b-4343-a5f1-33c1d29302d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3140600296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3140600296
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1677702887
Short name T196
Test name
Test status
Simulation time 46928416 ps
CPU time 0.7 seconds
Started Jul 24 05:09:29 PM PDT 24
Finished Jul 24 05:09:30 PM PDT 24
Peak memory 206116 kb
Host smart-3439fd15-a89f-4c4c-a1ce-7d022ab7f03c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1677702887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.1677702887
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1153727637
Short name T2756
Test name
Test status
Simulation time 42695218 ps
CPU time 0.65 seconds
Started Jul 24 05:09:52 PM PDT 24
Finished Jul 24 05:09:53 PM PDT 24
Peak memory 206152 kb
Host smart-4c08bd1a-c775-4c63-9ead-1ad2883a2aa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1153727637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.1153727637
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.529754478
Short name T2850
Test name
Test status
Simulation time 31802400 ps
CPU time 0.66 seconds
Started Jul 24 05:09:54 PM PDT 24
Finished Jul 24 05:09:55 PM PDT 24
Peak memory 206312 kb
Host smart-e3eb9d24-e075-443a-a643-ea2fcf6541f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=529754478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.529754478
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2052197678
Short name T285
Test name
Test status
Simulation time 50049356 ps
CPU time 0.65 seconds
Started Jul 24 05:09:52 PM PDT 24
Finished Jul 24 05:09:53 PM PDT 24
Peak memory 206320 kb
Host smart-18da57c8-2140-4e1d-81a4-a478774b9e66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2052197678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.2052197678
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.20284216
Short name T193
Test name
Test status
Simulation time 53949783 ps
CPU time 0.65 seconds
Started Jul 24 05:09:42 PM PDT 24
Finished Jul 24 05:09:44 PM PDT 24
Peak memory 206104 kb
Host smart-d2029b80-7280-4efc-82b4-25d22b17d02d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=20284216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.20284216
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1072978186
Short name T286
Test name
Test status
Simulation time 43340025 ps
CPU time 0.67 seconds
Started Jul 24 05:09:34 PM PDT 24
Finished Jul 24 05:09:35 PM PDT 24
Peak memory 206132 kb
Host smart-91530d55-3074-4197-b345-1a10af8295a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1072978186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.1072978186
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3888452380
Short name T2851
Test name
Test status
Simulation time 42817239 ps
CPU time 0.66 seconds
Started Jul 24 05:09:36 PM PDT 24
Finished Jul 24 05:09:37 PM PDT 24
Peak memory 206188 kb
Host smart-e9506d30-731a-4b37-ac59-e800c233bf02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3888452380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.3888452380
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3116198052
Short name T2816
Test name
Test status
Simulation time 32391643 ps
CPU time 0.64 seconds
Started Jul 24 05:09:41 PM PDT 24
Finished Jul 24 05:09:42 PM PDT 24
Peak memory 206108 kb
Host smart-fdfc6c61-1442-4aa6-acad-16c6b58f883e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3116198052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.3116198052
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2168303464
Short name T2762
Test name
Test status
Simulation time 61900404 ps
CPU time 1.19 seconds
Started Jul 24 05:09:18 PM PDT 24
Finished Jul 24 05:09:20 PM PDT 24
Peak memory 214768 kb
Host smart-c825ab88-7309-4bfa-a09f-beb1a9967ebf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168303464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.2168303464
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.517216502
Short name T251
Test name
Test status
Simulation time 78293461 ps
CPU time 1.1 seconds
Started Jul 24 05:09:27 PM PDT 24
Finished Jul 24 05:09:28 PM PDT 24
Peak memory 206384 kb
Host smart-d825540e-c15b-402c-abc1-6f856af9e17a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=517216502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.517216502
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2123503256
Short name T277
Test name
Test status
Simulation time 40730838 ps
CPU time 0.67 seconds
Started Jul 24 05:09:25 PM PDT 24
Finished Jul 24 05:09:26 PM PDT 24
Peak memory 206180 kb
Host smart-ee888884-1061-4e01-a72b-79458df19bb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2123503256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.2123503256
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2245824001
Short name T269
Test name
Test status
Simulation time 206300452 ps
CPU time 1.21 seconds
Started Jul 24 05:09:24 PM PDT 24
Finished Jul 24 05:09:25 PM PDT 24
Peak memory 206552 kb
Host smart-8793ae82-d946-47a4-86ce-f422ea5ab207
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2245824001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.2245824001
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3537282453
Short name T217
Test name
Test status
Simulation time 244294852 ps
CPU time 2.55 seconds
Started Jul 24 05:09:18 PM PDT 24
Finished Jul 24 05:09:21 PM PDT 24
Peak memory 214676 kb
Host smart-e33a6f12-b6eb-444c-9839-1053e5b4ab63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3537282453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.3537282453
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.775404388
Short name T207
Test name
Test status
Simulation time 91031445 ps
CPU time 1.15 seconds
Started Jul 24 05:09:40 PM PDT 24
Finished Jul 24 05:09:41 PM PDT 24
Peak memory 214704 kb
Host smart-757e00fa-7101-427a-a217-a6901f6bf190
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775404388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev
_csr_mem_rw_with_rand_reset.775404388
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1089599245
Short name T2839
Test name
Test status
Simulation time 124342304 ps
CPU time 1.08 seconds
Started Jul 24 05:09:25 PM PDT 24
Finished Jul 24 05:09:26 PM PDT 24
Peak memory 206596 kb
Host smart-dba36b68-4736-45ef-81c1-03a6e6f2e3e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1089599245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1089599245
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.252510513
Short name T272
Test name
Test status
Simulation time 67684844 ps
CPU time 0.72 seconds
Started Jul 24 05:09:34 PM PDT 24
Finished Jul 24 05:09:35 PM PDT 24
Peak memory 206140 kb
Host smart-5d11dbc3-6216-444a-b163-28357b738f8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=252510513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.252510513
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.573513181
Short name T2817
Test name
Test status
Simulation time 96663000 ps
CPU time 1.04 seconds
Started Jul 24 05:09:10 PM PDT 24
Finished Jul 24 05:09:11 PM PDT 24
Peak memory 206276 kb
Host smart-d2c1e68c-58e0-4560-83b7-7158676f9cb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=573513181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.573513181
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.128359637
Short name T2792
Test name
Test status
Simulation time 315112962 ps
CPU time 3.09 seconds
Started Jul 24 05:09:32 PM PDT 24
Finished Jul 24 05:09:35 PM PDT 24
Peak memory 222496 kb
Host smart-4848ccd2-e208-41b2-9365-b5e49028575b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=128359637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.128359637
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2266303038
Short name T2814
Test name
Test status
Simulation time 401949687 ps
CPU time 2.92 seconds
Started Jul 24 05:09:24 PM PDT 24
Finished Jul 24 05:09:27 PM PDT 24
Peak memory 206372 kb
Host smart-3268bf83-8b94-4bb5-8522-29425f849445
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2266303038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.2266303038
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1507515024
Short name T186
Test name
Test status
Simulation time 132683033 ps
CPU time 1.3 seconds
Started Jul 24 05:09:25 PM PDT 24
Finished Jul 24 05:09:27 PM PDT 24
Peak memory 216236 kb
Host smart-71e27e7b-1cf9-4255-b374-6865e1bef8b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507515024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.1507515024
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2958526170
Short name T2813
Test name
Test status
Simulation time 66171826 ps
CPU time 0.83 seconds
Started Jul 24 05:09:36 PM PDT 24
Finished Jul 24 05:09:37 PM PDT 24
Peak memory 206152 kb
Host smart-dba015f0-3fc0-440a-9f3d-37f8e08a1297
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2958526170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.2958526170
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.432163736
Short name T2766
Test name
Test status
Simulation time 111251279 ps
CPU time 0.7 seconds
Started Jul 24 05:09:33 PM PDT 24
Finished Jul 24 05:09:34 PM PDT 24
Peak memory 206024 kb
Host smart-edf56c67-857e-4c1b-af49-9a3cac127dda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=432163736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.432163736
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.4013237879
Short name T260
Test name
Test status
Simulation time 81862012 ps
CPU time 1.33 seconds
Started Jul 24 05:09:23 PM PDT 24
Finished Jul 24 05:09:25 PM PDT 24
Peak memory 206400 kb
Host smart-7dbcbf64-7f0f-46e1-a340-a820dae75ad3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4013237879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.4013237879
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.949887544
Short name T2781
Test name
Test status
Simulation time 301034932 ps
CPU time 3.63 seconds
Started Jul 24 05:09:52 PM PDT 24
Finished Jul 24 05:09:56 PM PDT 24
Peak memory 214776 kb
Host smart-19ae3489-2cc1-4a41-ab5c-22527cc09fbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=949887544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.949887544
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.71190879
Short name T220
Test name
Test status
Simulation time 133483720 ps
CPU time 1.32 seconds
Started Jul 24 05:09:20 PM PDT 24
Finished Jul 24 05:09:22 PM PDT 24
Peak memory 214588 kb
Host smart-23763b06-5946-4225-9b4e-c18dcd38f044
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71190879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_
csr_mem_rw_with_rand_reset.71190879
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.3299411681
Short name T2791
Test name
Test status
Simulation time 51800016 ps
CPU time 0.94 seconds
Started Jul 24 05:09:25 PM PDT 24
Finished Jul 24 05:09:26 PM PDT 24
Peak memory 206292 kb
Host smart-15786f9d-031d-4118-8fc2-81bb05a3e32c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3299411681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.3299411681
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.719454186
Short name T192
Test name
Test status
Simulation time 52681284 ps
CPU time 0.68 seconds
Started Jul 24 05:09:28 PM PDT 24
Finished Jul 24 05:09:29 PM PDT 24
Peak memory 206192 kb
Host smart-687a333a-cc8e-4049-8721-c7ed1bfc0f1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=719454186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.719454186
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2677499648
Short name T2790
Test name
Test status
Simulation time 218058401 ps
CPU time 1.69 seconds
Started Jul 24 05:09:22 PM PDT 24
Finished Jul 24 05:09:24 PM PDT 24
Peak memory 206540 kb
Host smart-6aaf4567-8a99-4d4a-80e4-8577456e6c7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2677499648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.2677499648
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1624675580
Short name T2807
Test name
Test status
Simulation time 61292497 ps
CPU time 1.6 seconds
Started Jul 24 05:09:15 PM PDT 24
Finished Jul 24 05:09:17 PM PDT 24
Peak memory 206524 kb
Host smart-5137c0b5-24de-483a-b5d0-31ab47cd2093
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1624675580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.1624675580
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.538300584
Short name T2787
Test name
Test status
Simulation time 1332994019 ps
CPU time 5.42 seconds
Started Jul 24 05:09:14 PM PDT 24
Finished Jul 24 05:09:19 PM PDT 24
Peak memory 206420 kb
Host smart-79d9be1a-a27f-48ef-8f22-44353edd538e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=538300584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.538300584
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3936605047
Short name T2833
Test name
Test status
Simulation time 61808000 ps
CPU time 1.34 seconds
Started Jul 24 05:09:29 PM PDT 24
Finished Jul 24 05:09:30 PM PDT 24
Peak memory 214680 kb
Host smart-4a53f568-4379-4a2c-853b-353004bbb60e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936605047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.3936605047
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2352431469
Short name T248
Test name
Test status
Simulation time 53188030 ps
CPU time 0.94 seconds
Started Jul 24 05:09:29 PM PDT 24
Finished Jul 24 05:09:30 PM PDT 24
Peak memory 206388 kb
Host smart-9720f327-2279-4ab1-976d-d7b43391dbee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2352431469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2352431469
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.900878424
Short name T2772
Test name
Test status
Simulation time 47089664 ps
CPU time 0.69 seconds
Started Jul 24 05:09:26 PM PDT 24
Finished Jul 24 05:09:27 PM PDT 24
Peak memory 206168 kb
Host smart-d3903517-d684-4645-8c97-106888446a67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=900878424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.900878424
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3081985009
Short name T2806
Test name
Test status
Simulation time 81055698 ps
CPU time 1.12 seconds
Started Jul 24 05:09:18 PM PDT 24
Finished Jul 24 05:09:24 PM PDT 24
Peak memory 206508 kb
Host smart-75965638-f848-40da-a94b-89f97950b6de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3081985009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.3081985009
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3918756557
Short name T2765
Test name
Test status
Simulation time 100408222 ps
CPU time 1.44 seconds
Started Jul 24 05:09:11 PM PDT 24
Finished Jul 24 05:09:13 PM PDT 24
Peak memory 221992 kb
Host smart-412696fc-3b6f-4532-b60f-db7fdf06d830
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3918756557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.3918756557
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1451492623
Short name T2799
Test name
Test status
Simulation time 483981226 ps
CPU time 2.87 seconds
Started Jul 24 05:09:34 PM PDT 24
Finished Jul 24 05:09:37 PM PDT 24
Peak memory 206500 kb
Host smart-11b7cd04-8ede-4f08-a24f-52c71f786e46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1451492623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.1451492623
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.410401822
Short name T2221
Test name
Test status
Simulation time 31930572 ps
CPU time 0.62 seconds
Started Jul 24 05:23:44 PM PDT 24
Finished Jul 24 05:23:44 PM PDT 24
Peak memory 206612 kb
Host smart-3746dcfb-ec3c-4116-82b4-0cc7057aaca9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=410401822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.410401822
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.164748146
Short name T6
Test name
Test status
Simulation time 3457910139 ps
CPU time 3.82 seconds
Started Jul 24 05:23:49 PM PDT 24
Finished Jul 24 05:23:53 PM PDT 24
Peak memory 206676 kb
Host smart-730cef6c-df26-4035-ae50-e03b38308163
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=164748146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.164748146
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.1306373631
Short name T1968
Test name
Test status
Simulation time 13344769083 ps
CPU time 13.87 seconds
Started Jul 24 05:23:39 PM PDT 24
Finished Jul 24 05:23:53 PM PDT 24
Peak memory 206704 kb
Host smart-8af7af63-1b93-4e98-8dfd-cb316e78d13a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1306373631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.1306373631
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.3414075103
Short name T2316
Test name
Test status
Simulation time 23348233473 ps
CPU time 22.07 seconds
Started Jul 24 05:23:39 PM PDT 24
Finished Jul 24 05:24:01 PM PDT 24
Peak memory 206912 kb
Host smart-3ca7c869-2c28-4e5f-8e0e-bdd973a6d355
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3414075103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.3414075103
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.4041606119
Short name T1293
Test name
Test status
Simulation time 191976247 ps
CPU time 0.79 seconds
Started Jul 24 05:23:46 PM PDT 24
Finished Jul 24 05:23:47 PM PDT 24
Peak memory 206596 kb
Host smart-2aaab8fe-9a86-48eb-bc38-3c24adfe5d78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40416
06119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.4041606119
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.1765017498
Short name T1500
Test name
Test status
Simulation time 169458897 ps
CPU time 0.79 seconds
Started Jul 24 05:23:53 PM PDT 24
Finished Jul 24 05:23:54 PM PDT 24
Peak memory 206556 kb
Host smart-136fafaf-93bd-4a68-a3cd-e5005113b8df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17650
17498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.1765017498
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.248976077
Short name T52
Test name
Test status
Simulation time 266372796 ps
CPU time 0.96 seconds
Started Jul 24 05:23:35 PM PDT 24
Finished Jul 24 05:23:36 PM PDT 24
Peak memory 206560 kb
Host smart-0b853b79-e165-4b7f-88a5-3a1cf0ffe6d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24897
6077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.248976077
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.1325515397
Short name T1525
Test name
Test status
Simulation time 1008455586 ps
CPU time 2.47 seconds
Started Jul 24 05:23:40 PM PDT 24
Finished Jul 24 05:23:42 PM PDT 24
Peak memory 206800 kb
Host smart-51329841-7294-44fc-acfa-7a54322997dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13255
15397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.1325515397
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.3348219257
Short name T2000
Test name
Test status
Simulation time 11959312327 ps
CPU time 21.32 seconds
Started Jul 24 05:23:43 PM PDT 24
Finished Jul 24 05:24:05 PM PDT 24
Peak memory 206900 kb
Host smart-82647964-efb1-4719-9eb8-de0cff8601ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33482
19257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.3348219257
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.3649451241
Short name T1632
Test name
Test status
Simulation time 473480761 ps
CPU time 1.26 seconds
Started Jul 24 05:23:41 PM PDT 24
Finished Jul 24 05:23:42 PM PDT 24
Peak memory 206504 kb
Host smart-75846b36-42c9-465c-b1b6-35b751592527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36494
51241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.3649451241
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.3958407304
Short name T1479
Test name
Test status
Simulation time 146100451 ps
CPU time 0.75 seconds
Started Jul 24 05:23:39 PM PDT 24
Finished Jul 24 05:23:40 PM PDT 24
Peak memory 206476 kb
Host smart-8fa3a79c-b580-40ef-be1d-b3879e3e8cec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39584
07304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.3958407304
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.714541667
Short name T750
Test name
Test status
Simulation time 5108604513 ps
CPU time 133.95 seconds
Started Jul 24 05:23:40 PM PDT 24
Finished Jul 24 05:25:54 PM PDT 24
Peak memory 206948 kb
Host smart-9741aa33-7228-4cea-9598-997e89d0bc87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71454
1667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.714541667
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_enable.3525712249
Short name T461
Test name
Test status
Simulation time 39158489 ps
CPU time 0.65 seconds
Started Jul 24 05:23:41 PM PDT 24
Finished Jul 24 05:23:42 PM PDT 24
Peak memory 206580 kb
Host smart-029d6839-db33-46e5-9c43-92465febe803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35257
12249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.3525712249
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.918540082
Short name T1621
Test name
Test status
Simulation time 798549879 ps
CPU time 1.92 seconds
Started Jul 24 05:23:57 PM PDT 24
Finished Jul 24 05:23:59 PM PDT 24
Peak memory 206772 kb
Host smart-cc9fbeb3-f478-49fb-9ce8-4581b9423367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91854
0082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.918540082
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.2654118592
Short name T2228
Test name
Test status
Simulation time 303904020 ps
CPU time 2.24 seconds
Started Jul 24 05:23:38 PM PDT 24
Finished Jul 24 05:23:41 PM PDT 24
Peak memory 206748 kb
Host smart-41fd002b-29cd-4f8d-a728-78e8c88a9ac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26541
18592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.2654118592
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.2145995703
Short name T1308
Test name
Test status
Simulation time 109182088755 ps
CPU time 157.53 seconds
Started Jul 24 05:23:41 PM PDT 24
Finished Jul 24 05:26:19 PM PDT 24
Peak memory 207024 kb
Host smart-81a5b59d-b1f1-4875-ae64-944945fcec36
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2145995703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.2145995703
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.1390389794
Short name T1566
Test name
Test status
Simulation time 97178333581 ps
CPU time 135.65 seconds
Started Jul 24 05:23:44 PM PDT 24
Finished Jul 24 05:26:00 PM PDT 24
Peak memory 206844 kb
Host smart-f7964c8b-15b9-4c62-a2f2-8530476c3b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390389794 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.1390389794
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.1764729820
Short name T608
Test name
Test status
Simulation time 88120438103 ps
CPU time 119.5 seconds
Started Jul 24 05:23:45 PM PDT 24
Finished Jul 24 05:25:45 PM PDT 24
Peak memory 206992 kb
Host smart-64d72de8-c452-4a55-9731-f4f0eabb5a0e
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1764729820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.1764729820
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.2954318955
Short name T1827
Test name
Test status
Simulation time 88184555023 ps
CPU time 134.44 seconds
Started Jul 24 05:24:05 PM PDT 24
Finished Jul 24 05:26:19 PM PDT 24
Peak memory 206960 kb
Host smart-0d6ad408-bf6b-4b31-80dc-fa8899047e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954318955 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.2954318955
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.3259024455
Short name T2719
Test name
Test status
Simulation time 83172932480 ps
CPU time 131.33 seconds
Started Jul 24 05:23:48 PM PDT 24
Finished Jul 24 05:25:59 PM PDT 24
Peak memory 206888 kb
Host smart-6f83bc76-2e90-4844-97db-8cfa666ab5ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32590
24455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.3259024455
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.1382608844
Short name T1301
Test name
Test status
Simulation time 195402684 ps
CPU time 0.84 seconds
Started Jul 24 05:23:43 PM PDT 24
Finished Jul 24 05:23:44 PM PDT 24
Peak memory 206560 kb
Host smart-0d1acbab-a6ba-4766-8283-a52ab14e83c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13826
08844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.1382608844
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.2327721246
Short name T2737
Test name
Test status
Simulation time 156894843 ps
CPU time 0.74 seconds
Started Jul 24 05:23:41 PM PDT 24
Finished Jul 24 05:23:42 PM PDT 24
Peak memory 206560 kb
Host smart-29a81685-1774-48db-bc3a-6da20914c0e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23277
21246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.2327721246
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.4145179304
Short name T803
Test name
Test status
Simulation time 263718686 ps
CPU time 0.92 seconds
Started Jul 24 05:23:39 PM PDT 24
Finished Jul 24 05:23:40 PM PDT 24
Peak memory 206548 kb
Host smart-1a193b16-5356-41f3-88f1-f7fef9b027ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41451
79304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.4145179304
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.1928820429
Short name T1310
Test name
Test status
Simulation time 215108221 ps
CPU time 0.91 seconds
Started Jul 24 05:23:46 PM PDT 24
Finished Jul 24 05:23:47 PM PDT 24
Peak memory 206592 kb
Host smart-5a5e6a2d-e85c-4928-bcf6-b392d51e89ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19288
20429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.1928820429
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.1545335756
Short name T60
Test name
Test status
Simulation time 464673819 ps
CPU time 1.35 seconds
Started Jul 24 05:23:48 PM PDT 24
Finished Jul 24 05:23:50 PM PDT 24
Peak memory 206588 kb
Host smart-a723a400-56d5-4808-98e9-07a8bd92cc5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15453
35756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.1545335756
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.2423201387
Short name T1993
Test name
Test status
Simulation time 23286242796 ps
CPU time 22.94 seconds
Started Jul 24 05:23:37 PM PDT 24
Finished Jul 24 05:24:00 PM PDT 24
Peak memory 206720 kb
Host smart-9de324e5-4ccd-46da-85f6-3749772e3cb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24232
01387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.2423201387
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.2990557613
Short name T544
Test name
Test status
Simulation time 3280278124 ps
CPU time 3.81 seconds
Started Jul 24 05:23:46 PM PDT 24
Finished Jul 24 05:23:50 PM PDT 24
Peak memory 206716 kb
Host smart-64128845-faa0-46ed-8b62-a9e797e18a8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29905
57613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.2990557613
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.2142623224
Short name T1048
Test name
Test status
Simulation time 8955048505 ps
CPU time 243.43 seconds
Started Jul 24 05:23:42 PM PDT 24
Finished Jul 24 05:27:46 PM PDT 24
Peak memory 206992 kb
Host smart-10f03413-9116-4f13-a78b-36719e59298a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21426
23224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.2142623224
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.4199201216
Short name T1725
Test name
Test status
Simulation time 5719682877 ps
CPU time 148.14 seconds
Started Jul 24 05:23:35 PM PDT 24
Finished Jul 24 05:26:03 PM PDT 24
Peak memory 206920 kb
Host smart-37f502c9-9d9d-49e0-b64f-5e1be5fb0b6a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4199201216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.4199201216
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.3349871954
Short name T2401
Test name
Test status
Simulation time 240775522 ps
CPU time 0.94 seconds
Started Jul 24 05:23:39 PM PDT 24
Finished Jul 24 05:23:40 PM PDT 24
Peak memory 206624 kb
Host smart-3dcc49b0-3748-4ef7-adce-bc9ee4c0f84e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3349871954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.3349871954
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.2515814641
Short name T1614
Test name
Test status
Simulation time 192929381 ps
CPU time 0.83 seconds
Started Jul 24 05:23:46 PM PDT 24
Finished Jul 24 05:23:47 PM PDT 24
Peak memory 206548 kb
Host smart-6c12e2fb-2c76-4fdc-8f93-8309354e40ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25158
14641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.2515814641
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.3738162382
Short name T1586
Test name
Test status
Simulation time 7424519618 ps
CPU time 201.97 seconds
Started Jul 24 05:23:42 PM PDT 24
Finished Jul 24 05:27:04 PM PDT 24
Peak memory 206912 kb
Host smart-1105cd0c-157d-47c4-a06d-0a74f1509616
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3738162382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.3738162382
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.2110286391
Short name T647
Test name
Test status
Simulation time 169272566 ps
CPU time 0.79 seconds
Started Jul 24 05:23:35 PM PDT 24
Finished Jul 24 05:23:36 PM PDT 24
Peak memory 206632 kb
Host smart-97f54a21-1f96-4000-8944-dd5ecf56be0a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2110286391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.2110286391
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.2044787964
Short name T541
Test name
Test status
Simulation time 145477330 ps
CPU time 0.77 seconds
Started Jul 24 05:23:39 PM PDT 24
Finished Jul 24 05:23:40 PM PDT 24
Peak memory 206516 kb
Host smart-c546c498-45ea-4e49-b8fd-20b62f915710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20447
87964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.2044787964
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.3206637704
Short name T61
Test name
Test status
Simulation time 470442998 ps
CPU time 1.3 seconds
Started Jul 24 05:23:46 PM PDT 24
Finished Jul 24 05:23:47 PM PDT 24
Peak memory 206636 kb
Host smart-48623132-83a4-4d8d-b327-c55eeb1e99d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32066
37704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.3206637704
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.3460525241
Short name T1007
Test name
Test status
Simulation time 156661533 ps
CPU time 0.79 seconds
Started Jul 24 05:23:47 PM PDT 24
Finished Jul 24 05:23:48 PM PDT 24
Peak memory 206540 kb
Host smart-7e445d6e-8a95-4c70-ad98-8e883f122bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34605
25241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.3460525241
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.2321408702
Short name T829
Test name
Test status
Simulation time 141571168 ps
CPU time 0.76 seconds
Started Jul 24 05:23:40 PM PDT 24
Finished Jul 24 05:23:41 PM PDT 24
Peak memory 206632 kb
Host smart-ec27af13-f800-4366-8f51-e6807b6679ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23214
08702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.2321408702
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.2243471153
Short name T2475
Test name
Test status
Simulation time 200026796 ps
CPU time 0.8 seconds
Started Jul 24 05:23:41 PM PDT 24
Finished Jul 24 05:23:42 PM PDT 24
Peak memory 206600 kb
Host smart-7045d410-11c0-497d-a999-e9dce84db40f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22434
71153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.2243471153
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.163989635
Short name T2123
Test name
Test status
Simulation time 205621136 ps
CPU time 0.89 seconds
Started Jul 24 05:23:33 PM PDT 24
Finished Jul 24 05:23:34 PM PDT 24
Peak memory 206548 kb
Host smart-b2b9b28f-3af0-4bbd-bac4-30dc6ee383cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16398
9635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.163989635
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.3674906909
Short name T1624
Test name
Test status
Simulation time 167005671 ps
CPU time 0.77 seconds
Started Jul 24 05:23:39 PM PDT 24
Finished Jul 24 05:23:40 PM PDT 24
Peak memory 206592 kb
Host smart-c1b04a17-e3ae-49ce-98a0-add73a52dc94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36749
06909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.3674906909
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.3012655443
Short name T2290
Test name
Test status
Simulation time 211472014 ps
CPU time 0.89 seconds
Started Jul 24 05:23:38 PM PDT 24
Finished Jul 24 05:23:39 PM PDT 24
Peak memory 206588 kb
Host smart-f847586f-77cb-4489-8562-1a62374e3b93
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3012655443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.3012655443
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.478372574
Short name T2143
Test name
Test status
Simulation time 214223020 ps
CPU time 0.92 seconds
Started Jul 24 05:23:39 PM PDT 24
Finished Jul 24 05:23:40 PM PDT 24
Peak memory 206548 kb
Host smart-1111c0b1-1dbb-47e6-b01e-b4092165b24c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47837
2574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.478372574
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.424761352
Short name T1506
Test name
Test status
Simulation time 291081778 ps
CPU time 1.01 seconds
Started Jul 24 05:23:36 PM PDT 24
Finished Jul 24 05:23:37 PM PDT 24
Peak memory 206584 kb
Host smart-7921bc36-5f5e-49e3-8dff-2b5dd40cf363
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=424761352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.424761352
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.1828971204
Short name T189
Test name
Test status
Simulation time 227758469 ps
CPU time 0.9 seconds
Started Jul 24 05:23:54 PM PDT 24
Finished Jul 24 05:23:55 PM PDT 24
Peak memory 206516 kb
Host smart-bda3b2b5-e52a-490b-9063-9f47d1bafad6
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1828971204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.1828971204
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.3688933201
Short name T2526
Test name
Test status
Simulation time 141193062 ps
CPU time 0.76 seconds
Started Jul 24 05:23:44 PM PDT 24
Finished Jul 24 05:23:45 PM PDT 24
Peak memory 206636 kb
Host smart-6324642d-75f0-4fed-b4e9-d4e9cc069005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36889
33201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.3688933201
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.2915426157
Short name T1371
Test name
Test status
Simulation time 44309115 ps
CPU time 0.69 seconds
Started Jul 24 05:23:49 PM PDT 24
Finished Jul 24 05:23:49 PM PDT 24
Peak memory 206572 kb
Host smart-0713591c-1475-4bad-a10b-46abad6f3d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29154
26157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.2915426157
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.2420027063
Short name T1281
Test name
Test status
Simulation time 10384388194 ps
CPU time 22.38 seconds
Started Jul 24 05:23:46 PM PDT 24
Finished Jul 24 05:24:14 PM PDT 24
Peak memory 215152 kb
Host smart-ee884751-05c0-47fa-83c1-a9cc5211f800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24200
27063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.2420027063
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.1005354996
Short name T801
Test name
Test status
Simulation time 155568412 ps
CPU time 0.78 seconds
Started Jul 24 05:23:45 PM PDT 24
Finished Jul 24 05:23:46 PM PDT 24
Peak memory 206592 kb
Host smart-764ac550-6ce7-468a-bacb-d2b4afc8fd81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10053
54996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.1005354996
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.2552451992
Short name T407
Test name
Test status
Simulation time 232548916 ps
CPU time 0.92 seconds
Started Jul 24 05:24:00 PM PDT 24
Finished Jul 24 05:24:01 PM PDT 24
Peak memory 206552 kb
Host smart-c9922bb5-7ccb-4466-ac2b-e4ff4308a0da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25524
51992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.2552451992
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.2988967944
Short name T769
Test name
Test status
Simulation time 15929339622 ps
CPU time 336.46 seconds
Started Jul 24 05:23:57 PM PDT 24
Finished Jul 24 05:29:34 PM PDT 24
Peak memory 206952 kb
Host smart-6c90a916-e5ae-48bd-8e30-c8e7b12f9d53
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2988967944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.2988967944
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.3628625527
Short name T1129
Test name
Test status
Simulation time 244312120 ps
CPU time 0.92 seconds
Started Jul 24 05:23:40 PM PDT 24
Finished Jul 24 05:23:41 PM PDT 24
Peak memory 206584 kb
Host smart-f30de77c-a3b1-4ae0-8e8a-1497cb3ff7c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36286
25527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.3628625527
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.1206514793
Short name T1388
Test name
Test status
Simulation time 152854214 ps
CPU time 0.78 seconds
Started Jul 24 05:23:49 PM PDT 24
Finished Jul 24 05:23:50 PM PDT 24
Peak memory 206560 kb
Host smart-8a8b2def-e793-48c5-a534-89b3ab55dd05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12065
14793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.1206514793
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.4184630425
Short name T746
Test name
Test status
Simulation time 145235580 ps
CPU time 0.78 seconds
Started Jul 24 05:23:40 PM PDT 24
Finished Jul 24 05:23:41 PM PDT 24
Peak memory 206480 kb
Host smart-752892ed-e9f0-48c7-9d47-4cc04cab7006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41846
30425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.4184630425
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.73701507
Short name T184
Test name
Test status
Simulation time 410946857 ps
CPU time 1.31 seconds
Started Jul 24 05:23:54 PM PDT 24
Finished Jul 24 05:23:56 PM PDT 24
Peak memory 225264 kb
Host smart-c06b4daf-bb42-405a-8ccf-6df39d827a2e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=73701507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.73701507
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.4278376502
Short name T1745
Test name
Test status
Simulation time 217223782 ps
CPU time 0.93 seconds
Started Jul 24 05:23:45 PM PDT 24
Finished Jul 24 05:23:46 PM PDT 24
Peak memory 206596 kb
Host smart-86b307df-b2b9-40b5-baf7-3d4042d785b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42783
76502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.4278376502
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.1833228061
Short name T1102
Test name
Test status
Simulation time 188469831 ps
CPU time 0.79 seconds
Started Jul 24 05:23:39 PM PDT 24
Finished Jul 24 05:23:40 PM PDT 24
Peak memory 206548 kb
Host smart-8661c622-17cf-40fe-9ddf-cd73d2ddf0ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18332
28061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.1833228061
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.1864137649
Short name T1378
Test name
Test status
Simulation time 217385238 ps
CPU time 0.8 seconds
Started Jul 24 05:23:51 PM PDT 24
Finished Jul 24 05:23:52 PM PDT 24
Peak memory 206528 kb
Host smart-a2e73616-7b48-4278-bf6d-e76385ca72dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18641
37649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.1864137649
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.2662525425
Short name T616
Test name
Test status
Simulation time 282283763 ps
CPU time 1.01 seconds
Started Jul 24 05:23:40 PM PDT 24
Finished Jul 24 05:23:41 PM PDT 24
Peak memory 206516 kb
Host smart-452bcddf-eba9-44a2-a4a8-266af942162c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26625
25425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.2662525425
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.1561462066
Short name T2690
Test name
Test status
Simulation time 4733080002 ps
CPU time 132.89 seconds
Started Jul 24 05:23:40 PM PDT 24
Finished Jul 24 05:25:53 PM PDT 24
Peak memory 206868 kb
Host smart-692cf81f-a396-4c4c-9b40-9a621cc41944
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1561462066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.1561462066
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.2714011068
Short name T2022
Test name
Test status
Simulation time 157238644 ps
CPU time 0.8 seconds
Started Jul 24 05:23:51 PM PDT 24
Finished Jul 24 05:23:52 PM PDT 24
Peak memory 206664 kb
Host smart-1979dd32-1cc1-450e-a1c3-287dc839f814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27140
11068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.2714011068
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.2349426953
Short name T2259
Test name
Test status
Simulation time 183382016 ps
CPU time 0.8 seconds
Started Jul 24 05:23:57 PM PDT 24
Finished Jul 24 05:23:58 PM PDT 24
Peak memory 206488 kb
Host smart-b4ac611e-fb68-47d6-9744-6925c1bbe2c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23494
26953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.2349426953
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.1121605336
Short name T1139
Test name
Test status
Simulation time 605668142 ps
CPU time 1.49 seconds
Started Jul 24 05:24:05 PM PDT 24
Finished Jul 24 05:24:07 PM PDT 24
Peak memory 206584 kb
Host smart-bc1c7f7a-b20e-4f6d-be33-77eb8a4f0a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11216
05336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.1121605336
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.3004674081
Short name T2634
Test name
Test status
Simulation time 5017835782 ps
CPU time 43.4 seconds
Started Jul 24 05:24:04 PM PDT 24
Finished Jul 24 05:24:47 PM PDT 24
Peak memory 206884 kb
Host smart-40e7f1fa-6119-41d9-bde0-eced5511ad61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30046
74081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.3004674081
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.1630839857
Short name T1717
Test name
Test status
Simulation time 44009925 ps
CPU time 0.66 seconds
Started Jul 24 05:24:00 PM PDT 24
Finished Jul 24 05:24:01 PM PDT 24
Peak memory 206452 kb
Host smart-2098c116-ee3d-4fed-83ad-3600ca912948
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1630839857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.1630839857
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.212377451
Short name T993
Test name
Test status
Simulation time 4153353192 ps
CPU time 6.04 seconds
Started Jul 24 05:23:40 PM PDT 24
Finished Jul 24 05:23:47 PM PDT 24
Peak memory 206968 kb
Host smart-24f0dca0-0071-4904-87e0-76748a6a14cb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=212377451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.212377451
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.1794190188
Short name T1859
Test name
Test status
Simulation time 13415891647 ps
CPU time 13.12 seconds
Started Jul 24 05:23:41 PM PDT 24
Finished Jul 24 05:23:54 PM PDT 24
Peak memory 206704 kb
Host smart-e8d92aab-0032-4282-a91d-3d668e2da0e7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1794190188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.1794190188
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.3123279714
Short name T2428
Test name
Test status
Simulation time 23463394735 ps
CPU time 23.01 seconds
Started Jul 24 05:23:44 PM PDT 24
Finished Jul 24 05:24:07 PM PDT 24
Peak memory 206932 kb
Host smart-932edb3c-33cf-4302-9acc-4a8f7eda4ca8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3123279714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.3123279714
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.2694183945
Short name T1015
Test name
Test status
Simulation time 155077842 ps
CPU time 0.8 seconds
Started Jul 24 05:23:42 PM PDT 24
Finished Jul 24 05:23:43 PM PDT 24
Peak memory 206596 kb
Host smart-3030ba38-723b-4623-b8b0-4ac1ddabb0db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26941
83945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.2694183945
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.1692373454
Short name T2455
Test name
Test status
Simulation time 165933382 ps
CPU time 0.79 seconds
Started Jul 24 05:23:40 PM PDT 24
Finished Jul 24 05:23:46 PM PDT 24
Peak memory 206564 kb
Host smart-d53ee65a-7bc0-49a8-af3c-4af7e8b443c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16923
73454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.1692373454
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.1429903700
Short name T1546
Test name
Test status
Simulation time 150106764 ps
CPU time 0.72 seconds
Started Jul 24 05:23:41 PM PDT 24
Finished Jul 24 05:23:42 PM PDT 24
Peak memory 206548 kb
Host smart-8bd73bca-565e-49ff-904a-2d390a6ab745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14299
03700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.1429903700
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.1669922043
Short name T1951
Test name
Test status
Simulation time 179596479 ps
CPU time 0.8 seconds
Started Jul 24 05:24:54 PM PDT 24
Finished Jul 24 05:24:55 PM PDT 24
Peak memory 206628 kb
Host smart-9744dd40-0cea-42d4-979f-a538c0658f41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16699
22043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.1669922043
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.241058508
Short name T2033
Test name
Test status
Simulation time 305515439 ps
CPU time 1.02 seconds
Started Jul 24 05:23:44 PM PDT 24
Finished Jul 24 05:23:45 PM PDT 24
Peak memory 206584 kb
Host smart-860de2a4-8624-425a-9888-3c2ae383e835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24105
8508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.241058508
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.1331665167
Short name T1923
Test name
Test status
Simulation time 22292577634 ps
CPU time 45.7 seconds
Started Jul 24 05:23:40 PM PDT 24
Finished Jul 24 05:24:26 PM PDT 24
Peak memory 206952 kb
Host smart-7004823c-54bd-48af-9914-dc2f8f36b92c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13316
65167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.1331665167
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.3867523272
Short name T1306
Test name
Test status
Simulation time 428338956 ps
CPU time 1.24 seconds
Started Jul 24 05:23:56 PM PDT 24
Finished Jul 24 05:23:58 PM PDT 24
Peak memory 206604 kb
Host smart-51cc84dd-cc8e-461f-8f59-21669b8a84ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38675
23272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.3867523272
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.1003826402
Short name T2747
Test name
Test status
Simulation time 149517939 ps
CPU time 0.73 seconds
Started Jul 24 05:23:43 PM PDT 24
Finished Jul 24 05:23:44 PM PDT 24
Peak memory 206580 kb
Host smart-f62814a8-6d8c-4ff8-8e0e-15d6bf8c090c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10038
26402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.1003826402
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.2989977793
Short name T449
Test name
Test status
Simulation time 32237493 ps
CPU time 0.67 seconds
Started Jul 24 05:23:46 PM PDT 24
Finished Jul 24 05:23:47 PM PDT 24
Peak memory 206576 kb
Host smart-7aa57318-c2b1-4dc8-9245-881cface22b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29899
77793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.2989977793
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.2421416784
Short name T319
Test name
Test status
Simulation time 760554202 ps
CPU time 1.78 seconds
Started Jul 24 05:24:03 PM PDT 24
Finished Jul 24 05:24:05 PM PDT 24
Peak memory 206832 kb
Host smart-7e554aef-9262-428d-a2e1-9896b5a5479b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24214
16784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.2421416784
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.3598744217
Short name T813
Test name
Test status
Simulation time 271403229 ps
CPU time 1.99 seconds
Started Jul 24 05:23:38 PM PDT 24
Finished Jul 24 05:23:40 PM PDT 24
Peak memory 206716 kb
Host smart-ccf0846e-052d-4825-b629-14f49f4ae499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35987
44217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.3598744217
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.2820144530
Short name T981
Test name
Test status
Simulation time 89173636707 ps
CPU time 123.65 seconds
Started Jul 24 05:23:47 PM PDT 24
Finished Jul 24 05:25:50 PM PDT 24
Peak memory 206976 kb
Host smart-991aa99b-e6ba-4940-8e4b-3acbdffd8f31
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2820144530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.2820144530
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.4217097659
Short name T2089
Test name
Test status
Simulation time 101420863966 ps
CPU time 148.88 seconds
Started Jul 24 05:24:04 PM PDT 24
Finished Jul 24 05:26:33 PM PDT 24
Peak memory 206908 kb
Host smart-fd11baff-4af1-456b-9c54-1d248775213a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217097659 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.4217097659
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.3442765618
Short name T490
Test name
Test status
Simulation time 109136296544 ps
CPU time 141.84 seconds
Started Jul 24 05:23:45 PM PDT 24
Finished Jul 24 05:26:07 PM PDT 24
Peak memory 206944 kb
Host smart-dab746b9-b595-44fb-bb2b-19ced822d82e
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3442765618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.3442765618
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.133665006
Short name T595
Test name
Test status
Simulation time 82248100843 ps
CPU time 116.73 seconds
Started Jul 24 05:24:03 PM PDT 24
Finished Jul 24 05:26:00 PM PDT 24
Peak memory 206948 kb
Host smart-0655c15d-a163-4d00-abc3-154422fde2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133665006 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.133665006
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.1110631956
Short name T2267
Test name
Test status
Simulation time 121185687552 ps
CPU time 176.63 seconds
Started Jul 24 05:23:45 PM PDT 24
Finished Jul 24 05:26:42 PM PDT 24
Peak memory 206908 kb
Host smart-6e4b1122-c42f-4468-a378-0a0b88fc5c50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11106
31956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.1110631956
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.2570609719
Short name T1791
Test name
Test status
Simulation time 225849676 ps
CPU time 0.89 seconds
Started Jul 24 05:23:58 PM PDT 24
Finished Jul 24 05:23:59 PM PDT 24
Peak memory 206540 kb
Host smart-a637c893-f6d4-441b-a365-ab962ad3e49c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25706
09719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.2570609719
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.584404292
Short name T1654
Test name
Test status
Simulation time 148241832 ps
CPU time 0.76 seconds
Started Jul 24 05:24:06 PM PDT 24
Finished Jul 24 05:24:06 PM PDT 24
Peak memory 206540 kb
Host smart-604169bb-3fd1-405e-a832-23c7e1d796f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58440
4292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.584404292
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.2216610507
Short name T2553
Test name
Test status
Simulation time 209321689 ps
CPU time 0.87 seconds
Started Jul 24 05:23:53 PM PDT 24
Finished Jul 24 05:23:54 PM PDT 24
Peak memory 206548 kb
Host smart-62c5d7ac-004d-485a-9e8b-5563894645e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22166
10507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.2216610507
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.875039837
Short name T2330
Test name
Test status
Simulation time 8130741496 ps
CPU time 77.64 seconds
Started Jul 24 05:23:55 PM PDT 24
Finished Jul 24 05:25:13 PM PDT 24
Peak memory 206936 kb
Host smart-eca4d326-734b-46de-9703-218de773399b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=875039837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.875039837
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_iso_retraction.432028648
Short name T614
Test name
Test status
Simulation time 3313131398 ps
CPU time 27.82 seconds
Started Jul 24 05:23:56 PM PDT 24
Finished Jul 24 05:24:24 PM PDT 24
Peak memory 205956 kb
Host smart-3d9d3664-b93d-4718-a9fc-2eb4638ed8c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43202
8648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.432028648
Directory /workspace/1.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.2618826935
Short name T2427
Test name
Test status
Simulation time 190955589 ps
CPU time 0.86 seconds
Started Jul 24 05:24:02 PM PDT 24
Finished Jul 24 05:24:03 PM PDT 24
Peak memory 206532 kb
Host smart-8a1655be-785d-4a0f-8561-1787a6cb65de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26188
26935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.2618826935
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.2957847463
Short name T2617
Test name
Test status
Simulation time 23284258418 ps
CPU time 22.54 seconds
Started Jul 24 05:23:56 PM PDT 24
Finished Jul 24 05:24:18 PM PDT 24
Peak memory 205876 kb
Host smart-8944dbb4-1ffd-4400-a02c-51beccc989ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29578
47463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.2957847463
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.4128652197
Short name T841
Test name
Test status
Simulation time 3306078263 ps
CPU time 4.07 seconds
Started Jul 24 05:23:47 PM PDT 24
Finished Jul 24 05:23:51 PM PDT 24
Peak memory 206704 kb
Host smart-e3a59096-5986-4fc5-a41e-2f0ea603cd90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41286
52197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.4128652197
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.2287372902
Short name T1668
Test name
Test status
Simulation time 10752630976 ps
CPU time 75.53 seconds
Started Jul 24 05:23:56 PM PDT 24
Finished Jul 24 05:25:12 PM PDT 24
Peak memory 206920 kb
Host smart-67bd9589-3c67-4b6f-94cd-2d38dee3de59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22873
72902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.2287372902
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.859140588
Short name T1488
Test name
Test status
Simulation time 4906214590 ps
CPU time 134.02 seconds
Started Jul 24 05:23:58 PM PDT 24
Finished Jul 24 05:26:12 PM PDT 24
Peak memory 206860 kb
Host smart-483b11a6-8fb9-480c-8b0e-d74cbacc1a98
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=859140588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.859140588
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.4267512203
Short name T702
Test name
Test status
Simulation time 236570231 ps
CPU time 0.87 seconds
Started Jul 24 05:23:46 PM PDT 24
Finished Jul 24 05:23:47 PM PDT 24
Peak memory 206584 kb
Host smart-a8448349-9b49-4bbc-8c4e-51a085261852
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4267512203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.4267512203
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.267447514
Short name T2318
Test name
Test status
Simulation time 188956342 ps
CPU time 0.85 seconds
Started Jul 24 05:24:01 PM PDT 24
Finished Jul 24 05:24:02 PM PDT 24
Peak memory 206656 kb
Host smart-1204c6e8-ad07-47b3-8324-8008b18d727f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26744
7514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.267447514
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.201570631
Short name T2609
Test name
Test status
Simulation time 4518128537 ps
CPU time 40.79 seconds
Started Jul 24 05:23:47 PM PDT 24
Finished Jul 24 05:24:27 PM PDT 24
Peak memory 206956 kb
Host smart-872ec661-2b05-459a-b647-641045db3299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20157
0631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.201570631
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.4292269083
Short name T2053
Test name
Test status
Simulation time 3548110408 ps
CPU time 89.03 seconds
Started Jul 24 05:23:40 PM PDT 24
Finished Jul 24 05:25:09 PM PDT 24
Peak memory 206956 kb
Host smart-8788af3c-9928-43d3-86bc-f364d2bdf504
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4292269083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.4292269083
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.1182737283
Short name T437
Test name
Test status
Simulation time 169086235 ps
CPU time 0.78 seconds
Started Jul 24 05:24:02 PM PDT 24
Finished Jul 24 05:24:03 PM PDT 24
Peak memory 206580 kb
Host smart-e3a8324a-4060-4537-954f-4c542de9b76a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1182737283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.1182737283
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.2225780732
Short name T2529
Test name
Test status
Simulation time 139293197 ps
CPU time 0.72 seconds
Started Jul 24 05:23:51 PM PDT 24
Finished Jul 24 05:23:52 PM PDT 24
Peak memory 206628 kb
Host smart-8c11db31-9fef-4d2f-8bc7-ea836614c865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22257
80732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.2225780732
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.3171999036
Short name T1980
Test name
Test status
Simulation time 161894683 ps
CPU time 0.77 seconds
Started Jul 24 05:23:56 PM PDT 24
Finished Jul 24 05:23:57 PM PDT 24
Peak memory 206532 kb
Host smart-21d0e65b-5b92-4222-8e06-2e940f7c5577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31719
99036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.3171999036
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.3572851347
Short name T1722
Test name
Test status
Simulation time 181154717 ps
CPU time 0.82 seconds
Started Jul 24 05:23:57 PM PDT 24
Finished Jul 24 05:23:58 PM PDT 24
Peak memory 206572 kb
Host smart-172b9b22-8dec-49eb-bef3-54acec6ca7dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35728
51347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.3572851347
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.771890744
Short name T482
Test name
Test status
Simulation time 170065295 ps
CPU time 0.8 seconds
Started Jul 24 05:24:27 PM PDT 24
Finished Jul 24 05:24:28 PM PDT 24
Peak memory 206488 kb
Host smart-208b4071-3cff-492d-ae36-f4d684a4c6fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77189
0744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.771890744
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.2138007883
Short name T1300
Test name
Test status
Simulation time 154679941 ps
CPU time 0.73 seconds
Started Jul 24 05:23:45 PM PDT 24
Finished Jul 24 05:23:46 PM PDT 24
Peak memory 206564 kb
Host smart-8c459669-4363-4325-b017-905713215528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21380
07883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.2138007883
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.1805209636
Short name T1860
Test name
Test status
Simulation time 209339689 ps
CPU time 0.87 seconds
Started Jul 24 05:23:47 PM PDT 24
Finished Jul 24 05:23:48 PM PDT 24
Peak memory 206604 kb
Host smart-81415801-ef16-4a67-b7e8-0ab13c60fbe3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1805209636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.1805209636
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.3960939939
Short name T2178
Test name
Test status
Simulation time 238303343 ps
CPU time 0.96 seconds
Started Jul 24 05:23:57 PM PDT 24
Finished Jul 24 05:23:58 PM PDT 24
Peak memory 206584 kb
Host smart-b49ebce9-3f3e-4c2d-8915-3286cb0681cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39609
39939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.3960939939
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.601080200
Short name T929
Test name
Test status
Simulation time 144298861 ps
CPU time 0.72 seconds
Started Jul 24 05:23:48 PM PDT 24
Finished Jul 24 05:23:49 PM PDT 24
Peak memory 206600 kb
Host smart-9180174f-0535-4bd8-9e3f-bd3e398b7c8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60108
0200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.601080200
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.3390383959
Short name T933
Test name
Test status
Simulation time 59670738 ps
CPU time 0.64 seconds
Started Jul 24 05:23:49 PM PDT 24
Finished Jul 24 05:23:49 PM PDT 24
Peak memory 206380 kb
Host smart-270dd664-b6b3-4f05-a3e6-c99ce2334a81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33903
83959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.3390383959
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.2879772489
Short name T2437
Test name
Test status
Simulation time 16276646646 ps
CPU time 36.59 seconds
Started Jul 24 05:23:44 PM PDT 24
Finished Jul 24 05:24:21 PM PDT 24
Peak memory 215196 kb
Host smart-2799cd2d-4e68-47f4-9e64-38c3b226dcf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28797
72489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.2879772489
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.1392969108
Short name T2377
Test name
Test status
Simulation time 235830163 ps
CPU time 0.84 seconds
Started Jul 24 05:24:06 PM PDT 24
Finished Jul 24 05:24:07 PM PDT 24
Peak memory 206596 kb
Host smart-40694072-5560-4fe3-a913-38ef3cecf76b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13929
69108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.1392969108
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.3090120252
Short name T487
Test name
Test status
Simulation time 214813482 ps
CPU time 0.89 seconds
Started Jul 24 05:23:53 PM PDT 24
Finished Jul 24 05:23:54 PM PDT 24
Peak memory 206600 kb
Host smart-e9df3c58-a2fe-4301-be27-b3a3d560be96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30901
20252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.3090120252
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.468023122
Short name T1111
Test name
Test status
Simulation time 7863922459 ps
CPU time 124.21 seconds
Started Jul 24 05:23:47 PM PDT 24
Finished Jul 24 05:25:51 PM PDT 24
Peak memory 206836 kb
Host smart-59abcd64-206f-4aba-8d4d-773502354de6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=468023122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.468023122
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.3340637483
Short name T718
Test name
Test status
Simulation time 12125468854 ps
CPU time 81.73 seconds
Started Jul 24 05:23:55 PM PDT 24
Finished Jul 24 05:25:17 PM PDT 24
Peak memory 206992 kb
Host smart-982d6f5e-5db6-4028-950d-00eaf0b89dab
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3340637483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.3340637483
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.2738809936
Short name T1073
Test name
Test status
Simulation time 189026293 ps
CPU time 0.83 seconds
Started Jul 24 05:23:56 PM PDT 24
Finished Jul 24 05:23:57 PM PDT 24
Peak memory 206776 kb
Host smart-5f09a819-4aac-495a-bc92-6885b3adc67d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27388
09936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.2738809936
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.2189679053
Short name T2540
Test name
Test status
Simulation time 206712174 ps
CPU time 0.81 seconds
Started Jul 24 05:23:48 PM PDT 24
Finished Jul 24 05:23:49 PM PDT 24
Peak memory 206532 kb
Host smart-6f309414-0f2b-4b7c-b11b-2605290ac1ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21896
79053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.2189679053
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.3165708960
Short name T1313
Test name
Test status
Simulation time 145624779 ps
CPU time 0.78 seconds
Started Jul 24 05:24:04 PM PDT 24
Finished Jul 24 05:24:05 PM PDT 24
Peak memory 206492 kb
Host smart-13006276-6041-4f16-be60-141e4e37c869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31657
08960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.3165708960
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.122794243
Short name T70
Test name
Test status
Simulation time 157687585 ps
CPU time 0.77 seconds
Started Jul 24 05:23:55 PM PDT 24
Finished Jul 24 05:23:56 PM PDT 24
Peak memory 206572 kb
Host smart-38d05e2d-450f-40db-901a-c6158e95deaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12279
4243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.122794243
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.384500528
Short name T198
Test name
Test status
Simulation time 728287977 ps
CPU time 1.49 seconds
Started Jul 24 05:23:50 PM PDT 24
Finished Jul 24 05:23:52 PM PDT 24
Peak memory 224332 kb
Host smart-ce0a1e77-e9bd-430c-90c8-efdbefaf4cc3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=384500528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.384500528
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.2217233834
Short name T47
Test name
Test status
Simulation time 493257393 ps
CPU time 1.42 seconds
Started Jul 24 05:24:05 PM PDT 24
Finished Jul 24 05:24:07 PM PDT 24
Peak memory 206652 kb
Host smart-93f50f7f-0118-4c34-b59e-876389f5381a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22172
33834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.2217233834
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.236696017
Short name T1744
Test name
Test status
Simulation time 218464496 ps
CPU time 0.94 seconds
Started Jul 24 05:23:55 PM PDT 24
Finished Jul 24 05:23:56 PM PDT 24
Peak memory 206588 kb
Host smart-798d6631-4efd-4775-bdca-3d5a3ab2fd39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23669
6017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.236696017
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.3769640798
Short name T1345
Test name
Test status
Simulation time 150126123 ps
CPU time 0.75 seconds
Started Jul 24 05:23:46 PM PDT 24
Finished Jul 24 05:23:51 PM PDT 24
Peak memory 206556 kb
Host smart-ba0bce47-8966-46f2-af9e-fe7e0e124d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37696
40798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.3769640798
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.1855179863
Short name T2651
Test name
Test status
Simulation time 155223885 ps
CPU time 0.75 seconds
Started Jul 24 05:23:49 PM PDT 24
Finished Jul 24 05:23:50 PM PDT 24
Peak memory 206388 kb
Host smart-45201553-b671-40e7-a70c-ec6281dcb190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18551
79863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.1855179863
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.937712831
Short name T1220
Test name
Test status
Simulation time 178632177 ps
CPU time 0.87 seconds
Started Jul 24 05:23:45 PM PDT 24
Finished Jul 24 05:23:51 PM PDT 24
Peak memory 206600 kb
Host smart-5f0a978d-92a0-48f2-a3de-15e90a61779d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93771
2831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.937712831
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.3518010692
Short name T2570
Test name
Test status
Simulation time 4039048020 ps
CPU time 38.63 seconds
Started Jul 24 05:23:46 PM PDT 24
Finished Jul 24 05:24:24 PM PDT 24
Peak memory 206968 kb
Host smart-efdd9cb2-c370-4c16-9107-d345b427642e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3518010692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.3518010692
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.1084088756
Short name T986
Test name
Test status
Simulation time 174833456 ps
CPU time 0.79 seconds
Started Jul 24 05:23:54 PM PDT 24
Finished Jul 24 05:23:55 PM PDT 24
Peak memory 206580 kb
Host smart-91ae7303-1642-4f50-a52b-cad9869856bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10840
88756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.1084088756
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.3315220808
Short name T2132
Test name
Test status
Simulation time 168386810 ps
CPU time 0.76 seconds
Started Jul 24 05:23:50 PM PDT 24
Finished Jul 24 05:23:51 PM PDT 24
Peak memory 206592 kb
Host smart-bd4769b5-7d54-4044-af78-b221f2ae0184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33152
20808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.3315220808
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.3063045807
Short name T1113
Test name
Test status
Simulation time 530536983 ps
CPU time 1.4 seconds
Started Jul 24 05:23:44 PM PDT 24
Finished Jul 24 05:23:46 PM PDT 24
Peak memory 206576 kb
Host smart-526af5ea-23d0-4435-bd6b-233d3537f1a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30630
45807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.3063045807
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.2578319516
Short name T1991
Test name
Test status
Simulation time 4056119408 ps
CPU time 28.57 seconds
Started Jul 24 05:23:54 PM PDT 24
Finished Jul 24 05:24:23 PM PDT 24
Peak memory 206748 kb
Host smart-4948a1ee-9777-438f-9d12-68c26f82c992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25783
19516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.2578319516
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.699786843
Short name T1995
Test name
Test status
Simulation time 38502571 ps
CPU time 0.69 seconds
Started Jul 24 05:25:18 PM PDT 24
Finished Jul 24 05:25:19 PM PDT 24
Peak memory 206624 kb
Host smart-9b5e205c-4025-463e-8362-6e1198b2b8e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=699786843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.699786843
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.1305285714
Short name T1593
Test name
Test status
Simulation time 4381244030 ps
CPU time 5.65 seconds
Started Jul 24 05:25:06 PM PDT 24
Finished Jul 24 05:25:12 PM PDT 24
Peak memory 206768 kb
Host smart-c95e99a0-7f54-49c6-9e3b-2e64f5cec150
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1305285714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.1305285714
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.3242050130
Short name T2577
Test name
Test status
Simulation time 13389272113 ps
CPU time 11.59 seconds
Started Jul 24 05:25:07 PM PDT 24
Finished Jul 24 05:25:19 PM PDT 24
Peak memory 206888 kb
Host smart-dbac84c3-c8fc-4262-804a-a0f4b91b9dde
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3242050130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.3242050130
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.1427624240
Short name T1242
Test name
Test status
Simulation time 23383280498 ps
CPU time 25.75 seconds
Started Jul 24 05:25:12 PM PDT 24
Finished Jul 24 05:25:38 PM PDT 24
Peak memory 206728 kb
Host smart-f0bcaa4f-1219-4f01-ba73-f75431a1cd3f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1427624240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.1427624240
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.1788689778
Short name T2056
Test name
Test status
Simulation time 183319625 ps
CPU time 0.83 seconds
Started Jul 24 05:25:08 PM PDT 24
Finished Jul 24 05:25:09 PM PDT 24
Peak memory 206640 kb
Host smart-8b8f6b16-f39b-461f-9f7a-9987a6cbb3f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17886
89778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.1788689778
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.1978401489
Short name T1117
Test name
Test status
Simulation time 140991025 ps
CPU time 0.77 seconds
Started Jul 24 05:25:12 PM PDT 24
Finished Jul 24 05:25:13 PM PDT 24
Peak memory 206528 kb
Host smart-94c93db0-8f44-4ba4-8abb-e14f225f30f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19784
01489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.1978401489
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.1763253694
Short name T1052
Test name
Test status
Simulation time 186499821 ps
CPU time 0.97 seconds
Started Jul 24 05:25:01 PM PDT 24
Finished Jul 24 05:25:02 PM PDT 24
Peak memory 206576 kb
Host smart-58c735f7-767f-45e0-9074-92a89a78a6b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17632
53694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.1763253694
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.257769524
Short name T2115
Test name
Test status
Simulation time 1094785969 ps
CPU time 2.35 seconds
Started Jul 24 05:25:05 PM PDT 24
Finished Jul 24 05:25:08 PM PDT 24
Peak memory 206840 kb
Host smart-0635fcfd-8ae5-4b02-84c0-898457506a20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25776
9524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.257769524
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.3947159238
Short name T2397
Test name
Test status
Simulation time 20022531645 ps
CPU time 40.57 seconds
Started Jul 24 05:25:09 PM PDT 24
Finished Jul 24 05:25:50 PM PDT 24
Peak memory 206824 kb
Host smart-0a1f574f-8f30-4be2-8ef9-4e6b1f141b1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39471
59238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.3947159238
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.2842425948
Short name T2255
Test name
Test status
Simulation time 363337320 ps
CPU time 1.24 seconds
Started Jul 24 05:25:10 PM PDT 24
Finished Jul 24 05:25:11 PM PDT 24
Peak memory 206552 kb
Host smart-272b2de1-9989-4ab4-ac09-2a98dbe72a99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28424
25948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.2842425948
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.2558335879
Short name T1055
Test name
Test status
Simulation time 172662204 ps
CPU time 0.79 seconds
Started Jul 24 05:25:10 PM PDT 24
Finished Jul 24 05:25:11 PM PDT 24
Peak memory 206576 kb
Host smart-c5ee4bb3-7bac-40b2-a9f6-98fc12b4ff53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25583
35879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.2558335879
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.1012044186
Short name T1629
Test name
Test status
Simulation time 29005522 ps
CPU time 0.71 seconds
Started Jul 24 05:25:12 PM PDT 24
Finished Jul 24 05:25:13 PM PDT 24
Peak memory 206592 kb
Host smart-f6cbbb4d-01a1-44c8-9018-d0c7c937fc52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10120
44186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.1012044186
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.3324250285
Short name T357
Test name
Test status
Simulation time 918473814 ps
CPU time 2.1 seconds
Started Jul 24 05:25:10 PM PDT 24
Finished Jul 24 05:25:13 PM PDT 24
Peak memory 206784 kb
Host smart-6a106b3b-aeec-444c-a3fd-533458924197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33242
50285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.3324250285
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.3103432823
Short name T759
Test name
Test status
Simulation time 223841683 ps
CPU time 0.82 seconds
Started Jul 24 05:25:11 PM PDT 24
Finished Jul 24 05:25:12 PM PDT 24
Peak memory 206600 kb
Host smart-58371d6e-eb5d-4684-a0cb-916e708d1478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31034
32823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.3103432823
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.1310101078
Short name T426
Test name
Test status
Simulation time 138246101 ps
CPU time 0.73 seconds
Started Jul 24 05:25:10 PM PDT 24
Finished Jul 24 05:25:11 PM PDT 24
Peak memory 206072 kb
Host smart-30ec783a-209c-4d6c-962d-719c69cf57fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13101
01078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.1310101078
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.1075043889
Short name T202
Test name
Test status
Simulation time 162729057 ps
CPU time 0.78 seconds
Started Jul 24 05:25:10 PM PDT 24
Finished Jul 24 05:25:11 PM PDT 24
Peak memory 206384 kb
Host smart-a36279ee-9aa9-4202-ae98-1cd585781d1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10750
43889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.1075043889
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_invalid_sync.1964792916
Short name T66
Test name
Test status
Simulation time 8399157782 ps
CPU time 239.51 seconds
Started Jul 24 05:25:11 PM PDT 24
Finished Jul 24 05:29:11 PM PDT 24
Peak memory 206968 kb
Host smart-c546bf32-d41a-43a5-aa30-755724891158
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1964792916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.1964792916
Directory /workspace/10.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_iso_retraction.2264851081
Short name T2157
Test name
Test status
Simulation time 8346068348 ps
CPU time 66.06 seconds
Started Jul 24 05:25:13 PM PDT 24
Finished Jul 24 05:26:19 PM PDT 24
Peak memory 206852 kb
Host smart-2208c204-5957-4995-8781-2f4ae45a5d3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22648
51081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.2264851081
Directory /workspace/10.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.3606070617
Short name T516
Test name
Test status
Simulation time 219719465 ps
CPU time 0.88 seconds
Started Jul 24 05:25:04 PM PDT 24
Finished Jul 24 05:25:05 PM PDT 24
Peak memory 206580 kb
Host smart-9579fd8c-8db1-4480-92c1-6492f055fa74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36060
70617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.3606070617
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.3106121092
Short name T914
Test name
Test status
Simulation time 23337737366 ps
CPU time 26.13 seconds
Started Jul 24 05:25:19 PM PDT 24
Finished Jul 24 05:25:46 PM PDT 24
Peak memory 206668 kb
Host smart-c008f173-9fb1-4a58-8afe-7fd23dfd6804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31061
21092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.3106121092
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.1747385253
Short name T1825
Test name
Test status
Simulation time 3327928387 ps
CPU time 4.22 seconds
Started Jul 24 05:25:10 PM PDT 24
Finished Jul 24 05:25:14 PM PDT 24
Peak memory 206676 kb
Host smart-d01b56f6-e029-4942-bd7f-6cd799be402b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17473
85253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.1747385253
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.493853935
Short name T530
Test name
Test status
Simulation time 8663653352 ps
CPU time 81.5 seconds
Started Jul 24 05:25:03 PM PDT 24
Finished Jul 24 05:26:25 PM PDT 24
Peak memory 206968 kb
Host smart-1ed01cec-007b-4dc8-8b4d-b0e1b085a172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49385
3935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.493853935
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.325763115
Short name T388
Test name
Test status
Simulation time 4998782304 ps
CPU time 142.04 seconds
Started Jul 24 05:25:03 PM PDT 24
Finished Jul 24 05:27:26 PM PDT 24
Peak memory 206900 kb
Host smart-e51ac32f-0766-4347-9f76-97df242ca304
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=325763115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.325763115
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.1132403368
Short name T1684
Test name
Test status
Simulation time 247743311 ps
CPU time 0.91 seconds
Started Jul 24 05:25:19 PM PDT 24
Finished Jul 24 05:25:20 PM PDT 24
Peak memory 206624 kb
Host smart-07818fd9-a60e-4859-8608-ace2d262ad91
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1132403368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.1132403368
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.3070884117
Short name T379
Test name
Test status
Simulation time 221916386 ps
CPU time 0.87 seconds
Started Jul 24 05:25:21 PM PDT 24
Finished Jul 24 05:25:22 PM PDT 24
Peak memory 206616 kb
Host smart-b90f39af-e903-4b00-accc-5c6b92e6cb28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30708
84117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.3070884117
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.2688702407
Short name T1536
Test name
Test status
Simulation time 7111160701 ps
CPU time 49.91 seconds
Started Jul 24 05:25:16 PM PDT 24
Finished Jul 24 05:26:06 PM PDT 24
Peak memory 207012 kb
Host smart-914bbe9c-08da-4eb7-888c-69bbcfe5d2e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26887
02407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.2688702407
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.1135720898
Short name T2045
Test name
Test status
Simulation time 7824637893 ps
CPU time 55.85 seconds
Started Jul 24 05:25:15 PM PDT 24
Finished Jul 24 05:26:11 PM PDT 24
Peak memory 206976 kb
Host smart-bd2db562-1431-4658-b9dd-7aac69c67065
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1135720898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.1135720898
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.669108076
Short name T2606
Test name
Test status
Simulation time 168019877 ps
CPU time 0.81 seconds
Started Jul 24 05:25:11 PM PDT 24
Finished Jul 24 05:25:13 PM PDT 24
Peak memory 206608 kb
Host smart-d6317747-fc39-4b65-8618-e6da307f2784
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=669108076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.669108076
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.329333359
Short name T1362
Test name
Test status
Simulation time 208871214 ps
CPU time 0.87 seconds
Started Jul 24 05:25:21 PM PDT 24
Finished Jul 24 05:25:22 PM PDT 24
Peak memory 206516 kb
Host smart-874b4213-2071-439a-b408-321ea80a10fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32933
3359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.329333359
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.1886285617
Short name T1992
Test name
Test status
Simulation time 179394900 ps
CPU time 0.82 seconds
Started Jul 24 05:25:07 PM PDT 24
Finished Jul 24 05:25:09 PM PDT 24
Peak memory 206468 kb
Host smart-cd5d8931-0212-4a09-a0cf-6feab88278b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18862
85617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.1886285617
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.3317570674
Short name T2692
Test name
Test status
Simulation time 142612510 ps
CPU time 0.8 seconds
Started Jul 24 05:25:14 PM PDT 24
Finished Jul 24 05:25:15 PM PDT 24
Peak memory 206396 kb
Host smart-4f59b98f-ffc5-43bb-ad27-1bb3a2490327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33175
70674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.3317570674
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.4193277142
Short name T545
Test name
Test status
Simulation time 184328325 ps
CPU time 0.8 seconds
Started Jul 24 05:25:12 PM PDT 24
Finished Jul 24 05:25:13 PM PDT 24
Peak memory 206548 kb
Host smart-6076db12-f803-413d-8122-2112dba29945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41932
77142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.4193277142
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.1428225172
Short name T1908
Test name
Test status
Simulation time 169847677 ps
CPU time 0.79 seconds
Started Jul 24 05:25:05 PM PDT 24
Finished Jul 24 05:25:06 PM PDT 24
Peak memory 206504 kb
Host smart-6bf909ff-79a4-43eb-9f05-4bf6e929dba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14282
25172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.1428225172
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.4198473850
Short name T878
Test name
Test status
Simulation time 224209325 ps
CPU time 0.93 seconds
Started Jul 24 05:25:11 PM PDT 24
Finished Jul 24 05:25:12 PM PDT 24
Peak memory 206568 kb
Host smart-9a8d6ce6-bff4-48b8-8381-ebc658428b78
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4198473850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.4198473850
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.1941837580
Short name T573
Test name
Test status
Simulation time 148240837 ps
CPU time 0.76 seconds
Started Jul 24 05:25:06 PM PDT 24
Finished Jul 24 05:25:07 PM PDT 24
Peak memory 206572 kb
Host smart-cb56dba1-be6b-40da-b1bf-9db8ac4db164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19418
37580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.1941837580
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.3861349595
Short name T2386
Test name
Test status
Simulation time 29949079 ps
CPU time 0.62 seconds
Started Jul 24 05:25:06 PM PDT 24
Finished Jul 24 05:25:07 PM PDT 24
Peak memory 206588 kb
Host smart-08329e06-9ef7-4aff-a511-50554e3df340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38613
49595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.3861349595
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.3515304905
Short name T2729
Test name
Test status
Simulation time 18279403221 ps
CPU time 42.22 seconds
Started Jul 24 05:25:36 PM PDT 24
Finished Jul 24 05:26:19 PM PDT 24
Peak memory 206992 kb
Host smart-f4cd237b-fc4a-41fb-b4d4-41f5b02af3a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35153
04905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.3515304905
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.2916115174
Short name T1162
Test name
Test status
Simulation time 220550047 ps
CPU time 0.84 seconds
Started Jul 24 05:25:15 PM PDT 24
Finished Jul 24 05:25:16 PM PDT 24
Peak memory 206544 kb
Host smart-36a70533-96c0-48e2-9b00-d7732a018770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29161
15174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.2916115174
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.3999848292
Short name T2176
Test name
Test status
Simulation time 226536789 ps
CPU time 0.87 seconds
Started Jul 24 05:25:11 PM PDT 24
Finished Jul 24 05:25:12 PM PDT 24
Peak memory 206544 kb
Host smart-81370194-8295-4b3f-aec8-76de55d732b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39998
48292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.3999848292
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.2117994354
Short name T1214
Test name
Test status
Simulation time 247249721 ps
CPU time 0.87 seconds
Started Jul 24 05:27:27 PM PDT 24
Finished Jul 24 05:27:28 PM PDT 24
Peak memory 206568 kb
Host smart-2516737e-2687-4d33-9e2f-66fcd2b64805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21179
94354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.2117994354
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.1317653755
Short name T2008
Test name
Test status
Simulation time 187731369 ps
CPU time 0.77 seconds
Started Jul 24 05:25:15 PM PDT 24
Finished Jul 24 05:25:16 PM PDT 24
Peak memory 206608 kb
Host smart-40edcb56-9a11-40ec-844f-16493bb6ce46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13176
53755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.1317653755
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.1340607234
Short name T1932
Test name
Test status
Simulation time 132212648 ps
CPU time 0.71 seconds
Started Jul 24 05:25:19 PM PDT 24
Finished Jul 24 05:25:20 PM PDT 24
Peak memory 206528 kb
Host smart-74ad9add-dfc9-4c31-a283-2b1a5ada64eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13406
07234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.1340607234
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.3892674708
Short name T1478
Test name
Test status
Simulation time 154882326 ps
CPU time 0.8 seconds
Started Jul 24 05:25:20 PM PDT 24
Finished Jul 24 05:25:21 PM PDT 24
Peak memory 206564 kb
Host smart-f9575ce0-693a-4066-828f-d05b4f4317ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38926
74708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.3892674708
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.969796481
Short name T1534
Test name
Test status
Simulation time 190957401 ps
CPU time 0.77 seconds
Started Jul 24 05:25:17 PM PDT 24
Finished Jul 24 05:25:17 PM PDT 24
Peak memory 206640 kb
Host smart-2c1b12c8-c5b5-4b89-888e-b8ab7c424988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96979
6481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.969796481
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.3738813459
Short name T2196
Test name
Test status
Simulation time 248929607 ps
CPU time 1 seconds
Started Jul 24 05:25:18 PM PDT 24
Finished Jul 24 05:25:19 PM PDT 24
Peak memory 206600 kb
Host smart-cece3d72-627e-489e-96cf-538aac91da14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37388
13459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.3738813459
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.1705112349
Short name T335
Test name
Test status
Simulation time 6126946629 ps
CPU time 173.18 seconds
Started Jul 24 05:25:07 PM PDT 24
Finished Jul 24 05:28:00 PM PDT 24
Peak memory 206968 kb
Host smart-643a3fc4-2fb1-4b1d-8836-dbe0e8e14a4b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1705112349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.1705112349
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.1686961149
Short name T1202
Test name
Test status
Simulation time 164227249 ps
CPU time 0.79 seconds
Started Jul 24 05:25:06 PM PDT 24
Finished Jul 24 05:25:07 PM PDT 24
Peak memory 206584 kb
Host smart-96513f37-51d5-4f86-9166-8f2ce0381a16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16869
61149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.1686961149
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.4135752335
Short name T895
Test name
Test status
Simulation time 154014160 ps
CPU time 0.79 seconds
Started Jul 24 05:25:12 PM PDT 24
Finished Jul 24 05:25:13 PM PDT 24
Peak memory 206660 kb
Host smart-67a9c397-b670-4af2-84fe-98d7a4a6045c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41357
52335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.4135752335
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.3291803532
Short name T2472
Test name
Test status
Simulation time 683109582 ps
CPU time 1.74 seconds
Started Jul 24 05:25:16 PM PDT 24
Finished Jul 24 05:25:18 PM PDT 24
Peak memory 206544 kb
Host smart-924f402b-556e-4a78-8625-0415a344e46b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32918
03532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.3291803532
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.2778310542
Short name T564
Test name
Test status
Simulation time 4749220102 ps
CPU time 33.72 seconds
Started Jul 24 05:25:09 PM PDT 24
Finished Jul 24 05:25:43 PM PDT 24
Peak memory 206856 kb
Host smart-94bf8ece-cf4e-4743-9bbb-4860462a7412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27783
10542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.2778310542
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.529601864
Short name T2591
Test name
Test status
Simulation time 103750227 ps
CPU time 0.74 seconds
Started Jul 24 05:25:21 PM PDT 24
Finished Jul 24 05:25:22 PM PDT 24
Peak memory 206600 kb
Host smart-978379d4-943e-4764-91a1-4322aedd8c04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=529601864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.529601864
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.347448926
Short name T669
Test name
Test status
Simulation time 4049982499 ps
CPU time 5.18 seconds
Started Jul 24 05:25:12 PM PDT 24
Finished Jul 24 05:25:17 PM PDT 24
Peak memory 206708 kb
Host smart-e5580f13-a1f6-43f7-9d15-69bd81d56513
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=347448926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.347448926
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.1243807066
Short name T12
Test name
Test status
Simulation time 13335296045 ps
CPU time 16.45 seconds
Started Jul 24 05:25:11 PM PDT 24
Finished Jul 24 05:25:28 PM PDT 24
Peak memory 206604 kb
Host smart-09d656e9-e77a-456f-abb4-c3f28a5d8656
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1243807066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.1243807066
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.2827847253
Short name T2077
Test name
Test status
Simulation time 23387662201 ps
CPU time 29.69 seconds
Started Jul 24 05:25:05 PM PDT 24
Finished Jul 24 05:25:35 PM PDT 24
Peak memory 206740 kb
Host smart-7e17a281-c651-4554-a0fe-8086df0f2ad0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2827847253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.2827847253
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.3459305384
Short name T442
Test name
Test status
Simulation time 152398012 ps
CPU time 0.8 seconds
Started Jul 24 05:25:08 PM PDT 24
Finished Jul 24 05:25:09 PM PDT 24
Peak memory 206392 kb
Host smart-67069849-60e8-46f2-af0b-6903224656a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34593
05384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.3459305384
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.2683060980
Short name T96
Test name
Test status
Simulation time 162519360 ps
CPU time 0.82 seconds
Started Jul 24 05:25:10 PM PDT 24
Finished Jul 24 05:25:11 PM PDT 24
Peak memory 206576 kb
Host smart-668c5e5d-5ce1-4ef9-b0a3-35f39a741ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26830
60980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.2683060980
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.2267369511
Short name T2326
Test name
Test status
Simulation time 559984971 ps
CPU time 1.53 seconds
Started Jul 24 05:25:15 PM PDT 24
Finished Jul 24 05:25:17 PM PDT 24
Peak memory 206696 kb
Host smart-91b220fe-cb59-46db-b294-e5a0f96c2cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22673
69511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.2267369511
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.2149840679
Short name T1837
Test name
Test status
Simulation time 795992328 ps
CPU time 2.18 seconds
Started Jul 24 05:25:21 PM PDT 24
Finished Jul 24 05:25:24 PM PDT 24
Peak memory 206624 kb
Host smart-d7b1554f-9fb2-4cc2-b2ef-6a1d189910c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21498
40679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.2149840679
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.3220072583
Short name T1060
Test name
Test status
Simulation time 10247101918 ps
CPU time 20.39 seconds
Started Jul 24 05:25:17 PM PDT 24
Finished Jul 24 05:25:37 PM PDT 24
Peak memory 206888 kb
Host smart-a60b51da-1266-402c-b111-ecc9d56a11f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32200
72583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.3220072583
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.3339346732
Short name T1664
Test name
Test status
Simulation time 415961144 ps
CPU time 1.26 seconds
Started Jul 24 05:25:11 PM PDT 24
Finished Jul 24 05:25:13 PM PDT 24
Peak memory 206644 kb
Host smart-be8a32de-e1ea-4865-8e9a-ec9783df0b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33393
46732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.3339346732
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.2157763845
Short name T1755
Test name
Test status
Simulation time 147930587 ps
CPU time 0.78 seconds
Started Jul 24 05:25:16 PM PDT 24
Finished Jul 24 05:25:17 PM PDT 24
Peak memory 206528 kb
Host smart-2477c809-9595-422e-8148-805c45d27a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21577
63845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.2157763845
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.3236539382
Short name T421
Test name
Test status
Simulation time 57122160 ps
CPU time 0.68 seconds
Started Jul 24 05:25:22 PM PDT 24
Finished Jul 24 05:25:23 PM PDT 24
Peak memory 206552 kb
Host smart-92621d0d-a73a-431e-8af6-04dda1ab986c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32365
39382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.3236539382
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.1236917321
Short name T2681
Test name
Test status
Simulation time 701815831 ps
CPU time 1.82 seconds
Started Jul 24 05:25:28 PM PDT 24
Finished Jul 24 05:25:30 PM PDT 24
Peak memory 206852 kb
Host smart-96a957d9-2f2e-4d44-9bb5-83aae6a50980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12369
17321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.1236917321
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.4185817995
Short name T2533
Test name
Test status
Simulation time 335507933 ps
CPU time 2.44 seconds
Started Jul 24 05:25:22 PM PDT 24
Finished Jul 24 05:25:24 PM PDT 24
Peak memory 206824 kb
Host smart-52b97b44-0a6f-438f-8b12-abbc2bdf1e2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41858
17995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.4185817995
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.718010885
Short name T2341
Test name
Test status
Simulation time 247339564 ps
CPU time 0.86 seconds
Started Jul 24 05:25:30 PM PDT 24
Finished Jul 24 05:25:31 PM PDT 24
Peak memory 206516 kb
Host smart-6f0b7866-db33-42ac-8c64-e47fbf62e161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71801
0885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.718010885
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.1646651791
Short name T2477
Test name
Test status
Simulation time 141438267 ps
CPU time 0.72 seconds
Started Jul 24 05:25:18 PM PDT 24
Finished Jul 24 05:25:19 PM PDT 24
Peak memory 206576 kb
Host smart-7db47901-a37f-458d-982f-a977708d9107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16466
51791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.1646651791
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.2127723336
Short name T1322
Test name
Test status
Simulation time 164619232 ps
CPU time 0.82 seconds
Started Jul 24 05:25:36 PM PDT 24
Finished Jul 24 05:25:37 PM PDT 24
Peak memory 206612 kb
Host smart-ad4cb623-7f48-4962-b319-1fc74e5b89b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21277
23336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.2127723336
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_invalid_sync.1726215273
Short name T1821
Test name
Test status
Simulation time 5028861861 ps
CPU time 47.21 seconds
Started Jul 24 05:25:23 PM PDT 24
Finished Jul 24 05:26:11 PM PDT 24
Peak memory 206916 kb
Host smart-4135a3eb-6480-439c-9bf6-78fc3945efa7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1726215273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.1726215273
Directory /workspace/11.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/11.usbdev_iso_retraction.3230985608
Short name T938
Test name
Test status
Simulation time 7501218073 ps
CPU time 63.81 seconds
Started Jul 24 05:25:20 PM PDT 24
Finished Jul 24 05:26:24 PM PDT 24
Peak memory 207000 kb
Host smart-3e708c4b-d053-4eaa-b5dc-7d03563b517d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32309
85608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.3230985608
Directory /workspace/11.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.2774251435
Short name T900
Test name
Test status
Simulation time 173767126 ps
CPU time 0.81 seconds
Started Jul 24 05:25:26 PM PDT 24
Finished Jul 24 05:25:27 PM PDT 24
Peak memory 206556 kb
Host smart-eb7843d9-610d-417a-a0f5-f6e4e04aac44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27742
51435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.2774251435
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.2905451249
Short name T2408
Test name
Test status
Simulation time 23283307764 ps
CPU time 23 seconds
Started Jul 24 05:25:36 PM PDT 24
Finished Jul 24 05:25:59 PM PDT 24
Peak memory 206676 kb
Host smart-c09045c2-3db3-4127-b6dc-88c3af6b1692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29054
51249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.2905451249
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.3441298196
Short name T585
Test name
Test status
Simulation time 3290427758 ps
CPU time 4.02 seconds
Started Jul 24 05:25:30 PM PDT 24
Finished Jul 24 05:25:34 PM PDT 24
Peak memory 206548 kb
Host smart-d99297fe-4a9d-4a76-88bb-4e3d93107e0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34412
98196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.3441298196
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.1307592331
Short name T2092
Test name
Test status
Simulation time 11892719619 ps
CPU time 81.89 seconds
Started Jul 24 05:25:23 PM PDT 24
Finished Jul 24 05:26:50 PM PDT 24
Peak memory 206980 kb
Host smart-7836459c-e23d-4aad-92ed-3a9dca24b5d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13075
92331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.1307592331
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.945494075
Short name T2192
Test name
Test status
Simulation time 4961966096 ps
CPU time 34.26 seconds
Started Jul 24 05:25:28 PM PDT 24
Finished Jul 24 05:26:03 PM PDT 24
Peak memory 206824 kb
Host smart-7aca233f-015d-482d-be3e-45509d4dc908
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=945494075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.945494075
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.689710255
Short name T305
Test name
Test status
Simulation time 247718633 ps
CPU time 0.94 seconds
Started Jul 24 05:25:21 PM PDT 24
Finished Jul 24 05:25:22 PM PDT 24
Peak memory 206612 kb
Host smart-3f544034-8d03-4b22-99a0-207815659f3d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=689710255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.689710255
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.1885137601
Short name T719
Test name
Test status
Simulation time 198410165 ps
CPU time 0.87 seconds
Started Jul 24 05:25:24 PM PDT 24
Finished Jul 24 05:25:25 PM PDT 24
Peak memory 206588 kb
Host smart-d40e0497-0f36-4620-91cc-84c10c173385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18851
37601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.1885137601
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.3859313647
Short name T1843
Test name
Test status
Simulation time 6083295027 ps
CPU time 56.32 seconds
Started Jul 24 05:25:20 PM PDT 24
Finished Jul 24 05:26:16 PM PDT 24
Peak memory 206836 kb
Host smart-2ca2d721-2755-42fa-9bb9-44845bcbb583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38593
13647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.3859313647
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.3924989063
Short name T2144
Test name
Test status
Simulation time 3833506027 ps
CPU time 33.4 seconds
Started Jul 24 05:25:22 PM PDT 24
Finished Jul 24 05:25:56 PM PDT 24
Peak memory 206896 kb
Host smart-223af96b-cef1-4dbe-8c39-c0117546e3c5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3924989063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.3924989063
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.245047923
Short name T354
Test name
Test status
Simulation time 155996625 ps
CPU time 0.8 seconds
Started Jul 24 05:25:27 PM PDT 24
Finished Jul 24 05:25:28 PM PDT 24
Peak memory 206572 kb
Host smart-8721e0b9-b973-45d7-88d6-7f8169f2a0a6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=245047923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.245047923
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.4286708103
Short name T1491
Test name
Test status
Simulation time 163403509 ps
CPU time 0.77 seconds
Started Jul 24 05:25:19 PM PDT 24
Finished Jul 24 05:25:20 PM PDT 24
Peak memory 206576 kb
Host smart-a8a5b665-dda5-4817-b698-5f3f22ab6447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42867
08103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.4286708103
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.960055522
Short name T2405
Test name
Test status
Simulation time 210373684 ps
CPU time 0.88 seconds
Started Jul 24 05:25:23 PM PDT 24
Finished Jul 24 05:25:24 PM PDT 24
Peak memory 206772 kb
Host smart-7424b25a-efbc-443f-a13a-a20eeb0e1e07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96005
5522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.960055522
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.841509748
Short name T457
Test name
Test status
Simulation time 157524378 ps
CPU time 0.76 seconds
Started Jul 24 05:25:24 PM PDT 24
Finished Jul 24 05:25:25 PM PDT 24
Peak memory 206572 kb
Host smart-bfd13f11-727d-40cd-9a9a-b71a83e6a907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84150
9748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.841509748
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.4219732681
Short name T473
Test name
Test status
Simulation time 179895262 ps
CPU time 0.79 seconds
Started Jul 24 05:25:20 PM PDT 24
Finished Jul 24 05:25:21 PM PDT 24
Peak memory 206576 kb
Host smart-7584f0ab-530c-43e9-9bdd-4ebe4db03323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42197
32681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.4219732681
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.3601254956
Short name T2512
Test name
Test status
Simulation time 183501609 ps
CPU time 0.82 seconds
Started Jul 24 05:25:37 PM PDT 24
Finished Jul 24 05:25:38 PM PDT 24
Peak memory 206624 kb
Host smart-27b8f31b-6dac-4e6e-aadb-aed998258f9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36012
54956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.3601254956
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.2571277546
Short name T2167
Test name
Test status
Simulation time 182970311 ps
CPU time 0.82 seconds
Started Jul 24 05:25:27 PM PDT 24
Finished Jul 24 05:25:28 PM PDT 24
Peak memory 206592 kb
Host smart-cf1bca5b-90c8-4e75-93db-806d48db780d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2571277546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.2571277546
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.4198709714
Short name T1400
Test name
Test status
Simulation time 157078318 ps
CPU time 0.75 seconds
Started Jul 24 05:25:28 PM PDT 24
Finished Jul 24 05:25:29 PM PDT 24
Peak memory 206620 kb
Host smart-6e4efb96-9a88-4a48-9675-2548b3589f4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41987
09714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.4198709714
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.1703429590
Short name T1421
Test name
Test status
Simulation time 92136008 ps
CPU time 0.66 seconds
Started Jul 24 05:25:13 PM PDT 24
Finished Jul 24 05:25:14 PM PDT 24
Peak memory 206584 kb
Host smart-26899bbd-5ba0-403d-8ed2-c6f7307bc240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17034
29590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.1703429590
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.591245121
Short name T1317
Test name
Test status
Simulation time 21283057297 ps
CPU time 44.38 seconds
Started Jul 24 05:25:22 PM PDT 24
Finished Jul 24 05:26:06 PM PDT 24
Peak memory 215168 kb
Host smart-75c95601-b25a-4ae8-a145-1affe7b0b908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59124
5121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.591245121
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.2373380859
Short name T657
Test name
Test status
Simulation time 234527727 ps
CPU time 0.87 seconds
Started Jul 24 05:25:25 PM PDT 24
Finished Jul 24 05:25:26 PM PDT 24
Peak memory 206640 kb
Host smart-554e0f62-efab-4f22-829a-c8173c0a8f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23733
80859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.2373380859
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.4152117776
Short name T1120
Test name
Test status
Simulation time 170263044 ps
CPU time 0.81 seconds
Started Jul 24 05:25:14 PM PDT 24
Finished Jul 24 05:25:15 PM PDT 24
Peak memory 206580 kb
Host smart-3f0624e1-80e4-4056-90d7-cc1d0d805bce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41521
17776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.4152117776
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.1299164509
Short name T1145
Test name
Test status
Simulation time 163503838 ps
CPU time 0.83 seconds
Started Jul 24 05:25:36 PM PDT 24
Finished Jul 24 05:25:37 PM PDT 24
Peak memory 206516 kb
Host smart-f3cb55da-49d9-4b82-8588-044e3b73f8cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12991
64509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.1299164509
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.731336978
Short name T1816
Test name
Test status
Simulation time 190278110 ps
CPU time 0.84 seconds
Started Jul 24 05:25:21 PM PDT 24
Finished Jul 24 05:25:22 PM PDT 24
Peak memory 206592 kb
Host smart-c2196ffb-5aad-4af0-94e8-1740be122527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73133
6978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.731336978
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.4055519606
Short name T2237
Test name
Test status
Simulation time 180119487 ps
CPU time 0.82 seconds
Started Jul 24 05:25:31 PM PDT 24
Finished Jul 24 05:25:32 PM PDT 24
Peak memory 206592 kb
Host smart-81576cd7-2345-4aa1-bcf4-e1f31f887228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40555
19606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.4055519606
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.2973954797
Short name T359
Test name
Test status
Simulation time 151173492 ps
CPU time 0.75 seconds
Started Jul 24 05:25:34 PM PDT 24
Finished Jul 24 05:25:35 PM PDT 24
Peak memory 206580 kb
Host smart-22045a48-bb72-4a60-bb10-eacd0b018871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29739
54797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.2973954797
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.2175095574
Short name T1476
Test name
Test status
Simulation time 240832630 ps
CPU time 1.02 seconds
Started Jul 24 05:25:25 PM PDT 24
Finished Jul 24 05:25:26 PM PDT 24
Peak memory 206592 kb
Host smart-1283f9de-7e0b-4ace-9901-54971e19cb65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21750
95574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.2175095574
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.3264651933
Short name T2218
Test name
Test status
Simulation time 6098192987 ps
CPU time 170.56 seconds
Started Jul 24 05:25:20 PM PDT 24
Finished Jul 24 05:28:10 PM PDT 24
Peak memory 206932 kb
Host smart-03b2d5df-298d-4602-b9e7-5680ae9bcb2e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3264651933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.3264651933
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.2515552284
Short name T1390
Test name
Test status
Simulation time 172342926 ps
CPU time 0.82 seconds
Started Jul 24 05:25:19 PM PDT 24
Finished Jul 24 05:25:20 PM PDT 24
Peak memory 206584 kb
Host smart-3ee539f1-702e-455c-868f-48e1c878f94f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25155
52284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.2515552284
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.2777830114
Short name T2442
Test name
Test status
Simulation time 198689169 ps
CPU time 0.9 seconds
Started Jul 24 05:25:12 PM PDT 24
Finished Jul 24 05:25:13 PM PDT 24
Peak memory 206604 kb
Host smart-b0a1e9e0-c52a-4e13-9964-652edb2c17e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27778
30114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.2777830114
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.1929697562
Short name T1359
Test name
Test status
Simulation time 1073814900 ps
CPU time 2.59 seconds
Started Jul 24 05:25:14 PM PDT 24
Finished Jul 24 05:25:16 PM PDT 24
Peak memory 206632 kb
Host smart-d64b5d80-32a8-4a81-9681-abbf41fe435e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19296
97562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.1929697562
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.2023397237
Short name T1740
Test name
Test status
Simulation time 7599648523 ps
CPU time 65.83 seconds
Started Jul 24 05:25:31 PM PDT 24
Finished Jul 24 05:26:37 PM PDT 24
Peak memory 206960 kb
Host smart-a1240b9b-3d8d-45be-8487-ed09afe539ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20233
97237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.2023397237
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.1963210887
Short name T1681
Test name
Test status
Simulation time 4017444681 ps
CPU time 5.06 seconds
Started Jul 24 05:25:18 PM PDT 24
Finished Jul 24 05:25:23 PM PDT 24
Peak memory 206940 kb
Host smart-49522e45-562d-46f4-8b93-9a82182257ee
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1963210887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.1963210887
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.2208705428
Short name T483
Test name
Test status
Simulation time 13377838118 ps
CPU time 12.28 seconds
Started Jul 24 05:25:18 PM PDT 24
Finished Jul 24 05:25:31 PM PDT 24
Peak memory 206928 kb
Host smart-a9bb7243-c0ef-4401-aa01-1f697ca34dcc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2208705428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.2208705428
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.313172499
Short name T416
Test name
Test status
Simulation time 23355435060 ps
CPU time 23.6 seconds
Started Jul 24 05:25:31 PM PDT 24
Finished Jul 24 05:25:55 PM PDT 24
Peak memory 206732 kb
Host smart-9592538a-e141-4da1-bd00-f8ae3866d097
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=313172499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.313172499
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.3938705323
Short name T450
Test name
Test status
Simulation time 213591969 ps
CPU time 0.81 seconds
Started Jul 24 05:25:38 PM PDT 24
Finished Jul 24 05:25:39 PM PDT 24
Peak memory 206576 kb
Host smart-c2a2e14b-413f-42d6-8546-83ea3476dcf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39387
05323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.3938705323
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.421730625
Short name T714
Test name
Test status
Simulation time 185838421 ps
CPU time 0.8 seconds
Started Jul 24 05:25:19 PM PDT 24
Finished Jul 24 05:25:20 PM PDT 24
Peak memory 206580 kb
Host smart-17263135-8f0a-4882-b35f-720a080131f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42173
0625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.421730625
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.698325923
Short name T51
Test name
Test status
Simulation time 269232538 ps
CPU time 1.08 seconds
Started Jul 24 05:25:22 PM PDT 24
Finished Jul 24 05:25:24 PM PDT 24
Peak memory 206544 kb
Host smart-a88fad65-515a-431e-bcc9-8c191101b4c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69832
5923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.698325923
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.578769259
Short name T632
Test name
Test status
Simulation time 492595471 ps
CPU time 1.3 seconds
Started Jul 24 05:25:20 PM PDT 24
Finished Jul 24 05:25:21 PM PDT 24
Peak memory 206576 kb
Host smart-84444597-3705-43ac-acd0-720ba2bc8bd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57876
9259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.578769259
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.3274768434
Short name T971
Test name
Test status
Simulation time 19374674814 ps
CPU time 35.29 seconds
Started Jul 24 05:25:35 PM PDT 24
Finished Jul 24 05:26:10 PM PDT 24
Peak memory 206912 kb
Host smart-2d495d2d-dc32-4ef6-ac7f-021a58a5b3c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32747
68434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.3274768434
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.4174825779
Short name T1847
Test name
Test status
Simulation time 403105328 ps
CPU time 1.24 seconds
Started Jul 24 05:25:19 PM PDT 24
Finished Jul 24 05:25:21 PM PDT 24
Peak memory 206576 kb
Host smart-d3f0d704-c64f-4d81-ab45-fd8f66edc637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41748
25779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.4174825779
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.3245890676
Short name T35
Test name
Test status
Simulation time 163201596 ps
CPU time 0.76 seconds
Started Jul 24 05:25:31 PM PDT 24
Finished Jul 24 05:25:32 PM PDT 24
Peak memory 206592 kb
Host smart-fdd180f4-e93c-4630-bc64-6b312afd820d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32458
90676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.3245890676
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.2313239829
Short name T1818
Test name
Test status
Simulation time 56544082 ps
CPU time 0.64 seconds
Started Jul 24 05:25:21 PM PDT 24
Finished Jul 24 05:25:22 PM PDT 24
Peak memory 206544 kb
Host smart-d75d92a8-385a-4cb0-a4c8-f6a5d30dc316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23132
39829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.2313239829
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.824009047
Short name T1732
Test name
Test status
Simulation time 843547613 ps
CPU time 2.06 seconds
Started Jul 24 05:25:36 PM PDT 24
Finished Jul 24 05:25:39 PM PDT 24
Peak memory 206772 kb
Host smart-2721c5a5-73be-472a-866e-16d1c74093a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82400
9047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.824009047
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.311110500
Short name T1351
Test name
Test status
Simulation time 240046225 ps
CPU time 1.6 seconds
Started Jul 24 05:25:24 PM PDT 24
Finished Jul 24 05:25:26 PM PDT 24
Peak memory 206788 kb
Host smart-5575990b-3a87-4b1b-bb04-060767ad53c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31111
0500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.311110500
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.2439679608
Short name T2396
Test name
Test status
Simulation time 202085141 ps
CPU time 0.89 seconds
Started Jul 24 05:25:19 PM PDT 24
Finished Jul 24 05:25:20 PM PDT 24
Peak memory 206548 kb
Host smart-2cdc4dd1-d98d-4d7c-97c6-4e3d59059b5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24396
79608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.2439679608
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.3549456127
Short name T677
Test name
Test status
Simulation time 151823076 ps
CPU time 0.76 seconds
Started Jul 24 05:25:25 PM PDT 24
Finished Jul 24 05:25:26 PM PDT 24
Peak memory 206596 kb
Host smart-fce3d782-7711-40ee-82a8-9af99d5dd3fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35494
56127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.3549456127
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.90147429
Short name T1009
Test name
Test status
Simulation time 201099128 ps
CPU time 0.84 seconds
Started Jul 24 05:25:19 PM PDT 24
Finished Jul 24 05:25:20 PM PDT 24
Peak memory 206588 kb
Host smart-7a7621da-13ce-4541-9a00-deb147045fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90147
429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.90147429
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_iso_retraction.4014914961
Short name T2510
Test name
Test status
Simulation time 10804465605 ps
CPU time 39.55 seconds
Started Jul 24 05:25:30 PM PDT 24
Finished Jul 24 05:26:10 PM PDT 24
Peak memory 206908 kb
Host smart-0182135f-b707-4b93-ad7e-ea06f9ea1ad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40149
14961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.4014914961
Directory /workspace/12.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.814201202
Short name T2238
Test name
Test status
Simulation time 154442420 ps
CPU time 0.82 seconds
Started Jul 24 05:25:29 PM PDT 24
Finished Jul 24 05:25:30 PM PDT 24
Peak memory 206576 kb
Host smart-8096b026-e591-40ce-897a-090dbb4e930e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81420
1202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.814201202
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.2128604984
Short name T1940
Test name
Test status
Simulation time 23338646607 ps
CPU time 24.47 seconds
Started Jul 24 05:25:31 PM PDT 24
Finished Jul 24 05:25:55 PM PDT 24
Peak memory 206720 kb
Host smart-c6af6434-3bce-4aa3-8fff-f328ecb05715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21286
04984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.2128604984
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.3916728331
Short name T1855
Test name
Test status
Simulation time 3355002496 ps
CPU time 4.02 seconds
Started Jul 24 05:25:28 PM PDT 24
Finished Jul 24 05:25:32 PM PDT 24
Peak memory 206712 kb
Host smart-a4499a34-2d6c-44e1-a4ee-d31596599c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39167
28331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.3916728331
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.3621628244
Short name T2600
Test name
Test status
Simulation time 9499566000 ps
CPU time 83.47 seconds
Started Jul 24 05:25:27 PM PDT 24
Finished Jul 24 05:26:51 PM PDT 24
Peak memory 206984 kb
Host smart-f3698274-bd08-4ef5-8d91-9c476c202e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36216
28244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.3621628244
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.270044660
Short name T1290
Test name
Test status
Simulation time 3997727023 ps
CPU time 108.12 seconds
Started Jul 24 05:25:23 PM PDT 24
Finished Jul 24 05:27:11 PM PDT 24
Peak memory 206880 kb
Host smart-3f3772af-eeaf-435b-9129-3f881070b7c2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=270044660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.270044660
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.2285900117
Short name T2303
Test name
Test status
Simulation time 240282478 ps
CPU time 0.91 seconds
Started Jul 24 05:25:38 PM PDT 24
Finished Jul 24 05:25:40 PM PDT 24
Peak memory 206556 kb
Host smart-8c38add9-bd69-427b-8412-e6351c4ebdd1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2285900117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.2285900117
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.4048564015
Short name T433
Test name
Test status
Simulation time 196313906 ps
CPU time 0.83 seconds
Started Jul 24 05:25:36 PM PDT 24
Finished Jul 24 05:25:37 PM PDT 24
Peak memory 206588 kb
Host smart-4424b753-d6fa-4a4d-aea2-4ddf4cbf1a07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40485
64015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.4048564015
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.806906638
Short name T2568
Test name
Test status
Simulation time 4673335834 ps
CPU time 44.18 seconds
Started Jul 24 05:25:29 PM PDT 24
Finished Jul 24 05:26:13 PM PDT 24
Peak memory 206900 kb
Host smart-784a1b45-80cf-43d7-80b3-37155de76532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80690
6638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.806906638
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.1245647498
Short name T2620
Test name
Test status
Simulation time 5320168410 ps
CPU time 36.06 seconds
Started Jul 24 05:25:36 PM PDT 24
Finished Jul 24 05:26:13 PM PDT 24
Peak memory 207120 kb
Host smart-bb46293e-55ad-4187-addb-9920928fd02e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1245647498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.1245647498
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.2885423627
Short name T1418
Test name
Test status
Simulation time 171472517 ps
CPU time 0.85 seconds
Started Jul 24 05:25:21 PM PDT 24
Finished Jul 24 05:25:23 PM PDT 24
Peak memory 206632 kb
Host smart-c37cea72-6bcd-4eb2-9874-02bf1d6fdd2d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2885423627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.2885423627
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.2066507327
Short name T905
Test name
Test status
Simulation time 149287614 ps
CPU time 0.74 seconds
Started Jul 24 05:25:20 PM PDT 24
Finished Jul 24 05:25:21 PM PDT 24
Peak memory 206552 kb
Host smart-0e906dd3-86ae-4bd3-be5b-c7e977bb022e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20665
07327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.2066507327
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.2405039135
Short name T1283
Test name
Test status
Simulation time 169708716 ps
CPU time 0.78 seconds
Started Jul 24 05:25:22 PM PDT 24
Finished Jul 24 05:25:23 PM PDT 24
Peak memory 206516 kb
Host smart-56bc50e2-e3bd-4854-bac4-8dfe106720b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24050
39135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.2405039135
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.2729997065
Short name T498
Test name
Test status
Simulation time 159953638 ps
CPU time 0.8 seconds
Started Jul 24 05:25:38 PM PDT 24
Finished Jul 24 05:25:39 PM PDT 24
Peak memory 206608 kb
Host smart-bbaee730-8359-4947-a65e-547614ca4db2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27299
97065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.2729997065
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.2012887746
Short name T2445
Test name
Test status
Simulation time 146840327 ps
CPU time 0.82 seconds
Started Jul 24 05:25:27 PM PDT 24
Finished Jul 24 05:25:28 PM PDT 24
Peak memory 206560 kb
Host smart-e0f392da-fcdb-48ca-8fc1-00deed347d9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20128
87746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.2012887746
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.3459404098
Short name T2502
Test name
Test status
Simulation time 151731243 ps
CPU time 0.8 seconds
Started Jul 24 05:25:26 PM PDT 24
Finished Jul 24 05:25:27 PM PDT 24
Peak memory 206556 kb
Host smart-c34d10c7-6c91-4555-8e73-8054c3d72230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34594
04098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.3459404098
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.1521094711
Short name T549
Test name
Test status
Simulation time 227499327 ps
CPU time 0.93 seconds
Started Jul 24 05:25:40 PM PDT 24
Finished Jul 24 05:25:41 PM PDT 24
Peak memory 206656 kb
Host smart-b7a6771e-576a-49e8-8492-536edd5b8185
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1521094711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.1521094711
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.4151176359
Short name T2194
Test name
Test status
Simulation time 40215701 ps
CPU time 0.63 seconds
Started Jul 24 05:25:27 PM PDT 24
Finished Jul 24 05:25:28 PM PDT 24
Peak memory 206516 kb
Host smart-99bdea5d-bdd3-4556-9881-2d95983f4fb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41511
76359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.4151176359
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.2338770290
Short name T1522
Test name
Test status
Simulation time 21639274836 ps
CPU time 47.3 seconds
Started Jul 24 05:25:20 PM PDT 24
Finished Jul 24 05:26:07 PM PDT 24
Peak memory 215244 kb
Host smart-00fcc0f7-d477-4225-bc36-458a6346c956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23387
70290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.2338770290
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.1855369176
Short name T1096
Test name
Test status
Simulation time 166442690 ps
CPU time 0.84 seconds
Started Jul 24 05:25:31 PM PDT 24
Finished Jul 24 05:25:32 PM PDT 24
Peak memory 206596 kb
Host smart-9354ead2-2807-4d7c-8f06-000fc4672eed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18553
69176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.1855369176
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.19377369
Short name T1869
Test name
Test status
Simulation time 182580939 ps
CPU time 0.79 seconds
Started Jul 24 05:25:27 PM PDT 24
Finished Jul 24 05:25:28 PM PDT 24
Peak memory 206468 kb
Host smart-e35c10b0-35a8-490a-8d84-7af40c8fc300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19377
369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.19377369
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.3875411307
Short name T2406
Test name
Test status
Simulation time 232483728 ps
CPU time 0.88 seconds
Started Jul 24 05:25:22 PM PDT 24
Finished Jul 24 05:25:23 PM PDT 24
Peak memory 206464 kb
Host smart-801e7ae4-4e90-48a1-bbf2-8076a00ae246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38754
11307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.3875411307
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.3793891184
Short name T2247
Test name
Test status
Simulation time 179237910 ps
CPU time 0.81 seconds
Started Jul 24 05:25:47 PM PDT 24
Finished Jul 24 05:25:48 PM PDT 24
Peak memory 206600 kb
Host smart-6788981a-fd80-4943-b145-858642e86fae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37938
91184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.3793891184
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.4027142338
Short name T2226
Test name
Test status
Simulation time 209500478 ps
CPU time 0.81 seconds
Started Jul 24 05:25:50 PM PDT 24
Finished Jul 24 05:25:51 PM PDT 24
Peak memory 206496 kb
Host smart-e5cb32a5-95c1-45a0-b53f-2cc5ae6e3eec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40271
42338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.4027142338
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.95173954
Short name T1172
Test name
Test status
Simulation time 152643938 ps
CPU time 0.76 seconds
Started Jul 24 05:25:44 PM PDT 24
Finished Jul 24 05:25:45 PM PDT 24
Peak memory 206576 kb
Host smart-4caa4c6d-4571-4042-8b7e-57077b065a86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95173
954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.95173954
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.1050647998
Short name T1559
Test name
Test status
Simulation time 150017957 ps
CPU time 0.76 seconds
Started Jul 24 05:25:38 PM PDT 24
Finished Jul 24 05:25:39 PM PDT 24
Peak memory 206560 kb
Host smart-e180caa1-3c84-47b2-917c-ac150fc586e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10506
47998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.1050647998
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.3582161300
Short name T1778
Test name
Test status
Simulation time 225925724 ps
CPU time 0.96 seconds
Started Jul 24 05:25:40 PM PDT 24
Finished Jul 24 05:25:41 PM PDT 24
Peak memory 206584 kb
Host smart-24a2114d-5650-4740-ab04-9a9e60de42de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35821
61300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.3582161300
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.4294402190
Short name T2628
Test name
Test status
Simulation time 5018355292 ps
CPU time 47.37 seconds
Started Jul 24 05:25:30 PM PDT 24
Finished Jul 24 05:26:18 PM PDT 24
Peak memory 206860 kb
Host smart-0d97d277-ba1a-4419-bcdc-44691826e4d6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4294402190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.4294402190
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.308924470
Short name T139
Test name
Test status
Simulation time 168917874 ps
CPU time 0.83 seconds
Started Jul 24 05:25:31 PM PDT 24
Finished Jul 24 05:25:32 PM PDT 24
Peak memory 206604 kb
Host smart-ecdf71dd-fa24-4b97-bde0-df1c0cedd561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30892
4470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.308924470
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.1402325736
Short name T1417
Test name
Test status
Simulation time 158738082 ps
CPU time 0.75 seconds
Started Jul 24 05:25:29 PM PDT 24
Finished Jul 24 05:25:30 PM PDT 24
Peak memory 206644 kb
Host smart-d12761f1-26b7-485e-b372-605cf9b14979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14023
25736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.1402325736
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.3555971745
Short name T2469
Test name
Test status
Simulation time 306498868 ps
CPU time 0.92 seconds
Started Jul 24 05:25:48 PM PDT 24
Finished Jul 24 05:25:49 PM PDT 24
Peak memory 206576 kb
Host smart-5ddf5c10-875d-4d0c-9ad0-dc5998d9acf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35559
71745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.3555971745
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.751316767
Short name T1721
Test name
Test status
Simulation time 4844587841 ps
CPU time 132.28 seconds
Started Jul 24 05:25:35 PM PDT 24
Finished Jul 24 05:27:48 PM PDT 24
Peak memory 206900 kb
Host smart-7ca576e3-8404-4b5f-abe7-f5d5762f7d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75131
6767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.751316767
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.2574138476
Short name T2438
Test name
Test status
Simulation time 56378359 ps
CPU time 0.69 seconds
Started Jul 24 05:25:33 PM PDT 24
Finished Jul 24 05:25:33 PM PDT 24
Peak memory 206608 kb
Host smart-ad1f7970-5f81-4256-a0f6-adaf576fc27b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2574138476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.2574138476
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.4050107903
Short name T1410
Test name
Test status
Simulation time 3696053670 ps
CPU time 4.15 seconds
Started Jul 24 05:25:25 PM PDT 24
Finished Jul 24 05:25:29 PM PDT 24
Peak memory 206972 kb
Host smart-f2780c26-d8cd-440f-bfd3-6e68497c477d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4050107903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.4050107903
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.3860198923
Short name T2140
Test name
Test status
Simulation time 13371356282 ps
CPU time 15.22 seconds
Started Jul 24 05:25:37 PM PDT 24
Finished Jul 24 05:25:52 PM PDT 24
Peak memory 206664 kb
Host smart-a78567d4-29f4-4608-a58b-e72b63f87d1d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3860198923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.3860198923
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.3145374973
Short name T2057
Test name
Test status
Simulation time 23361447183 ps
CPU time 22.97 seconds
Started Jul 24 05:25:38 PM PDT 24
Finished Jul 24 05:26:01 PM PDT 24
Peak memory 206916 kb
Host smart-fab01f78-c899-4576-8063-0e93970ea719
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3145374973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.3145374973
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.2054522910
Short name T2552
Test name
Test status
Simulation time 166991854 ps
CPU time 0.82 seconds
Started Jul 24 05:25:41 PM PDT 24
Finished Jul 24 05:25:42 PM PDT 24
Peak memory 206596 kb
Host smart-50d1fa38-be80-47c2-8001-4e94d6a5e99a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20545
22910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.2054522910
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.2545462149
Short name T1085
Test name
Test status
Simulation time 166968322 ps
CPU time 0.84 seconds
Started Jul 24 05:25:29 PM PDT 24
Finished Jul 24 05:25:30 PM PDT 24
Peak memory 206572 kb
Host smart-a4be7121-ffa3-4c50-9b82-c0ecfca5d126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25454
62149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.2545462149
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.3865596823
Short name T2547
Test name
Test status
Simulation time 1101708041 ps
CPU time 2.34 seconds
Started Jul 24 05:25:28 PM PDT 24
Finished Jul 24 05:25:30 PM PDT 24
Peak memory 206784 kb
Host smart-2e883d09-27e2-49de-b376-e523cffa35ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38655
96823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.3865596823
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.1231975463
Short name T1219
Test name
Test status
Simulation time 17855083206 ps
CPU time 34.65 seconds
Started Jul 24 05:25:31 PM PDT 24
Finished Jul 24 05:26:06 PM PDT 24
Peak memory 206964 kb
Host smart-cac1aa53-d424-4af9-8611-344ad581cade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12319
75463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.1231975463
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.704218736
Short name T830
Test name
Test status
Simulation time 472869327 ps
CPU time 1.23 seconds
Started Jul 24 05:25:46 PM PDT 24
Finished Jul 24 05:25:47 PM PDT 24
Peak memory 206600 kb
Host smart-4484ff1e-6a7e-4c36-a60a-03d213fafc99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70421
8736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.704218736
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.4083086350
Short name T1874
Test name
Test status
Simulation time 149695340 ps
CPU time 0.75 seconds
Started Jul 24 05:25:40 PM PDT 24
Finished Jul 24 05:25:41 PM PDT 24
Peak memory 206500 kb
Host smart-07d5f5d4-4726-43a5-83a9-dbf7c2833a85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40830
86350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.4083086350
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.541331772
Short name T668
Test name
Test status
Simulation time 48845096 ps
CPU time 0.65 seconds
Started Jul 24 05:25:42 PM PDT 24
Finished Jul 24 05:25:43 PM PDT 24
Peak memory 206540 kb
Host smart-f790da53-ce63-4d6e-ae07-2f7842053701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54133
1772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.541331772
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.2589717442
Short name T141
Test name
Test status
Simulation time 749213199 ps
CPU time 1.76 seconds
Started Jul 24 05:25:44 PM PDT 24
Finished Jul 24 05:25:46 PM PDT 24
Peak memory 206828 kb
Host smart-1ddeb750-e85b-4d8b-841e-dd4c301700d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25897
17442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.2589717442
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.1039932428
Short name T1253
Test name
Test status
Simulation time 330358703 ps
CPU time 1.94 seconds
Started Jul 24 05:25:48 PM PDT 24
Finished Jul 24 05:25:51 PM PDT 24
Peak memory 206836 kb
Host smart-f8c34e66-f95e-4453-af68-16cc2b7eab5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10399
32428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.1039932428
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.4080197934
Short name T532
Test name
Test status
Simulation time 199163010 ps
CPU time 0.85 seconds
Started Jul 24 05:25:27 PM PDT 24
Finished Jul 24 05:25:28 PM PDT 24
Peak memory 206600 kb
Host smart-e8684621-63a4-4edd-abfe-2fb641384a74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40801
97934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.4080197934
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.3510202549
Short name T342
Test name
Test status
Simulation time 204776085 ps
CPU time 0.86 seconds
Started Jul 24 05:25:29 PM PDT 24
Finished Jul 24 05:25:30 PM PDT 24
Peak memory 206600 kb
Host smart-3f96daca-ff82-40d9-b800-7b18b3f2af76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35102
02549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.3510202549
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.1704338703
Short name T2565
Test name
Test status
Simulation time 166294730 ps
CPU time 0.78 seconds
Started Jul 24 05:25:36 PM PDT 24
Finished Jul 24 05:25:37 PM PDT 24
Peak memory 206604 kb
Host smart-37c0fd78-9984-4679-ac84-9ce32cd038d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17043
38703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.1704338703
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_iso_retraction.2462585707
Short name T909
Test name
Test status
Simulation time 4816634614 ps
CPU time 37.39 seconds
Started Jul 24 05:25:44 PM PDT 24
Finished Jul 24 05:26:22 PM PDT 24
Peak memory 206888 kb
Host smart-93bc80a9-f60c-418b-866c-11e4eb370880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24625
85707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.2462585707
Directory /workspace/13.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.2109943151
Short name T2589
Test name
Test status
Simulation time 235716796 ps
CPU time 0.89 seconds
Started Jul 24 05:25:48 PM PDT 24
Finished Jul 24 05:25:55 PM PDT 24
Peak memory 206576 kb
Host smart-0e79096d-e30b-4d49-9176-b3277dec11e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21099
43151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.2109943151
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.2862543938
Short name T1014
Test name
Test status
Simulation time 23348919372 ps
CPU time 24.15 seconds
Started Jul 24 05:25:46 PM PDT 24
Finished Jul 24 05:26:10 PM PDT 24
Peak memory 206664 kb
Host smart-7cff7f17-9b1d-4359-a009-0f6635ab380d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28625
43938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.2862543938
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.166728206
Short name T18
Test name
Test status
Simulation time 3353780842 ps
CPU time 3.65 seconds
Started Jul 24 05:25:34 PM PDT 24
Finished Jul 24 05:25:38 PM PDT 24
Peak memory 206692 kb
Host smart-3462cd30-7a0d-4ce7-9687-4485a6468967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16672
8206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.166728206
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.2460616156
Short name T2283
Test name
Test status
Simulation time 8571650466 ps
CPU time 78.72 seconds
Started Jul 24 05:25:25 PM PDT 24
Finished Jul 24 05:26:44 PM PDT 24
Peak memory 207016 kb
Host smart-8d1a590d-1dda-49f1-ae37-411954cbe4d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24606
16156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.2460616156
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.3737437679
Short name T915
Test name
Test status
Simulation time 6028805984 ps
CPU time 58.52 seconds
Started Jul 24 05:25:39 PM PDT 24
Finished Jul 24 05:26:38 PM PDT 24
Peak memory 206972 kb
Host smart-e0cd2147-97cb-4632-a93c-f5ae59b715a2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3737437679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.3737437679
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.365572464
Short name T563
Test name
Test status
Simulation time 323199814 ps
CPU time 0.98 seconds
Started Jul 24 05:25:29 PM PDT 24
Finished Jul 24 05:25:30 PM PDT 24
Peak memory 206408 kb
Host smart-0028898a-b1f9-4004-9b9c-cb156dfda42e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=365572464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.365572464
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.4161211183
Short name T397
Test name
Test status
Simulation time 201938656 ps
CPU time 0.86 seconds
Started Jul 24 05:25:44 PM PDT 24
Finished Jul 24 05:25:45 PM PDT 24
Peak memory 206600 kb
Host smart-bb637cce-4604-4360-a1a6-b8c6902be7e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41612
11183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.4161211183
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.759387174
Short name T1552
Test name
Test status
Simulation time 4818704784 ps
CPU time 32.94 seconds
Started Jul 24 05:25:38 PM PDT 24
Finished Jul 24 05:26:11 PM PDT 24
Peak memory 206916 kb
Host smart-1b56b380-aaf9-455b-91f5-85ebf2a37964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75938
7174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.759387174
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.4042645128
Short name T2507
Test name
Test status
Simulation time 6819841222 ps
CPU time 65 seconds
Started Jul 24 05:25:28 PM PDT 24
Finished Jul 24 05:26:33 PM PDT 24
Peak memory 206964 kb
Host smart-60207665-07d1-4622-bc59-6622b38d15ea
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4042645128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.4042645128
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.3042492252
Short name T327
Test name
Test status
Simulation time 189254803 ps
CPU time 0.79 seconds
Started Jul 24 05:25:41 PM PDT 24
Finished Jul 24 05:25:42 PM PDT 24
Peak memory 206564 kb
Host smart-38a01f77-eee0-4af8-b8bb-c02ddfc098dd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3042492252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.3042492252
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.4148754873
Short name T1906
Test name
Test status
Simulation time 163632289 ps
CPU time 0.82 seconds
Started Jul 24 05:25:51 PM PDT 24
Finished Jul 24 05:25:51 PM PDT 24
Peak memory 206600 kb
Host smart-4caedd2d-b3a9-4c46-a3ef-cb5ab76577b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41487
54873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.4148754873
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.4073501038
Short name T807
Test name
Test status
Simulation time 181974016 ps
CPU time 0.8 seconds
Started Jul 24 05:25:44 PM PDT 24
Finished Jul 24 05:25:45 PM PDT 24
Peak memory 206624 kb
Host smart-57eacac2-01e4-47d5-a058-e93c67f705ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40735
01038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.4073501038
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.2318225076
Short name T1649
Test name
Test status
Simulation time 187141385 ps
CPU time 0.79 seconds
Started Jul 24 05:25:44 PM PDT 24
Finished Jul 24 05:25:45 PM PDT 24
Peak memory 206592 kb
Host smart-a1a36156-80fe-45a6-a18e-e4861d312566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23182
25076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.2318225076
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.4091068279
Short name T330
Test name
Test status
Simulation time 162342767 ps
CPU time 0.8 seconds
Started Jul 24 05:25:44 PM PDT 24
Finished Jul 24 05:25:45 PM PDT 24
Peak memory 206580 kb
Host smart-cc8258dd-f5eb-49e5-bda2-64c69fe64093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40910
68279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.4091068279
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.3009871681
Short name T1319
Test name
Test status
Simulation time 148819562 ps
CPU time 0.78 seconds
Started Jul 24 05:25:35 PM PDT 24
Finished Jul 24 05:25:36 PM PDT 24
Peak memory 206588 kb
Host smart-59c5266d-f6b8-4608-99bd-c07ee10e0769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30098
71681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.3009871681
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.2047094903
Short name T1040
Test name
Test status
Simulation time 211286669 ps
CPU time 0.9 seconds
Started Jul 24 05:25:35 PM PDT 24
Finished Jul 24 05:25:37 PM PDT 24
Peak memory 206604 kb
Host smart-ebe8fdba-c8f7-40f8-8069-d4049952fc0a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2047094903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.2047094903
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.1231274009
Short name T2736
Test name
Test status
Simulation time 146705849 ps
CPU time 0.75 seconds
Started Jul 24 05:25:35 PM PDT 24
Finished Jul 24 05:25:36 PM PDT 24
Peak memory 206640 kb
Host smart-7a7829e2-edd2-43c1-b8b6-3c68cd2310ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12312
74009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.1231274009
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.423485861
Short name T1314
Test name
Test status
Simulation time 6629117756 ps
CPU time 16.97 seconds
Started Jul 24 05:25:31 PM PDT 24
Finished Jul 24 05:25:48 PM PDT 24
Peak memory 206872 kb
Host smart-a3c0f95f-e5d6-4553-9bba-1da7d5934b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42348
5861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.423485861
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.1656693140
Short name T2614
Test name
Test status
Simulation time 179338948 ps
CPU time 0.84 seconds
Started Jul 24 05:25:46 PM PDT 24
Finished Jul 24 05:25:47 PM PDT 24
Peak memory 206592 kb
Host smart-6073c099-633b-4d18-9338-c903bf8e96de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16566
93140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.1656693140
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.3500587465
Short name T1945
Test name
Test status
Simulation time 237336455 ps
CPU time 0.87 seconds
Started Jul 24 05:25:30 PM PDT 24
Finished Jul 24 05:25:32 PM PDT 24
Peak memory 206588 kb
Host smart-5ed989d9-0689-4468-9610-e354994c45b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35005
87465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.3500587465
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.1452872450
Short name T14
Test name
Test status
Simulation time 229503629 ps
CPU time 0.89 seconds
Started Jul 24 05:25:30 PM PDT 24
Finished Jul 24 05:25:31 PM PDT 24
Peak memory 206540 kb
Host smart-9f2fc860-cc1d-47ce-b38a-62985f6d4231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14528
72450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.1452872450
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.2038684022
Short name T1892
Test name
Test status
Simulation time 144232587 ps
CPU time 0.77 seconds
Started Jul 24 05:25:28 PM PDT 24
Finished Jul 24 05:25:29 PM PDT 24
Peak memory 206608 kb
Host smart-abe0eb6d-a920-4088-946a-4fd3580c701a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20386
84022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.2038684022
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.562436077
Short name T1966
Test name
Test status
Simulation time 203640504 ps
CPU time 0.81 seconds
Started Jul 24 05:25:41 PM PDT 24
Finished Jul 24 05:25:42 PM PDT 24
Peak memory 206580 kb
Host smart-eee72c1f-2cb7-4d4f-a285-2a7a02d70662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56243
6077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.562436077
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.2797356607
Short name T372
Test name
Test status
Simulation time 184194469 ps
CPU time 0.77 seconds
Started Jul 24 05:25:53 PM PDT 24
Finished Jul 24 05:25:54 PM PDT 24
Peak memory 206560 kb
Host smart-186af077-a0bd-4af0-ba1b-349bf0409e02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27973
56607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.2797356607
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.3584286722
Short name T1812
Test name
Test status
Simulation time 244419213 ps
CPU time 0.92 seconds
Started Jul 24 05:25:32 PM PDT 24
Finished Jul 24 05:25:33 PM PDT 24
Peak memory 206516 kb
Host smart-e1f23a9a-0683-44ff-8197-68444b7f7728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35842
86722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.3584286722
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.962760459
Short name T716
Test name
Test status
Simulation time 4146843721 ps
CPU time 114.76 seconds
Started Jul 24 05:25:32 PM PDT 24
Finished Jul 24 05:27:27 PM PDT 24
Peak memory 207024 kb
Host smart-4f6bb5bb-190e-499c-b610-812b05f49335
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=962760459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.962760459
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.3645926946
Short name T1893
Test name
Test status
Simulation time 194272794 ps
CPU time 0.82 seconds
Started Jul 24 05:25:50 PM PDT 24
Finished Jul 24 05:25:50 PM PDT 24
Peak memory 206672 kb
Host smart-60a0f2d3-f037-438f-b2d7-7f84eb15a15d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36459
26946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.3645926946
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.547655148
Short name T493
Test name
Test status
Simulation time 214060876 ps
CPU time 0.84 seconds
Started Jul 24 05:25:50 PM PDT 24
Finished Jul 24 05:25:51 PM PDT 24
Peak memory 206504 kb
Host smart-08180f3c-8a25-46bf-a7dd-6eeb21c6d5f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54765
5148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.547655148
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.3688046356
Short name T979
Test name
Test status
Simulation time 681634283 ps
CPU time 1.67 seconds
Started Jul 24 05:25:56 PM PDT 24
Finished Jul 24 05:25:58 PM PDT 24
Peak memory 206496 kb
Host smart-6404bacb-4b33-4af4-bb29-4e7cac584a38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36880
46356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.3688046356
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.2412929434
Short name T1212
Test name
Test status
Simulation time 3660356351 ps
CPU time 34.5 seconds
Started Jul 24 05:25:43 PM PDT 24
Finished Jul 24 05:26:18 PM PDT 24
Peak memory 206856 kb
Host smart-810772d8-c019-4540-a1a8-333e6fe45a42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24129
29434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.2412929434
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.877569950
Short name T2648
Test name
Test status
Simulation time 117769274 ps
CPU time 0.71 seconds
Started Jul 24 05:25:43 PM PDT 24
Finished Jul 24 05:25:49 PM PDT 24
Peak memory 206552 kb
Host smart-ead11448-ae09-4ae7-a15f-87b822bcae86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=877569950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.877569950
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.1320282839
Short name T2463
Test name
Test status
Simulation time 3746872891 ps
CPU time 4.37 seconds
Started Jul 24 05:25:42 PM PDT 24
Finished Jul 24 05:25:46 PM PDT 24
Peak memory 206984 kb
Host smart-a3ebb351-c8b2-4828-a2c2-abd1537865e2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1320282839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.1320282839
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.839551181
Short name T1210
Test name
Test status
Simulation time 13481532565 ps
CPU time 14.47 seconds
Started Jul 24 05:25:44 PM PDT 24
Finished Jul 24 05:25:58 PM PDT 24
Peak memory 206944 kb
Host smart-fcfd5666-7a5e-4b60-bfa7-b5f64f4895dc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=839551181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.839551181
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.418187612
Short name T828
Test name
Test status
Simulation time 23344306223 ps
CPU time 23.76 seconds
Started Jul 24 05:25:40 PM PDT 24
Finished Jul 24 05:26:04 PM PDT 24
Peak memory 206524 kb
Host smart-b0843511-2dbf-4e2b-938c-d34f62f86535
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=418187612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.418187612
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.4044620441
Short name T2197
Test name
Test status
Simulation time 150458134 ps
CPU time 0.8 seconds
Started Jul 24 05:25:35 PM PDT 24
Finished Jul 24 05:25:37 PM PDT 24
Peak memory 206596 kb
Host smart-9d6fe289-1f0a-460e-a140-987247f01dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40446
20441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.4044620441
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.2043709761
Short name T1880
Test name
Test status
Simulation time 147892932 ps
CPU time 0.83 seconds
Started Jul 24 05:25:34 PM PDT 24
Finished Jul 24 05:25:35 PM PDT 24
Peak memory 206576 kb
Host smart-615c31df-83b1-4d33-8f8a-a4e1f8e393cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20437
09761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.2043709761
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.3564480625
Short name T1436
Test name
Test status
Simulation time 227552413 ps
CPU time 0.92 seconds
Started Jul 24 05:25:48 PM PDT 24
Finished Jul 24 05:25:49 PM PDT 24
Peak memory 206524 kb
Host smart-200beda8-b10c-4332-8f07-1060e83335c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35644
80625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.3564480625
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.580284860
Short name T808
Test name
Test status
Simulation time 783599256 ps
CPU time 2.15 seconds
Started Jul 24 05:25:36 PM PDT 24
Finished Jul 24 05:25:38 PM PDT 24
Peak memory 206836 kb
Host smart-c35cb846-2553-46b0-b4ef-f3e8e11ca9e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58028
4860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.580284860
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.4066075302
Short name T1405
Test name
Test status
Simulation time 6713489191 ps
CPU time 13.65 seconds
Started Jul 24 05:25:38 PM PDT 24
Finished Jul 24 05:25:52 PM PDT 24
Peak memory 206892 kb
Host smart-56e0b819-09ae-42a6-861b-96bf5f515e6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40660
75302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.4066075302
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.2628681293
Short name T575
Test name
Test status
Simulation time 331694567 ps
CPU time 1.16 seconds
Started Jul 24 05:25:49 PM PDT 24
Finished Jul 24 05:25:50 PM PDT 24
Peak memory 206572 kb
Host smart-88be94d2-7815-411d-8db2-18864ca87ebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26286
81293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.2628681293
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.3979704409
Short name T2686
Test name
Test status
Simulation time 149779430 ps
CPU time 0.78 seconds
Started Jul 24 05:25:33 PM PDT 24
Finished Jul 24 05:25:33 PM PDT 24
Peak memory 206588 kb
Host smart-e5d66da1-7bf4-4aa2-8316-40a75559466b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39797
04409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.3979704409
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.789702677
Short name T580
Test name
Test status
Simulation time 32135943 ps
CPU time 0.65 seconds
Started Jul 24 05:25:48 PM PDT 24
Finished Jul 24 05:25:49 PM PDT 24
Peak memory 206536 kb
Host smart-79556842-2d9a-4bef-a14e-506cc43f6bba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78970
2677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.789702677
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.2990235307
Short name T1760
Test name
Test status
Simulation time 896438204 ps
CPU time 2.19 seconds
Started Jul 24 05:25:34 PM PDT 24
Finished Jul 24 05:25:36 PM PDT 24
Peak memory 206708 kb
Host smart-44ae2f17-afce-40cd-ad3b-32f67e1495a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29902
35307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.2990235307
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.512188089
Short name T990
Test name
Test status
Simulation time 289003763 ps
CPU time 1.66 seconds
Started Jul 24 05:25:38 PM PDT 24
Finished Jul 24 05:25:40 PM PDT 24
Peak memory 206824 kb
Host smart-6150afe7-0950-4271-add5-2e9141926796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51218
8089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.512188089
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.3723378446
Short name T961
Test name
Test status
Simulation time 209922767 ps
CPU time 0.83 seconds
Started Jul 24 05:25:34 PM PDT 24
Finished Jul 24 05:25:35 PM PDT 24
Peak memory 206560 kb
Host smart-727439e8-b729-40e3-af1b-385471b14f6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37233
78446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.3723378446
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.2777137237
Short name T391
Test name
Test status
Simulation time 169247957 ps
CPU time 0.75 seconds
Started Jul 24 05:26:02 PM PDT 24
Finished Jul 24 05:26:03 PM PDT 24
Peak memory 206592 kb
Host smart-e2cb9143-342b-4230-9253-9f71ecef2e1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27771
37237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.2777137237
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.790903080
Short name T952
Test name
Test status
Simulation time 197182941 ps
CPU time 0.98 seconds
Started Jul 24 05:25:35 PM PDT 24
Finished Jul 24 05:25:36 PM PDT 24
Peak memory 206592 kb
Host smart-34b848f0-3322-49c1-8bc2-36fc6044587c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79090
3080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.790903080
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.202448623
Short name T2120
Test name
Test status
Simulation time 8065075967 ps
CPU time 77.07 seconds
Started Jul 24 05:25:34 PM PDT 24
Finished Jul 24 05:26:52 PM PDT 24
Peak memory 206968 kb
Host smart-6d2a490e-4e54-450e-96c4-243e6459157c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=202448623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.202448623
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.799300758
Short name T2345
Test name
Test status
Simulation time 234034514 ps
CPU time 0.93 seconds
Started Jul 24 05:25:39 PM PDT 24
Finished Jul 24 05:25:40 PM PDT 24
Peak memory 206564 kb
Host smart-8de5d627-4e5b-481e-a5cd-268b2a5dd602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79930
0758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.799300758
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.1177877111
Short name T1303
Test name
Test status
Simulation time 23301727695 ps
CPU time 22.15 seconds
Started Jul 24 05:25:31 PM PDT 24
Finished Jul 24 05:25:53 PM PDT 24
Peak memory 206700 kb
Host smart-7919255c-4c18-4bec-9099-013a779c246d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11778
77111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.1177877111
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.3501974873
Short name T1695
Test name
Test status
Simulation time 3296063067 ps
CPU time 3.71 seconds
Started Jul 24 05:25:32 PM PDT 24
Finished Jul 24 05:25:36 PM PDT 24
Peak memory 206668 kb
Host smart-36c57b41-c29e-4865-a6e9-6a65e6237093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35019
74873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.3501974873
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.2241983307
Short name T1325
Test name
Test status
Simulation time 8739729729 ps
CPU time 240.31 seconds
Started Jul 24 05:25:39 PM PDT 24
Finished Jul 24 05:29:39 PM PDT 24
Peak memory 206980 kb
Host smart-2b37a22a-eedb-4668-8c94-0e93f1e133fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22419
83307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.2241983307
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.3370783507
Short name T1438
Test name
Test status
Simulation time 6161909349 ps
CPU time 177.81 seconds
Started Jul 24 05:25:53 PM PDT 24
Finished Jul 24 05:28:51 PM PDT 24
Peak memory 206792 kb
Host smart-bbc5e7c7-0065-4c8c-ba7d-fc7a9cecd7f5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3370783507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.3370783507
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.3630296613
Short name T1208
Test name
Test status
Simulation time 260880973 ps
CPU time 0.91 seconds
Started Jul 24 05:25:48 PM PDT 24
Finished Jul 24 05:25:49 PM PDT 24
Peak memory 206552 kb
Host smart-48d7081e-306e-4765-bcaf-725f95aa16a8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3630296613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.3630296613
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.3980187422
Short name T940
Test name
Test status
Simulation time 194406132 ps
CPU time 0.88 seconds
Started Jul 24 05:25:49 PM PDT 24
Finished Jul 24 05:25:50 PM PDT 24
Peak memory 206588 kb
Host smart-49838ff1-10e5-4d27-a2f5-85ccc8e2d138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39801
87422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.3980187422
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.2609406430
Short name T1185
Test name
Test status
Simulation time 4460213281 ps
CPU time 124.22 seconds
Started Jul 24 05:25:42 PM PDT 24
Finished Jul 24 05:27:47 PM PDT 24
Peak memory 206776 kb
Host smart-32aeb8dd-b418-4b1a-ac27-7e9ff8d349f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26094
06430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.2609406430
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.2302197823
Short name T2343
Test name
Test status
Simulation time 4396478406 ps
CPU time 31.67 seconds
Started Jul 24 05:25:43 PM PDT 24
Finished Jul 24 05:26:15 PM PDT 24
Peak memory 206924 kb
Host smart-ec7f4d0e-112d-413d-b8c7-1ed450a3f2b4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2302197823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.2302197823
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.339375635
Short name T2746
Test name
Test status
Simulation time 152566152 ps
CPU time 0.77 seconds
Started Jul 24 05:26:00 PM PDT 24
Finished Jul 24 05:26:01 PM PDT 24
Peak memory 206592 kb
Host smart-5b6b1746-6a86-4eda-9f68-69da4a650b73
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=339375635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.339375635
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.3755534675
Short name T1625
Test name
Test status
Simulation time 149648064 ps
CPU time 0.75 seconds
Started Jul 24 05:25:55 PM PDT 24
Finished Jul 24 05:25:56 PM PDT 24
Peak memory 206788 kb
Host smart-7262e51f-742e-44b5-bad0-a33658b06cc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37555
34675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.3755534675
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.846366886
Short name T1788
Test name
Test status
Simulation time 151208334 ps
CPU time 0.76 seconds
Started Jul 24 05:25:45 PM PDT 24
Finished Jul 24 05:25:46 PM PDT 24
Peak memory 206592 kb
Host smart-2ffe4c8a-4a63-4783-b9d1-c4def58c741f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84636
6886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.846366886
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.242381466
Short name T2419
Test name
Test status
Simulation time 191426415 ps
CPU time 0.79 seconds
Started Jul 24 05:25:44 PM PDT 24
Finished Jul 24 05:25:45 PM PDT 24
Peak memory 206556 kb
Host smart-d45783b1-0ca9-4541-a2b9-bf983132018e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24238
1466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.242381466
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.2309882259
Short name T537
Test name
Test status
Simulation time 178835716 ps
CPU time 0.87 seconds
Started Jul 24 05:25:47 PM PDT 24
Finished Jul 24 05:25:48 PM PDT 24
Peak memory 206528 kb
Host smart-c12ab717-f3ae-412c-8f23-aa6563e1aa4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23098
82259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.2309882259
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.4004657754
Short name T1183
Test name
Test status
Simulation time 164354618 ps
CPU time 0.78 seconds
Started Jul 24 05:25:59 PM PDT 24
Finished Jul 24 05:26:00 PM PDT 24
Peak memory 206776 kb
Host smart-7342fc21-70ce-4910-9a3d-7563727552f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40046
57754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.4004657754
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.493007204
Short name T1155
Test name
Test status
Simulation time 233642499 ps
CPU time 0.92 seconds
Started Jul 24 05:25:52 PM PDT 24
Finished Jul 24 05:25:53 PM PDT 24
Peak memory 206488 kb
Host smart-b8d7caf9-6fd6-40fe-9e33-c6255c79f5ae
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=493007204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.493007204
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.4293883954
Short name T922
Test name
Test status
Simulation time 142374399 ps
CPU time 0.77 seconds
Started Jul 24 05:25:51 PM PDT 24
Finished Jul 24 05:25:52 PM PDT 24
Peak memory 206660 kb
Host smart-79b8ba3d-73fb-48c8-b369-be52841cc2a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42938
83954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.4293883954
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.3820212116
Short name T2122
Test name
Test status
Simulation time 39632103 ps
CPU time 0.64 seconds
Started Jul 24 05:25:59 PM PDT 24
Finished Jul 24 05:26:00 PM PDT 24
Peak memory 206552 kb
Host smart-9d983456-ad4e-4986-9866-bbf977ce5d50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38202
12116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.3820212116
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.3366533888
Short name T2735
Test name
Test status
Simulation time 14473229991 ps
CPU time 31.74 seconds
Started Jul 24 05:25:43 PM PDT 24
Finished Jul 24 05:26:15 PM PDT 24
Peak memory 206956 kb
Host smart-e53ece3e-12ed-4051-b907-270f98c0ae3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33665
33888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.3366533888
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.1404893465
Short name T783
Test name
Test status
Simulation time 193894507 ps
CPU time 0.88 seconds
Started Jul 24 05:25:54 PM PDT 24
Finished Jul 24 05:25:55 PM PDT 24
Peak memory 206496 kb
Host smart-8fdbdd4a-8268-4adb-aa7d-48a48e716bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14048
93465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.1404893465
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.4233680834
Short name T514
Test name
Test status
Simulation time 233275080 ps
CPU time 0.89 seconds
Started Jul 24 05:25:44 PM PDT 24
Finished Jul 24 05:25:45 PM PDT 24
Peak memory 206604 kb
Host smart-a2defd35-be15-4a97-9e81-6c745fd7b63d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42336
80834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.4233680834
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.539870106
Short name T2670
Test name
Test status
Simulation time 224904005 ps
CPU time 0.85 seconds
Started Jul 24 05:26:00 PM PDT 24
Finished Jul 24 05:26:01 PM PDT 24
Peak memory 206784 kb
Host smart-1ab5a302-bd16-4184-b2fd-eab1e5c6569f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53987
0106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.539870106
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.1711772017
Short name T2562
Test name
Test status
Simulation time 185161496 ps
CPU time 0.83 seconds
Started Jul 24 05:25:40 PM PDT 24
Finished Jul 24 05:25:41 PM PDT 24
Peak memory 206548 kb
Host smart-b08ae308-ef5c-4edd-b357-8b0f0d0df424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17117
72017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.1711772017
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.2736635587
Short name T765
Test name
Test status
Simulation time 134531460 ps
CPU time 0.74 seconds
Started Jul 24 05:25:50 PM PDT 24
Finished Jul 24 05:25:51 PM PDT 24
Peak memory 206500 kb
Host smart-2098c260-9145-43e6-85c9-2a5e304dfbfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27366
35587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.2736635587
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.677025955
Short name T1839
Test name
Test status
Simulation time 154255336 ps
CPU time 0.82 seconds
Started Jul 24 05:25:43 PM PDT 24
Finished Jul 24 05:25:45 PM PDT 24
Peak memory 206540 kb
Host smart-ab16f456-bbe6-495a-a632-c6335f3e9372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67702
5955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.677025955
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.192824440
Short name T2705
Test name
Test status
Simulation time 156317053 ps
CPU time 0.78 seconds
Started Jul 24 05:26:12 PM PDT 24
Finished Jul 24 05:26:13 PM PDT 24
Peak memory 206596 kb
Host smart-3d68bc5a-3cc5-41ae-8925-afe74b39df0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19282
4440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.192824440
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.3359542179
Short name T767
Test name
Test status
Simulation time 231084670 ps
CPU time 0.92 seconds
Started Jul 24 05:25:44 PM PDT 24
Finished Jul 24 05:25:46 PM PDT 24
Peak memory 206516 kb
Host smart-91bc912c-e3e1-49dd-892e-2ad9046785ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33595
42179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.3359542179
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.2248016991
Short name T1564
Test name
Test status
Simulation time 3458029844 ps
CPU time 32.27 seconds
Started Jul 24 05:25:45 PM PDT 24
Finished Jul 24 05:26:17 PM PDT 24
Peak memory 206916 kb
Host smart-ec3ce429-fe2b-4136-831b-7008aae4a345
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2248016991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.2248016991
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.3062890143
Short name T639
Test name
Test status
Simulation time 165212667 ps
CPU time 0.8 seconds
Started Jul 24 05:25:50 PM PDT 24
Finished Jul 24 05:25:51 PM PDT 24
Peak memory 206564 kb
Host smart-db5e4e98-1ae4-4b91-85dc-638347e38a6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30628
90143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.3062890143
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.1665227442
Short name T1742
Test name
Test status
Simulation time 175900606 ps
CPU time 0.8 seconds
Started Jul 24 05:25:56 PM PDT 24
Finished Jul 24 05:25:57 PM PDT 24
Peak memory 206520 kb
Host smart-cf965e21-ed92-4b2c-b6f1-469bd82f0979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16652
27442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.1665227442
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.2568964165
Short name T804
Test name
Test status
Simulation time 1365231300 ps
CPU time 3.06 seconds
Started Jul 24 05:25:55 PM PDT 24
Finished Jul 24 05:25:59 PM PDT 24
Peak memory 206764 kb
Host smart-ba8f95d6-91bc-4c20-85ce-e968581d9032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25689
64165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.2568964165
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.4015169963
Short name T2034
Test name
Test status
Simulation time 3183897833 ps
CPU time 84.76 seconds
Started Jul 24 05:25:49 PM PDT 24
Finished Jul 24 05:27:14 PM PDT 24
Peak memory 206908 kb
Host smart-9c7510b8-8206-4adf-80dd-fe2593198d18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40151
69963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.4015169963
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.4272158369
Short name T2263
Test name
Test status
Simulation time 53754728 ps
CPU time 0.68 seconds
Started Jul 24 05:26:10 PM PDT 24
Finished Jul 24 05:26:11 PM PDT 24
Peak memory 206512 kb
Host smart-15cecd39-39a0-44f8-929a-16ed3da34e00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4272158369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.4272158369
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.1378520401
Short name T1312
Test name
Test status
Simulation time 4268615820 ps
CPU time 4.66 seconds
Started Jul 24 05:25:55 PM PDT 24
Finished Jul 24 05:26:00 PM PDT 24
Peak memory 206884 kb
Host smart-2a56ac6e-6849-4e3e-94b6-0dbe47ea097d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1378520401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.1378520401
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.3981989855
Short name T2583
Test name
Test status
Simulation time 13335861104 ps
CPU time 13.83 seconds
Started Jul 24 05:25:50 PM PDT 24
Finished Jul 24 05:26:04 PM PDT 24
Peak memory 206716 kb
Host smart-80d4f462-235a-4ce1-831d-718d3dfd3a19
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3981989855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.3981989855
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.4108595052
Short name T1602
Test name
Test status
Simulation time 23385982792 ps
CPU time 23.15 seconds
Started Jul 24 05:25:42 PM PDT 24
Finished Jul 24 05:26:06 PM PDT 24
Peak memory 206524 kb
Host smart-c4fd67d9-d432-4929-ae9b-d359f5060ee0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4108595052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.4108595052
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.1255809133
Short name T1459
Test name
Test status
Simulation time 202604205 ps
CPU time 0.87 seconds
Started Jul 24 05:25:44 PM PDT 24
Finished Jul 24 05:25:46 PM PDT 24
Peak memory 206520 kb
Host smart-03ac0ddd-37ee-44fe-9530-a5a5dc11e6d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12558
09133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.1255809133
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.847625564
Short name T1863
Test name
Test status
Simulation time 156474785 ps
CPU time 0.75 seconds
Started Jul 24 05:25:56 PM PDT 24
Finished Jul 24 05:25:57 PM PDT 24
Peak memory 206592 kb
Host smart-e2bc6c78-de40-4ffd-8c5e-e266c61514f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84762
5564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.847625564
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.639616027
Short name T1329
Test name
Test status
Simulation time 217603551 ps
CPU time 0.94 seconds
Started Jul 24 05:25:57 PM PDT 24
Finished Jul 24 05:25:58 PM PDT 24
Peak memory 206572 kb
Host smart-c755d322-7cd4-49e9-a1ca-84290d5827dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63961
6027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.639616027
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.4048462490
Short name T1727
Test name
Test status
Simulation time 335857167 ps
CPU time 1.04 seconds
Started Jul 24 05:25:41 PM PDT 24
Finished Jul 24 05:25:42 PM PDT 24
Peak memory 206608 kb
Host smart-7c10d69c-148c-4282-808c-548ab114b349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40484
62490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.4048462490
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.1156957195
Short name T2518
Test name
Test status
Simulation time 18039477711 ps
CPU time 36.84 seconds
Started Jul 24 05:25:46 PM PDT 24
Finished Jul 24 05:26:23 PM PDT 24
Peak memory 206692 kb
Host smart-d61ab66d-45b3-4ba0-b972-5a5194fa4713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11569
57195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.1156957195
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.3566360309
Short name T1610
Test name
Test status
Simulation time 437103298 ps
CPU time 1.37 seconds
Started Jul 24 05:25:44 PM PDT 24
Finished Jul 24 05:25:46 PM PDT 24
Peak memory 206560 kb
Host smart-41438998-545e-4ed1-970d-d53ab1b65303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35663
60309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.3566360309
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.96410528
Short name T2619
Test name
Test status
Simulation time 140441239 ps
CPU time 0.78 seconds
Started Jul 24 05:25:44 PM PDT 24
Finished Jul 24 05:25:45 PM PDT 24
Peak memory 206528 kb
Host smart-acde594a-b091-4fd8-b883-2359aaffadeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96410
528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.96410528
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.869540899
Short name T2447
Test name
Test status
Simulation time 64529154 ps
CPU time 0.66 seconds
Started Jul 24 05:26:01 PM PDT 24
Finished Jul 24 05:26:02 PM PDT 24
Peak memory 206592 kb
Host smart-171d6f71-be93-4157-a3b1-f0192b1b2dfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86954
0899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.869540899
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.2310213160
Short name T2398
Test name
Test status
Simulation time 1076106917 ps
CPU time 2.39 seconds
Started Jul 24 05:25:50 PM PDT 24
Finished Jul 24 05:25:53 PM PDT 24
Peak memory 206740 kb
Host smart-1efc3ba5-5407-4a6e-b7e9-362158b84033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23102
13160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.2310213160
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.4044770321
Short name T1352
Test name
Test status
Simulation time 348070001 ps
CPU time 1.87 seconds
Started Jul 24 05:25:40 PM PDT 24
Finished Jul 24 05:25:42 PM PDT 24
Peak memory 206832 kb
Host smart-05d1e50f-d1e5-43c4-81d8-fc3a052491e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40447
70321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.4044770321
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.1350497177
Short name T2070
Test name
Test status
Simulation time 191151405 ps
CPU time 0.82 seconds
Started Jul 24 05:25:55 PM PDT 24
Finished Jul 24 05:25:56 PM PDT 24
Peak memory 206608 kb
Host smart-4d1c0a83-e8f5-41a9-8a08-604da65d454a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13504
97177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.1350497177
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.1228377959
Short name T1192
Test name
Test status
Simulation time 153628113 ps
CPU time 0.75 seconds
Started Jul 24 05:25:48 PM PDT 24
Finished Jul 24 05:25:49 PM PDT 24
Peak memory 206548 kb
Host smart-3c45dfda-181b-40c8-ad1e-a9d49c1610b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12283
77959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.1228377959
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.2720636165
Short name T2644
Test name
Test status
Simulation time 174740686 ps
CPU time 0.83 seconds
Started Jul 24 05:25:40 PM PDT 24
Finished Jul 24 05:25:41 PM PDT 24
Peak memory 206580 kb
Host smart-f1af00ac-94c3-4a55-ab73-fda5f847f39e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27206
36165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.2720636165
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_iso_retraction.845003869
Short name T1081
Test name
Test status
Simulation time 8225797031 ps
CPU time 24.86 seconds
Started Jul 24 05:26:02 PM PDT 24
Finished Jul 24 05:26:27 PM PDT 24
Peak memory 206908 kb
Host smart-525d5ec9-3bbf-4283-a886-574355073d17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84500
3869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.845003869
Directory /workspace/15.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.2491064752
Short name T1099
Test name
Test status
Simulation time 244902132 ps
CPU time 0.85 seconds
Started Jul 24 05:25:47 PM PDT 24
Finished Jul 24 05:25:48 PM PDT 24
Peak memory 206596 kb
Host smart-2e5b02d5-cb41-4172-aca6-ef037f6968e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24910
64752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.2491064752
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.3540743031
Short name T758
Test name
Test status
Simulation time 23394959238 ps
CPU time 27.14 seconds
Started Jul 24 05:26:02 PM PDT 24
Finished Jul 24 05:26:30 PM PDT 24
Peak memory 206512 kb
Host smart-9e0050be-ec3b-422a-bfac-80e2ca9ac6d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35407
43031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.3540743031
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.1571013005
Short name T1831
Test name
Test status
Simulation time 3303745545 ps
CPU time 4.46 seconds
Started Jul 24 05:26:09 PM PDT 24
Finished Jul 24 05:26:14 PM PDT 24
Peak memory 206668 kb
Host smart-151be03d-979d-4a84-9d70-c3e15248d9b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15710
13005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.1571013005
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.252647698
Short name T897
Test name
Test status
Simulation time 6557420367 ps
CPU time 172.2 seconds
Started Jul 24 05:25:46 PM PDT 24
Finished Jul 24 05:28:38 PM PDT 24
Peak memory 206948 kb
Host smart-a2c74b94-7cd7-442c-85ee-f1885f1ab657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25264
7698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.252647698
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.2909274423
Short name T1700
Test name
Test status
Simulation time 4977236083 ps
CPU time 35.89 seconds
Started Jul 24 05:26:10 PM PDT 24
Finished Jul 24 05:26:46 PM PDT 24
Peak memory 206944 kb
Host smart-1b962c1e-5031-4830-b176-c77de17c09e3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2909274423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.2909274423
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.2673529528
Short name T2720
Test name
Test status
Simulation time 268122694 ps
CPU time 0.91 seconds
Started Jul 24 05:25:54 PM PDT 24
Finished Jul 24 05:25:55 PM PDT 24
Peak memory 206608 kb
Host smart-f5426721-cb5a-47c7-a156-a36212f5a1b4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2673529528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.2673529528
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.1865217453
Short name T228
Test name
Test status
Simulation time 185107599 ps
CPU time 0.91 seconds
Started Jul 24 05:26:02 PM PDT 24
Finished Jul 24 05:26:03 PM PDT 24
Peak memory 206616 kb
Host smart-c3da207d-956f-4ef5-9dfa-fb83baf97052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18652
17453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.1865217453
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.2688927461
Short name T1415
Test name
Test status
Simulation time 6406554010 ps
CPU time 173.65 seconds
Started Jul 24 05:25:45 PM PDT 24
Finished Jul 24 05:28:39 PM PDT 24
Peak memory 206896 kb
Host smart-ad30a324-9215-4854-bcd9-4ca44136fa5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26889
27461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.2688927461
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.1554989737
Short name T1135
Test name
Test status
Simulation time 3487155393 ps
CPU time 24.89 seconds
Started Jul 24 05:25:46 PM PDT 24
Finished Jul 24 05:26:11 PM PDT 24
Peak memory 206964 kb
Host smart-bebfad21-c37b-4cae-b6be-b98ab8ae06d2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1554989737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.1554989737
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.1711250572
Short name T2579
Test name
Test status
Simulation time 157734193 ps
CPU time 0.91 seconds
Started Jul 24 05:26:01 PM PDT 24
Finished Jul 24 05:26:02 PM PDT 24
Peak memory 206404 kb
Host smart-b275b3a1-7a3f-466f-a0f3-b17a7f3c2c3b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1711250572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.1711250572
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.1430850246
Short name T353
Test name
Test status
Simulation time 143846395 ps
CPU time 0.75 seconds
Started Jul 24 05:25:57 PM PDT 24
Finished Jul 24 05:25:58 PM PDT 24
Peak memory 206616 kb
Host smart-57a42400-d854-4a77-944c-6cb44d1d20f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14308
50246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.1430850246
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.4062395563
Short name T2047
Test name
Test status
Simulation time 166454787 ps
CPU time 0.79 seconds
Started Jul 24 05:25:52 PM PDT 24
Finished Jul 24 05:25:53 PM PDT 24
Peak memory 206516 kb
Host smart-30ea99c0-e3ac-4b36-bb02-335a446f1105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40623
95563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.4062395563
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.4263973803
Short name T1011
Test name
Test status
Simulation time 178259788 ps
CPU time 0.85 seconds
Started Jul 24 05:25:46 PM PDT 24
Finished Jul 24 05:25:47 PM PDT 24
Peak memory 206552 kb
Host smart-c399674b-6c3d-4628-9022-2592db894399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42639
73803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.4263973803
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.1590362577
Short name T2346
Test name
Test status
Simulation time 198702399 ps
CPU time 0.82 seconds
Started Jul 24 05:26:08 PM PDT 24
Finished Jul 24 05:26:09 PM PDT 24
Peak memory 206544 kb
Host smart-76c21418-05c5-4989-80b3-861644d37393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15903
62577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.1590362577
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.1791758549
Short name T1169
Test name
Test status
Simulation time 167548958 ps
CPU time 0.77 seconds
Started Jul 24 05:25:47 PM PDT 24
Finished Jul 24 05:25:48 PM PDT 24
Peak memory 206588 kb
Host smart-996810c2-5f8a-4f18-adaa-94cb09db3692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17917
58549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.1791758549
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.2657902055
Short name T1606
Test name
Test status
Simulation time 159207472 ps
CPU time 0.76 seconds
Started Jul 24 05:26:01 PM PDT 24
Finished Jul 24 05:26:02 PM PDT 24
Peak memory 206576 kb
Host smart-c324d63c-15dc-48f2-a2a1-8cde078e08f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26579
02055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.2657902055
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.2484178681
Short name T576
Test name
Test status
Simulation time 245672503 ps
CPU time 0.88 seconds
Started Jul 24 05:26:02 PM PDT 24
Finished Jul 24 05:26:03 PM PDT 24
Peak memory 206592 kb
Host smart-9cd4d756-e33c-407a-a370-de4bd9a2726b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2484178681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.2484178681
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.1278371364
Short name T2443
Test name
Test status
Simulation time 164543090 ps
CPU time 0.74 seconds
Started Jul 24 05:25:48 PM PDT 24
Finished Jul 24 05:25:49 PM PDT 24
Peak memory 206612 kb
Host smart-eb142597-84f6-46b0-8fe7-82bbd62a8a9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12783
71364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.1278371364
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.1590598864
Short name T998
Test name
Test status
Simulation time 40504313 ps
CPU time 0.65 seconds
Started Jul 24 05:26:07 PM PDT 24
Finished Jul 24 05:26:08 PM PDT 24
Peak memory 206600 kb
Host smart-da336241-4dca-4273-9eaf-e64568281240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15905
98864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.1590598864
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.428908934
Short name T240
Test name
Test status
Simulation time 9517979559 ps
CPU time 21.43 seconds
Started Jul 24 05:26:01 PM PDT 24
Finished Jul 24 05:26:23 PM PDT 24
Peak memory 206988 kb
Host smart-482e471e-39c5-45c5-86ef-b87b10384b10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42890
8934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.428908934
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.2991111066
Short name T2560
Test name
Test status
Simulation time 185375350 ps
CPU time 0.87 seconds
Started Jul 24 05:25:59 PM PDT 24
Finished Jul 24 05:26:00 PM PDT 24
Peak memory 206576 kb
Host smart-f224e849-7d7c-4772-ad5b-99e134133ded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29911
11066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.2991111066
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.3825399986
Short name T1861
Test name
Test status
Simulation time 224900877 ps
CPU time 0.87 seconds
Started Jul 24 05:26:06 PM PDT 24
Finished Jul 24 05:26:07 PM PDT 24
Peak memory 206564 kb
Host smart-749f7d0e-2ca2-4ba5-b497-815aef17e7e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38253
99986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.3825399986
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.1602763760
Short name T2124
Test name
Test status
Simulation time 170140762 ps
CPU time 0.8 seconds
Started Jul 24 05:25:51 PM PDT 24
Finished Jul 24 05:25:52 PM PDT 24
Peak memory 206164 kb
Host smart-922b15dc-f10e-4139-8b23-f8acad077f8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16027
63760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.1602763760
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.1600872671
Short name T1823
Test name
Test status
Simulation time 247501570 ps
CPU time 0.85 seconds
Started Jul 24 05:25:48 PM PDT 24
Finished Jul 24 05:25:49 PM PDT 24
Peak memory 206592 kb
Host smart-7899da43-77af-455a-9076-e4a10840aa1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16008
72671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.1600872671
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.1631688047
Short name T1857
Test name
Test status
Simulation time 196723525 ps
CPU time 0.87 seconds
Started Jul 24 05:25:53 PM PDT 24
Finished Jul 24 05:25:54 PM PDT 24
Peak memory 206580 kb
Host smart-7f81fa01-a148-41aa-8342-9ee7d03f8671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16316
88047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.1631688047
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.2321330609
Short name T2641
Test name
Test status
Simulation time 153755610 ps
CPU time 0.77 seconds
Started Jul 24 05:25:51 PM PDT 24
Finished Jul 24 05:25:52 PM PDT 24
Peak memory 206220 kb
Host smart-afcac7d1-8179-41d2-8273-92ad92e31339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23213
30609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.2321330609
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.669495539
Short name T448
Test name
Test status
Simulation time 181815058 ps
CPU time 0.79 seconds
Started Jul 24 05:25:59 PM PDT 24
Finished Jul 24 05:26:06 PM PDT 24
Peak memory 206620 kb
Host smart-8c6b53d2-87c1-4c7f-b6da-6905757b690a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66949
5539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.669495539
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.599360349
Short name T2079
Test name
Test status
Simulation time 236699606 ps
CPU time 1.02 seconds
Started Jul 24 05:25:47 PM PDT 24
Finished Jul 24 05:25:48 PM PDT 24
Peak memory 206636 kb
Host smart-169e29e0-b8e5-494c-b8f6-02c0d2230c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59936
0349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.599360349
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.4154820895
Short name T851
Test name
Test status
Simulation time 7316923481 ps
CPU time 49.45 seconds
Started Jul 24 05:25:54 PM PDT 24
Finished Jul 24 05:26:43 PM PDT 24
Peak memory 206868 kb
Host smart-3d872652-4f61-4ab4-a434-6df63fa151c2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4154820895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.4154820895
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.170015794
Short name T1158
Test name
Test status
Simulation time 175260863 ps
CPU time 0.81 seconds
Started Jul 24 05:26:01 PM PDT 24
Finished Jul 24 05:26:02 PM PDT 24
Peak memory 206592 kb
Host smart-b176dae3-51cc-4cca-9142-8f7b6afb52c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17001
5794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.170015794
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.1503608436
Short name T1455
Test name
Test status
Simulation time 159424431 ps
CPU time 0.79 seconds
Started Jul 24 05:25:48 PM PDT 24
Finished Jul 24 05:25:49 PM PDT 24
Peak memory 206660 kb
Host smart-9bf17a76-3705-4334-a907-d36668d5db1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15036
08436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.1503608436
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.3784268970
Short name T1377
Test name
Test status
Simulation time 528953944 ps
CPU time 1.47 seconds
Started Jul 24 05:26:06 PM PDT 24
Finished Jul 24 05:26:08 PM PDT 24
Peak memory 206488 kb
Host smart-395641f2-1550-4d46-95ed-e693244f3d39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37842
68970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.3784268970
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.759313246
Short name T2675
Test name
Test status
Simulation time 7644813694 ps
CPU time 51.38 seconds
Started Jul 24 05:26:00 PM PDT 24
Finished Jul 24 05:26:52 PM PDT 24
Peak memory 206692 kb
Host smart-bb5bec69-4b2c-4e72-a592-c62760e22d2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75931
3246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.759313246
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.1421214682
Short name T497
Test name
Test status
Simulation time 69307718 ps
CPU time 0.7 seconds
Started Jul 24 05:26:06 PM PDT 24
Finished Jul 24 05:26:07 PM PDT 24
Peak memory 206616 kb
Host smart-2b6bcb39-042e-4cff-8389-254e687f59e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1421214682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.1421214682
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.152282740
Short name T1762
Test name
Test status
Simulation time 3421187311 ps
CPU time 4.75 seconds
Started Jul 24 05:26:01 PM PDT 24
Finished Jul 24 05:26:06 PM PDT 24
Peak memory 206800 kb
Host smart-de3c9c26-fe92-4fb7-be18-542f7429e8b2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=152282740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.152282740
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.3057062251
Short name T1473
Test name
Test status
Simulation time 13357808062 ps
CPU time 12.4 seconds
Started Jul 24 05:25:52 PM PDT 24
Finished Jul 24 05:26:04 PM PDT 24
Peak memory 206716 kb
Host smart-c45447aa-5fd5-4e1a-a132-67323fea76e5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3057062251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.3057062251
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.2744504495
Short name T547
Test name
Test status
Simulation time 23449786773 ps
CPU time 23.4 seconds
Started Jul 24 05:25:56 PM PDT 24
Finished Jul 24 05:26:20 PM PDT 24
Peak memory 206888 kb
Host smart-b5e6f3eb-25c5-43ec-b19c-1ebb70589174
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2744504495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.2744504495
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.1322791803
Short name T383
Test name
Test status
Simulation time 180017867 ps
CPU time 0.84 seconds
Started Jul 24 05:25:47 PM PDT 24
Finished Jul 24 05:25:48 PM PDT 24
Peak memory 206536 kb
Host smart-a6e3d3bd-2938-4445-a4be-380a2f2afee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13227
91803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.1322791803
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.2644036875
Short name T2355
Test name
Test status
Simulation time 217199781 ps
CPU time 0.84 seconds
Started Jul 24 05:25:54 PM PDT 24
Finished Jul 24 05:25:55 PM PDT 24
Peak memory 206512 kb
Host smart-8f542deb-0a42-4dc0-9820-d7cfa25adc70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26440
36875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.2644036875
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.2461393218
Short name T799
Test name
Test status
Simulation time 525172599 ps
CPU time 1.53 seconds
Started Jul 24 05:25:57 PM PDT 24
Finished Jul 24 05:25:59 PM PDT 24
Peak memory 206764 kb
Host smart-fd7115a7-a775-4da2-939d-4a129562b445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24613
93218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.2461393218
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.4226348776
Short name T1190
Test name
Test status
Simulation time 540447368 ps
CPU time 1.39 seconds
Started Jul 24 05:26:03 PM PDT 24
Finished Jul 24 05:26:04 PM PDT 24
Peak memory 206564 kb
Host smart-e8959f9a-7862-45d9-88ef-2ea94111135f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42263
48776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.4226348776
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.1967181016
Short name T1620
Test name
Test status
Simulation time 15837696615 ps
CPU time 30.23 seconds
Started Jul 24 05:26:09 PM PDT 24
Finished Jul 24 05:26:39 PM PDT 24
Peak memory 206960 kb
Host smart-eb46528b-e9ec-422b-a4e5-0b502b9b3201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19671
81016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.1967181016
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.1546905255
Short name T311
Test name
Test status
Simulation time 482585930 ps
CPU time 1.35 seconds
Started Jul 24 05:25:50 PM PDT 24
Finished Jul 24 05:25:51 PM PDT 24
Peak memory 206608 kb
Host smart-7ac70b9f-4e94-46c3-a0ea-93cb92ad6a51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15469
05255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.1546905255
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.2664871062
Short name T2585
Test name
Test status
Simulation time 190980266 ps
CPU time 0.78 seconds
Started Jul 24 05:25:46 PM PDT 24
Finished Jul 24 05:25:47 PM PDT 24
Peak memory 206600 kb
Host smart-b74ef1b8-428d-40a0-9780-e4142b412379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26648
71062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.2664871062
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.3298222475
Short name T1765
Test name
Test status
Simulation time 33290701 ps
CPU time 0.66 seconds
Started Jul 24 05:25:49 PM PDT 24
Finished Jul 24 05:25:50 PM PDT 24
Peak memory 206472 kb
Host smart-0b731ad0-aad0-4c32-9cdd-55bdc8dba905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32982
22475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.3298222475
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.2605422271
Short name T526
Test name
Test status
Simulation time 724852951 ps
CPU time 1.8 seconds
Started Jul 24 05:25:49 PM PDT 24
Finished Jul 24 05:25:51 PM PDT 24
Peak memory 206652 kb
Host smart-9511083d-64af-4c9a-bd57-44482326f503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26054
22271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.2605422271
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.1137420342
Short name T170
Test name
Test status
Simulation time 218601764 ps
CPU time 1.58 seconds
Started Jul 24 05:25:54 PM PDT 24
Finished Jul 24 05:25:56 PM PDT 24
Peak memory 206788 kb
Host smart-79d7a19d-0923-4846-b874-3b0cacf92ac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11374
20342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.1137420342
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.1594505527
Short name T2701
Test name
Test status
Simulation time 277253226 ps
CPU time 0.99 seconds
Started Jul 24 05:25:59 PM PDT 24
Finished Jul 24 05:26:00 PM PDT 24
Peak memory 206580 kb
Host smart-5064f037-b2a0-4675-8fa7-ead4623c4e11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15945
05527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.1594505527
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.2912005094
Short name T1952
Test name
Test status
Simulation time 145928742 ps
CPU time 0.76 seconds
Started Jul 24 05:26:00 PM PDT 24
Finished Jul 24 05:26:01 PM PDT 24
Peak memory 206560 kb
Host smart-14249bff-b569-4716-b754-bb7943bd458b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29120
05094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.2912005094
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.4018305313
Short name T572
Test name
Test status
Simulation time 156271249 ps
CPU time 0.79 seconds
Started Jul 24 05:25:57 PM PDT 24
Finished Jul 24 05:25:58 PM PDT 24
Peak memory 206572 kb
Host smart-6314a9b5-414d-4315-b0d4-0e947d37cfb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40183
05313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.4018305313
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.2751073878
Short name T2106
Test name
Test status
Simulation time 7913035506 ps
CPU time 219.7 seconds
Started Jul 24 05:26:07 PM PDT 24
Finished Jul 24 05:29:47 PM PDT 24
Peak memory 206968 kb
Host smart-5583b3d8-6776-47ee-9476-8ea78836bbc5
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2751073878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.2751073878
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/16.usbdev_iso_retraction.2080162563
Short name T2374
Test name
Test status
Simulation time 4313116478 ps
CPU time 13.39 seconds
Started Jul 24 05:26:03 PM PDT 24
Finished Jul 24 05:26:17 PM PDT 24
Peak memory 206868 kb
Host smart-6f325fc2-09ea-40d4-91ec-5a57523bdfc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20801
62563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.2080162563
Directory /workspace/16.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.3011324156
Short name T2738
Test name
Test status
Simulation time 180818728 ps
CPU time 0.84 seconds
Started Jul 24 05:26:00 PM PDT 24
Finished Jul 24 05:26:01 PM PDT 24
Peak memory 206580 kb
Host smart-d9f37be4-3bdf-4b64-9753-fa83ac1a7876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30113
24156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.3011324156
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.3737688408
Short name T1028
Test name
Test status
Simulation time 23313759965 ps
CPU time 22.29 seconds
Started Jul 24 05:26:01 PM PDT 24
Finished Jul 24 05:26:24 PM PDT 24
Peak memory 206704 kb
Host smart-c0a8e69c-ab2a-4844-bee1-9d32b28dcfaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37376
88408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.3737688408
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.3847236779
Short name T2320
Test name
Test status
Simulation time 3342211572 ps
CPU time 4.46 seconds
Started Jul 24 05:25:55 PM PDT 24
Finished Jul 24 05:26:00 PM PDT 24
Peak memory 206684 kb
Host smart-16c4c3da-e6b8-48b4-8be8-07898ee4953f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38472
36779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.3847236779
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.1124884207
Short name T1041
Test name
Test status
Simulation time 6326785200 ps
CPU time 58.58 seconds
Started Jul 24 05:25:57 PM PDT 24
Finished Jul 24 05:26:56 PM PDT 24
Peak memory 206984 kb
Host smart-678b9ab3-a600-46f9-91ed-b67d25af862d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11248
84207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.1124884207
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.3897955933
Short name T1280
Test name
Test status
Simulation time 7233167168 ps
CPU time 62.82 seconds
Started Jul 24 05:25:53 PM PDT 24
Finished Jul 24 05:26:56 PM PDT 24
Peak memory 206928 kb
Host smart-cf11bbc3-7e53-4164-9a9d-69161b6fd9e6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3897955933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.3897955933
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.3462729567
Short name T999
Test name
Test status
Simulation time 236113611 ps
CPU time 0.98 seconds
Started Jul 24 05:25:52 PM PDT 24
Finished Jul 24 05:25:53 PM PDT 24
Peak memory 206600 kb
Host smart-7bd826fc-4527-45fc-8ba2-ec11ddfe6118
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3462729567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.3462729567
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.1349257723
Short name T2654
Test name
Test status
Simulation time 212139602 ps
CPU time 0.87 seconds
Started Jul 24 05:26:09 PM PDT 24
Finished Jul 24 05:26:10 PM PDT 24
Peak memory 206452 kb
Host smart-7dcd39d8-50bb-4bfa-9a9a-55108151dc8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13492
57723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.1349257723
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.3250311415
Short name T1285
Test name
Test status
Simulation time 4445617250 ps
CPU time 42.62 seconds
Started Jul 24 05:26:03 PM PDT 24
Finished Jul 24 05:26:46 PM PDT 24
Peak memory 206816 kb
Host smart-10ca86b1-fb0b-47e8-bb71-81262a12f6ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32503
11415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.3250311415
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.1376225988
Short name T2375
Test name
Test status
Simulation time 3949423001 ps
CPU time 35.91 seconds
Started Jul 24 05:26:03 PM PDT 24
Finished Jul 24 05:26:39 PM PDT 24
Peak memory 206904 kb
Host smart-ff29c659-e379-40c3-9530-e3018ab33313
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1376225988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.1376225988
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.583547311
Short name T2100
Test name
Test status
Simulation time 149925249 ps
CPU time 0.79 seconds
Started Jul 24 05:26:04 PM PDT 24
Finished Jul 24 05:26:05 PM PDT 24
Peak memory 206584 kb
Host smart-0176608b-fbea-4ca7-bf95-79d14b98dd83
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=583547311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.583547311
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.736515432
Short name T1555
Test name
Test status
Simulation time 162996868 ps
CPU time 0.8 seconds
Started Jul 24 05:26:05 PM PDT 24
Finished Jul 24 05:26:06 PM PDT 24
Peak memory 206516 kb
Host smart-8d7be1fc-8260-4697-afee-7d53e84ce2ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73651
5432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.736515432
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.2672932411
Short name T2603
Test name
Test status
Simulation time 185670570 ps
CPU time 0.82 seconds
Started Jul 24 05:26:05 PM PDT 24
Finished Jul 24 05:26:06 PM PDT 24
Peak memory 206536 kb
Host smart-19372641-ecb9-4de2-a8be-1b6c4da068d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26729
32411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.2672932411
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.3668014290
Short name T1739
Test name
Test status
Simulation time 172651137 ps
CPU time 0.79 seconds
Started Jul 24 05:26:03 PM PDT 24
Finished Jul 24 05:26:04 PM PDT 24
Peak memory 206596 kb
Host smart-8dea1506-1901-4dbb-9b3c-b2b166b765bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36680
14290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.3668014290
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.2168025908
Short name T458
Test name
Test status
Simulation time 153017275 ps
CPU time 0.81 seconds
Started Jul 24 05:26:02 PM PDT 24
Finished Jul 24 05:26:03 PM PDT 24
Peak memory 206548 kb
Host smart-b62693f1-a9e4-4088-ada1-faed76697dd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21680
25908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.2168025908
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.339551215
Short name T860
Test name
Test status
Simulation time 203659011 ps
CPU time 0.88 seconds
Started Jul 24 05:26:05 PM PDT 24
Finished Jul 24 05:26:07 PM PDT 24
Peak memory 206596 kb
Host smart-527cd14f-982e-4253-bdc5-eeb761f28bd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33955
1215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.339551215
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.2043773983
Short name T896
Test name
Test status
Simulation time 216813272 ps
CPU time 0.93 seconds
Started Jul 24 05:26:05 PM PDT 24
Finished Jul 24 05:26:07 PM PDT 24
Peak memory 206500 kb
Host smart-225f02b8-3dc5-494e-8cac-83b8a124a46e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2043773983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.2043773983
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.1684213340
Short name T30
Test name
Test status
Simulation time 149536762 ps
CPU time 0.73 seconds
Started Jul 24 05:26:06 PM PDT 24
Finished Jul 24 05:26:07 PM PDT 24
Peak memory 206564 kb
Host smart-0ac4616f-762a-46d4-b0da-5ffc7490cc9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16842
13340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.1684213340
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.2019338947
Short name T1282
Test name
Test status
Simulation time 36425507 ps
CPU time 0.6 seconds
Started Jul 24 05:26:00 PM PDT 24
Finished Jul 24 05:26:01 PM PDT 24
Peak memory 206572 kb
Host smart-7fd8d154-a914-4125-a59f-6d0d3d2aaa55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20193
38947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.2019338947
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.489111822
Short name T546
Test name
Test status
Simulation time 10664100467 ps
CPU time 23.25 seconds
Started Jul 24 05:25:55 PM PDT 24
Finished Jul 24 05:26:18 PM PDT 24
Peak memory 206984 kb
Host smart-8f218379-4498-4cbe-8ca4-5e2c7f5ad032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48911
1822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.489111822
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.3000882908
Short name T694
Test name
Test status
Simulation time 196924977 ps
CPU time 0.92 seconds
Started Jul 24 05:26:07 PM PDT 24
Finished Jul 24 05:26:09 PM PDT 24
Peak memory 206600 kb
Host smart-b33251b2-c5e7-4698-b455-59d50bbc5daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30008
82908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.3000882908
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.2158249938
Short name T1341
Test name
Test status
Simulation time 220837759 ps
CPU time 0.96 seconds
Started Jul 24 05:26:03 PM PDT 24
Finished Jul 24 05:26:05 PM PDT 24
Peak memory 206516 kb
Host smart-ae29764c-46aa-4a83-8e62-2de5fdd6c03f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21582
49938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.2158249938
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.3310581979
Short name T1604
Test name
Test status
Simulation time 239749983 ps
CPU time 0.9 seconds
Started Jul 24 05:25:56 PM PDT 24
Finished Jul 24 05:25:57 PM PDT 24
Peak memory 206636 kb
Host smart-fa296087-bb40-457f-820d-c09492ea32df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33105
81979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.3310581979
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.1078215449
Short name T1887
Test name
Test status
Simulation time 188384302 ps
CPU time 0.81 seconds
Started Jul 24 05:26:02 PM PDT 24
Finished Jul 24 05:26:03 PM PDT 24
Peak memory 206508 kb
Host smart-a3eb4dad-5cf5-468e-9b22-a7277d922592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10782
15449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.1078215449
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.126017812
Short name T1643
Test name
Test status
Simulation time 134023188 ps
CPU time 0.74 seconds
Started Jul 24 05:26:16 PM PDT 24
Finished Jul 24 05:26:17 PM PDT 24
Peak memory 206484 kb
Host smart-55e49358-c377-43de-92e3-9cfec00b26ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12601
7812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.126017812
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.1481640317
Short name T396
Test name
Test status
Simulation time 162740318 ps
CPU time 0.82 seconds
Started Jul 24 05:26:06 PM PDT 24
Finished Jul 24 05:26:08 PM PDT 24
Peak memory 206776 kb
Host smart-486f5658-6ea5-49d8-b50b-23d3f864652e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14816
40317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.1481640317
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.2001609738
Short name T641
Test name
Test status
Simulation time 153158816 ps
CPU time 0.78 seconds
Started Jul 24 05:26:09 PM PDT 24
Finished Jul 24 05:26:10 PM PDT 24
Peak memory 206432 kb
Host smart-7475cb4a-3b79-4827-b2db-11a56e6912e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20016
09738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.2001609738
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.675395843
Short name T229
Test name
Test status
Simulation time 260583938 ps
CPU time 0.91 seconds
Started Jul 24 05:26:16 PM PDT 24
Finished Jul 24 05:26:17 PM PDT 24
Peak memory 206596 kb
Host smart-be94be11-67ea-42f9-b86b-5f03dd236d98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67539
5843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.675395843
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.2467410807
Short name T1148
Test name
Test status
Simulation time 3837979120 ps
CPU time 34.75 seconds
Started Jul 24 05:26:06 PM PDT 24
Finished Jul 24 05:26:41 PM PDT 24
Peak memory 206892 kb
Host smart-7ed8ad1d-b4f2-49b6-bb86-1fbf3ea7fa01
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2467410807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.2467410807
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.695085355
Short name T2213
Test name
Test status
Simulation time 196742492 ps
CPU time 0.81 seconds
Started Jul 24 05:26:05 PM PDT 24
Finished Jul 24 05:26:06 PM PDT 24
Peak memory 206516 kb
Host smart-3340fd97-372b-4ff1-be21-6186bcba8859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69508
5355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.695085355
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.1540426885
Short name T1387
Test name
Test status
Simulation time 182454111 ps
CPU time 0.83 seconds
Started Jul 24 05:26:02 PM PDT 24
Finished Jul 24 05:26:03 PM PDT 24
Peak memory 206516 kb
Host smart-c953e348-888d-4bbd-afae-32fd3fd07331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15404
26885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.1540426885
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.1421683717
Short name T1853
Test name
Test status
Simulation time 891860360 ps
CPU time 2.02 seconds
Started Jul 24 05:26:06 PM PDT 24
Finished Jul 24 05:26:09 PM PDT 24
Peak memory 206836 kb
Host smart-45c45186-34c7-4753-8378-5d9cc58f27a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14216
83717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.1421683717
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.3461913236
Short name T1756
Test name
Test status
Simulation time 4258277585 ps
CPU time 111.52 seconds
Started Jul 24 05:26:11 PM PDT 24
Finished Jul 24 05:28:03 PM PDT 24
Peak memory 206924 kb
Host smart-afab7d4e-05b9-4b23-8717-06242cbdd54e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34619
13236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.3461913236
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.1788226937
Short name T1142
Test name
Test status
Simulation time 43357474 ps
CPU time 0.68 seconds
Started Jul 24 05:26:16 PM PDT 24
Finished Jul 24 05:26:17 PM PDT 24
Peak memory 206576 kb
Host smart-84a3b957-06df-40c8-a776-bf31ea39e0bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1788226937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.1788226937
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.3850933355
Short name T2531
Test name
Test status
Simulation time 4378807300 ps
CPU time 5.87 seconds
Started Jul 24 05:26:06 PM PDT 24
Finished Jul 24 05:26:12 PM PDT 24
Peak memory 206964 kb
Host smart-71b54194-3aa0-430a-bf42-2c209c5f1ff2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3850933355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.3850933355
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.2812973008
Short name T2639
Test name
Test status
Simulation time 13387241715 ps
CPU time 12.89 seconds
Started Jul 24 05:25:58 PM PDT 24
Finished Jul 24 05:26:11 PM PDT 24
Peak memory 206552 kb
Host smart-6acac5ff-76a8-4cf6-9903-0d3c69c52508
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2812973008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.2812973008
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.2985208757
Short name T2149
Test name
Test status
Simulation time 23343834923 ps
CPU time 22.48 seconds
Started Jul 24 05:26:08 PM PDT 24
Finished Jul 24 05:26:30 PM PDT 24
Peak memory 206736 kb
Host smart-99b00cb5-ae2c-4e1f-9af8-44386177f729
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2985208757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.2985208757
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.2251351987
Short name T1570
Test name
Test status
Simulation time 151025366 ps
CPU time 0.79 seconds
Started Jul 24 05:26:05 PM PDT 24
Finished Jul 24 05:26:06 PM PDT 24
Peak memory 206520 kb
Host smart-8cabe84b-3f59-4fcd-917c-4a01de428409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22513
51987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.2251351987
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.793635538
Short name T1513
Test name
Test status
Simulation time 162362557 ps
CPU time 0.83 seconds
Started Jul 24 05:25:57 PM PDT 24
Finished Jul 24 05:25:58 PM PDT 24
Peak memory 206576 kb
Host smart-079df233-4b41-461e-96ae-fdff67e07746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79363
5538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.793635538
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.10994793
Short name T2142
Test name
Test status
Simulation time 369914104 ps
CPU time 1.3 seconds
Started Jul 24 05:26:24 PM PDT 24
Finished Jul 24 05:26:26 PM PDT 24
Peak memory 206556 kb
Host smart-5f2e22e4-4e9a-42be-8d67-5c0d8de0f5be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10994
793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.10994793
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.2950519301
Short name T676
Test name
Test status
Simulation time 421958753 ps
CPU time 1.32 seconds
Started Jul 24 05:26:09 PM PDT 24
Finished Jul 24 05:26:11 PM PDT 24
Peak memory 206560 kb
Host smart-307ee14d-4098-4948-8121-406477c4f6e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29505
19301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.2950519301
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.2255341666
Short name T85
Test name
Test status
Simulation time 16939923844 ps
CPU time 30.35 seconds
Started Jul 24 05:26:02 PM PDT 24
Finished Jul 24 05:26:32 PM PDT 24
Peak memory 206748 kb
Host smart-55d9fae1-7d19-45ff-a10a-4431dbc5359d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22553
41666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.2255341666
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.642784871
Short name T881
Test name
Test status
Simulation time 304003838 ps
CPU time 1.14 seconds
Started Jul 24 05:26:02 PM PDT 24
Finished Jul 24 05:26:03 PM PDT 24
Peak memory 206504 kb
Host smart-dc6a00d4-42fc-4600-b446-8e54cde7eb67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64278
4871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.642784871
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.2010636252
Short name T1121
Test name
Test status
Simulation time 137829283 ps
CPU time 0.75 seconds
Started Jul 24 05:25:59 PM PDT 24
Finished Jul 24 05:26:00 PM PDT 24
Peak memory 206640 kb
Host smart-a4dd5872-b799-42a6-b6f8-8efa34f09460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20106
36252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.2010636252
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.1193411480
Short name T939
Test name
Test status
Simulation time 38514067 ps
CPU time 0.66 seconds
Started Jul 24 05:26:00 PM PDT 24
Finished Jul 24 05:26:01 PM PDT 24
Peak memory 206540 kb
Host smart-5ad685a9-437f-4917-9d7c-2a2e0db3d2f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11934
11480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.1193411480
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.2654574823
Short name T1297
Test name
Test status
Simulation time 1024148523 ps
CPU time 2.77 seconds
Started Jul 24 05:25:59 PM PDT 24
Finished Jul 24 05:26:02 PM PDT 24
Peak memory 206776 kb
Host smart-f724cf0e-a8db-4ebb-8724-2c24632dd2af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26545
74823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.2654574823
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.4130898972
Short name T1556
Test name
Test status
Simulation time 169951384 ps
CPU time 1.4 seconds
Started Jul 24 05:26:03 PM PDT 24
Finished Jul 24 05:26:05 PM PDT 24
Peak memory 206756 kb
Host smart-034ee655-8990-4863-9767-f0f1d2e7bd24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41308
98972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.4130898972
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.4047036144
Short name T1603
Test name
Test status
Simulation time 167305955 ps
CPU time 0.81 seconds
Started Jul 24 05:26:01 PM PDT 24
Finished Jul 24 05:26:02 PM PDT 24
Peak memory 206588 kb
Host smart-e7a4437c-bef1-4e3a-9410-4a3fc7495168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40470
36144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.4047036144
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.3242577319
Short name T1267
Test name
Test status
Simulation time 138660782 ps
CPU time 0.77 seconds
Started Jul 24 05:26:05 PM PDT 24
Finished Jul 24 05:26:06 PM PDT 24
Peak memory 206508 kb
Host smart-97f5fcf7-f8c9-41f8-abab-80c21b3bf183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32425
77319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.3242577319
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.3942201915
Short name T615
Test name
Test status
Simulation time 218603692 ps
CPU time 0.94 seconds
Started Jul 24 05:26:20 PM PDT 24
Finished Jul 24 05:26:27 PM PDT 24
Peak memory 206596 kb
Host smart-ec3ace39-6472-4190-8bc7-aa9976f9f63f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39422
01915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.3942201915
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.4115717837
Short name T1440
Test name
Test status
Simulation time 6167933533 ps
CPU time 169.15 seconds
Started Jul 24 05:26:05 PM PDT 24
Finished Jul 24 05:28:55 PM PDT 24
Peak memory 206920 kb
Host smart-de94776d-5c06-45a8-bdb9-b63762c8ceee
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4115717837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.4115717837
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/17.usbdev_iso_retraction.2092033604
Short name T2524
Test name
Test status
Simulation time 11581921953 ps
CPU time 93.05 seconds
Started Jul 24 05:26:06 PM PDT 24
Finished Jul 24 05:27:40 PM PDT 24
Peak memory 206872 kb
Host smart-6c5ffbe4-bf95-4e4a-8c8a-c2e0e2386403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20920
33604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.2092033604
Directory /workspace/17.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.2674371696
Short name T752
Test name
Test status
Simulation time 157836962 ps
CPU time 0.8 seconds
Started Jul 24 05:26:04 PM PDT 24
Finished Jul 24 05:26:06 PM PDT 24
Peak memory 206528 kb
Host smart-98c59152-4c64-4e86-9fb9-2aaee335ba4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26743
71696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.2674371696
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.1149683145
Short name T1768
Test name
Test status
Simulation time 23302518873 ps
CPU time 24.33 seconds
Started Jul 24 05:26:32 PM PDT 24
Finished Jul 24 05:26:56 PM PDT 24
Peak memory 206664 kb
Host smart-4a646a28-3095-4d7b-ba02-e41a4de01aa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11496
83145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.1149683145
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.2049869132
Short name T1774
Test name
Test status
Simulation time 3357254691 ps
CPU time 3.55 seconds
Started Jul 24 05:26:06 PM PDT 24
Finished Jul 24 05:26:10 PM PDT 24
Peak memory 206680 kb
Host smart-0f43a129-7a8a-4580-9e8b-1afe8827bf85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20498
69132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.2049869132
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.3286347326
Short name T870
Test name
Test status
Simulation time 6466822985 ps
CPU time 172.28 seconds
Started Jul 24 05:26:17 PM PDT 24
Finished Jul 24 05:29:09 PM PDT 24
Peak memory 206836 kb
Host smart-0d7303f1-4b45-4547-b987-2b01d4b4f817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32863
47326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.3286347326
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.1253475688
Short name T1463
Test name
Test status
Simulation time 5375679212 ps
CPU time 38.46 seconds
Started Jul 24 05:26:07 PM PDT 24
Finished Jul 24 05:26:46 PM PDT 24
Peak memory 206860 kb
Host smart-6c2087af-a8f3-4102-9058-bcf7e79c892b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1253475688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.1253475688
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.3076355439
Short name T880
Test name
Test status
Simulation time 247895695 ps
CPU time 1.03 seconds
Started Jul 24 05:26:02 PM PDT 24
Finished Jul 24 05:26:04 PM PDT 24
Peak memory 206648 kb
Host smart-8706be47-4c1e-4c19-bb14-177fd7057b5f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3076355439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.3076355439
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.1471527234
Short name T1019
Test name
Test status
Simulation time 193091721 ps
CPU time 0.85 seconds
Started Jul 24 05:26:28 PM PDT 24
Finished Jul 24 05:26:29 PM PDT 24
Peak memory 206568 kb
Host smart-7740150e-b757-48c7-9a3d-f1dc404b6595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14715
27234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.1471527234
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.4115118744
Short name T1673
Test name
Test status
Simulation time 6394443770 ps
CPU time 46.07 seconds
Started Jul 24 05:26:08 PM PDT 24
Finished Jul 24 05:26:55 PM PDT 24
Peak memory 206828 kb
Host smart-b30fa178-8a49-4469-aa4b-9b914314d3f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41151
18744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.4115118744
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.4020997523
Short name T2170
Test name
Test status
Simulation time 4472140069 ps
CPU time 42.13 seconds
Started Jul 24 05:26:19 PM PDT 24
Finished Jul 24 05:27:02 PM PDT 24
Peak memory 206852 kb
Host smart-6cbc6945-3d72-4c55-861d-b3c8d8b1d424
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4020997523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.4020997523
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.209609365
Short name T823
Test name
Test status
Simulation time 155699844 ps
CPU time 0.78 seconds
Started Jul 24 05:26:06 PM PDT 24
Finished Jul 24 05:26:07 PM PDT 24
Peak memory 206616 kb
Host smart-338455e9-7ef8-4938-b5a3-be47a958dffc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=209609365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.209609365
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.2213263692
Short name T1714
Test name
Test status
Simulation time 146703365 ps
CPU time 0.73 seconds
Started Jul 24 05:26:15 PM PDT 24
Finished Jul 24 05:26:16 PM PDT 24
Peak memory 206592 kb
Host smart-ebf1d8c9-2d5a-4407-aa0a-318c8996af5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22132
63692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.2213263692
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.3595277720
Short name T126
Test name
Test status
Simulation time 233060073 ps
CPU time 0.89 seconds
Started Jul 24 05:26:04 PM PDT 24
Finished Jul 24 05:26:05 PM PDT 24
Peak memory 206536 kb
Host smart-cc5327cb-4e34-4f5c-81c6-9dbf7a6028cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35952
77720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.3595277720
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.3242170016
Short name T2108
Test name
Test status
Simulation time 146252991 ps
CPU time 0.77 seconds
Started Jul 24 05:26:11 PM PDT 24
Finished Jul 24 05:26:12 PM PDT 24
Peak memory 206592 kb
Host smart-de3f3bbe-8647-4af7-8a10-b9329ac64634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32421
70016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.3242170016
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.3809570486
Short name T2439
Test name
Test status
Simulation time 165008011 ps
CPU time 0.82 seconds
Started Jul 24 05:26:15 PM PDT 24
Finished Jul 24 05:26:16 PM PDT 24
Peak memory 206612 kb
Host smart-3131f166-ca68-4adc-b3bd-47d7c435fbab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38095
70486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.3809570486
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.1148052921
Short name T2649
Test name
Test status
Simulation time 223985874 ps
CPU time 0.86 seconds
Started Jul 24 05:26:06 PM PDT 24
Finished Jul 24 05:26:07 PM PDT 24
Peak memory 206600 kb
Host smart-b4f700ed-9ec7-440f-9fa9-2b710c3d2b58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11480
52921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.1148052921
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.1492542816
Short name T2027
Test name
Test status
Simulation time 163537777 ps
CPU time 0.77 seconds
Started Jul 24 05:26:22 PM PDT 24
Finished Jul 24 05:26:23 PM PDT 24
Peak memory 206608 kb
Host smart-18dd6698-54a1-4a26-809b-4888d1db8b50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14925
42816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.1492542816
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.4017848382
Short name T1151
Test name
Test status
Simulation time 235169606 ps
CPU time 0.94 seconds
Started Jul 24 05:26:15 PM PDT 24
Finished Jul 24 05:26:16 PM PDT 24
Peak memory 206540 kb
Host smart-0923c985-5fc8-430b-86b9-0deae188212b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4017848382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.4017848382
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.3358635717
Short name T1241
Test name
Test status
Simulation time 139141065 ps
CPU time 0.75 seconds
Started Jul 24 05:26:22 PM PDT 24
Finished Jul 24 05:26:23 PM PDT 24
Peak memory 206576 kb
Host smart-6a6c2851-dbd9-48ee-a2b4-8026491c4aad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33586
35717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.3358635717
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.3553397389
Short name T2319
Test name
Test status
Simulation time 38840321 ps
CPU time 0.64 seconds
Started Jul 24 05:26:07 PM PDT 24
Finished Jul 24 05:26:08 PM PDT 24
Peak memory 206592 kb
Host smart-5a06d40a-8497-48a0-9138-9aba5bb58af1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35533
97389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.3553397389
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.1271428608
Short name T238
Test name
Test status
Simulation time 14527980162 ps
CPU time 29.72 seconds
Started Jul 24 05:26:17 PM PDT 24
Finished Jul 24 05:26:47 PM PDT 24
Peak memory 206960 kb
Host smart-9c355a1e-9de7-454a-af66-69a5d3cfa9c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12714
28608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.1271428608
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.96896524
Short name T1461
Test name
Test status
Simulation time 183452580 ps
CPU time 0.87 seconds
Started Jul 24 05:26:03 PM PDT 24
Finished Jul 24 05:26:04 PM PDT 24
Peak memory 206472 kb
Host smart-8073e8b8-d6cf-4ec2-82f0-bf4cfc885004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96896
524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.96896524
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.2570998075
Short name T1044
Test name
Test status
Simulation time 237155463 ps
CPU time 0.91 seconds
Started Jul 24 05:26:06 PM PDT 24
Finished Jul 24 05:26:07 PM PDT 24
Peak memory 206632 kb
Host smart-b7bb5914-379a-4978-b4e5-ac33fef6c5dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25709
98075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.2570998075
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.3489173871
Short name T2643
Test name
Test status
Simulation time 208113662 ps
CPU time 0.9 seconds
Started Jul 24 05:26:25 PM PDT 24
Finished Jul 24 05:26:26 PM PDT 24
Peak memory 206596 kb
Host smart-10950c0d-89e5-484b-bfb4-908c0fc19142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34891
73871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.3489173871
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.2879377545
Short name T2511
Test name
Test status
Simulation time 245400738 ps
CPU time 0.9 seconds
Started Jul 24 05:26:05 PM PDT 24
Finished Jul 24 05:26:06 PM PDT 24
Peak memory 206548 kb
Host smart-8b8c1cda-dd87-4bd5-82c5-dc2fb5a32905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28793
77545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.2879377545
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.1411255958
Short name T2399
Test name
Test status
Simulation time 211040944 ps
CPU time 0.82 seconds
Started Jul 24 05:26:00 PM PDT 24
Finished Jul 24 05:26:01 PM PDT 24
Peak memory 206600 kb
Host smart-c0979cfe-c3c0-4e20-8ddf-1e54d66a3af6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14112
55958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.1411255958
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.2311450777
Short name T2672
Test name
Test status
Simulation time 153969007 ps
CPU time 0.79 seconds
Started Jul 24 05:26:18 PM PDT 24
Finished Jul 24 05:26:19 PM PDT 24
Peak memory 206552 kb
Host smart-6b6a9d7f-f557-44fb-bc16-12fdd3fd8c6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23114
50777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.2311450777
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.2612883136
Short name T2358
Test name
Test status
Simulation time 149018376 ps
CPU time 0.77 seconds
Started Jul 24 05:26:40 PM PDT 24
Finished Jul 24 05:26:41 PM PDT 24
Peak memory 206600 kb
Host smart-d8bd1429-f7a6-4e0b-a8ea-25beab11ecf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26128
83136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.2612883136
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.2068149452
Short name T2550
Test name
Test status
Simulation time 217326306 ps
CPU time 0.87 seconds
Started Jul 24 05:26:07 PM PDT 24
Finished Jul 24 05:26:09 PM PDT 24
Peak memory 206656 kb
Host smart-77a35620-d547-4ab7-ad90-5d1ea444151a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20681
49452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.2068149452
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.1431944858
Short name T1133
Test name
Test status
Simulation time 5653160004 ps
CPU time 152.06 seconds
Started Jul 24 05:26:16 PM PDT 24
Finished Jul 24 05:28:48 PM PDT 24
Peak memory 206980 kb
Host smart-b99dbb31-95c8-4720-8b00-ba44272683e2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1431944858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.1431944858
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.1714914686
Short name T1296
Test name
Test status
Simulation time 154908158 ps
CPU time 0.83 seconds
Started Jul 24 05:26:29 PM PDT 24
Finished Jul 24 05:26:30 PM PDT 24
Peak memory 206676 kb
Host smart-d02b9ea2-2904-42f5-b8d2-8035a54ba51b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17149
14686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.1714914686
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.2844158909
Short name T1840
Test name
Test status
Simulation time 192158114 ps
CPU time 0.87 seconds
Started Jul 24 05:26:38 PM PDT 24
Finished Jul 24 05:26:39 PM PDT 24
Peak memory 206592 kb
Host smart-8d069b19-f953-4c8e-a221-dcab8248ea4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28441
58909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.2844158909
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.2812853486
Short name T1579
Test name
Test status
Simulation time 584204250 ps
CPU time 1.58 seconds
Started Jul 24 05:26:04 PM PDT 24
Finished Jul 24 05:26:06 PM PDT 24
Peak memory 206588 kb
Host smart-f41b23e5-4700-48ef-971d-fc93334a0c6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28128
53486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.2812853486
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.2191921599
Short name T1634
Test name
Test status
Simulation time 5469799221 ps
CPU time 52.67 seconds
Started Jul 24 05:26:06 PM PDT 24
Finished Jul 24 05:26:59 PM PDT 24
Peak memory 207008 kb
Host smart-1ab133f8-7648-46f3-bd11-63aa2680449b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21919
21599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.2191921599
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.905163065
Short name T381
Test name
Test status
Simulation time 67050731 ps
CPU time 0.68 seconds
Started Jul 24 05:26:20 PM PDT 24
Finished Jul 24 05:26:20 PM PDT 24
Peak memory 206604 kb
Host smart-5d0d129d-359e-4eec-a81b-b8fd5409d722
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=905163065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.905163065
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.3947328210
Short name T2095
Test name
Test status
Simulation time 3657400688 ps
CPU time 4.34 seconds
Started Jul 24 05:26:05 PM PDT 24
Finished Jul 24 05:26:09 PM PDT 24
Peak memory 206736 kb
Host smart-3455fe54-0684-401b-9404-33d9b0a0e9a4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3947328210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.3947328210
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.2674223477
Short name T1143
Test name
Test status
Simulation time 13339791961 ps
CPU time 13.3 seconds
Started Jul 24 05:26:06 PM PDT 24
Finished Jul 24 05:26:20 PM PDT 24
Peak memory 206736 kb
Host smart-fbfa5bbd-4346-4f9c-af0b-06c963dc5a30
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2674223477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.2674223477
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.2160242981
Short name T2630
Test name
Test status
Simulation time 23480269286 ps
CPU time 22.59 seconds
Started Jul 24 05:26:09 PM PDT 24
Finished Jul 24 05:26:32 PM PDT 24
Peak memory 206916 kb
Host smart-0fd57068-17cb-4ddb-8492-cae41feef4c0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2160242981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.2160242981
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.996672271
Short name T75
Test name
Test status
Simulation time 187658320 ps
CPU time 0.86 seconds
Started Jul 24 05:26:00 PM PDT 24
Finished Jul 24 05:26:02 PM PDT 24
Peak memory 206468 kb
Host smart-6af57726-3319-4f35-8a13-22cbb8d45575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99667
2271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.996672271
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.1791717339
Short name T2198
Test name
Test status
Simulation time 166620199 ps
CPU time 0.75 seconds
Started Jul 24 05:26:22 PM PDT 24
Finished Jul 24 05:26:23 PM PDT 24
Peak memory 206552 kb
Host smart-3c7eda05-5b1b-4f47-a201-19fca73a1809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17917
17339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.1791717339
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.628942358
Short name T104
Test name
Test status
Simulation time 400562641 ps
CPU time 1.29 seconds
Started Jul 24 05:26:01 PM PDT 24
Finished Jul 24 05:26:02 PM PDT 24
Peak memory 206576 kb
Host smart-c168c643-92ef-476c-b97b-535c21ffeea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62894
2358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.628942358
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.1899109506
Short name T1537
Test name
Test status
Simulation time 803231272 ps
CPU time 1.82 seconds
Started Jul 24 05:26:20 PM PDT 24
Finished Jul 24 05:26:22 PM PDT 24
Peak memory 206832 kb
Host smart-b0f812ba-8405-475a-a027-2dbd1ff69f36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18991
09506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.1899109506
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.1031216675
Short name T2519
Test name
Test status
Simulation time 23235058372 ps
CPU time 46.82 seconds
Started Jul 24 05:26:23 PM PDT 24
Finished Jul 24 05:27:10 PM PDT 24
Peak memory 206864 kb
Host smart-eb6aa762-fa9c-4f94-84e7-2c90f4c0b338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10312
16675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.1031216675
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.3531675058
Short name T2676
Test name
Test status
Simulation time 369378737 ps
CPU time 1.16 seconds
Started Jul 24 05:26:15 PM PDT 24
Finished Jul 24 05:26:17 PM PDT 24
Peak memory 206596 kb
Host smart-ae761d7d-8196-479d-bf9e-77b4ae652300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35316
75058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.3531675058
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.3766604459
Short name T1532
Test name
Test status
Simulation time 164970145 ps
CPU time 0.81 seconds
Started Jul 24 05:26:06 PM PDT 24
Finished Jul 24 05:26:07 PM PDT 24
Peak memory 206556 kb
Host smart-fe7ffd37-9ff5-4714-8f01-fde41ed68ed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37666
04459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.3766604459
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.3140202202
Short name T1409
Test name
Test status
Simulation time 38419474 ps
CPU time 0.64 seconds
Started Jul 24 05:26:06 PM PDT 24
Finished Jul 24 05:26:07 PM PDT 24
Peak memory 206576 kb
Host smart-35ecb497-1332-41d0-a05f-238ca9619f43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31402
02202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.3140202202
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.593046783
Short name T557
Test name
Test status
Simulation time 905093868 ps
CPU time 2.05 seconds
Started Jul 24 05:26:12 PM PDT 24
Finished Jul 24 05:26:14 PM PDT 24
Peak memory 206736 kb
Host smart-9ba2ea64-e008-461e-a9fb-013e4f9acbae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59304
6783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.593046783
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.2480106235
Short name T721
Test name
Test status
Simulation time 230248770 ps
CPU time 1.47 seconds
Started Jul 24 05:26:23 PM PDT 24
Finished Jul 24 05:26:25 PM PDT 24
Peak memory 206852 kb
Host smart-22be5afe-f7a7-4bb1-8c68-9c2165d4e2b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24801
06235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.2480106235
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.482109804
Short name T1787
Test name
Test status
Simulation time 213633433 ps
CPU time 0.9 seconds
Started Jul 24 05:26:08 PM PDT 24
Finished Jul 24 05:26:10 PM PDT 24
Peak memory 206588 kb
Host smart-27bbf172-4e7c-4f96-aef0-713e10aa21a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48210
9804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.482109804
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.1561655439
Short name T1927
Test name
Test status
Simulation time 153925278 ps
CPU time 0.79 seconds
Started Jul 24 05:26:08 PM PDT 24
Finished Jul 24 05:26:09 PM PDT 24
Peak memory 206628 kb
Host smart-4cbfe170-a666-492f-9c3b-b13681c5207d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15616
55439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.1561655439
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.3046325852
Short name T536
Test name
Test status
Simulation time 209422640 ps
CPU time 0.85 seconds
Started Jul 24 05:26:10 PM PDT 24
Finished Jul 24 05:26:11 PM PDT 24
Peak memory 206552 kb
Host smart-776df54d-b9d5-4ef1-94ca-99f3bc276bd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30463
25852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.3046325852
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_iso_retraction.3940566101
Short name T689
Test name
Test status
Simulation time 10844515711 ps
CPU time 86.59 seconds
Started Jul 24 05:26:18 PM PDT 24
Finished Jul 24 05:27:45 PM PDT 24
Peak memory 206800 kb
Host smart-67f1a466-2664-4f9e-9c09-0995c6bcc5ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39405
66101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_iso_retraction.3940566101
Directory /workspace/18.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.2531210343
Short name T1939
Test name
Test status
Simulation time 196656746 ps
CPU time 0.87 seconds
Started Jul 24 05:26:16 PM PDT 24
Finished Jul 24 05:26:17 PM PDT 24
Peak memory 206552 kb
Host smart-86b1e113-0fae-4792-8e1c-e596da27735c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25312
10343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.2531210343
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.1668438946
Short name T2128
Test name
Test status
Simulation time 23306068668 ps
CPU time 22.42 seconds
Started Jul 24 05:26:30 PM PDT 24
Finished Jul 24 05:26:53 PM PDT 24
Peak memory 206620 kb
Host smart-95d833f5-ac98-487e-9184-a78a813b28f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16684
38946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.1668438946
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.3521237995
Short name T1838
Test name
Test status
Simulation time 3325816365 ps
CPU time 3.75 seconds
Started Jul 24 05:26:17 PM PDT 24
Finished Jul 24 05:26:21 PM PDT 24
Peak memory 206672 kb
Host smart-c3568db6-27e4-461a-afbe-b789614f9478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35212
37995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.3521237995
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.4167281340
Short name T1747
Test name
Test status
Simulation time 13490891653 ps
CPU time 369.5 seconds
Started Jul 24 05:26:07 PM PDT 24
Finished Jul 24 05:32:17 PM PDT 24
Peak memory 206992 kb
Host smart-bd26e012-95d9-4640-ae02-1d164626372a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41672
81340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.4167281340
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.1071358869
Short name T864
Test name
Test status
Simulation time 5046768499 ps
CPU time 47.21 seconds
Started Jul 24 05:26:16 PM PDT 24
Finished Jul 24 05:27:03 PM PDT 24
Peak memory 206860 kb
Host smart-8c317cec-460d-4189-891a-dcf4580ee7d1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1071358869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.1071358869
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.1120178830
Short name T982
Test name
Test status
Simulation time 256213453 ps
CPU time 0.99 seconds
Started Jul 24 05:26:16 PM PDT 24
Finished Jul 24 05:26:17 PM PDT 24
Peak memory 206584 kb
Host smart-57a96e45-6bb5-4be8-bc1e-4b87cfc8abb5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1120178830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.1120178830
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.3241881650
Short name T987
Test name
Test status
Simulation time 190628408 ps
CPU time 0.9 seconds
Started Jul 24 05:26:31 PM PDT 24
Finished Jul 24 05:26:32 PM PDT 24
Peak memory 206604 kb
Host smart-b79d02c4-c7f0-4e11-9d07-8bf8320cc122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32418
81650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.3241881650
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.3744945100
Short name T1206
Test name
Test status
Simulation time 3838384254 ps
CPU time 27.19 seconds
Started Jul 24 05:26:23 PM PDT 24
Finished Jul 24 05:26:50 PM PDT 24
Peak memory 206932 kb
Host smart-c9c1e269-0a81-4f75-8200-564b617c2c66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37449
45100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.3744945100
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.140399715
Short name T148
Test name
Test status
Simulation time 3384073582 ps
CPU time 91.66 seconds
Started Jul 24 05:26:15 PM PDT 24
Finished Jul 24 05:27:47 PM PDT 24
Peak memory 206824 kb
Host smart-5266125d-a265-4971-a0e4-7fe784d7f0f4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=140399715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.140399715
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.315063739
Short name T264
Test name
Test status
Simulation time 160763009 ps
CPU time 0.77 seconds
Started Jul 24 05:26:21 PM PDT 24
Finished Jul 24 05:26:22 PM PDT 24
Peak memory 206536 kb
Host smart-636a73da-3d9e-4dfb-ae23-a833dbbe60eb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=315063739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.315063739
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.421868728
Short name T2071
Test name
Test status
Simulation time 143541631 ps
CPU time 0.78 seconds
Started Jul 24 05:26:12 PM PDT 24
Finished Jul 24 05:26:13 PM PDT 24
Peak memory 206592 kb
Host smart-58ed1897-19fd-4073-8425-c24133649429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42186
8728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.421868728
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.3769279564
Short name T2035
Test name
Test status
Simulation time 157664846 ps
CPU time 0.78 seconds
Started Jul 24 05:26:16 PM PDT 24
Finished Jul 24 05:26:17 PM PDT 24
Peak memory 206492 kb
Host smart-084499e8-9e5f-491b-8409-89c1dbe1b156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37692
79564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.3769279564
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.1994793962
Short name T347
Test name
Test status
Simulation time 209925076 ps
CPU time 0.89 seconds
Started Jul 24 05:26:14 PM PDT 24
Finished Jul 24 05:26:15 PM PDT 24
Peak memory 206556 kb
Host smart-49f8414c-3995-436d-a248-3e25a3a75e64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19947
93962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.1994793962
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.1328833753
Short name T2121
Test name
Test status
Simulation time 187685415 ps
CPU time 0.81 seconds
Started Jul 24 05:26:23 PM PDT 24
Finished Jul 24 05:26:24 PM PDT 24
Peak memory 206580 kb
Host smart-2e032e80-cc7f-4af7-91ee-e7cd2eced1e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13288
33753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.1328833753
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.377569726
Short name T2604
Test name
Test status
Simulation time 160210079 ps
CPU time 0.78 seconds
Started Jul 24 05:26:07 PM PDT 24
Finished Jul 24 05:26:08 PM PDT 24
Peak memory 206536 kb
Host smart-63b6b1bb-c862-4ccf-8537-ccfb5b9025af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37756
9726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.377569726
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.2531726848
Short name T1276
Test name
Test status
Simulation time 288201208 ps
CPU time 1.08 seconds
Started Jul 24 05:26:12 PM PDT 24
Finished Jul 24 05:26:13 PM PDT 24
Peak memory 206540 kb
Host smart-a6803d1f-41d2-4edd-beb8-cf6de2a3131e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2531726848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.2531726848
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.3376739406
Short name T401
Test name
Test status
Simulation time 187514160 ps
CPU time 0.88 seconds
Started Jul 24 05:26:17 PM PDT 24
Finished Jul 24 05:26:18 PM PDT 24
Peak memory 206568 kb
Host smart-d93be7a2-6b91-4609-9acc-6be5401df875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33767
39406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.3376739406
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.743920810
Short name T2152
Test name
Test status
Simulation time 32445950 ps
CPU time 0.7 seconds
Started Jul 24 05:26:34 PM PDT 24
Finished Jul 24 05:26:35 PM PDT 24
Peak memory 206776 kb
Host smart-aa7f69c5-f5a8-473f-b6c8-051544fc8b10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74392
0810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.743920810
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.3939237967
Short name T562
Test name
Test status
Simulation time 21211635778 ps
CPU time 47.37 seconds
Started Jul 24 05:26:18 PM PDT 24
Finished Jul 24 05:27:05 PM PDT 24
Peak memory 215056 kb
Host smart-1e467ab1-f92f-47a4-98f0-0bebda72f467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39392
37967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.3939237967
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.3220747212
Short name T1328
Test name
Test status
Simulation time 187115942 ps
CPU time 0.83 seconds
Started Jul 24 05:26:21 PM PDT 24
Finished Jul 24 05:26:22 PM PDT 24
Peak memory 206428 kb
Host smart-0618f79d-0b0e-432c-afb8-a09550772d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32207
47212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.3220747212
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.2985229887
Short name T644
Test name
Test status
Simulation time 183543309 ps
CPU time 0.82 seconds
Started Jul 24 05:26:21 PM PDT 24
Finished Jul 24 05:26:22 PM PDT 24
Peak memory 206568 kb
Host smart-9b50b17e-0601-4dae-b004-d77d60f74a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29852
29887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.2985229887
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.2619055409
Short name T1299
Test name
Test status
Simulation time 240367672 ps
CPU time 0.94 seconds
Started Jul 24 05:26:20 PM PDT 24
Finished Jul 24 05:26:21 PM PDT 24
Peak memory 206624 kb
Host smart-75c0a305-50b4-41f1-a4f3-1f7df0bdd189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26190
55409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.2619055409
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.54394396
Short name T782
Test name
Test status
Simulation time 179064172 ps
CPU time 0.87 seconds
Started Jul 24 05:26:14 PM PDT 24
Finished Jul 24 05:26:15 PM PDT 24
Peak memory 206468 kb
Host smart-8f6acb1a-d77a-4466-81c6-2268ade2a392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54394
396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.54394396
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.4213602203
Short name T1450
Test name
Test status
Simulation time 160756277 ps
CPU time 0.79 seconds
Started Jul 24 05:26:23 PM PDT 24
Finished Jul 24 05:26:24 PM PDT 24
Peak memory 206776 kb
Host smart-812154c1-4dc8-4c29-b634-a11ed59768c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42136
02203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.4213602203
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.3430585023
Short name T1439
Test name
Test status
Simulation time 146856744 ps
CPU time 0.82 seconds
Started Jul 24 05:26:11 PM PDT 24
Finished Jul 24 05:26:12 PM PDT 24
Peak memory 206592 kb
Host smart-88e7372f-6442-458e-992f-eeeecf74eba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34305
85023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.3430585023
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.4168471114
Short name T2608
Test name
Test status
Simulation time 148449029 ps
CPU time 0.84 seconds
Started Jul 24 05:26:09 PM PDT 24
Finished Jul 24 05:26:10 PM PDT 24
Peak memory 206476 kb
Host smart-2fefc552-2516-460a-9415-7e179cdcfce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41684
71114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.4168471114
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.2315983131
Short name T1928
Test name
Test status
Simulation time 200043650 ps
CPU time 0.87 seconds
Started Jul 24 05:26:22 PM PDT 24
Finished Jul 24 05:26:23 PM PDT 24
Peak memory 206568 kb
Host smart-3ecae25a-1801-45a7-a769-b7ec044feb10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23159
83131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.2315983131
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.2167446434
Short name T1502
Test name
Test status
Simulation time 6015074560 ps
CPU time 43.44 seconds
Started Jul 24 05:26:14 PM PDT 24
Finished Jul 24 05:26:57 PM PDT 24
Peak memory 206860 kb
Host smart-a6b9adfb-0641-4ecd-80c3-e1f843387dfb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2167446434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.2167446434
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.203109313
Short name T2687
Test name
Test status
Simulation time 198211566 ps
CPU time 0.8 seconds
Started Jul 24 05:26:21 PM PDT 24
Finished Jul 24 05:26:22 PM PDT 24
Peak memory 206628 kb
Host smart-3d0d4d74-93ec-447f-bcf8-fb5719db9372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20310
9313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.203109313
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.769928259
Short name T1752
Test name
Test status
Simulation time 188555842 ps
CPU time 0.77 seconds
Started Jul 24 05:26:21 PM PDT 24
Finished Jul 24 05:26:22 PM PDT 24
Peak memory 206540 kb
Host smart-e407a0e1-3b0d-4f34-af92-8802f7de412b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76992
8259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.769928259
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.3579698094
Short name T1900
Test name
Test status
Simulation time 612345077 ps
CPU time 1.42 seconds
Started Jul 24 05:26:28 PM PDT 24
Finished Jul 24 05:26:30 PM PDT 24
Peak memory 206532 kb
Host smart-c564b3aa-dbfe-42ad-a27e-963a3a8e2efb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35796
98094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.3579698094
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.784733749
Short name T1775
Test name
Test status
Simulation time 4063042352 ps
CPU time 110.59 seconds
Started Jul 24 05:26:12 PM PDT 24
Finished Jul 24 05:28:03 PM PDT 24
Peak memory 206892 kb
Host smart-a04fe1e1-d699-43a0-9421-2d53a65fbd85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78473
3749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.784733749
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.2937085169
Short name T1990
Test name
Test status
Simulation time 35769153 ps
CPU time 0.7 seconds
Started Jul 24 05:26:35 PM PDT 24
Finished Jul 24 05:26:36 PM PDT 24
Peak memory 206600 kb
Host smart-49ac1953-13cf-42a3-b5f0-cfdb49c153d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2937085169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.2937085169
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.553055264
Short name T211
Test name
Test status
Simulation time 4018764192 ps
CPU time 5.34 seconds
Started Jul 24 05:26:24 PM PDT 24
Finished Jul 24 05:26:29 PM PDT 24
Peak memory 206936 kb
Host smart-2672d25c-d799-4f0c-ae40-3d8376e9f7ee
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=553055264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.553055264
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.3809019426
Short name T1592
Test name
Test status
Simulation time 13429388379 ps
CPU time 13.55 seconds
Started Jul 24 05:26:19 PM PDT 24
Finished Jul 24 05:26:32 PM PDT 24
Peak memory 206688 kb
Host smart-887d3f72-0b09-45d6-ad61-cbacfd123908
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3809019426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.3809019426
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.3212444991
Short name T2277
Test name
Test status
Simulation time 23343798836 ps
CPU time 21.75 seconds
Started Jul 24 05:26:35 PM PDT 24
Finished Jul 24 05:26:57 PM PDT 24
Peak memory 206948 kb
Host smart-b2494d73-f9f5-46d2-91e1-f7b7c792bb5e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3212444991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.3212444991
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.3829526341
Short name T1231
Test name
Test status
Simulation time 155347239 ps
CPU time 0.78 seconds
Started Jul 24 05:26:11 PM PDT 24
Finished Jul 24 05:26:13 PM PDT 24
Peak memory 206584 kb
Host smart-f8f9e946-bc0f-409c-aec9-d691eb3ef4b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38295
26341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.3829526341
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.1547838
Short name T394
Test name
Test status
Simulation time 143782503 ps
CPU time 0.75 seconds
Started Jul 24 05:26:19 PM PDT 24
Finished Jul 24 05:26:20 PM PDT 24
Peak memory 206540 kb
Host smart-88b90ce6-9f72-475c-8d85-0b3349f65e97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15478
38 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.1547838
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.1426554969
Short name T439
Test name
Test status
Simulation time 228217082 ps
CPU time 0.95 seconds
Started Jul 24 05:26:14 PM PDT 24
Finished Jul 24 05:26:15 PM PDT 24
Peak memory 206460 kb
Host smart-3813dbab-147a-457e-b777-f7334e79dec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14265
54969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.1426554969
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.1564952911
Short name T2532
Test name
Test status
Simulation time 1009767495 ps
CPU time 2.1 seconds
Started Jul 24 05:26:13 PM PDT 24
Finished Jul 24 05:26:15 PM PDT 24
Peak memory 206852 kb
Host smart-850ba14f-cca8-4a18-80a8-28d67bf74a60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15649
52911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.1564952911
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.317958731
Short name T1734
Test name
Test status
Simulation time 12716782072 ps
CPU time 22.65 seconds
Started Jul 24 05:26:14 PM PDT 24
Finished Jul 24 05:26:37 PM PDT 24
Peak memory 206904 kb
Host smart-2a44a33b-01ca-4e2e-9f82-c8633f774bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31795
8731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.317958731
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.4221681005
Short name T2711
Test name
Test status
Simulation time 312139809 ps
CPU time 1.09 seconds
Started Jul 24 05:26:35 PM PDT 24
Finished Jul 24 05:26:37 PM PDT 24
Peak memory 206564 kb
Host smart-dd1b2057-1946-4286-861e-206964a6c21d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42216
81005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.4221681005
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.3439456851
Short name T2299
Test name
Test status
Simulation time 168124095 ps
CPU time 0.74 seconds
Started Jul 24 05:26:14 PM PDT 24
Finished Jul 24 05:26:15 PM PDT 24
Peak memory 206600 kb
Host smart-0ac976f7-f35e-45c6-8530-a4adfbf67991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34394
56851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.3439456851
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.517393764
Short name T2394
Test name
Test status
Simulation time 42937804 ps
CPU time 0.68 seconds
Started Jul 24 05:26:13 PM PDT 24
Finished Jul 24 05:26:14 PM PDT 24
Peak memory 206576 kb
Host smart-80ae8f77-d945-4fb7-a2b1-ef5a67b2a1b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51739
3764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.517393764
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.2448355244
Short name T2072
Test name
Test status
Simulation time 859835774 ps
CPU time 2.29 seconds
Started Jul 24 05:26:17 PM PDT 24
Finished Jul 24 05:26:19 PM PDT 24
Peak memory 206692 kb
Host smart-ebbe1b00-5641-4330-b585-81d995d2c7ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24483
55244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.2448355244
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.2249710592
Short name T2383
Test name
Test status
Simulation time 179765267 ps
CPU time 1.44 seconds
Started Jul 24 05:26:25 PM PDT 24
Finished Jul 24 05:26:27 PM PDT 24
Peak memory 206832 kb
Host smart-77ddcad2-6351-4563-af12-04f2a61d802f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22497
10592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.2249710592
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.4272319921
Short name T1594
Test name
Test status
Simulation time 232623649 ps
CPU time 0.88 seconds
Started Jul 24 05:26:34 PM PDT 24
Finished Jul 24 05:26:35 PM PDT 24
Peak memory 206580 kb
Host smart-a1cf9be0-f15d-46d0-ac9e-4c653fe9ba2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42723
19921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.4272319921
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.3697664404
Short name T2260
Test name
Test status
Simulation time 143276356 ps
CPU time 0.77 seconds
Started Jul 24 05:26:32 PM PDT 24
Finished Jul 24 05:26:33 PM PDT 24
Peak memory 206560 kb
Host smart-5f952601-f620-43d4-8696-ef70d9511122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36976
64404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.3697664404
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.888494994
Short name T419
Test name
Test status
Simulation time 190042761 ps
CPU time 0.85 seconds
Started Jul 24 05:26:35 PM PDT 24
Finished Jul 24 05:26:36 PM PDT 24
Peak memory 206636 kb
Host smart-20a459b8-00c1-4479-9d15-5b6a7404b440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88849
4994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.888494994
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.2601873669
Short name T2161
Test name
Test status
Simulation time 6148726668 ps
CPU time 160 seconds
Started Jul 24 05:26:41 PM PDT 24
Finished Jul 24 05:29:21 PM PDT 24
Peak memory 206896 kb
Host smart-e4b8d8e1-84a4-44a4-b488-2592a2805ee8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2601873669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.2601873669
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/19.usbdev_iso_retraction.2819240729
Short name T1457
Test name
Test status
Simulation time 11527249663 ps
CPU time 42.96 seconds
Started Jul 24 05:26:11 PM PDT 24
Finished Jul 24 05:26:55 PM PDT 24
Peak memory 206888 kb
Host smart-7160cbac-d186-40e4-bf5a-34c621f6b08d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28192
40729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.2819240729
Directory /workspace/19.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.675935577
Short name T748
Test name
Test status
Simulation time 281539352 ps
CPU time 1 seconds
Started Jul 24 05:26:19 PM PDT 24
Finished Jul 24 05:26:20 PM PDT 24
Peak memory 206588 kb
Host smart-090adc28-9d0e-4e1d-9d01-7e85b0baaec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67593
5577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.675935577
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.311107708
Short name T474
Test name
Test status
Simulation time 23301314712 ps
CPU time 21.98 seconds
Started Jul 24 05:26:23 PM PDT 24
Finished Jul 24 05:26:45 PM PDT 24
Peak memory 206744 kb
Host smart-dba44ba1-fb6f-4cb3-9f4a-a709d32cb5ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31110
7708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.311107708
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.3438457173
Short name T1035
Test name
Test status
Simulation time 3335882673 ps
CPU time 4.04 seconds
Started Jul 24 05:26:29 PM PDT 24
Finished Jul 24 05:26:33 PM PDT 24
Peak memory 206668 kb
Host smart-97487079-d20e-4f29-b3bb-7d78c7545d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34384
57173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.3438457173
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.3477727512
Short name T1256
Test name
Test status
Simulation time 8467272939 ps
CPU time 76.49 seconds
Started Jul 24 05:26:32 PM PDT 24
Finished Jul 24 05:27:48 PM PDT 24
Peak memory 206968 kb
Host smart-6fca6ab9-0f40-4649-9cb1-540a8dd8f049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34777
27512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.3477727512
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.2166156554
Short name T334
Test name
Test status
Simulation time 4886054895 ps
CPU time 132.64 seconds
Started Jul 24 05:26:15 PM PDT 24
Finished Jul 24 05:28:28 PM PDT 24
Peak memory 206680 kb
Host smart-917d4d59-a953-476c-bba6-4f37b5bbdc25
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2166156554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.2166156554
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.2220833485
Short name T509
Test name
Test status
Simulation time 234043233 ps
CPU time 1.04 seconds
Started Jul 24 05:26:16 PM PDT 24
Finished Jul 24 05:26:18 PM PDT 24
Peak memory 206584 kb
Host smart-e6cbab8b-205d-43d5-8dcb-8dc54739714d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2220833485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.2220833485
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.4272539031
Short name T1919
Test name
Test status
Simulation time 198505233 ps
CPU time 0.9 seconds
Started Jul 24 05:26:27 PM PDT 24
Finished Jul 24 05:26:28 PM PDT 24
Peak memory 206604 kb
Host smart-984ede13-d8f2-40d3-9224-56d24c2d86d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42725
39031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.4272539031
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.1337731377
Short name T2733
Test name
Test status
Simulation time 5209803682 ps
CPU time 146.01 seconds
Started Jul 24 05:26:34 PM PDT 24
Finished Jul 24 05:29:00 PM PDT 24
Peak memory 206956 kb
Host smart-eaadf375-6847-43f8-abed-d99ae6d2c314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13377
31377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.1337731377
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.1955703208
Short name T2004
Test name
Test status
Simulation time 7729886245 ps
CPU time 70.65 seconds
Started Jul 24 05:26:14 PM PDT 24
Finished Jul 24 05:27:25 PM PDT 24
Peak memory 206964 kb
Host smart-ee9b9ac3-b346-433b-926b-9c99717d2d20
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1955703208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.1955703208
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.4072683999
Short name T1965
Test name
Test status
Simulation time 159336647 ps
CPU time 0.8 seconds
Started Jul 24 05:26:25 PM PDT 24
Finished Jul 24 05:26:27 PM PDT 24
Peak memory 206616 kb
Host smart-9f8d5a13-b27e-411d-b300-a110856bf8e3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4072683999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.4072683999
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.1431970077
Short name T2103
Test name
Test status
Simulation time 191214253 ps
CPU time 0.84 seconds
Started Jul 24 05:26:12 PM PDT 24
Finished Jul 24 05:26:13 PM PDT 24
Peak memory 206528 kb
Host smart-ecee8922-b109-428c-8cc0-caef17e009ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14319
70077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.1431970077
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.459141390
Short name T133
Test name
Test status
Simulation time 257353296 ps
CPU time 0.88 seconds
Started Jul 24 05:26:34 PM PDT 24
Finished Jul 24 05:26:36 PM PDT 24
Peak memory 206600 kb
Host smart-30c8c83c-03ce-4e4f-be1b-400fb0a998a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45914
1390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.459141390
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.1356776748
Short name T2418
Test name
Test status
Simulation time 158898970 ps
CPU time 0.79 seconds
Started Jul 24 05:26:15 PM PDT 24
Finished Jul 24 05:26:17 PM PDT 24
Peak memory 206604 kb
Host smart-97d109e8-cab7-4318-aae3-dd32fa4a6ec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13567
76748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.1356776748
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.3601021591
Short name T2118
Test name
Test status
Simulation time 199347636 ps
CPU time 0.84 seconds
Started Jul 24 05:26:16 PM PDT 24
Finished Jul 24 05:26:17 PM PDT 24
Peak memory 206568 kb
Host smart-c5582354-7fd4-412c-825f-54e69e5357d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36010
21591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.3601021591
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.2644486594
Short name T761
Test name
Test status
Simulation time 186353067 ps
CPU time 0.78 seconds
Started Jul 24 05:26:15 PM PDT 24
Finished Jul 24 05:26:16 PM PDT 24
Peak memory 206544 kb
Host smart-a563381e-9903-43d6-b661-c46b32078686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26444
86594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.2644486594
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.4213593426
Short name T1379
Test name
Test status
Simulation time 145901718 ps
CPU time 0.81 seconds
Started Jul 24 05:26:12 PM PDT 24
Finished Jul 24 05:26:13 PM PDT 24
Peak memory 206644 kb
Host smart-7176394a-5d1a-45c1-9391-491e6e4d6a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42135
93426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.4213593426
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.26179286
Short name T2356
Test name
Test status
Simulation time 232944161 ps
CPU time 0.92 seconds
Started Jul 24 05:26:15 PM PDT 24
Finished Jul 24 05:26:16 PM PDT 24
Peak memory 206400 kb
Host smart-147baf05-8022-4405-baa1-b0dea1da006c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=26179286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.26179286
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.2885104422
Short name T480
Test name
Test status
Simulation time 162630842 ps
CPU time 0.84 seconds
Started Jul 24 05:26:14 PM PDT 24
Finished Jul 24 05:26:15 PM PDT 24
Peak memory 206548 kb
Host smart-b3a3fbd6-1a96-457c-80eb-afaeeec59fcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28851
04422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.2885104422
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.774801018
Short name T24
Test name
Test status
Simulation time 38498547 ps
CPU time 0.66 seconds
Started Jul 24 05:26:22 PM PDT 24
Finished Jul 24 05:26:23 PM PDT 24
Peak memory 206580 kb
Host smart-a15376be-56a1-4905-9946-a4e72409cb02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77480
1018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.774801018
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.2389394207
Short name T1229
Test name
Test status
Simulation time 15177043736 ps
CPU time 35 seconds
Started Jul 24 05:26:26 PM PDT 24
Finished Jul 24 05:27:01 PM PDT 24
Peak memory 206900 kb
Host smart-037ea71a-eb5e-4c84-90b3-8205b2bd68ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23893
94207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.2389394207
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.4035500263
Short name T2593
Test name
Test status
Simulation time 158748447 ps
CPU time 0.77 seconds
Started Jul 24 05:26:25 PM PDT 24
Finished Jul 24 05:26:26 PM PDT 24
Peak memory 206588 kb
Host smart-9984d0bd-54f6-4c82-ad33-6109a77872e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40355
00263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.4035500263
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.475257300
Short name T1426
Test name
Test status
Simulation time 246552666 ps
CPU time 0.9 seconds
Started Jul 24 05:26:30 PM PDT 24
Finished Jul 24 05:26:31 PM PDT 24
Peak memory 206508 kb
Host smart-ed8449bc-278f-4482-883f-8f511fc023b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47525
7300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.475257300
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.1872788691
Short name T836
Test name
Test status
Simulation time 223025308 ps
CPU time 0.93 seconds
Started Jul 24 05:26:41 PM PDT 24
Finished Jul 24 05:26:42 PM PDT 24
Peak memory 206592 kb
Host smart-0870bb65-1d80-4567-9710-16194e6f88df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18727
88691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.1872788691
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.2208172029
Short name T866
Test name
Test status
Simulation time 184486432 ps
CPU time 0.82 seconds
Started Jul 24 05:26:24 PM PDT 24
Finished Jul 24 05:26:25 PM PDT 24
Peak memory 206608 kb
Host smart-ef1fe8ef-d881-4030-b9ca-ae950863535e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22081
72029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.2208172029
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.1240436083
Short name T775
Test name
Test status
Simulation time 149672490 ps
CPU time 0.76 seconds
Started Jul 24 05:26:25 PM PDT 24
Finished Jul 24 05:26:26 PM PDT 24
Peak memory 206636 kb
Host smart-6a511ea3-71cf-4afc-b3ce-b5c8d9e15121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12404
36083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.1240436083
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.4163899805
Short name T1650
Test name
Test status
Simulation time 194274521 ps
CPU time 0.82 seconds
Started Jul 24 05:26:29 PM PDT 24
Finished Jul 24 05:26:30 PM PDT 24
Peak memory 206592 kb
Host smart-e7f60622-66d4-4c6c-a028-efc42c656022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41638
99805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.4163899805
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.576620659
Short name T2646
Test name
Test status
Simulation time 170301498 ps
CPU time 0.76 seconds
Started Jul 24 05:26:25 PM PDT 24
Finished Jul 24 05:26:26 PM PDT 24
Peak memory 206588 kb
Host smart-afa6c15a-f238-4633-8f25-0fe8aa86d880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57662
0659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.576620659
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.2596491627
Short name T1687
Test name
Test status
Simulation time 227730414 ps
CPU time 0.98 seconds
Started Jul 24 05:26:23 PM PDT 24
Finished Jul 24 05:26:25 PM PDT 24
Peak memory 206552 kb
Host smart-14befc03-0e1d-47a5-82c1-98803dc2259c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25964
91627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.2596491627
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.3556206767
Short name T2179
Test name
Test status
Simulation time 5123431424 ps
CPU time 47.43 seconds
Started Jul 24 05:26:29 PM PDT 24
Finished Jul 24 05:27:17 PM PDT 24
Peak memory 206952 kb
Host smart-0cfc652e-a488-4ab9-b890-16fbef4cb204
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3556206767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.3556206767
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.4189781413
Short name T1414
Test name
Test status
Simulation time 166479182 ps
CPU time 0.79 seconds
Started Jul 24 05:26:35 PM PDT 24
Finished Jul 24 05:26:36 PM PDT 24
Peak memory 206572 kb
Host smart-1126cae9-9fbf-47de-9348-90a3bd9e25b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41897
81413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.4189781413
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.613291613
Short name T262
Test name
Test status
Simulation time 166766576 ps
CPU time 0.8 seconds
Started Jul 24 05:26:32 PM PDT 24
Finished Jul 24 05:26:33 PM PDT 24
Peak memory 206592 kb
Host smart-774b44e3-562b-4d51-ae4b-0edcc318dac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61329
1613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.613291613
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.812713439
Short name T2501
Test name
Test status
Simulation time 285221881 ps
CPU time 1.01 seconds
Started Jul 24 05:26:37 PM PDT 24
Finished Jul 24 05:26:38 PM PDT 24
Peak memory 206536 kb
Host smart-848aa67b-3313-4411-a862-9c5b8b51fb9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81271
3439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.812713439
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.2650882464
Short name T2125
Test name
Test status
Simulation time 5434159753 ps
CPU time 50.03 seconds
Started Jul 24 05:26:27 PM PDT 24
Finished Jul 24 05:27:17 PM PDT 24
Peak memory 206952 kb
Host smart-68a7061b-7cc4-4139-9ee9-cffbdeeb5c4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26508
82464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.2650882464
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.431149352
Short name T558
Test name
Test status
Simulation time 35685122 ps
CPU time 0.65 seconds
Started Jul 24 05:24:09 PM PDT 24
Finished Jul 24 05:24:10 PM PDT 24
Peak memory 206612 kb
Host smart-97b0ab74-2405-4dec-ab7f-37f90d394fff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=431149352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.431149352
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.2902062032
Short name T941
Test name
Test status
Simulation time 3647971011 ps
CPU time 4.22 seconds
Started Jul 24 05:23:46 PM PDT 24
Finished Jul 24 05:23:50 PM PDT 24
Peak memory 206960 kb
Host smart-ad22f16f-478a-44a7-9523-0f7feff5c84b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2902062032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.2902062032
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.1526130559
Short name T2338
Test name
Test status
Simulation time 13323244593 ps
CPU time 12.76 seconds
Started Jul 24 05:23:47 PM PDT 24
Finished Jul 24 05:24:03 PM PDT 24
Peak memory 206932 kb
Host smart-df673203-66e2-4278-9db2-1968818e5cd4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1526130559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.1526130559
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.1217152054
Short name T1045
Test name
Test status
Simulation time 23349364282 ps
CPU time 24.21 seconds
Started Jul 24 05:23:49 PM PDT 24
Finished Jul 24 05:24:14 PM PDT 24
Peak memory 206908 kb
Host smart-ae24557d-e393-47a5-8e56-ee69caa98bca
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1217152054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.1217152054
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.4178084335
Short name T1598
Test name
Test status
Simulation time 154120605 ps
CPU time 0.78 seconds
Started Jul 24 05:23:49 PM PDT 24
Finished Jul 24 05:23:50 PM PDT 24
Peak memory 206388 kb
Host smart-706dcf6b-6bbd-45de-adc1-98296efb2c90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41780
84335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.4178084335
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.3241831308
Short name T44
Test name
Test status
Simulation time 174520326 ps
CPU time 0.82 seconds
Started Jul 24 05:23:54 PM PDT 24
Finished Jul 24 05:23:55 PM PDT 24
Peak memory 206552 kb
Host smart-8a4c180e-b614-4042-b0bf-249f3dfed180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32418
31308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.3241831308
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.1627453764
Short name T77
Test name
Test status
Simulation time 160702751 ps
CPU time 0.76 seconds
Started Jul 24 05:24:00 PM PDT 24
Finished Jul 24 05:24:02 PM PDT 24
Peak memory 206524 kb
Host smart-383c4796-0f50-4958-835a-e6c09f29c5f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16274
53764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.1627453764
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.1515952892
Short name T1343
Test name
Test status
Simulation time 147723359 ps
CPU time 0.79 seconds
Started Jul 24 05:23:45 PM PDT 24
Finished Jul 24 05:23:46 PM PDT 24
Peak memory 206516 kb
Host smart-6268ec99-c31b-41ee-89cf-b7e24c8d0eec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15159
52892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.1515952892
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.17798391
Short name T2334
Test name
Test status
Simulation time 218088484 ps
CPU time 0.86 seconds
Started Jul 24 05:23:50 PM PDT 24
Finished Jul 24 05:23:51 PM PDT 24
Peak memory 206596 kb
Host smart-1271d949-bd86-4f4e-b987-b23c402f5063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17798
391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.17798391
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.1145458158
Short name T1394
Test name
Test status
Simulation time 722813346 ps
CPU time 1.77 seconds
Started Jul 24 05:24:00 PM PDT 24
Finished Jul 24 05:24:03 PM PDT 24
Peak memory 206820 kb
Host smart-739872fb-675f-44b0-a3d0-0531d45939b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11454
58158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.1145458158
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.3570125474
Short name T960
Test name
Test status
Simulation time 8704258831 ps
CPU time 16.67 seconds
Started Jul 24 05:24:03 PM PDT 24
Finished Jul 24 05:24:20 PM PDT 24
Peak memory 206692 kb
Host smart-fe8c7c9f-7496-45cd-84f6-13d14bf51857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35701
25474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.3570125474
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.1421895005
Short name T2002
Test name
Test status
Simulation time 443317304 ps
CPU time 1.45 seconds
Started Jul 24 05:24:01 PM PDT 24
Finished Jul 24 05:24:03 PM PDT 24
Peak memory 206568 kb
Host smart-70e6c6d5-bc3e-4bfe-87b4-67fa684acc71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14218
95005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.1421895005
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.308812720
Short name T1682
Test name
Test status
Simulation time 140344439 ps
CPU time 0.73 seconds
Started Jul 24 05:24:00 PM PDT 24
Finished Jul 24 05:24:00 PM PDT 24
Peak memory 206496 kb
Host smart-1f1cba20-be6f-47cc-975e-a0e1f35443cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30881
2720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.308812720
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.1679861323
Short name T370
Test name
Test status
Simulation time 59006870 ps
CPU time 0.66 seconds
Started Jul 24 05:23:46 PM PDT 24
Finished Jul 24 05:23:46 PM PDT 24
Peak memory 206652 kb
Host smart-c5f4f559-6da3-4683-a292-d849919e9151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16798
61323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.1679861323
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.3338495492
Short name T1718
Test name
Test status
Simulation time 1089209414 ps
CPU time 2.21 seconds
Started Jul 24 05:24:05 PM PDT 24
Finished Jul 24 05:24:07 PM PDT 24
Peak memory 206844 kb
Host smart-5d83c2c5-0aec-4d24-9381-85db7dd6ba22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33384
95492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.3338495492
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.1509360256
Short name T2612
Test name
Test status
Simulation time 271207420 ps
CPU time 1.76 seconds
Started Jul 24 05:23:58 PM PDT 24
Finished Jul 24 05:24:00 PM PDT 24
Peak memory 206740 kb
Host smart-64074aa4-8fbe-4b69-8b2d-83e217258832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15093
60256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.1509360256
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.2418062667
Short name T745
Test name
Test status
Simulation time 121197836510 ps
CPU time 186.39 seconds
Started Jul 24 05:24:00 PM PDT 24
Finished Jul 24 05:27:07 PM PDT 24
Peak memory 207000 kb
Host smart-0e990a7b-ebba-4153-a0b9-688a48b75c64
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2418062667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.2418062667
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.4135141155
Short name T1342
Test name
Test status
Simulation time 117341407239 ps
CPU time 169.84 seconds
Started Jul 24 05:23:45 PM PDT 24
Finished Jul 24 05:26:35 PM PDT 24
Peak memory 206960 kb
Host smart-db2db518-6802-487c-b91b-af465b4f4585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135141155 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.4135141155
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.3719938507
Short name T21
Test name
Test status
Simulation time 121122462451 ps
CPU time 187.59 seconds
Started Jul 24 05:23:45 PM PDT 24
Finished Jul 24 05:26:53 PM PDT 24
Peak memory 206940 kb
Host smart-02233aeb-eb06-4970-b1df-0f852e1369b8
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3719938507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.3719938507
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.1481960815
Short name T2716
Test name
Test status
Simulation time 82175789879 ps
CPU time 101.77 seconds
Started Jul 24 05:23:49 PM PDT 24
Finished Jul 24 05:25:31 PM PDT 24
Peak memory 206760 kb
Host smart-78f4dc4e-2910-4a61-b452-1774c49e38ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481960815 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.1481960815
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.1843934027
Short name T899
Test name
Test status
Simulation time 120145714325 ps
CPU time 181.42 seconds
Started Jul 24 05:23:55 PM PDT 24
Finished Jul 24 05:26:57 PM PDT 24
Peak memory 207012 kb
Host smart-40a6f4e4-103c-469e-803d-9324102eb64a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18439
34027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.1843934027
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.285772249
Short name T2602
Test name
Test status
Simulation time 304128046 ps
CPU time 0.96 seconds
Started Jul 24 05:24:08 PM PDT 24
Finished Jul 24 05:24:09 PM PDT 24
Peak memory 206548 kb
Host smart-73f2b0ee-f4cb-49e4-9159-74bae7eb27fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28577
2249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.285772249
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.3428787021
Short name T763
Test name
Test status
Simulation time 134914956 ps
CPU time 0.74 seconds
Started Jul 24 05:24:02 PM PDT 24
Finished Jul 24 05:24:03 PM PDT 24
Peak memory 206504 kb
Host smart-bf5ee0cb-cad0-4887-abcd-844859acd8cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34287
87021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.3428787021
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.4203780068
Short name T2582
Test name
Test status
Simulation time 188999378 ps
CPU time 0.85 seconds
Started Jul 24 05:24:02 PM PDT 24
Finished Jul 24 05:24:03 PM PDT 24
Peak memory 206560 kb
Host smart-47c287cb-119b-4961-ac51-661bb3d1acab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42037
80068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.4203780068
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.2648824424
Short name T2407
Test name
Test status
Simulation time 7598904089 ps
CPU time 70.28 seconds
Started Jul 24 05:23:58 PM PDT 24
Finished Jul 24 05:25:09 PM PDT 24
Peak memory 206976 kb
Host smart-004c7fdf-ffad-4da1-a39a-f1c13fd2cc24
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2648824424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.2648824424
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_iso_retraction.3575654998
Short name T2416
Test name
Test status
Simulation time 10383436991 ps
CPU time 30.74 seconds
Started Jul 24 05:24:10 PM PDT 24
Finished Jul 24 05:24:41 PM PDT 24
Peak memory 206908 kb
Host smart-db87c782-b610-468f-9e53-1bfbcd2e7532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35756
54998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_iso_retraction.3575654998
Directory /workspace/2.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.2179446925
Short name T1370
Test name
Test status
Simulation time 185875596 ps
CPU time 0.85 seconds
Started Jul 24 05:24:02 PM PDT 24
Finished Jul 24 05:24:04 PM PDT 24
Peak memory 206556 kb
Host smart-52e58d04-ec84-4ad9-97a3-34a956819df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21794
46925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.2179446925
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.2462044567
Short name T504
Test name
Test status
Simulation time 23285716534 ps
CPU time 22.17 seconds
Started Jul 24 05:24:04 PM PDT 24
Finished Jul 24 05:24:26 PM PDT 24
Peak memory 206676 kb
Host smart-014f9e98-027c-4931-bf65-561a093ed114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24620
44567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.2462044567
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.1756675962
Short name T2243
Test name
Test status
Simulation time 3284094960 ps
CPU time 3.74 seconds
Started Jul 24 05:24:05 PM PDT 24
Finished Jul 24 05:24:09 PM PDT 24
Peak memory 206716 kb
Host smart-8f9d6707-9da1-4ace-a199-db3baeaacebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17566
75962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.1756675962
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.4109660092
Short name T1213
Test name
Test status
Simulation time 14027185567 ps
CPU time 135.07 seconds
Started Jul 24 05:23:52 PM PDT 24
Finished Jul 24 05:26:07 PM PDT 24
Peak memory 207040 kb
Host smart-4bd5e809-5f86-4235-b8de-68e109fe5204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41096
60092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.4109660092
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.292417008
Short name T1781
Test name
Test status
Simulation time 6566709060 ps
CPU time 60.95 seconds
Started Jul 24 05:23:58 PM PDT 24
Finished Jul 24 05:24:59 PM PDT 24
Peak memory 206884 kb
Host smart-15a0eb25-badd-493c-b997-87682dcda1f7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=292417008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.292417008
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.3123168602
Short name T589
Test name
Test status
Simulation time 240197741 ps
CPU time 0.92 seconds
Started Jul 24 05:23:59 PM PDT 24
Finished Jul 24 05:24:00 PM PDT 24
Peak memory 206756 kb
Host smart-ef490b44-1b96-4a93-883c-05b96296ddff
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3123168602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.3123168602
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.3063498809
Short name T1829
Test name
Test status
Simulation time 208869254 ps
CPU time 0.86 seconds
Started Jul 24 05:24:07 PM PDT 24
Finished Jul 24 05:24:08 PM PDT 24
Peak memory 206580 kb
Host smart-2639be04-0d6e-4349-b8d5-e8e8ab1e99d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30634
98809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.3063498809
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.895040332
Short name T1205
Test name
Test status
Simulation time 5971130135 ps
CPU time 55.47 seconds
Started Jul 24 05:24:00 PM PDT 24
Finished Jul 24 05:24:55 PM PDT 24
Peak memory 206880 kb
Host smart-96d6318d-75b8-429c-abd4-6dc725318cb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89504
0332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.895040332
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.3846240914
Short name T2285
Test name
Test status
Simulation time 6761748349 ps
CPU time 185.44 seconds
Started Jul 24 05:23:46 PM PDT 24
Finished Jul 24 05:26:52 PM PDT 24
Peak memory 206864 kb
Host smart-92d82fb6-778d-481d-b69f-f9e03aba75c8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3846240914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.3846240914
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.3359117106
Short name T2205
Test name
Test status
Simulation time 195168141 ps
CPU time 0.82 seconds
Started Jul 24 05:23:57 PM PDT 24
Finished Jul 24 05:23:58 PM PDT 24
Peak memory 206496 kb
Host smart-e7c5973c-6d4b-4cd3-835d-0b166a31ff3b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3359117106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.3359117106
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.3545524230
Short name T2440
Test name
Test status
Simulation time 145665095 ps
CPU time 0.75 seconds
Started Jul 24 05:23:59 PM PDT 24
Finished Jul 24 05:24:00 PM PDT 24
Peak memory 206568 kb
Host smart-4591ab3f-52e7-4ce0-8bea-0e2ec34dc5c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35455
24230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.3545524230
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.1280567199
Short name T2467
Test name
Test status
Simulation time 247037770 ps
CPU time 0.91 seconds
Started Jul 24 05:24:14 PM PDT 24
Finished Jul 24 05:24:15 PM PDT 24
Peak memory 206612 kb
Host smart-b7ca61e9-8490-44b8-bc3f-31d6dfe5a1cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12805
67199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.1280567199
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.259591576
Short name T1423
Test name
Test status
Simulation time 168887675 ps
CPU time 0.82 seconds
Started Jul 24 05:23:58 PM PDT 24
Finished Jul 24 05:23:59 PM PDT 24
Peak memory 206580 kb
Host smart-456dc8f3-bebf-4c90-9761-9004cf6e9c85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25959
1576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.259591576
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.1079311566
Short name T2459
Test name
Test status
Simulation time 176085675 ps
CPU time 0.83 seconds
Started Jul 24 05:24:13 PM PDT 24
Finished Jul 24 05:24:14 PM PDT 24
Peak memory 206552 kb
Host smart-6d643529-daf7-4bfc-b8b8-04f1a4db4494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10793
11566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.1079311566
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.2057515269
Short name T810
Test name
Test status
Simulation time 155497332 ps
CPU time 0.8 seconds
Started Jul 24 05:24:00 PM PDT 24
Finished Jul 24 05:24:02 PM PDT 24
Peak memory 206568 kb
Host smart-14a57a52-a990-4c46-beac-ce0d5e0e817b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20575
15269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.2057515269
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.2296344646
Short name T40
Test name
Test status
Simulation time 247780811 ps
CPU time 0.94 seconds
Started Jul 24 05:23:59 PM PDT 24
Finished Jul 24 05:24:00 PM PDT 24
Peak memory 206604 kb
Host smart-b4ae17e0-ebdf-4bc9-87f3-cfe7086eff12
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2296344646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.2296344646
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.2466249694
Short name T191
Test name
Test status
Simulation time 182763821 ps
CPU time 0.86 seconds
Started Jul 24 05:24:13 PM PDT 24
Finished Jul 24 05:24:14 PM PDT 24
Peak memory 206388 kb
Host smart-e1d7586a-4218-4b00-a95f-a306eae20eb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24662
49694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.2466249694
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.1332938303
Short name T2231
Test name
Test status
Simulation time 141081115 ps
CPU time 0.8 seconds
Started Jul 24 05:23:52 PM PDT 24
Finished Jul 24 05:23:53 PM PDT 24
Peak memory 206600 kb
Host smart-b3b7a11f-6d00-46c7-b45f-e47457b0e7ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13329
38303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.1332938303
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.2002721381
Short name T1147
Test name
Test status
Simulation time 40730814 ps
CPU time 0.64 seconds
Started Jul 24 05:23:54 PM PDT 24
Finished Jul 24 05:23:54 PM PDT 24
Peak memory 206580 kb
Host smart-d98d40ba-88f6-42f2-bc88-95f5d07d2df6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20027
21381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.2002721381
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.964044609
Short name T82
Test name
Test status
Simulation time 19970453093 ps
CPU time 47.03 seconds
Started Jul 24 05:23:53 PM PDT 24
Finished Jul 24 05:24:40 PM PDT 24
Peak memory 207060 kb
Host smart-2e3f932e-dd2e-4f45-805f-54b7ce202039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96404
4609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.964044609
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.183364343
Short name T901
Test name
Test status
Simulation time 184927635 ps
CPU time 0.83 seconds
Started Jul 24 05:24:03 PM PDT 24
Finished Jul 24 05:24:04 PM PDT 24
Peak memory 206556 kb
Host smart-a447bdf9-894a-49c9-ba77-c6231953ace7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18336
4343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.183364343
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.4189227431
Short name T1822
Test name
Test status
Simulation time 219296107 ps
CPU time 0.82 seconds
Started Jul 24 05:24:12 PM PDT 24
Finished Jul 24 05:24:14 PM PDT 24
Peak memory 206520 kb
Host smart-65d1f9c3-209b-4be8-a8e8-a169704387ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41892
27431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.4189227431
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.1716208336
Short name T1295
Test name
Test status
Simulation time 8901335063 ps
CPU time 77.84 seconds
Started Jul 24 05:23:59 PM PDT 24
Finished Jul 24 05:25:17 PM PDT 24
Peak memory 206880 kb
Host smart-8787405b-f38f-4cd8-b276-9c12aaed51b7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1716208336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.1716208336
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.1950090208
Short name T403
Test name
Test status
Simulation time 23197501892 ps
CPU time 525.03 seconds
Started Jul 24 05:23:46 PM PDT 24
Finished Jul 24 05:32:31 PM PDT 24
Peak memory 207020 kb
Host smart-880f0073-1c4a-433b-8cb4-62252bc33dee
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1950090208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.1950090208
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.3707202716
Short name T324
Test name
Test status
Simulation time 218990212 ps
CPU time 0.85 seconds
Started Jul 24 05:24:04 PM PDT 24
Finished Jul 24 05:24:05 PM PDT 24
Peak memory 206600 kb
Host smart-75ab5f7f-1888-459e-a918-f0c1e480d384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37072
02716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.3707202716
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.3423480508
Short name T1233
Test name
Test status
Simulation time 159137352 ps
CPU time 0.84 seconds
Started Jul 24 05:24:12 PM PDT 24
Finished Jul 24 05:24:13 PM PDT 24
Peak memory 206584 kb
Host smart-917f1346-f0b4-4018-bbcb-c77188023eec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34234
80508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.3423480508
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.1279399083
Short name T770
Test name
Test status
Simulation time 222745983 ps
CPU time 0.84 seconds
Started Jul 24 05:24:04 PM PDT 24
Finished Jul 24 05:24:05 PM PDT 24
Peak memory 206588 kb
Host smart-ff5398b2-b499-4953-8bfc-7319ab85d9a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12793
99083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.1279399083
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.2642375112
Short name T69
Test name
Test status
Simulation time 185355508 ps
CPU time 0.83 seconds
Started Jul 24 05:24:02 PM PDT 24
Finished Jul 24 05:24:02 PM PDT 24
Peak memory 206544 kb
Host smart-5526aa15-6d89-4b7a-bb68-6bc3c9943110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26423
75112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.2642375112
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.2616139350
Short name T2492
Test name
Test status
Simulation time 303881300 ps
CPU time 1.05 seconds
Started Jul 24 05:24:04 PM PDT 24
Finished Jul 24 05:24:05 PM PDT 24
Peak memory 206596 kb
Host smart-3afcc5dc-1a51-4810-b5a1-8372da420dcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26161
39350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.2616139350
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.1135285830
Short name T1711
Test name
Test status
Simulation time 314401198 ps
CPU time 0.96 seconds
Started Jul 24 05:23:48 PM PDT 24
Finished Jul 24 05:23:49 PM PDT 24
Peak memory 206568 kb
Host smart-d50a66a1-92b8-448d-8811-63bb14fb6f40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11352
85830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.1135285830
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.3800133464
Short name T2667
Test name
Test status
Simulation time 157680035 ps
CPU time 0.83 seconds
Started Jul 24 05:24:02 PM PDT 24
Finished Jul 24 05:24:03 PM PDT 24
Peak memory 206528 kb
Host smart-9213e702-2214-4f48-8687-3d58806c6ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38001
33464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.3800133464
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.2685776837
Short name T963
Test name
Test status
Simulation time 165116016 ps
CPU time 0.75 seconds
Started Jul 24 05:23:48 PM PDT 24
Finished Jul 24 05:23:49 PM PDT 24
Peak memory 206588 kb
Host smart-d7e3f10b-94cc-4adb-a16c-2a4f2e80552a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26857
76837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.2685776837
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.150627016
Short name T362
Test name
Test status
Simulation time 198157778 ps
CPU time 0.86 seconds
Started Jul 24 05:24:06 PM PDT 24
Finished Jul 24 05:24:07 PM PDT 24
Peak memory 206560 kb
Host smart-22a33090-11b9-4776-94fb-3884fbc74a93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15062
7016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.150627016
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.2303616225
Short name T2673
Test name
Test status
Simulation time 4220539440 ps
CPU time 38.83 seconds
Started Jul 24 05:24:20 PM PDT 24
Finished Jul 24 05:24:58 PM PDT 24
Peak memory 206780 kb
Host smart-fe505c50-64b5-4017-893f-aba2f009ce42
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2303616225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.2303616225
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.1870784085
Short name T2315
Test name
Test status
Simulation time 161044738 ps
CPU time 0.75 seconds
Started Jul 24 05:23:56 PM PDT 24
Finished Jul 24 05:23:57 PM PDT 24
Peak memory 206584 kb
Host smart-f82ceb84-5cdb-44ba-9f9a-e5a0e34db8b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18707
84085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.1870784085
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.1003132168
Short name T2187
Test name
Test status
Simulation time 165265936 ps
CPU time 0.79 seconds
Started Jul 24 05:24:04 PM PDT 24
Finished Jul 24 05:24:05 PM PDT 24
Peak memory 206496 kb
Host smart-f2054636-9800-4943-928e-5dbfc53182c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10031
32168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.1003132168
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.3233143031
Short name T894
Test name
Test status
Simulation time 196777471 ps
CPU time 0.85 seconds
Started Jul 24 05:23:48 PM PDT 24
Finished Jul 24 05:23:49 PM PDT 24
Peak memory 206584 kb
Host smart-edbf8183-3050-48f8-aa9a-4c141e40860a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32331
43031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.3233143031
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.989465144
Short name T917
Test name
Test status
Simulation time 5840221871 ps
CPU time 54.89 seconds
Started Jul 24 05:24:13 PM PDT 24
Finished Jul 24 05:25:08 PM PDT 24
Peak memory 206924 kb
Host smart-99cb1ab7-00e3-4d11-b1b2-e92cda6ec7e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98946
5144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.989465144
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.1929145686
Short name T155
Test name
Test status
Simulation time 6039156005 ps
CPU time 142.19 seconds
Started Jul 24 05:24:16 PM PDT 24
Finished Jul 24 05:26:38 PM PDT 24
Peak memory 206876 kb
Host smart-e485cb72-92ee-45f6-9f89-439a95fa4c76
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1929145686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.1929145686
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.76342268
Short name T1954
Test name
Test status
Simulation time 45837983 ps
CPU time 0.72 seconds
Started Jul 24 05:26:52 PM PDT 24
Finished Jul 24 05:26:53 PM PDT 24
Peak memory 206576 kb
Host smart-2ade631b-e505-4a6e-8944-df4e8442cbfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=76342268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.76342268
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.205981129
Short name T2725
Test name
Test status
Simulation time 3694069499 ps
CPU time 4.51 seconds
Started Jul 24 05:26:32 PM PDT 24
Finished Jul 24 05:26:37 PM PDT 24
Peak memory 206720 kb
Host smart-40c30017-6dd8-4521-b0de-12f64cb4556b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=205981129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.205981129
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.3331526500
Short name T1425
Test name
Test status
Simulation time 13360153508 ps
CPU time 12.57 seconds
Started Jul 24 05:26:49 PM PDT 24
Finished Jul 24 05:27:02 PM PDT 24
Peak memory 206668 kb
Host smart-f28ceccf-9634-4e9c-924c-2bc1fce97824
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3331526500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.3331526500
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.3671662372
Short name T553
Test name
Test status
Simulation time 23397027185 ps
CPU time 25.55 seconds
Started Jul 24 05:26:25 PM PDT 24
Finished Jul 24 05:26:51 PM PDT 24
Peak memory 206916 kb
Host smart-3d7e3a3f-52ba-4976-afdc-ca825ab432be
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3671662372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.3671662372
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.2785355036
Short name T463
Test name
Test status
Simulation time 187284977 ps
CPU time 0.8 seconds
Started Jul 24 05:26:20 PM PDT 24
Finished Jul 24 05:26:21 PM PDT 24
Peak memory 206552 kb
Host smart-dde1f6db-e4d4-4407-9337-a05eeb9d97e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27853
55036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.2785355036
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.107074944
Short name T1070
Test name
Test status
Simulation time 155592154 ps
CPU time 0.77 seconds
Started Jul 24 05:26:24 PM PDT 24
Finished Jul 24 05:26:24 PM PDT 24
Peak memory 206584 kb
Host smart-a7d27bed-33cd-45d0-8c85-88b667a7dba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10707
4944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.107074944
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.2856719112
Short name T1278
Test name
Test status
Simulation time 1140620408 ps
CPU time 2.57 seconds
Started Jul 24 05:26:26 PM PDT 24
Finished Jul 24 05:26:29 PM PDT 24
Peak memory 206860 kb
Host smart-5d68289e-0c1f-4e3e-b2d1-68c5a417adf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28567
19112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.2856719112
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.3375965153
Short name T87
Test name
Test status
Simulation time 10244501521 ps
CPU time 22.96 seconds
Started Jul 24 05:26:37 PM PDT 24
Finished Jul 24 05:27:00 PM PDT 24
Peak memory 206888 kb
Host smart-8aee59a3-204d-4589-a9b4-9541441882f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33759
65153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.3375965153
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.2156000363
Short name T965
Test name
Test status
Simulation time 406341650 ps
CPU time 1.22 seconds
Started Jul 24 05:26:36 PM PDT 24
Finished Jul 24 05:26:38 PM PDT 24
Peak memory 206608 kb
Host smart-3f00b17b-96f3-4d33-b2a3-906fca05bf3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21560
00363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.2156000363
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_enable.3830698757
Short name T834
Test name
Test status
Simulation time 42358708 ps
CPU time 0.67 seconds
Started Jul 24 05:26:49 PM PDT 24
Finished Jul 24 05:26:50 PM PDT 24
Peak memory 206604 kb
Host smart-9a415e07-51f2-4036-8151-88df7d4d745c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38306
98757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.3830698757
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.2703748162
Short name T680
Test name
Test status
Simulation time 969615412 ps
CPU time 2.23 seconds
Started Jul 24 05:26:38 PM PDT 24
Finished Jul 24 05:26:41 PM PDT 24
Peak memory 206752 kb
Host smart-51341d7d-8eb4-484a-8d0b-5fd2d53d11ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27037
48162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.2703748162
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.220724188
Short name T584
Test name
Test status
Simulation time 157710531 ps
CPU time 1.51 seconds
Started Jul 24 05:26:36 PM PDT 24
Finished Jul 24 05:26:38 PM PDT 24
Peak memory 206716 kb
Host smart-bb797cbf-4c48-4f54-88c4-9bdc1f9ac06a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22072
4188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.220724188
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.2745771401
Short name T2636
Test name
Test status
Simulation time 179204181 ps
CPU time 0.82 seconds
Started Jul 24 05:26:24 PM PDT 24
Finished Jul 24 05:26:25 PM PDT 24
Peak memory 206588 kb
Host smart-d9474e71-6b5c-45e5-ba2f-b476933a4392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27457
71401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.2745771401
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.1006628565
Short name T1100
Test name
Test status
Simulation time 164164853 ps
CPU time 0.76 seconds
Started Jul 24 05:26:24 PM PDT 24
Finished Jul 24 05:26:25 PM PDT 24
Peak memory 206552 kb
Host smart-f92e30fe-ea6f-4590-a76a-3b74c983b464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10066
28565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.1006628565
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.2551170999
Short name T2599
Test name
Test status
Simulation time 231973887 ps
CPU time 0.96 seconds
Started Jul 24 05:26:38 PM PDT 24
Finished Jul 24 05:26:39 PM PDT 24
Peak memory 206548 kb
Host smart-2f86c48d-71b9-4fe9-b03f-fcc62aa2d24f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25511
70999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.2551170999
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_iso_retraction.2341172929
Short name T1499
Test name
Test status
Simulation time 4248732285 ps
CPU time 35.36 seconds
Started Jul 24 05:26:51 PM PDT 24
Finished Jul 24 05:27:27 PM PDT 24
Peak memory 206960 kb
Host smart-836aed20-d409-40c7-8b54-c737e354d7be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23411
72929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.2341172929
Directory /workspace/20.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.2041794018
Short name T793
Test name
Test status
Simulation time 232605107 ps
CPU time 0.94 seconds
Started Jul 24 05:26:25 PM PDT 24
Finished Jul 24 05:26:31 PM PDT 24
Peak memory 206592 kb
Host smart-c2476a64-31f1-4386-85ad-33150277f803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20417
94018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.2041794018
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.3517591851
Short name T1347
Test name
Test status
Simulation time 23294864597 ps
CPU time 24.49 seconds
Started Jul 24 05:26:29 PM PDT 24
Finished Jul 24 05:26:54 PM PDT 24
Peak memory 206704 kb
Host smart-642e6437-57b1-45b2-a7b4-d305c231e39c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35175
91851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.3517591851
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.2653276703
Short name T2753
Test name
Test status
Simulation time 3267576720 ps
CPU time 3.54 seconds
Started Jul 24 05:26:22 PM PDT 24
Finished Jul 24 05:26:26 PM PDT 24
Peak memory 206652 kb
Host smart-b85584fb-820c-4857-a107-b6b58b58135f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26532
76703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.2653276703
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.1035547987
Short name T2156
Test name
Test status
Simulation time 6605851028 ps
CPU time 183.8 seconds
Started Jul 24 05:26:26 PM PDT 24
Finished Jul 24 05:29:30 PM PDT 24
Peak memory 206900 kb
Host smart-ef5b9a08-8d97-4f68-aba2-4551a8522d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10355
47987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.1035547987
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.3487878532
Short name T2697
Test name
Test status
Simulation time 5849434621 ps
CPU time 155.16 seconds
Started Jul 24 05:26:38 PM PDT 24
Finished Jul 24 05:29:13 PM PDT 24
Peak memory 206852 kb
Host smart-d6d053e5-4ec0-4e24-b98f-2416e9333c5e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3487878532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.3487878532
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.18516909
Short name T2522
Test name
Test status
Simulation time 263056902 ps
CPU time 0.94 seconds
Started Jul 24 05:26:29 PM PDT 24
Finished Jul 24 05:26:30 PM PDT 24
Peak memory 206604 kb
Host smart-4d736869-9cae-4c4a-8628-951d0eb9d9fd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=18516909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.18516909
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.60119051
Short name T1383
Test name
Test status
Simulation time 220644601 ps
CPU time 0.9 seconds
Started Jul 24 05:26:26 PM PDT 24
Finished Jul 24 05:26:27 PM PDT 24
Peak memory 206532 kb
Host smart-cfde15ff-eae5-4c74-b560-1d04d1c83208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60119
051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.60119051
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.1912636414
Short name T1514
Test name
Test status
Simulation time 5342234229 ps
CPU time 148.92 seconds
Started Jul 24 05:26:29 PM PDT 24
Finished Jul 24 05:28:58 PM PDT 24
Peak memory 206984 kb
Host smart-54335288-dece-4a84-a7c6-17da44ff135a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19126
36414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.1912636414
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.3737979872
Short name T1545
Test name
Test status
Simulation time 4918083594 ps
CPU time 34.54 seconds
Started Jul 24 05:26:44 PM PDT 24
Finished Jul 24 05:27:18 PM PDT 24
Peak memory 206896 kb
Host smart-8e3b6764-34a5-4f8c-b6e8-9026214d9108
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3737979872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.3737979872
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.760480155
Short name T2431
Test name
Test status
Simulation time 155346937 ps
CPU time 0.81 seconds
Started Jul 24 05:26:27 PM PDT 24
Finished Jul 24 05:26:28 PM PDT 24
Peak memory 206576 kb
Host smart-e5d3c065-bc87-492d-a926-8af6b59c9310
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=760480155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.760480155
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.1030416949
Short name T1997
Test name
Test status
Simulation time 204008039 ps
CPU time 0.76 seconds
Started Jul 24 05:26:47 PM PDT 24
Finished Jul 24 05:26:48 PM PDT 24
Peak memory 206604 kb
Host smart-278a4dd0-921d-475f-8e24-112f68c1f9fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10304
16949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.1030416949
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.232818739
Short name T1910
Test name
Test status
Simulation time 216258161 ps
CPU time 0.9 seconds
Started Jul 24 05:26:50 PM PDT 24
Finished Jul 24 05:26:51 PM PDT 24
Peak memory 206564 kb
Host smart-ada096f9-e201-4a49-a15a-784c7b80e12a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23281
8739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.232818739
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.1582924612
Short name T551
Test name
Test status
Simulation time 190218666 ps
CPU time 0.82 seconds
Started Jul 24 05:26:38 PM PDT 24
Finished Jul 24 05:26:39 PM PDT 24
Peak memory 206596 kb
Host smart-e126a716-dafd-4cc4-9d72-90e5df4cadb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15829
24612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.1582924612
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.817123818
Short name T425
Test name
Test status
Simulation time 177272733 ps
CPU time 0.76 seconds
Started Jul 24 05:26:27 PM PDT 24
Finished Jul 24 05:26:28 PM PDT 24
Peak memory 206544 kb
Host smart-a2c5e75c-53ef-42d1-886f-5667e58552ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81712
3818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.817123818
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.468107869
Short name T422
Test name
Test status
Simulation time 203727044 ps
CPU time 0.86 seconds
Started Jul 24 05:26:34 PM PDT 24
Finished Jul 24 05:26:35 PM PDT 24
Peak memory 206600 kb
Host smart-cf1a028f-e6c9-47e8-ae7c-687d0cd82bcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46810
7869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.468107869
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.2802271589
Short name T2680
Test name
Test status
Simulation time 197535041 ps
CPU time 0.8 seconds
Started Jul 24 05:26:44 PM PDT 24
Finished Jul 24 05:26:45 PM PDT 24
Peak memory 206536 kb
Host smart-089e1b4f-26b6-44dc-9433-2453427e09f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28022
71589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.2802271589
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.2788605207
Short name T1467
Test name
Test status
Simulation time 253340891 ps
CPU time 0.99 seconds
Started Jul 24 05:26:25 PM PDT 24
Finished Jul 24 05:26:27 PM PDT 24
Peak memory 206620 kb
Host smart-d08ef9dc-18b2-4237-b705-dac66c2541ca
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2788605207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.2788605207
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.186991063
Short name T1284
Test name
Test status
Simulation time 142293993 ps
CPU time 0.76 seconds
Started Jul 24 05:26:30 PM PDT 24
Finished Jul 24 05:26:31 PM PDT 24
Peak memory 206476 kb
Host smart-48a26b97-367e-4c27-9f93-a474b0a46a13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18699
1063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.186991063
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.701306086
Short name T2436
Test name
Test status
Simulation time 41314635 ps
CPU time 0.64 seconds
Started Jul 24 05:26:32 PM PDT 24
Finished Jul 24 05:26:33 PM PDT 24
Peak memory 206556 kb
Host smart-a2b6fad0-da94-4741-bc76-f3b84b61f66c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70130
6086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.701306086
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.1995309336
Short name T1828
Test name
Test status
Simulation time 14679215045 ps
CPU time 34.03 seconds
Started Jul 24 05:26:28 PM PDT 24
Finished Jul 24 05:27:02 PM PDT 24
Peak memory 206956 kb
Host smart-8ba5084a-6069-46d6-a6e5-6a6095afe369
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19953
09336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.1995309336
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.3436552715
Short name T282
Test name
Test status
Simulation time 193254679 ps
CPU time 0.8 seconds
Started Jul 24 05:26:32 PM PDT 24
Finished Jul 24 05:26:33 PM PDT 24
Peak memory 206560 kb
Host smart-7ed0d2c0-d742-4c62-ba70-43a7e51cd353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34365
52715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.3436552715
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.1117689155
Short name T815
Test name
Test status
Simulation time 245483886 ps
CPU time 0.88 seconds
Started Jul 24 05:26:44 PM PDT 24
Finished Jul 24 05:26:45 PM PDT 24
Peak memory 206564 kb
Host smart-fe8cd43d-7caa-4d67-8c16-9e94bff58a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11176
89155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.1117689155
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.3525584454
Short name T513
Test name
Test status
Simulation time 189703007 ps
CPU time 0.83 seconds
Started Jul 24 05:26:26 PM PDT 24
Finished Jul 24 05:26:27 PM PDT 24
Peak memory 206568 kb
Host smart-6e69e6e3-35df-4f33-94e2-896490e98159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35255
84454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.3525584454
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.886526789
Short name T876
Test name
Test status
Simulation time 160096993 ps
CPU time 0.83 seconds
Started Jul 24 05:26:27 PM PDT 24
Finished Jul 24 05:26:28 PM PDT 24
Peak memory 206552 kb
Host smart-fcb05b73-edfe-4075-8254-48a6d4415705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88652
6789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.886526789
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.1177338524
Short name T927
Test name
Test status
Simulation time 177731976 ps
CPU time 0.82 seconds
Started Jul 24 05:26:43 PM PDT 24
Finished Jul 24 05:26:44 PM PDT 24
Peak memory 206520 kb
Host smart-c0694176-05b1-4a8b-8926-f5d69021a87e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11773
38524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.1177338524
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.2632418464
Short name T1583
Test name
Test status
Simulation time 166267311 ps
CPU time 0.78 seconds
Started Jul 24 05:26:32 PM PDT 24
Finished Jul 24 05:26:33 PM PDT 24
Peak memory 206560 kb
Host smart-3d3ff2f7-087c-4c80-ae3d-3a6c8cbf6b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26324
18464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.2632418464
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.1717360175
Short name T524
Test name
Test status
Simulation time 164044557 ps
CPU time 0.8 seconds
Started Jul 24 05:26:26 PM PDT 24
Finished Jul 24 05:26:27 PM PDT 24
Peak memory 206520 kb
Host smart-e48924b9-579c-4f95-ab81-fa5b491e3051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17173
60175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.1717360175
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.1107828644
Short name T1529
Test name
Test status
Simulation time 220873018 ps
CPU time 0.96 seconds
Started Jul 24 05:26:36 PM PDT 24
Finished Jul 24 05:26:37 PM PDT 24
Peak memory 206504 kb
Host smart-ca10e9b4-3d22-40cc-9bc2-ef4a3801c487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11078
28644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.1107828644
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.1280687693
Short name T1049
Test name
Test status
Simulation time 4963561750 ps
CPU time 140.99 seconds
Started Jul 24 05:26:30 PM PDT 24
Finished Jul 24 05:28:51 PM PDT 24
Peak memory 206836 kb
Host smart-52f1b3b4-5d83-42f9-86b4-e4af19cc5b76
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1280687693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.1280687693
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.2543154516
Short name T1631
Test name
Test status
Simulation time 170589276 ps
CPU time 0.79 seconds
Started Jul 24 05:26:38 PM PDT 24
Finished Jul 24 05:26:39 PM PDT 24
Peak memory 206664 kb
Host smart-0e5f5b70-03a6-410e-936b-c199c9932286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25431
54516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.2543154516
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.3635881666
Short name T1904
Test name
Test status
Simulation time 188739788 ps
CPU time 0.8 seconds
Started Jul 24 05:26:44 PM PDT 24
Finished Jul 24 05:26:45 PM PDT 24
Peak memory 206580 kb
Host smart-5ce7d397-5af4-4cc4-9542-a6878c80324f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36358
81666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.3635881666
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.1186545631
Short name T399
Test name
Test status
Simulation time 736538367 ps
CPU time 1.8 seconds
Started Jul 24 05:26:44 PM PDT 24
Finished Jul 24 05:26:46 PM PDT 24
Peak memory 206708 kb
Host smart-dd8033a3-07f5-4522-95ab-e70e07287103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11865
45631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.1186545631
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.3027900012
Short name T2087
Test name
Test status
Simulation time 7177101816 ps
CPU time 206.09 seconds
Started Jul 24 05:26:46 PM PDT 24
Finished Jul 24 05:30:12 PM PDT 24
Peak memory 206740 kb
Host smart-ddf8791d-3a76-4d46-b8d3-be5d1498e535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30279
00012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.3027900012
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.2479569301
Short name T869
Test name
Test status
Simulation time 92956786 ps
CPU time 0.71 seconds
Started Jul 24 05:26:43 PM PDT 24
Finished Jul 24 05:26:43 PM PDT 24
Peak memory 206588 kb
Host smart-056214ba-4e14-4cb9-b154-363989bd4cc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2479569301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.2479569301
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.1156405621
Short name T1294
Test name
Test status
Simulation time 3640197318 ps
CPU time 5.73 seconds
Started Jul 24 05:26:41 PM PDT 24
Finished Jul 24 05:26:47 PM PDT 24
Peak memory 206796 kb
Host smart-66b05b8c-d406-4956-a00b-51030103a16f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1156405621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.1156405621
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.3460254676
Short name T469
Test name
Test status
Simulation time 13400919391 ps
CPU time 15.96 seconds
Started Jul 24 05:26:52 PM PDT 24
Finished Jul 24 05:27:08 PM PDT 24
Peak memory 206612 kb
Host smart-72319b29-6dbd-41c4-b122-875fd7c659d5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3460254676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.3460254676
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.2799979951
Short name T599
Test name
Test status
Simulation time 23395570681 ps
CPU time 25 seconds
Started Jul 24 05:26:36 PM PDT 24
Finished Jul 24 05:27:01 PM PDT 24
Peak memory 206728 kb
Host smart-6040a13c-6657-40f7-87f6-b2d2ea228ab3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2799979951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.2799979951
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.3162840433
Short name T738
Test name
Test status
Simulation time 161711712 ps
CPU time 0.83 seconds
Started Jul 24 05:26:56 PM PDT 24
Finished Jul 24 05:26:57 PM PDT 24
Peak memory 206540 kb
Host smart-4799a6ad-f8b7-4015-8b35-5433e70589cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31628
40433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.3162840433
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.2568496704
Short name T20
Test name
Test status
Simulation time 147936419 ps
CPU time 0.76 seconds
Started Jul 24 05:26:30 PM PDT 24
Finished Jul 24 05:26:31 PM PDT 24
Peak memory 206544 kb
Host smart-84975d63-33c2-4eb3-887c-938a65b08e6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25684
96704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.2568496704
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.4206357476
Short name T2387
Test name
Test status
Simulation time 655418188 ps
CPU time 1.79 seconds
Started Jul 24 05:26:27 PM PDT 24
Finished Jul 24 05:26:29 PM PDT 24
Peak memory 206756 kb
Host smart-b107f72f-b035-483a-ae75-eae850bba2e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42063
57476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.4206357476
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.2727673766
Short name T2727
Test name
Test status
Simulation time 478227009 ps
CPU time 1.37 seconds
Started Jul 24 05:26:27 PM PDT 24
Finished Jul 24 05:26:28 PM PDT 24
Peak memory 206588 kb
Host smart-8d5cfd0c-801e-459b-8e61-1646f403fb86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27276
73766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.2727673766
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.3092904436
Short name T1804
Test name
Test status
Simulation time 13609415895 ps
CPU time 26.45 seconds
Started Jul 24 05:26:41 PM PDT 24
Finished Jul 24 05:27:08 PM PDT 24
Peak memory 206956 kb
Host smart-7677b7cf-d0c2-4012-9ca8-f1b487d10828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30929
04436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.3092904436
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.3620210352
Short name T318
Test name
Test status
Simulation time 449737435 ps
CPU time 1.34 seconds
Started Jul 24 05:26:25 PM PDT 24
Finished Jul 24 05:26:27 PM PDT 24
Peak memory 206588 kb
Host smart-cc5ef390-3ba6-4a90-8fa4-0187772b4ab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36202
10352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.3620210352
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.3114320666
Short name T1982
Test name
Test status
Simulation time 147825412 ps
CPU time 0.76 seconds
Started Jul 24 05:26:25 PM PDT 24
Finished Jul 24 05:26:26 PM PDT 24
Peak memory 206588 kb
Host smart-04f4a6c7-4700-482d-baed-a19f24f4357d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31143
20666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.3114320666
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.4116014276
Short name T978
Test name
Test status
Simulation time 40101602 ps
CPU time 0.71 seconds
Started Jul 24 05:26:42 PM PDT 24
Finished Jul 24 05:26:43 PM PDT 24
Peak memory 206560 kb
Host smart-1a86fb10-ff11-4d48-8787-66227abe87ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41160
14276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.4116014276
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.549461897
Short name T1596
Test name
Test status
Simulation time 961757480 ps
CPU time 2.45 seconds
Started Jul 24 05:26:41 PM PDT 24
Finished Jul 24 05:26:43 PM PDT 24
Peak memory 206804 kb
Host smart-3cee5625-b2bf-4e70-a92f-f0c7d467b302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54946
1897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.549461897
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.3833760358
Short name T1805
Test name
Test status
Simulation time 181828575 ps
CPU time 1.56 seconds
Started Jul 24 05:26:26 PM PDT 24
Finished Jul 24 05:26:28 PM PDT 24
Peak memory 206844 kb
Host smart-6bfd14a7-189e-4edd-848a-c1631d82dcb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38337
60358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.3833760358
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.3014041297
Short name T2215
Test name
Test status
Simulation time 176390295 ps
CPU time 0.81 seconds
Started Jul 24 05:26:44 PM PDT 24
Finished Jul 24 05:26:45 PM PDT 24
Peak memory 206512 kb
Host smart-2cca5a5a-abd1-4e78-b054-43f707de5c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30140
41297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.3014041297
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.3003203751
Short name T1772
Test name
Test status
Simulation time 177542468 ps
CPU time 0.76 seconds
Started Jul 24 05:26:54 PM PDT 24
Finished Jul 24 05:26:55 PM PDT 24
Peak memory 206596 kb
Host smart-ac9ff451-e1ae-40e6-bb8a-3604d1b8e1c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30032
03751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.3003203751
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.352921528
Short name T2304
Test name
Test status
Simulation time 223853074 ps
CPU time 0.88 seconds
Started Jul 24 05:26:39 PM PDT 24
Finished Jul 24 05:26:40 PM PDT 24
Peak memory 206532 kb
Host smart-2851a368-16b2-43a9-acbb-3585ede77985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35292
1528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.352921528
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_iso_retraction.2261674991
Short name T1327
Test name
Test status
Simulation time 4238682176 ps
CPU time 33.93 seconds
Started Jul 24 05:26:30 PM PDT 24
Finished Jul 24 05:27:04 PM PDT 24
Peak memory 206832 kb
Host smart-e790c7c9-3166-4d43-bf7e-bf4cd98f23a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22616
74991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_iso_retraction.2261674991
Directory /workspace/21.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.546206884
Short name T2201
Test name
Test status
Simulation time 185587759 ps
CPU time 0.83 seconds
Started Jul 24 05:26:47 PM PDT 24
Finished Jul 24 05:26:48 PM PDT 24
Peak memory 206576 kb
Host smart-1e396959-e0b8-4214-9a56-bf5a8b8bd4b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54620
6884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.546206884
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.4145328820
Short name T924
Test name
Test status
Simulation time 23289635392 ps
CPU time 25.86 seconds
Started Jul 24 05:26:40 PM PDT 24
Finished Jul 24 05:27:06 PM PDT 24
Peak memory 206620 kb
Host smart-1aac54f9-859c-4875-ac41-72c112e7d3d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41453
28820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.4145328820
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.24269051
Short name T1024
Test name
Test status
Simulation time 3318135574 ps
CPU time 4.35 seconds
Started Jul 24 05:26:25 PM PDT 24
Finished Jul 24 05:26:30 PM PDT 24
Peak memory 206724 kb
Host smart-5575ec52-44c6-401a-8789-c25887d68dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24269
051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.24269051
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.2391880751
Short name T1635
Test name
Test status
Simulation time 9037093332 ps
CPU time 242.15 seconds
Started Jul 24 05:26:29 PM PDT 24
Finished Jul 24 05:30:31 PM PDT 24
Peak memory 206916 kb
Host smart-b92a5d8d-2dc2-4ff2-85f2-5d2d33e95666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23918
80751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.2391880751
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.2003401796
Short name T412
Test name
Test status
Simulation time 5582444649 ps
CPU time 39.15 seconds
Started Jul 24 05:26:37 PM PDT 24
Finished Jul 24 05:27:17 PM PDT 24
Peak memory 206916 kb
Host smart-b81033ca-3909-4652-bbe7-a973e710ef7e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2003401796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.2003401796
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.2779629229
Short name T964
Test name
Test status
Simulation time 261866492 ps
CPU time 0.93 seconds
Started Jul 24 05:26:25 PM PDT 24
Finished Jul 24 05:26:27 PM PDT 24
Peak memory 206612 kb
Host smart-6421bd52-f7fa-49d5-b0f8-2444a04eb4b6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2779629229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.2779629229
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.655428360
Short name T409
Test name
Test status
Simulation time 182470320 ps
CPU time 0.83 seconds
Started Jul 24 05:26:49 PM PDT 24
Finished Jul 24 05:26:50 PM PDT 24
Peak memory 206536 kb
Host smart-97f8d870-d8a3-4e7e-b82d-cecca72fbe21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65542
8360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.655428360
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.3641771898
Short name T1680
Test name
Test status
Simulation time 5136458237 ps
CPU time 48.54 seconds
Started Jul 24 05:26:51 PM PDT 24
Finished Jul 24 05:27:40 PM PDT 24
Peak memory 206920 kb
Host smart-91050c19-8e44-407f-84a6-7ec0c16d44a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36417
71898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.3641771898
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.3244292132
Short name T571
Test name
Test status
Simulation time 6491461290 ps
CPU time 43.48 seconds
Started Jul 24 05:26:43 PM PDT 24
Finished Jul 24 05:27:27 PM PDT 24
Peak memory 206896 kb
Host smart-6ac34afa-1f63-4efa-ad36-e1449e004549
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3244292132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.3244292132
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.3156248385
Short name T2453
Test name
Test status
Simulation time 225081251 ps
CPU time 0.84 seconds
Started Jul 24 05:26:47 PM PDT 24
Finished Jul 24 05:26:48 PM PDT 24
Peak memory 206556 kb
Host smart-d57ba4a6-6aea-4973-a087-d3a9993f6df1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3156248385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.3156248385
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.2241216695
Short name T2723
Test name
Test status
Simulation time 137274984 ps
CPU time 0.77 seconds
Started Jul 24 05:26:42 PM PDT 24
Finished Jul 24 05:26:43 PM PDT 24
Peak memory 206600 kb
Host smart-8da15f11-51d6-4d1c-a873-0189ae38d602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22412
16695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.2241216695
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.3830241956
Short name T2239
Test name
Test status
Simulation time 251555461 ps
CPU time 0.93 seconds
Started Jul 24 05:26:31 PM PDT 24
Finished Jul 24 05:26:32 PM PDT 24
Peak memory 206596 kb
Host smart-e3b96248-7878-4ceb-ab93-ac2c80a97b33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38302
41956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.3830241956
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.2197447406
Short name T1156
Test name
Test status
Simulation time 231512552 ps
CPU time 0.91 seconds
Started Jul 24 05:26:38 PM PDT 24
Finished Jul 24 05:26:39 PM PDT 24
Peak memory 206516 kb
Host smart-c7efaadd-ccb2-473f-8f3b-429d25abf8ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21974
47406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.2197447406
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.2592928799
Short name T522
Test name
Test status
Simulation time 141209220 ps
CPU time 0.76 seconds
Started Jul 24 05:26:42 PM PDT 24
Finished Jul 24 05:26:43 PM PDT 24
Peak memory 206596 kb
Host smart-a179f595-e029-4514-a802-c29d7cc22eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25929
28799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.2592928799
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.2186447745
Short name T596
Test name
Test status
Simulation time 145695934 ps
CPU time 0.77 seconds
Started Jul 24 05:26:58 PM PDT 24
Finished Jul 24 05:26:59 PM PDT 24
Peak memory 206584 kb
Host smart-967b3b80-2baa-4df3-a2f9-1575666e55f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21864
47745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.2186447745
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.1060573907
Short name T1540
Test name
Test status
Simulation time 150190988 ps
CPU time 0.78 seconds
Started Jul 24 05:26:50 PM PDT 24
Finished Jul 24 05:26:51 PM PDT 24
Peak memory 206636 kb
Host smart-fc2b4665-b875-4c93-a75f-1ccd963858a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10605
73907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.1060573907
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.781709306
Short name T150
Test name
Test status
Simulation time 227490024 ps
CPU time 0.98 seconds
Started Jul 24 05:26:48 PM PDT 24
Finished Jul 24 05:26:50 PM PDT 24
Peak memory 206620 kb
Host smart-2de28bff-920b-4d0a-8e21-050fb4942c3a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=781709306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.781709306
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.3697343886
Short name T1064
Test name
Test status
Simulation time 168724031 ps
CPU time 0.75 seconds
Started Jul 24 05:26:40 PM PDT 24
Finished Jul 24 05:26:41 PM PDT 24
Peak memory 206624 kb
Host smart-f69dd69f-1ddd-469b-b4f4-516bb4eb0294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36973
43886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.3697343886
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.281399950
Short name T816
Test name
Test status
Simulation time 61978389 ps
CPU time 0.67 seconds
Started Jul 24 05:26:57 PM PDT 24
Finished Jul 24 05:26:58 PM PDT 24
Peak memory 206524 kb
Host smart-ec275bd4-ee3a-473b-b840-fe163ee9a55c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28139
9950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.281399950
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.3019637294
Short name T2412
Test name
Test status
Simulation time 21083128825 ps
CPU time 45.3 seconds
Started Jul 24 05:26:51 PM PDT 24
Finished Jul 24 05:27:37 PM PDT 24
Peak memory 206928 kb
Host smart-ecf0048a-1d76-4dcb-b696-0b7e3e13936c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30196
37294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.3019637294
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.669017655
Short name T2183
Test name
Test status
Simulation time 183681067 ps
CPU time 0.83 seconds
Started Jul 24 05:26:46 PM PDT 24
Finished Jul 24 05:26:47 PM PDT 24
Peak memory 206576 kb
Host smart-a45b8725-4628-49f6-b3e9-e62d02497e67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66901
7655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.669017655
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.3703662917
Short name T554
Test name
Test status
Simulation time 183314355 ps
CPU time 0.82 seconds
Started Jul 24 05:26:49 PM PDT 24
Finished Jul 24 05:26:50 PM PDT 24
Peak memory 206628 kb
Host smart-67dd3a25-33c9-43b3-8495-5e89263b55f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37036
62917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.3703662917
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.205743602
Short name T2348
Test name
Test status
Simulation time 191971041 ps
CPU time 0.83 seconds
Started Jul 24 05:26:52 PM PDT 24
Finished Jul 24 05:26:53 PM PDT 24
Peak memory 206560 kb
Host smart-f40cd504-41cd-47d8-9368-1a87a1fa9d37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20574
3602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.205743602
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.2903152187
Short name T1487
Test name
Test status
Simulation time 178822472 ps
CPU time 0.81 seconds
Started Jul 24 05:26:42 PM PDT 24
Finished Jul 24 05:26:43 PM PDT 24
Peak memory 206572 kb
Host smart-d1dbe85e-7a62-476c-bc2f-1c8234b4a51a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29031
52187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.2903152187
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.575513733
Short name T2274
Test name
Test status
Simulation time 177145945 ps
CPU time 0.79 seconds
Started Jul 24 05:26:47 PM PDT 24
Finished Jul 24 05:26:48 PM PDT 24
Peak memory 206584 kb
Host smart-b37d94ad-34f2-4729-931e-52d7f11ca7b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57551
3733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.575513733
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.4086527925
Short name T932
Test name
Test status
Simulation time 214253223 ps
CPU time 0.85 seconds
Started Jul 24 05:26:36 PM PDT 24
Finished Jul 24 05:26:37 PM PDT 24
Peak memory 206476 kb
Host smart-ccffde9f-cba3-4e04-80e8-9eec24b18382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40865
27925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.4086527925
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.2929852110
Short name T975
Test name
Test status
Simulation time 150373393 ps
CPU time 0.77 seconds
Started Jul 24 05:26:44 PM PDT 24
Finished Jul 24 05:26:45 PM PDT 24
Peak memory 206536 kb
Host smart-421baacc-6343-4120-8eda-70ddbe7d7a5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29298
52110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.2929852110
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.2028426829
Short name T1444
Test name
Test status
Simulation time 194025529 ps
CPU time 0.86 seconds
Started Jul 24 05:26:33 PM PDT 24
Finished Jul 24 05:26:40 PM PDT 24
Peak memory 206468 kb
Host smart-49a33be9-125d-4f9f-bf7e-543b8a05bd3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20284
26829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.2028426829
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.1922151531
Short name T338
Test name
Test status
Simulation time 5249397933 ps
CPU time 48.65 seconds
Started Jul 24 05:26:43 PM PDT 24
Finished Jul 24 05:27:32 PM PDT 24
Peak memory 206960 kb
Host smart-d9bdf183-6162-47a9-8d1b-9dc1e83d360e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1922151531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.1922151531
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.1761093020
Short name T2509
Test name
Test status
Simulation time 176538709 ps
CPU time 0.8 seconds
Started Jul 24 05:26:35 PM PDT 24
Finished Jul 24 05:26:36 PM PDT 24
Peak memory 206464 kb
Host smart-186406ca-3010-4c07-b3ef-3313494f5826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17610
93020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.1761093020
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.3523787122
Short name T59
Test name
Test status
Simulation time 170341978 ps
CPU time 0.77 seconds
Started Jul 24 05:26:50 PM PDT 24
Finished Jul 24 05:26:51 PM PDT 24
Peak memory 206576 kb
Host smart-572609dc-72aa-49c2-9600-960a0e65fa5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35237
87122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.3523787122
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.1650563070
Short name T2020
Test name
Test status
Simulation time 394362896 ps
CPU time 1.16 seconds
Started Jul 24 05:26:51 PM PDT 24
Finished Jul 24 05:26:52 PM PDT 24
Peak memory 206556 kb
Host smart-94e2ffa3-93b8-4457-bfbc-790d9a91cd2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16505
63070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.1650563070
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.2813858720
Short name T1027
Test name
Test status
Simulation time 5256068267 ps
CPU time 46.06 seconds
Started Jul 24 05:26:46 PM PDT 24
Finished Jul 24 05:27:32 PM PDT 24
Peak memory 206840 kb
Host smart-6b4c6919-94de-4b1d-a12c-57c2f7ad69f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28138
58720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.2813858720
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.2027413426
Short name T175
Test name
Test status
Simulation time 46565571 ps
CPU time 0.69 seconds
Started Jul 24 05:26:51 PM PDT 24
Finished Jul 24 05:26:52 PM PDT 24
Peak memory 206616 kb
Host smart-1f86e329-459f-411c-a960-05daf363083f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2027413426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.2027413426
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.2302952194
Short name T2229
Test name
Test status
Simulation time 3829007885 ps
CPU time 4.3 seconds
Started Jul 24 05:26:43 PM PDT 24
Finished Jul 24 05:26:53 PM PDT 24
Peak memory 206624 kb
Host smart-5b50fad5-1372-4aa4-b941-8dc50db6e6cc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2302952194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.2302952194
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.1997480772
Short name T784
Test name
Test status
Simulation time 13397308444 ps
CPU time 13.05 seconds
Started Jul 24 05:26:47 PM PDT 24
Finished Jul 24 05:27:00 PM PDT 24
Peak memory 206716 kb
Host smart-083cba9c-0336-442d-b417-63cebbe7bea2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1997480772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.1997480772
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.1611594750
Short name T1599
Test name
Test status
Simulation time 23416034194 ps
CPU time 24.89 seconds
Started Jul 24 05:26:33 PM PDT 24
Finished Jul 24 05:26:58 PM PDT 24
Peak memory 206956 kb
Host smart-0f8aa6a1-1121-4d3c-8784-5bdd3601cc2c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1611594750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.1611594750
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.3987915454
Short name T2647
Test name
Test status
Simulation time 152444470 ps
CPU time 0.77 seconds
Started Jul 24 05:26:34 PM PDT 24
Finished Jul 24 05:26:35 PM PDT 24
Peak memory 206480 kb
Host smart-9b5b5247-f5bf-45c0-9e14-6af354d56e05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39879
15454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.3987915454
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.4199308196
Short name T802
Test name
Test status
Simulation time 145282523 ps
CPU time 0.76 seconds
Started Jul 24 05:26:48 PM PDT 24
Finished Jul 24 05:26:49 PM PDT 24
Peak memory 206528 kb
Host smart-111cbbb2-8a95-4ca3-a6dc-0db576e5b4b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41993
08196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.4199308196
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.3430243353
Short name T2007
Test name
Test status
Simulation time 200777421 ps
CPU time 0.83 seconds
Started Jul 24 05:26:43 PM PDT 24
Finished Jul 24 05:26:44 PM PDT 24
Peak memory 206520 kb
Host smart-f1f9f4a4-4ffb-437e-ac10-91d2e5a5869e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34302
43353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.3430243353
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.1934603152
Short name T646
Test name
Test status
Simulation time 783726655 ps
CPU time 1.9 seconds
Started Jul 24 05:26:56 PM PDT 24
Finished Jul 24 05:26:58 PM PDT 24
Peak memory 206716 kb
Host smart-ea9b20ac-67d3-4657-95a0-54e4facb5cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19346
03152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.1934603152
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.2032203656
Short name T1873
Test name
Test status
Simulation time 7490415646 ps
CPU time 13.06 seconds
Started Jul 24 05:26:53 PM PDT 24
Finished Jul 24 05:27:06 PM PDT 24
Peak memory 206888 kb
Host smart-582a17f6-8a18-427f-a2e4-60fb60224b36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20322
03656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.2032203656
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.2626906691
Short name T944
Test name
Test status
Simulation time 332961702 ps
CPU time 1.16 seconds
Started Jul 24 05:26:56 PM PDT 24
Finished Jul 24 05:26:57 PM PDT 24
Peak memory 206528 kb
Host smart-5440ccd3-4c1a-4307-b636-f4b3d0e93003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26269
06691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.2626906691
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.2610953842
Short name T2486
Test name
Test status
Simulation time 157949787 ps
CPU time 0.77 seconds
Started Jul 24 05:26:38 PM PDT 24
Finished Jul 24 05:26:38 PM PDT 24
Peak memory 206532 kb
Host smart-0928faa9-391d-431b-a600-269d0fc0ae4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26109
53842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.2610953842
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.575782359
Short name T1200
Test name
Test status
Simulation time 89099166 ps
CPU time 0.71 seconds
Started Jul 24 05:26:56 PM PDT 24
Finished Jul 24 05:26:57 PM PDT 24
Peak memory 206484 kb
Host smart-54c3da29-acf4-4a6b-9d22-97e893c3d0c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57578
2359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.575782359
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.1743155036
Short name T1199
Test name
Test status
Simulation time 837760999 ps
CPU time 1.85 seconds
Started Jul 24 05:26:31 PM PDT 24
Finished Jul 24 05:26:33 PM PDT 24
Peak memory 206832 kb
Host smart-25d0bed1-1755-4860-aa26-692195910a51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17431
55036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.1743155036
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.328847431
Short name T1539
Test name
Test status
Simulation time 237825244 ps
CPU time 1.62 seconds
Started Jul 24 05:27:02 PM PDT 24
Finished Jul 24 05:27:04 PM PDT 24
Peak memory 206796 kb
Host smart-85ae4712-851f-4a51-b6fc-a0765c555c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32884
7431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.328847431
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.4180585306
Short name T2286
Test name
Test status
Simulation time 178237224 ps
CPU time 0.77 seconds
Started Jul 24 05:26:58 PM PDT 24
Finished Jul 24 05:26:59 PM PDT 24
Peak memory 206608 kb
Host smart-275c7c66-6168-49d1-b2f4-7eace67fb612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41805
85306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.4180585306
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.3231740286
Short name T693
Test name
Test status
Simulation time 146540432 ps
CPU time 0.78 seconds
Started Jul 24 05:26:58 PM PDT 24
Finished Jul 24 05:26:59 PM PDT 24
Peak memory 206640 kb
Host smart-5c217f8f-9977-44da-a561-c4b0fdb73cef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32317
40286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.3231740286
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.2957757000
Short name T1006
Test name
Test status
Simulation time 261436720 ps
CPU time 0.99 seconds
Started Jul 24 05:26:46 PM PDT 24
Finished Jul 24 05:26:48 PM PDT 24
Peak memory 206564 kb
Host smart-1ee20c57-6ce5-4d39-a4fc-1748ebc4c8c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29577
57000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.2957757000
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.1583676371
Short name T1516
Test name
Test status
Simulation time 7009883264 ps
CPU time 48.06 seconds
Started Jul 24 05:26:51 PM PDT 24
Finished Jul 24 05:27:39 PM PDT 24
Peak memory 206924 kb
Host smart-b203fc61-e8af-491d-9e98-49308973b0bd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1583676371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.1583676371
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_iso_retraction.1884197585
Short name T2097
Test name
Test status
Simulation time 4689457863 ps
CPU time 14.59 seconds
Started Jul 24 05:26:45 PM PDT 24
Finished Jul 24 05:27:00 PM PDT 24
Peak memory 206872 kb
Host smart-57132cbb-52e7-428a-9ebe-8fc5b3afb179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18841
97585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.1884197585
Directory /workspace/22.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.2951098629
Short name T1642
Test name
Test status
Simulation time 184161112 ps
CPU time 0.83 seconds
Started Jul 24 05:26:53 PM PDT 24
Finished Jul 24 05:26:54 PM PDT 24
Peak memory 206592 kb
Host smart-4e1b442b-124c-496e-a7d2-c09888e51521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29510
98629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.2951098629
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.3542022816
Short name T992
Test name
Test status
Simulation time 23322564055 ps
CPU time 22.78 seconds
Started Jul 24 05:26:57 PM PDT 24
Finished Jul 24 05:27:20 PM PDT 24
Peak memory 206700 kb
Host smart-2ca6e26a-4f40-403c-befc-e58a53c874f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35420
22816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.3542022816
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.76450156
Short name T355
Test name
Test status
Simulation time 3310639406 ps
CPU time 3.74 seconds
Started Jul 24 05:26:59 PM PDT 24
Finished Jul 24 05:27:03 PM PDT 24
Peak memory 206696 kb
Host smart-9dccdcb5-24f6-4c06-9de3-784e0cfafa9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76450
156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.76450156
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.673631401
Short name T1355
Test name
Test status
Simulation time 11318205983 ps
CPU time 314.55 seconds
Started Jul 24 05:26:53 PM PDT 24
Finished Jul 24 05:32:08 PM PDT 24
Peak memory 206992 kb
Host smart-ac14be1e-8952-42e4-a8dd-3d46e01a731e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67363
1401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.673631401
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.1239986443
Short name T2542
Test name
Test status
Simulation time 3646856692 ps
CPU time 33.09 seconds
Started Jul 24 05:26:56 PM PDT 24
Finished Jul 24 05:27:30 PM PDT 24
Peak memory 206956 kb
Host smart-25116ef3-9a0c-46d7-94a8-3989f3daba65
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1239986443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.1239986443
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.483418025
Short name T2430
Test name
Test status
Simulation time 285361348 ps
CPU time 0.89 seconds
Started Jul 24 05:26:49 PM PDT 24
Finished Jul 24 05:26:50 PM PDT 24
Peak memory 206512 kb
Host smart-aeead3aa-b165-4845-bf23-5c4c0c7b0118
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=483418025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.483418025
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.4065097485
Short name T704
Test name
Test status
Simulation time 245685703 ps
CPU time 0.93 seconds
Started Jul 24 05:26:54 PM PDT 24
Finished Jul 24 05:26:56 PM PDT 24
Peak memory 206516 kb
Host smart-4353487d-9ca8-433e-b457-82ebe299823a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40650
97485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.4065097485
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.3603036984
Short name T1521
Test name
Test status
Simulation time 5695226710 ps
CPU time 157.25 seconds
Started Jul 24 05:27:02 PM PDT 24
Finished Jul 24 05:29:39 PM PDT 24
Peak memory 206936 kb
Host smart-43bc4a4d-3452-4121-b6c3-51355bc6e8a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36030
36984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.3603036984
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.1689072405
Short name T2525
Test name
Test status
Simulation time 5525086409 ps
CPU time 50.4 seconds
Started Jul 24 05:27:12 PM PDT 24
Finished Jul 24 05:28:02 PM PDT 24
Peak memory 206984 kb
Host smart-e8d658f1-9950-4bc6-92e7-07c3d5a8c422
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1689072405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.1689072405
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.2787818689
Short name T837
Test name
Test status
Simulation time 146442835 ps
CPU time 0.8 seconds
Started Jul 24 05:27:06 PM PDT 24
Finished Jul 24 05:27:07 PM PDT 24
Peak memory 206552 kb
Host smart-93a64f26-20dc-4699-a083-bdfc75a015e7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2787818689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.2787818689
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.2929204007
Short name T2424
Test name
Test status
Simulation time 209205476 ps
CPU time 0.85 seconds
Started Jul 24 05:26:50 PM PDT 24
Finished Jul 24 05:26:51 PM PDT 24
Peak memory 206576 kb
Host smart-ce5bb7db-be0b-4237-9b97-1a3be909c4b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29292
04007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.2929204007
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.373052015
Short name T97
Test name
Test status
Simulation time 172626159 ps
CPU time 0.87 seconds
Started Jul 24 05:26:51 PM PDT 24
Finished Jul 24 05:26:52 PM PDT 24
Peak memory 206576 kb
Host smart-b7a27ecc-1854-4761-9569-9e6bdf12b5b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37305
2015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.373052015
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.3981083628
Short name T1246
Test name
Test status
Simulation time 165475820 ps
CPU time 0.83 seconds
Started Jul 24 05:27:02 PM PDT 24
Finished Jul 24 05:27:03 PM PDT 24
Peak memory 206500 kb
Host smart-304d4b86-f677-432b-b232-d1b6335a0287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39810
83628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.3981083628
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.2714844276
Short name T890
Test name
Test status
Simulation time 207296700 ps
CPU time 0.88 seconds
Started Jul 24 05:27:01 PM PDT 24
Finished Jul 24 05:27:02 PM PDT 24
Peak memory 206584 kb
Host smart-66261db1-648d-47a8-aba8-fd48b89cd8cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27148
44276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.2714844276
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.1990723495
Short name T605
Test name
Test status
Simulation time 154367626 ps
CPU time 0.8 seconds
Started Jul 24 05:26:59 PM PDT 24
Finished Jul 24 05:27:00 PM PDT 24
Peak memory 206644 kb
Host smart-938a0f5a-022e-4400-8a96-708fba31d58d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19907
23495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.1990723495
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.3623283080
Short name T1336
Test name
Test status
Simulation time 158812741 ps
CPU time 0.75 seconds
Started Jul 24 05:26:55 PM PDT 24
Finished Jul 24 05:26:56 PM PDT 24
Peak memory 206596 kb
Host smart-b5c90f4b-38ed-49ee-8e60-adc7d28e3e02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36232
83080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.3623283080
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.887889976
Short name T1749
Test name
Test status
Simulation time 235218415 ps
CPU time 0.93 seconds
Started Jul 24 05:26:59 PM PDT 24
Finished Jul 24 05:27:01 PM PDT 24
Peak memory 206604 kb
Host smart-a7c2b899-0ca2-4394-a86f-8b8f58ad4a7d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=887889976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.887889976
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.2887826378
Short name T966
Test name
Test status
Simulation time 188392510 ps
CPU time 0.79 seconds
Started Jul 24 05:26:47 PM PDT 24
Finished Jul 24 05:26:48 PM PDT 24
Peak memory 206520 kb
Host smart-73edc044-e74e-419a-ac0d-99b9a7e1dd65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28878
26378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.2887826378
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.1924977931
Short name T1588
Test name
Test status
Simulation time 21279212980 ps
CPU time 50.89 seconds
Started Jul 24 05:26:54 PM PDT 24
Finished Jul 24 05:27:45 PM PDT 24
Peak memory 206952 kb
Host smart-efdefff8-e77d-4cff-a68c-7bfca7f18197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19249
77931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.1924977931
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.3671278729
Short name T2064
Test name
Test status
Simulation time 169767249 ps
CPU time 0.8 seconds
Started Jul 24 05:26:56 PM PDT 24
Finished Jul 24 05:26:57 PM PDT 24
Peak memory 206552 kb
Host smart-6ac12616-b32c-4841-a438-f5712434dd79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36712
78729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.3671278729
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.245670809
Short name T2558
Test name
Test status
Simulation time 238779077 ps
CPU time 0.85 seconds
Started Jul 24 05:26:55 PM PDT 24
Finished Jul 24 05:26:56 PM PDT 24
Peak memory 206580 kb
Host smart-2397b1d6-6a2d-4b33-8ddb-a85a760ed7f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24567
0809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.245670809
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.1609689653
Short name T1769
Test name
Test status
Simulation time 196312789 ps
CPU time 0.86 seconds
Started Jul 24 05:26:52 PM PDT 24
Finished Jul 24 05:26:53 PM PDT 24
Peak memory 206568 kb
Host smart-583c87d3-2568-41d8-8843-e768f77e237f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16096
89653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.1609689653
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.646202262
Short name T884
Test name
Test status
Simulation time 226766545 ps
CPU time 0.9 seconds
Started Jul 24 05:26:59 PM PDT 24
Finished Jul 24 05:27:00 PM PDT 24
Peak memory 206580 kb
Host smart-b258a9d2-547b-4df8-aefd-3aec8948e8a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64620
2262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.646202262
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.2749091511
Short name T2046
Test name
Test status
Simulation time 196459580 ps
CPU time 0.79 seconds
Started Jul 24 05:26:57 PM PDT 24
Finished Jul 24 05:26:58 PM PDT 24
Peak memory 206516 kb
Host smart-be220b16-ab20-475d-afb6-31220fa90a61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27490
91511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.2749091511
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.3722126184
Short name T2181
Test name
Test status
Simulation time 207189199 ps
CPU time 0.83 seconds
Started Jul 24 05:26:51 PM PDT 24
Finished Jul 24 05:26:52 PM PDT 24
Peak memory 206780 kb
Host smart-a69daa81-932c-46ad-916c-fd632fcee14c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37221
26184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.3722126184
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.2340312716
Short name T1913
Test name
Test status
Simulation time 167132185 ps
CPU time 0.81 seconds
Started Jul 24 05:26:51 PM PDT 24
Finished Jul 24 05:26:52 PM PDT 24
Peak memory 206560 kb
Host smart-cf237576-17c9-4856-96e2-7ec2be5d36ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23403
12716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.2340312716
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.3969109813
Short name T317
Test name
Test status
Simulation time 238611969 ps
CPU time 0.92 seconds
Started Jul 24 05:26:59 PM PDT 24
Finished Jul 24 05:27:00 PM PDT 24
Peak memory 206580 kb
Host smart-d4e910e8-28d9-4ad8-a1e3-6cc2ce2db7f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39691
09813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.3969109813
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.2797957194
Short name T79
Test name
Test status
Simulation time 3830470363 ps
CPU time 105.15 seconds
Started Jul 24 05:26:52 PM PDT 24
Finished Jul 24 05:28:38 PM PDT 24
Peak memory 206964 kb
Host smart-aac2e987-dce3-40ba-8a95-5874fc91a773
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2797957194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.2797957194
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.3245474304
Short name T356
Test name
Test status
Simulation time 238020604 ps
CPU time 0.84 seconds
Started Jul 24 05:26:43 PM PDT 24
Finished Jul 24 05:26:44 PM PDT 24
Peak memory 206600 kb
Host smart-b66ef37a-a4ec-426c-810b-f3596356b7ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32454
74304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.3245474304
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.1368170701
Short name T2478
Test name
Test status
Simulation time 194365311 ps
CPU time 0.81 seconds
Started Jul 24 05:26:56 PM PDT 24
Finished Jul 24 05:26:57 PM PDT 24
Peak memory 206584 kb
Host smart-903b276f-24c9-4f58-a6b6-971eb7ef3c06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13681
70701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.1368170701
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.1320142838
Short name T1382
Test name
Test status
Simulation time 630821605 ps
CPU time 1.71 seconds
Started Jul 24 05:26:52 PM PDT 24
Finished Jul 24 05:26:54 PM PDT 24
Peak memory 206592 kb
Host smart-ddf67230-a074-4fc9-8da9-f13700898084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13201
42838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.1320142838
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.1165632470
Short name T1302
Test name
Test status
Simulation time 3966187081 ps
CPU time 104.21 seconds
Started Jul 24 05:26:51 PM PDT 24
Finished Jul 24 05:28:35 PM PDT 24
Peak memory 206884 kb
Host smart-f5d8c868-a74b-428b-82b9-3d94c5ac52cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11656
32470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.1165632470
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.3335288129
Short name T1016
Test name
Test status
Simulation time 34149470 ps
CPU time 0.64 seconds
Started Jul 24 05:26:51 PM PDT 24
Finished Jul 24 05:26:52 PM PDT 24
Peak memory 206596 kb
Host smart-4700e36a-fb02-440a-8341-4ec40203b374
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3335288129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.3335288129
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.3487116420
Short name T2052
Test name
Test status
Simulation time 4101119197 ps
CPU time 4.62 seconds
Started Jul 24 05:27:04 PM PDT 24
Finished Jul 24 05:27:09 PM PDT 24
Peak memory 206692 kb
Host smart-5b972be4-dfaa-42a0-b966-69efc44b0031
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3487116420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.3487116420
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.2290317615
Short name T1305
Test name
Test status
Simulation time 13324077520 ps
CPU time 15.1 seconds
Started Jul 24 05:26:53 PM PDT 24
Finished Jul 24 05:27:08 PM PDT 24
Peak memory 206716 kb
Host smart-a612d6a7-0502-4704-9fef-1c89710e3280
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2290317615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.2290317615
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.2386064440
Short name T1628
Test name
Test status
Simulation time 23328698989 ps
CPU time 22.51 seconds
Started Jul 24 05:27:01 PM PDT 24
Finished Jul 24 05:27:24 PM PDT 24
Peak memory 206768 kb
Host smart-3556ff3c-68a8-4066-beb9-94bca91ffc78
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2386064440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.2386064440
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.2233371328
Short name T1255
Test name
Test status
Simulation time 155044802 ps
CPU time 0.83 seconds
Started Jul 24 05:27:01 PM PDT 24
Finished Jul 24 05:27:02 PM PDT 24
Peak memory 206596 kb
Host smart-29eb4316-3dea-4721-8d0e-86eab507c8eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22333
71328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.2233371328
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.1496491742
Short name T771
Test name
Test status
Simulation time 170855407 ps
CPU time 0.77 seconds
Started Jul 24 05:26:51 PM PDT 24
Finished Jul 24 05:26:51 PM PDT 24
Peak memory 206576 kb
Host smart-ad9fae66-728f-4c0c-9907-794b7a050578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14964
91742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.1496491742
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.357239734
Short name T73
Test name
Test status
Simulation time 222138404 ps
CPU time 0.94 seconds
Started Jul 24 05:27:09 PM PDT 24
Finished Jul 24 05:27:10 PM PDT 24
Peak memory 206608 kb
Host smart-c2a54418-255a-496e-8adb-7b3c13c3df2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35723
9734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.357239734
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.3337029979
Short name T919
Test name
Test status
Simulation time 1280930658 ps
CPU time 2.89 seconds
Started Jul 24 05:26:55 PM PDT 24
Finished Jul 24 05:26:58 PM PDT 24
Peak memory 207028 kb
Host smart-aa7863d7-3b23-434f-9e4d-1e784ef18e65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33370
29979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.3337029979
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.2304864291
Short name T2503
Test name
Test status
Simulation time 20666588177 ps
CPU time 38 seconds
Started Jul 24 05:26:55 PM PDT 24
Finished Jul 24 05:27:38 PM PDT 24
Peak memory 206840 kb
Host smart-50c262f6-0ae8-4f5c-ac78-b941c9402cea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23048
64291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.2304864291
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.3433241134
Short name T1069
Test name
Test status
Simulation time 506108115 ps
CPU time 1.39 seconds
Started Jul 24 05:27:04 PM PDT 24
Finished Jul 24 05:27:05 PM PDT 24
Peak memory 206612 kb
Host smart-d6809496-1d8c-40f3-9c87-8d72cfc0c7c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34332
41134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.3433241134
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.2809787642
Short name T2749
Test name
Test status
Simulation time 158882150 ps
CPU time 0.76 seconds
Started Jul 24 05:27:03 PM PDT 24
Finished Jul 24 05:27:04 PM PDT 24
Peak memory 206564 kb
Host smart-d3f6c0e8-e342-4eb4-9344-dc9278635ec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28097
87642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.2809787642
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.3140989074
Short name T1561
Test name
Test status
Simulation time 30908419 ps
CPU time 0.66 seconds
Started Jul 24 05:26:57 PM PDT 24
Finished Jul 24 05:26:58 PM PDT 24
Peak memory 206596 kb
Host smart-38f5b00a-0c0b-4480-9a98-b53aec3457e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31409
89074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.3140989074
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.3882500235
Short name T2369
Test name
Test status
Simulation time 1009119308 ps
CPU time 2.46 seconds
Started Jul 24 05:26:59 PM PDT 24
Finished Jul 24 05:27:02 PM PDT 24
Peak memory 206812 kb
Host smart-9bdcc552-af26-4006-831e-da3bd24eba8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38825
00235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.3882500235
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.1353565029
Short name T1509
Test name
Test status
Simulation time 221790750 ps
CPU time 1.5 seconds
Started Jul 24 05:26:58 PM PDT 24
Finished Jul 24 05:27:00 PM PDT 24
Peak memory 206700 kb
Host smart-dca85807-0fca-4893-bb7b-74d4794b888a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13535
65029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.1353565029
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.467736090
Short name T1974
Test name
Test status
Simulation time 172797754 ps
CPU time 0.79 seconds
Started Jul 24 05:27:02 PM PDT 24
Finished Jul 24 05:27:03 PM PDT 24
Peak memory 206512 kb
Host smart-6d3e5dbb-3fa3-4b26-ba1b-dbfc81db9ce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46773
6090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.467736090
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.528544550
Short name T1986
Test name
Test status
Simulation time 142241224 ps
CPU time 0.78 seconds
Started Jul 24 05:26:52 PM PDT 24
Finished Jul 24 05:26:53 PM PDT 24
Peak memory 206576 kb
Host smart-215e4125-be59-458e-aee4-102be100890d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52854
4550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.528544550
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.680065580
Short name T903
Test name
Test status
Simulation time 246916007 ps
CPU time 0.93 seconds
Started Jul 24 05:26:54 PM PDT 24
Finished Jul 24 05:26:56 PM PDT 24
Peak memory 206564 kb
Host smart-8c34425a-04ad-4762-8296-755a74dd9dab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68006
5580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.680065580
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.2361752422
Short name T1022
Test name
Test status
Simulation time 10090278681 ps
CPU time 70 seconds
Started Jul 24 05:27:12 PM PDT 24
Finished Jul 24 05:28:23 PM PDT 24
Peak memory 206916 kb
Host smart-e6c4a365-8631-4447-bf43-3648bcbbe15d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2361752422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.2361752422
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_iso_retraction.1585658840
Short name T81
Test name
Test status
Simulation time 12187478159 ps
CPU time 38.84 seconds
Started Jul 24 05:26:57 PM PDT 24
Finished Jul 24 05:27:36 PM PDT 24
Peak memory 206760 kb
Host smart-8624fe56-6380-4da5-8a9e-5de8d42d0d97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15856
58840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_iso_retraction.1585658840
Directory /workspace/23.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.3484838852
Short name T2073
Test name
Test status
Simulation time 166125701 ps
CPU time 0.78 seconds
Started Jul 24 05:26:58 PM PDT 24
Finished Jul 24 05:26:59 PM PDT 24
Peak memory 206604 kb
Host smart-2c3db8a8-fdaf-4031-a748-7ac43f56dd44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34848
38852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.3484838852
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.2343251569
Short name T1615
Test name
Test status
Simulation time 23288653334 ps
CPU time 22.12 seconds
Started Jul 24 05:27:04 PM PDT 24
Finished Jul 24 05:27:26 PM PDT 24
Peak memory 206592 kb
Host smart-5ad2c48b-95d9-4d28-ae3a-4bbb268941ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23432
51569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.2343251569
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.3658829229
Short name T691
Test name
Test status
Simulation time 3380913870 ps
CPU time 3.77 seconds
Started Jul 24 05:26:53 PM PDT 24
Finished Jul 24 05:26:57 PM PDT 24
Peak memory 206756 kb
Host smart-32dbf5da-626e-4332-b196-812171592635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36588
29229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.3658829229
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.3222916791
Short name T795
Test name
Test status
Simulation time 9602750859 ps
CPU time 93.86 seconds
Started Jul 24 05:27:00 PM PDT 24
Finished Jul 24 05:28:35 PM PDT 24
Peak memory 206960 kb
Host smart-a0c8623c-0df9-4410-8808-5c51500ed975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32229
16791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.3222916791
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.4107489020
Short name T2297
Test name
Test status
Simulation time 4700409218 ps
CPU time 39.29 seconds
Started Jul 24 05:27:01 PM PDT 24
Finished Jul 24 05:27:40 PM PDT 24
Peak memory 206836 kb
Host smart-4f9c1b8f-21f5-4ef6-a1ee-75b435e56a46
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4107489020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.4107489020
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.3279372079
Short name T1174
Test name
Test status
Simulation time 295522893 ps
CPU time 0.94 seconds
Started Jul 24 05:27:14 PM PDT 24
Finished Jul 24 05:27:15 PM PDT 24
Peak memory 206452 kb
Host smart-3890b4ee-cd20-45ce-b2e0-380f6e432f5c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3279372079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.3279372079
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.3158230879
Short name T581
Test name
Test status
Simulation time 189779878 ps
CPU time 0.9 seconds
Started Jul 24 05:26:53 PM PDT 24
Finished Jul 24 05:26:54 PM PDT 24
Peak memory 206388 kb
Host smart-9db2e717-95bf-4430-a73f-1e113a3ea6c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31582
30879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.3158230879
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.25624325
Short name T1075
Test name
Test status
Simulation time 3850110394 ps
CPU time 103.31 seconds
Started Jul 24 05:26:57 PM PDT 24
Finished Jul 24 05:28:41 PM PDT 24
Peak memory 206768 kb
Host smart-9dfe0fd7-94bd-48aa-89b3-43229d686709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25624
325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.25624325
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.3986054018
Short name T1480
Test name
Test status
Simulation time 6891964648 ps
CPU time 189.03 seconds
Started Jul 24 05:26:57 PM PDT 24
Finished Jul 24 05:30:06 PM PDT 24
Peak memory 206924 kb
Host smart-8e2c9691-9e8c-499a-b376-e4553e545857
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3986054018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.3986054018
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.2034227000
Short name T2339
Test name
Test status
Simulation time 192286491 ps
CPU time 0.81 seconds
Started Jul 24 05:26:57 PM PDT 24
Finished Jul 24 05:26:58 PM PDT 24
Peak memory 206576 kb
Host smart-1cde1622-14be-4c89-b900-daf8fa2f009d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2034227000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.2034227000
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.89647207
Short name T863
Test name
Test status
Simulation time 153544041 ps
CPU time 0.77 seconds
Started Jul 24 05:26:59 PM PDT 24
Finished Jul 24 05:27:00 PM PDT 24
Peak memory 206476 kb
Host smart-fd043b1e-4911-4190-9e0b-b2b055cb2bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89647
207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.89647207
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.1697333738
Short name T1404
Test name
Test status
Simulation time 198628734 ps
CPU time 0.84 seconds
Started Jul 24 05:27:05 PM PDT 24
Finished Jul 24 05:27:06 PM PDT 24
Peak memory 206388 kb
Host smart-971d2268-b18a-4a50-b001-7cc9dbf6d949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16973
33738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.1697333738
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.2334604537
Short name T1109
Test name
Test status
Simulation time 183823690 ps
CPU time 0.78 seconds
Started Jul 24 05:26:59 PM PDT 24
Finished Jul 24 05:27:00 PM PDT 24
Peak memory 206592 kb
Host smart-7ecc6af2-772f-46ca-818e-8715e76561b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23346
04537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.2334604537
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.4274164260
Short name T2588
Test name
Test status
Simulation time 170602545 ps
CPU time 0.78 seconds
Started Jul 24 05:27:03 PM PDT 24
Finished Jul 24 05:27:04 PM PDT 24
Peak memory 206548 kb
Host smart-64f4b4c4-94a5-4ca5-87f2-f0da5e94a812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42741
64260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.4274164260
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.839035949
Short name T1010
Test name
Test status
Simulation time 153704665 ps
CPU time 0.84 seconds
Started Jul 24 05:27:19 PM PDT 24
Finished Jul 24 05:27:20 PM PDT 24
Peak memory 206448 kb
Host smart-b5a5785a-7885-4c36-9125-1a050d4514c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83903
5949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.839035949
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.151665403
Short name T1118
Test name
Test status
Simulation time 219854713 ps
CPU time 0.9 seconds
Started Jul 24 05:26:59 PM PDT 24
Finished Jul 24 05:27:00 PM PDT 24
Peak memory 206556 kb
Host smart-d241e548-9ace-42ac-873f-64526a2f78c4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=151665403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.151665403
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.1269280185
Short name T2500
Test name
Test status
Simulation time 142986913 ps
CPU time 0.72 seconds
Started Jul 24 05:26:58 PM PDT 24
Finished Jul 24 05:26:59 PM PDT 24
Peak memory 206640 kb
Host smart-0c70c70c-d6de-498d-9277-601f73c9f587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12692
80185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.1269280185
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2555456468
Short name T1567
Test name
Test status
Simulation time 45677331 ps
CPU time 0.64 seconds
Started Jul 24 05:26:53 PM PDT 24
Finished Jul 24 05:26:54 PM PDT 24
Peak memory 206524 kb
Host smart-8186e5cd-88b8-4e4d-a114-f2ffb0d780cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25554
56468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2555456468
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.711482490
Short name T2625
Test name
Test status
Simulation time 14479412153 ps
CPU time 34.86 seconds
Started Jul 24 05:26:58 PM PDT 24
Finished Jul 24 05:27:33 PM PDT 24
Peak memory 206916 kb
Host smart-fd3ac19f-b523-4605-8556-e8566153f63f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71148
2490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.711482490
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.1649230027
Short name T1098
Test name
Test status
Simulation time 150689768 ps
CPU time 0.78 seconds
Started Jul 24 05:26:59 PM PDT 24
Finished Jul 24 05:27:00 PM PDT 24
Peak memory 206464 kb
Host smart-69aa8588-c772-4eb4-a412-c29185fbd392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16492
30027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.1649230027
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.3335677920
Short name T1146
Test name
Test status
Simulation time 280614838 ps
CPU time 0.99 seconds
Started Jul 24 05:27:02 PM PDT 24
Finished Jul 24 05:27:03 PM PDT 24
Peak memory 206628 kb
Host smart-5af5db2b-cdc8-48ae-9725-9fc346cab648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33356
77920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.3335677920
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.2204058683
Short name T382
Test name
Test status
Simulation time 211665741 ps
CPU time 0.86 seconds
Started Jul 24 05:27:11 PM PDT 24
Finished Jul 24 05:27:12 PM PDT 24
Peak memory 206504 kb
Host smart-1d62f76b-f4e9-435c-b054-a45aef96e10e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22040
58683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.2204058683
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.3721440510
Short name T1897
Test name
Test status
Simulation time 202213716 ps
CPU time 0.9 seconds
Started Jul 24 05:27:00 PM PDT 24
Finished Jul 24 05:27:02 PM PDT 24
Peak memory 206564 kb
Host smart-2480b857-544b-4694-85b5-801a14418e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37214
40510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.3721440510
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.2251846818
Short name T1402
Test name
Test status
Simulation time 222416867 ps
CPU time 0.83 seconds
Started Jul 24 05:27:03 PM PDT 24
Finished Jul 24 05:27:04 PM PDT 24
Peak memory 206660 kb
Host smart-c3a21c17-2346-4e55-93da-47cde835c79a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22518
46818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.2251846818
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.2810994604
Short name T2110
Test name
Test status
Simulation time 151259461 ps
CPU time 0.78 seconds
Started Jul 24 05:26:57 PM PDT 24
Finished Jul 24 05:26:58 PM PDT 24
Peak memory 206560 kb
Host smart-e7151e23-9704-46ee-84cf-6abc833e88b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28109
94604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.2810994604
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.1673308663
Short name T1884
Test name
Test status
Simulation time 175360490 ps
CPU time 0.74 seconds
Started Jul 24 05:26:58 PM PDT 24
Finished Jul 24 05:26:59 PM PDT 24
Peak memory 206560 kb
Host smart-ee07b823-d5b6-4580-aa17-81800e59fd6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16733
08663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.1673308663
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.145402432
Short name T1751
Test name
Test status
Simulation time 220486060 ps
CPU time 0.94 seconds
Started Jul 24 05:26:58 PM PDT 24
Finished Jul 24 05:26:59 PM PDT 24
Peak memory 206592 kb
Host smart-f53c6f56-ed9c-47ba-a5f9-1c8cfdc74da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14540
2432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.145402432
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.1450670882
Short name T1866
Test name
Test status
Simulation time 5232399633 ps
CPU time 141.42 seconds
Started Jul 24 05:26:54 PM PDT 24
Finished Jul 24 05:29:16 PM PDT 24
Peak memory 207024 kb
Host smart-4daaae9c-78a4-4dc3-bd4e-ab4904de17ee
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1450670882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.1450670882
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.2316622530
Short name T466
Test name
Test status
Simulation time 182281109 ps
CPU time 0.81 seconds
Started Jul 24 05:27:06 PM PDT 24
Finished Jul 24 05:27:07 PM PDT 24
Peak memory 206600 kb
Host smart-47ea4901-deea-497b-863a-afca00fe603b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23166
22530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.2316622530
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.2887960654
Short name T1977
Test name
Test status
Simulation time 184165567 ps
CPU time 0.77 seconds
Started Jul 24 05:26:58 PM PDT 24
Finished Jul 24 05:26:59 PM PDT 24
Peak memory 206488 kb
Host smart-766adbce-a45c-4a1b-a309-d5be0b021c6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28879
60654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.2887960654
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.1027790196
Short name T1338
Test name
Test status
Simulation time 1086867113 ps
CPU time 2.29 seconds
Started Jul 24 05:27:02 PM PDT 24
Finished Jul 24 05:27:05 PM PDT 24
Peak memory 206840 kb
Host smart-ef083491-622a-475d-9d0c-7fc08b8325a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10277
90196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.1027790196
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.2742265503
Short name T928
Test name
Test status
Simulation time 3951187862 ps
CPU time 28.31 seconds
Started Jul 24 05:27:01 PM PDT 24
Finished Jul 24 05:27:30 PM PDT 24
Peak memory 206824 kb
Host smart-c147e480-5e15-4d8e-8240-ca2a0b55eee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27422
65503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.2742265503
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.3251067087
Short name T654
Test name
Test status
Simulation time 80765047 ps
CPU time 0.69 seconds
Started Jul 24 05:27:18 PM PDT 24
Finished Jul 24 05:27:19 PM PDT 24
Peak memory 206584 kb
Host smart-5d1e22f6-da22-4a44-ab5c-2ecd23f8726e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3251067087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.3251067087
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.1754380581
Short name T726
Test name
Test status
Simulation time 4105079018 ps
CPU time 5.12 seconds
Started Jul 24 05:27:02 PM PDT 24
Finished Jul 24 05:27:07 PM PDT 24
Peak memory 206968 kb
Host smart-ab5554e6-4d3c-436c-8f96-c7962985a5e5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1754380581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.1754380581
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.1867225477
Short name T715
Test name
Test status
Simulation time 13447400868 ps
CPU time 14.25 seconds
Started Jul 24 05:26:59 PM PDT 24
Finished Jul 24 05:27:14 PM PDT 24
Peak memory 206964 kb
Host smart-f5d8cbe6-524c-4fa0-afc5-c5d0af5f3948
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1867225477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.1867225477
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.1064865674
Short name T2270
Test name
Test status
Simulation time 23372266153 ps
CPU time 24.4 seconds
Started Jul 24 05:27:10 PM PDT 24
Finished Jul 24 05:27:35 PM PDT 24
Peak memory 206724 kb
Host smart-13bf2ca2-2625-4d7b-81d2-32b3a096db35
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1064865674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.1064865674
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.1686158546
Short name T2495
Test name
Test status
Simulation time 182607937 ps
CPU time 0.8 seconds
Started Jul 24 05:26:59 PM PDT 24
Finished Jul 24 05:27:00 PM PDT 24
Peak memory 206600 kb
Host smart-0e00b124-9ffa-44d0-8428-4cbb2f598f64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16861
58546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.1686158546
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.2373138471
Short name T1794
Test name
Test status
Simulation time 145385378 ps
CPU time 0.79 seconds
Started Jul 24 05:27:00 PM PDT 24
Finished Jul 24 05:27:01 PM PDT 24
Peak memory 206528 kb
Host smart-9ad8ac58-0d5d-416b-a537-870232e4982e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23731
38471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.2373138471
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.3867637454
Short name T2335
Test name
Test status
Simulation time 397114172 ps
CPU time 1.31 seconds
Started Jul 24 05:27:12 PM PDT 24
Finished Jul 24 05:27:13 PM PDT 24
Peak memory 206572 kb
Host smart-e6a56463-186a-4d43-952e-5292dfccef3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38676
37454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.3867637454
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.443450110
Short name T661
Test name
Test status
Simulation time 1345405659 ps
CPU time 2.99 seconds
Started Jul 24 05:26:59 PM PDT 24
Finished Jul 24 05:27:02 PM PDT 24
Peak memory 206732 kb
Host smart-a5059db7-2b0e-46f7-9651-5891a3a6c52c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44345
0110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.443450110
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.2244569137
Short name T1763
Test name
Test status
Simulation time 8380869567 ps
CPU time 15.19 seconds
Started Jul 24 05:27:03 PM PDT 24
Finished Jul 24 05:27:18 PM PDT 24
Peak memory 206856 kb
Host smart-6db7af1d-970d-45f3-b92b-bc88bc863f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22445
69137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.2244569137
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_device_timeout.1700006590
Short name T2107
Test name
Test status
Simulation time 186752758 ps
CPU time 0.86 seconds
Started Jul 24 05:26:53 PM PDT 24
Finished Jul 24 05:26:54 PM PDT 24
Peak memory 206780 kb
Host smart-6833c507-a2ac-47f4-8cf9-4dca5af6f4b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17000
06590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_timeout.1700006590
Directory /workspace/24.usbdev_device_timeout/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.3360213088
Short name T1809
Test name
Test status
Simulation time 490372723 ps
CPU time 1.45 seconds
Started Jul 24 05:27:08 PM PDT 24
Finished Jul 24 05:27:09 PM PDT 24
Peak memory 206596 kb
Host smart-5fd51f00-4b0b-4ecf-9771-fcf448f98482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33602
13088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.3360213088
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.448934753
Short name T1953
Test name
Test status
Simulation time 138330701 ps
CPU time 0.72 seconds
Started Jul 24 05:27:03 PM PDT 24
Finished Jul 24 05:27:03 PM PDT 24
Peak memory 206568 kb
Host smart-f2816841-b4d9-4786-8efd-40d05ebfeecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44893
4753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.448934753
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.663892378
Short name T973
Test name
Test status
Simulation time 105714912 ps
CPU time 0.7 seconds
Started Jul 24 05:27:12 PM PDT 24
Finished Jul 24 05:27:13 PM PDT 24
Peak memory 206544 kb
Host smart-e1e27a6f-0482-4e3d-928a-21f483c58ccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66389
2378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.663892378
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.4137809292
Short name T2003
Test name
Test status
Simulation time 774194315 ps
CPU time 2.11 seconds
Started Jul 24 05:27:10 PM PDT 24
Finished Jul 24 05:27:12 PM PDT 24
Peak memory 206840 kb
Host smart-e3bb1752-a16a-4d12-b2b9-bc1c2761fbbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41378
09292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.4137809292
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.2047464762
Short name T2329
Test name
Test status
Simulation time 250926548 ps
CPU time 1.77 seconds
Started Jul 24 05:26:54 PM PDT 24
Finished Jul 24 05:26:56 PM PDT 24
Peak memory 206996 kb
Host smart-2f9c880b-a633-464a-adcc-0c24cb4d7fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20474
64762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.2047464762
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.60662707
Short name T620
Test name
Test status
Simulation time 237687796 ps
CPU time 0.87 seconds
Started Jul 24 05:26:58 PM PDT 24
Finished Jul 24 05:27:00 PM PDT 24
Peak memory 206556 kb
Host smart-def5c303-fa93-4a6c-bbcb-1b9ca84a9faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60662
707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.60662707
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.2840597301
Short name T2435
Test name
Test status
Simulation time 136321986 ps
CPU time 0.8 seconds
Started Jul 24 05:27:02 PM PDT 24
Finished Jul 24 05:27:03 PM PDT 24
Peak memory 206544 kb
Host smart-3f5f5214-c41c-457d-a3b3-e96d46369c12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28405
97301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.2840597301
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.3616696152
Short name T322
Test name
Test status
Simulation time 190733295 ps
CPU time 0.88 seconds
Started Jul 24 05:26:59 PM PDT 24
Finished Jul 24 05:27:00 PM PDT 24
Peak memory 206552 kb
Host smart-d52b5048-56f7-4f75-9b53-69fee0a7cc9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36166
96152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.3616696152
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.3159683052
Short name T1679
Test name
Test status
Simulation time 5025014424 ps
CPU time 136.16 seconds
Started Jul 24 05:27:06 PM PDT 24
Finished Jul 24 05:29:22 PM PDT 24
Peak memory 206964 kb
Host smart-536a5d49-407a-486e-bcad-f3a2a5894a11
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3159683052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.3159683052
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_iso_retraction.489366222
Short name T717
Test name
Test status
Simulation time 7989147148 ps
CPU time 29.01 seconds
Started Jul 24 05:27:12 PM PDT 24
Finished Jul 24 05:27:42 PM PDT 24
Peak memory 206748 kb
Host smart-867e313f-5b27-4272-921b-dd57d4e0310d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48936
6222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_iso_retraction.489366222
Directory /workspace/24.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.715892095
Short name T358
Test name
Test status
Simulation time 211402008 ps
CPU time 0.87 seconds
Started Jul 24 05:27:04 PM PDT 24
Finished Jul 24 05:27:05 PM PDT 24
Peak memory 206532 kb
Host smart-79fb4e56-3bf6-4470-aabb-b40d17ce8f5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71589
2095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.715892095
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.295065261
Short name T1460
Test name
Test status
Simulation time 23345042301 ps
CPU time 20.83 seconds
Started Jul 24 05:27:07 PM PDT 24
Finished Jul 24 05:27:28 PM PDT 24
Peak memory 206704 kb
Host smart-dfa55817-b5e4-4da3-b323-171cb3698731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29506
5261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.295065261
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.1510498296
Short name T1933
Test name
Test status
Simulation time 3344007481 ps
CPU time 3.96 seconds
Started Jul 24 05:26:56 PM PDT 24
Finished Jul 24 05:27:00 PM PDT 24
Peak memory 206708 kb
Host smart-d3f021aa-2926-49ee-85ef-abc23f33dd31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15104
98296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.1510498296
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.2166966830
Short name T1140
Test name
Test status
Simulation time 8647972357 ps
CPU time 82.62 seconds
Started Jul 24 05:27:10 PM PDT 24
Finished Jul 24 05:28:33 PM PDT 24
Peak memory 206952 kb
Host smart-ad7cda52-b133-42f8-97a1-c2387763370f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21669
66830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.2166966830
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.2859466481
Short name T1967
Test name
Test status
Simulation time 7248867579 ps
CPU time 201.76 seconds
Started Jul 24 05:27:05 PM PDT 24
Finished Jul 24 05:30:27 PM PDT 24
Peak memory 206908 kb
Host smart-ee8a5bdb-f38f-41e7-9c70-3f4abf69e9cc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2859466481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.2859466481
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.985252203
Short name T882
Test name
Test status
Simulation time 241875301 ps
CPU time 0.85 seconds
Started Jul 24 05:26:57 PM PDT 24
Finished Jul 24 05:26:58 PM PDT 24
Peak memory 206604 kb
Host smart-1b53c89f-fd22-466c-b666-7fa2a3961498
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=985252203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.985252203
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.810275870
Short name T2476
Test name
Test status
Simulation time 254764387 ps
CPU time 0.9 seconds
Started Jul 24 05:26:58 PM PDT 24
Finished Jul 24 05:26:59 PM PDT 24
Peak memory 206644 kb
Host smart-41004dff-cb80-48ed-baea-75a7d4005b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81027
5870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.810275870
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.2146402164
Short name T709
Test name
Test status
Simulation time 5779006209 ps
CPU time 39.08 seconds
Started Jul 24 05:26:58 PM PDT 24
Finished Jul 24 05:27:37 PM PDT 24
Peak memory 206936 kb
Host smart-030df009-cf6f-409b-90a2-b9ba9e55e4c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21464
02164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.2146402164
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.1019355273
Short name T142
Test name
Test status
Simulation time 3539218529 ps
CPU time 32.68 seconds
Started Jul 24 05:27:12 PM PDT 24
Finished Jul 24 05:27:45 PM PDT 24
Peak memory 206888 kb
Host smart-2fb1c652-dc13-42ca-96f6-9527fe32e502
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1019355273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.1019355273
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.1730383219
Short name T1269
Test name
Test status
Simulation time 157204670 ps
CPU time 0.8 seconds
Started Jul 24 05:27:00 PM PDT 24
Finished Jul 24 05:27:01 PM PDT 24
Peak memory 206552 kb
Host smart-b8773861-8c71-4e51-90af-9878d3adf7e1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1730383219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.1730383219
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.2768530639
Short name T705
Test name
Test status
Simulation time 142947818 ps
CPU time 0.79 seconds
Started Jul 24 05:27:14 PM PDT 24
Finished Jul 24 05:27:15 PM PDT 24
Peak memory 206600 kb
Host smart-a0fd3c35-c730-436a-a92e-dc8963b2f022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27685
30639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.2768530639
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.874221191
Short name T2489
Test name
Test status
Simulation time 199811445 ps
CPU time 0.88 seconds
Started Jul 24 05:27:07 PM PDT 24
Finished Jul 24 05:27:08 PM PDT 24
Peak memory 206780 kb
Host smart-50a6a836-a241-45ab-8484-48f01078e525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87422
1191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.874221191
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.2780868265
Short name T512
Test name
Test status
Simulation time 207311369 ps
CPU time 0.89 seconds
Started Jul 24 05:27:03 PM PDT 24
Finished Jul 24 05:27:04 PM PDT 24
Peak memory 206532 kb
Host smart-5b3f9303-6178-441d-ac79-417455ad30ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27808
68265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.2780868265
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.2085578483
Short name T1748
Test name
Test status
Simulation time 212753485 ps
CPU time 0.83 seconds
Started Jul 24 05:27:06 PM PDT 24
Finished Jul 24 05:27:07 PM PDT 24
Peak memory 206584 kb
Host smart-156bae72-d758-4b39-89b0-c2a5fe161719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20855
78483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.2085578483
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.2842680146
Short name T2147
Test name
Test status
Simulation time 180728361 ps
CPU time 0.82 seconds
Started Jul 24 05:27:18 PM PDT 24
Finished Jul 24 05:27:19 PM PDT 24
Peak memory 206600 kb
Host smart-4b5488dc-71bf-402b-98b2-78ed8b45cc28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28426
80146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.2842680146
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.3911059610
Short name T164
Test name
Test status
Simulation time 183159667 ps
CPU time 0.79 seconds
Started Jul 24 05:27:03 PM PDT 24
Finished Jul 24 05:27:04 PM PDT 24
Peak memory 206632 kb
Host smart-b2abdccc-a677-4c8e-beb8-5e8a25091c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39110
59610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.3911059610
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.1499851333
Short name T1489
Test name
Test status
Simulation time 219889039 ps
CPU time 0.89 seconds
Started Jul 24 05:27:17 PM PDT 24
Finished Jul 24 05:27:18 PM PDT 24
Peak memory 206576 kb
Host smart-968a060b-fc54-4a9c-a83f-ce05b7ebb735
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1499851333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.1499851333
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.2746523847
Short name T818
Test name
Test status
Simulation time 178683944 ps
CPU time 0.78 seconds
Started Jul 24 05:27:05 PM PDT 24
Finished Jul 24 05:27:06 PM PDT 24
Peak memory 206548 kb
Host smart-c8a5a566-ba2f-46ee-87dd-de6160524bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27465
23847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.2746523847
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.3161171390
Short name T1472
Test name
Test status
Simulation time 62725540 ps
CPU time 0.66 seconds
Started Jul 24 05:27:09 PM PDT 24
Finished Jul 24 05:27:10 PM PDT 24
Peak memory 206544 kb
Host smart-359ab60a-3311-4b48-8bf5-ae53bb1894b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31611
71390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.3161171390
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.2433443231
Short name T1690
Test name
Test status
Simulation time 21222202378 ps
CPU time 44.3 seconds
Started Jul 24 05:27:05 PM PDT 24
Finished Jul 24 05:27:50 PM PDT 24
Peak memory 215196 kb
Host smart-69fe01ea-c03b-48a6-b752-719f6c16356f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24334
43231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.2433443231
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.422197910
Short name T582
Test name
Test status
Simulation time 159398034 ps
CPU time 0.81 seconds
Started Jul 24 05:27:10 PM PDT 24
Finished Jul 24 05:27:11 PM PDT 24
Peak memory 206584 kb
Host smart-dfb1610c-285c-44a1-b8f3-f636c421cf3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42219
7910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.422197910
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.1117662477
Short name T2289
Test name
Test status
Simulation time 165276473 ps
CPU time 0.81 seconds
Started Jul 24 05:27:09 PM PDT 24
Finished Jul 24 05:27:10 PM PDT 24
Peak memory 206648 kb
Host smart-a8c3699e-9d2f-4ffc-8b83-064b86c09339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11176
62477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.1117662477
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.977505947
Short name T2380
Test name
Test status
Simulation time 155266876 ps
CPU time 0.79 seconds
Started Jul 24 05:27:15 PM PDT 24
Finished Jul 24 05:27:16 PM PDT 24
Peak memory 206628 kb
Host smart-80cd6e13-d141-4edb-8517-d2eb39a6d5c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97750
5947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.977505947
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.1706003664
Short name T1678
Test name
Test status
Simulation time 175959390 ps
CPU time 0.82 seconds
Started Jul 24 05:27:08 PM PDT 24
Finished Jul 24 05:27:09 PM PDT 24
Peak memory 206444 kb
Host smart-9cb99489-2dea-4551-9014-3367bd2b9a73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17060
03664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.1706003664
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.260481327
Short name T1477
Test name
Test status
Simulation time 197818023 ps
CPU time 0.82 seconds
Started Jul 24 05:27:04 PM PDT 24
Finished Jul 24 05:27:05 PM PDT 24
Peak memory 206608 kb
Host smart-94b8dbed-9b10-46fe-99d2-da35dc5ca099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26048
1327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.260481327
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.2527537207
Short name T985
Test name
Test status
Simulation time 156495222 ps
CPU time 0.76 seconds
Started Jul 24 05:27:06 PM PDT 24
Finished Jul 24 05:27:07 PM PDT 24
Peak memory 206588 kb
Host smart-9336966a-b104-4221-8ea3-720602545acf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25275
37207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.2527537207
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.4134451727
Short name T791
Test name
Test status
Simulation time 154831449 ps
CPU time 0.8 seconds
Started Jul 24 05:27:06 PM PDT 24
Finished Jul 24 05:27:07 PM PDT 24
Peak memory 206480 kb
Host smart-d3a2598c-7bba-4e58-9cf7-1d2068f3b21b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41344
51727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.4134451727
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.4203813167
Short name T2722
Test name
Test status
Simulation time 239799022 ps
CPU time 0.88 seconds
Started Jul 24 05:27:06 PM PDT 24
Finished Jul 24 05:27:07 PM PDT 24
Peak memory 206580 kb
Host smart-2b80a725-6d0e-4dc1-b5d6-db850830ee0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42038
13167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.4203813167
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.3505847034
Short name T1080
Test name
Test status
Simulation time 4624256881 ps
CPU time 119.08 seconds
Started Jul 24 05:27:08 PM PDT 24
Finished Jul 24 05:29:07 PM PDT 24
Peak memory 206964 kb
Host smart-a93f67da-35ad-4ecb-84fc-31397ab5a427
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3505847034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.3505847034
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.2331858520
Short name T533
Test name
Test status
Simulation time 174865819 ps
CPU time 0.79 seconds
Started Jul 24 05:27:02 PM PDT 24
Finished Jul 24 05:27:03 PM PDT 24
Peak memory 206592 kb
Host smart-09749f20-a20e-4d8d-9b28-223cd30a3fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23318
58520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.2331858520
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.2079701810
Short name T199
Test name
Test status
Simulation time 176519500 ps
CPU time 0.79 seconds
Started Jul 24 05:27:14 PM PDT 24
Finished Jul 24 05:27:15 PM PDT 24
Peak memory 206544 kb
Host smart-abbe7ed1-d69f-4a8e-a742-fa5ad08b85c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20797
01810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.2079701810
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.3638693749
Short name T1013
Test name
Test status
Simulation time 198976618 ps
CPU time 0.87 seconds
Started Jul 24 05:27:13 PM PDT 24
Finished Jul 24 05:27:14 PM PDT 24
Peak memory 206544 kb
Host smart-e097da0b-45c7-4bba-b09d-060f321782ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36386
93749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.3638693749
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.3796578062
Short name T2119
Test name
Test status
Simulation time 4108448907 ps
CPU time 28.29 seconds
Started Jul 24 05:27:32 PM PDT 24
Finished Jul 24 05:28:00 PM PDT 24
Peak memory 206944 kb
Host smart-0a8df648-529a-480c-ae33-957914049776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37965
78062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.3796578062
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.407440688
Short name T1597
Test name
Test status
Simulation time 31300533 ps
CPU time 0.65 seconds
Started Jul 24 05:27:13 PM PDT 24
Finished Jul 24 05:27:14 PM PDT 24
Peak memory 206572 kb
Host smart-ef22ac35-aafd-4e06-8ff9-1bad21e0840e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=407440688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.407440688
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.1825855790
Short name T212
Test name
Test status
Simulation time 4206715218 ps
CPU time 6.12 seconds
Started Jul 24 05:27:14 PM PDT 24
Finished Jul 24 05:27:20 PM PDT 24
Peak memory 206884 kb
Host smart-c83e371f-8629-4e27-b83d-4b74746f2f26
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1825855790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.1825855790
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.2227620089
Short name T1709
Test name
Test status
Simulation time 13387741049 ps
CPU time 12.72 seconds
Started Jul 24 05:27:04 PM PDT 24
Finished Jul 24 05:27:17 PM PDT 24
Peak memory 206740 kb
Host smart-f7919015-46e8-452a-bb4b-412984bbea4d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2227620089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.2227620089
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.4265469092
Short name T1817
Test name
Test status
Simulation time 23320081751 ps
CPU time 22.17 seconds
Started Jul 24 05:27:20 PM PDT 24
Finished Jul 24 05:27:43 PM PDT 24
Peak memory 206724 kb
Host smart-fc14e81a-0cd7-468e-92c6-1cdde250606c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4265469092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.4265469092
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.2008601561
Short name T429
Test name
Test status
Simulation time 167652503 ps
CPU time 0.77 seconds
Started Jul 24 05:27:12 PM PDT 24
Finished Jul 24 05:27:13 PM PDT 24
Peak memory 206612 kb
Host smart-89105317-d021-464e-934a-a67bb2ac3d4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20086
01561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.2008601561
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.473085079
Short name T2015
Test name
Test status
Simulation time 164911893 ps
CPU time 0.83 seconds
Started Jul 24 05:27:05 PM PDT 24
Finished Jul 24 05:27:06 PM PDT 24
Peak memory 206588 kb
Host smart-75fcbe6c-8754-409e-94f6-13d5084cc4a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47308
5079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.473085079
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.1941359493
Short name T1456
Test name
Test status
Simulation time 314385079 ps
CPU time 1.19 seconds
Started Jul 24 05:26:59 PM PDT 24
Finished Jul 24 05:27:01 PM PDT 24
Peak memory 206588 kb
Host smart-777001bc-b827-4131-b324-cc8cef1eca37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19413
59493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.1941359493
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.3833941048
Short name T945
Test name
Test status
Simulation time 1294956265 ps
CPU time 2.72 seconds
Started Jul 24 05:27:11 PM PDT 24
Finished Jul 24 05:27:14 PM PDT 24
Peak memory 206844 kb
Host smart-45248107-a3fa-48de-b1b8-0c218c2ebdde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38339
41048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.3833941048
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.3683140252
Short name T2669
Test name
Test status
Simulation time 20620164350 ps
CPU time 40.62 seconds
Started Jul 24 05:27:19 PM PDT 24
Finished Jul 24 05:28:00 PM PDT 24
Peak memory 206740 kb
Host smart-2d2919a8-2712-496e-9196-a2c7418a8f5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36831
40252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.3683140252
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.2377393633
Short name T380
Test name
Test status
Simulation time 500774209 ps
CPU time 1.34 seconds
Started Jul 24 05:27:11 PM PDT 24
Finished Jul 24 05:27:12 PM PDT 24
Peak memory 206552 kb
Host smart-b5ae3cdc-43bc-4c34-bcac-9abfd1a6bd31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23773
93633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.2377393633
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.2925584854
Short name T744
Test name
Test status
Simulation time 133550743 ps
CPU time 0.74 seconds
Started Jul 24 05:27:11 PM PDT 24
Finished Jul 24 05:27:12 PM PDT 24
Peak memory 206592 kb
Host smart-b4efa550-f651-44d3-a59b-6580376d689f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29255
84854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.2925584854
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.935105776
Short name T2368
Test name
Test status
Simulation time 87346584 ps
CPU time 0.7 seconds
Started Jul 24 05:27:05 PM PDT 24
Finished Jul 24 05:27:05 PM PDT 24
Peak memory 206560 kb
Host smart-dc2a974a-9856-4b56-a69d-ff1c3cbae35d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93510
5776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.935105776
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.1166440348
Short name T1243
Test name
Test status
Simulation time 776456488 ps
CPU time 1.92 seconds
Started Jul 24 05:27:23 PM PDT 24
Finished Jul 24 05:27:25 PM PDT 24
Peak memory 206856 kb
Host smart-799a5dd9-f512-4a86-a612-1eb0557150d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11664
40348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.1166440348
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.4048060164
Short name T438
Test name
Test status
Simulation time 206404124 ps
CPU time 2.08 seconds
Started Jul 24 05:27:12 PM PDT 24
Finished Jul 24 05:27:14 PM PDT 24
Peak memory 206724 kb
Host smart-5e71b250-894a-4191-adde-2a547d5d00fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40480
60164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.4048060164
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.2205289752
Short name T2642
Test name
Test status
Simulation time 249533337 ps
CPU time 0.91 seconds
Started Jul 24 05:27:06 PM PDT 24
Finished Jul 24 05:27:07 PM PDT 24
Peak memory 206552 kb
Host smart-16f67484-75b8-4f03-9a31-8526c4cbf599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22052
89752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.2205289752
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.1160956858
Short name T235
Test name
Test status
Simulation time 142419995 ps
CPU time 0.72 seconds
Started Jul 24 05:27:18 PM PDT 24
Finished Jul 24 05:27:19 PM PDT 24
Peak memory 206512 kb
Host smart-770e0a30-adf7-4bc9-89e6-739545c4f0fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11609
56858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.1160956858
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.4169653469
Short name T2523
Test name
Test status
Simulation time 167672352 ps
CPU time 0.81 seconds
Started Jul 24 05:27:08 PM PDT 24
Finished Jul 24 05:27:09 PM PDT 24
Peak memory 206516 kb
Host smart-598a9d3f-03bb-4982-8ed2-494a11b46f90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41696
53469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.4169653469
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_iso_retraction.1753663904
Short name T1059
Test name
Test status
Simulation time 5966014198 ps
CPU time 18.52 seconds
Started Jul 24 05:27:11 PM PDT 24
Finished Jul 24 05:27:30 PM PDT 24
Peak memory 206800 kb
Host smart-4bba080c-2d5c-48de-bf76-67b666a830da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17536
63904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_iso_retraction.1753663904
Directory /workspace/25.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.1762497957
Short name T886
Test name
Test status
Simulation time 204247460 ps
CPU time 0.92 seconds
Started Jul 24 05:27:03 PM PDT 24
Finished Jul 24 05:27:04 PM PDT 24
Peak memory 206588 kb
Host smart-5d3dcf0a-879b-4abb-9d09-f0548c7de6f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17624
97957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.1762497957
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.3657447246
Short name T854
Test name
Test status
Simulation time 23329198268 ps
CPU time 24.5 seconds
Started Jul 24 05:27:09 PM PDT 24
Finished Jul 24 05:27:38 PM PDT 24
Peak memory 206512 kb
Host smart-9edb734e-a564-487b-aaeb-830bd49e9302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36574
47246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.3657447246
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.578024845
Short name T1320
Test name
Test status
Simulation time 3288956493 ps
CPU time 4.11 seconds
Started Jul 24 05:27:10 PM PDT 24
Finished Jul 24 05:27:14 PM PDT 24
Peak memory 206700 kb
Host smart-6bab0c55-dde5-4da0-ac33-a2b097f1b76f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57802
4845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.578024845
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.3105382623
Short name T2083
Test name
Test status
Simulation time 10515995376 ps
CPU time 75.57 seconds
Started Jul 24 05:27:15 PM PDT 24
Finished Jul 24 05:28:31 PM PDT 24
Peak memory 206996 kb
Host smart-75feb6b4-f521-47ff-becc-206e5f57b433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31053
82623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.3105382623
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.596271094
Short name T1131
Test name
Test status
Simulation time 5335836403 ps
CPU time 48.98 seconds
Started Jul 24 05:27:03 PM PDT 24
Finished Jul 24 05:27:52 PM PDT 24
Peak memory 206888 kb
Host smart-fb3aafbc-1482-4dee-95be-e1377d23867b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=596271094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.596271094
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.3987010032
Short name T308
Test name
Test status
Simulation time 258323190 ps
CPU time 0.95 seconds
Started Jul 24 05:27:04 PM PDT 24
Finished Jul 24 05:27:05 PM PDT 24
Peak memory 206616 kb
Host smart-b618d69a-d99d-4ec5-a7db-733d6b777b6f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3987010032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.3987010032
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.3091202664
Short name T1453
Test name
Test status
Simulation time 189447517 ps
CPU time 0.87 seconds
Started Jul 24 05:27:08 PM PDT 24
Finished Jul 24 05:27:09 PM PDT 24
Peak memory 206660 kb
Host smart-5b11ed5a-32bd-487d-bc41-61b47aa0b90f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30912
02664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.3091202664
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.2400225455
Short name T1065
Test name
Test status
Simulation time 3722834671 ps
CPU time 35 seconds
Started Jul 24 05:27:06 PM PDT 24
Finished Jul 24 05:27:41 PM PDT 24
Peak memory 206948 kb
Host smart-db5e37b9-9488-41ea-9689-249d5020127f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24002
25455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.2400225455
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.3442995072
Short name T4
Test name
Test status
Simulation time 3686030494 ps
CPU time 32.47 seconds
Started Jul 24 05:27:03 PM PDT 24
Finished Jul 24 05:27:36 PM PDT 24
Peak memory 206888 kb
Host smart-5780f8a2-1e27-4ab6-af43-5cf88e9c7042
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3442995072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.3442995072
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.2709589948
Short name T1526
Test name
Test status
Simulation time 157217296 ps
CPU time 0.8 seconds
Started Jul 24 05:27:17 PM PDT 24
Finished Jul 24 05:27:18 PM PDT 24
Peak memory 206508 kb
Host smart-f19b2881-642d-4db0-8022-3350072c9a88
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2709589948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.2709589948
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.3807831322
Short name T300
Test name
Test status
Simulation time 162839828 ps
CPU time 0.75 seconds
Started Jul 24 05:27:17 PM PDT 24
Finished Jul 24 05:27:17 PM PDT 24
Peak memory 206592 kb
Host smart-6ea1b282-80c9-4075-ba66-7ba355e7ad59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38078
31322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.3807831322
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.2411546548
Short name T2280
Test name
Test status
Simulation time 158322222 ps
CPU time 0.79 seconds
Started Jul 24 05:27:07 PM PDT 24
Finished Jul 24 05:27:08 PM PDT 24
Peak memory 206588 kb
Host smart-beb4f25f-7632-4d0e-8db4-5bd91a7c4247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24115
46548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.2411546548
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.3056105403
Short name T2180
Test name
Test status
Simulation time 230568303 ps
CPU time 0.9 seconds
Started Jul 24 05:27:05 PM PDT 24
Finished Jul 24 05:27:06 PM PDT 24
Peak memory 206660 kb
Host smart-75338bf2-5921-4090-b927-eba097656e8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30561
05403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.3056105403
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.4143310533
Short name T1134
Test name
Test status
Simulation time 181951739 ps
CPU time 0.81 seconds
Started Jul 24 05:27:09 PM PDT 24
Finished Jul 24 05:27:10 PM PDT 24
Peak memory 206600 kb
Host smart-ab47e7d7-ce58-46c3-b181-fa2877438fa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41433
10533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.4143310533
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.1658825186
Short name T1786
Test name
Test status
Simulation time 173992440 ps
CPU time 0.82 seconds
Started Jul 24 05:27:08 PM PDT 24
Finished Jul 24 05:27:09 PM PDT 24
Peak memory 206592 kb
Host smart-e97d1ea0-3182-4241-acd5-70f2063a4443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16588
25186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.1658825186
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.1319457200
Short name T2191
Test name
Test status
Simulation time 190336906 ps
CPU time 0.86 seconds
Started Jul 24 05:27:22 PM PDT 24
Finished Jul 24 05:27:23 PM PDT 24
Peak memory 206544 kb
Host smart-05713d20-fc85-4aeb-9a7d-cb02bad3e1f0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1319457200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.1319457200
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.4268649611
Short name T943
Test name
Test status
Simulation time 169582278 ps
CPU time 0.8 seconds
Started Jul 24 05:27:15 PM PDT 24
Finished Jul 24 05:27:16 PM PDT 24
Peak memory 206604 kb
Host smart-2ea09e71-5fbb-45d6-ad91-ac43d30d9d18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42686
49611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.4268649611
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.2472946633
Short name T637
Test name
Test status
Simulation time 43044050 ps
CPU time 0.64 seconds
Started Jul 24 05:27:18 PM PDT 24
Finished Jul 24 05:27:19 PM PDT 24
Peak memory 206640 kb
Host smart-7bc764d9-af45-4f79-b289-fd7b09bed746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24729
46633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.2472946633
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.1478292653
Short name T1482
Test name
Test status
Simulation time 8489547002 ps
CPU time 18.76 seconds
Started Jul 24 05:27:09 PM PDT 24
Finished Jul 24 05:27:28 PM PDT 24
Peak memory 206956 kb
Host smart-0210e479-f37e-4bfe-8091-46ce16542d77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14782
92653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.1478292653
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.624896599
Short name T1251
Test name
Test status
Simulation time 188749509 ps
CPU time 0.86 seconds
Started Jul 24 05:27:11 PM PDT 24
Finished Jul 24 05:27:12 PM PDT 24
Peak memory 206588 kb
Host smart-83e8c15f-1706-43ab-bc11-7c2ba717ec80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62489
6599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.624896599
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.4009008760
Short name T302
Test name
Test status
Simulation time 191143102 ps
CPU time 0.81 seconds
Started Jul 24 05:27:14 PM PDT 24
Finished Jul 24 05:27:15 PM PDT 24
Peak memory 206644 kb
Host smart-d04b042f-6bff-4c83-a817-c1e9d97a1c4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40090
08760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.4009008760
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.1705610998
Short name T812
Test name
Test status
Simulation time 246124570 ps
CPU time 0.9 seconds
Started Jul 24 05:27:27 PM PDT 24
Finished Jul 24 05:27:28 PM PDT 24
Peak memory 206556 kb
Host smart-93edbfde-96f7-45d3-b233-fcd0493eb332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17056
10998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.1705610998
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.3067311701
Short name T1062
Test name
Test status
Simulation time 201264820 ps
CPU time 0.9 seconds
Started Jul 24 05:27:15 PM PDT 24
Finished Jul 24 05:27:16 PM PDT 24
Peak memory 206644 kb
Host smart-e75044f1-845a-4cb2-9c86-da8afb6e4884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30673
11701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.3067311701
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.3760448548
Short name T38
Test name
Test status
Simulation time 172726422 ps
CPU time 0.76 seconds
Started Jul 24 05:27:06 PM PDT 24
Finished Jul 24 05:27:07 PM PDT 24
Peak memory 206584 kb
Host smart-41259269-1e85-497b-8f47-405565aa5dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37604
48548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.3760448548
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.318873827
Short name T664
Test name
Test status
Simulation time 159181401 ps
CPU time 0.77 seconds
Started Jul 24 05:27:06 PM PDT 24
Finished Jul 24 05:27:07 PM PDT 24
Peak memory 206556 kb
Host smart-1df0f26a-beda-44c5-b337-d3df13b00ea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31887
3827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.318873827
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.292254426
Short name T2256
Test name
Test status
Simulation time 155387149 ps
CPU time 0.78 seconds
Started Jul 24 05:27:05 PM PDT 24
Finished Jul 24 05:27:06 PM PDT 24
Peak memory 206460 kb
Host smart-1a99abff-e913-476b-a8e8-fab942aaebcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29225
4426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.292254426
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.570877066
Short name T2078
Test name
Test status
Simulation time 255671239 ps
CPU time 0.91 seconds
Started Jul 24 05:27:16 PM PDT 24
Finished Jul 24 05:27:17 PM PDT 24
Peak memory 206592 kb
Host smart-9b01f986-6a94-401b-adca-59109fce8045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57087
7066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.570877066
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.1923233939
Short name T2265
Test name
Test status
Simulation time 5996634442 ps
CPU time 171.4 seconds
Started Jul 24 05:27:07 PM PDT 24
Finished Jul 24 05:29:58 PM PDT 24
Peak memory 206868 kb
Host smart-b4c9b927-0865-40de-9aa7-1f953234fbde
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1923233939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.1923233939
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.1195000656
Short name T1943
Test name
Test status
Simulation time 190949329 ps
CPU time 0.76 seconds
Started Jul 24 05:27:21 PM PDT 24
Finished Jul 24 05:27:22 PM PDT 24
Peak memory 206552 kb
Host smart-d2bd3c64-5fb0-44c2-92ef-26fcbc0097d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11950
00656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.1195000656
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.3017646182
Short name T1475
Test name
Test status
Simulation time 149563387 ps
CPU time 0.77 seconds
Started Jul 24 05:27:17 PM PDT 24
Finished Jul 24 05:27:18 PM PDT 24
Peak memory 206488 kb
Host smart-4900c853-469f-4b8d-9c8e-81be800c3840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30176
46182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.3017646182
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.3407406529
Short name T871
Test name
Test status
Simulation time 443716285 ps
CPU time 1.26 seconds
Started Jul 24 05:27:21 PM PDT 24
Finished Jul 24 05:27:23 PM PDT 24
Peak memory 206588 kb
Host smart-45201e0e-3d8c-47ee-a23c-af604f3b7118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34074
06529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.3407406529
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.3663649712
Short name T1713
Test name
Test status
Simulation time 5364479926 ps
CPU time 34.67 seconds
Started Jul 24 05:27:13 PM PDT 24
Finished Jul 24 05:27:48 PM PDT 24
Peak memory 206856 kb
Host smart-b04fd3ed-098b-4eab-bb91-c6ee5eb1d2aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36636
49712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.3663649712
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.3360168054
Short name T2741
Test name
Test status
Simulation time 43716116 ps
CPU time 0.67 seconds
Started Jul 24 05:27:23 PM PDT 24
Finished Jul 24 05:27:24 PM PDT 24
Peak memory 206620 kb
Host smart-d25b0f9e-c568-4738-bf92-1e4ad807414f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3360168054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.3360168054
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.3479343241
Short name T2717
Test name
Test status
Simulation time 3764954106 ps
CPU time 4.53 seconds
Started Jul 24 05:27:17 PM PDT 24
Finished Jul 24 05:27:21 PM PDT 24
Peak memory 206740 kb
Host smart-21fd3ca5-f2e0-4e0b-9351-e8d8cc4eabac
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3479343241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.3479343241
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.806756853
Short name T2688
Test name
Test status
Simulation time 13372180965 ps
CPU time 12.37 seconds
Started Jul 24 05:27:18 PM PDT 24
Finished Jul 24 05:27:31 PM PDT 24
Peak memory 206864 kb
Host smart-4975cbae-dd3a-48ff-948a-1cbfbfcab854
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=806756853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.806756853
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.3880247658
Short name T1830
Test name
Test status
Simulation time 23333612760 ps
CPU time 21.22 seconds
Started Jul 24 05:27:19 PM PDT 24
Finished Jul 24 05:27:40 PM PDT 24
Peak memory 206928 kb
Host smart-6e804557-c282-432d-953d-2adf49b70f3b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3880247658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.3880247658
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.446864868
Short name T1754
Test name
Test status
Simulation time 199153683 ps
CPU time 0.85 seconds
Started Jul 24 05:27:16 PM PDT 24
Finished Jul 24 05:27:17 PM PDT 24
Peak memory 206544 kb
Host smart-56f2d6ec-74c4-42f3-b98e-2569f4d49657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44686
4868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.446864868
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.2189117921
Short name T1079
Test name
Test status
Simulation time 199016392 ps
CPU time 0.88 seconds
Started Jul 24 05:27:23 PM PDT 24
Finished Jul 24 05:27:24 PM PDT 24
Peak memory 206620 kb
Host smart-ef656043-120d-4a65-b2a9-6a4844c2c0dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21891
17921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.2189117921
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.665108423
Short name T2169
Test name
Test status
Simulation time 521968151 ps
CPU time 1.47 seconds
Started Jul 24 05:27:05 PM PDT 24
Finished Jul 24 05:27:06 PM PDT 24
Peak memory 206728 kb
Host smart-4561ea7b-8067-4061-ab0e-103f63fb2618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66510
8423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.665108423
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.674163238
Short name T1970
Test name
Test status
Simulation time 700515761 ps
CPU time 1.74 seconds
Started Jul 24 05:27:05 PM PDT 24
Finished Jul 24 05:27:07 PM PDT 24
Peak memory 206728 kb
Host smart-f6fe2046-d961-4e03-933e-ac45fc980e48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67416
3238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.674163238
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.3586502103
Short name T2458
Test name
Test status
Simulation time 9381898009 ps
CPU time 18.61 seconds
Started Jul 24 05:27:19 PM PDT 24
Finished Jul 24 05:27:38 PM PDT 24
Peak memory 206856 kb
Host smart-1866455e-a318-4091-8fee-e0adf6c1fdf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35865
02103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.3586502103
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_device_timeout.2908713166
Short name T2425
Test name
Test status
Simulation time 153380865 ps
CPU time 0.75 seconds
Started Jul 24 05:27:12 PM PDT 24
Finished Jul 24 05:27:13 PM PDT 24
Peak memory 206568 kb
Host smart-5083e98a-3552-4a0e-b0e5-acda214c4fad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29087
13166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_timeout.2908713166
Directory /workspace/26.usbdev_device_timeout/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.3748364915
Short name T772
Test name
Test status
Simulation time 422646666 ps
CPU time 1.36 seconds
Started Jul 24 05:27:10 PM PDT 24
Finished Jul 24 05:27:11 PM PDT 24
Peak memory 206520 kb
Host smart-e313e01f-f2fa-4f2f-8855-91403c7dbbbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37483
64915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.3748364915
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.1841763233
Short name T2728
Test name
Test status
Simulation time 141281031 ps
CPU time 0.73 seconds
Started Jul 24 05:27:24 PM PDT 24
Finished Jul 24 05:27:25 PM PDT 24
Peak memory 206504 kb
Host smart-0f36699a-b97e-4f29-83d5-239f6bce9a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18417
63233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.1841763233
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.2381881320
Short name T2312
Test name
Test status
Simulation time 36335918 ps
CPU time 0.67 seconds
Started Jul 24 05:27:16 PM PDT 24
Finished Jul 24 05:27:16 PM PDT 24
Peak memory 206516 kb
Host smart-224e87b3-bfaa-4a4b-9605-b613d47a6ed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23818
81320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.2381881320
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.713401765
Short name T1683
Test name
Test status
Simulation time 847709747 ps
CPU time 1.88 seconds
Started Jul 24 05:27:18 PM PDT 24
Finished Jul 24 05:27:21 PM PDT 24
Peak memory 206756 kb
Host smart-0d0a2bd0-3039-4c8a-8f39-8127e85c4177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71340
1765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.713401765
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.705822586
Short name T447
Test name
Test status
Simulation time 338865003 ps
CPU time 2.08 seconds
Started Jul 24 05:27:18 PM PDT 24
Finished Jul 24 05:27:20 PM PDT 24
Peak memory 206788 kb
Host smart-b886147c-c4e7-4896-966c-aecd3ef0676c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70582
2586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.705822586
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.3480457125
Short name T925
Test name
Test status
Simulation time 264504324 ps
CPU time 1.06 seconds
Started Jul 24 05:27:17 PM PDT 24
Finished Jul 24 05:27:19 PM PDT 24
Peak memory 206572 kb
Host smart-51150bf6-3626-496d-a213-6b7f22d6968a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34804
57125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.3480457125
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.1856508289
Short name T321
Test name
Test status
Simulation time 183169678 ps
CPU time 0.78 seconds
Started Jul 24 05:27:23 PM PDT 24
Finished Jul 24 05:27:24 PM PDT 24
Peak memory 206528 kb
Host smart-161390f7-abd9-45a1-8c78-4fbb3c93d3f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18565
08289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.1856508289
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.1049792562
Short name T310
Test name
Test status
Simulation time 208418639 ps
CPU time 0.88 seconds
Started Jul 24 05:27:04 PM PDT 24
Finished Jul 24 05:27:05 PM PDT 24
Peak memory 206580 kb
Host smart-740e6008-a041-45cf-adc7-a508203932c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10497
92562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.1049792562
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_invalid_sync.809506162
Short name T2714
Test name
Test status
Simulation time 4749768373 ps
CPU time 47.16 seconds
Started Jul 24 05:27:12 PM PDT 24
Finished Jul 24 05:28:00 PM PDT 24
Peak memory 206948 kb
Host smart-87e32205-0a9b-406f-8598-20ce0b2f3bb4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=809506162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.809506162
Directory /workspace/26.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/26.usbdev_iso_retraction.2920736673
Short name T1012
Test name
Test status
Simulation time 4854243881 ps
CPU time 38.53 seconds
Started Jul 24 05:27:19 PM PDT 24
Finished Jul 24 05:27:58 PM PDT 24
Peak memory 206856 kb
Host smart-259dbd31-62f7-41d5-9e73-5cc0229d60d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29207
36673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_iso_retraction.2920736673
Directory /workspace/26.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.838506198
Short name T465
Test name
Test status
Simulation time 164275357 ps
CPU time 0.81 seconds
Started Jul 24 05:27:08 PM PDT 24
Finished Jul 24 05:27:09 PM PDT 24
Peak memory 206640 kb
Host smart-0a2d9a46-7c76-461e-8abd-d4677e17c398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83850
6198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.838506198
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.2500016740
Short name T643
Test name
Test status
Simulation time 23334703709 ps
CPU time 25.59 seconds
Started Jul 24 05:27:18 PM PDT 24
Finished Jul 24 05:27:43 PM PDT 24
Peak memory 206684 kb
Host smart-4bb2c15c-0aca-4099-86cf-2725b0c20f27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25000
16740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.2500016740
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.1416157747
Short name T1956
Test name
Test status
Simulation time 3347902798 ps
CPU time 3.87 seconds
Started Jul 24 05:27:18 PM PDT 24
Finished Jul 24 05:27:22 PM PDT 24
Peak memory 206692 kb
Host smart-c274111f-bc9f-40a0-b095-d73fd3d9f711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14161
57747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.1416157747
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.3805036008
Short name T152
Test name
Test status
Simulation time 7723639192 ps
CPU time 72.01 seconds
Started Jul 24 05:27:30 PM PDT 24
Finished Jul 24 05:28:42 PM PDT 24
Peak memory 206916 kb
Host smart-34190c5e-b0b9-474e-8768-c6ac0bc8044f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38050
36008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.3805036008
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.944754628
Short name T1685
Test name
Test status
Simulation time 4611816016 ps
CPU time 30.41 seconds
Started Jul 24 05:27:19 PM PDT 24
Finished Jul 24 05:27:50 PM PDT 24
Peak memory 206960 kb
Host smart-c92c1ef0-c779-4a8a-a7c3-1dbb66592b2f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=944754628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.944754628
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.3548053721
Short name T2616
Test name
Test status
Simulation time 257793058 ps
CPU time 0.95 seconds
Started Jul 24 05:27:15 PM PDT 24
Finished Jul 24 05:27:16 PM PDT 24
Peak memory 206644 kb
Host smart-0e451347-afd3-457b-8944-74ebc7ec3410
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3548053721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.3548053721
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.4247779969
Short name T1724
Test name
Test status
Simulation time 190594322 ps
CPU time 0.83 seconds
Started Jul 24 05:27:25 PM PDT 24
Finished Jul 24 05:27:26 PM PDT 24
Peak memory 206552 kb
Host smart-15afd041-d647-4585-91fa-c6036fac4a8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42477
79969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.4247779969
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.912410304
Short name T778
Test name
Test status
Simulation time 6217209043 ps
CPU time 55.24 seconds
Started Jul 24 05:27:14 PM PDT 24
Finished Jul 24 05:28:09 PM PDT 24
Peak memory 206852 kb
Host smart-303aed4b-2cd0-4522-80ec-3ce32e0ee5b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91241
0304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.912410304
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.904109483
Short name T159
Test name
Test status
Simulation time 6388889510 ps
CPU time 172.48 seconds
Started Jul 24 05:27:19 PM PDT 24
Finished Jul 24 05:30:12 PM PDT 24
Peak memory 206896 kb
Host smart-7acd0cff-e927-4143-98b6-c855f5c26975
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=904109483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.904109483
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.4233742799
Short name T1638
Test name
Test status
Simulation time 153665198 ps
CPU time 0.79 seconds
Started Jul 24 05:27:23 PM PDT 24
Finished Jul 24 05:27:24 PM PDT 24
Peak memory 206604 kb
Host smart-c722a392-dd57-478e-b058-43f07f8e6267
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4233742799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.4233742799
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.3533956176
Short name T1034
Test name
Test status
Simulation time 150900159 ps
CPU time 0.78 seconds
Started Jul 24 05:27:24 PM PDT 24
Finished Jul 24 05:27:25 PM PDT 24
Peak memory 206788 kb
Host smart-88f821fb-afaa-4831-ba81-4f92aae7e24b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35339
56176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.3533956176
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.222798428
Short name T138
Test name
Test status
Simulation time 197791633 ps
CPU time 0.89 seconds
Started Jul 24 05:27:18 PM PDT 24
Finished Jul 24 05:27:19 PM PDT 24
Peak memory 206604 kb
Host smart-0f65e0a6-72ab-4c43-8ac9-fa01e23a0ede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22279
8428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.222798428
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.617805809
Short name T1801
Test name
Test status
Simulation time 209196723 ps
CPU time 0.84 seconds
Started Jul 24 05:27:30 PM PDT 24
Finished Jul 24 05:27:31 PM PDT 24
Peak memory 206548 kb
Host smart-ab574768-fa7f-4b38-bd22-76bb372bf6b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61780
5809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.617805809
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.892821343
Short name T1307
Test name
Test status
Simulation time 231107575 ps
CPU time 0.83 seconds
Started Jul 24 05:27:23 PM PDT 24
Finished Jul 24 05:27:25 PM PDT 24
Peak memory 206592 kb
Host smart-a6413600-6c8f-4d89-8462-e9d53c4a7e9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89282
1343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.892821343
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.4038113795
Short name T1412
Test name
Test status
Simulation time 217181783 ps
CPU time 0.9 seconds
Started Jul 24 05:27:25 PM PDT 24
Finished Jul 24 05:27:26 PM PDT 24
Peak memory 206504 kb
Host smart-fdfffff5-8a7a-449a-a03b-db8da2b1e055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40381
13795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.4038113795
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.3702714173
Short name T1149
Test name
Test status
Simulation time 213528324 ps
CPU time 0.93 seconds
Started Jul 24 05:27:26 PM PDT 24
Finished Jul 24 05:27:27 PM PDT 24
Peak memory 206776 kb
Host smart-24c258eb-6a0a-4e93-95eb-9774b0614e17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37027
14173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.3702714173
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.4066631651
Short name T1888
Test name
Test status
Simulation time 224534247 ps
CPU time 0.9 seconds
Started Jul 24 05:27:26 PM PDT 24
Finished Jul 24 05:27:27 PM PDT 24
Peak memory 206592 kb
Host smart-10a111e0-f8c8-4311-aa58-b3d6f89f7a5a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4066631651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.4066631651
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.2399702936
Short name T873
Test name
Test status
Simulation time 160798729 ps
CPU time 0.79 seconds
Started Jul 24 05:27:18 PM PDT 24
Finished Jul 24 05:27:19 PM PDT 24
Peak memory 206548 kb
Host smart-ce913a2d-4a23-487d-8285-f4a0caa7fc2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23997
02936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.2399702936
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.3068287843
Short name T413
Test name
Test status
Simulation time 38889635 ps
CPU time 0.65 seconds
Started Jul 24 05:27:30 PM PDT 24
Finished Jul 24 05:27:31 PM PDT 24
Peak memory 206548 kb
Host smart-e2efe1b5-bfc8-401f-9aba-b24e84e2f336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30682
87843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.3068287843
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.1977929263
Short name T237
Test name
Test status
Simulation time 16391544939 ps
CPU time 38.07 seconds
Started Jul 24 05:27:21 PM PDT 24
Finished Jul 24 05:27:59 PM PDT 24
Peak memory 215140 kb
Host smart-b5675f6c-a003-435c-9052-e28a1434fdd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19779
29263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.1977929263
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.1325692704
Short name T1082
Test name
Test status
Simulation time 173902176 ps
CPU time 0.77 seconds
Started Jul 24 05:27:25 PM PDT 24
Finished Jul 24 05:27:26 PM PDT 24
Peak memory 206548 kb
Host smart-feb1d045-ce89-4a87-a20c-7af869552445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13256
92704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.1325692704
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.481136561
Short name T1531
Test name
Test status
Simulation time 202498286 ps
CPU time 0.84 seconds
Started Jul 24 05:27:30 PM PDT 24
Finished Jul 24 05:27:31 PM PDT 24
Peak memory 206552 kb
Host smart-9e4d6420-9a28-4c3e-aafa-c91d1630e84c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48113
6561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.481136561
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.2008863886
Short name T1764
Test name
Test status
Simulation time 185048329 ps
CPU time 0.81 seconds
Started Jul 24 05:27:21 PM PDT 24
Finished Jul 24 05:27:22 PM PDT 24
Peak memory 206492 kb
Host smart-51be0660-5611-4e7c-9c63-de6e32f110c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20088
63886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.2008863886
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.4271436478
Short name T1380
Test name
Test status
Simulation time 175611548 ps
CPU time 0.83 seconds
Started Jul 24 05:27:18 PM PDT 24
Finished Jul 24 05:27:19 PM PDT 24
Peak memory 206568 kb
Host smart-52ef3a39-2a4b-48e8-b661-7d32d8cff62a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42714
36478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.4271436478
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.2982927664
Short name T1225
Test name
Test status
Simulation time 208649042 ps
CPU time 0.86 seconds
Started Jul 24 05:27:24 PM PDT 24
Finished Jul 24 05:27:25 PM PDT 24
Peak memory 206780 kb
Host smart-7bedba76-d58f-4524-b26b-ecf35cb6ca18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29829
27664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.2982927664
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.970958101
Short name T1776
Test name
Test status
Simulation time 152547055 ps
CPU time 0.78 seconds
Started Jul 24 05:27:24 PM PDT 24
Finished Jul 24 05:27:25 PM PDT 24
Peak memory 206636 kb
Host smart-e1a01ecf-5946-40a0-9687-c4f37080c4d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97095
8101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.970958101
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.3384998173
Short name T885
Test name
Test status
Simulation time 158917913 ps
CPU time 0.78 seconds
Started Jul 24 05:27:25 PM PDT 24
Finished Jul 24 05:27:26 PM PDT 24
Peak memory 206552 kb
Host smart-0a221f3f-fa9f-4d64-8494-c10e7f8385d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33849
98173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.3384998173
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.2143539225
Short name T690
Test name
Test status
Simulation time 209243602 ps
CPU time 0.87 seconds
Started Jul 24 05:27:20 PM PDT 24
Finished Jul 24 05:27:21 PM PDT 24
Peak memory 206488 kb
Host smart-e177878e-44c8-4267-bf1e-2333ba431188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21435
39225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.2143539225
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.2974820968
Short name T1442
Test name
Test status
Simulation time 3988806436 ps
CPU time 111.95 seconds
Started Jul 24 05:27:19 PM PDT 24
Finished Jul 24 05:29:11 PM PDT 24
Peak memory 206940 kb
Host smart-34fee5ca-87a6-4e79-b2f3-605c50141a3b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2974820968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.2974820968
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.2871374414
Short name T706
Test name
Test status
Simulation time 168673638 ps
CPU time 0.78 seconds
Started Jul 24 05:27:19 PM PDT 24
Finished Jul 24 05:27:21 PM PDT 24
Peak memory 206592 kb
Host smart-934bd472-3d31-4da2-9378-18967d23b6d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28713
74414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.2871374414
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.3227065545
Short name T2019
Test name
Test status
Simulation time 187108791 ps
CPU time 0.79 seconds
Started Jul 24 05:27:19 PM PDT 24
Finished Jul 24 05:27:20 PM PDT 24
Peak memory 206556 kb
Host smart-0ab37a34-b118-474f-9cee-84e298f90881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32270
65545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.3227065545
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.690641975
Short name T1230
Test name
Test status
Simulation time 673344428 ps
CPU time 1.6 seconds
Started Jul 24 05:27:16 PM PDT 24
Finished Jul 24 05:27:18 PM PDT 24
Peak memory 206764 kb
Host smart-7b7853fa-8f20-4cb3-8815-bc0bdf67b7cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69064
1975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.690641975
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.2415535468
Short name T534
Test name
Test status
Simulation time 3597295155 ps
CPU time 34.68 seconds
Started Jul 24 05:27:16 PM PDT 24
Finished Jul 24 05:27:51 PM PDT 24
Peak memory 206880 kb
Host smart-76f4fa95-4c65-491b-9f19-b7385227fc39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24155
35468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.2415535468
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.3895787123
Short name T2718
Test name
Test status
Simulation time 61731797 ps
CPU time 0.66 seconds
Started Jul 24 05:27:46 PM PDT 24
Finished Jul 24 05:27:47 PM PDT 24
Peak memory 206624 kb
Host smart-c8ae8216-db4b-41ee-882d-649e8d1a545f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3895787123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.3895787123
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.2647107213
Short name T1844
Test name
Test status
Simulation time 3843175873 ps
CPU time 4.87 seconds
Started Jul 24 05:27:17 PM PDT 24
Finished Jul 24 05:27:23 PM PDT 24
Peak memory 206952 kb
Host smart-292f70d5-344d-44e0-8ca4-d4c3bd7686ee
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2647107213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.2647107213
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.2605157091
Short name T210
Test name
Test status
Simulation time 13341965921 ps
CPU time 13.5 seconds
Started Jul 24 05:27:25 PM PDT 24
Finished Jul 24 05:27:39 PM PDT 24
Peak memory 206928 kb
Host smart-fc7c0b27-dc66-4457-a9a7-b226edbbbdf8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2605157091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.2605157091
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.1376530042
Short name T1091
Test name
Test status
Simulation time 23389519545 ps
CPU time 25.83 seconds
Started Jul 24 05:27:20 PM PDT 24
Finished Jul 24 05:27:46 PM PDT 24
Peak memory 206636 kb
Host smart-a15db8d2-5412-4623-803e-f1e08071519d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1376530042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.1376530042
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.2103958224
Short name T997
Test name
Test status
Simulation time 148620668 ps
CPU time 0.78 seconds
Started Jul 24 05:27:21 PM PDT 24
Finished Jul 24 05:27:22 PM PDT 24
Peak memory 206568 kb
Host smart-a8ff5ff9-5d23-4709-a6cf-8c7eb514b00d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21039
58224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.2103958224
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.3828069229
Short name T953
Test name
Test status
Simulation time 146033930 ps
CPU time 0.79 seconds
Started Jul 24 05:27:06 PM PDT 24
Finished Jul 24 05:27:07 PM PDT 24
Peak memory 206588 kb
Host smart-2818be69-247d-46dd-b45a-21bcd5abc9f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38280
69229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.3828069229
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.2731942433
Short name T1492
Test name
Test status
Simulation time 297792127 ps
CPU time 1.08 seconds
Started Jul 24 05:27:18 PM PDT 24
Finished Jul 24 05:27:19 PM PDT 24
Peak memory 206600 kb
Host smart-a49487c0-3fde-4c43-98d4-e2b68237ba26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27319
42433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.2731942433
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.397950056
Short name T2224
Test name
Test status
Simulation time 350334192 ps
CPU time 1.14 seconds
Started Jul 24 05:27:20 PM PDT 24
Finished Jul 24 05:27:22 PM PDT 24
Peak memory 206560 kb
Host smart-dc73a207-6cab-4eef-82c6-071f7ff07069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39795
0056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.397950056
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.3465117148
Short name T2151
Test name
Test status
Simulation time 14373732906 ps
CPU time 24.94 seconds
Started Jul 24 05:27:18 PM PDT 24
Finished Jul 24 05:27:43 PM PDT 24
Peak memory 206956 kb
Host smart-d18f2bdf-5bc0-49a7-93f7-2e142b4ad37c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34651
17148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.3465117148
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.1836552410
Short name T729
Test name
Test status
Simulation time 342486954 ps
CPU time 1.11 seconds
Started Jul 24 05:27:39 PM PDT 24
Finished Jul 24 05:27:41 PM PDT 24
Peak memory 206544 kb
Host smart-948080a7-72b2-44c4-b184-4a058041e099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18365
52410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.1836552410
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.3149611037
Short name T2130
Test name
Test status
Simulation time 131210230 ps
CPU time 0.72 seconds
Started Jul 24 05:27:32 PM PDT 24
Finished Jul 24 05:27:33 PM PDT 24
Peak memory 206524 kb
Host smart-33e35b80-f31a-498c-ac47-12259557116f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31496
11037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.3149611037
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.106710572
Short name T949
Test name
Test status
Simulation time 43367557 ps
CPU time 0.74 seconds
Started Jul 24 05:27:31 PM PDT 24
Finished Jul 24 05:27:33 PM PDT 24
Peak memory 206572 kb
Host smart-91ec1fb7-0a57-48be-b77d-7bb2ecf74dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10671
0572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.106710572
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.3547354971
Short name T2624
Test name
Test status
Simulation time 898634731 ps
CPU time 2.07 seconds
Started Jul 24 05:27:37 PM PDT 24
Finished Jul 24 05:27:39 PM PDT 24
Peak memory 206816 kb
Host smart-77adf23f-1e3f-4ca7-bb4f-04072c21a313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35473
54971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.3547354971
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.2247718089
Short name T2199
Test name
Test status
Simulation time 306811290 ps
CPU time 2.36 seconds
Started Jul 24 05:27:47 PM PDT 24
Finished Jul 24 05:27:50 PM PDT 24
Peak memory 206652 kb
Host smart-554d2e13-d863-44cd-bb9f-f2002bb1e2d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22477
18089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.2247718089
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.1664528316
Short name T1348
Test name
Test status
Simulation time 220569073 ps
CPU time 0.9 seconds
Started Jul 24 05:27:35 PM PDT 24
Finished Jul 24 05:27:41 PM PDT 24
Peak memory 206588 kb
Host smart-7edb1dec-0aeb-4e50-9145-c87cb47f6bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16645
28316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.1664528316
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.2570405842
Short name T786
Test name
Test status
Simulation time 137124332 ps
CPU time 0.79 seconds
Started Jul 24 05:27:23 PM PDT 24
Finished Jul 24 05:27:24 PM PDT 24
Peak memory 206604 kb
Host smart-7a7263fd-4823-4838-b5f9-ccb74fec9c4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25704
05842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.2570405842
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.783764671
Short name T2158
Test name
Test status
Simulation time 247458343 ps
CPU time 0.91 seconds
Started Jul 24 05:27:42 PM PDT 24
Finished Jul 24 05:27:44 PM PDT 24
Peak memory 206556 kb
Host smart-a22479f0-4e6e-4468-af11-9899f18a908b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78376
4671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.783764671
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_iso_retraction.3621268151
Short name T1542
Test name
Test status
Simulation time 4288821995 ps
CPU time 35.56 seconds
Started Jul 24 05:27:36 PM PDT 24
Finished Jul 24 05:28:12 PM PDT 24
Peak memory 206856 kb
Host smart-8c4f287a-ded3-4a9c-95d0-275845682b37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36212
68151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.3621268151
Directory /workspace/27.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.2388937595
Short name T1179
Test name
Test status
Simulation time 226533763 ps
CPU time 0.95 seconds
Started Jul 24 05:27:28 PM PDT 24
Finished Jul 24 05:27:29 PM PDT 24
Peak memory 206520 kb
Host smart-4299f2f7-6d37-4d1b-99d9-bd46fcec1f2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23889
37595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.2388937595
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.2382454564
Short name T2732
Test name
Test status
Simulation time 23349251285 ps
CPU time 24.04 seconds
Started Jul 24 05:27:23 PM PDT 24
Finished Jul 24 05:27:47 PM PDT 24
Peak memory 206680 kb
Host smart-bec32540-90e8-4126-b29a-769cfdf1a43e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23824
54564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.2382454564
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.3225415886
Short name T263
Test name
Test status
Simulation time 3291684467 ps
CPU time 3.74 seconds
Started Jul 24 05:27:32 PM PDT 24
Finished Jul 24 05:27:36 PM PDT 24
Peak memory 206612 kb
Host smart-d3cbcce7-7942-426d-afcc-47f5afe9fa91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32254
15886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.3225415886
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.12442991
Short name T741
Test name
Test status
Simulation time 8375720489 ps
CPU time 60.87 seconds
Started Jul 24 05:27:19 PM PDT 24
Finished Jul 24 05:28:20 PM PDT 24
Peak memory 206912 kb
Host smart-fb6f6f24-81cf-4eba-b1a9-2c982bc2db14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12442
991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.12442991
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.2218326170
Short name T1541
Test name
Test status
Simulation time 7776603441 ps
CPU time 74.51 seconds
Started Jul 24 05:27:38 PM PDT 24
Finished Jul 24 05:28:52 PM PDT 24
Peak memory 206972 kb
Host smart-68d1752f-a3bc-451f-8356-8c877e7a932e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2218326170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.2218326170
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.1908820610
Short name T1265
Test name
Test status
Simulation time 250192595 ps
CPU time 0.91 seconds
Started Jul 24 05:27:22 PM PDT 24
Finished Jul 24 05:27:28 PM PDT 24
Peak memory 206600 kb
Host smart-e3a52133-a057-461f-914d-3d657e348022
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1908820610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.1908820610
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.3998162870
Short name T2496
Test name
Test status
Simulation time 209411986 ps
CPU time 0.87 seconds
Started Jul 24 05:27:25 PM PDT 24
Finished Jul 24 05:27:26 PM PDT 24
Peak memory 206612 kb
Host smart-4b22d741-faa5-42fd-a5ec-f7a04276b772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39981
62870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.3998162870
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.3008536557
Short name T2487
Test name
Test status
Simulation time 6280794556 ps
CPU time 176.45 seconds
Started Jul 24 05:27:30 PM PDT 24
Finished Jul 24 05:30:27 PM PDT 24
Peak memory 206912 kb
Host smart-619beb20-e3ef-4b9e-9703-5a69f615aac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30085
36557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.3008536557
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.895849943
Short name T1543
Test name
Test status
Simulation time 4049087555 ps
CPU time 107.14 seconds
Started Jul 24 05:27:33 PM PDT 24
Finished Jul 24 05:29:21 PM PDT 24
Peak memory 206912 kb
Host smart-702a30fc-fc96-4ab7-8fdc-b74f8df78972
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=895849943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.895849943
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.496255099
Short name T1988
Test name
Test status
Simulation time 148157779 ps
CPU time 0.74 seconds
Started Jul 24 05:27:24 PM PDT 24
Finished Jul 24 05:27:25 PM PDT 24
Peak memory 206608 kb
Host smart-64069a36-219c-4d96-9f2f-4d847445c256
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=496255099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.496255099
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.2263160242
Short name T2075
Test name
Test status
Simulation time 139708197 ps
CPU time 0.8 seconds
Started Jul 24 05:27:35 PM PDT 24
Finished Jul 24 05:27:36 PM PDT 24
Peak memory 206524 kb
Host smart-d3c342c9-252d-426c-9473-c29cdae6e335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22631
60242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.2263160242
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.1714726178
Short name T112
Test name
Test status
Simulation time 201931814 ps
CPU time 0.91 seconds
Started Jul 24 05:27:23 PM PDT 24
Finished Jul 24 05:27:24 PM PDT 24
Peak memory 206612 kb
Host smart-03b3c552-0cc0-40d3-bded-1c2ff6d13149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17147
26178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.1714726178
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.2533687023
Short name T1157
Test name
Test status
Simulation time 178703686 ps
CPU time 0.88 seconds
Started Jul 24 05:27:43 PM PDT 24
Finished Jul 24 05:27:44 PM PDT 24
Peak memory 206536 kb
Host smart-aafe364c-ebf9-472e-82b4-a1fa111538ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25336
87023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.2533687023
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.2164997868
Short name T2422
Test name
Test status
Simulation time 213619748 ps
CPU time 0.84 seconds
Started Jul 24 05:27:20 PM PDT 24
Finished Jul 24 05:27:21 PM PDT 24
Peak memory 206520 kb
Host smart-1180deac-b955-4d8a-a810-f991533b867e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21649
97868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.2164997868
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.1867418601
Short name T2065
Test name
Test status
Simulation time 187020897 ps
CPU time 0.79 seconds
Started Jul 24 05:27:26 PM PDT 24
Finished Jul 24 05:27:27 PM PDT 24
Peak memory 206576 kb
Host smart-88e79a9b-9f1c-4067-aa0c-aa753fe482aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18674
18601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.1867418601
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.3492273195
Short name T1469
Test name
Test status
Simulation time 156163558 ps
CPU time 0.76 seconds
Started Jul 24 05:27:35 PM PDT 24
Finished Jul 24 05:27:36 PM PDT 24
Peak memory 206636 kb
Host smart-1ad51e6b-7e4c-4d9b-a6d6-72f8714655dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34922
73195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.3492273195
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.3132353493
Short name T2202
Test name
Test status
Simulation time 274905627 ps
CPU time 0.97 seconds
Started Jul 24 05:27:43 PM PDT 24
Finished Jul 24 05:27:45 PM PDT 24
Peak memory 206616 kb
Host smart-0696b306-26c4-40fd-ac20-5557e6fddde1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3132353493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.3132353493
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.4038796279
Short name T2317
Test name
Test status
Simulation time 154886084 ps
CPU time 0.78 seconds
Started Jul 24 05:27:35 PM PDT 24
Finished Jul 24 05:27:36 PM PDT 24
Peak memory 206612 kb
Host smart-40b8c0f4-f2f9-4914-a5a9-f95371e9044c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40387
96279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.4038796279
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.2251267981
Short name T2246
Test name
Test status
Simulation time 59925392 ps
CPU time 0.67 seconds
Started Jul 24 05:27:28 PM PDT 24
Finished Jul 24 05:27:29 PM PDT 24
Peak memory 206420 kb
Host smart-9b478572-75bd-4065-a423-57a7400c68c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22512
67981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.2251267981
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.4115055961
Short name T241
Test name
Test status
Simulation time 17438807439 ps
CPU time 39.07 seconds
Started Jul 24 05:27:43 PM PDT 24
Finished Jul 24 05:28:23 PM PDT 24
Peak memory 206884 kb
Host smart-5b49e6e0-558f-474d-8a3d-b3ac50f62108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41150
55961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.4115055961
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.1716923931
Short name T366
Test name
Test status
Simulation time 171888553 ps
CPU time 0.77 seconds
Started Jul 24 05:27:18 PM PDT 24
Finished Jul 24 05:27:19 PM PDT 24
Peak memory 206588 kb
Host smart-fec4e108-cf7d-4f4c-8036-5e01b773785e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17169
23931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.1716923931
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.2422402042
Short name T1218
Test name
Test status
Simulation time 241896721 ps
CPU time 0.89 seconds
Started Jul 24 05:27:31 PM PDT 24
Finished Jul 24 05:27:33 PM PDT 24
Peak memory 206644 kb
Host smart-721d0ee0-157e-42ec-849f-08a2e486a4f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24224
02042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.2422402042
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.3459619413
Short name T295
Test name
Test status
Simulation time 160049772 ps
CPU time 0.78 seconds
Started Jul 24 05:27:20 PM PDT 24
Finished Jul 24 05:27:21 PM PDT 24
Peak memory 206504 kb
Host smart-384bf0b9-af69-465f-a43d-7ea5f706a3b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34596
19413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.3459619413
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.673323505
Short name T743
Test name
Test status
Simulation time 161371973 ps
CPU time 0.8 seconds
Started Jul 24 05:27:44 PM PDT 24
Finished Jul 24 05:27:45 PM PDT 24
Peak memory 206572 kb
Host smart-ffe0c9d0-5fc7-4477-bb14-6ed1fb5b1f13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67332
3505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.673323505
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.1379898525
Short name T764
Test name
Test status
Simulation time 154678161 ps
CPU time 0.77 seconds
Started Jul 24 05:27:18 PM PDT 24
Finished Jul 24 05:27:19 PM PDT 24
Peak memory 206604 kb
Host smart-c69a13ca-8e9a-4812-8ff8-f5adb42ab1c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13798
98525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.1379898525
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.1701650277
Short name T1608
Test name
Test status
Simulation time 194877522 ps
CPU time 0.78 seconds
Started Jul 24 05:27:25 PM PDT 24
Finished Jul 24 05:27:26 PM PDT 24
Peak memory 206536 kb
Host smart-b1646278-71e7-4c1c-9a10-c3035c5142a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17016
50277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.1701650277
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.521717728
Short name T1640
Test name
Test status
Simulation time 155408650 ps
CPU time 0.83 seconds
Started Jul 24 05:27:29 PM PDT 24
Finished Jul 24 05:27:30 PM PDT 24
Peak memory 206644 kb
Host smart-d475a046-030c-4f5d-885a-5d743d941e49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52171
7728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.521717728
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.849545434
Short name T2310
Test name
Test status
Simulation time 272781638 ps
CPU time 0.95 seconds
Started Jul 24 05:27:24 PM PDT 24
Finished Jul 24 05:27:26 PM PDT 24
Peak memory 206596 kb
Host smart-abc28741-d965-47f8-8423-997aba4f9a86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84954
5434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.849545434
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.3661081877
Short name T2309
Test name
Test status
Simulation time 5775337821 ps
CPU time 45.89 seconds
Started Jul 24 05:27:25 PM PDT 24
Finished Jul 24 05:28:11 PM PDT 24
Peak memory 206780 kb
Host smart-e1e4e262-9875-4e17-ba68-e8011eb526d2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3661081877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.3661081877
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.2585873972
Short name T140
Test name
Test status
Simulation time 196307212 ps
CPU time 0.8 seconds
Started Jul 24 05:27:39 PM PDT 24
Finished Jul 24 05:27:40 PM PDT 24
Peak memory 206588 kb
Host smart-fdb15dcf-48cf-453d-b76f-030c620336c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25858
73972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.2585873972
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.3363889055
Short name T301
Test name
Test status
Simulation time 185640157 ps
CPU time 0.78 seconds
Started Jul 24 05:27:34 PM PDT 24
Finished Jul 24 05:27:34 PM PDT 24
Peak memory 206592 kb
Host smart-f40a8867-b8ed-4358-a029-3d62984c6f25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33638
89055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.3363889055
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.134277734
Short name T2566
Test name
Test status
Simulation time 257151011 ps
CPU time 0.92 seconds
Started Jul 24 05:27:18 PM PDT 24
Finished Jul 24 05:27:19 PM PDT 24
Peak memory 206652 kb
Host smart-1f095475-9e63-40b7-8666-8839528ebff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13427
7734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.134277734
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.780023356
Short name T2069
Test name
Test status
Simulation time 4752602802 ps
CPU time 131.11 seconds
Started Jul 24 05:27:27 PM PDT 24
Finished Jul 24 05:29:38 PM PDT 24
Peak memory 206864 kb
Host smart-9be700b0-df06-4271-abc3-79b5e4368def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78002
3356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.780023356
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.4124459424
Short name T1315
Test name
Test status
Simulation time 54170335 ps
CPU time 0.65 seconds
Started Jul 24 05:27:27 PM PDT 24
Finished Jul 24 05:27:28 PM PDT 24
Peak memory 206668 kb
Host smart-df3f1cc5-4275-4782-8cdb-1893a0dc26ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4124459424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.4124459424
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.481675727
Short name T2721
Test name
Test status
Simulation time 4368589990 ps
CPU time 4.63 seconds
Started Jul 24 05:27:19 PM PDT 24
Finished Jul 24 05:27:24 PM PDT 24
Peak memory 206808 kb
Host smart-8fe21d88-67d6-4a5c-8fa3-f0ded8eda354
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=481675727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.481675727
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.773992042
Short name T739
Test name
Test status
Simulation time 13412966740 ps
CPU time 15.33 seconds
Started Jul 24 05:27:48 PM PDT 24
Finished Jul 24 05:28:03 PM PDT 24
Peak memory 206980 kb
Host smart-e34af428-8d37-4d4c-b1fc-1ef57d6a28dc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=773992042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.773992042
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.3472864970
Short name T1254
Test name
Test status
Simulation time 23386045021 ps
CPU time 22.07 seconds
Started Jul 24 05:27:38 PM PDT 24
Finished Jul 24 05:28:01 PM PDT 24
Peak memory 206916 kb
Host smart-df624189-c7ed-464f-a8b9-f9c525d1733a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3472864970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.3472864970
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.3667455448
Short name T2217
Test name
Test status
Simulation time 176489345 ps
CPU time 0.8 seconds
Started Jul 24 05:27:44 PM PDT 24
Finished Jul 24 05:27:45 PM PDT 24
Peak memory 206600 kb
Host smart-5bd51952-f7ab-4ac4-b30f-134bdee3caef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36674
55448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.3667455448
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.100875271
Short name T1761
Test name
Test status
Simulation time 226024166 ps
CPU time 0.87 seconds
Started Jul 24 05:27:39 PM PDT 24
Finished Jul 24 05:27:40 PM PDT 24
Peak memory 206628 kb
Host smart-d2bd377c-3019-4551-ab41-3c04869922e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10087
5271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.100875271
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.1575147320
Short name T2535
Test name
Test status
Simulation time 200786650 ps
CPU time 0.83 seconds
Started Jul 24 05:27:34 PM PDT 24
Finished Jul 24 05:27:35 PM PDT 24
Peak memory 206644 kb
Host smart-90a82dae-847f-4fbc-b607-819125e32962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15751
47320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.1575147320
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.2383081408
Short name T1128
Test name
Test status
Simulation time 738082339 ps
CPU time 1.79 seconds
Started Jul 24 05:27:41 PM PDT 24
Finished Jul 24 05:27:43 PM PDT 24
Peak memory 206756 kb
Host smart-c8c2e0f2-eb6c-4218-bb88-4c3bfb5157b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23830
81408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.2383081408
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.1079689045
Short name T542
Test name
Test status
Simulation time 325243775 ps
CPU time 1.13 seconds
Started Jul 24 05:27:39 PM PDT 24
Finished Jul 24 05:27:40 PM PDT 24
Peak memory 206548 kb
Host smart-77efd90a-0780-4066-bcd1-5608333dc07e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10796
89045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.1079689045
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.1943108025
Short name T2598
Test name
Test status
Simulation time 150756388 ps
CPU time 0.77 seconds
Started Jul 24 05:27:32 PM PDT 24
Finished Jul 24 05:27:33 PM PDT 24
Peak memory 206576 kb
Host smart-41f2acce-09d3-47b2-bd36-75e0c4c06695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19431
08025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.1943108025
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.2522563857
Short name T2557
Test name
Test status
Simulation time 60201471 ps
CPU time 0.68 seconds
Started Jul 24 05:27:36 PM PDT 24
Finished Jul 24 05:27:37 PM PDT 24
Peak memory 206608 kb
Host smart-aa761a07-dfd8-41b9-b094-252b91b7ca86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25225
63857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.2522563857
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.728788640
Short name T1813
Test name
Test status
Simulation time 978948755 ps
CPU time 2.24 seconds
Started Jul 24 05:27:34 PM PDT 24
Finished Jul 24 05:27:37 PM PDT 24
Peak memory 206736 kb
Host smart-1f27fec8-e1dc-4c09-b671-c1c54441c131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72878
8640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.728788640
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.2126341647
Short name T700
Test name
Test status
Simulation time 206485327 ps
CPU time 1.38 seconds
Started Jul 24 05:27:55 PM PDT 24
Finished Jul 24 05:27:57 PM PDT 24
Peak memory 206780 kb
Host smart-c17b5949-7451-480e-8c06-ff4a736b1136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21263
41647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.2126341647
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.131685170
Short name T2514
Test name
Test status
Simulation time 214485389 ps
CPU time 0.88 seconds
Started Jul 24 05:27:51 PM PDT 24
Finished Jul 24 05:27:52 PM PDT 24
Peak memory 206652 kb
Host smart-beccb953-75b8-4326-bdb9-f84e652d563e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13168
5170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.131685170
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.235424335
Short name T1766
Test name
Test status
Simulation time 192064017 ps
CPU time 0.82 seconds
Started Jul 24 05:27:37 PM PDT 24
Finished Jul 24 05:27:38 PM PDT 24
Peak memory 206592 kb
Host smart-b0d19975-b0ed-49e6-9d52-51645ecb8729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23542
4335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.235424335
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.3884274
Short name T200
Test name
Test status
Simulation time 209340834 ps
CPU time 0.84 seconds
Started Jul 24 05:27:44 PM PDT 24
Finished Jul 24 05:27:46 PM PDT 24
Peak memory 206568 kb
Host smart-ec86717f-3510-432f-8e9a-4135c4b1e1a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38842
74 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.3884274
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.3686880972
Short name T67
Test name
Test status
Simulation time 5693011237 ps
CPU time 162.05 seconds
Started Jul 24 05:27:29 PM PDT 24
Finished Jul 24 05:30:11 PM PDT 24
Peak memory 206944 kb
Host smart-edb0c326-5265-4f21-86e3-4718a7623bef
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3686880972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.3686880972
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_iso_retraction.3287116028
Short name T1780
Test name
Test status
Simulation time 11878806872 ps
CPU time 101.58 seconds
Started Jul 24 05:27:49 PM PDT 24
Finished Jul 24 05:29:30 PM PDT 24
Peak memory 206816 kb
Host smart-16d7b1bb-45cc-434c-bee9-dc372f83cb84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32871
16028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_iso_retraction.3287116028
Directory /workspace/28.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.1094986369
Short name T100
Test name
Test status
Simulation time 162359580 ps
CPU time 0.8 seconds
Started Jul 24 05:27:49 PM PDT 24
Finished Jul 24 05:27:50 PM PDT 24
Peak memory 206516 kb
Host smart-5294b733-0be2-403e-bc3b-deb0d4d69e6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10949
86369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.1094986369
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.3869642999
Short name T179
Test name
Test status
Simulation time 23282530508 ps
CPU time 26.85 seconds
Started Jul 24 05:27:38 PM PDT 24
Finished Jul 24 05:28:05 PM PDT 24
Peak memory 206712 kb
Host smart-52780a4f-53a9-4e25-b125-aa84174f518e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38696
42999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.3869642999
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.2354787618
Short name T1810
Test name
Test status
Simulation time 3357251958 ps
CPU time 4.44 seconds
Started Jul 24 05:27:32 PM PDT 24
Finished Jul 24 05:27:36 PM PDT 24
Peak memory 206628 kb
Host smart-a24cbf5c-dee1-47a1-a5f0-596c3b9a8011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23547
87618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.2354787618
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.608444230
Short name T811
Test name
Test status
Simulation time 11370852981 ps
CPU time 109.81 seconds
Started Jul 24 05:27:29 PM PDT 24
Finished Jul 24 05:29:19 PM PDT 24
Peak memory 206932 kb
Host smart-4bb7ed5e-b63e-45b9-90e1-c8c206358fe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60844
4230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.608444230
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.2128692236
Short name T411
Test name
Test status
Simulation time 4447445596 ps
CPU time 32.79 seconds
Started Jul 24 05:27:38 PM PDT 24
Finished Jul 24 05:28:11 PM PDT 24
Peak memory 206884 kb
Host smart-822dd298-6dfc-4937-bebc-b6654def37c9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2128692236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.2128692236
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.312207047
Short name T2287
Test name
Test status
Simulation time 254689405 ps
CPU time 0.94 seconds
Started Jul 24 05:27:29 PM PDT 24
Finished Jul 24 05:27:31 PM PDT 24
Peak memory 206648 kb
Host smart-5713a488-0ba5-4a50-a06a-b28a28138954
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=312207047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.312207047
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.2523542550
Short name T1077
Test name
Test status
Simulation time 235467370 ps
CPU time 0.91 seconds
Started Jul 24 05:27:28 PM PDT 24
Finished Jul 24 05:27:29 PM PDT 24
Peak memory 206600 kb
Host smart-88e06447-3cdb-46a4-82d9-83afec29c855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25235
42550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.2523542550
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.2771865526
Short name T1815
Test name
Test status
Simulation time 3760249946 ps
CPU time 35.17 seconds
Started Jul 24 05:27:19 PM PDT 24
Finished Jul 24 05:27:55 PM PDT 24
Peak memory 206872 kb
Host smart-d61ae30b-b48f-49cb-8a86-ff531d8d0aa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27718
65526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.2771865526
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.4067722700
Short name T2361
Test name
Test status
Simulation time 5577862761 ps
CPU time 49.72 seconds
Started Jul 24 05:27:40 PM PDT 24
Finished Jul 24 05:28:30 PM PDT 24
Peak memory 206976 kb
Host smart-631e2bb3-5fd6-4b09-88e3-75ba0297e865
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4067722700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.4067722700
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.833345635
Short name T298
Test name
Test status
Simulation time 160747805 ps
CPU time 0.84 seconds
Started Jul 24 05:27:33 PM PDT 24
Finished Jul 24 05:27:34 PM PDT 24
Peak memory 206560 kb
Host smart-ff6a4511-4949-4aae-95f4-8582f8a05564
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=833345635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.833345635
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.3394337927
Short name T2594
Test name
Test status
Simulation time 145228174 ps
CPU time 0.78 seconds
Started Jul 24 05:27:39 PM PDT 24
Finished Jul 24 05:27:39 PM PDT 24
Peak memory 206604 kb
Host smart-01d9fa6a-06a2-49a7-b311-804c965e8177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33943
37927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.3394337927
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.2031052909
Short name T1657
Test name
Test status
Simulation time 222724813 ps
CPU time 0.82 seconds
Started Jul 24 05:27:27 PM PDT 24
Finished Jul 24 05:27:28 PM PDT 24
Peak memory 206600 kb
Host smart-18e59dc6-2bb7-488b-b3a2-404b07f576e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20310
52909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.2031052909
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.1170932804
Short name T1437
Test name
Test status
Simulation time 159904099 ps
CPU time 0.81 seconds
Started Jul 24 05:27:40 PM PDT 24
Finished Jul 24 05:27:41 PM PDT 24
Peak memory 206584 kb
Host smart-0f92e76d-b3cc-434c-bfba-a42bc1419c34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11709
32804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.1170932804
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.1511519436
Short name T1365
Test name
Test status
Simulation time 167207882 ps
CPU time 0.85 seconds
Started Jul 24 05:27:38 PM PDT 24
Finished Jul 24 05:27:39 PM PDT 24
Peak memory 206600 kb
Host smart-dcc36118-645b-4ebd-a440-7a9657930e1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15115
19436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.1511519436
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.4084836505
Short name T569
Test name
Test status
Simulation time 192256773 ps
CPU time 0.78 seconds
Started Jul 24 05:27:25 PM PDT 24
Finished Jul 24 05:27:26 PM PDT 24
Peak memory 206584 kb
Host smart-bdfc10b9-c415-43aa-86f7-f708a9c72997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40848
36505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.4084836505
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.1460590941
Short name T1733
Test name
Test status
Simulation time 168196869 ps
CPU time 0.79 seconds
Started Jul 24 05:27:43 PM PDT 24
Finished Jul 24 05:27:44 PM PDT 24
Peak memory 206512 kb
Host smart-42ac3793-c0ff-4521-bd22-9ee1da9d6a8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14605
90941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.1460590941
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.3597472804
Short name T1089
Test name
Test status
Simulation time 236073264 ps
CPU time 1.01 seconds
Started Jul 24 05:27:37 PM PDT 24
Finished Jul 24 05:27:38 PM PDT 24
Peak memory 206520 kb
Host smart-908384ff-42e3-4eb3-8905-869cfcacb806
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3597472804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.3597472804
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.3833897259
Short name T2611
Test name
Test status
Simulation time 148839849 ps
CPU time 0.73 seconds
Started Jul 24 05:27:51 PM PDT 24
Finished Jul 24 05:27:52 PM PDT 24
Peak memory 206728 kb
Host smart-0913f9e6-b8dc-4b40-b4cc-93538809309c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38338
97259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.3833897259
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.1456075928
Short name T577
Test name
Test status
Simulation time 66234663 ps
CPU time 0.65 seconds
Started Jul 24 05:27:45 PM PDT 24
Finished Jul 24 05:27:46 PM PDT 24
Peak memory 206572 kb
Host smart-dac3c44b-621b-46f6-bb8f-1df2def65557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14560
75928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.1456075928
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.1685033751
Short name T1523
Test name
Test status
Simulation time 8356980542 ps
CPU time 18.21 seconds
Started Jul 24 05:27:43 PM PDT 24
Finished Jul 24 05:28:02 PM PDT 24
Peak memory 215180 kb
Host smart-54f44430-bf5f-4956-bfad-e13f1ff0dbc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16850
33751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.1685033751
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.3119243955
Short name T1429
Test name
Test status
Simulation time 159373168 ps
CPU time 0.83 seconds
Started Jul 24 05:27:41 PM PDT 24
Finished Jul 24 05:27:42 PM PDT 24
Peak memory 206552 kb
Host smart-b03dc8b4-0a88-478f-8310-c9a7e5989d14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31192
43955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.3119243955
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.1759071626
Short name T1159
Test name
Test status
Simulation time 177610068 ps
CPU time 0.78 seconds
Started Jul 24 05:27:21 PM PDT 24
Finished Jul 24 05:27:22 PM PDT 24
Peak memory 206384 kb
Host smart-3f28af2c-43f9-48b5-9c76-96b7c23f451c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17590
71626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.1759071626
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.3461921663
Short name T735
Test name
Test status
Simulation time 234002212 ps
CPU time 0.86 seconds
Started Jul 24 05:27:20 PM PDT 24
Finished Jul 24 05:27:21 PM PDT 24
Peak memory 206556 kb
Host smart-0837ee31-b14b-4f8b-a4b1-68f93d0903c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34619
21663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.3461921663
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.104253456
Short name T1936
Test name
Test status
Simulation time 178542764 ps
CPU time 0.83 seconds
Started Jul 24 05:27:42 PM PDT 24
Finished Jul 24 05:27:43 PM PDT 24
Peak memory 206556 kb
Host smart-518ba545-4baa-4306-84bf-c3a771ed006a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10425
3456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.104253456
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.1382366236
Short name T2699
Test name
Test status
Simulation time 150285208 ps
CPU time 0.75 seconds
Started Jul 24 05:27:58 PM PDT 24
Finished Jul 24 05:27:59 PM PDT 24
Peak memory 206580 kb
Host smart-7787ddec-165c-44a3-81e4-661453e814d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13823
66236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.1382366236
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.836468327
Short name T601
Test name
Test status
Simulation time 159773339 ps
CPU time 0.75 seconds
Started Jul 24 05:27:49 PM PDT 24
Finished Jul 24 05:27:50 PM PDT 24
Peak memory 206580 kb
Host smart-7b921ab8-a219-41f0-8772-cdb24e3892ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83646
8327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.836468327
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.1149991725
Short name T348
Test name
Test status
Simulation time 148586205 ps
CPU time 0.77 seconds
Started Jul 24 05:27:36 PM PDT 24
Finished Jul 24 05:27:37 PM PDT 24
Peak memory 206580 kb
Host smart-5ff27b3d-75c3-468c-80a7-39bdb0a7ec62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11499
91725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.1149991725
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.157936264
Short name T732
Test name
Test status
Simulation time 203453919 ps
CPU time 0.89 seconds
Started Jul 24 05:27:38 PM PDT 24
Finished Jul 24 05:27:39 PM PDT 24
Peak memory 206532 kb
Host smart-20426672-b9a5-4c5f-908d-7cc5747be297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15793
6264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.157936264
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.57284798
Short name T660
Test name
Test status
Simulation time 3774210091 ps
CPU time 26.07 seconds
Started Jul 24 05:27:44 PM PDT 24
Finished Jul 24 05:28:10 PM PDT 24
Peak memory 207004 kb
Host smart-de2fa756-74c7-4885-8cfc-5f98164deb21
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=57284798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.57284798
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.1325679137
Short name T2601
Test name
Test status
Simulation time 162853152 ps
CPU time 0.81 seconds
Started Jul 24 05:27:47 PM PDT 24
Finished Jul 24 05:27:48 PM PDT 24
Peak memory 206592 kb
Host smart-3e3c5276-cbaf-44ea-b69d-7903d9f0f294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13256
79137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.1325679137
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.3869553602
Short name T1623
Test name
Test status
Simulation time 195127151 ps
CPU time 0.83 seconds
Started Jul 24 05:27:30 PM PDT 24
Finished Jul 24 05:27:31 PM PDT 24
Peak memory 206580 kb
Host smart-75cd2a32-ef21-470d-9212-18430f8f8c00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38695
53602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.3869553602
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.1276285577
Short name T2731
Test name
Test status
Simulation time 1189316479 ps
CPU time 2.63 seconds
Started Jul 24 05:27:30 PM PDT 24
Finished Jul 24 05:27:33 PM PDT 24
Peak memory 206820 kb
Host smart-6587759a-ac13-4988-a6c7-7152cc6fc1b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12762
85577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.1276285577
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.3409438617
Short name T2549
Test name
Test status
Simulation time 4189852158 ps
CPU time 114.54 seconds
Started Jul 24 05:27:39 PM PDT 24
Finished Jul 24 05:29:34 PM PDT 24
Peak memory 206784 kb
Host smart-f2c245ea-e38d-4a0d-ad30-de6d999a36be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34094
38617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.3409438617
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.1814244583
Short name T1729
Test name
Test status
Simulation time 40631247 ps
CPU time 0.66 seconds
Started Jul 24 05:27:44 PM PDT 24
Finished Jul 24 05:27:45 PM PDT 24
Peak memory 206408 kb
Host smart-8c72bd5f-16f7-453b-a007-a40beebcc637
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1814244583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.1814244583
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.359572389
Short name T2298
Test name
Test status
Simulation time 3854631919 ps
CPU time 4.25 seconds
Started Jul 24 05:27:26 PM PDT 24
Finished Jul 24 05:27:30 PM PDT 24
Peak memory 206712 kb
Host smart-7ee40e07-1122-44aa-ad74-282cf96c9781
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=359572389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.359572389
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.890301705
Short name T2005
Test name
Test status
Simulation time 13352018774 ps
CPU time 12.45 seconds
Started Jul 24 05:27:48 PM PDT 24
Finished Jul 24 05:28:01 PM PDT 24
Peak memory 206716 kb
Host smart-25b50d03-a3af-4177-9841-34f58686c313
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=890301705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.890301705
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.1898242502
Short name T1770
Test name
Test status
Simulation time 23351731189 ps
CPU time 24 seconds
Started Jul 24 05:27:37 PM PDT 24
Finished Jul 24 05:28:01 PM PDT 24
Peak memory 206768 kb
Host smart-e8228587-36a6-46c0-8fe4-d4d452382bdb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1898242502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.1898242502
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.249991736
Short name T2249
Test name
Test status
Simulation time 156969341 ps
CPU time 0.75 seconds
Started Jul 24 05:27:45 PM PDT 24
Finished Jul 24 05:27:46 PM PDT 24
Peak memory 206580 kb
Host smart-1e276bbd-c6b4-44f7-957a-55424e780673
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24999
1736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.249991736
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.126219170
Short name T420
Test name
Test status
Simulation time 170335755 ps
CPU time 0.82 seconds
Started Jul 24 05:27:45 PM PDT 24
Finished Jul 24 05:27:46 PM PDT 24
Peak memory 206580 kb
Host smart-ba755650-99d7-4dc4-b0cc-cc7d3f3ef954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12621
9170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.126219170
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.3945244393
Short name T1669
Test name
Test status
Simulation time 455537572 ps
CPU time 1.48 seconds
Started Jul 24 05:27:44 PM PDT 24
Finished Jul 24 05:27:46 PM PDT 24
Peak memory 206588 kb
Host smart-dfd7bb11-10c1-4d0c-a750-1dfb68fa0ab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39452
44393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.3945244393
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.2382201056
Short name T796
Test name
Test status
Simulation time 702542603 ps
CPU time 1.7 seconds
Started Jul 24 05:27:34 PM PDT 24
Finished Jul 24 05:27:35 PM PDT 24
Peak memory 206808 kb
Host smart-57be3156-bbf1-4328-be37-1bec3be39aa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23822
01056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.2382201056
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.2183934744
Short name T2554
Test name
Test status
Simulation time 11692238249 ps
CPU time 22.63 seconds
Started Jul 24 05:27:49 PM PDT 24
Finished Jul 24 05:28:12 PM PDT 24
Peak memory 206860 kb
Host smart-7a0ade3a-3e95-4ec3-bf95-29b98190d6ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21839
34744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.2183934744
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.1010817962
Short name T2488
Test name
Test status
Simulation time 385812015 ps
CPU time 1.22 seconds
Started Jul 24 05:27:49 PM PDT 24
Finished Jul 24 05:27:50 PM PDT 24
Peak memory 206584 kb
Host smart-fd573190-c092-4189-abeb-0ed3e7a4d44e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10108
17962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.1010817962
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.2515116541
Short name T1164
Test name
Test status
Simulation time 193991663 ps
CPU time 0.79 seconds
Started Jul 24 05:27:53 PM PDT 24
Finished Jul 24 05:27:54 PM PDT 24
Peak memory 206580 kb
Host smart-31100425-2e61-421c-b541-9ff39e9d931a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25151
16541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.2515116541
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.1029553593
Short name T1587
Test name
Test status
Simulation time 78464516 ps
CPU time 0.67 seconds
Started Jul 24 05:27:50 PM PDT 24
Finished Jul 24 05:27:51 PM PDT 24
Peak memory 206588 kb
Host smart-db35cd98-d814-454f-b7ef-bd0d2342ff74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10295
53593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.1029553593
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.3133479176
Short name T2250
Test name
Test status
Simulation time 304899667 ps
CPU time 2.26 seconds
Started Jul 24 05:27:50 PM PDT 24
Finished Jul 24 05:27:53 PM PDT 24
Peak memory 206928 kb
Host smart-69f448e9-b639-4cf9-a9bc-e204624deb6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31334
79176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.3133479176
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.4115828119
Short name T1870
Test name
Test status
Simulation time 218701638 ps
CPU time 0.85 seconds
Started Jul 24 05:27:41 PM PDT 24
Finished Jul 24 05:27:42 PM PDT 24
Peak memory 206744 kb
Host smart-aa7ecb8d-81c0-4eeb-a263-9cdfd5c9d067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41158
28119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.4115828119
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.2239972297
Short name T2679
Test name
Test status
Simulation time 138985190 ps
CPU time 0.75 seconds
Started Jul 24 05:27:49 PM PDT 24
Finished Jul 24 05:27:50 PM PDT 24
Peak memory 206552 kb
Host smart-83dd12f0-a05e-4860-ab9b-94facc02b720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22399
72297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.2239972297
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.2262184782
Short name T814
Test name
Test status
Simulation time 192342420 ps
CPU time 0.87 seconds
Started Jul 24 05:27:41 PM PDT 24
Finished Jul 24 05:27:42 PM PDT 24
Peak memory 206540 kb
Host smart-3c6de106-dc84-4a55-bd08-04297be5fb16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22621
84782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.2262184782
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_invalid_sync.1981187445
Short name T2567
Test name
Test status
Simulation time 7391000735 ps
CPU time 71.45 seconds
Started Jul 24 05:27:44 PM PDT 24
Finished Jul 24 05:28:55 PM PDT 24
Peak memory 206980 kb
Host smart-399bc97e-6d8c-4c23-aae2-f508e4603273
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1981187445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.1981187445
Directory /workspace/29.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.1941146994
Short name T1983
Test name
Test status
Simulation time 196838998 ps
CPU time 0.83 seconds
Started Jul 24 05:27:48 PM PDT 24
Finished Jul 24 05:27:49 PM PDT 24
Peak memory 206576 kb
Host smart-06e569ab-5fbb-4493-a306-9502ee626588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19411
46994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.1941146994
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.2530108097
Short name T946
Test name
Test status
Simulation time 23353803331 ps
CPU time 23.51 seconds
Started Jul 24 05:27:58 PM PDT 24
Finished Jul 24 05:28:22 PM PDT 24
Peak memory 206680 kb
Host smart-89fdd904-5a7a-41b1-9824-faa158327aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25301
08097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.2530108097
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.1910502831
Short name T566
Test name
Test status
Simulation time 3389096721 ps
CPU time 4.98 seconds
Started Jul 24 05:27:47 PM PDT 24
Finished Jul 24 05:27:52 PM PDT 24
Peak memory 206704 kb
Host smart-0cf25110-591d-485e-a047-9f2405d78051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19105
02831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.1910502831
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.3245223585
Short name T1949
Test name
Test status
Simulation time 13255133220 ps
CPU time 360.66 seconds
Started Jul 24 05:27:46 PM PDT 24
Finished Jul 24 05:33:47 PM PDT 24
Peak memory 206948 kb
Host smart-39a3b19e-b3a2-447e-95f8-219ac1729db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32452
23585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.3245223585
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.221468156
Short name T1735
Test name
Test status
Simulation time 4838609508 ps
CPU time 32.08 seconds
Started Jul 24 05:27:49 PM PDT 24
Finished Jul 24 05:28:21 PM PDT 24
Peak memory 206756 kb
Host smart-00c6b14d-7c17-4e68-99c1-90af36f3ea87
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=221468156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.221468156
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.3412690533
Short name T432
Test name
Test status
Simulation time 250892757 ps
CPU time 1 seconds
Started Jul 24 05:27:51 PM PDT 24
Finished Jul 24 05:27:52 PM PDT 24
Peak memory 206604 kb
Host smart-8c23c07b-4feb-42ed-ae62-2f5de0b768b2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3412690533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.3412690533
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.1162758836
Short name T2068
Test name
Test status
Simulation time 195002782 ps
CPU time 0.82 seconds
Started Jul 24 05:27:42 PM PDT 24
Finished Jul 24 05:27:43 PM PDT 24
Peak memory 206512 kb
Host smart-6eedeae0-323d-4722-a177-01f4f45655d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11627
58836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.1162758836
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.263492775
Short name T853
Test name
Test status
Simulation time 3355512417 ps
CPU time 87.09 seconds
Started Jul 24 05:27:54 PM PDT 24
Finished Jul 24 05:29:22 PM PDT 24
Peak memory 206916 kb
Host smart-ee953572-98cb-45e8-829e-a6a39edc500e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26349
2775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.263492775
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.3116397022
Short name T1935
Test name
Test status
Simulation time 3921495661 ps
CPU time 29.13 seconds
Started Jul 24 05:27:56 PM PDT 24
Finished Jul 24 05:28:25 PM PDT 24
Peak memory 206756 kb
Host smart-ab0ecd70-829f-4f28-a335-d392f5e709c9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3116397022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.3116397022
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.2966532749
Short name T1244
Test name
Test status
Simulation time 166329729 ps
CPU time 0.81 seconds
Started Jul 24 05:28:08 PM PDT 24
Finished Jul 24 05:28:09 PM PDT 24
Peak memory 206520 kb
Host smart-9a55aa0f-a5ce-4cff-8bb1-9e571e2319ef
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2966532749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.2966532749
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.1483505169
Short name T710
Test name
Test status
Simulation time 141333224 ps
CPU time 0.77 seconds
Started Jul 24 05:27:53 PM PDT 24
Finished Jul 24 05:27:54 PM PDT 24
Peak memory 206604 kb
Host smart-aaf6ec79-33fc-4cba-93e7-73278bf3d882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14835
05169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.1483505169
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.2640519506
Short name T119
Test name
Test status
Simulation time 194256041 ps
CPU time 0.79 seconds
Started Jul 24 05:27:47 PM PDT 24
Finished Jul 24 05:27:48 PM PDT 24
Peak memory 206596 kb
Host smart-a010c029-7522-4283-a094-c36df941b9ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26405
19506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.2640519506
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.4021008005
Short name T930
Test name
Test status
Simulation time 191177116 ps
CPU time 0.82 seconds
Started Jul 24 05:27:47 PM PDT 24
Finished Jul 24 05:27:48 PM PDT 24
Peak memory 206388 kb
Host smart-d1e50d98-8790-4666-a6c2-b7e26eeebcc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40210
08005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.4021008005
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.2767422855
Short name T1573
Test name
Test status
Simulation time 165237829 ps
CPU time 0.76 seconds
Started Jul 24 05:27:39 PM PDT 24
Finished Jul 24 05:27:40 PM PDT 24
Peak memory 206508 kb
Host smart-73302509-e0b9-49b6-bbe7-02a0b0b47d7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27674
22855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.2767422855
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.2936946033
Short name T1716
Test name
Test status
Simulation time 187827112 ps
CPU time 0.78 seconds
Started Jul 24 05:27:49 PM PDT 24
Finished Jul 24 05:27:50 PM PDT 24
Peak memory 206600 kb
Host smart-4d780378-c58b-4ab8-b160-cbc038bd03ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29369
46033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.2936946033
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.1901965390
Short name T167
Test name
Test status
Simulation time 151294923 ps
CPU time 0.78 seconds
Started Jul 24 05:27:59 PM PDT 24
Finished Jul 24 05:28:00 PM PDT 24
Peak memory 206528 kb
Host smart-2bbd52d0-2c60-41b3-a69e-f1ec2aef98ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19019
65390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.1901965390
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.1888212613
Short name T2271
Test name
Test status
Simulation time 259842350 ps
CPU time 0.94 seconds
Started Jul 24 05:27:47 PM PDT 24
Finished Jul 24 05:27:48 PM PDT 24
Peak memory 206640 kb
Host smart-a97d56b0-6a8d-4729-a8c9-cb3db4350a79
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1888212613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.1888212613
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.2114752928
Short name T667
Test name
Test status
Simulation time 141647318 ps
CPU time 0.74 seconds
Started Jul 24 05:27:44 PM PDT 24
Finished Jul 24 05:27:45 PM PDT 24
Peak memory 206616 kb
Host smart-004448f3-5108-4313-ba2f-72c4bb957086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21147
52928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.2114752928
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.2527068292
Short name T727
Test name
Test status
Simulation time 45087400 ps
CPU time 0.63 seconds
Started Jul 24 05:27:56 PM PDT 24
Finished Jul 24 05:27:57 PM PDT 24
Peak memory 206544 kb
Host smart-a1006964-4b39-4cf4-b597-fb293a9ffd9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25270
68292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.2527068292
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.657494105
Short name T2457
Test name
Test status
Simulation time 14167042027 ps
CPU time 32.38 seconds
Started Jul 24 05:27:44 PM PDT 24
Finished Jul 24 05:28:17 PM PDT 24
Peak memory 215136 kb
Host smart-e24cf5d4-0eda-42ff-abfd-52468894a9fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65749
4105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.657494105
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.3167763607
Short name T1501
Test name
Test status
Simulation time 199553818 ps
CPU time 0.85 seconds
Started Jul 24 05:27:45 PM PDT 24
Finished Jul 24 05:27:46 PM PDT 24
Peak memory 206564 kb
Host smart-41170274-2aff-4439-a1dc-93a939883694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31677
63607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.3167763607
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.393016044
Short name T1918
Test name
Test status
Simulation time 219544047 ps
CPU time 0.85 seconds
Started Jul 24 05:27:48 PM PDT 24
Finished Jul 24 05:27:50 PM PDT 24
Peak memory 206596 kb
Host smart-bc4a6c2f-d071-485c-9a1c-e80f8e87c6de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39301
6044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.393016044
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.2411133649
Short name T1086
Test name
Test status
Simulation time 237291158 ps
CPU time 0.89 seconds
Started Jul 24 05:27:55 PM PDT 24
Finished Jul 24 05:27:56 PM PDT 24
Peak memory 206504 kb
Host smart-77a94ab8-24fd-4658-9853-1afa185f5871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24111
33649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.2411133649
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.1109885980
Short name T2209
Test name
Test status
Simulation time 196003242 ps
CPU time 0.88 seconds
Started Jul 24 05:27:40 PM PDT 24
Finished Jul 24 05:27:41 PM PDT 24
Peak memory 206556 kb
Host smart-ee6a98d7-b8de-40a3-9caa-276060cc88c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11098
85980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.1109885980
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.722727643
Short name T1018
Test name
Test status
Simulation time 141472529 ps
CPU time 0.73 seconds
Started Jul 24 05:27:40 PM PDT 24
Finished Jul 24 05:27:41 PM PDT 24
Peak memory 206484 kb
Host smart-952daa95-829f-4a94-a068-aac30d6e4ffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72272
7643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.722727643
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.838544528
Short name T798
Test name
Test status
Simulation time 204934532 ps
CPU time 0.84 seconds
Started Jul 24 05:27:48 PM PDT 24
Finished Jul 24 05:27:49 PM PDT 24
Peak memory 206776 kb
Host smart-5386b013-d1a8-450c-a0d4-9ce51d06795f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83854
4528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.838544528
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.802895223
Short name T1207
Test name
Test status
Simulation time 186451506 ps
CPU time 0.79 seconds
Started Jul 24 05:27:42 PM PDT 24
Finished Jul 24 05:27:43 PM PDT 24
Peak memory 206532 kb
Host smart-379b9496-5bdc-470f-b68f-5eee7a23d6bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80289
5223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.802895223
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.4099883114
Short name T846
Test name
Test status
Simulation time 225005318 ps
CPU time 0.92 seconds
Started Jul 24 05:27:51 PM PDT 24
Finished Jul 24 05:27:52 PM PDT 24
Peak memory 206584 kb
Host smart-cf2cdb99-142a-48ba-8c38-86fcf651c828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40998
83114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.4099883114
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.4166819954
Short name T2702
Test name
Test status
Simulation time 5354556120 ps
CPU time 39.78 seconds
Started Jul 24 05:27:42 PM PDT 24
Finished Jul 24 05:28:22 PM PDT 24
Peak memory 206892 kb
Host smart-eb19dc96-52bb-4864-90b5-c6fe11a1dadb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4166819954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.4166819954
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.3401073130
Short name T203
Test name
Test status
Simulation time 188815834 ps
CPU time 0.82 seconds
Started Jul 24 05:27:42 PM PDT 24
Finished Jul 24 05:27:44 PM PDT 24
Peak memory 206512 kb
Host smart-043fcb6d-8800-4061-a828-994a9dfa7adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34010
73130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.3401073130
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.1827617587
Short name T1222
Test name
Test status
Simulation time 178182582 ps
CPU time 0.86 seconds
Started Jul 24 05:27:46 PM PDT 24
Finished Jul 24 05:27:47 PM PDT 24
Peak memory 206428 kb
Host smart-9e0bda3a-4bc0-4884-aa66-b7eeb316f40e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18276
17587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.1827617587
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.674580021
Short name T848
Test name
Test status
Simulation time 394538126 ps
CPU time 1.21 seconds
Started Jul 24 05:27:41 PM PDT 24
Finished Jul 24 05:27:43 PM PDT 24
Peak memory 206624 kb
Host smart-c009e256-a0aa-4415-bddc-efcf913395b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67458
0021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.674580021
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.3586509615
Short name T1321
Test name
Test status
Simulation time 6836602350 ps
CPU time 63.13 seconds
Started Jul 24 05:27:43 PM PDT 24
Finished Jul 24 05:28:46 PM PDT 24
Peak memory 206928 kb
Host smart-4dd64d66-2be8-4444-894f-543c6f5b4e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35865
09615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.3586509615
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.4261382046
Short name T875
Test name
Test status
Simulation time 52479267 ps
CPU time 0.66 seconds
Started Jul 24 05:24:20 PM PDT 24
Finished Jul 24 05:24:20 PM PDT 24
Peak memory 206512 kb
Host smart-9529ac18-c89f-4c72-bca3-a77e9c7f6a42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4261382046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.4261382046
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.1716954625
Short name T369
Test name
Test status
Simulation time 3952739359 ps
CPU time 4.72 seconds
Started Jul 24 05:24:23 PM PDT 24
Finished Jul 24 05:24:28 PM PDT 24
Peak memory 206612 kb
Host smart-e89e8ace-f60f-48f5-b71d-5578bd9a5620
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1716954625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.1716954625
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.1660028366
Short name T3
Test name
Test status
Simulation time 13414405342 ps
CPU time 13.14 seconds
Started Jul 24 05:24:05 PM PDT 24
Finished Jul 24 05:24:19 PM PDT 24
Peak memory 206724 kb
Host smart-47a19f35-df71-4342-8395-2dc98be6da1e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1660028366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.1660028366
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.415954610
Short name T2044
Test name
Test status
Simulation time 23309697450 ps
CPU time 26.49 seconds
Started Jul 24 05:24:10 PM PDT 24
Finished Jul 24 05:24:37 PM PDT 24
Peak memory 206716 kb
Host smart-d5ba7a20-b319-448d-83f0-0cc2073f0667
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=415954610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.415954610
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.1027623918
Short name T1895
Test name
Test status
Simulation time 206016854 ps
CPU time 0.79 seconds
Started Jul 24 05:24:11 PM PDT 24
Finished Jul 24 05:24:12 PM PDT 24
Peak memory 206600 kb
Host smart-5e2c38db-e830-45a8-9b38-47522323bf83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10276
23918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.1027623918
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.597599180
Short name T55
Test name
Test status
Simulation time 161540860 ps
CPU time 0.81 seconds
Started Jul 24 05:24:15 PM PDT 24
Finished Jul 24 05:24:16 PM PDT 24
Peak memory 206620 kb
Host smart-e603e95c-f81a-4ac0-becb-21994c222f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59759
9180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.597599180
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.492607222
Short name T84
Test name
Test status
Simulation time 186909236 ps
CPU time 0.82 seconds
Started Jul 24 05:24:06 PM PDT 24
Finished Jul 24 05:24:07 PM PDT 24
Peak memory 206592 kb
Host smart-1952276d-28c5-4e49-89aa-782a12b1aa88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49260
7222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.492607222
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.2193357540
Short name T1590
Test name
Test status
Simulation time 154912281 ps
CPU time 0.82 seconds
Started Jul 24 05:24:04 PM PDT 24
Finished Jul 24 05:24:05 PM PDT 24
Peak memory 206544 kb
Host smart-44c5f885-20fd-4e6e-82cf-23270b5c2a99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21933
57540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.2193357540
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.1033771115
Short name T617
Test name
Test status
Simulation time 317166030 ps
CPU time 0.97 seconds
Started Jul 24 05:24:06 PM PDT 24
Finished Jul 24 05:24:07 PM PDT 24
Peak memory 206596 kb
Host smart-8284ea2d-42ec-4410-837c-ff229d821620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10337
71115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.1033771115
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.1488891178
Short name T165
Test name
Test status
Simulation time 22793830643 ps
CPU time 49.91 seconds
Started Jul 24 05:24:12 PM PDT 24
Finished Jul 24 05:25:02 PM PDT 24
Peak memory 206956 kb
Host smart-84b04fc4-3b15-4e3c-90c2-42bb2ec34729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14888
91178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.1488891178
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.1709447606
Short name T2006
Test name
Test status
Simulation time 465051126 ps
CPU time 1.35 seconds
Started Jul 24 05:24:01 PM PDT 24
Finished Jul 24 05:24:03 PM PDT 24
Peak memory 206468 kb
Host smart-66f14666-436e-40ed-bd69-0c920fc8a3d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17094
47606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.1709447606
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.1209764216
Short name T1083
Test name
Test status
Simulation time 139148930 ps
CPU time 0.75 seconds
Started Jul 24 05:24:05 PM PDT 24
Finished Jul 24 05:24:06 PM PDT 24
Peak memory 206468 kb
Host smart-db2ffb71-cea7-4463-bf95-6a2125c27ead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12097
64216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.1209764216
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.2937947359
Short name T723
Test name
Test status
Simulation time 88252437 ps
CPU time 0.7 seconds
Started Jul 24 05:24:06 PM PDT 24
Finished Jul 24 05:24:06 PM PDT 24
Peak memory 206580 kb
Host smart-6631c914-7d6d-44cf-9123-b0c9b7941c4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29379
47359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.2937947359
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.1106096828
Short name T2031
Test name
Test status
Simulation time 879486371 ps
CPU time 2.01 seconds
Started Jul 24 05:24:07 PM PDT 24
Finished Jul 24 05:24:09 PM PDT 24
Peak memory 206684 kb
Host smart-cce7c566-69f1-488f-bfbd-3fa46d8f9dfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11060
96828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.1106096828
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.1318500118
Short name T1136
Test name
Test status
Simulation time 258529845 ps
CPU time 1.77 seconds
Started Jul 24 05:24:08 PM PDT 24
Finished Jul 24 05:24:15 PM PDT 24
Peak memory 206708 kb
Host smart-05b4d9e3-eec7-41f9-ab3a-f3445629270f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13185
00118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.1318500118
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.897480650
Short name T760
Test name
Test status
Simulation time 83227140027 ps
CPU time 114.55 seconds
Started Jul 24 05:24:07 PM PDT 24
Finished Jul 24 05:26:02 PM PDT 24
Peak memory 206980 kb
Host smart-8c7d2ee5-ffa1-4438-b34d-bf71fd2208a4
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=897480650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.897480650
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.3612257310
Short name T2744
Test name
Test status
Simulation time 104276604686 ps
CPU time 127.3 seconds
Started Jul 24 05:24:08 PM PDT 24
Finished Jul 24 05:26:15 PM PDT 24
Peak memory 206796 kb
Host smart-0fdec18f-5c6c-4888-ad49-a8ef6e8f28cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612257310 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.3612257310
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.866485472
Short name T1088
Test name
Test status
Simulation time 120118250112 ps
CPU time 155.33 seconds
Started Jul 24 05:24:13 PM PDT 24
Finished Jul 24 05:26:48 PM PDT 24
Peak memory 206984 kb
Host smart-38201854-93b4-4cd4-a25d-4ad935bcdaac
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=866485472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.866485472
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.4272266085
Short name T337
Test name
Test status
Simulation time 113036137208 ps
CPU time 164.31 seconds
Started Jul 24 05:24:00 PM PDT 24
Finished Jul 24 05:26:45 PM PDT 24
Peak memory 206996 kb
Host smart-4e0bdf3a-97c9-40a3-97ad-c23cccbe029e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272266085 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.4272266085
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.227514368
Short name T1017
Test name
Test status
Simulation time 114153703015 ps
CPU time 157 seconds
Started Jul 24 05:24:12 PM PDT 24
Finished Jul 24 05:26:50 PM PDT 24
Peak memory 206880 kb
Host smart-54f7e3f7-0a36-45f4-a0de-65415c69a4f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22751
4368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.227514368
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.4054969406
Short name T1177
Test name
Test status
Simulation time 237756471 ps
CPU time 0.95 seconds
Started Jul 24 05:24:14 PM PDT 24
Finished Jul 24 05:24:15 PM PDT 24
Peak memory 206588 kb
Host smart-7f9520af-6266-4211-9004-bf57e1a24fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40549
69406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.4054969406
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.1250779589
Short name T1793
Test name
Test status
Simulation time 140178054 ps
CPU time 0.78 seconds
Started Jul 24 05:24:20 PM PDT 24
Finished Jul 24 05:24:21 PM PDT 24
Peak memory 206588 kb
Host smart-bae969bd-d96e-4725-a88b-93bea380dd97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12507
79589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.1250779589
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.2561928780
Short name T2366
Test name
Test status
Simulation time 266318575 ps
CPU time 0.92 seconds
Started Jul 24 05:24:00 PM PDT 24
Finished Jul 24 05:24:02 PM PDT 24
Peak memory 206536 kb
Host smart-481218c5-da67-4ab4-bee6-9f10a0f2f8be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25619
28780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.2561928780
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_iso_retraction.643580479
Short name T845
Test name
Test status
Simulation time 6846476129 ps
CPU time 56.78 seconds
Started Jul 24 05:24:15 PM PDT 24
Finished Jul 24 05:25:12 PM PDT 24
Peak memory 206824 kb
Host smart-13d048e8-8323-4954-9189-56d200ce6c91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64358
0479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.643580479
Directory /workspace/3.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.1697188847
Short name T649
Test name
Test status
Simulation time 208540340 ps
CPU time 0.92 seconds
Started Jul 24 05:24:08 PM PDT 24
Finished Jul 24 05:24:09 PM PDT 24
Peak memory 206640 kb
Host smart-5c7462e3-f67a-426b-88e5-adc13c88bdf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16971
88847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.1697188847
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.3855741776
Short name T1445
Test name
Test status
Simulation time 23328046526 ps
CPU time 29.49 seconds
Started Jul 24 05:24:15 PM PDT 24
Finished Jul 24 05:24:44 PM PDT 24
Peak memory 206760 kb
Host smart-7b61a1f2-05a3-41f1-8426-b686d6dddbe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38557
41776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.3855741776
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.2471274676
Short name T2204
Test name
Test status
Simulation time 3324636795 ps
CPU time 3.72 seconds
Started Jul 24 05:24:10 PM PDT 24
Finished Jul 24 05:24:14 PM PDT 24
Peak memory 206676 kb
Host smart-ceacd34b-7cfb-4c22-a272-d836a7f719ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24712
74676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.2471274676
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.3370493222
Short name T1551
Test name
Test status
Simulation time 9807516546 ps
CPU time 74.28 seconds
Started Jul 24 05:24:14 PM PDT 24
Finished Jul 24 05:25:29 PM PDT 24
Peak memory 206916 kb
Host smart-d47084f4-d9e6-438c-9f41-73b9bef028a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33704
93222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.3370493222
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.1632271796
Short name T1862
Test name
Test status
Simulation time 5507572190 ps
CPU time 157.22 seconds
Started Jul 24 05:24:15 PM PDT 24
Finished Jul 24 05:26:52 PM PDT 24
Peak memory 206764 kb
Host smart-bc9deaa4-b048-4757-a8e4-d72bf2bcfc2b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1632271796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.1632271796
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.282014718
Short name T1867
Test name
Test status
Simulation time 260983122 ps
CPU time 0.95 seconds
Started Jul 24 05:24:05 PM PDT 24
Finished Jul 24 05:24:06 PM PDT 24
Peak memory 206584 kb
Host smart-0ca2e12c-58cc-417d-b766-dc2257f4a025
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=282014718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.282014718
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.1875241385
Short name T1334
Test name
Test status
Simulation time 187966877 ps
CPU time 0.84 seconds
Started Jul 24 05:24:14 PM PDT 24
Finished Jul 24 05:24:15 PM PDT 24
Peak memory 206452 kb
Host smart-9ce06c00-d2f4-436d-ba67-4c241f07094e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18752
41385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.1875241385
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.975799452
Short name T711
Test name
Test status
Simulation time 3308459227 ps
CPU time 30.47 seconds
Started Jul 24 05:24:12 PM PDT 24
Finished Jul 24 05:24:42 PM PDT 24
Peak memory 206908 kb
Host smart-40c4d01a-f42a-44b3-bfa5-7ac1d503d198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97579
9452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.975799452
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.2392227713
Short name T592
Test name
Test status
Simulation time 5692670428 ps
CPU time 143.78 seconds
Started Jul 24 05:24:15 PM PDT 24
Finished Jul 24 05:26:39 PM PDT 24
Peak memory 206912 kb
Host smart-615b59bc-26e0-47f6-b456-037ad8763606
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2392227713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.2392227713
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.3531312026
Short name T1789
Test name
Test status
Simulation time 192248284 ps
CPU time 0.79 seconds
Started Jul 24 05:24:15 PM PDT 24
Finished Jul 24 05:24:16 PM PDT 24
Peak memory 206568 kb
Host smart-8462a1b7-65a5-413a-b218-58fe93bbd4c9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3531312026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.3531312026
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.992887980
Short name T2668
Test name
Test status
Simulation time 143688996 ps
CPU time 0.78 seconds
Started Jul 24 05:24:12 PM PDT 24
Finished Jul 24 05:24:13 PM PDT 24
Peak memory 206584 kb
Host smart-931d7533-3fa4-4e33-b5bb-3893a9327c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99288
7980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.992887980
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.1416777183
Short name T129
Test name
Test status
Simulation time 166551094 ps
CPU time 0.85 seconds
Started Jul 24 05:24:11 PM PDT 24
Finished Jul 24 05:24:12 PM PDT 24
Peak memory 206516 kb
Host smart-5fe0d0cf-fcac-4d31-96e5-e71e5f4d1361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14167
77183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.1416777183
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.2267764245
Short name T1981
Test name
Test status
Simulation time 206254385 ps
CPU time 0.9 seconds
Started Jul 24 05:24:12 PM PDT 24
Finished Jul 24 05:24:13 PM PDT 24
Peak memory 206576 kb
Host smart-9e9e1857-0f61-4b87-ad26-9ba603bbc8f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22677
64245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.2267764245
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.677200468
Short name T326
Test name
Test status
Simulation time 179019952 ps
CPU time 0.81 seconds
Started Jul 24 05:24:14 PM PDT 24
Finished Jul 24 05:24:15 PM PDT 24
Peak memory 206564 kb
Host smart-2598a3fe-03a5-449f-abc6-b1d995c76bee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67720
0468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.677200468
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.2549178505
Short name T1947
Test name
Test status
Simulation time 235216028 ps
CPU time 0.89 seconds
Started Jul 24 05:24:23 PM PDT 24
Finished Jul 24 05:24:24 PM PDT 24
Peak memory 206588 kb
Host smart-f1565429-29e0-4516-842a-cdf4ea16c2d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25491
78505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.2549178505
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.529930912
Short name T1268
Test name
Test status
Simulation time 149272633 ps
CPU time 0.76 seconds
Started Jul 24 05:24:16 PM PDT 24
Finished Jul 24 05:24:16 PM PDT 24
Peak memory 206512 kb
Host smart-b796715b-b9a7-428c-b488-454cec2dab95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52993
0912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.529930912
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.2787175987
Short name T1674
Test name
Test status
Simulation time 220864926 ps
CPU time 0.92 seconds
Started Jul 24 05:24:12 PM PDT 24
Finished Jul 24 05:24:13 PM PDT 24
Peak memory 206592 kb
Host smart-9fdbe995-00b0-4c87-ad96-936ca2cc631e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2787175987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.2787175987
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.3737742520
Short name T190
Test name
Test status
Simulation time 190186701 ps
CPU time 0.91 seconds
Started Jul 24 05:24:16 PM PDT 24
Finished Jul 24 05:24:17 PM PDT 24
Peak memory 206592 kb
Host smart-fbe55049-084a-4eca-a527-45c3463fc298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37377
42520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.3737742520
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.1002943340
Short name T607
Test name
Test status
Simulation time 157438644 ps
CPU time 0.78 seconds
Started Jul 24 05:24:15 PM PDT 24
Finished Jul 24 05:24:16 PM PDT 24
Peak memory 206540 kb
Host smart-06b581ff-b8e5-4982-8c1e-a69331828e1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10029
43340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.1002943340
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.1872643356
Short name T374
Test name
Test status
Simulation time 38963781 ps
CPU time 0.67 seconds
Started Jul 24 05:24:12 PM PDT 24
Finished Jul 24 05:24:13 PM PDT 24
Peak memory 206560 kb
Host smart-789ae092-b9cf-47b1-86c7-40c08b43a07e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18726
43356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.1872643356
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.2835913808
Short name T266
Test name
Test status
Simulation time 17019033706 ps
CPU time 38.19 seconds
Started Jul 24 05:24:11 PM PDT 24
Finished Jul 24 05:24:55 PM PDT 24
Peak memory 206924 kb
Host smart-a9e20d34-a8f5-4076-af8f-ff95432c9a11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28359
13808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.2835913808
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.1698864431
Short name T1367
Test name
Test status
Simulation time 159118103 ps
CPU time 0.78 seconds
Started Jul 24 05:24:09 PM PDT 24
Finished Jul 24 05:24:10 PM PDT 24
Peak memory 206524 kb
Host smart-8793f236-c54d-40e3-9308-9419716ff653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16988
64431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.1698864431
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.820425877
Short name T762
Test name
Test status
Simulation time 193592058 ps
CPU time 0.87 seconds
Started Jul 24 05:24:20 PM PDT 24
Finished Jul 24 05:24:21 PM PDT 24
Peak memory 206576 kb
Host smart-05fd3a94-930f-41e4-bb33-555a8f21c8fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82042
5877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.820425877
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.463679531
Short name T147
Test name
Test status
Simulation time 7642586398 ps
CPU time 31.54 seconds
Started Jul 24 05:24:15 PM PDT 24
Finished Jul 24 05:24:47 PM PDT 24
Peak memory 206920 kb
Host smart-8939cb14-e8e0-4b08-a722-d965bd52ced9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=463679531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.463679531
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.2876437802
Short name T428
Test name
Test status
Simulation time 10669331129 ps
CPU time 191.14 seconds
Started Jul 24 05:24:18 PM PDT 24
Finished Jul 24 05:27:29 PM PDT 24
Peak memory 206920 kb
Host smart-c75643df-8a20-4cb7-97b8-809f59795eb0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2876437802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.2876437802
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.2454701554
Short name T2082
Test name
Test status
Simulation time 6805147327 ps
CPU time 99.69 seconds
Started Jul 24 05:24:17 PM PDT 24
Finished Jul 24 05:25:57 PM PDT 24
Peak memory 206916 kb
Host smart-63446e32-bf26-4461-9360-b2fe7e296aa2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2454701554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.2454701554
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.2587283468
Short name T817
Test name
Test status
Simulation time 210281026 ps
CPU time 0.94 seconds
Started Jul 24 05:24:28 PM PDT 24
Finished Jul 24 05:24:30 PM PDT 24
Peak memory 206440 kb
Host smart-c6912207-eb3a-4aed-9fa2-12545b777599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25872
83468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.2587283468
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.4200175909
Short name T2370
Test name
Test status
Simulation time 182049708 ps
CPU time 0.92 seconds
Started Jul 24 05:24:16 PM PDT 24
Finished Jul 24 05:24:17 PM PDT 24
Peak memory 206596 kb
Host smart-8d5bc81e-5a11-4f42-8198-17bcba2a5331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42001
75909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.4200175909
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.611127609
Short name T64
Test name
Test status
Simulation time 142106996 ps
CPU time 0.77 seconds
Started Jul 24 05:24:15 PM PDT 24
Finished Jul 24 05:24:16 PM PDT 24
Peak memory 206516 kb
Host smart-59ea84a3-2e81-48f9-89e9-f64ae8bad947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61112
7609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.611127609
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.1876829606
Short name T68
Test name
Test status
Simulation time 188611361 ps
CPU time 0.85 seconds
Started Jul 24 05:24:19 PM PDT 24
Finished Jul 24 05:24:20 PM PDT 24
Peak memory 206584 kb
Host smart-fd8d44c2-f9ee-4939-8dff-3de92cf30e24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18768
29606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.1876829606
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.2784106771
Short name T197
Test name
Test status
Simulation time 998786315 ps
CPU time 1.79 seconds
Started Jul 24 05:24:17 PM PDT 24
Finished Jul 24 05:24:19 PM PDT 24
Peak memory 224364 kb
Host smart-353f1e93-70a5-4d19-bf30-398dca5239fb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2784106771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.2784106771
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.1799458113
Short name T49
Test name
Test status
Simulation time 458016984 ps
CPU time 1.33 seconds
Started Jul 24 05:24:20 PM PDT 24
Finished Jul 24 05:24:22 PM PDT 24
Peak memory 206592 kb
Host smart-795625b9-cee5-4343-9c06-ac23fe5b537b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17994
58113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.1799458113
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.2215016822
Short name T15
Test name
Test status
Simulation time 194431307 ps
CPU time 0.85 seconds
Started Jul 24 05:24:10 PM PDT 24
Finished Jul 24 05:24:11 PM PDT 24
Peak memory 206572 kb
Host smart-59c6255c-434f-4a50-9ca3-601ce0fe5e66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22150
16822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.2215016822
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.4040131830
Short name T2264
Test name
Test status
Simulation time 156877717 ps
CPU time 0.76 seconds
Started Jul 24 05:24:26 PM PDT 24
Finished Jul 24 05:24:27 PM PDT 24
Peak memory 206576 kb
Host smart-4ab35832-287c-4d08-96e1-6fcdfeace1a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40401
31830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.4040131830
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.1161926344
Short name T2112
Test name
Test status
Simulation time 158342468 ps
CPU time 0.76 seconds
Started Jul 24 05:24:26 PM PDT 24
Finished Jul 24 05:24:27 PM PDT 24
Peak memory 206588 kb
Host smart-6c569544-a65d-47d5-8890-c76233a4b78d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11619
26344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.1161926344
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.1635854912
Short name T1465
Test name
Test status
Simulation time 216049475 ps
CPU time 0.93 seconds
Started Jul 24 05:24:14 PM PDT 24
Finished Jul 24 05:24:15 PM PDT 24
Peak memory 206596 kb
Host smart-1a1d3c96-2c6d-4c65-a45d-27150c66a0b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16358
54912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.1635854912
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.3830065322
Short name T1618
Test name
Test status
Simulation time 3898718135 ps
CPU time 108.14 seconds
Started Jul 24 05:24:16 PM PDT 24
Finished Jul 24 05:26:05 PM PDT 24
Peak memory 206976 kb
Host smart-f345208b-f266-488d-8fbf-67f27f5d2644
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3830065322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.3830065322
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.1781837950
Short name T1248
Test name
Test status
Simulation time 221010546 ps
CPU time 0.85 seconds
Started Jul 24 05:24:10 PM PDT 24
Finished Jul 24 05:24:11 PM PDT 24
Peak memory 206432 kb
Host smart-ea7b0a89-0e64-4f15-9d93-fc2a07aef58a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17818
37950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.1781837950
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.3474368111
Short name T2674
Test name
Test status
Simulation time 229031887 ps
CPU time 0.85 seconds
Started Jul 24 05:24:29 PM PDT 24
Finished Jul 24 05:24:31 PM PDT 24
Peak memory 206564 kb
Host smart-c6ff83f9-d229-4d8d-9bad-f44381df23f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34743
68111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.3474368111
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.1694639975
Short name T1323
Test name
Test status
Simulation time 427169265 ps
CPU time 1.19 seconds
Started Jul 24 05:24:11 PM PDT 24
Finished Jul 24 05:24:13 PM PDT 24
Peak memory 206552 kb
Host smart-709282b3-ec46-41f2-9277-b5dbd244503e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16946
39975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.1694639975
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.1323356873
Short name T2311
Test name
Test status
Simulation time 3534610753 ps
CPU time 25.12 seconds
Started Jul 24 05:24:14 PM PDT 24
Finished Jul 24 05:24:40 PM PDT 24
Peak memory 206956 kb
Host smart-96be758c-e2ef-4edc-81ea-4af3050c626d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13233
56873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.1323356873
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.2760831637
Short name T2664
Test name
Test status
Simulation time 32186656 ps
CPU time 0.66 seconds
Started Jul 24 05:27:57 PM PDT 24
Finished Jul 24 05:27:58 PM PDT 24
Peak memory 206756 kb
Host smart-71b413bb-1761-4e05-9106-6d5fa1ee331b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2760831637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.2760831637
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.1800922545
Short name T648
Test name
Test status
Simulation time 3541626870 ps
CPU time 4.17 seconds
Started Jul 24 05:27:46 PM PDT 24
Finished Jul 24 05:27:50 PM PDT 24
Peak memory 206916 kb
Host smart-a69b4ee8-63b1-454c-ab15-f8a186abe167
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1800922545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.1800922545
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.3928522243
Short name T604
Test name
Test status
Simulation time 13344349430 ps
CPU time 14.21 seconds
Started Jul 24 05:27:55 PM PDT 24
Finished Jul 24 05:28:09 PM PDT 24
Peak memory 206716 kb
Host smart-da83caec-acbb-4ea2-9879-025fec3f1569
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3928522243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.3928522243
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.214870882
Short name T1699
Test name
Test status
Simulation time 23363101863 ps
CPU time 23.34 seconds
Started Jul 24 05:27:33 PM PDT 24
Finished Jul 24 05:27:56 PM PDT 24
Peak memory 206724 kb
Host smart-ea5f20e0-3712-462e-84a6-e5fd3b0ebda6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=214870882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.214870882
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.2013117143
Short name T1975
Test name
Test status
Simulation time 143779348 ps
CPU time 0.8 seconds
Started Jul 24 05:27:47 PM PDT 24
Finished Jul 24 05:27:48 PM PDT 24
Peak memory 206576 kb
Host smart-1ec7ec35-0b2e-4d72-b4ef-f6943ae6f73b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20131
17143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.2013117143
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.653840447
Short name T1653
Test name
Test status
Simulation time 150290699 ps
CPU time 0.8 seconds
Started Jul 24 05:27:42 PM PDT 24
Finished Jul 24 05:27:43 PM PDT 24
Peak memory 206648 kb
Host smart-080cb937-3711-4fab-a8f5-d7e2f7f40601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65384
0447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.653840447
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.3337139251
Short name T2520
Test name
Test status
Simulation time 208043016 ps
CPU time 0.85 seconds
Started Jul 24 05:27:46 PM PDT 24
Finished Jul 24 05:27:47 PM PDT 24
Peak memory 206576 kb
Host smart-08e4afd7-3f21-45f6-b632-add588f79620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33371
39251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.3337139251
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.2017861399
Short name T1232
Test name
Test status
Simulation time 576038042 ps
CPU time 1.5 seconds
Started Jul 24 05:27:52 PM PDT 24
Finished Jul 24 05:27:53 PM PDT 24
Peak memory 206592 kb
Host smart-2d792a2c-37ea-4b4b-8f94-e68f869668d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20178
61399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.2017861399
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.4201642137
Short name T168
Test name
Test status
Simulation time 9069581920 ps
CPU time 15.13 seconds
Started Jul 24 05:27:43 PM PDT 24
Finished Jul 24 05:27:58 PM PDT 24
Peak memory 206936 kb
Host smart-b81e02da-7dd5-45b8-8be1-ca45802ad63e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42016
42137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.4201642137
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.1955204604
Short name T2657
Test name
Test status
Simulation time 392018059 ps
CPU time 1.2 seconds
Started Jul 24 05:27:46 PM PDT 24
Finished Jul 24 05:27:48 PM PDT 24
Peak memory 206596 kb
Host smart-c22768c5-0ec3-45a2-8c03-397fbd7b98b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19552
04604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.1955204604
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.2017178435
Short name T1826
Test name
Test status
Simulation time 151686423 ps
CPU time 0.77 seconds
Started Jul 24 05:27:45 PM PDT 24
Finished Jul 24 05:27:46 PM PDT 24
Peak memory 206592 kb
Host smart-b67eb052-0594-4435-8194-ee20f8d1080d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20171
78435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.2017178435
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.421062311
Short name T201
Test name
Test status
Simulation time 38193751 ps
CPU time 0.64 seconds
Started Jul 24 05:27:54 PM PDT 24
Finished Jul 24 05:27:55 PM PDT 24
Peak memory 206576 kb
Host smart-be60fc68-8760-45dd-870e-4f8606a19692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42106
2311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.421062311
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.719554738
Short name T1186
Test name
Test status
Simulation time 884412718 ps
CPU time 1.96 seconds
Started Jul 24 05:28:01 PM PDT 24
Finished Jul 24 05:28:03 PM PDT 24
Peak memory 206700 kb
Host smart-5ad21f14-4988-41aa-a330-94a446d00efd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71955
4738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.719554738
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.3944679314
Short name T172
Test name
Test status
Simulation time 301953765 ps
CPU time 1.91 seconds
Started Jul 24 05:27:57 PM PDT 24
Finished Jul 24 05:27:59 PM PDT 24
Peak memory 206732 kb
Host smart-98e8a277-39c8-48aa-88a1-73f1203af6e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39446
79314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.3944679314
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.1074620353
Short name T687
Test name
Test status
Simulation time 240141600 ps
CPU time 0.88 seconds
Started Jul 24 05:28:02 PM PDT 24
Finished Jul 24 05:28:03 PM PDT 24
Peak memory 206580 kb
Host smart-c24bc658-5fc6-480b-b427-1d21c0289a0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10746
20353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.1074620353
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.3156114426
Short name T2734
Test name
Test status
Simulation time 192634423 ps
CPU time 0.82 seconds
Started Jul 24 05:27:46 PM PDT 24
Finished Jul 24 05:27:47 PM PDT 24
Peak memory 206444 kb
Host smart-102f7df9-c89e-4965-8db5-8fadf3bb671b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31561
14426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.3156114426
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.3992753572
Short name T2578
Test name
Test status
Simulation time 277479928 ps
CPU time 1.08 seconds
Started Jul 24 05:28:06 PM PDT 24
Finished Jul 24 05:28:08 PM PDT 24
Peak memory 206556 kb
Host smart-66fc6756-70b8-467e-8ec5-a67b2b9ab2bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39927
53572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.3992753572
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_invalid_sync.2609287924
Short name T1411
Test name
Test status
Simulation time 6182955674 ps
CPU time 43.18 seconds
Started Jul 24 05:27:51 PM PDT 24
Finished Jul 24 05:28:34 PM PDT 24
Peak memory 206948 kb
Host smart-d00b3179-80a6-45ff-9281-b6eea2ed2feb
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2609287924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.2609287924
Directory /workspace/30.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/30.usbdev_iso_retraction.1755795630
Short name T1619
Test name
Test status
Simulation time 7665524365 ps
CPU time 67.45 seconds
Started Jul 24 05:27:47 PM PDT 24
Finished Jul 24 05:28:55 PM PDT 24
Peak memory 206840 kb
Host smart-ba9eb2db-c55b-483c-a298-7d8f3258b804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17557
95630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_iso_retraction.1755795630
Directory /workspace/30.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.4087854478
Short name T2384
Test name
Test status
Simulation time 194879699 ps
CPU time 0.9 seconds
Started Jul 24 05:27:47 PM PDT 24
Finished Jul 24 05:27:48 PM PDT 24
Peak memory 206400 kb
Host smart-af86fbe6-ac78-42d2-b7e8-33f1cc2d8f88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40878
54478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.4087854478
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.3251493536
Short name T2413
Test name
Test status
Simulation time 23286287597 ps
CPU time 28.08 seconds
Started Jul 24 05:27:47 PM PDT 24
Finished Jul 24 05:28:15 PM PDT 24
Peak memory 206704 kb
Host smart-5d10220a-1623-42a8-96d0-26c0174eb69a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32514
93536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.3251493536
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.848964975
Short name T343
Test name
Test status
Simulation time 3319655104 ps
CPU time 3.97 seconds
Started Jul 24 05:27:51 PM PDT 24
Finished Jul 24 05:27:56 PM PDT 24
Peak memory 206788 kb
Host smart-2cc59c4a-2f3c-456f-bdcf-48666a742066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84896
4975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.848964975
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.2064488901
Short name T1105
Test name
Test status
Simulation time 6664833193 ps
CPU time 46.17 seconds
Started Jul 24 05:27:55 PM PDT 24
Finished Jul 24 05:28:41 PM PDT 24
Peak memory 206948 kb
Host smart-202f9b6c-d692-4e82-8e31-545141a73dd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20644
88901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.2064488901
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.2560567577
Short name T1331
Test name
Test status
Simulation time 4496834082 ps
CPU time 122.5 seconds
Started Jul 24 05:27:56 PM PDT 24
Finished Jul 24 05:29:59 PM PDT 24
Peak memory 206924 kb
Host smart-24eb140d-d66e-4909-9e15-617f6bb36121
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2560567577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.2560567577
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.1733903048
Short name T494
Test name
Test status
Simulation time 236604839 ps
CPU time 0.93 seconds
Started Jul 24 05:28:07 PM PDT 24
Finished Jul 24 05:28:09 PM PDT 24
Peak memory 206592 kb
Host smart-2b3e147a-ab6a-4ed8-9887-363124222b73
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1733903048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.1733903048
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.3920982201
Short name T1273
Test name
Test status
Simulation time 247902817 ps
CPU time 0.91 seconds
Started Jul 24 05:28:09 PM PDT 24
Finished Jul 24 05:28:10 PM PDT 24
Peak memory 206604 kb
Host smart-0ed32786-d9cd-4ce9-a249-60f66efbea86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39209
82201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.3920982201
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.2694310052
Short name T451
Test name
Test status
Simulation time 3486609518 ps
CPU time 31.48 seconds
Started Jul 24 05:28:10 PM PDT 24
Finished Jul 24 05:28:42 PM PDT 24
Peak memory 206916 kb
Host smart-f53289de-d52b-4234-bcc4-e051e144ea95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26943
10052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.2694310052
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.3559719337
Short name T299
Test name
Test status
Simulation time 4436427230 ps
CPU time 31.86 seconds
Started Jul 24 05:27:56 PM PDT 24
Finished Jul 24 05:28:28 PM PDT 24
Peak memory 206700 kb
Host smart-a404f49d-c10e-4b3e-b394-d6201ce2b4d3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3559719337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.3559719337
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.1491132510
Short name T1903
Test name
Test status
Simulation time 161910701 ps
CPU time 0.84 seconds
Started Jul 24 05:28:02 PM PDT 24
Finished Jul 24 05:28:03 PM PDT 24
Peak memory 206536 kb
Host smart-0c9bbe4c-0b1c-4755-9eb1-7cbff9729830
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1491132510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.1491132510
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.2427717048
Short name T1326
Test name
Test status
Simulation time 146695521 ps
CPU time 0.77 seconds
Started Jul 24 05:28:01 PM PDT 24
Finished Jul 24 05:28:02 PM PDT 24
Peak memory 206616 kb
Host smart-40c8db81-34ab-45e3-b58e-f4663d79e4cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24277
17048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.2427717048
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.321345410
Short name T115
Test name
Test status
Simulation time 192839326 ps
CPU time 0.83 seconds
Started Jul 24 05:28:01 PM PDT 24
Finished Jul 24 05:28:02 PM PDT 24
Peak memory 206596 kb
Host smart-bb9c0298-2a81-4fc4-9b3c-bb4016b13715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32134
5410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.321345410
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.1119871565
Short name T93
Test name
Test status
Simulation time 186154433 ps
CPU time 0.81 seconds
Started Jul 24 05:27:51 PM PDT 24
Finished Jul 24 05:27:52 PM PDT 24
Peak memory 206592 kb
Host smart-794f963b-6c7a-471c-8d6f-4f8cc3c34654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11198
71565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.1119871565
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.1136243215
Short name T1941
Test name
Test status
Simulation time 181525667 ps
CPU time 0.8 seconds
Started Jul 24 05:28:03 PM PDT 24
Finished Jul 24 05:28:04 PM PDT 24
Peak memory 206572 kb
Host smart-a658c70b-ea25-4628-890b-eda161b0ccbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11362
43215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.1136243215
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.2103494449
Short name T523
Test name
Test status
Simulation time 181753662 ps
CPU time 0.78 seconds
Started Jul 24 05:27:52 PM PDT 24
Finished Jul 24 05:27:53 PM PDT 24
Peak memory 206728 kb
Host smart-60cd8330-4da9-4adf-b7f0-49d9be323389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21034
94449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.2103494449
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.877582712
Short name T508
Test name
Test status
Simulation time 183862205 ps
CPU time 0.79 seconds
Started Jul 24 05:27:54 PM PDT 24
Finished Jul 24 05:27:55 PM PDT 24
Peak memory 206504 kb
Host smart-17143c55-732b-48e9-87dd-2b03265d2730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87758
2712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.877582712
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.1454629019
Short name T1807
Test name
Test status
Simulation time 230764571 ps
CPU time 1.03 seconds
Started Jul 24 05:28:02 PM PDT 24
Finished Jul 24 05:28:03 PM PDT 24
Peak memory 206556 kb
Host smart-b851e869-bc5b-47aa-b148-e981ecd745cc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1454629019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.1454629019
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.2589629826
Short name T2351
Test name
Test status
Simulation time 139531763 ps
CPU time 0.73 seconds
Started Jul 24 05:27:47 PM PDT 24
Finished Jul 24 05:27:48 PM PDT 24
Peak memory 206604 kb
Host smart-860df6ab-d207-4c50-a4bb-309441eb0c26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25896
29826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.2589629826
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.2183832411
Short name T1201
Test name
Test status
Simulation time 57376012 ps
CPU time 0.69 seconds
Started Jul 24 05:27:46 PM PDT 24
Finished Jul 24 05:27:47 PM PDT 24
Peak memory 206584 kb
Host smart-e620c0ea-4d08-46c1-81f8-678852801841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21838
32411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.2183832411
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.150306960
Short name T1574
Test name
Test status
Simulation time 10215799659 ps
CPU time 22.4 seconds
Started Jul 24 05:27:57 PM PDT 24
Finished Jul 24 05:28:20 PM PDT 24
Peak memory 206940 kb
Host smart-a9240009-0ec8-4dfe-9d30-0602695c1921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15030
6960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.150306960
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.3373975767
Short name T387
Test name
Test status
Simulation time 154417142 ps
CPU time 0.77 seconds
Started Jul 24 05:28:06 PM PDT 24
Finished Jul 24 05:28:07 PM PDT 24
Peak memory 206576 kb
Host smart-da19a088-7193-446c-a1e6-9f9ec7d33f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33739
75767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.3373975767
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.1424386468
Short name T1767
Test name
Test status
Simulation time 253498172 ps
CPU time 0.98 seconds
Started Jul 24 05:27:53 PM PDT 24
Finished Jul 24 05:27:54 PM PDT 24
Peak memory 206520 kb
Host smart-3e15876b-2d67-44c9-8a04-78ddfe1350be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14243
86468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.1424386468
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.836401104
Short name T740
Test name
Test status
Simulation time 234224274 ps
CPU time 0.82 seconds
Started Jul 24 05:27:44 PM PDT 24
Finished Jul 24 05:27:45 PM PDT 24
Peak memory 206632 kb
Host smart-733e06a3-1956-4edb-aca9-8dbce22f05b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83640
1104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.836401104
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.233623905
Short name T2385
Test name
Test status
Simulation time 181400230 ps
CPU time 0.85 seconds
Started Jul 24 05:27:47 PM PDT 24
Finished Jul 24 05:27:48 PM PDT 24
Peak memory 206552 kb
Host smart-3f00912b-de36-4ed8-913d-e68764fabdc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23362
3905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.233623905
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.2706118390
Short name T645
Test name
Test status
Simulation time 232494977 ps
CPU time 0.92 seconds
Started Jul 24 05:27:53 PM PDT 24
Finished Jul 24 05:27:54 PM PDT 24
Peak memory 206660 kb
Host smart-544dcf16-d1e3-49a6-9ff5-009f788bf2bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27061
18390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.2706118390
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.1020326661
Short name T2365
Test name
Test status
Simulation time 147443401 ps
CPU time 0.82 seconds
Started Jul 24 05:28:02 PM PDT 24
Finished Jul 24 05:28:04 PM PDT 24
Peak memory 206560 kb
Host smart-9df21b25-fff4-473d-bc63-9b70c67748cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10203
26661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.1020326661
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.527501683
Short name T232
Test name
Test status
Simulation time 164698425 ps
CPU time 0.78 seconds
Started Jul 24 05:27:43 PM PDT 24
Finished Jul 24 05:27:44 PM PDT 24
Peak memory 206536 kb
Host smart-3a11150c-baa5-430a-9bdf-0065317dadc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52750
1683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.527501683
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.900654803
Short name T2750
Test name
Test status
Simulation time 252319572 ps
CPU time 0.96 seconds
Started Jul 24 05:27:45 PM PDT 24
Finished Jul 24 05:27:46 PM PDT 24
Peak memory 206776 kb
Host smart-f74723f0-7851-4c4a-b42b-c45646864a28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90065
4803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.900654803
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.40464061
Short name T1443
Test name
Test status
Simulation time 5144721865 ps
CPU time 142.15 seconds
Started Jul 24 05:27:50 PM PDT 24
Finished Jul 24 05:30:13 PM PDT 24
Peak memory 206984 kb
Host smart-a5251c56-65fb-4b7b-8b8a-50c078749b89
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=40464061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.40464061
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.4193264465
Short name T1217
Test name
Test status
Simulation time 148408458 ps
CPU time 0.78 seconds
Started Jul 24 05:28:03 PM PDT 24
Finished Jul 24 05:28:04 PM PDT 24
Peak memory 206520 kb
Host smart-4aa18ffa-e3a3-4e4f-b9de-1e1d8cd5c557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41932
64465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.4193264465
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.4087105500
Short name T368
Test name
Test status
Simulation time 196430567 ps
CPU time 0.8 seconds
Started Jul 24 05:28:06 PM PDT 24
Finished Jul 24 05:28:07 PM PDT 24
Peak memory 206520 kb
Host smart-ed26bc6b-e6a3-4e50-b9a8-0b4dc0b668de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40871
05500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.4087105500
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.2605614044
Short name T2054
Test name
Test status
Simulation time 343753926 ps
CPU time 1.15 seconds
Started Jul 24 05:28:04 PM PDT 24
Finished Jul 24 05:28:05 PM PDT 24
Peak memory 206516 kb
Host smart-3dedf1de-0b97-4aaa-9aee-9736a3527d20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26056
14044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.2605614044
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.407174483
Short name T2188
Test name
Test status
Simulation time 4912717236 ps
CPU time 37.87 seconds
Started Jul 24 05:27:48 PM PDT 24
Finished Jul 24 05:28:27 PM PDT 24
Peak memory 206920 kb
Host smart-fa8c251f-f017-42fc-a88e-20452dfb190b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40717
4483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.407174483
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.1474890540
Short name T470
Test name
Test status
Simulation time 42481090 ps
CPU time 0.66 seconds
Started Jul 24 05:27:51 PM PDT 24
Finished Jul 24 05:27:52 PM PDT 24
Peak memory 206600 kb
Host smart-1ee1f0c8-7ba9-413b-bcf5-4a7a03b0d5d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1474890540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.1474890540
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.3466516278
Short name T13
Test name
Test status
Simulation time 3950373441 ps
CPU time 5.34 seconds
Started Jul 24 05:28:00 PM PDT 24
Finished Jul 24 05:28:06 PM PDT 24
Peak memory 206664 kb
Host smart-4b67636b-c67c-4874-89a2-77d14edd1315
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3466516278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.3466516278
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.2424847509
Short name T610
Test name
Test status
Simulation time 13377850456 ps
CPU time 13.44 seconds
Started Jul 24 05:27:46 PM PDT 24
Finished Jul 24 05:28:00 PM PDT 24
Peak memory 206844 kb
Host smart-e5c8d2f3-0640-4c06-9c77-1fe91fa9b925
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2424847509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.2424847509
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.3713953059
Short name T2388
Test name
Test status
Simulation time 23335865253 ps
CPU time 24.44 seconds
Started Jul 24 05:27:50 PM PDT 24
Finished Jul 24 05:28:15 PM PDT 24
Peak memory 206716 kb
Host smart-bf139614-e9ef-4af5-9993-c788bb875f4d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3713953059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.3713953059
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.3110686657
Short name T455
Test name
Test status
Simulation time 184432172 ps
CPU time 0.88 seconds
Started Jul 24 05:28:07 PM PDT 24
Finished Jul 24 05:28:08 PM PDT 24
Peak memory 206576 kb
Host smart-3674c996-1c69-4378-b9ab-99f97335a37c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31106
86657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.3110686657
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.3221304919
Short name T2114
Test name
Test status
Simulation time 182269874 ps
CPU time 0.77 seconds
Started Jul 24 05:28:01 PM PDT 24
Finished Jul 24 05:28:02 PM PDT 24
Peak memory 206516 kb
Host smart-2b3a5a3f-3434-4cac-ad9d-bb39f68e3473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32213
04919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.3221304919
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.3246263655
Short name T105
Test name
Test status
Simulation time 527919052 ps
CPU time 1.57 seconds
Started Jul 24 05:27:57 PM PDT 24
Finished Jul 24 05:27:59 PM PDT 24
Peak memory 206784 kb
Host smart-0e43e94e-3c5b-45ec-8366-3b15d18ab999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32462
63655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.3246263655
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.1156645319
Short name T1672
Test name
Test status
Simulation time 1680209526 ps
CPU time 3.38 seconds
Started Jul 24 05:27:56 PM PDT 24
Finished Jul 24 05:28:00 PM PDT 24
Peak memory 206692 kb
Host smart-1504e1c4-8123-4689-bfa2-096eb14dd0d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11566
45319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.1156645319
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.3765985465
Short name T2009
Test name
Test status
Simulation time 19206925534 ps
CPU time 33.28 seconds
Started Jul 24 05:27:52 PM PDT 24
Finished Jul 24 05:28:26 PM PDT 24
Peak memory 206920 kb
Host smart-616a612c-e2a4-483a-8cb7-a5ebdc301f87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37659
85465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.3765985465
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.288012831
Short name T2324
Test name
Test status
Simulation time 475099536 ps
CPU time 1.38 seconds
Started Jul 24 05:28:05 PM PDT 24
Finished Jul 24 05:28:06 PM PDT 24
Peak memory 206564 kb
Host smart-67bc59fc-9958-463e-8d8b-f066dbbe0ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28801
2831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.288012831
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.327602782
Short name T1452
Test name
Test status
Simulation time 173116417 ps
CPU time 0.76 seconds
Started Jul 24 05:27:40 PM PDT 24
Finished Jul 24 05:27:41 PM PDT 24
Peak memory 206620 kb
Host smart-0029b76b-bc63-47b5-94a0-1cbf098d89b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32760
2782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.327602782
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.2318780227
Short name T1633
Test name
Test status
Simulation time 50659845 ps
CPU time 0.64 seconds
Started Jul 24 05:27:53 PM PDT 24
Finished Jul 24 05:27:54 PM PDT 24
Peak memory 206564 kb
Host smart-420f155b-9f24-492f-8466-09055b74b11d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23187
80227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.2318780227
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.2701490798
Short name T2349
Test name
Test status
Simulation time 1102624842 ps
CPU time 2.51 seconds
Started Jul 24 05:28:00 PM PDT 24
Finished Jul 24 05:28:02 PM PDT 24
Peak memory 206748 kb
Host smart-0fb8ec62-4545-48a7-b1b9-d601b1315237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27014
90798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.2701490798
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.2938349300
Short name T2357
Test name
Test status
Simulation time 231804717 ps
CPU time 1.48 seconds
Started Jul 24 05:27:49 PM PDT 24
Finished Jul 24 05:27:50 PM PDT 24
Peak memory 206788 kb
Host smart-48d3ca34-9a28-4635-b4e5-849249256bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29383
49300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.2938349300
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.587108825
Short name T833
Test name
Test status
Simulation time 209609515 ps
CPU time 0.86 seconds
Started Jul 24 05:28:04 PM PDT 24
Finished Jul 24 05:28:05 PM PDT 24
Peak memory 206588 kb
Host smart-15632d7c-e0b2-4322-852a-ac43c3f36493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58710
8825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.587108825
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.1523679178
Short name T1507
Test name
Test status
Simulation time 174055837 ps
CPU time 0.77 seconds
Started Jul 24 05:27:50 PM PDT 24
Finished Jul 24 05:27:51 PM PDT 24
Peak memory 206624 kb
Host smart-70d566ee-008e-4ffc-9080-4decb6361334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15236
79178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.1523679178
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.312773462
Short name T2461
Test name
Test status
Simulation time 228699996 ps
CPU time 0.92 seconds
Started Jul 24 05:28:07 PM PDT 24
Finished Jul 24 05:28:08 PM PDT 24
Peak memory 206516 kb
Host smart-f3bd55e1-ec05-4fca-8639-9a575f0ae14e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31277
3462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.312773462
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_iso_retraction.611950371
Short name T1963
Test name
Test status
Simulation time 5286348156 ps
CPU time 44.14 seconds
Started Jul 24 05:27:59 PM PDT 24
Finished Jul 24 05:28:43 PM PDT 24
Peak memory 206880 kb
Host smart-b6cc15dd-5082-4f02-964d-3f44867483c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61195
0371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_iso_retraction.611950371
Directory /workspace/31.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.1008701254
Short name T2340
Test name
Test status
Simulation time 219328896 ps
CPU time 0.82 seconds
Started Jul 24 05:27:48 PM PDT 24
Finished Jul 24 05:27:49 PM PDT 24
Peak memory 206580 kb
Host smart-fac016ec-2c17-4d54-8096-1a4234f016d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10087
01254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.1008701254
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.2106953406
Short name T2707
Test name
Test status
Simulation time 23278115544 ps
CPU time 24.61 seconds
Started Jul 24 05:27:49 PM PDT 24
Finished Jul 24 05:28:14 PM PDT 24
Peak memory 206716 kb
Host smart-e7cf4f39-4478-4fee-a283-a1fe1dbf852f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21069
53406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.2106953406
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.492028126
Short name T983
Test name
Test status
Simulation time 3337128746 ps
CPU time 4.45 seconds
Started Jul 24 05:28:00 PM PDT 24
Finished Jul 24 05:28:05 PM PDT 24
Peak memory 206692 kb
Host smart-087f6836-badc-48cc-a107-2d61dab5ac3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49202
8126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.492028126
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.1505253060
Short name T2541
Test name
Test status
Simulation time 7478170699 ps
CPU time 201.35 seconds
Started Jul 24 05:27:59 PM PDT 24
Finished Jul 24 05:31:20 PM PDT 24
Peak memory 206960 kb
Host smart-f8919e2f-7a3f-47b0-b239-2365f172ad47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15052
53060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.1505253060
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.3174261885
Short name T1800
Test name
Test status
Simulation time 3229102456 ps
CPU time 33.25 seconds
Started Jul 24 05:28:05 PM PDT 24
Finished Jul 24 05:28:38 PM PDT 24
Peak memory 206856 kb
Host smart-6d59f731-ea4c-41c0-af5a-6c2651fc2095
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3174261885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.3174261885
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.2077673840
Short name T1846
Test name
Test status
Simulation time 243614422 ps
CPU time 0.91 seconds
Started Jul 24 05:31:27 PM PDT 24
Finished Jul 24 05:31:28 PM PDT 24
Peak memory 206560 kb
Host smart-09c7dab2-86d0-49e7-9f83-63c98feb47f8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2077673840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.2077673840
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.3911552702
Short name T1728
Test name
Test status
Simulation time 270511533 ps
CPU time 0.99 seconds
Started Jul 24 05:28:06 PM PDT 24
Finished Jul 24 05:28:08 PM PDT 24
Peak memory 206644 kb
Host smart-b159e82d-fb02-40c9-910c-233d9278de6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39115
52702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.3911552702
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.2176771633
Short name T1093
Test name
Test status
Simulation time 5040690585 ps
CPU time 34.11 seconds
Started Jul 24 05:27:48 PM PDT 24
Finished Jul 24 05:28:22 PM PDT 24
Peak memory 206884 kb
Host smart-1893aed8-45dd-481c-ad27-8d4133bebe5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21767
71633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.2176771633
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.2610268574
Short name T1366
Test name
Test status
Simulation time 4619255316 ps
CPU time 30.83 seconds
Started Jul 24 05:27:56 PM PDT 24
Finished Jul 24 05:28:27 PM PDT 24
Peak memory 206980 kb
Host smart-f16ca284-c413-42eb-b0f2-aa575fb502bf
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2610268574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.2610268574
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.343313357
Short name T1235
Test name
Test status
Simulation time 168971232 ps
CPU time 0.85 seconds
Started Jul 24 05:27:58 PM PDT 24
Finished Jul 24 05:28:00 PM PDT 24
Peak memory 206612 kb
Host smart-76f365bf-188d-4974-a620-1e78704b308f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=343313357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.343313357
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.2242143793
Short name T1043
Test name
Test status
Simulation time 144595226 ps
CPU time 0.74 seconds
Started Jul 24 05:28:07 PM PDT 24
Finished Jul 24 05:28:08 PM PDT 24
Peak memory 206596 kb
Host smart-3c3113f8-ca35-4e19-a23d-6e3324bbd5d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22421
43793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.2242143793
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.1134042781
Short name T117
Test name
Test status
Simulation time 217860153 ps
CPU time 0.9 seconds
Started Jul 24 05:27:51 PM PDT 24
Finished Jul 24 05:27:52 PM PDT 24
Peak memory 206592 kb
Host smart-8a46bc3d-56ca-446e-a6cc-5ed363e76b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11340
42781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.1134042781
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.891402337
Short name T733
Test name
Test status
Simulation time 191701253 ps
CPU time 0.86 seconds
Started Jul 24 05:28:01 PM PDT 24
Finished Jul 24 05:28:02 PM PDT 24
Peak memory 206600 kb
Host smart-d18139f3-6017-4a67-ae00-b4d0df0107b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89140
2337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.891402337
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.993555947
Short name T1658
Test name
Test status
Simulation time 202904005 ps
CPU time 0.8 seconds
Started Jul 24 05:27:57 PM PDT 24
Finished Jul 24 05:27:58 PM PDT 24
Peak memory 206572 kb
Host smart-1a681581-391a-425f-8303-59b93c1d9a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99355
5947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.993555947
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.1585388087
Short name T2402
Test name
Test status
Simulation time 164266520 ps
CPU time 0.76 seconds
Started Jul 24 05:28:05 PM PDT 24
Finished Jul 24 05:28:06 PM PDT 24
Peak memory 206596 kb
Host smart-b16f7c17-d3e8-471b-a0cf-a23aeeafcb4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15853
88087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.1585388087
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.1026771080
Short name T2244
Test name
Test status
Simulation time 150623077 ps
CPU time 0.78 seconds
Started Jul 24 05:28:04 PM PDT 24
Finished Jul 24 05:28:05 PM PDT 24
Peak memory 206556 kb
Host smart-1b5d7412-8923-44f9-aa8a-5ad1e4ee77b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10267
71080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.1026771080
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.510957933
Short name T2133
Test name
Test status
Simulation time 196850436 ps
CPU time 0.97 seconds
Started Jul 24 05:28:17 PM PDT 24
Finished Jul 24 05:28:19 PM PDT 24
Peak memory 206588 kb
Host smart-36ea8014-f67d-460c-935c-556ba37f40fb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=510957933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.510957933
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.4282137863
Short name T1796
Test name
Test status
Simulation time 170227485 ps
CPU time 0.79 seconds
Started Jul 24 05:28:00 PM PDT 24
Finished Jul 24 05:28:01 PM PDT 24
Peak memory 206640 kb
Host smart-ff3630a3-262f-4aeb-b58d-d86be29d6986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42821
37863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.4282137863
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.3881758449
Short name T29
Test name
Test status
Simulation time 36277374 ps
CPU time 0.63 seconds
Started Jul 24 05:28:07 PM PDT 24
Finished Jul 24 05:28:08 PM PDT 24
Peak memory 206600 kb
Host smart-f5ec5e91-d7ea-433e-9504-7c73df53f5d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38817
58449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.3881758449
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.1313707908
Short name T1942
Test name
Test status
Simulation time 18309808429 ps
CPU time 39.91 seconds
Started Jul 24 05:28:00 PM PDT 24
Finished Jul 24 05:28:40 PM PDT 24
Peak memory 206924 kb
Host smart-b351d3ce-f74b-4186-964d-d381cf7263f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13137
07908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.1313707908
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.1126734227
Short name T2190
Test name
Test status
Simulation time 157692410 ps
CPU time 0.82 seconds
Started Jul 24 05:27:52 PM PDT 24
Finished Jul 24 05:27:53 PM PDT 24
Peak memory 206600 kb
Host smart-e6c3fb42-c4ce-4f6e-ae11-f92175b4996d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11267
34227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.1126734227
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.1010553702
Short name T631
Test name
Test status
Simulation time 195059353 ps
CPU time 0.82 seconds
Started Jul 24 05:28:08 PM PDT 24
Finished Jul 24 05:28:09 PM PDT 24
Peak memory 206648 kb
Host smart-1b5d66d8-e5e3-4e9c-904e-b60dfff7da75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10105
53702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.1010553702
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.3931706098
Short name T1773
Test name
Test status
Simulation time 263029361 ps
CPU time 0.96 seconds
Started Jul 24 05:28:02 PM PDT 24
Finished Jul 24 05:28:03 PM PDT 24
Peak memory 206560 kb
Host smart-5e67b84c-fd9e-4fdd-84e1-7b90b743c8db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39317
06098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.3931706098
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.4158353056
Short name T485
Test name
Test status
Simulation time 194470220 ps
CPU time 0.85 seconds
Started Jul 24 05:27:58 PM PDT 24
Finished Jul 24 05:27:59 PM PDT 24
Peak memory 206572 kb
Host smart-e72d314c-142e-4254-8cd7-5e98d93f79c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41583
53056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.4158353056
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.4179632736
Short name T2041
Test name
Test status
Simulation time 139271891 ps
CPU time 0.71 seconds
Started Jul 24 05:28:17 PM PDT 24
Finished Jul 24 05:28:18 PM PDT 24
Peak memory 206588 kb
Host smart-b66acb70-4a25-4dd7-b148-fe98c979c4db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41796
32736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.4179632736
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.1860754128
Short name T2548
Test name
Test status
Simulation time 144852746 ps
CPU time 0.8 seconds
Started Jul 24 05:27:58 PM PDT 24
Finished Jul 24 05:28:00 PM PDT 24
Peak memory 206516 kb
Host smart-38f4695b-1571-4af3-82b9-057609659ca2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18607
54128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.1860754128
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.106072008
Short name T349
Test name
Test status
Simulation time 190338658 ps
CPU time 0.81 seconds
Started Jul 24 05:28:06 PM PDT 24
Finished Jul 24 05:28:08 PM PDT 24
Peak memory 206584 kb
Host smart-6fe69b2b-4b26-4088-b627-549090587a7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10607
2008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.106072008
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.1876655439
Short name T1021
Test name
Test status
Simulation time 205633748 ps
CPU time 0.85 seconds
Started Jul 24 05:28:04 PM PDT 24
Finished Jul 24 05:28:05 PM PDT 24
Peak memory 206572 kb
Host smart-3bffabe5-fd2a-4d01-a342-7e44d251def9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18766
55439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.1876655439
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.1402474444
Short name T1784
Test name
Test status
Simulation time 5506543682 ps
CPU time 150.06 seconds
Started Jul 24 05:27:50 PM PDT 24
Finished Jul 24 05:30:21 PM PDT 24
Peak memory 206944 kb
Host smart-769d59b1-3879-4d4f-bd53-b25a325ef023
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1402474444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.1402474444
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.2349237740
Short name T1957
Test name
Test status
Simulation time 224660927 ps
CPU time 0.83 seconds
Started Jul 24 05:28:03 PM PDT 24
Finished Jul 24 05:28:04 PM PDT 24
Peak memory 206552 kb
Host smart-80e90285-9bed-4474-8369-744fb0a59b22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23492
37740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.2349237740
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.2970176461
Short name T583
Test name
Test status
Simulation time 171419755 ps
CPU time 0.77 seconds
Started Jul 24 05:27:57 PM PDT 24
Finished Jul 24 05:27:59 PM PDT 24
Peak memory 206488 kb
Host smart-dced6bf1-19ea-44b5-b8b7-5f21c94852b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29701
76461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.2970176461
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.434538867
Short name T2521
Test name
Test status
Simulation time 508988627 ps
CPU time 1.42 seconds
Started Jul 24 05:28:03 PM PDT 24
Finished Jul 24 05:28:04 PM PDT 24
Peak memory 206572 kb
Host smart-d200a2ea-7860-4c73-a105-da39d3ddae1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43453
8867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.434538867
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.3410314776
Short name T1877
Test name
Test status
Simulation time 4105083621 ps
CPU time 114.4 seconds
Started Jul 24 05:28:05 PM PDT 24
Finished Jul 24 05:29:59 PM PDT 24
Peak memory 206856 kb
Host smart-ea0caa4e-cd5f-47c6-8457-b45da43cd9c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34103
14776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.3410314776
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.647716839
Short name T1446
Test name
Test status
Simulation time 105775868 ps
CPU time 0.75 seconds
Started Jul 24 05:28:05 PM PDT 24
Finished Jul 24 05:28:06 PM PDT 24
Peak memory 206504 kb
Host smart-fe81c999-4643-47e2-8a96-00efca034a2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=647716839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.647716839
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.2202648774
Short name T947
Test name
Test status
Simulation time 3845203353 ps
CPU time 4.48 seconds
Started Jul 24 05:28:06 PM PDT 24
Finished Jul 24 05:28:10 PM PDT 24
Peak memory 206912 kb
Host smart-a9562c76-7843-446a-bcaf-647d91657791
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2202648774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.2202648774
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.3363741130
Short name T2344
Test name
Test status
Simulation time 13323955098 ps
CPU time 12.76 seconds
Started Jul 24 05:27:57 PM PDT 24
Finished Jul 24 05:28:10 PM PDT 24
Peak memory 206728 kb
Host smart-8fccf3f3-98ee-4ee6-8bb0-c10eda284a17
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3363741130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.3363741130
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.182060
Short name T1803
Test name
Test status
Simulation time 23424474033 ps
CPU time 24.62 seconds
Started Jul 24 05:28:02 PM PDT 24
Finished Jul 24 05:28:27 PM PDT 24
Peak memory 206672 kb
Host smart-5910a8d8-89bf-4949-9b0a-74b22138bec2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=182060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.182060
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.472895138
Short name T2165
Test name
Test status
Simulation time 157933335 ps
CPU time 0.78 seconds
Started Jul 24 05:27:56 PM PDT 24
Finished Jul 24 05:27:57 PM PDT 24
Peak memory 206580 kb
Host smart-8181c354-ddee-456c-a3a5-38a7beb51e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47289
5138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.472895138
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.1446107590
Short name T1783
Test name
Test status
Simulation time 204347402 ps
CPU time 0.84 seconds
Started Jul 24 05:28:00 PM PDT 24
Finished Jul 24 05:28:01 PM PDT 24
Peak memory 206544 kb
Host smart-58be8d5e-3247-4022-aa1c-d3e722ca7bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14461
07590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.1446107590
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.1598681154
Short name T1835
Test name
Test status
Simulation time 226878921 ps
CPU time 0.95 seconds
Started Jul 24 05:28:11 PM PDT 24
Finished Jul 24 05:28:12 PM PDT 24
Peak memory 206540 kb
Host smart-1d8b7a42-a552-4139-ba0d-666eb1d95353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15986
81154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.1598681154
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.1643550470
Short name T1346
Test name
Test status
Simulation time 1361905053 ps
CPU time 2.87 seconds
Started Jul 24 05:27:55 PM PDT 24
Finished Jul 24 05:27:58 PM PDT 24
Peak memory 206972 kb
Host smart-8239c4a1-988a-4410-86ed-6174ecbbcb09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16435
50470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.1643550470
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.786830120
Short name T1544
Test name
Test status
Simulation time 6428664665 ps
CPU time 12.27 seconds
Started Jul 24 05:27:56 PM PDT 24
Finished Jul 24 05:28:09 PM PDT 24
Peak memory 206872 kb
Host smart-e9c4d6ce-df90-4998-93fe-a184b1366792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78683
0120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.786830120
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.3862374444
Short name T2323
Test name
Test status
Simulation time 436089250 ps
CPU time 1.35 seconds
Started Jul 24 05:28:04 PM PDT 24
Finished Jul 24 05:28:05 PM PDT 24
Peak memory 206560 kb
Host smart-1bddb9d4-a09c-450d-9755-6024ae5ff4bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38623
74444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.3862374444
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.2387975831
Short name T1195
Test name
Test status
Simulation time 178554421 ps
CPU time 0.79 seconds
Started Jul 24 05:28:11 PM PDT 24
Finished Jul 24 05:28:12 PM PDT 24
Peak memory 206544 kb
Host smart-4590a6ff-4b45-48ea-a72e-5176168aa026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23879
75831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.2387975831
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.1864857914
Short name T468
Test name
Test status
Simulation time 36035394 ps
CPU time 0.65 seconds
Started Jul 24 05:27:59 PM PDT 24
Finished Jul 24 05:28:00 PM PDT 24
Peak memory 206572 kb
Host smart-87aa16eb-b78f-48af-bab5-808a854ec920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18648
57914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.1864857914
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.54117812
Short name T2414
Test name
Test status
Simulation time 921445061 ps
CPU time 2.14 seconds
Started Jul 24 05:27:54 PM PDT 24
Finished Jul 24 05:27:56 PM PDT 24
Peak memory 206720 kb
Host smart-29959f9b-10de-491f-a09e-24de0bcb615c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54117
812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.54117812
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.3624333578
Short name T430
Test name
Test status
Simulation time 198552678 ps
CPU time 2.18 seconds
Started Jul 24 05:28:03 PM PDT 24
Finished Jul 24 05:28:05 PM PDT 24
Peak memory 206840 kb
Host smart-5575943b-e895-47b2-9390-772fc9d4846b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36243
33578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.3624333578
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.338796592
Short name T2104
Test name
Test status
Simulation time 213419045 ps
CPU time 0.87 seconds
Started Jul 24 05:27:55 PM PDT 24
Finished Jul 24 05:27:56 PM PDT 24
Peak memory 206564 kb
Host smart-e62ef04b-8e39-458a-8ea0-0e0cde2bdccf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33879
6592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.338796592
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.2774241013
Short name T2497
Test name
Test status
Simulation time 154392501 ps
CPU time 0.75 seconds
Started Jul 24 05:27:58 PM PDT 24
Finished Jul 24 05:27:59 PM PDT 24
Peak memory 206528 kb
Host smart-5b1a22c5-851d-4b56-9b63-894bf52578c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27742
41013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.2774241013
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.1504496293
Short name T1309
Test name
Test status
Simulation time 171048635 ps
CPU time 0.84 seconds
Started Jul 24 05:28:02 PM PDT 24
Finished Jul 24 05:28:03 PM PDT 24
Peak memory 206564 kb
Host smart-1ff4f19f-36fb-4ea8-97de-c07c613aa620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15044
96293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.1504496293
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_invalid_sync.1227874846
Short name T94
Test name
Test status
Simulation time 8309230333 ps
CPU time 226.46 seconds
Started Jul 24 05:27:54 PM PDT 24
Finished Jul 24 05:31:41 PM PDT 24
Peak memory 207048 kb
Host smart-a33f6f0d-512c-4502-8996-bffbcae0467f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1227874846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.1227874846
Directory /workspace/32.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/32.usbdev_iso_retraction.102129674
Short name T2372
Test name
Test status
Simulation time 12588849202 ps
CPU time 103.11 seconds
Started Jul 24 05:27:59 PM PDT 24
Finished Jul 24 05:29:43 PM PDT 24
Peak memory 207012 kb
Host smart-40f40a38-5bf3-46bb-859a-43f24e5f07f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10212
9674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.102129674
Directory /workspace/32.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.1930040105
Short name T99
Test name
Test status
Simulation time 256029882 ps
CPU time 0.88 seconds
Started Jul 24 05:28:05 PM PDT 24
Finished Jul 24 05:28:06 PM PDT 24
Peak memory 206520 kb
Host smart-7f82c6f5-d685-48f3-a2d8-a13997757fc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19300
40105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.1930040105
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.2989758642
Short name T1782
Test name
Test status
Simulation time 23296231679 ps
CPU time 22.83 seconds
Started Jul 24 05:27:54 PM PDT 24
Finished Jul 24 05:28:17 PM PDT 24
Peak memory 206628 kb
Host smart-c2355321-3674-4bd5-8c9a-9015ce4a08d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29897
58642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.2989758642
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.3636289582
Short name T2216
Test name
Test status
Simulation time 3398553043 ps
CPU time 3.7 seconds
Started Jul 24 05:28:15 PM PDT 24
Finished Jul 24 05:28:19 PM PDT 24
Peak memory 206704 kb
Host smart-c42fcc1e-b641-4d9e-85af-f0857ac80cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36362
89582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.3636289582
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.424746139
Short name T623
Test name
Test status
Simulation time 9088714219 ps
CPU time 64.42 seconds
Started Jul 24 05:28:15 PM PDT 24
Finished Jul 24 05:29:19 PM PDT 24
Peak memory 206972 kb
Host smart-07e62785-5765-4cc4-ae85-67754f1e6839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42474
6139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.424746139
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.3897695784
Short name T1416
Test name
Test status
Simulation time 6184047542 ps
CPU time 170.03 seconds
Started Jul 24 05:28:13 PM PDT 24
Finished Jul 24 05:31:03 PM PDT 24
Peak memory 206916 kb
Host smart-693a3dc1-f5d4-434f-9995-274ef57d2ed8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3897695784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.3897695784
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.2914623345
Short name T1753
Test name
Test status
Simulation time 239760881 ps
CPU time 0.87 seconds
Started Jul 24 05:28:06 PM PDT 24
Finished Jul 24 05:28:07 PM PDT 24
Peak memory 206452 kb
Host smart-b06e7652-9ab2-443e-a7b4-26618c8d025b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2914623345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.2914623345
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.1882255514
Short name T2043
Test name
Test status
Simulation time 190749358 ps
CPU time 0.85 seconds
Started Jul 24 05:28:06 PM PDT 24
Finished Jul 24 05:28:07 PM PDT 24
Peak memory 206612 kb
Host smart-840cb664-9336-4fd6-be0b-8f2a021afd3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18822
55514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.1882255514
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.177694006
Short name T1508
Test name
Test status
Simulation time 5573117484 ps
CPU time 42.28 seconds
Started Jul 24 05:28:12 PM PDT 24
Finished Jul 24 05:28:55 PM PDT 24
Peak memory 206912 kb
Host smart-acc952de-64cd-45c9-8ef9-dd2b88d0ac8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17769
4006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.177694006
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.1861710648
Short name T1215
Test name
Test status
Simulation time 6217253830 ps
CPU time 41.44 seconds
Started Jul 24 05:28:00 PM PDT 24
Finished Jul 24 05:28:41 PM PDT 24
Peak memory 206888 kb
Host smart-42f0bee9-6b5d-4ad2-9728-f7eb018ebada
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1861710648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.1861710648
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.2825551368
Short name T956
Test name
Test status
Simulation time 153729408 ps
CPU time 0.77 seconds
Started Jul 24 05:28:01 PM PDT 24
Finished Jul 24 05:28:02 PM PDT 24
Peak memory 206552 kb
Host smart-dc951441-69e8-4c7f-9913-d7b5bcd4d34c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2825551368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.2825551368
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.2688272042
Short name T1227
Test name
Test status
Simulation time 144452840 ps
CPU time 0.77 seconds
Started Jul 24 05:28:10 PM PDT 24
Finished Jul 24 05:28:11 PM PDT 24
Peak memory 206616 kb
Host smart-1467898c-ff40-4d11-af4a-f0b7b97c2bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26882
72042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.2688272042
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.4243466056
Short name T121
Test name
Test status
Simulation time 217840741 ps
CPU time 0.87 seconds
Started Jul 24 05:28:05 PM PDT 24
Finished Jul 24 05:28:06 PM PDT 24
Peak memory 206584 kb
Host smart-b2a36254-f920-4390-bc74-8f84a292259b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42434
66056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.4243466056
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.305610980
Short name T2470
Test name
Test status
Simulation time 233062657 ps
CPU time 0.89 seconds
Started Jul 24 05:28:06 PM PDT 24
Finished Jul 24 05:28:07 PM PDT 24
Peak memory 206596 kb
Host smart-7092a346-e08f-4277-916c-3577bebeb568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30561
0980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.305610980
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.3229933244
Short name T2023
Test name
Test status
Simulation time 162095230 ps
CPU time 0.77 seconds
Started Jul 24 05:28:02 PM PDT 24
Finished Jul 24 05:28:03 PM PDT 24
Peak memory 206552 kb
Host smart-ec815da8-901c-4165-959a-0939accd2016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32299
33244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.3229933244
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.3694200309
Short name T593
Test name
Test status
Simulation time 150207109 ps
CPU time 0.76 seconds
Started Jul 24 05:28:03 PM PDT 24
Finished Jul 24 05:28:04 PM PDT 24
Peak memory 206512 kb
Host smart-e76dd85d-501a-4176-883a-08e4d01197fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36942
00309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.3694200309
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.2158474024
Short name T1554
Test name
Test status
Simulation time 205360573 ps
CPU time 0.83 seconds
Started Jul 24 05:28:06 PM PDT 24
Finished Jul 24 05:28:07 PM PDT 24
Peak memory 206656 kb
Host smart-6fab7c62-b49d-4e70-a1ef-7d527631c353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21584
74024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.2158474024
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.671789665
Short name T2214
Test name
Test status
Simulation time 226239013 ps
CPU time 0.93 seconds
Started Jul 24 05:28:03 PM PDT 24
Finished Jul 24 05:28:04 PM PDT 24
Peak memory 206544 kb
Host smart-2106d8e1-fd52-40bc-aeb9-3386867e6360
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=671789665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.671789665
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.2264027157
Short name T180
Test name
Test status
Simulation time 213217352 ps
CPU time 0.83 seconds
Started Jul 24 05:27:50 PM PDT 24
Finished Jul 24 05:27:51 PM PDT 24
Peak memory 206628 kb
Host smart-8ced2cf8-011f-44c1-987a-4255ea7ba19e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22640
27157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.2264027157
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.54199733
Short name T2126
Test name
Test status
Simulation time 43280053 ps
CPU time 0.66 seconds
Started Jul 24 05:28:10 PM PDT 24
Finished Jul 24 05:28:11 PM PDT 24
Peak memory 206776 kb
Host smart-c36794ca-2df5-4b56-a4fc-ded6de215a57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54199
733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.54199733
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.999013378
Short name T2605
Test name
Test status
Simulation time 14992288641 ps
CPU time 35.4 seconds
Started Jul 24 05:28:17 PM PDT 24
Finished Jul 24 05:28:52 PM PDT 24
Peak memory 206980 kb
Host smart-e41059d8-db26-4320-ae1c-e85bbd4ecc1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99901
3378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.999013378
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.2071229655
Short name T776
Test name
Test status
Simulation time 146148153 ps
CPU time 0.76 seconds
Started Jul 24 05:28:11 PM PDT 24
Finished Jul 24 05:28:12 PM PDT 24
Peak memory 206588 kb
Host smart-5573131a-cabd-4a44-9221-4c5af7709dd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20712
29655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.2071229655
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.3868059448
Short name T527
Test name
Test status
Simulation time 253590636 ps
CPU time 0.87 seconds
Started Jul 24 05:28:10 PM PDT 24
Finished Jul 24 05:28:12 PM PDT 24
Peak memory 206544 kb
Host smart-57c8d5f4-0065-40fb-a3ec-96ae5008be62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38680
59448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3868059448
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.3880067546
Short name T2200
Test name
Test status
Simulation time 191587069 ps
CPU time 0.84 seconds
Started Jul 24 05:28:11 PM PDT 24
Finished Jul 24 05:28:12 PM PDT 24
Peak memory 206584 kb
Host smart-3eb74dd5-e1f2-4ade-84ab-39fe76be176d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38800
67546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.3880067546
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.3813780050
Short name T2219
Test name
Test status
Simulation time 182299632 ps
CPU time 0.79 seconds
Started Jul 24 05:28:18 PM PDT 24
Finished Jul 24 05:28:19 PM PDT 24
Peak memory 206600 kb
Host smart-d737993a-c713-4284-8bdb-e99ec8828362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38137
80050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.3813780050
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.3787439092
Short name T1656
Test name
Test status
Simulation time 170139560 ps
CPU time 0.83 seconds
Started Jul 24 05:28:13 PM PDT 24
Finished Jul 24 05:28:14 PM PDT 24
Peak memory 206580 kb
Host smart-5f285cc5-da37-4776-bdc1-71d345787706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37874
39092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.3787439092
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.1800875993
Short name T149
Test name
Test status
Simulation time 169662257 ps
CPU time 0.76 seconds
Started Jul 24 05:28:16 PM PDT 24
Finished Jul 24 05:28:17 PM PDT 24
Peak memory 206588 kb
Host smart-d9350926-db75-409d-aac0-3f1f2c7e04b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18008
75993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.1800875993
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.489692673
Short name T90
Test name
Test status
Simulation time 150214712 ps
CPU time 0.76 seconds
Started Jul 24 05:28:22 PM PDT 24
Finished Jul 24 05:28:23 PM PDT 24
Peak memory 206532 kb
Host smart-18561af2-02e9-4c49-aeb3-305f031cdf8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48969
2673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.489692673
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.2663060096
Short name T2661
Test name
Test status
Simulation time 212945324 ps
CPU time 0.85 seconds
Started Jul 24 05:28:09 PM PDT 24
Finished Jul 24 05:28:10 PM PDT 24
Peak memory 206548 kb
Host smart-ffd28ff8-689a-401a-82c6-047cce9c24e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26630
60096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2663060096
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.2108930284
Short name T2575
Test name
Test status
Simulation time 6116162090 ps
CPU time 56.01 seconds
Started Jul 24 05:28:07 PM PDT 24
Finished Jul 24 05:29:04 PM PDT 24
Peak memory 206864 kb
Host smart-eb8f0c37-a575-4b7d-9216-cc96b0b0b110
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2108930284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.2108930284
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.4109639311
Short name T1486
Test name
Test status
Simulation time 151868956 ps
CPU time 0.79 seconds
Started Jul 24 05:28:14 PM PDT 24
Finished Jul 24 05:28:15 PM PDT 24
Peak memory 206584 kb
Host smart-73985dc8-3dd5-4745-807b-550587b698ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41096
39311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.4109639311
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.3922605022
Short name T1428
Test name
Test status
Simulation time 195553416 ps
CPU time 0.84 seconds
Started Jul 24 05:27:57 PM PDT 24
Finished Jul 24 05:27:58 PM PDT 24
Peak memory 206592 kb
Host smart-0bacfce4-ec69-492e-a008-c8e30f8349a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39226
05022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.3922605022
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.472138312
Short name T76
Test name
Test status
Simulation time 491616652 ps
CPU time 1.27 seconds
Started Jul 24 05:28:21 PM PDT 24
Finished Jul 24 05:28:22 PM PDT 24
Peak memory 206624 kb
Host smart-5fd880e4-6a14-4c27-8343-7bce87bff108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47213
8312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.472138312
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.100123530
Short name T400
Test name
Test status
Simulation time 5140234016 ps
CPU time 37.17 seconds
Started Jul 24 05:28:26 PM PDT 24
Finished Jul 24 05:29:03 PM PDT 24
Peak memory 207144 kb
Host smart-33bcb843-f962-4db5-b6ff-0ed0facaa3b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10012
3530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.100123530
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.2212066346
Short name T1376
Test name
Test status
Simulation time 99099097 ps
CPU time 0.72 seconds
Started Jul 24 05:28:12 PM PDT 24
Finished Jul 24 05:28:13 PM PDT 24
Peak memory 206600 kb
Host smart-ec89f334-007a-4e26-b00c-a4f9cadbcfdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2212066346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.2212066346
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.3595524057
Short name T628
Test name
Test status
Simulation time 4416974496 ps
CPU time 4.78 seconds
Started Jul 24 05:28:13 PM PDT 24
Finished Jul 24 05:28:18 PM PDT 24
Peak memory 206852 kb
Host smart-eb7a7d22-e943-49ac-adb7-6cc8afb38069
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3595524057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.3595524057
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.4083127509
Short name T825
Test name
Test status
Simulation time 13371653471 ps
CPU time 11.69 seconds
Started Jul 24 05:28:00 PM PDT 24
Finished Jul 24 05:28:12 PM PDT 24
Peak memory 206944 kb
Host smart-9e6f43df-03e9-478d-925a-4ecd5a1bd64c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4083127509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.4083127509
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.2406903781
Short name T1261
Test name
Test status
Simulation time 23372053369 ps
CPU time 25.02 seconds
Started Jul 24 05:28:14 PM PDT 24
Finished Jul 24 05:28:39 PM PDT 24
Peak memory 206724 kb
Host smart-a2063213-91c5-4e0e-9397-5a44e36cd206
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2406903781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.2406903781
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.4126955967
Short name T204
Test name
Test status
Simulation time 151108685 ps
CPU time 0.77 seconds
Started Jul 24 05:28:07 PM PDT 24
Finished Jul 24 05:28:08 PM PDT 24
Peak memory 206576 kb
Host smart-ddda05a8-1b1c-4473-bf41-4ec3cc1d2af3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41269
55967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.4126955967
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.2013952012
Short name T708
Test name
Test status
Simulation time 167175833 ps
CPU time 0.78 seconds
Started Jul 24 05:28:14 PM PDT 24
Finished Jul 24 05:28:15 PM PDT 24
Peak memory 206588 kb
Host smart-a3bc1a2f-feba-4301-a26c-b989e0847362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20139
52012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.2013952012
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.781872325
Short name T1340
Test name
Test status
Simulation time 302763296 ps
CPU time 1.12 seconds
Started Jul 24 05:28:09 PM PDT 24
Finished Jul 24 05:28:10 PM PDT 24
Peak memory 206544 kb
Host smart-3ab9d6ba-7811-4a06-9cd7-fba94f24221c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78187
2325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.781872325
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.1075034757
Short name T1344
Test name
Test status
Simulation time 1043805808 ps
CPU time 2.33 seconds
Started Jul 24 05:28:07 PM PDT 24
Finished Jul 24 05:28:10 PM PDT 24
Peak memory 206788 kb
Host smart-3fd44fea-45fa-4109-bfac-088c4ed335ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10750
34757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.1075034757
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.2723398260
Short name T2703
Test name
Test status
Simulation time 21968069021 ps
CPU time 48.72 seconds
Started Jul 24 05:28:06 PM PDT 24
Finished Jul 24 05:28:55 PM PDT 24
Peak memory 206964 kb
Host smart-cc24139c-ef1f-42c8-a85f-b68339da1c42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27233
98260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.2723398260
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.1289481551
Short name T590
Test name
Test status
Simulation time 410387024 ps
CPU time 1.25 seconds
Started Jul 24 05:27:58 PM PDT 24
Finished Jul 24 05:28:00 PM PDT 24
Peak memory 206572 kb
Host smart-ac9e7ba2-e32a-421b-847c-db1f3ddae975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12894
81551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.1289481551
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.343550520
Short name T1036
Test name
Test status
Simulation time 203281444 ps
CPU time 0.81 seconds
Started Jul 24 05:28:12 PM PDT 24
Finished Jul 24 05:28:13 PM PDT 24
Peak memory 206528 kb
Host smart-6df614c2-2853-4ec8-a24c-de9343dd5cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34355
0520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.343550520
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.2859689476
Short name T1934
Test name
Test status
Simulation time 64302285 ps
CPU time 0.68 seconds
Started Jul 24 05:28:00 PM PDT 24
Finished Jul 24 05:28:01 PM PDT 24
Peak memory 206588 kb
Host smart-aaa158cc-982a-4875-8d48-34efff629ba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28596
89476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.2859689476
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.478418417
Short name T1350
Test name
Test status
Simulation time 903882030 ps
CPU time 1.96 seconds
Started Jul 24 05:28:03 PM PDT 24
Finished Jul 24 05:28:06 PM PDT 24
Peak memory 206740 kb
Host smart-e98d46f3-cbd5-49ee-a2d1-fd0ecde32083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47841
8417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.478418417
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.2538773103
Short name T861
Test name
Test status
Simulation time 314003309 ps
CPU time 2.31 seconds
Started Jul 24 05:28:11 PM PDT 24
Finished Jul 24 05:28:13 PM PDT 24
Peak memory 206820 kb
Host smart-32f59060-6192-49ef-9e20-81b1e0e8a44e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25387
73103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.2538773103
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.1125077414
Short name T1173
Test name
Test status
Simulation time 188300188 ps
CPU time 0.83 seconds
Started Jul 24 05:28:16 PM PDT 24
Finished Jul 24 05:28:17 PM PDT 24
Peak memory 206596 kb
Host smart-f134da07-6fba-41d3-b153-b7d7eb26c762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11250
77414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.1125077414
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.836008142
Short name T2590
Test name
Test status
Simulation time 148931120 ps
CPU time 0.75 seconds
Started Jul 24 05:28:06 PM PDT 24
Finished Jul 24 05:28:07 PM PDT 24
Peak memory 206540 kb
Host smart-2b551b7c-070f-48b7-91b1-be5acab403e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83600
8142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.836008142
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.3395007192
Short name T1369
Test name
Test status
Simulation time 229533586 ps
CPU time 0.87 seconds
Started Jul 24 05:28:22 PM PDT 24
Finished Jul 24 05:28:23 PM PDT 24
Peak memory 206616 kb
Host smart-01a77609-1af0-4933-9d5c-8a0cf71161b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33950
07192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.3395007192
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_invalid_sync.3084236441
Short name T2677
Test name
Test status
Simulation time 6613807582 ps
CPU time 48.93 seconds
Started Jul 24 05:28:08 PM PDT 24
Finished Jul 24 05:28:57 PM PDT 24
Peak memory 206948 kb
Host smart-699a9171-a672-4c6e-a603-2f7eec1eb364
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3084236441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.3084236441
Directory /workspace/33.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/33.usbdev_iso_retraction.1802977562
Short name T1538
Test name
Test status
Simulation time 9622644580 ps
CPU time 76.81 seconds
Started Jul 24 05:28:10 PM PDT 24
Finished Jul 24 05:29:28 PM PDT 24
Peak memory 206864 kb
Host smart-da7286e5-d8e9-42d1-87da-f5906f6bf552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18029
77562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.1802977562
Directory /workspace/33.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.3174905750
Short name T1905
Test name
Test status
Simulation time 256692250 ps
CPU time 0.91 seconds
Started Jul 24 05:28:23 PM PDT 24
Finished Jul 24 05:28:24 PM PDT 24
Peak memory 206544 kb
Host smart-2adcd146-5c06-4ea2-929e-e4023ecffa51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31749
05750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.3174905750
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.4201664419
Short name T1287
Test name
Test status
Simulation time 23320043430 ps
CPU time 21.1 seconds
Started Jul 24 05:28:09 PM PDT 24
Finished Jul 24 05:28:30 PM PDT 24
Peak memory 206680 kb
Host smart-d2f54cd6-f056-4167-bc46-08e36b19a429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42016
64419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.4201664419
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.1767042025
Short name T2048
Test name
Test status
Simulation time 3344514050 ps
CPU time 3.73 seconds
Started Jul 24 05:28:30 PM PDT 24
Finished Jul 24 05:28:34 PM PDT 24
Peak memory 206744 kb
Host smart-8531ba97-dc8e-499f-8688-277b84ac281a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17670
42025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.1767042025
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.1062092164
Short name T1563
Test name
Test status
Simulation time 8495201694 ps
CPU time 78.59 seconds
Started Jul 24 05:28:08 PM PDT 24
Finished Jul 24 05:29:27 PM PDT 24
Peak memory 206984 kb
Host smart-8e1895d7-1eac-4f4b-95d1-40627ea21258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10620
92164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.1062092164
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.1070257707
Short name T377
Test name
Test status
Simulation time 4418247729 ps
CPU time 29.9 seconds
Started Jul 24 05:28:10 PM PDT 24
Finished Jul 24 05:28:41 PM PDT 24
Peak memory 206920 kb
Host smart-ee67a5e8-b5f3-40d3-9102-7c22218b3134
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1070257707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.1070257707
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.639451322
Short name T2042
Test name
Test status
Simulation time 258031311 ps
CPU time 0.93 seconds
Started Jul 24 05:28:08 PM PDT 24
Finished Jul 24 05:28:10 PM PDT 24
Peak memory 206572 kb
Host smart-78580379-5e8b-4a13-9b25-6090b60dfed0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=639451322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.639451322
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.3233174700
Short name T1595
Test name
Test status
Simulation time 185590125 ps
CPU time 0.87 seconds
Started Jul 24 05:28:04 PM PDT 24
Finished Jul 24 05:28:05 PM PDT 24
Peak memory 206544 kb
Host smart-ede3b6bc-f78b-4d49-a2a9-3757f45487fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32331
74700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.3233174700
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.3269199588
Short name T2302
Test name
Test status
Simulation time 3699483234 ps
CPU time 25.9 seconds
Started Jul 24 05:28:07 PM PDT 24
Finished Jul 24 05:28:33 PM PDT 24
Peak memory 206964 kb
Host smart-23d98584-f942-40f5-8b06-20c4b106b99b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32691
99588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.3269199588
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.2541763963
Short name T1907
Test name
Test status
Simulation time 3435658009 ps
CPU time 95.41 seconds
Started Jul 24 05:28:14 PM PDT 24
Finished Jul 24 05:29:49 PM PDT 24
Peak memory 206908 kb
Host smart-ee1bba0d-c02b-429d-ad44-f9df91fc012a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2541763963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.2541763963
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.2230106286
Short name T1961
Test name
Test status
Simulation time 172845783 ps
CPU time 0.78 seconds
Started Jul 24 05:28:18 PM PDT 24
Finished Jul 24 05:28:19 PM PDT 24
Peak memory 206448 kb
Host smart-a213a60f-0d3f-46f5-9aee-1b15f88a12e1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2230106286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.2230106286
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.2688453166
Short name T440
Test name
Test status
Simulation time 142015488 ps
CPU time 0.79 seconds
Started Jul 24 05:28:15 PM PDT 24
Finished Jul 24 05:28:16 PM PDT 24
Peak memory 206516 kb
Host smart-7b5f4874-d9e6-4b4a-9606-3ad901bfcd30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26884
53166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.2688453166
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.95362729
Short name T1901
Test name
Test status
Simulation time 196169564 ps
CPU time 0.83 seconds
Started Jul 24 05:28:11 PM PDT 24
Finished Jul 24 05:28:17 PM PDT 24
Peak memory 206652 kb
Host smart-4456342f-fe0a-4bdb-aa49-6edca4261078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95362
729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.95362729
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.2507860573
Short name T1311
Test name
Test status
Simulation time 162337922 ps
CPU time 0.79 seconds
Started Jul 24 05:28:15 PM PDT 24
Finished Jul 24 05:28:16 PM PDT 24
Peak memory 206512 kb
Host smart-ebefd19b-2492-467f-947d-1c18883938e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25078
60573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.2507860573
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.2591506726
Short name T2706
Test name
Test status
Simulation time 155188887 ps
CPU time 0.78 seconds
Started Jul 24 05:28:13 PM PDT 24
Finished Jul 24 05:28:14 PM PDT 24
Peak memory 206640 kb
Host smart-68de8032-7cf7-445b-a94b-98886400734f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25915
06726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.2591506726
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.3160810663
Short name T1571
Test name
Test status
Simulation time 181799360 ps
CPU time 0.79 seconds
Started Jul 24 05:28:11 PM PDT 24
Finished Jul 24 05:28:12 PM PDT 24
Peak memory 206588 kb
Host smart-1723c1c6-4639-4436-bbb8-ef8e7977d26b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31608
10663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.3160810663
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.3069635006
Short name T1393
Test name
Test status
Simulation time 162284575 ps
CPU time 0.78 seconds
Started Jul 24 05:28:05 PM PDT 24
Finished Jul 24 05:28:05 PM PDT 24
Peak memory 206464 kb
Host smart-4ce6be26-f927-4e58-a39f-81ccdcd6de34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30696
35006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.3069635006
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.4232501610
Short name T2292
Test name
Test status
Simulation time 253709969 ps
CPU time 0.94 seconds
Started Jul 24 05:28:19 PM PDT 24
Finished Jul 24 05:28:20 PM PDT 24
Peak memory 206580 kb
Host smart-e271d79a-7c6d-4da2-b3fa-c6fc67ffffe2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4232501610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.4232501610
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.1910870194
Short name T1533
Test name
Test status
Simulation time 178713586 ps
CPU time 0.79 seconds
Started Jul 24 05:28:11 PM PDT 24
Finished Jul 24 05:28:12 PM PDT 24
Peak memory 206612 kb
Host smart-3ac3ad4c-322f-4b76-940e-4fa8d15cd112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19108
70194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.1910870194
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.2479431050
Short name T28
Test name
Test status
Simulation time 27533311 ps
CPU time 0.65 seconds
Started Jul 24 05:28:05 PM PDT 24
Finished Jul 24 05:28:06 PM PDT 24
Peak memory 206596 kb
Host smart-3f2294e5-f965-40e1-aa28-786645bbd792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24794
31050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.2479431050
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.3972625119
Short name T962
Test name
Test status
Simulation time 7550696469 ps
CPU time 16.56 seconds
Started Jul 24 05:28:18 PM PDT 24
Finished Jul 24 05:28:35 PM PDT 24
Peak memory 215120 kb
Host smart-140b797e-cab3-4c3c-be03-0646c62085e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39726
25119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.3972625119
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.788865679
Short name T2327
Test name
Test status
Simulation time 143736915 ps
CPU time 0.77 seconds
Started Jul 24 05:28:06 PM PDT 24
Finished Jul 24 05:28:07 PM PDT 24
Peak memory 206384 kb
Host smart-4825dea2-93b5-48b4-b578-a63815192ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78886
5679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.788865679
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.1939065172
Short name T2347
Test name
Test status
Simulation time 187182269 ps
CPU time 0.92 seconds
Started Jul 24 05:28:12 PM PDT 24
Finished Jul 24 05:28:16 PM PDT 24
Peak memory 206468 kb
Host smart-6921564d-edbc-4a2b-a0c7-78e08c947075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19390
65172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.1939065172
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.1730780458
Short name T1856
Test name
Test status
Simulation time 242131018 ps
CPU time 0.93 seconds
Started Jul 24 05:28:22 PM PDT 24
Finished Jul 24 05:28:23 PM PDT 24
Peak memory 206556 kb
Host smart-8459c05b-125e-4fbb-8e26-039f49b0022c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17307
80458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.1730780458
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.128839907
Short name T2141
Test name
Test status
Simulation time 183062083 ps
CPU time 0.87 seconds
Started Jul 24 05:28:02 PM PDT 24
Finished Jul 24 05:28:03 PM PDT 24
Peak memory 206572 kb
Host smart-eda36ba1-97d2-4229-850f-db9159180ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12883
9907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.128839907
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.211283875
Short name T1971
Test name
Test status
Simulation time 196388760 ps
CPU time 0.87 seconds
Started Jul 24 05:28:11 PM PDT 24
Finished Jul 24 05:28:12 PM PDT 24
Peak memory 206472 kb
Host smart-4f65c43b-360c-4984-9d14-efa441023d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21128
3875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.211283875
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.2519470944
Short name T859
Test name
Test status
Simulation time 168936264 ps
CPU time 0.8 seconds
Started Jul 24 05:28:02 PM PDT 24
Finished Jul 24 05:28:03 PM PDT 24
Peak memory 206588 kb
Host smart-6442a7bb-8a79-422f-af91-78326278666b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25194
70944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.2519470944
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.3889047531
Short name T988
Test name
Test status
Simulation time 159940563 ps
CPU time 0.81 seconds
Started Jul 24 05:28:11 PM PDT 24
Finished Jul 24 05:28:13 PM PDT 24
Peak memory 206552 kb
Host smart-2be79572-1771-4a97-9b29-72aa30da14f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38890
47531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.3889047531
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.2671876091
Short name T2367
Test name
Test status
Simulation time 267260462 ps
CPU time 0.95 seconds
Started Jul 24 05:28:00 PM PDT 24
Finished Jul 24 05:28:02 PM PDT 24
Peak memory 206552 kb
Host smart-5e249db9-9903-45b2-8638-c4143eaa7cad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26718
76091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.2671876091
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.3938295517
Short name T911
Test name
Test status
Simulation time 5890207806 ps
CPU time 56.32 seconds
Started Jul 24 05:28:20 PM PDT 24
Finished Jul 24 05:29:16 PM PDT 24
Peak memory 206856 kb
Host smart-4cb9bd68-3363-43cb-869a-ff27b93cda00
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3938295517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.3938295517
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.1875307779
Short name T392
Test name
Test status
Simulation time 161828946 ps
CPU time 0.76 seconds
Started Jul 24 05:28:15 PM PDT 24
Finished Jul 24 05:28:16 PM PDT 24
Peak memory 206600 kb
Host smart-f56e910b-0326-473b-87d0-53de95f7160d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18753
07779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.1875307779
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.2878130740
Short name T2086
Test name
Test status
Simulation time 222315251 ps
CPU time 0.92 seconds
Started Jul 24 05:28:07 PM PDT 24
Finished Jul 24 05:28:08 PM PDT 24
Peak memory 206528 kb
Host smart-74023f4c-6283-46f7-8237-ef66be14c537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28781
30740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.2878130740
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.929433319
Short name T912
Test name
Test status
Simulation time 1054013583 ps
CPU time 2.25 seconds
Started Jul 24 05:28:10 PM PDT 24
Finished Jul 24 05:28:13 PM PDT 24
Peak memory 206800 kb
Host smart-0e7ec257-a61d-4beb-bb4d-67364d30a79b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92943
3319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.929433319
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.3156057525
Short name T331
Test name
Test status
Simulation time 6244124160 ps
CPU time 173.29 seconds
Started Jul 24 05:28:19 PM PDT 24
Finished Jul 24 05:31:12 PM PDT 24
Peak memory 206872 kb
Host smart-21fd9cff-981c-4e08-b050-b3a3164842b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31560
57525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.3156057525
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.3312337407
Short name T888
Test name
Test status
Simulation time 82474536 ps
CPU time 0.74 seconds
Started Jul 24 05:28:35 PM PDT 24
Finished Jul 24 05:28:35 PM PDT 24
Peak memory 206408 kb
Host smart-86169a9d-b3ce-4f21-8909-8822fa837ec5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3312337407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.3312337407
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.1054938844
Short name T2074
Test name
Test status
Simulation time 4061980297 ps
CPU time 4.39 seconds
Started Jul 24 05:28:13 PM PDT 24
Finished Jul 24 05:28:18 PM PDT 24
Peak memory 206704 kb
Host smart-b7d83d3c-fc2e-4d0b-a0be-90bc1c669bc5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1054938844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.1054938844
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.3456867459
Short name T653
Test name
Test status
Simulation time 13344720406 ps
CPU time 13.91 seconds
Started Jul 24 05:28:13 PM PDT 24
Finished Jul 24 05:28:27 PM PDT 24
Peak memory 206700 kb
Host smart-f81affcd-8993-4908-9eee-58f28325e5ec
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3456867459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.3456867459
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.720489562
Short name T1601
Test name
Test status
Simulation time 23444561569 ps
CPU time 24.04 seconds
Started Jul 24 05:28:16 PM PDT 24
Finished Jul 24 05:28:40 PM PDT 24
Peak memory 206896 kb
Host smart-e39aec24-9ff2-4c10-a146-6b059eba5de5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=720489562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.720489562
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.129225123
Short name T395
Test name
Test status
Simulation time 219434475 ps
CPU time 0.98 seconds
Started Jul 24 05:28:17 PM PDT 24
Finished Jul 24 05:28:18 PM PDT 24
Peak memory 206564 kb
Host smart-5d4ac271-01f8-45b9-b23e-1c55fbf23bca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12922
5123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.129225123
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.1183729509
Short name T479
Test name
Test status
Simulation time 145754954 ps
CPU time 0.76 seconds
Started Jul 24 05:28:27 PM PDT 24
Finished Jul 24 05:28:27 PM PDT 24
Peak memory 206564 kb
Host smart-947b753b-516c-432c-a298-a63270c69b74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11837
29509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.1183729509
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.1013737066
Short name T1651
Test name
Test status
Simulation time 539413569 ps
CPU time 1.52 seconds
Started Jul 24 05:28:22 PM PDT 24
Finished Jul 24 05:28:23 PM PDT 24
Peak memory 206776 kb
Host smart-c53846ac-e3b9-412a-bb8c-7815fbdac713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10137
37066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.1013737066
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.2463807554
Short name T501
Test name
Test status
Simulation time 1225002225 ps
CPU time 2.51 seconds
Started Jul 24 05:28:12 PM PDT 24
Finished Jul 24 05:28:15 PM PDT 24
Peak memory 206832 kb
Host smart-6fa60c32-e531-4ece-8250-848ee0374948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24638
07554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.2463807554
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.3978782304
Short name T1152
Test name
Test status
Simulation time 23008865904 ps
CPU time 43.1 seconds
Started Jul 24 05:28:29 PM PDT 24
Finished Jul 24 05:29:12 PM PDT 24
Peak memory 206960 kb
Host smart-667806a1-5a08-4f2e-9084-bce5b9c08a79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39787
82304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.3978782304
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.1532127284
Short name T539
Test name
Test status
Simulation time 374552422 ps
CPU time 1.26 seconds
Started Jul 24 05:28:13 PM PDT 24
Finished Jul 24 05:28:14 PM PDT 24
Peak memory 206636 kb
Host smart-4955ff85-0acf-4c2e-b1ff-df148dec72ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15321
27284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.1532127284
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.2343950132
Short name T34
Test name
Test status
Simulation time 170640129 ps
CPU time 0.77 seconds
Started Jul 24 05:28:21 PM PDT 24
Finished Jul 24 05:28:22 PM PDT 24
Peak memory 206548 kb
Host smart-8a688095-9384-4f62-ace1-c374526dc9ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23439
50132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.2343950132
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.1822089018
Short name T535
Test name
Test status
Simulation time 94954043 ps
CPU time 0.7 seconds
Started Jul 24 05:28:11 PM PDT 24
Finished Jul 24 05:28:12 PM PDT 24
Peak memory 206588 kb
Host smart-c6f0bdb5-f4d4-45ad-b422-e00bb6379746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18220
89018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.1822089018
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.827080375
Short name T2154
Test name
Test status
Simulation time 770422764 ps
CPU time 1.97 seconds
Started Jul 24 05:28:23 PM PDT 24
Finished Jul 24 05:28:25 PM PDT 24
Peak memory 206684 kb
Host smart-710a1807-a657-4ec5-8a6a-53a4600bb191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82708
0375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.827080375
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.4067077889
Short name T781
Test name
Test status
Simulation time 171966870 ps
CPU time 1.85 seconds
Started Jul 24 05:28:09 PM PDT 24
Finished Jul 24 05:28:11 PM PDT 24
Peak memory 206816 kb
Host smart-4e695338-b344-4d66-a603-cab066697697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40670
77889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.4067077889
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.1690055043
Short name T570
Test name
Test status
Simulation time 167652398 ps
CPU time 0.81 seconds
Started Jul 24 05:28:15 PM PDT 24
Finished Jul 24 05:28:16 PM PDT 24
Peak memory 206568 kb
Host smart-9976408c-23d0-4951-a14a-266c32ed1985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16900
55043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.1690055043
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.524764261
Short name T1419
Test name
Test status
Simulation time 150148351 ps
CPU time 0.77 seconds
Started Jul 24 05:28:19 PM PDT 24
Finished Jul 24 05:28:20 PM PDT 24
Peak memory 206596 kb
Host smart-eacfd9b9-81df-4999-ac22-ab8a63c185cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52476
4261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.524764261
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.1373173762
Short name T1584
Test name
Test status
Simulation time 173447486 ps
CPU time 0.83 seconds
Started Jul 24 05:28:17 PM PDT 24
Finished Jul 24 05:28:19 PM PDT 24
Peak memory 206572 kb
Host smart-94169d16-5dcd-4532-afd4-4648f2f584fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13731
73762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.1373173762
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.2651143986
Short name T206
Test name
Test status
Simulation time 7902253045 ps
CPU time 73.48 seconds
Started Jul 24 05:28:25 PM PDT 24
Finished Jul 24 05:29:39 PM PDT 24
Peak memory 206740 kb
Host smart-4aee69dc-7720-4a88-8632-73a14a41caeb
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2651143986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.2651143986
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/34.usbdev_iso_retraction.1233522935
Short name T1868
Test name
Test status
Simulation time 6912914065 ps
CPU time 60.07 seconds
Started Jul 24 05:28:37 PM PDT 24
Finished Jul 24 05:29:38 PM PDT 24
Peak memory 206900 kb
Host smart-8ba102eb-9d31-45cb-a075-50b3a2028335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12335
22935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_iso_retraction.1233522935
Directory /workspace/34.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.2534568423
Short name T1250
Test name
Test status
Simulation time 206329067 ps
CPU time 0.92 seconds
Started Jul 24 05:28:12 PM PDT 24
Finished Jul 24 05:28:13 PM PDT 24
Peak memory 206512 kb
Host smart-f1162b33-8596-4384-b8ee-632ea567e5c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25345
68423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.2534568423
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.3584614323
Short name T1122
Test name
Test status
Simulation time 23380151089 ps
CPU time 22.28 seconds
Started Jul 24 05:28:20 PM PDT 24
Finished Jul 24 05:28:42 PM PDT 24
Peak memory 206696 kb
Host smart-179fab06-65e5-4dc1-8d11-351a1961b824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35846
14323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.3584614323
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.2496704592
Short name T2135
Test name
Test status
Simulation time 3313399478 ps
CPU time 3.83 seconds
Started Jul 24 05:28:14 PM PDT 24
Finished Jul 24 05:28:18 PM PDT 24
Peak memory 206756 kb
Host smart-ee92214b-77f7-4237-aa99-6b9e39be6338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24967
04592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.2496704592
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.4116913710
Short name T831
Test name
Test status
Simulation time 6922054860 ps
CPU time 177.69 seconds
Started Jul 24 05:28:13 PM PDT 24
Finished Jul 24 05:31:11 PM PDT 24
Peak memory 206916 kb
Host smart-a3f265e0-9cd1-46bc-8fdf-d4f504570821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41169
13710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.4116913710
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.1817785603
Short name T1698
Test name
Test status
Simulation time 5114900882 ps
CPU time 142.38 seconds
Started Jul 24 05:28:18 PM PDT 24
Finished Jul 24 05:30:45 PM PDT 24
Peak memory 206888 kb
Host smart-7612df1c-2a7f-467d-aa7e-6ca255cf1c86
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1817785603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.1817785603
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.4037352001
Short name T1196
Test name
Test status
Simulation time 246097604 ps
CPU time 0.87 seconds
Started Jul 24 05:28:15 PM PDT 24
Finished Jul 24 05:28:16 PM PDT 24
Peak memory 206592 kb
Host smart-b41c5453-7e07-4c2b-a300-a6ce4c8c1e96
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4037352001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.4037352001
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.3582731281
Short name T2353
Test name
Test status
Simulation time 203840570 ps
CPU time 0.9 seconds
Started Jul 24 05:28:12 PM PDT 24
Finished Jul 24 05:28:13 PM PDT 24
Peak memory 206476 kb
Host smart-7cd7c748-40a2-4bf6-b039-59b898f92efa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35827
31281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.3582731281
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.563667482
Short name T1530
Test name
Test status
Simulation time 4604166036 ps
CPU time 127.06 seconds
Started Jul 24 05:28:22 PM PDT 24
Finished Jul 24 05:30:29 PM PDT 24
Peak memory 206876 kb
Host smart-199622ed-1f29-459b-b970-d318692675da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56366
7482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.563667482
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.3151639599
Short name T1878
Test name
Test status
Simulation time 3332501712 ps
CPU time 23.91 seconds
Started Jul 24 05:28:28 PM PDT 24
Finished Jul 24 05:28:52 PM PDT 24
Peak memory 206944 kb
Host smart-5fa80a26-b86a-4f82-8b2f-154efb65c17f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3151639599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.3151639599
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.1472719652
Short name T1188
Test name
Test status
Simulation time 159113384 ps
CPU time 0.81 seconds
Started Jul 24 05:28:04 PM PDT 24
Finished Jul 24 05:28:05 PM PDT 24
Peak memory 206568 kb
Host smart-21830b0a-a7c9-4227-9c33-1cb3ecd08e5b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1472719652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.1472719652
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.3959883930
Short name T2555
Test name
Test status
Simulation time 167953249 ps
CPU time 0.77 seconds
Started Jul 24 05:28:10 PM PDT 24
Finished Jul 24 05:28:16 PM PDT 24
Peak memory 206476 kb
Host smart-f872efa1-4b3d-4e7c-a656-b2651f5a76d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39598
83930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.3959883930
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.2963438885
Short name T2232
Test name
Test status
Simulation time 231355925 ps
CPU time 0.92 seconds
Started Jul 24 05:28:15 PM PDT 24
Finished Jul 24 05:28:21 PM PDT 24
Peak memory 206572 kb
Host smart-95feee1c-465a-43ad-8404-8c82ee139dfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29634
38885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.2963438885
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.2990863324
Short name T1694
Test name
Test status
Simulation time 162788850 ps
CPU time 0.81 seconds
Started Jul 24 05:28:11 PM PDT 24
Finished Jul 24 05:28:12 PM PDT 24
Peak memory 206600 kb
Host smart-5c8ce747-f9ab-4b37-833d-a94844fa3bea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29908
63324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.2990863324
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.2524188101
Short name T1589
Test name
Test status
Simulation time 175953161 ps
CPU time 0.83 seconds
Started Jul 24 05:28:17 PM PDT 24
Finished Jul 24 05:28:18 PM PDT 24
Peak memory 206576 kb
Host smart-9f9e6862-9577-41c6-84b0-926725a834f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25241
88101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.2524188101
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.77086868
Short name T1114
Test name
Test status
Simulation time 191489186 ps
CPU time 0.8 seconds
Started Jul 24 05:28:37 PM PDT 24
Finished Jul 24 05:28:38 PM PDT 24
Peak memory 206592 kb
Host smart-efa25f6b-2a15-452d-a695-03344749811d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77086
868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.77086868
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.917136061
Short name T162
Test name
Test status
Simulation time 149261478 ps
CPU time 0.78 seconds
Started Jul 24 05:28:15 PM PDT 24
Finished Jul 24 05:28:16 PM PDT 24
Peak memory 206576 kb
Host smart-1b829e13-8b74-4f40-80f9-482c90a7591e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91713
6061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.917136061
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.3206980288
Short name T2395
Test name
Test status
Simulation time 198823106 ps
CPU time 0.89 seconds
Started Jul 24 05:28:12 PM PDT 24
Finished Jul 24 05:28:13 PM PDT 24
Peak memory 206596 kb
Host smart-aa098bbd-16a3-4287-ba15-d8f8e3d62a6d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3206980288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.3206980288
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.3396232841
Short name T824
Test name
Test status
Simulation time 172274018 ps
CPU time 0.77 seconds
Started Jul 24 05:28:11 PM PDT 24
Finished Jul 24 05:28:12 PM PDT 24
Peak memory 206636 kb
Host smart-3ba12151-8b14-41de-b4c8-31c12e901228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33962
32841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.3396232841
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.3726709180
Short name T858
Test name
Test status
Simulation time 73992949 ps
CPU time 0.67 seconds
Started Jul 24 05:28:12 PM PDT 24
Finished Jul 24 05:28:13 PM PDT 24
Peak memory 206596 kb
Host smart-86fd322e-2938-4b2d-a91c-5205085172b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37267
09180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.3726709180
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.3319898766
Short name T1000
Test name
Test status
Simulation time 20917712579 ps
CPU time 51.16 seconds
Started Jul 24 05:28:22 PM PDT 24
Finished Jul 24 05:29:13 PM PDT 24
Peak memory 215156 kb
Host smart-19821e37-fe58-4f0a-90b3-d70a4e2989a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33198
98766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.3319898766
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.3410191208
Short name T1693
Test name
Test status
Simulation time 187296520 ps
CPU time 0.85 seconds
Started Jul 24 05:28:08 PM PDT 24
Finished Jul 24 05:28:09 PM PDT 24
Peak memory 206620 kb
Host smart-5c8e75f2-5645-4f79-a87d-67a913dd1c5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34101
91208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.3410191208
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.1501242889
Short name T568
Test name
Test status
Simulation time 190778176 ps
CPU time 0.78 seconds
Started Jul 24 05:28:18 PM PDT 24
Finished Jul 24 05:28:19 PM PDT 24
Peak memory 206644 kb
Host smart-fe6e886c-b27f-4513-b624-48e934abf9f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15012
42889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.1501242889
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.1699395346
Short name T1119
Test name
Test status
Simulation time 225233311 ps
CPU time 0.9 seconds
Started Jul 24 05:28:24 PM PDT 24
Finished Jul 24 05:28:25 PM PDT 24
Peak memory 206780 kb
Host smart-0ca035ee-4726-4420-b5bf-a6acae958508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16993
95346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.1699395346
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.2062977594
Short name T385
Test name
Test status
Simulation time 163202723 ps
CPU time 0.77 seconds
Started Jul 24 05:28:05 PM PDT 24
Finished Jul 24 05:28:06 PM PDT 24
Peak memory 206368 kb
Host smart-2ba60669-a2c4-4793-b390-36f1a9608974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20629
77594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.2062977594
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.448742717
Short name T462
Test name
Test status
Simulation time 157920183 ps
CPU time 0.73 seconds
Started Jul 24 05:28:13 PM PDT 24
Finished Jul 24 05:28:14 PM PDT 24
Peak memory 206476 kb
Host smart-040e8bd4-e12b-4070-bf58-ad814813051b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44874
2717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.448742717
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.4175146617
Short name T1665
Test name
Test status
Simulation time 153421879 ps
CPU time 0.78 seconds
Started Jul 24 05:28:28 PM PDT 24
Finished Jul 24 05:28:29 PM PDT 24
Peak memory 206536 kb
Host smart-93cfb044-cfcd-4cd2-b3df-6933c2339c3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41751
46617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.4175146617
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.2199203079
Short name T1547
Test name
Test status
Simulation time 151443228 ps
CPU time 0.74 seconds
Started Jul 24 05:28:36 PM PDT 24
Finished Jul 24 05:28:37 PM PDT 24
Peak memory 206544 kb
Host smart-730b73d3-7a9c-48cc-b6b8-0fc6f51920ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21992
03079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.2199203079
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.3014737509
Short name T840
Test name
Test status
Simulation time 233575245 ps
CPU time 0.92 seconds
Started Jul 24 05:28:12 PM PDT 24
Finished Jul 24 05:28:13 PM PDT 24
Peak memory 206476 kb
Host smart-59126e18-9d4a-4e3d-b841-c65990375508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30147
37509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.3014737509
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.3501126475
Short name T663
Test name
Test status
Simulation time 4736344271 ps
CPU time 129.55 seconds
Started Jul 24 05:28:10 PM PDT 24
Finished Jul 24 05:30:20 PM PDT 24
Peak memory 206908 kb
Host smart-7264aea4-8a50-4606-8ce9-54c82cf58888
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3501126475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.3501126475
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.2873932268
Short name T1710
Test name
Test status
Simulation time 216172395 ps
CPU time 0.81 seconds
Started Jul 24 05:28:10 PM PDT 24
Finished Jul 24 05:28:11 PM PDT 24
Peak memory 206580 kb
Host smart-22ec7eee-6f95-4306-bc28-3d4bf00e1c27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28739
32268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.2873932268
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.4243344972
Short name T1368
Test name
Test status
Simulation time 216757568 ps
CPU time 0.92 seconds
Started Jul 24 05:28:16 PM PDT 24
Finished Jul 24 05:28:17 PM PDT 24
Peak memory 206540 kb
Host smart-ddd327ec-d90e-42b6-8d34-332f87e4171b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42433
44972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.4243344972
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.647289675
Short name T1792
Test name
Test status
Simulation time 382501997 ps
CPU time 1.2 seconds
Started Jul 24 05:28:25 PM PDT 24
Finished Jul 24 05:28:31 PM PDT 24
Peak memory 206624 kb
Host smart-b8e3b5fc-3e5c-4cb0-896c-a7609b15b6ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64728
9675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.647289675
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.2322177343
Short name T1824
Test name
Test status
Simulation time 3859858734 ps
CPU time 101.42 seconds
Started Jul 24 05:28:18 PM PDT 24
Finished Jul 24 05:29:59 PM PDT 24
Peak memory 206816 kb
Host smart-c18dd4dd-2cda-41d5-b61c-86cd811241df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23221
77343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.2322177343
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.1550019194
Short name T408
Test name
Test status
Simulation time 41769906 ps
CPU time 0.71 seconds
Started Jul 24 05:28:29 PM PDT 24
Finished Jul 24 05:28:29 PM PDT 24
Peak memory 206580 kb
Host smart-54c969e7-e276-47af-9c85-844a1907c9e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1550019194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.1550019194
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.694868834
Short name T456
Test name
Test status
Simulation time 3985985301 ps
CPU time 5.02 seconds
Started Jul 24 05:28:12 PM PDT 24
Finished Jul 24 05:28:18 PM PDT 24
Peak memory 206972 kb
Host smart-0e1879ff-9682-424d-8fdc-f654b6f856cf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=694868834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.694868834
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.490081525
Short name T773
Test name
Test status
Simulation time 13319629000 ps
CPU time 12.19 seconds
Started Jul 24 05:28:14 PM PDT 24
Finished Jul 24 05:28:26 PM PDT 24
Peak memory 206712 kb
Host smart-fa76e02d-d56e-499d-a2d8-aa037d536f7b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=490081525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.490081525
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.3367455038
Short name T2010
Test name
Test status
Simulation time 23483838742 ps
CPU time 23.31 seconds
Started Jul 24 05:28:11 PM PDT 24
Finished Jul 24 05:28:35 PM PDT 24
Peak memory 206960 kb
Host smart-d2901762-d6e2-4607-a36d-b3feb5697af4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3367455038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.3367455038
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.1742091346
Short name T1153
Test name
Test status
Simulation time 141865086 ps
CPU time 0.76 seconds
Started Jul 24 05:28:31 PM PDT 24
Finished Jul 24 05:28:32 PM PDT 24
Peak memory 206612 kb
Host smart-12caefcc-9ee4-4303-b44c-ffe477c29644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17420
91346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.1742091346
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.3497824549
Short name T1005
Test name
Test status
Simulation time 196959359 ps
CPU time 0.85 seconds
Started Jul 24 05:28:24 PM PDT 24
Finished Jul 24 05:28:25 PM PDT 24
Peak memory 206520 kb
Host smart-884cd759-6fed-4379-b919-205649ea1d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34978
24549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.3497824549
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.2877116357
Short name T703
Test name
Test status
Simulation time 153946739 ps
CPU time 0.74 seconds
Started Jul 24 05:28:41 PM PDT 24
Finished Jul 24 05:28:42 PM PDT 24
Peak memory 206636 kb
Host smart-4616a05d-bc18-43e6-a847-066cadba7fdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28771
16357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.2877116357
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.1595569198
Short name T1087
Test name
Test status
Simulation time 1566859129 ps
CPU time 3.65 seconds
Started Jul 24 05:28:32 PM PDT 24
Finished Jul 24 05:28:36 PM PDT 24
Peak memory 206716 kb
Host smart-3e88b926-18df-4cef-bfcb-dbeaf40e73cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15955
69198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.1595569198
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.3009560628
Short name T1107
Test name
Test status
Simulation time 10117912641 ps
CPU time 17.64 seconds
Started Jul 24 05:28:12 PM PDT 24
Finished Jul 24 05:28:29 PM PDT 24
Peak memory 206960 kb
Host smart-b149ea01-4a08-41ff-9fe4-6113ada0b1d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30095
60628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.3009560628
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.1947653064
Short name T333
Test name
Test status
Simulation time 331640021 ps
CPU time 1.16 seconds
Started Jul 24 05:28:15 PM PDT 24
Finished Jul 24 05:28:16 PM PDT 24
Peak memory 206560 kb
Host smart-8ffea562-9a59-4272-9d5a-0f0602b87290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19476
53064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.1947653064
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.1084074461
Short name T1955
Test name
Test status
Simulation time 179182950 ps
CPU time 0.81 seconds
Started Jul 24 05:28:40 PM PDT 24
Finished Jul 24 05:28:42 PM PDT 24
Peak memory 206472 kb
Host smart-0001219c-0f53-418d-86da-479d4ab5a890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10840
74461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.1084074461
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.4008752676
Short name T936
Test name
Test status
Simulation time 65492064 ps
CPU time 0.68 seconds
Started Jul 24 05:28:22 PM PDT 24
Finished Jul 24 05:28:23 PM PDT 24
Peak memory 206588 kb
Host smart-b195d5a9-1f04-48e1-9d26-4137f3f0c50d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40087
52676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.4008752676
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.917647324
Short name T2359
Test name
Test status
Simulation time 930266275 ps
CPU time 1.95 seconds
Started Jul 24 05:28:31 PM PDT 24
Finished Jul 24 05:28:33 PM PDT 24
Peak memory 206764 kb
Host smart-edf1d403-269c-43a8-9d3b-00b48a092564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91764
7324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.917647324
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.3812835991
Short name T2400
Test name
Test status
Simulation time 216807857 ps
CPU time 1.48 seconds
Started Jul 24 05:28:14 PM PDT 24
Finished Jul 24 05:28:17 PM PDT 24
Peak memory 206700 kb
Host smart-46b50057-5856-48b5-a694-5cdb9efa54fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38128
35991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.3812835991
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.2525243176
Short name T989
Test name
Test status
Simulation time 175993733 ps
CPU time 0.82 seconds
Started Jul 24 05:28:34 PM PDT 24
Finished Jul 24 05:28:35 PM PDT 24
Peak memory 206512 kb
Host smart-739eb25c-6c51-4376-afe1-b2c917817ecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25252
43176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.2525243176
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.3313955370
Short name T1834
Test name
Test status
Simulation time 139659155 ps
CPU time 0.71 seconds
Started Jul 24 05:28:27 PM PDT 24
Finished Jul 24 05:28:27 PM PDT 24
Peak memory 206548 kb
Host smart-c822ad5b-56dd-4986-9e2d-e94d10c63578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33139
55370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.3313955370
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.354069474
Short name T821
Test name
Test status
Simulation time 202612592 ps
CPU time 0.88 seconds
Started Jul 24 05:28:23 PM PDT 24
Finished Jul 24 05:28:24 PM PDT 24
Peak memory 206552 kb
Host smart-55e8efa2-d26b-4338-92d1-4e49f3f4887d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35406
9474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.354069474
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_iso_retraction.282440035
Short name T1066
Test name
Test status
Simulation time 10497725861 ps
CPU time 34.83 seconds
Started Jul 24 05:28:25 PM PDT 24
Finished Jul 24 05:29:00 PM PDT 24
Peak memory 206904 kb
Host smart-2ddfd874-2841-4d0f-a0ec-b61cf1e8f176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28244
0035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.282440035
Directory /workspace/35.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.501965169
Short name T2028
Test name
Test status
Simulation time 170605341 ps
CPU time 0.8 seconds
Started Jul 24 05:28:26 PM PDT 24
Finished Jul 24 05:28:27 PM PDT 24
Peak memory 206504 kb
Host smart-139dfe15-cac1-40bf-a791-0f9cf7ceb97c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50196
5169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.501965169
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.1005520985
Short name T1719
Test name
Test status
Simulation time 23327112410 ps
CPU time 22.4 seconds
Started Jul 24 05:28:29 PM PDT 24
Finished Jul 24 05:28:52 PM PDT 24
Peak memory 206716 kb
Host smart-be0b23eb-3f79-46d8-a669-8c529bafafc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10055
20985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.1005520985
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.4278756247
Short name T955
Test name
Test status
Simulation time 3273242553 ps
CPU time 4.75 seconds
Started Jul 24 05:28:22 PM PDT 24
Finished Jul 24 05:28:27 PM PDT 24
Peak memory 206700 kb
Host smart-f0d1d69c-5240-4145-a352-ccd9d98700bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42787
56247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.4278756247
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.1105217685
Short name T1743
Test name
Test status
Simulation time 7040574791 ps
CPU time 49.69 seconds
Started Jul 24 05:28:14 PM PDT 24
Finished Jul 24 05:29:04 PM PDT 24
Peak memory 206960 kb
Host smart-7e88fd12-b857-4df7-94e8-78228178f319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11052
17685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.1105217685
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.2975428388
Short name T1688
Test name
Test status
Simulation time 5326898508 ps
CPU time 36.96 seconds
Started Jul 24 05:28:16 PM PDT 24
Finished Jul 24 05:28:53 PM PDT 24
Peak memory 206948 kb
Host smart-8747cfd5-c758-4955-a247-690d4f59d86a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2975428388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.2975428388
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.3813463430
Short name T1141
Test name
Test status
Simulation time 251115407 ps
CPU time 0.9 seconds
Started Jul 24 05:28:41 PM PDT 24
Finished Jul 24 05:28:42 PM PDT 24
Peak memory 206592 kb
Host smart-ae35bd77-8423-4fa8-8225-072006df9e1c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3813463430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.3813463430
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.243525039
Short name T2014
Test name
Test status
Simulation time 246690343 ps
CPU time 1.02 seconds
Started Jul 24 05:28:23 PM PDT 24
Finished Jul 24 05:28:24 PM PDT 24
Peak memory 206576 kb
Host smart-c027a6a9-3771-4132-8c2b-e495e0bba8d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24352
5039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.243525039
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.313808805
Short name T2131
Test name
Test status
Simulation time 5037152498 ps
CPU time 49.29 seconds
Started Jul 24 05:28:14 PM PDT 24
Finished Jul 24 05:29:04 PM PDT 24
Peak memory 206892 kb
Host smart-06ed734b-34ea-4196-b476-da93c9696c0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31380
8805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.313808805
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.1714225693
Short name T1363
Test name
Test status
Simulation time 3398473778 ps
CPU time 31.56 seconds
Started Jul 24 05:28:32 PM PDT 24
Finished Jul 24 05:29:04 PM PDT 24
Peak memory 206888 kb
Host smart-ee626da3-0b1d-4373-9e27-fde74e1f8cb6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1714225693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.1714225693
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.3198130881
Short name T2473
Test name
Test status
Simulation time 188366086 ps
CPU time 0.83 seconds
Started Jul 24 05:28:30 PM PDT 24
Finished Jul 24 05:28:31 PM PDT 24
Peak memory 206612 kb
Host smart-baa473d2-bea6-4fce-b5a8-8a1998055a68
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3198130881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.3198130881
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.2788928076
Short name T967
Test name
Test status
Simulation time 190108110 ps
CPU time 0.8 seconds
Started Jul 24 05:28:28 PM PDT 24
Finished Jul 24 05:28:29 PM PDT 24
Peak memory 206452 kb
Host smart-8a4d6f2c-dee0-4b8b-884c-c988f549b5d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27889
28076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.2788928076
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.4083811931
Short name T1039
Test name
Test status
Simulation time 175588118 ps
CPU time 0.81 seconds
Started Jul 24 05:28:22 PM PDT 24
Finished Jul 24 05:28:23 PM PDT 24
Peak memory 206476 kb
Host smart-32ecd565-5baf-4861-9cb5-879ce6690474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40838
11931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.4083811931
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.845600382
Short name T2423
Test name
Test status
Simulation time 202615622 ps
CPU time 0.84 seconds
Started Jul 24 05:28:38 PM PDT 24
Finished Jul 24 05:28:39 PM PDT 24
Peak memory 206632 kb
Host smart-32de591c-d56a-4c03-b689-08c4d0dda1a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84560
0382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.845600382
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.2379096254
Short name T935
Test name
Test status
Simulation time 173629781 ps
CPU time 0.83 seconds
Started Jul 24 05:28:58 PM PDT 24
Finished Jul 24 05:28:59 PM PDT 24
Peak memory 206584 kb
Host smart-e8348915-bc34-496a-adba-5a02afedb40e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23790
96254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.2379096254
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.467949551
Short name T2373
Test name
Test status
Simulation time 226481241 ps
CPU time 0.83 seconds
Started Jul 24 05:28:32 PM PDT 24
Finished Jul 24 05:28:33 PM PDT 24
Peak memory 206568 kb
Host smart-412ee3fb-883c-4372-9b7d-1a247c0ee986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46794
9551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.467949551
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.886926394
Short name T1211
Test name
Test status
Simulation time 191906134 ps
CPU time 0.83 seconds
Started Jul 24 05:28:41 PM PDT 24
Finished Jul 24 05:28:42 PM PDT 24
Peak memory 206564 kb
Host smart-d47b24b1-0c94-4a50-acfa-3a409483dee6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=886926394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.886926394
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.2348514464
Short name T2148
Test name
Test status
Simulation time 149576770 ps
CPU time 0.78 seconds
Started Jul 24 05:28:38 PM PDT 24
Finished Jul 24 05:28:44 PM PDT 24
Peak memory 206548 kb
Host smart-62a61816-b7b5-4027-a307-e387868e5c9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23485
14464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.2348514464
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.1599622432
Short name T2364
Test name
Test status
Simulation time 39198633 ps
CPU time 0.63 seconds
Started Jul 24 05:28:30 PM PDT 24
Finished Jul 24 05:28:30 PM PDT 24
Peak memory 206572 kb
Host smart-4d790234-6d47-4790-9c58-b31236877851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15996
22432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.1599622432
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.1799209311
Short name T2485
Test name
Test status
Simulation time 23173775116 ps
CPU time 51.08 seconds
Started Jul 24 05:28:36 PM PDT 24
Finished Jul 24 05:29:27 PM PDT 24
Peak memory 215136 kb
Host smart-5e184e68-f3dc-473c-a301-31390fa86637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17992
09311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.1799209311
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.2622547373
Short name T672
Test name
Test status
Simulation time 178318017 ps
CPU time 0.8 seconds
Started Jul 24 05:28:17 PM PDT 24
Finished Jul 24 05:28:18 PM PDT 24
Peak memory 206384 kb
Host smart-119072ad-b628-478e-9c33-8504a617d151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26225
47373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.2622547373
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.2672645147
Short name T2468
Test name
Test status
Simulation time 179520151 ps
CPU time 0.88 seconds
Started Jul 24 05:28:36 PM PDT 24
Finished Jul 24 05:28:37 PM PDT 24
Peak memory 206636 kb
Host smart-0797c757-8758-4826-b28a-9662e6c1ad53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26726
45147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.2672645147
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.2572878316
Short name T486
Test name
Test status
Simulation time 208980278 ps
CPU time 0.83 seconds
Started Jul 24 05:28:37 PM PDT 24
Finished Jul 24 05:28:38 PM PDT 24
Peak memory 206584 kb
Host smart-22eaa841-a315-4ba4-9e7e-4abe33c3781d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25728
78316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.2572878316
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.2833517317
Short name T972
Test name
Test status
Simulation time 211026018 ps
CPU time 0.82 seconds
Started Jul 24 05:28:15 PM PDT 24
Finished Jul 24 05:28:16 PM PDT 24
Peak memory 206536 kb
Host smart-6e888a29-1bdb-4226-ad3e-b29041de8097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28335
17317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.2833517317
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.2370021158
Short name T1899
Test name
Test status
Simulation time 136939368 ps
CPU time 0.77 seconds
Started Jul 24 05:28:33 PM PDT 24
Finished Jul 24 05:28:34 PM PDT 24
Peak memory 206576 kb
Host smart-c44aa6fb-f8e3-4a56-8fea-ea01ad4678d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23700
21158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.2370021158
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.1350148985
Short name T1922
Test name
Test status
Simulation time 159369606 ps
CPU time 0.76 seconds
Started Jul 24 05:28:35 PM PDT 24
Finished Jul 24 05:28:36 PM PDT 24
Peak memory 206600 kb
Host smart-cbf1d334-ce2a-40a1-bede-c9e2d037646c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13501
48985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.1350148985
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.2664794777
Short name T2253
Test name
Test status
Simulation time 149354448 ps
CPU time 0.81 seconds
Started Jul 24 05:28:30 PM PDT 24
Finished Jul 24 05:28:31 PM PDT 24
Peak memory 206596 kb
Host smart-f92bb5f9-6264-4db5-882a-7e41cda8008d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26647
94777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.2664794777
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.2338234273
Short name T2168
Test name
Test status
Simulation time 214565773 ps
CPU time 0.87 seconds
Started Jul 24 05:28:30 PM PDT 24
Finished Jul 24 05:28:31 PM PDT 24
Peak memory 206468 kb
Host smart-254edb5c-1b1f-4ae8-83c7-8ac886ca9c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23382
34273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.2338234273
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.1144337489
Short name T1891
Test name
Test status
Simulation time 6141466317 ps
CPU time 42.56 seconds
Started Jul 24 05:28:47 PM PDT 24
Finished Jul 24 05:29:29 PM PDT 24
Peak memory 207012 kb
Host smart-d0962085-ab30-4b18-a500-d98df4b13e57
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1144337489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.1144337489
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.3363620601
Short name T550
Test name
Test status
Simulation time 194514000 ps
CPU time 0.83 seconds
Started Jul 24 05:28:28 PM PDT 24
Finished Jul 24 05:28:29 PM PDT 24
Peak memory 206536 kb
Host smart-7edf267d-57bb-4758-9912-aec835606fca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33636
20601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.3363620601
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.1039138484
Short name T602
Test name
Test status
Simulation time 195474947 ps
CPU time 0.8 seconds
Started Jul 24 05:28:25 PM PDT 24
Finished Jul 24 05:28:26 PM PDT 24
Peak memory 206544 kb
Host smart-a434d8c5-1b06-49b3-bc05-92707d72b601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10391
38484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.1039138484
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.677733181
Short name T328
Test name
Test status
Simulation time 268374605 ps
CPU time 0.95 seconds
Started Jul 24 05:28:34 PM PDT 24
Finished Jul 24 05:28:35 PM PDT 24
Peak memory 206592 kb
Host smart-6a1b44c6-7721-4c87-a190-0247171188f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67773
3181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.677733181
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.132059199
Short name T671
Test name
Test status
Simulation time 5555663544 ps
CPU time 38.14 seconds
Started Jul 24 05:28:47 PM PDT 24
Finished Jul 24 05:29:25 PM PDT 24
Peak memory 206856 kb
Host smart-7d744aa1-3256-45d5-b89b-1b52dbc05049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13205
9199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.132059199
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.871050796
Short name T2655
Test name
Test status
Simulation time 33570140 ps
CPU time 0.7 seconds
Started Jul 24 05:28:30 PM PDT 24
Finished Jul 24 05:28:31 PM PDT 24
Peak memory 206600 kb
Host smart-6a261088-0f91-4188-8a0c-e3a4668b7826
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=871050796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.871050796
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.4112463993
Short name T1600
Test name
Test status
Simulation time 13440565847 ps
CPU time 12.76 seconds
Started Jul 24 05:28:23 PM PDT 24
Finished Jul 24 05:28:36 PM PDT 24
Peak memory 206888 kb
Host smart-d0d728ee-401e-4427-af4f-fecf011bfb62
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4112463993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.4112463993
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.913537688
Short name T1435
Test name
Test status
Simulation time 23357412362 ps
CPU time 28.56 seconds
Started Jul 24 05:28:30 PM PDT 24
Finished Jul 24 05:28:59 PM PDT 24
Peak memory 206692 kb
Host smart-6ee52361-855d-40c0-af1d-ec6a6067057c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=913537688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.913537688
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.1952521232
Short name T2063
Test name
Test status
Simulation time 228176000 ps
CPU time 0.83 seconds
Started Jul 24 05:28:26 PM PDT 24
Finished Jul 24 05:28:26 PM PDT 24
Peak memory 206612 kb
Host smart-f4535939-44d8-4e08-b5d7-a52f74963546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19525
21232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.1952521232
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.3461493954
Short name T1707
Test name
Test status
Simulation time 183798336 ps
CPU time 0.78 seconds
Started Jul 24 05:28:37 PM PDT 24
Finished Jul 24 05:28:38 PM PDT 24
Peak memory 206600 kb
Host smart-6d948fbd-5723-444a-b7a6-5094c6c65b77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34614
93954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.3461493954
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.1537624712
Short name T98
Test name
Test status
Simulation time 211565248 ps
CPU time 0.92 seconds
Started Jul 24 05:28:33 PM PDT 24
Finished Jul 24 05:28:34 PM PDT 24
Peak memory 206780 kb
Host smart-31fe8e97-7581-4938-9afa-b753fef9a19d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15376
24712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.1537624712
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.1170423041
Short name T1072
Test name
Test status
Simulation time 768137715 ps
CPU time 2.03 seconds
Started Jul 24 05:28:58 PM PDT 24
Finished Jul 24 05:29:00 PM PDT 24
Peak memory 206716 kb
Host smart-91d116fa-f96a-48f9-bb3e-71056a090761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11704
23041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.1170423041
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.1339164990
Short name T774
Test name
Test status
Simulation time 18940963959 ps
CPU time 40.62 seconds
Started Jul 24 05:28:33 PM PDT 24
Finished Jul 24 05:29:14 PM PDT 24
Peak memory 207092 kb
Host smart-e94f3b82-74f0-4f7a-93eb-f0bbe338cfaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13391
64990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.1339164990
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.2943090980
Short name T1431
Test name
Test status
Simulation time 552877888 ps
CPU time 1.6 seconds
Started Jul 24 05:28:44 PM PDT 24
Finished Jul 24 05:28:46 PM PDT 24
Peak memory 206600 kb
Host smart-e34b76b8-b97c-4ede-8064-971e22babfb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29430
90980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.2943090980
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.3843488416
Short name T1790
Test name
Test status
Simulation time 141838897 ps
CPU time 0.75 seconds
Started Jul 24 05:28:35 PM PDT 24
Finished Jul 24 05:28:36 PM PDT 24
Peak memory 206580 kb
Host smart-0f7c59df-c65b-40ce-8d76-3958c32cad52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38434
88416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.3843488416
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.2652104754
Short name T1611
Test name
Test status
Simulation time 39215397 ps
CPU time 0.64 seconds
Started Jul 24 05:28:22 PM PDT 24
Finished Jul 24 05:28:22 PM PDT 24
Peak memory 206540 kb
Host smart-e3d9557c-ad91-41f5-943a-b9d244fe4515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26521
04754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.2652104754
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.991045374
Short name T339
Test name
Test status
Simulation time 877476061 ps
CPU time 2 seconds
Started Jul 24 05:28:30 PM PDT 24
Finished Jul 24 05:28:32 PM PDT 24
Peak memory 206788 kb
Host smart-e6fe9314-413d-42c9-b10c-59bbe2c5cc1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99104
5374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.991045374
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.1110041328
Short name T495
Test name
Test status
Simulation time 281509248 ps
CPU time 1.66 seconds
Started Jul 24 05:28:25 PM PDT 24
Finished Jul 24 05:28:26 PM PDT 24
Peak memory 206788 kb
Host smart-363f8181-5992-4aaa-be21-aa604a99dda2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11100
41328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.1110041328
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.2741047773
Short name T1996
Test name
Test status
Simulation time 158710866 ps
CPU time 0.77 seconds
Started Jul 24 05:28:34 PM PDT 24
Finished Jul 24 05:28:35 PM PDT 24
Peak memory 206600 kb
Host smart-752747cf-10f4-40c6-9b2b-d32f8f082aab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27410
47773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.2741047773
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.1007639094
Short name T2432
Test name
Test status
Simulation time 156257578 ps
CPU time 0.83 seconds
Started Jul 24 05:28:40 PM PDT 24
Finished Jul 24 05:28:42 PM PDT 24
Peak memory 206608 kb
Host smart-6c056c7d-bcd4-4397-a687-6e38d1517e8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10076
39094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.1007639094
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.2665579802
Short name T1266
Test name
Test status
Simulation time 233271491 ps
CPU time 0.88 seconds
Started Jul 24 05:28:38 PM PDT 24
Finished Jul 24 05:28:39 PM PDT 24
Peak memory 206532 kb
Host smart-9c2c1b4c-895a-4ba6-b674-a1f53b62f566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26655
79802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.2665579802
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_invalid_sync.2331202707
Short name T205
Test name
Test status
Simulation time 4961262035 ps
CPU time 35.59 seconds
Started Jul 24 05:28:36 PM PDT 24
Finished Jul 24 05:29:12 PM PDT 24
Peak memory 206912 kb
Host smart-51449a60-611f-4179-86d9-77ea8829d781
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2331202707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.2331202707
Directory /workspace/36.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/36.usbdev_iso_retraction.2626541531
Short name T2272
Test name
Test status
Simulation time 3800679188 ps
CPU time 28.95 seconds
Started Jul 24 05:28:51 PM PDT 24
Finished Jul 24 05:29:20 PM PDT 24
Peak memory 206904 kb
Host smart-29c808a1-4f42-4bb5-b385-755cbf7e2c5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26265
41531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_iso_retraction.2626541531
Directory /workspace/36.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.400641700
Short name T826
Test name
Test status
Simulation time 270071228 ps
CPU time 0.87 seconds
Started Jul 24 05:28:40 PM PDT 24
Finished Jul 24 05:28:41 PM PDT 24
Peak memory 206592 kb
Host smart-b1fd57a6-de32-469e-b8da-770ce84d395e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40064
1700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.400641700
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.3646136402
Short name T555
Test name
Test status
Simulation time 23358322289 ps
CPU time 29.99 seconds
Started Jul 24 05:28:43 PM PDT 24
Finished Jul 24 05:29:13 PM PDT 24
Peak memory 206600 kb
Host smart-a1f9e423-b3f1-4c9c-aa97-b37d515fa7f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36461
36402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.3646136402
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.3593523284
Short name T1617
Test name
Test status
Simulation time 3326313263 ps
CPU time 3.64 seconds
Started Jul 24 05:28:39 PM PDT 24
Finished Jul 24 05:28:42 PM PDT 24
Peak memory 206724 kb
Host smart-fe93fcc3-845c-4297-84cd-9158f912a55e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35935
23284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.3593523284
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.3543324300
Short name T2262
Test name
Test status
Simulation time 11604209182 ps
CPU time 83.28 seconds
Started Jul 24 05:28:39 PM PDT 24
Finished Jul 24 05:30:07 PM PDT 24
Peak memory 206928 kb
Host smart-7c9e857e-51b5-401a-835c-71886094cb18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35433
24300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.3543324300
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.3971595653
Short name T1110
Test name
Test status
Simulation time 5132325982 ps
CPU time 47.12 seconds
Started Jul 24 05:28:39 PM PDT 24
Finished Jul 24 05:29:27 PM PDT 24
Peak memory 206960 kb
Host smart-6ebb9b82-f34b-4682-a552-f4014001bcdd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3971595653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.3971595653
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.1389095346
Short name T684
Test name
Test status
Simulation time 258420395 ps
CPU time 0.91 seconds
Started Jul 24 05:28:25 PM PDT 24
Finished Jul 24 05:28:26 PM PDT 24
Peak memory 206616 kb
Host smart-ae4c7197-f8cd-485d-88ae-0498db901c05
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1389095346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.1389095346
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.3377036256
Short name T435
Test name
Test status
Simulation time 191709698 ps
CPU time 0.96 seconds
Started Jul 24 05:28:37 PM PDT 24
Finished Jul 24 05:28:38 PM PDT 24
Peak memory 206616 kb
Host smart-d6af657a-ccbe-4f35-8ec0-df45223a4352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33770
36256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.3377036256
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.734123284
Short name T151
Test name
Test status
Simulation time 5726817982 ps
CPU time 54.78 seconds
Started Jul 24 05:28:29 PM PDT 24
Finished Jul 24 05:29:24 PM PDT 24
Peak memory 206784 kb
Host smart-ef16f4c1-b2b4-4b69-8e5a-999c8cfbcb4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73412
3284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.734123284
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.323516149
Short name T2483
Test name
Test status
Simulation time 4879357952 ps
CPU time 137.86 seconds
Started Jul 24 05:28:47 PM PDT 24
Finished Jul 24 05:31:05 PM PDT 24
Peak memory 206916 kb
Host smart-8a726a64-f117-43d9-8556-a63aa6793de7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=323516149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.323516149
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.2774560928
Short name T1675
Test name
Test status
Simulation time 153612455 ps
CPU time 0.75 seconds
Started Jul 24 05:28:46 PM PDT 24
Finished Jul 24 05:28:47 PM PDT 24
Peak memory 206556 kb
Host smart-beb4545c-5d4e-40d2-96b1-70c73bbb0a68
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2774560928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.2774560928
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.2420699971
Short name T849
Test name
Test status
Simulation time 168711881 ps
CPU time 0.79 seconds
Started Jul 24 05:28:32 PM PDT 24
Finished Jul 24 05:28:33 PM PDT 24
Peak memory 206520 kb
Host smart-702e82d7-d1a2-4574-821c-036d3ad3a617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24206
99971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.2420699971
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.1704325390
Short name T110
Test name
Test status
Simulation time 167318478 ps
CPU time 0.82 seconds
Started Jul 24 05:28:40 PM PDT 24
Finished Jul 24 05:28:41 PM PDT 24
Peak memory 206520 kb
Host smart-226387b3-6691-47d7-bec4-7dc183ab5a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17043
25390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.1704325390
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.1152022293
Short name T1397
Test name
Test status
Simulation time 175712846 ps
CPU time 0.83 seconds
Started Jul 24 05:28:47 PM PDT 24
Finished Jul 24 05:28:48 PM PDT 24
Peak memory 206580 kb
Host smart-cce901e8-ce20-4551-b133-a69a4b9999be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11520
22293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.1152022293
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.1775860319
Short name T603
Test name
Test status
Simulation time 171692233 ps
CPU time 0.78 seconds
Started Jul 24 05:28:36 PM PDT 24
Finished Jul 24 05:28:37 PM PDT 24
Peak memory 206584 kb
Host smart-95fdc0f7-890a-4289-a90e-9946b5b70388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17758
60319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.1775860319
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.3939391299
Short name T755
Test name
Test status
Simulation time 184067644 ps
CPU time 0.82 seconds
Started Jul 24 05:28:30 PM PDT 24
Finished Jul 24 05:28:32 PM PDT 24
Peak memory 206628 kb
Host smart-5bca7021-bcde-4adf-b129-d13a6a069907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39393
91299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.3939391299
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.2564908747
Short name T2193
Test name
Test status
Simulation time 149777428 ps
CPU time 0.79 seconds
Started Jul 24 05:28:36 PM PDT 24
Finished Jul 24 05:28:37 PM PDT 24
Peak memory 206608 kb
Host smart-18d68853-c555-4278-999a-0e95ca57c4bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25649
08747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.2564908747
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.1090052218
Short name T454
Test name
Test status
Simulation time 199989640 ps
CPU time 0.91 seconds
Started Jul 24 05:28:30 PM PDT 24
Finished Jul 24 05:28:31 PM PDT 24
Peak memory 206600 kb
Host smart-4b06b447-b4c1-4c46-acd4-bb84b8f5c103
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1090052218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.1090052218
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.3944627944
Short name T1391
Test name
Test status
Simulation time 165004486 ps
CPU time 0.74 seconds
Started Jul 24 05:28:40 PM PDT 24
Finished Jul 24 05:28:41 PM PDT 24
Peak memory 206556 kb
Host smart-3dabf728-f51e-4eab-96ee-bc2b9b5b1077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39446
27944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.3944627944
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.538248378
Short name T1703
Test name
Test status
Simulation time 54191571 ps
CPU time 0.64 seconds
Started Jul 24 05:28:35 PM PDT 24
Finished Jul 24 05:28:36 PM PDT 24
Peak memory 206496 kb
Host smart-05da51ee-992f-4a34-a5d6-2062f4d7b5d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53824
8378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.538248378
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.2289743012
Short name T31
Test name
Test status
Simulation time 11899442985 ps
CPU time 27.67 seconds
Started Jul 24 05:28:45 PM PDT 24
Finished Jul 24 05:29:13 PM PDT 24
Peak memory 206996 kb
Host smart-05dc1b0d-99c8-437f-ba69-9b9f29d897b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22897
43012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.2289743012
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.4240575562
Short name T757
Test name
Test status
Simulation time 195939095 ps
CPU time 0.88 seconds
Started Jul 24 05:28:50 PM PDT 24
Finished Jul 24 05:28:51 PM PDT 24
Peak memory 206384 kb
Host smart-be9cbe51-fe6a-4f4c-8d0d-b45d594ee6a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42405
75562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.4240575562
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.959194094
Short name T2099
Test name
Test status
Simulation time 182737832 ps
CPU time 0.81 seconds
Started Jul 24 05:28:44 PM PDT 24
Finished Jul 24 05:28:45 PM PDT 24
Peak memory 206632 kb
Host smart-0e633dca-70ec-496c-99e6-583a23ef3189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95919
4094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.959194094
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.2372578755
Short name T1572
Test name
Test status
Simulation time 186040491 ps
CPU time 0.8 seconds
Started Jul 24 05:28:39 PM PDT 24
Finished Jul 24 05:28:40 PM PDT 24
Peak memory 206564 kb
Host smart-22936e79-3ede-4bed-9b86-e1560cd577de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23725
78755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.2372578755
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.2086443379
Short name T2360
Test name
Test status
Simulation time 150526072 ps
CPU time 0.78 seconds
Started Jul 24 05:28:37 PM PDT 24
Finished Jul 24 05:28:38 PM PDT 24
Peak memory 206616 kb
Host smart-5e0ca6fb-f61e-4d96-9e39-0da36a72f0da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20864
43379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.2086443379
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.618642967
Short name T777
Test name
Test status
Simulation time 142662957 ps
CPU time 0.78 seconds
Started Jul 24 05:28:43 PM PDT 24
Finished Jul 24 05:28:44 PM PDT 24
Peak memory 206580 kb
Host smart-5b3175ca-1f18-4bbd-89e1-04a7ca512e41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61864
2967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.618642967
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.1734501306
Short name T2695
Test name
Test status
Simulation time 154806373 ps
CPU time 0.83 seconds
Started Jul 24 05:28:40 PM PDT 24
Finished Jul 24 05:28:41 PM PDT 24
Peak memory 206544 kb
Host smart-25a2d3cd-1e5e-4080-91c1-97f4e4e12486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17345
01306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.1734501306
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.2409691911
Short name T2021
Test name
Test status
Simulation time 199147006 ps
CPU time 0.79 seconds
Started Jul 24 05:28:52 PM PDT 24
Finished Jul 24 05:28:53 PM PDT 24
Peak memory 206628 kb
Host smart-2670a74d-f131-4e49-98ee-0e2956f6f1b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24096
91911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.2409691911
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.2803311065
Short name T685
Test name
Test status
Simulation time 232166350 ps
CPU time 0.92 seconds
Started Jul 24 05:28:44 PM PDT 24
Finished Jul 24 05:28:45 PM PDT 24
Peak memory 206652 kb
Host smart-70448247-10ec-48c9-91ad-0a9b86be204f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28033
11065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.2803311065
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.3721312241
Short name T145
Test name
Test status
Simulation time 6004339121 ps
CPU time 54.95 seconds
Started Jul 24 05:28:49 PM PDT 24
Finished Jul 24 05:29:44 PM PDT 24
Peak memory 206900 kb
Host smart-3e27de99-7eff-4225-8361-0ecb68eb49bb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3721312241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.3721312241
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.1213040978
Short name T1797
Test name
Test status
Simulation time 208545560 ps
CPU time 0.8 seconds
Started Jul 24 05:28:39 PM PDT 24
Finished Jul 24 05:28:40 PM PDT 24
Peak memory 206676 kb
Host smart-a4a7a713-c575-4af7-9035-f825b41665b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12130
40978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.1213040978
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.3029319755
Short name T951
Test name
Test status
Simulation time 145252675 ps
CPU time 0.79 seconds
Started Jul 24 05:28:38 PM PDT 24
Finished Jul 24 05:28:39 PM PDT 24
Peak memory 206548 kb
Host smart-eae4064c-7846-4283-8a31-dcc3d9e07b62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30293
19755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.3029319755
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.354486413
Short name T1591
Test name
Test status
Simulation time 1375387714 ps
CPU time 2.82 seconds
Started Jul 24 05:28:39 PM PDT 24
Finished Jul 24 05:28:42 PM PDT 24
Peak memory 206828 kb
Host smart-94dfc8be-e03e-4bcc-adce-4e1a18aeb34c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35448
6413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.354486413
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.1919550839
Short name T1392
Test name
Test status
Simulation time 4158128433 ps
CPU time 112.57 seconds
Started Jul 24 05:28:46 PM PDT 24
Finished Jul 24 05:30:38 PM PDT 24
Peak memory 206920 kb
Host smart-0714df1a-fbce-4613-872c-ea14d50ee457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19195
50839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.1919550839
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.2922198006
Short name T1292
Test name
Test status
Simulation time 36376437 ps
CPU time 0.67 seconds
Started Jul 24 05:28:44 PM PDT 24
Finished Jul 24 05:28:45 PM PDT 24
Peak memory 206512 kb
Host smart-b371875a-9745-4249-9b6e-6e17ed22df2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2922198006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.2922198006
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.1658857745
Short name T1911
Test name
Test status
Simulation time 3808606680 ps
CPU time 4.72 seconds
Started Jul 24 05:28:38 PM PDT 24
Finished Jul 24 05:28:43 PM PDT 24
Peak memory 206740 kb
Host smart-53257efb-412b-41a2-ac77-3001366ce474
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1658857745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.1658857745
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.2209789499
Short name T9
Test name
Test status
Simulation time 13365923241 ps
CPU time 14.09 seconds
Started Jul 24 05:28:31 PM PDT 24
Finished Jul 24 05:28:45 PM PDT 24
Peak memory 206620 kb
Host smart-cd19b29a-c5c5-4c80-a3ba-b0bc4aa4e755
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2209789499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.2209789499
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.3405910535
Short name T2113
Test name
Test status
Simulation time 23489816300 ps
CPU time 26.24 seconds
Started Jul 24 05:28:37 PM PDT 24
Finished Jul 24 05:29:03 PM PDT 24
Peak memory 206956 kb
Host smart-d8999cc8-1b88-4046-9338-c46552afcb52
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3405910535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.3405910535
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.3158165410
Short name T1236
Test name
Test status
Simulation time 202649596 ps
CPU time 0.85 seconds
Started Jul 24 05:28:40 PM PDT 24
Finished Jul 24 05:28:41 PM PDT 24
Peak memory 206520 kb
Host smart-ba423975-f660-4511-b808-29d198ee8722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31581
65410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.3158165410
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.283377749
Short name T2393
Test name
Test status
Simulation time 166351285 ps
CPU time 0.76 seconds
Started Jul 24 05:28:50 PM PDT 24
Finished Jul 24 05:28:51 PM PDT 24
Peak memory 206588 kb
Host smart-f5eccba8-a43e-4394-9718-797269a639e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28337
7749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.283377749
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.2003314338
Short name T2607
Test name
Test status
Simulation time 145809590 ps
CPU time 0.74 seconds
Started Jul 24 05:28:37 PM PDT 24
Finished Jul 24 05:28:38 PM PDT 24
Peak memory 206600 kb
Host smart-186006fe-0efd-42a5-bf83-7cdbad6f8585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20033
14338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.2003314338
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.3881470266
Short name T103
Test name
Test status
Simulation time 778900288 ps
CPU time 2 seconds
Started Jul 24 05:28:38 PM PDT 24
Finished Jul 24 05:28:40 PM PDT 24
Peak memory 206772 kb
Host smart-f337a39f-d1f8-4966-ad79-01d5dc8342f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38814
70266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.3881470266
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.35096082
Short name T1441
Test name
Test status
Simulation time 14447777882 ps
CPU time 29.82 seconds
Started Jul 24 05:28:40 PM PDT 24
Finished Jul 24 05:29:10 PM PDT 24
Peak memory 206872 kb
Host smart-0440f0e8-2760-4b0e-8676-e301e9c2cbbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35096
082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.35096082
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.1557226641
Short name T921
Test name
Test status
Simulation time 452881090 ps
CPU time 1.3 seconds
Started Jul 24 05:28:59 PM PDT 24
Finished Jul 24 05:29:01 PM PDT 24
Peak memory 206612 kb
Host smart-103d7ec6-7700-48b8-8624-5374d7c1fa05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15572
26641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.1557226641
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.2891447815
Short name T666
Test name
Test status
Simulation time 175921621 ps
CPU time 0.81 seconds
Started Jul 24 05:28:42 PM PDT 24
Finished Jul 24 05:28:43 PM PDT 24
Peak memory 206512 kb
Host smart-2e9f8c28-c1ae-4452-a53d-7349472d4884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28914
47815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.2891447815
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.3906699324
Short name T855
Test name
Test status
Simulation time 56275627 ps
CPU time 0.66 seconds
Started Jul 24 05:28:35 PM PDT 24
Finished Jul 24 05:28:36 PM PDT 24
Peak memory 206600 kb
Host smart-a1ff1398-5e78-4367-bd42-6ddeafe5c453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39066
99324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.3906699324
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.2776287170
Short name T910
Test name
Test status
Simulation time 674095767 ps
CPU time 1.75 seconds
Started Jul 24 05:28:36 PM PDT 24
Finished Jul 24 05:28:38 PM PDT 24
Peak memory 206836 kb
Host smart-4c6bd6eb-5e07-49ce-9a11-d4d2ca880348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27762
87170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.2776287170
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.2610533379
Short name T1372
Test name
Test status
Simulation time 231444632 ps
CPU time 1.66 seconds
Started Jul 24 05:29:00 PM PDT 24
Finished Jul 24 05:29:02 PM PDT 24
Peak memory 206764 kb
Host smart-99308108-70d5-4d29-9a3b-c07a55e552b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26105
33379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.2610533379
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.2273778201
Short name T1799
Test name
Test status
Simulation time 240345761 ps
CPU time 0.86 seconds
Started Jul 24 05:28:38 PM PDT 24
Finished Jul 24 05:28:39 PM PDT 24
Peak memory 206560 kb
Host smart-8ea5102d-da3d-4cd6-80ff-254d0073a9f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22737
78201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.2273778201
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.1632053388
Short name T2159
Test name
Test status
Simulation time 170363408 ps
CPU time 0.8 seconds
Started Jul 24 05:28:43 PM PDT 24
Finished Jul 24 05:28:44 PM PDT 24
Peak memory 206776 kb
Host smart-b032cb52-76a5-44d7-97b7-d16ab2746011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16320
53388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.1632053388
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.542634862
Short name T415
Test name
Test status
Simulation time 179216022 ps
CPU time 0.82 seconds
Started Jul 24 05:28:39 PM PDT 24
Finished Jul 24 05:28:40 PM PDT 24
Peak memory 206580 kb
Host smart-e053391a-74bd-4189-9121-4027b52ed673
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54263
4862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.542634862
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.3731482079
Short name T2313
Test name
Test status
Simulation time 6762907917 ps
CPU time 174.18 seconds
Started Jul 24 05:28:38 PM PDT 24
Finished Jul 24 05:31:32 PM PDT 24
Peak memory 206920 kb
Host smart-bcb1a6a0-b8d0-4edc-96d2-6fa9bb3b0530
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3731482079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.3731482079
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_iso_retraction.1083044827
Short name T2584
Test name
Test status
Simulation time 10171335897 ps
CPU time 84.02 seconds
Started Jul 24 05:28:37 PM PDT 24
Finished Jul 24 05:30:01 PM PDT 24
Peak memory 206844 kb
Host smart-becb7a9b-4633-4b83-8eae-efbb244a310e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10830
44827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_iso_retraction.1083044827
Directory /workspace/37.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.463497135
Short name T1150
Test name
Test status
Simulation time 217053296 ps
CPU time 0.84 seconds
Started Jul 24 05:28:53 PM PDT 24
Finished Jul 24 05:28:54 PM PDT 24
Peak memory 206516 kb
Host smart-d3fc5457-cd56-4e73-9926-47cc3f9a67e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46349
7135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.463497135
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.633597816
Short name T1841
Test name
Test status
Simulation time 23338627198 ps
CPU time 20.61 seconds
Started Jul 24 05:28:41 PM PDT 24
Finished Jul 24 05:29:02 PM PDT 24
Peak memory 206680 kb
Host smart-c5cc375c-1a17-430f-9a25-e912cea605d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63359
7816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.633597816
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.1699728791
Short name T2726
Test name
Test status
Simulation time 3361805867 ps
CPU time 3.82 seconds
Started Jul 24 05:28:40 PM PDT 24
Finished Jul 24 05:28:45 PM PDT 24
Peak memory 206668 kb
Host smart-9d8d03ed-401d-41b9-a595-6f78fe07b7c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16997
28791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.1699728791
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.4213157231
Short name T906
Test name
Test status
Simulation time 7634291836 ps
CPU time 58.45 seconds
Started Jul 24 05:28:43 PM PDT 24
Finished Jul 24 05:29:41 PM PDT 24
Peak memory 206972 kb
Host smart-999b9719-38b8-47a4-a710-f728ced1bc56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42131
57231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.4213157231
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.3885228395
Short name T2189
Test name
Test status
Simulation time 5286993759 ps
CPU time 145.87 seconds
Started Jul 24 05:28:56 PM PDT 24
Finished Jul 24 05:31:22 PM PDT 24
Peak memory 206908 kb
Host smart-9d52498d-a30a-4d83-9bfe-9a0e5935530d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3885228395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.3885228395
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.937749775
Short name T1798
Test name
Test status
Simulation time 276463025 ps
CPU time 1.01 seconds
Started Jul 24 05:28:39 PM PDT 24
Finished Jul 24 05:28:40 PM PDT 24
Peak memory 206564 kb
Host smart-09a0414f-37de-460b-b9ba-e72e0d4e256c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=937749775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.937749775
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.3600900834
Short name T2282
Test name
Test status
Simulation time 194175959 ps
CPU time 0.87 seconds
Started Jul 24 05:28:37 PM PDT 24
Finished Jul 24 05:28:38 PM PDT 24
Peak memory 206520 kb
Host smart-ce6ef0e7-b0e9-46d5-9d13-80ba74838cfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36009
00834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.3600900834
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.1471034057
Short name T5
Test name
Test status
Simulation time 5038324590 ps
CPU time 46.33 seconds
Started Jul 24 05:28:55 PM PDT 24
Finished Jul 24 05:29:41 PM PDT 24
Peak memory 206864 kb
Host smart-16309615-f0c9-4dc3-af94-6e0d2da7d29e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14710
34057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.1471034057
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.17740684
Short name T835
Test name
Test status
Simulation time 3840721075 ps
CPU time 26.14 seconds
Started Jul 24 05:28:46 PM PDT 24
Finished Jul 24 05:29:12 PM PDT 24
Peak memory 206936 kb
Host smart-4f1b2a60-7f6c-4d44-90ac-2c2b6519b63f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=17740684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.17740684
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.5076776
Short name T1484
Test name
Test status
Simulation time 173683470 ps
CPU time 0.79 seconds
Started Jul 24 05:28:42 PM PDT 24
Finished Jul 24 05:28:43 PM PDT 24
Peak memory 206580 kb
Host smart-c8739760-fe50-47d0-a724-7075fb58133f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=5076776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.5076776
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.942124542
Short name T1481
Test name
Test status
Simulation time 161431308 ps
CPU time 0.79 seconds
Started Jul 24 05:28:36 PM PDT 24
Finished Jul 24 05:28:37 PM PDT 24
Peak memory 206644 kb
Host smart-d076c788-d744-42b9-9372-c3cce76e8da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94212
4542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.942124542
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.188573568
Short name T1948
Test name
Test status
Simulation time 206221006 ps
CPU time 0.83 seconds
Started Jul 24 05:28:43 PM PDT 24
Finished Jul 24 05:28:44 PM PDT 24
Peak memory 206592 kb
Host smart-11ab0e4d-c02d-4964-9f2c-4d78d79ebdaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18857
3568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.188573568
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.719621309
Short name T1519
Test name
Test status
Simulation time 173406964 ps
CPU time 0.8 seconds
Started Jul 24 05:28:39 PM PDT 24
Finished Jul 24 05:28:40 PM PDT 24
Peak memory 206488 kb
Host smart-96c44a90-bf81-4bf6-b239-d990dc7ab47b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71962
1309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.719621309
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.3703627397
Short name T364
Test name
Test status
Simulation time 195376147 ps
CPU time 0.82 seconds
Started Jul 24 05:28:47 PM PDT 24
Finished Jul 24 05:28:48 PM PDT 24
Peak memory 206580 kb
Host smart-94f845c9-b8a0-4b07-9558-330d118af4f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37036
27397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.3703627397
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.558542378
Short name T525
Test name
Test status
Simulation time 161085196 ps
CPU time 0.83 seconds
Started Jul 24 05:28:48 PM PDT 24
Finished Jul 24 05:28:49 PM PDT 24
Peak memory 206536 kb
Host smart-53a1ab33-c30f-47c6-b48d-cbde9bfd7b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55854
2378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.558542378
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.166212609
Short name T797
Test name
Test status
Simulation time 151921597 ps
CPU time 0.8 seconds
Started Jul 24 05:28:40 PM PDT 24
Finished Jul 24 05:28:41 PM PDT 24
Peak memory 206640 kb
Host smart-e086e3f2-e3e8-47fc-afc9-471c44a6e247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16621
2609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.166212609
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.469360817
Short name T1474
Test name
Test status
Simulation time 228567137 ps
CPU time 0.97 seconds
Started Jul 24 05:28:53 PM PDT 24
Finished Jul 24 05:28:54 PM PDT 24
Peak memory 206456 kb
Host smart-14b6ba74-6406-4a25-9e5f-d93d07bd99f6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=469360817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.469360817
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.1808185229
Short name T367
Test name
Test status
Simulation time 151655709 ps
CPU time 0.75 seconds
Started Jul 24 05:28:38 PM PDT 24
Finished Jul 24 05:28:39 PM PDT 24
Peak memory 206564 kb
Host smart-edc0eaa2-f474-441a-92e4-bdea1af1f49f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18081
85229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.1808185229
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.1075601390
Short name T1364
Test name
Test status
Simulation time 39912293 ps
CPU time 0.65 seconds
Started Jul 24 05:28:49 PM PDT 24
Finished Jul 24 05:28:50 PM PDT 24
Peak memory 206536 kb
Host smart-ca96370f-1abf-4128-aadb-3e4f7109a794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10756
01390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.1075601390
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.2043894931
Short name T520
Test name
Test status
Simulation time 17899726134 ps
CPU time 35.62 seconds
Started Jul 24 05:28:39 PM PDT 24
Finished Jul 24 05:29:15 PM PDT 24
Peak memory 206956 kb
Host smart-355ca18c-8b15-42c5-a31d-6b11c0a395b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20438
94931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.2043894931
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.2443262641
Short name T2633
Test name
Test status
Simulation time 180680209 ps
CPU time 0.8 seconds
Started Jul 24 05:28:40 PM PDT 24
Finished Jul 24 05:28:42 PM PDT 24
Peak memory 206512 kb
Host smart-7bb8dad4-235a-47cd-8132-eed56fe6c7be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24432
62641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.2443262641
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.1168673777
Short name T2421
Test name
Test status
Simulation time 181675984 ps
CPU time 0.82 seconds
Started Jul 24 05:28:36 PM PDT 24
Finished Jul 24 05:28:37 PM PDT 24
Peak memory 206592 kb
Host smart-3a11fb43-2963-4359-9580-04deb4e4c4d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11686
73777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.1168673777
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.4264004709
Short name T578
Test name
Test status
Simulation time 222643299 ps
CPU time 0.87 seconds
Started Jul 24 05:28:35 PM PDT 24
Finished Jul 24 05:28:36 PM PDT 24
Peak memory 206648 kb
Host smart-883b0d55-bca9-4339-a35d-5ba5737825f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42640
04709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.4264004709
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.370381302
Short name T386
Test name
Test status
Simulation time 194990947 ps
CPU time 0.85 seconds
Started Jul 24 05:28:48 PM PDT 24
Finished Jul 24 05:28:49 PM PDT 24
Peak memory 206560 kb
Host smart-99698f66-ddbd-4ba3-8c50-d00b0aaab745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37038
1302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.370381302
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.3355565220
Short name T1607
Test name
Test status
Simulation time 229345111 ps
CPU time 0.85 seconds
Started Jul 24 05:28:45 PM PDT 24
Finished Jul 24 05:28:46 PM PDT 24
Peak memory 206644 kb
Host smart-db48019b-094f-485c-9d1f-3358edf0f29a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33555
65220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.3355565220
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.3531749414
Short name T2471
Test name
Test status
Simulation time 150464832 ps
CPU time 0.77 seconds
Started Jul 24 05:28:39 PM PDT 24
Finished Jul 24 05:28:40 PM PDT 24
Peak memory 206560 kb
Host smart-c341b233-c94c-454f-a791-c2fadf19d38e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35317
49414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.3531749414
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.915982933
Short name T518
Test name
Test status
Simulation time 180448655 ps
CPU time 0.78 seconds
Started Jul 24 05:28:43 PM PDT 24
Finished Jul 24 05:28:44 PM PDT 24
Peak memory 206556 kb
Host smart-2c7ba9ca-f328-427b-b60f-5c741cc4a0e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91598
2933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.915982933
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.2847501146
Short name T805
Test name
Test status
Simulation time 233428859 ps
CPU time 0.94 seconds
Started Jul 24 05:28:42 PM PDT 24
Finished Jul 24 05:28:44 PM PDT 24
Peak memory 206644 kb
Host smart-c8f5a30d-4fbe-4d14-bb19-03b232f336a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28475
01146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.2847501146
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.1118661386
Short name T2254
Test name
Test status
Simulation time 6210683576 ps
CPU time 41.31 seconds
Started Jul 24 05:28:53 PM PDT 24
Finished Jul 24 05:29:35 PM PDT 24
Peak memory 206772 kb
Host smart-1d6dfcca-a0a6-41bd-84aa-a0476bd8241d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1118661386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.1118661386
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.4277091770
Short name T1962
Test name
Test status
Simulation time 181411306 ps
CPU time 0.77 seconds
Started Jul 24 05:28:41 PM PDT 24
Finished Jul 24 05:28:42 PM PDT 24
Peak memory 206496 kb
Host smart-9e8e168a-1269-4fde-a736-57483c5d1eb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42770
91770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.4277091770
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.2320877497
Short name T1189
Test name
Test status
Simulation time 179434296 ps
CPU time 0.79 seconds
Started Jul 24 05:28:47 PM PDT 24
Finished Jul 24 05:28:48 PM PDT 24
Peak memory 206488 kb
Host smart-4f299a6c-4b5a-4278-96ca-35bddbb229c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23208
77497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.2320877497
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.2357745399
Short name T1648
Test name
Test status
Simulation time 817747643 ps
CPU time 1.82 seconds
Started Jul 24 05:28:38 PM PDT 24
Finished Jul 24 05:28:40 PM PDT 24
Peak memory 206732 kb
Host smart-ecf1e709-d8cd-4e20-aab1-e3520cf91dc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23577
45399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.2357745399
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.1422545085
Short name T1216
Test name
Test status
Simulation time 3634627177 ps
CPU time 25.59 seconds
Started Jul 24 05:28:31 PM PDT 24
Finished Jul 24 05:28:57 PM PDT 24
Peak memory 206864 kb
Host smart-b651250c-56db-45c9-8754-13550e17308a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14225
45085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.1422545085
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.3684368463
Short name T2638
Test name
Test status
Simulation time 51154208 ps
CPU time 0.67 seconds
Started Jul 24 05:29:04 PM PDT 24
Finished Jul 24 05:29:05 PM PDT 24
Peak memory 206572 kb
Host smart-15991866-3c05-44e3-af89-ccabb8ac7cac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3684368463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.3684368463
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.1176253314
Short name T642
Test name
Test status
Simulation time 4314022915 ps
CPU time 4.76 seconds
Started Jul 24 05:28:33 PM PDT 24
Finished Jul 24 05:28:38 PM PDT 24
Peak memory 206608 kb
Host smart-6a36e8f7-8f09-4440-ad2c-51e2cd431b95
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1176253314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.1176253314
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.919796993
Short name T2376
Test name
Test status
Simulation time 23489230237 ps
CPU time 23.81 seconds
Started Jul 24 05:28:34 PM PDT 24
Finished Jul 24 05:28:58 PM PDT 24
Peak memory 206920 kb
Host smart-6624104b-2f38-452c-b362-2462a0802b2f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=919796993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.919796993
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.642989226
Short name T904
Test name
Test status
Simulation time 164298932 ps
CPU time 0.77 seconds
Started Jul 24 05:28:57 PM PDT 24
Finished Jul 24 05:28:58 PM PDT 24
Peak memory 206556 kb
Host smart-9e456f9e-9a93-452f-91a0-389fb6438598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64298
9226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.642989226
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.2634449053
Short name T54
Test name
Test status
Simulation time 143717849 ps
CPU time 0.73 seconds
Started Jul 24 05:28:55 PM PDT 24
Finished Jul 24 05:28:56 PM PDT 24
Peak memory 206560 kb
Host smart-785dda55-086a-4bc0-a761-dfd1141e8210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26344
49053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.2634449053
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.4220915945
Short name T2234
Test name
Test status
Simulation time 283587036 ps
CPU time 1.04 seconds
Started Jul 24 05:28:43 PM PDT 24
Finished Jul 24 05:28:44 PM PDT 24
Peak memory 206576 kb
Host smart-d3d0d596-f049-4a98-b619-7ad035f68e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42209
15945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.4220915945
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.577512605
Short name T2671
Test name
Test status
Simulation time 1011439626 ps
CPU time 2.56 seconds
Started Jul 24 05:28:58 PM PDT 24
Finished Jul 24 05:29:00 PM PDT 24
Peak memory 206756 kb
Host smart-b63c9056-94e2-4955-b86b-48c67bb4ec8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57751
2605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.577512605
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.185245898
Short name T2622
Test name
Test status
Simulation time 22228989912 ps
CPU time 40.68 seconds
Started Jul 24 05:28:57 PM PDT 24
Finished Jul 24 05:29:38 PM PDT 24
Peak memory 206896 kb
Host smart-acfb7796-39b5-4fbc-a13d-70065e68b351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18524
5898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.185245898
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.3972517905
Short name T1198
Test name
Test status
Simulation time 459391525 ps
CPU time 1.37 seconds
Started Jul 24 05:28:50 PM PDT 24
Finished Jul 24 05:28:52 PM PDT 24
Peak memory 206584 kb
Host smart-500ab5ec-56a0-4eae-bbe6-2626ad2db39c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39725
17905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.3972517905
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.882365254
Short name T1872
Test name
Test status
Simulation time 168493491 ps
CPU time 0.78 seconds
Started Jul 24 05:28:59 PM PDT 24
Finished Jul 24 05:29:00 PM PDT 24
Peak memory 206552 kb
Host smart-02e39e1e-449e-4c9b-b9da-527b342ad79b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88236
5254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.882365254
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.1946285540
Short name T1667
Test name
Test status
Simulation time 48189434 ps
CPU time 0.69 seconds
Started Jul 24 05:29:04 PM PDT 24
Finished Jul 24 05:29:05 PM PDT 24
Peak memory 206544 kb
Host smart-ec2b4f7e-4be7-48a6-a38e-ba9c9345933b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19462
85540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.1946285540
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.3272690740
Short name T1702
Test name
Test status
Simulation time 832593725 ps
CPU time 1.98 seconds
Started Jul 24 05:29:00 PM PDT 24
Finished Jul 24 05:29:02 PM PDT 24
Peak memory 206696 kb
Host smart-7582083f-8ab6-4d8a-a9db-de38a5656b36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32726
90740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.3272690740
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.1708859078
Short name T792
Test name
Test status
Simulation time 181502060 ps
CPU time 1.69 seconds
Started Jul 24 05:28:53 PM PDT 24
Finished Jul 24 05:28:55 PM PDT 24
Peak memory 206832 kb
Host smart-26c4ac3b-bbc8-448f-acb0-4d4c69568108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17088
59078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.1708859078
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.895095145
Short name T2456
Test name
Test status
Simulation time 222503244 ps
CPU time 0.84 seconds
Started Jul 24 05:28:59 PM PDT 24
Finished Jul 24 05:29:00 PM PDT 24
Peak memory 206384 kb
Host smart-b757530c-7b2c-4cf5-9115-3ac2d8e14397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89509
5145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.895095145
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.3174918857
Short name T313
Test name
Test status
Simulation time 155133040 ps
CPU time 0.74 seconds
Started Jul 24 05:28:46 PM PDT 24
Finished Jul 24 05:28:47 PM PDT 24
Peak memory 206608 kb
Host smart-18082e5a-76a2-42be-ae42-4bef6161c113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31749
18857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.3174918857
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.1395444464
Short name T72
Test name
Test status
Simulation time 177303977 ps
CPU time 0.83 seconds
Started Jul 24 05:28:59 PM PDT 24
Finished Jul 24 05:29:05 PM PDT 24
Peak memory 206592 kb
Host smart-d82477c8-04d2-4335-abae-a1cf40ac0640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13954
44464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.1395444464
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.1763753164
Short name T2434
Test name
Test status
Simulation time 7188193771 ps
CPU time 46.6 seconds
Started Jul 24 05:28:53 PM PDT 24
Finished Jul 24 05:29:40 PM PDT 24
Peak memory 206840 kb
Host smart-8de08ccd-9e4d-4467-98a4-2935ba8103c3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1763753164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.1763753164
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_iso_retraction.2110258604
Short name T108
Test name
Test status
Simulation time 3895244582 ps
CPU time 11.53 seconds
Started Jul 24 05:29:00 PM PDT 24
Finished Jul 24 05:29:12 PM PDT 24
Peak memory 206824 kb
Host smart-a14c2b6a-39d3-4bc3-829d-ea1e4de487d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21102
58604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_iso_retraction.2110258604
Directory /workspace/38.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.4067872424
Short name T528
Test name
Test status
Simulation time 253176773 ps
CPU time 0.97 seconds
Started Jul 24 05:28:47 PM PDT 24
Finished Jul 24 05:28:51 PM PDT 24
Peak memory 206644 kb
Host smart-ba0f23ad-9e10-4b1a-9644-b82474c07fc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40678
72424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.4067872424
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.64853387
Short name T424
Test name
Test status
Simulation time 23321350322 ps
CPU time 22.85 seconds
Started Jul 24 05:28:49 PM PDT 24
Finished Jul 24 05:29:12 PM PDT 24
Peak memory 206780 kb
Host smart-f8a5d905-3c80-4f44-8233-248b19ffe137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64853
387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.64853387
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.2454277601
Short name T1989
Test name
Test status
Simulation time 3321814445 ps
CPU time 4.04 seconds
Started Jul 24 05:28:51 PM PDT 24
Finished Jul 24 05:28:55 PM PDT 24
Peak memory 206712 kb
Host smart-5838d5fd-67c4-413e-884b-09d533a7936b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24542
77601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.2454277601
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.343269647
Short name T1432
Test name
Test status
Simulation time 11722777823 ps
CPU time 316.7 seconds
Started Jul 24 05:29:04 PM PDT 24
Finished Jul 24 05:34:21 PM PDT 24
Peak memory 206916 kb
Host smart-0889de4f-a2fc-4fdb-8f6e-ecabf5f8d8e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34326
9647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.343269647
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.1314246579
Short name T957
Test name
Test status
Simulation time 2945134064 ps
CPU time 27.51 seconds
Started Jul 24 05:28:58 PM PDT 24
Finished Jul 24 05:29:31 PM PDT 24
Peak memory 206900 kb
Host smart-bdd57a43-9e8c-4922-8f9c-ad96f6cd5a63
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1314246579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.1314246579
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.1079781503
Short name T1836
Test name
Test status
Simulation time 250134453 ps
CPU time 0.9 seconds
Started Jul 24 05:28:49 PM PDT 24
Finished Jul 24 05:28:50 PM PDT 24
Peak memory 206452 kb
Host smart-d44be9a8-f8a8-43be-a512-266ea803e448
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1079781503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.1079781503
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.230435154
Short name T907
Test name
Test status
Simulation time 206291386 ps
CPU time 0.89 seconds
Started Jul 24 05:29:01 PM PDT 24
Finished Jul 24 05:29:02 PM PDT 24
Peak memory 206788 kb
Host smart-5b27127c-91ee-4fa7-9b4a-2b63b350a2c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23043
5154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.230435154
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.2203745600
Short name T1577
Test name
Test status
Simulation time 3598964740 ps
CPU time 24.88 seconds
Started Jul 24 05:28:47 PM PDT 24
Finished Jul 24 05:29:12 PM PDT 24
Peak memory 206892 kb
Host smart-a7ef5f09-40ad-420a-9a7a-3c75714af4a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22037
45600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.2203745600
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.4254699493
Short name T2081
Test name
Test status
Simulation time 5256301939 ps
CPU time 146.12 seconds
Started Jul 24 05:29:04 PM PDT 24
Finished Jul 24 05:31:31 PM PDT 24
Peak memory 206864 kb
Host smart-a52d8def-4f05-4025-9aaa-1bec9ddf1dba
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4254699493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.4254699493
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.3948680552
Short name T2314
Test name
Test status
Simulation time 151428046 ps
CPU time 0.77 seconds
Started Jul 24 05:28:51 PM PDT 24
Finished Jul 24 05:28:52 PM PDT 24
Peak memory 206552 kb
Host smart-df52851c-3a89-4332-82e0-740e8764d118
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3948680552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.3948680552
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.1648605045
Short name T371
Test name
Test status
Simulation time 178630017 ps
CPU time 0.78 seconds
Started Jul 24 05:28:45 PM PDT 24
Finished Jul 24 05:28:46 PM PDT 24
Peak memory 206584 kb
Host smart-c1990995-6ec6-4e97-888a-fb8c07331f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16486
05045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.1648605045
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.1077976621
Short name T127
Test name
Test status
Simulation time 179139815 ps
CPU time 0.8 seconds
Started Jul 24 05:28:47 PM PDT 24
Finished Jul 24 05:28:48 PM PDT 24
Peak memory 206472 kb
Host smart-1dd12151-daab-43df-8409-54316f097eac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10779
76621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.1077976621
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.2262773351
Short name T734
Test name
Test status
Simulation time 167235933 ps
CPU time 0.79 seconds
Started Jul 24 05:28:46 PM PDT 24
Finished Jul 24 05:28:47 PM PDT 24
Peak memory 206520 kb
Host smart-e4dfdb80-3b14-4483-bb55-4bcebfd5035d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22627
73351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.2262773351
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.3571225494
Short name T1061
Test name
Test status
Simulation time 195756764 ps
CPU time 0.8 seconds
Started Jul 24 05:28:44 PM PDT 24
Finished Jul 24 05:28:45 PM PDT 24
Peak memory 206540 kb
Host smart-0447063d-d68a-4112-a6ae-519c83d1cdac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35712
25494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.3571225494
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.2636596154
Short name T1357
Test name
Test status
Simulation time 171629417 ps
CPU time 0.8 seconds
Started Jul 24 05:29:14 PM PDT 24
Finished Jul 24 05:29:15 PM PDT 24
Peak memory 206640 kb
Host smart-c1540fd8-d4dc-4132-8640-20b5e81bfd8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26365
96154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.2636596154
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.3677179796
Short name T1661
Test name
Test status
Simulation time 232133414 ps
CPU time 0.86 seconds
Started Jul 24 05:29:11 PM PDT 24
Finished Jul 24 05:29:12 PM PDT 24
Peak memory 206560 kb
Host smart-10746f65-75e4-4213-a0b4-b69f427a53ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36771
79796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.3677179796
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.938128633
Short name T976
Test name
Test status
Simulation time 194477635 ps
CPU time 0.91 seconds
Started Jul 24 05:28:51 PM PDT 24
Finished Jul 24 05:28:52 PM PDT 24
Peak memory 206540 kb
Host smart-31863aa4-a316-4b3e-bed3-b1b8db8d83d1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=938128633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.938128633
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.3144038543
Short name T181
Test name
Test status
Simulation time 153692882 ps
CPU time 0.79 seconds
Started Jul 24 05:28:44 PM PDT 24
Finished Jul 24 05:28:45 PM PDT 24
Peak memory 206596 kb
Host smart-e2e1028f-35a0-4319-ad9d-0ae6dfbadcfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31440
38543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.3144038543
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.533294718
Short name T26
Test name
Test status
Simulation time 43812513 ps
CPU time 0.66 seconds
Started Jul 24 05:29:02 PM PDT 24
Finished Jul 24 05:29:03 PM PDT 24
Peak memory 206584 kb
Host smart-4466ec3d-5a8a-42ee-ae57-66dd79f7e894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53329
4718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.533294718
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.2529039260
Short name T1031
Test name
Test status
Simulation time 22020904701 ps
CPU time 52.85 seconds
Started Jul 24 05:29:18 PM PDT 24
Finished Jul 24 05:30:11 PM PDT 24
Peak memory 215152 kb
Host smart-d24f6d21-89fa-4395-8a02-eaa6364f9c07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25290
39260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.2529039260
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.3748023358
Short name T236
Test name
Test status
Simulation time 172938382 ps
CPU time 0.85 seconds
Started Jul 24 05:28:59 PM PDT 24
Finished Jul 24 05:29:00 PM PDT 24
Peak memory 206544 kb
Host smart-7c134005-f19f-44bf-a12f-4124abdf8d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37480
23358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.3748023358
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.478936207
Short name T679
Test name
Test status
Simulation time 191708024 ps
CPU time 0.86 seconds
Started Jul 24 05:28:45 PM PDT 24
Finished Jul 24 05:28:46 PM PDT 24
Peak memory 206780 kb
Host smart-6e166c35-1ff5-49b5-8514-1a34c0176c6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47893
6207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.478936207
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.2824155471
Short name T2538
Test name
Test status
Simulation time 247198554 ps
CPU time 0.9 seconds
Started Jul 24 05:29:02 PM PDT 24
Finished Jul 24 05:29:04 PM PDT 24
Peak memory 206520 kb
Host smart-10eb3b43-714e-4d05-baf8-b590ad9c669d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28241
55471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.2824155471
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.3881955799
Short name T531
Test name
Test status
Simulation time 170991218 ps
CPU time 0.84 seconds
Started Jul 24 05:28:53 PM PDT 24
Finished Jul 24 05:28:54 PM PDT 24
Peak memory 206448 kb
Host smart-8c5954c3-0c48-4d4b-8778-495a7e76125e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38819
55799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.3881955799
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.1311881551
Short name T2613
Test name
Test status
Simulation time 134958383 ps
CPU time 0.76 seconds
Started Jul 24 05:28:56 PM PDT 24
Finished Jul 24 05:28:57 PM PDT 24
Peak memory 206584 kb
Host smart-4ecf3f46-67b4-4fae-928f-8a8b05e1c959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13118
81551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.1311881551
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.1223034750
Short name T1622
Test name
Test status
Simulation time 172880822 ps
CPU time 0.82 seconds
Started Jul 24 05:28:50 PM PDT 24
Finished Jul 24 05:28:51 PM PDT 24
Peak memory 206512 kb
Host smart-deda18e8-d7ee-4624-84ad-aa6dc842d5eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12230
34750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.1223034750
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.2722145015
Short name T1116
Test name
Test status
Simulation time 151044390 ps
CPU time 0.75 seconds
Started Jul 24 05:28:49 PM PDT 24
Finished Jul 24 05:28:50 PM PDT 24
Peak memory 206580 kb
Host smart-d6287498-191b-4ad4-a922-544a202b5111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27221
45015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.2722145015
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.921142480
Short name T1697
Test name
Test status
Simulation time 230636343 ps
CPU time 0.89 seconds
Started Jul 24 05:28:48 PM PDT 24
Finished Jul 24 05:28:49 PM PDT 24
Peak memory 206556 kb
Host smart-6837817c-9906-4cea-a5f9-59447464f1ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92114
2480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.921142480
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.1362156381
Short name T510
Test name
Test status
Simulation time 3495993445 ps
CPU time 96.62 seconds
Started Jul 24 05:28:52 PM PDT 24
Finished Jul 24 05:30:29 PM PDT 24
Peak memory 206912 kb
Host smart-fd3c5317-f47b-48db-8565-653a977162c8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1362156381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.1362156381
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.3172246678
Short name T2660
Test name
Test status
Simulation time 192625359 ps
CPU time 0.84 seconds
Started Jul 24 05:28:51 PM PDT 24
Finished Jul 24 05:28:52 PM PDT 24
Peak memory 206652 kb
Host smart-3372b3c2-9e51-4af8-922d-10b852cd92fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31722
46678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.3172246678
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.1944163928
Short name T725
Test name
Test status
Simulation time 177250208 ps
CPU time 0.84 seconds
Started Jul 24 05:28:51 PM PDT 24
Finished Jul 24 05:28:52 PM PDT 24
Peak memory 206596 kb
Host smart-43571f3a-cf9c-4e66-8023-683ead4ee234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19441
63928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.1944163928
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.1214789349
Short name T390
Test name
Test status
Simulation time 1200511226 ps
CPU time 2.31 seconds
Started Jul 24 05:28:59 PM PDT 24
Finished Jul 24 05:29:01 PM PDT 24
Peak memory 206808 kb
Host smart-b0fe787b-13ef-440f-9f05-ca761b3e8a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12147
89349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.1214789349
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.3690243371
Short name T619
Test name
Test status
Simulation time 7092575418 ps
CPU time 197.27 seconds
Started Jul 24 05:28:58 PM PDT 24
Finished Jul 24 05:32:15 PM PDT 24
Peak memory 206816 kb
Host smart-b0f504da-8866-43f5-bfbd-e0e75e5f3299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36902
43371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.3690243371
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.1984917840
Short name T2278
Test name
Test status
Simulation time 43160687 ps
CPU time 0.69 seconds
Started Jul 24 05:29:05 PM PDT 24
Finished Jul 24 05:29:06 PM PDT 24
Peak memory 206572 kb
Host smart-3389338f-86d3-419e-9cc4-08519e581d1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1984917840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.1984917840
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.1532296264
Short name T2631
Test name
Test status
Simulation time 3603371289 ps
CPU time 4.28 seconds
Started Jul 24 05:29:00 PM PDT 24
Finished Jul 24 05:29:05 PM PDT 24
Peak memory 206536 kb
Host smart-8e51996a-7bee-4f5b-a09e-7ab20f2b06d4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1532296264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.1532296264
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.2120136346
Short name T1676
Test name
Test status
Simulation time 13388955491 ps
CPU time 13.08 seconds
Started Jul 24 05:28:55 PM PDT 24
Finished Jul 24 05:29:08 PM PDT 24
Peak memory 206652 kb
Host smart-59a97381-9053-4d36-8ccc-5d1eb570aa0c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2120136346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.2120136346
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.3003603857
Short name T588
Test name
Test status
Simulation time 23420969829 ps
CPU time 24.41 seconds
Started Jul 24 05:28:52 PM PDT 24
Finished Jul 24 05:29:17 PM PDT 24
Peak memory 206716 kb
Host smart-7b1977ee-d8c7-42cb-9962-2ddc2dc7561a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3003603857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.3003603857
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.199142991
Short name T2038
Test name
Test status
Simulation time 162475197 ps
CPU time 0.83 seconds
Started Jul 24 05:28:52 PM PDT 24
Finished Jul 24 05:28:53 PM PDT 24
Peak memory 206780 kb
Host smart-9989ce15-a091-4dbc-b6cc-3a3b888a8b78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19914
2991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.199142991
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.2826776445
Short name T476
Test name
Test status
Simulation time 151363490 ps
CPU time 0.76 seconds
Started Jul 24 05:28:57 PM PDT 24
Finished Jul 24 05:28:58 PM PDT 24
Peak memory 206588 kb
Host smart-449cd8c1-23af-4836-80ef-c55d4a67acf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28267
76445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.2826776445
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.3303058964
Short name T1286
Test name
Test status
Simulation time 183706410 ps
CPU time 0.9 seconds
Started Jul 24 05:29:03 PM PDT 24
Finished Jul 24 05:29:04 PM PDT 24
Peak memory 206588 kb
Host smart-9250d10c-698a-489f-978d-6892043b12db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33030
58964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.3303058964
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.4127031384
Short name T2051
Test name
Test status
Simulation time 965716674 ps
CPU time 2.34 seconds
Started Jul 24 05:28:52 PM PDT 24
Finished Jul 24 05:28:54 PM PDT 24
Peak memory 206828 kb
Host smart-5042035f-ea2f-41e2-9833-ab9e010dccf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41270
31384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.4127031384
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.2934627776
Short name T86
Test name
Test status
Simulation time 21794056928 ps
CPU time 40.2 seconds
Started Jul 24 05:28:51 PM PDT 24
Finished Jul 24 05:29:31 PM PDT 24
Peak memory 206920 kb
Host smart-60d8382a-6e6e-45de-bd92-03f19b9a7b31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29346
27776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.2934627776
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.4095003680
Short name T1686
Test name
Test status
Simulation time 379838520 ps
CPU time 1.17 seconds
Started Jul 24 05:29:03 PM PDT 24
Finished Jul 24 05:29:04 PM PDT 24
Peak memory 206588 kb
Host smart-a9512f8d-4fd8-4e01-a5fa-8c3b93da5141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40950
03680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.4095003680
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.589513190
Short name T1483
Test name
Test status
Simulation time 149083419 ps
CPU time 0.75 seconds
Started Jul 24 05:28:48 PM PDT 24
Finished Jul 24 05:28:49 PM PDT 24
Peak memory 206580 kb
Host smart-973e6b07-f5d9-4a8f-8dac-aa4d12cae8c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58951
3190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.589513190
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.2143434777
Short name T1252
Test name
Test status
Simulation time 96652879 ps
CPU time 0.7 seconds
Started Jul 24 05:29:00 PM PDT 24
Finished Jul 24 05:29:01 PM PDT 24
Peak memory 206596 kb
Host smart-7adf1d99-f7a8-42b5-8fb6-5ba873c97f8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21434
34777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.2143434777
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.663913000
Short name T1795
Test name
Test status
Simulation time 849171920 ps
CPU time 2.03 seconds
Started Jul 24 05:28:54 PM PDT 24
Finished Jul 24 05:28:56 PM PDT 24
Peak memory 206784 kb
Host smart-2ee46836-ac8a-4e25-a7ee-34ab1fb6a000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66391
3000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.663913000
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.4010478560
Short name T622
Test name
Test status
Simulation time 257349064 ps
CPU time 1.57 seconds
Started Jul 24 05:29:06 PM PDT 24
Finished Jul 24 05:29:08 PM PDT 24
Peak memory 206776 kb
Host smart-2409d7c1-5961-4854-a153-b906b6ae2f99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40104
78560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.4010478560
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.1691762550
Short name T567
Test name
Test status
Simulation time 209133094 ps
CPU time 0.84 seconds
Started Jul 24 05:29:04 PM PDT 24
Finished Jul 24 05:29:06 PM PDT 24
Peak memory 206528 kb
Host smart-ba99e919-fcf8-4c7a-9369-1f72eae61a46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16917
62550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.1691762550
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.1255527067
Short name T612
Test name
Test status
Simulation time 142957322 ps
CPU time 0.86 seconds
Started Jul 24 05:29:00 PM PDT 24
Finished Jul 24 05:29:02 PM PDT 24
Peak memory 206584 kb
Host smart-6d88893b-fb0d-4e71-9792-9f7f947cfd2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12555
27067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.1255527067
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.2759730568
Short name T2632
Test name
Test status
Simulation time 206395326 ps
CPU time 0.82 seconds
Started Jul 24 05:28:47 PM PDT 24
Finished Jul 24 05:28:48 PM PDT 24
Peak memory 206628 kb
Host smart-a840c561-3fa8-49e6-bd4d-6974988139a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27597
30568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.2759730568
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_iso_retraction.2507467873
Short name T1434
Test name
Test status
Simulation time 9229432390 ps
CPU time 31.84 seconds
Started Jul 24 05:28:55 PM PDT 24
Finished Jul 24 05:29:27 PM PDT 24
Peak memory 206900 kb
Host smart-5a662fb1-617c-4177-b178-90aaf4217a82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25074
67873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_iso_retraction.2507467873
Directory /workspace/39.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.669575635
Short name T350
Test name
Test status
Simulation time 187219232 ps
CPU time 0.84 seconds
Started Jul 24 05:29:07 PM PDT 24
Finished Jul 24 05:29:08 PM PDT 24
Peak memory 206580 kb
Host smart-5fe09168-af4e-4d1d-b41a-18c099438ae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66957
5635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.669575635
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.856314008
Short name T418
Test name
Test status
Simulation time 23322252927 ps
CPU time 24.02 seconds
Started Jul 24 05:28:58 PM PDT 24
Finished Jul 24 05:29:22 PM PDT 24
Peak memory 206700 kb
Host smart-f3220e3f-8891-49d9-8d5c-9f85e88af736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85631
4008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.856314008
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.2502756877
Short name T1165
Test name
Test status
Simulation time 3315034642 ps
CPU time 4.05 seconds
Started Jul 24 05:28:58 PM PDT 24
Finished Jul 24 05:29:02 PM PDT 24
Peak memory 206704 kb
Host smart-59c73349-8c75-478a-b07b-2a06e18b6898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25027
56877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.2502756877
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.3139779411
Short name T2342
Test name
Test status
Simulation time 8963292324 ps
CPU time 64.78 seconds
Started Jul 24 05:28:57 PM PDT 24
Finished Jul 24 05:30:02 PM PDT 24
Peak memory 206972 kb
Host smart-05b2ac65-cbc2-45c2-8024-631153619788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31397
79411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.3139779411
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.3405474552
Short name T303
Test name
Test status
Simulation time 6805132410 ps
CPU time 64.18 seconds
Started Jul 24 05:29:16 PM PDT 24
Finished Jul 24 05:30:20 PM PDT 24
Peak memory 206908 kb
Host smart-380e17e9-512b-44ea-af10-6662affe56fa
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3405474552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.3405474552
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.969748147
Short name T410
Test name
Test status
Simulation time 238644119 ps
CPU time 0.94 seconds
Started Jul 24 05:29:04 PM PDT 24
Finished Jul 24 05:29:05 PM PDT 24
Peak memory 206604 kb
Host smart-b1e3bfb1-c8a0-48b5-bf0c-41c1c5e63fa6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=969748147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.969748147
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.148444396
Short name T1279
Test name
Test status
Simulation time 195217078 ps
CPU time 0.86 seconds
Started Jul 24 05:28:59 PM PDT 24
Finished Jul 24 05:29:00 PM PDT 24
Peak memory 206580 kb
Host smart-a9873e89-8db5-40a8-bb0a-d50d428f7fbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14844
4396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.148444396
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.2105964564
Short name T2276
Test name
Test status
Simulation time 4333960324 ps
CPU time 112.4 seconds
Started Jul 24 05:28:51 PM PDT 24
Finished Jul 24 05:30:43 PM PDT 24
Peak memory 206936 kb
Host smart-2f596a08-9496-4264-ae29-90d6a732d3ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21059
64564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.2105964564
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.1075200794
Short name T436
Test name
Test status
Simulation time 3189090773 ps
CPU time 89.97 seconds
Started Jul 24 05:28:42 PM PDT 24
Finished Jul 24 05:30:12 PM PDT 24
Peak memory 206876 kb
Host smart-ccecabe8-a013-4eb3-b77e-e1578bfcce74
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1075200794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.1075200794
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.2228805704
Short name T2545
Test name
Test status
Simulation time 148189466 ps
CPU time 0.81 seconds
Started Jul 24 05:29:02 PM PDT 24
Finished Jul 24 05:29:04 PM PDT 24
Peak memory 206636 kb
Host smart-dc62ff94-f81f-4ca9-bc19-99ca122ab136
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2228805704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.2228805704
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.1379991131
Short name T2163
Test name
Test status
Simulation time 143237430 ps
CPU time 0.78 seconds
Started Jul 24 05:28:55 PM PDT 24
Finished Jul 24 05:28:56 PM PDT 24
Peak memory 206632 kb
Host smart-3970085a-cdf4-498f-a744-e9c453f68f25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13799
91131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.1379991131
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.2939447028
Short name T124
Test name
Test status
Simulation time 158592160 ps
CPU time 0.81 seconds
Started Jul 24 05:28:49 PM PDT 24
Finished Jul 24 05:28:50 PM PDT 24
Peak memory 206596 kb
Host smart-add58c4c-e0a1-4010-bab2-59d80f634fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29394
47028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.2939447028
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.1232765730
Short name T2257
Test name
Test status
Simulation time 230275888 ps
CPU time 0.86 seconds
Started Jul 24 05:29:00 PM PDT 24
Finished Jul 24 05:29:01 PM PDT 24
Peak memory 206580 kb
Host smart-e351547a-caa8-4a4c-a340-f7a2e7d5790d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12327
65730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.1232765730
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.1191401048
Short name T1124
Test name
Test status
Simulation time 171778947 ps
CPU time 0.78 seconds
Started Jul 24 05:28:57 PM PDT 24
Finished Jul 24 05:28:58 PM PDT 24
Peak memory 206564 kb
Host smart-0b7420e2-8b9d-436a-8a61-804daafe33d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11914
01048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.1191401048
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.3218263623
Short name T312
Test name
Test status
Simulation time 217944088 ps
CPU time 0.8 seconds
Started Jul 24 05:29:06 PM PDT 24
Finished Jul 24 05:29:07 PM PDT 24
Peak memory 206588 kb
Host smart-dc6c1f84-9393-4d19-8063-8460ea1b5fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32182
63623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.3218263623
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.1665099676
Short name T1272
Test name
Test status
Simulation time 169579180 ps
CPU time 0.76 seconds
Started Jul 24 05:29:04 PM PDT 24
Finished Jul 24 05:29:05 PM PDT 24
Peak memory 206592 kb
Host smart-d5c2650e-5307-4c7f-bab4-8f3017000c0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16650
99676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.1665099676
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.924367058
Short name T2059
Test name
Test status
Simulation time 264462717 ps
CPU time 0.99 seconds
Started Jul 24 05:28:55 PM PDT 24
Finished Jul 24 05:28:56 PM PDT 24
Peak memory 206628 kb
Host smart-ef2448a9-c1e4-4840-b3bf-b99e1479d9cb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=924367058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.924367058
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.3606953008
Short name T1067
Test name
Test status
Simulation time 152593617 ps
CPU time 0.77 seconds
Started Jul 24 05:28:58 PM PDT 24
Finished Jul 24 05:28:58 PM PDT 24
Peak memory 206548 kb
Host smart-614222cc-fbea-44a0-9adf-b4ee65ec56d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36069
53008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.3606953008
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.3925802089
Short name T1381
Test name
Test status
Simulation time 62353073 ps
CPU time 0.64 seconds
Started Jul 24 05:29:01 PM PDT 24
Finished Jul 24 05:29:02 PM PDT 24
Peak memory 206588 kb
Host smart-87dc1881-b77d-4e47-8995-09b557df49c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39258
02089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.3925802089
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.3866388367
Short name T239
Test name
Test status
Simulation time 15821173129 ps
CPU time 33.92 seconds
Started Jul 24 05:29:04 PM PDT 24
Finished Jul 24 05:29:39 PM PDT 24
Peak memory 207012 kb
Host smart-3e58c2ef-1cfa-4afb-9a65-4dd9fef68da8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38663
88367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.3866388367
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.1795764737
Short name T1097
Test name
Test status
Simulation time 204183822 ps
CPU time 0.83 seconds
Started Jul 24 05:29:04 PM PDT 24
Finished Jul 24 05:29:06 PM PDT 24
Peak memory 206576 kb
Host smart-b662d862-8837-44bf-b90d-038c851be693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17957
64737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.1795764737
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.2729465023
Short name T1260
Test name
Test status
Simulation time 185173694 ps
CPU time 0.83 seconds
Started Jul 24 05:29:03 PM PDT 24
Finished Jul 24 05:29:04 PM PDT 24
Peak memory 206600 kb
Host smart-7c957bac-4c4f-4dcc-aa47-1d9c30c04bad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27294
65023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.2729465023
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.3876450806
Short name T1277
Test name
Test status
Simulation time 234623327 ps
CPU time 0.96 seconds
Started Jul 24 05:28:50 PM PDT 24
Finished Jul 24 05:28:51 PM PDT 24
Peak memory 206504 kb
Host smart-cf1676f7-43bc-4428-975c-c891e666f7ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38764
50806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.3876450806
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.2820709447
Short name T2018
Test name
Test status
Simulation time 243648309 ps
CPU time 0.84 seconds
Started Jul 24 05:29:17 PM PDT 24
Finished Jul 24 05:29:18 PM PDT 24
Peak memory 206628 kb
Host smart-a0cb7707-759d-4847-a842-d23348bbcbca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28207
09447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.2820709447
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.3055194275
Short name T1373
Test name
Test status
Simulation time 182565798 ps
CPU time 0.82 seconds
Started Jul 24 05:29:13 PM PDT 24
Finished Jul 24 05:29:14 PM PDT 24
Peak memory 206552 kb
Host smart-ede8a6db-dc25-457c-82b1-ecd1b95ce1a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30551
94275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.3055194275
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.4054403221
Short name T1223
Test name
Test status
Simulation time 157896663 ps
CPU time 0.8 seconds
Started Jul 24 05:29:02 PM PDT 24
Finished Jul 24 05:29:08 PM PDT 24
Peak memory 206544 kb
Host smart-4a01bb39-d6e8-4718-b9c9-abc7adc65fb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40544
03221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.4054403221
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.329400435
Short name T984
Test name
Test status
Simulation time 159167980 ps
CPU time 0.76 seconds
Started Jul 24 05:29:03 PM PDT 24
Finished Jul 24 05:29:04 PM PDT 24
Peak memory 206528 kb
Host smart-843a0cb4-3ced-4573-b6d2-d5d7a912d6a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32940
0435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.329400435
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.4045117966
Short name T2039
Test name
Test status
Simulation time 244744910 ps
CPU time 0.93 seconds
Started Jul 24 05:29:08 PM PDT 24
Finished Jul 24 05:29:10 PM PDT 24
Peak memory 206600 kb
Host smart-a07eaa8a-34d0-4b1a-a50d-6a3690019aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40451
17966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.4045117966
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.2926346021
Short name T1275
Test name
Test status
Simulation time 6119202273 ps
CPU time 58.52 seconds
Started Jul 24 05:29:05 PM PDT 24
Finished Jul 24 05:30:04 PM PDT 24
Peak memory 206948 kb
Host smart-1fb8b87a-5ff4-48b6-a3ed-49772b972aec
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2926346021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.2926346021
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.2679226500
Short name T2586
Test name
Test status
Simulation time 155332779 ps
CPU time 0.8 seconds
Started Jul 24 05:29:07 PM PDT 24
Finished Jul 24 05:29:08 PM PDT 24
Peak memory 206520 kb
Host smart-ca31944f-0103-486d-87e4-71676f98c0a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26792
26500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.2679226500
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.3868340474
Short name T2293
Test name
Test status
Simulation time 267265919 ps
CPU time 0.97 seconds
Started Jul 24 05:29:13 PM PDT 24
Finished Jul 24 05:29:14 PM PDT 24
Peak memory 206620 kb
Host smart-eab8a28b-d0bd-4575-a8f5-43685d0a2bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38683
40474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.3868340474
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.1310744717
Short name T1401
Test name
Test status
Simulation time 941144601 ps
CPU time 2.1 seconds
Started Jul 24 05:29:05 PM PDT 24
Finished Jul 24 05:29:07 PM PDT 24
Peak memory 206788 kb
Host smart-97f1039a-3ab8-453d-a591-54aba2798236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13107
44717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.1310744717
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.3206635611
Short name T926
Test name
Test status
Simulation time 4761330789 ps
CPU time 130.73 seconds
Started Jul 24 05:29:07 PM PDT 24
Finished Jul 24 05:31:18 PM PDT 24
Peak memory 206908 kb
Host smart-ede87a8c-2434-4394-9292-263db431b2e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32066
35611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.3206635611
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.3781680733
Short name T794
Test name
Test status
Simulation time 73150978 ps
CPU time 0.72 seconds
Started Jul 24 05:24:27 PM PDT 24
Finished Jul 24 05:24:28 PM PDT 24
Peak memory 206648 kb
Host smart-93a510b8-cb40-4cc8-8362-7e39e9cba528
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3781680733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.3781680733
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.2038161366
Short name T2441
Test name
Test status
Simulation time 3604217348 ps
CPU time 4.59 seconds
Started Jul 24 05:24:17 PM PDT 24
Finished Jul 24 05:24:22 PM PDT 24
Peak memory 206740 kb
Host smart-2f390859-269c-4f20-8799-9b13c0e579b5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2038161366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.2038161366
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.2490050044
Short name T2101
Test name
Test status
Simulation time 13392497271 ps
CPU time 12.67 seconds
Started Jul 24 05:24:40 PM PDT 24
Finished Jul 24 05:24:53 PM PDT 24
Peak memory 206620 kb
Host smart-a0dac9a7-578e-4673-9d68-c4d76d8f11b8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2490050044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.2490050044
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.531196430
Short name T1490
Test name
Test status
Simulation time 23398739935 ps
CPU time 22.06 seconds
Started Jul 24 05:24:20 PM PDT 24
Finished Jul 24 05:24:42 PM PDT 24
Peak memory 206816 kb
Host smart-a858b4b9-2669-44f7-bf83-70fe6cecc0bb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=531196430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.531196430
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.2524515473
Short name T2016
Test name
Test status
Simulation time 150114692 ps
CPU time 0.75 seconds
Started Jul 24 05:24:17 PM PDT 24
Finished Jul 24 05:24:18 PM PDT 24
Peak memory 206552 kb
Host smart-cf5da8e1-6573-48fc-9027-ecfd4516f379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25245
15473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.2524515473
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.4070550303
Short name T45
Test name
Test status
Simulation time 164244896 ps
CPU time 0.78 seconds
Started Jul 24 05:24:17 PM PDT 24
Finished Jul 24 05:24:18 PM PDT 24
Peak memory 206492 kb
Host smart-bed7645d-8ada-4711-90c4-c666b4c8f4d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40705
50303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.4070550303
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.3877925224
Short name T80
Test name
Test status
Simulation time 161120922 ps
CPU time 0.8 seconds
Started Jul 24 05:24:29 PM PDT 24
Finished Jul 24 05:24:30 PM PDT 24
Peak memory 206560 kb
Host smart-c9223830-f222-41e5-bc27-2536b490a4ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38779
25224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.3877925224
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.2753736575
Short name T918
Test name
Test status
Simulation time 194647403 ps
CPU time 0.81 seconds
Started Jul 24 05:24:22 PM PDT 24
Finished Jul 24 05:24:23 PM PDT 24
Peak memory 206644 kb
Host smart-ae7f3458-dadf-4234-8b8d-4240a301d611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27537
36575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.2753736575
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.2549774421
Short name T2102
Test name
Test status
Simulation time 536376035 ps
CPU time 1.44 seconds
Started Jul 24 05:24:23 PM PDT 24
Finished Jul 24 05:24:25 PM PDT 24
Peak memory 206792 kb
Host smart-49a1af2c-5646-462f-a58a-103fe93eb9e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25497
74421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.2549774421
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.79235009
Short name T1046
Test name
Test status
Simulation time 1096437829 ps
CPU time 2.33 seconds
Started Jul 24 05:24:29 PM PDT 24
Finished Jul 24 05:24:32 PM PDT 24
Peak memory 206760 kb
Host smart-6210367f-09af-4482-b8f7-15597b1df7c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79235
009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.79235009
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.3302620036
Short name T1879
Test name
Test status
Simulation time 21290041754 ps
CPU time 38.79 seconds
Started Jul 24 05:24:14 PM PDT 24
Finished Jul 24 05:24:53 PM PDT 24
Peak memory 206840 kb
Host smart-dae58ae7-5b37-4c88-9302-1d8de449116f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33026
20036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.3302620036
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.3142902365
Short name T1630
Test name
Test status
Simulation time 422077508 ps
CPU time 1.3 seconds
Started Jul 24 05:24:14 PM PDT 24
Finished Jul 24 05:24:16 PM PDT 24
Peak memory 206504 kb
Host smart-916d919d-f7bc-4b11-9c10-594f8c11821c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31429
02365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.3142902365
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.2825622562
Short name T2268
Test name
Test status
Simulation time 184068329 ps
CPU time 0.78 seconds
Started Jul 24 05:24:15 PM PDT 24
Finished Jul 24 05:24:16 PM PDT 24
Peak memory 206592 kb
Host smart-a0cae3a4-1f59-4a53-b463-004e18759bf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28256
22562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.2825622562
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.4029675641
Short name T1221
Test name
Test status
Simulation time 30787843 ps
CPU time 0.65 seconds
Started Jul 24 05:24:11 PM PDT 24
Finished Jul 24 05:24:16 PM PDT 24
Peak memory 206540 kb
Host smart-178827b3-eeaf-4076-b78d-7d2ed2a0b12b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40296
75641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.4029675641
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.480239241
Short name T574
Test name
Test status
Simulation time 915591391 ps
CPU time 2.43 seconds
Started Jul 24 05:24:21 PM PDT 24
Finished Jul 24 05:24:24 PM PDT 24
Peak memory 206764 kb
Host smart-5665b23d-3a04-415d-a7cb-a01ba090ba29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48023
9241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.480239241
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.2940848065
Short name T2446
Test name
Test status
Simulation time 194703239 ps
CPU time 1.95 seconds
Started Jul 24 05:24:21 PM PDT 24
Finished Jul 24 05:24:23 PM PDT 24
Peak memory 206740 kb
Host smart-6f41ff7a-3e51-4eaa-a51c-8b125aaebfed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29408
48065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.2940848065
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.1124108704
Short name T695
Test name
Test status
Simulation time 94211020948 ps
CPU time 150.17 seconds
Started Jul 24 05:24:17 PM PDT 24
Finished Jul 24 05:26:47 PM PDT 24
Peak memory 206984 kb
Host smart-b3f66fe9-9271-4fc5-a7ec-f54cc3a270f4
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1124108704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.1124108704
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.3468549599
Short name T747
Test name
Test status
Simulation time 90142492767 ps
CPU time 110.75 seconds
Started Jul 24 05:24:13 PM PDT 24
Finished Jul 24 05:26:04 PM PDT 24
Peak memory 206896 kb
Host smart-46b043b2-3615-4ac8-b79f-c8a6be9c1857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468549599 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.3468549599
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.157182296
Short name T889
Test name
Test status
Simulation time 82109931127 ps
CPU time 117.25 seconds
Started Jul 24 05:24:17 PM PDT 24
Finished Jul 24 05:26:14 PM PDT 24
Peak memory 206900 kb
Host smart-9b599337-24ae-48ab-8bea-634487586816
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=157182296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.157182296
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.1201131740
Short name T2084
Test name
Test status
Simulation time 87161680209 ps
CPU time 125.64 seconds
Started Jul 24 05:24:33 PM PDT 24
Finished Jul 24 05:26:39 PM PDT 24
Peak memory 206888 kb
Host smart-11107b5b-4ad4-4471-819e-4367d8af89e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201131740 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.1201131740
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.3354265954
Short name T2288
Test name
Test status
Simulation time 99179466503 ps
CPU time 133.18 seconds
Started Jul 24 05:24:18 PM PDT 24
Finished Jul 24 05:26:32 PM PDT 24
Peak memory 206924 kb
Host smart-dc24b364-f850-4055-adc6-742af6bc94fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33542
65954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.3354265954
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.2893777415
Short name T1883
Test name
Test status
Simulation time 229129020 ps
CPU time 0.93 seconds
Started Jul 24 05:24:19 PM PDT 24
Finished Jul 24 05:24:20 PM PDT 24
Peak memory 206464 kb
Host smart-09ab9604-d1a9-4ab9-9bdf-8b5fc126db8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28937
77415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.2893777415
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.3600596114
Short name T519
Test name
Test status
Simulation time 143119367 ps
CPU time 0.73 seconds
Started Jul 24 05:24:24 PM PDT 24
Finished Jul 24 05:24:24 PM PDT 24
Peak memory 206544 kb
Host smart-380836fb-7467-49f8-a2e6-ee3df96f5160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36005
96114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.3600596114
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.2625803824
Short name T2595
Test name
Test status
Simulation time 186908338 ps
CPU time 0.78 seconds
Started Jul 24 05:24:19 PM PDT 24
Finished Jul 24 05:24:20 PM PDT 24
Peak memory 206544 kb
Host smart-218cb725-5940-41bf-ae44-7927a8ede47a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26258
03824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.2625803824
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_iso_retraction.1856979637
Short name T2415
Test name
Test status
Simulation time 9680927502 ps
CPU time 76.55 seconds
Started Jul 24 05:24:22 PM PDT 24
Finished Jul 24 05:25:39 PM PDT 24
Peak memory 206884 kb
Host smart-bbee353d-f419-448b-ba9a-71e396480f08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18569
79637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.1856979637
Directory /workspace/4.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.1647221746
Short name T1271
Test name
Test status
Simulation time 220675780 ps
CPU time 0.83 seconds
Started Jul 24 05:24:14 PM PDT 24
Finished Jul 24 05:24:15 PM PDT 24
Peak memory 206552 kb
Host smart-7ee08244-632a-4e09-89da-3452cd2900e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16472
21746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.1647221746
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.4078022864
Short name T404
Test name
Test status
Simulation time 23262415805 ps
CPU time 21.32 seconds
Started Jul 24 05:24:33 PM PDT 24
Finished Jul 24 05:24:55 PM PDT 24
Peak memory 206668 kb
Host smart-9b4fef84-27bf-4d2c-ba3e-199264d610b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40780
22864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.4078022864
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.2620999253
Short name T2381
Test name
Test status
Simulation time 3293333918 ps
CPU time 4.69 seconds
Started Jul 24 05:24:22 PM PDT 24
Finished Jul 24 05:24:31 PM PDT 24
Peak memory 206592 kb
Host smart-e5f80eae-ada6-4c05-a4b9-c78a6988b076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26209
99253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.2620999253
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.2035843947
Short name T1832
Test name
Test status
Simulation time 10054101240 ps
CPU time 74.8 seconds
Started Jul 24 05:24:15 PM PDT 24
Finished Jul 24 05:25:35 PM PDT 24
Peak memory 206916 kb
Host smart-cbc07bd3-9b37-47bf-beb9-d780e377604e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20358
43947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.2035843947
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.595631890
Short name T2506
Test name
Test status
Simulation time 4696378131 ps
CPU time 41.64 seconds
Started Jul 24 05:24:11 PM PDT 24
Finished Jul 24 05:24:52 PM PDT 24
Peak memory 206872 kb
Host smart-2f2f6348-fafe-4248-819c-868e21629f0c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=595631890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.595631890
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.1416215704
Short name T1238
Test name
Test status
Simulation time 278369148 ps
CPU time 0.9 seconds
Started Jul 24 05:24:22 PM PDT 24
Finished Jul 24 05:24:23 PM PDT 24
Peak memory 206564 kb
Host smart-abed6b6f-7c84-4f61-812e-25b1611f919a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1416215704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.1416215704
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.3082272851
Short name T543
Test name
Test status
Simulation time 238004708 ps
CPU time 0.89 seconds
Started Jul 24 05:24:20 PM PDT 24
Finished Jul 24 05:24:22 PM PDT 24
Peak memory 206580 kb
Host smart-bf1a2d52-a102-40f4-a372-b9d5873a3c71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30822
72851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.3082272851
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.257599367
Short name T1969
Test name
Test status
Simulation time 5737594721 ps
CPU time 54.24 seconds
Started Jul 24 05:24:25 PM PDT 24
Finished Jul 24 05:25:19 PM PDT 24
Peak memory 206908 kb
Host smart-42a6858b-5f92-43fa-b24f-454f3a39d52d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25759
9367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.257599367
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.3641931631
Short name T600
Test name
Test status
Simulation time 3292982137 ps
CPU time 31.63 seconds
Started Jul 24 05:24:29 PM PDT 24
Finished Jul 24 05:25:01 PM PDT 24
Peak memory 206808 kb
Host smart-ecdf6e24-88bb-4dc2-bd1e-5b5e32dc127f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3641931631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.3641931631
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.1343437506
Short name T453
Test name
Test status
Simulation time 211403243 ps
CPU time 0.84 seconds
Started Jul 24 05:24:16 PM PDT 24
Finished Jul 24 05:24:17 PM PDT 24
Peak memory 206552 kb
Host smart-beb6794b-1375-488b-85a1-adfc9da4671a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1343437506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.1343437506
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.3188120938
Short name T500
Test name
Test status
Simulation time 170173858 ps
CPU time 0.76 seconds
Started Jul 24 05:24:16 PM PDT 24
Finished Jul 24 05:24:17 PM PDT 24
Peak memory 206516 kb
Host smart-3640aa8b-dd9e-4346-bc44-545c4be3fe80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31881
20938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.3188120938
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.2274300506
Short name T116
Test name
Test status
Simulation time 206728959 ps
CPU time 0.92 seconds
Started Jul 24 05:24:25 PM PDT 24
Finished Jul 24 05:24:27 PM PDT 24
Peak memory 206516 kb
Host smart-f06f2996-1e2c-4e63-aa52-34f370608e20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22743
00506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.2274300506
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.2034295468
Short name T2494
Test name
Test status
Simulation time 185086300 ps
CPU time 0.86 seconds
Started Jul 24 05:24:21 PM PDT 24
Finished Jul 24 05:24:22 PM PDT 24
Peak memory 206600 kb
Host smart-c5d74d7a-501b-4ca7-92df-db2b8b3a2605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20342
95468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.2034295468
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.2901408947
Short name T2683
Test name
Test status
Simulation time 149515228 ps
CPU time 0.81 seconds
Started Jul 24 05:24:24 PM PDT 24
Finished Jul 24 05:24:25 PM PDT 24
Peak memory 206544 kb
Host smart-528bd78c-d135-426e-834c-eaf1e531efa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29014
08947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.2901408947
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.2200858095
Short name T2354
Test name
Test status
Simulation time 177466124 ps
CPU time 0.77 seconds
Started Jul 24 05:24:26 PM PDT 24
Finished Jul 24 05:24:27 PM PDT 24
Peak memory 206544 kb
Host smart-73ab5097-d77b-49c4-9ee0-e547747ea72a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22008
58095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.2200858095
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.3212308006
Short name T2301
Test name
Test status
Simulation time 147589249 ps
CPU time 0.76 seconds
Started Jul 24 05:24:27 PM PDT 24
Finished Jul 24 05:24:28 PM PDT 24
Peak memory 206612 kb
Host smart-51aa1da4-aa4d-4f04-b98c-6c0cea574b98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32123
08006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.3212308006
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.139356841
Short name T662
Test name
Test status
Simulation time 219948116 ps
CPU time 0.89 seconds
Started Jul 24 05:24:23 PM PDT 24
Finished Jul 24 05:24:24 PM PDT 24
Peak memory 206488 kb
Host smart-3a2d6432-6066-492c-a336-cb35ad18d954
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=139356841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.139356841
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.2026305023
Short name T1524
Test name
Test status
Simulation time 265198748 ps
CPU time 1.01 seconds
Started Jul 24 05:24:21 PM PDT 24
Finished Jul 24 05:24:22 PM PDT 24
Peak memory 206580 kb
Host smart-fa8d3f54-2041-470a-879d-77531f1917a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20263
05023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.2026305023
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.4250311880
Short name T1020
Test name
Test status
Simulation time 204148674 ps
CPU time 0.81 seconds
Started Jul 24 05:24:34 PM PDT 24
Finished Jul 24 05:24:35 PM PDT 24
Peak memory 206544 kb
Host smart-caf7e375-011b-4b0b-97e7-a00a08710e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42503
11880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.4250311880
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.2324152922
Short name T25
Test name
Test status
Simulation time 41909146 ps
CPU time 0.67 seconds
Started Jul 24 05:24:25 PM PDT 24
Finished Jul 24 05:24:25 PM PDT 24
Peak memory 206584 kb
Host smart-0d5c757f-9dd7-4ca3-a099-811308c6fed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23241
52922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.2324152922
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.3625972577
Short name T1833
Test name
Test status
Simulation time 12827629815 ps
CPU time 26.77 seconds
Started Jul 24 05:24:17 PM PDT 24
Finished Jul 24 05:24:44 PM PDT 24
Peak memory 215196 kb
Host smart-5a4bcc52-94ac-4198-bc26-e321c2f80854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36259
72577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.3625972577
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.647626377
Short name T931
Test name
Test status
Simulation time 233643708 ps
CPU time 0.96 seconds
Started Jul 24 05:24:31 PM PDT 24
Finished Jul 24 05:24:32 PM PDT 24
Peak memory 206592 kb
Host smart-1ed0e0de-14f9-4a93-ae21-06dc4c622c2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64762
6377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.647626377
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.1302670351
Short name T1407
Test name
Test status
Simulation time 218805942 ps
CPU time 0.88 seconds
Started Jul 24 05:24:30 PM PDT 24
Finished Jul 24 05:24:31 PM PDT 24
Peak memory 206584 kb
Host smart-0ca5bbc8-3476-4e13-a991-835a8f78bbbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13026
70351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.1302670351
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.2117347953
Short name T1550
Test name
Test status
Simulation time 8656922104 ps
CPU time 72.13 seconds
Started Jul 24 05:24:22 PM PDT 24
Finished Jul 24 05:25:34 PM PDT 24
Peak memory 206944 kb
Host smart-48654741-c607-4712-9a08-065e08ae10c7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2117347953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.2117347953
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.2305827768
Short name T1181
Test name
Test status
Simulation time 5129548561 ps
CPU time 43.53 seconds
Started Jul 24 05:24:17 PM PDT 24
Finished Jul 24 05:25:01 PM PDT 24
Peak memory 206840 kb
Host smart-7b57a3c9-60c9-40f5-9942-5f7b2919d096
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2305827768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.2305827768
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.3391372582
Short name T968
Test name
Test status
Simulation time 11160162079 ps
CPU time 203.78 seconds
Started Jul 24 05:24:21 PM PDT 24
Finished Jul 24 05:27:45 PM PDT 24
Peak memory 206996 kb
Host smart-8e33a461-6a41-4bcd-957f-400be7327c34
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3391372582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.3391372582
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.540991082
Short name T1517
Test name
Test status
Simulation time 175707854 ps
CPU time 0.81 seconds
Started Jul 24 05:24:40 PM PDT 24
Finished Jul 24 05:24:41 PM PDT 24
Peak memory 206612 kb
Host smart-47f50df3-f761-47cc-b13a-65a53bb980a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54099
1082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.540991082
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.3417377687
Short name T1108
Test name
Test status
Simulation time 160098223 ps
CPU time 0.73 seconds
Started Jul 24 05:24:12 PM PDT 24
Finished Jul 24 05:24:13 PM PDT 24
Peak memory 206596 kb
Host smart-be8694e6-bdaa-4dfc-846c-a8f0751fa3e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34173
77687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.3417377687
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.2601923917
Short name T2576
Test name
Test status
Simulation time 152601851 ps
CPU time 0.72 seconds
Started Jul 24 05:24:23 PM PDT 24
Finished Jul 24 05:24:24 PM PDT 24
Peak memory 206588 kb
Host smart-37f447fa-a2e3-409a-a0ec-03cd91794ad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26019
23917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.2601923917
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.1355211976
Short name T2242
Test name
Test status
Simulation time 168133997 ps
CPU time 0.8 seconds
Started Jul 24 05:24:20 PM PDT 24
Finished Jul 24 05:24:22 PM PDT 24
Peak memory 206584 kb
Host smart-a5eb3d08-9875-43e3-904f-f23eb235d5bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13552
11976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.1355211976
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.125121775
Short name T183
Test name
Test status
Simulation time 538027328 ps
CPU time 1.42 seconds
Started Jul 24 05:24:32 PM PDT 24
Finished Jul 24 05:24:34 PM PDT 24
Peak memory 224380 kb
Host smart-16cf400f-363e-4856-aed2-a0e9caaf062a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=125121775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.125121775
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.2379234733
Short name T2543
Test name
Test status
Simulation time 417333235 ps
CPU time 1.22 seconds
Started Jul 24 05:24:20 PM PDT 24
Finished Jul 24 05:24:22 PM PDT 24
Peak memory 206464 kb
Host smart-2c94a626-6951-4378-9585-91acbfb4caa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23792
34733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.2379234733
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.2919046841
Short name T2409
Test name
Test status
Simulation time 294312422 ps
CPU time 0.96 seconds
Started Jul 24 05:24:20 PM PDT 24
Finished Jul 24 05:24:21 PM PDT 24
Peak memory 206588 kb
Host smart-878a713a-20c3-4a63-8b56-56cca70dfea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29190
46841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.2919046841
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.85460166
Short name T2093
Test name
Test status
Simulation time 154342872 ps
CPU time 0.75 seconds
Started Jul 24 05:24:39 PM PDT 24
Finished Jul 24 05:24:40 PM PDT 24
Peak memory 206540 kb
Host smart-6c9fb540-d489-4fc3-a870-fce8ad18d2e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85460
166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.85460166
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.2984679126
Short name T1960
Test name
Test status
Simulation time 173333091 ps
CPU time 0.78 seconds
Started Jul 24 05:24:18 PM PDT 24
Finished Jul 24 05:24:19 PM PDT 24
Peak memory 206544 kb
Host smart-5bdd6734-d8c7-4c62-967a-0391feeac0d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29846
79126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.2984679126
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.1177965912
Short name T2333
Test name
Test status
Simulation time 214564819 ps
CPU time 0.92 seconds
Started Jul 24 05:24:13 PM PDT 24
Finished Jul 24 05:24:14 PM PDT 24
Peak memory 206620 kb
Host smart-b4843fbb-98bd-43f0-ac11-b9d2626ad2fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11779
65912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.1177965912
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.1829022761
Short name T1865
Test name
Test status
Simulation time 5452128420 ps
CPU time 150.33 seconds
Started Jul 24 05:24:32 PM PDT 24
Finished Jul 24 05:27:03 PM PDT 24
Peak memory 206908 kb
Host smart-a209586b-64d4-4454-a5b1-608793159ab5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1829022761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.1829022761
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.3730552498
Short name T346
Test name
Test status
Simulation time 192765484 ps
CPU time 0.81 seconds
Started Jul 24 05:24:21 PM PDT 24
Finished Jul 24 05:24:22 PM PDT 24
Peak memory 206588 kb
Host smart-8b9cd9b0-96c6-4a9d-be2a-16fbc1371d0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37305
52498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.3730552498
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.716822098
Short name T1998
Test name
Test status
Simulation time 186190861 ps
CPU time 0.84 seconds
Started Jul 24 05:24:27 PM PDT 24
Finished Jul 24 05:24:28 PM PDT 24
Peak memory 206568 kb
Host smart-3d2acaea-8580-4276-9280-b4806ab78967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71682
2098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.716822098
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.2888476531
Short name T1270
Test name
Test status
Simulation time 881402685 ps
CPU time 2.21 seconds
Started Jul 24 05:24:27 PM PDT 24
Finished Jul 24 05:24:30 PM PDT 24
Peak memory 206840 kb
Host smart-a8bd7716-dcd4-4385-b84d-ab717efdd779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28884
76531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.2888476531
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.1466640110
Short name T688
Test name
Test status
Simulation time 5394799127 ps
CPU time 50.5 seconds
Started Jul 24 05:24:28 PM PDT 24
Finished Jul 24 05:25:18 PM PDT 24
Peak memory 206784 kb
Host smart-ec718412-44b6-415d-9c6b-c838a60c6225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14666
40110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.1466640110
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.665898081
Short name T2085
Test name
Test status
Simulation time 49242381 ps
CPU time 0.68 seconds
Started Jul 24 05:29:11 PM PDT 24
Finished Jul 24 05:29:12 PM PDT 24
Peak memory 206452 kb
Host smart-dbe16529-0c03-4ccf-ab02-76324ef2e3ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=665898081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.665898081
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.3590485990
Short name T2444
Test name
Test status
Simulation time 4261696690 ps
CPU time 5.96 seconds
Started Jul 24 05:28:57 PM PDT 24
Finished Jul 24 05:29:03 PM PDT 24
Peak memory 206992 kb
Host smart-7c2c93e2-2874-4137-b8e3-6549fe63824d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3590485990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.3590485990
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.3670879957
Short name T1126
Test name
Test status
Simulation time 13332306420 ps
CPU time 13.2 seconds
Started Jul 24 05:29:00 PM PDT 24
Finished Jul 24 05:29:18 PM PDT 24
Peak memory 206708 kb
Host smart-032e9a89-51bb-4eb5-b84b-be399ee5f37b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3670879957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.3670879957
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.3883583861
Short name T2571
Test name
Test status
Simulation time 23370583133 ps
CPU time 29.94 seconds
Started Jul 24 05:29:14 PM PDT 24
Finished Jul 24 05:29:45 PM PDT 24
Peak memory 206700 kb
Host smart-23950ff9-d67d-474d-87f4-a963dee542ce
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3883583861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.3883583861
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.1469077648
Short name T472
Test name
Test status
Simulation time 163446937 ps
CPU time 0.83 seconds
Started Jul 24 05:28:59 PM PDT 24
Finished Jul 24 05:29:00 PM PDT 24
Peak memory 206588 kb
Host smart-7c8439f9-032a-483b-bf73-3e94bcc3f84d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14690
77648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.1469077648
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.3518707263
Short name T1001
Test name
Test status
Simulation time 194497946 ps
CPU time 0.87 seconds
Started Jul 24 05:29:08 PM PDT 24
Finished Jul 24 05:29:10 PM PDT 24
Peak memory 206548 kb
Host smart-7e48ba53-98d3-4f74-8f00-5cc7e960fe88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35187
07263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.3518707263
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.3353140470
Short name T1723
Test name
Test status
Simulation time 328881776 ps
CPU time 1.14 seconds
Started Jul 24 05:28:46 PM PDT 24
Finished Jul 24 05:28:47 PM PDT 24
Peak memory 206560 kb
Host smart-a919a134-c83b-43e0-8af4-e26a23b1a771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33531
40470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.3353140470
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.608315503
Short name T991
Test name
Test status
Simulation time 676148769 ps
CPU time 1.62 seconds
Started Jul 24 05:29:04 PM PDT 24
Finished Jul 24 05:29:07 PM PDT 24
Peak memory 206576 kb
Host smart-33facfd7-fd88-4b1d-a29d-400a160a61c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60831
5503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.608315503
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.361489239
Short name T511
Test name
Test status
Simulation time 15786061891 ps
CPU time 29.83 seconds
Started Jul 24 05:29:01 PM PDT 24
Finished Jul 24 05:29:31 PM PDT 24
Peak memory 206904 kb
Host smart-40cc2cf2-fa32-4bbd-a388-c3aea2d55cf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36148
9239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.361489239
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.3091433689
Short name T1447
Test name
Test status
Simulation time 351627987 ps
CPU time 1.12 seconds
Started Jul 24 05:29:03 PM PDT 24
Finished Jul 24 05:29:05 PM PDT 24
Peak memory 206596 kb
Host smart-7833d1b5-fe6b-4d97-9e75-51d05fa2591c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30914
33689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.3091433689
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.3393156904
Short name T2306
Test name
Test status
Simulation time 136445525 ps
CPU time 0.78 seconds
Started Jul 24 05:29:12 PM PDT 24
Finished Jul 24 05:29:13 PM PDT 24
Peak memory 206496 kb
Host smart-8f766afe-bd1e-4699-a8c7-e3301f687f54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33931
56904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.3393156904
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.3740630862
Short name T2220
Test name
Test status
Simulation time 63159621 ps
CPU time 0.66 seconds
Started Jul 24 05:29:16 PM PDT 24
Finished Jul 24 05:29:17 PM PDT 24
Peak memory 206516 kb
Host smart-9b8eacf7-53d9-46d3-aa2e-015d21511469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37406
30862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.3740630862
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.2147322328
Short name T1706
Test name
Test status
Simulation time 967261543 ps
CPU time 2.1 seconds
Started Jul 24 05:29:07 PM PDT 24
Finished Jul 24 05:29:09 PM PDT 24
Peak memory 206880 kb
Host smart-f1b2f3b4-e978-4dc5-8a26-ff3594053b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21473
22328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.2147322328
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.2063884961
Short name T1468
Test name
Test status
Simulation time 414210077 ps
CPU time 2.4 seconds
Started Jul 24 05:28:55 PM PDT 24
Finished Jul 24 05:28:57 PM PDT 24
Peak memory 206788 kb
Host smart-1600b10d-45f3-4f92-aef2-9df801796580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20638
84961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.2063884961
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.196240573
Short name T2166
Test name
Test status
Simulation time 188521503 ps
CPU time 0.83 seconds
Started Jul 24 05:29:04 PM PDT 24
Finished Jul 24 05:29:06 PM PDT 24
Peak memory 206544 kb
Host smart-d5a09303-cf1a-4fe5-ae57-6a539e7acdcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19624
0573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.196240573
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.2811227948
Short name T471
Test name
Test status
Simulation time 147104642 ps
CPU time 0.75 seconds
Started Jul 24 05:29:05 PM PDT 24
Finished Jul 24 05:29:06 PM PDT 24
Peak memory 206568 kb
Host smart-57139058-65a9-45be-bcda-158c22c9a613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28112
27948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.2811227948
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.3231975712
Short name T2460
Test name
Test status
Simulation time 204468974 ps
CPU time 0.87 seconds
Started Jul 24 05:29:04 PM PDT 24
Finished Jul 24 05:29:06 PM PDT 24
Peak memory 206504 kb
Host smart-7625c8fe-1cee-49a1-af9c-5ef565ce0de9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32319
75712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.3231975712
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.1876339000
Short name T2061
Test name
Test status
Simulation time 8597903178 ps
CPU time 63.63 seconds
Started Jul 24 05:29:00 PM PDT 24
Finished Jul 24 05:30:09 PM PDT 24
Peak memory 206960 kb
Host smart-df7266da-fb8d-4b90-b3ab-c6af2624527f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1876339000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.1876339000
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_iso_retraction.1853992629
Short name T2724
Test name
Test status
Simulation time 6148615585 ps
CPU time 18.45 seconds
Started Jul 24 05:29:00 PM PDT 24
Finished Jul 24 05:29:19 PM PDT 24
Peak memory 206912 kb
Host smart-be88d0f2-6879-498d-ba15-e9a4e7b1aac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18539
92629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.1853992629
Directory /workspace/40.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.3099404571
Short name T634
Test name
Test status
Simulation time 222729979 ps
CPU time 0.91 seconds
Started Jul 24 05:29:05 PM PDT 24
Finished Jul 24 05:29:06 PM PDT 24
Peak memory 206552 kb
Host smart-87da717d-6cd8-4bb4-a925-b276b384bda4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30994
04571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.3099404571
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.1149323974
Short name T2417
Test name
Test status
Simulation time 23358211544 ps
CPU time 25.9 seconds
Started Jul 24 05:28:59 PM PDT 24
Finished Jul 24 05:29:25 PM PDT 24
Peak memory 206708 kb
Host smart-6fbf1d00-27fd-4162-b074-074ff2b3785d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11493
23974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.1149323974
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.1889743225
Short name T1101
Test name
Test status
Simulation time 3324487930 ps
CPU time 3.92 seconds
Started Jul 24 05:28:58 PM PDT 24
Finished Jul 24 05:29:02 PM PDT 24
Peak memory 206704 kb
Host smart-7c2d619a-e656-46a7-89a6-a2ed804ce773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18897
43225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.1889743225
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.795014793
Short name T2629
Test name
Test status
Simulation time 12402004527 ps
CPU time 108.41 seconds
Started Jul 24 05:28:54 PM PDT 24
Finished Jul 24 05:30:43 PM PDT 24
Peak memory 206952 kb
Host smart-882d3398-e613-46cc-b07d-1c2a462333f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79501
4793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.795014793
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.3587159195
Short name T2281
Test name
Test status
Simulation time 3646847475 ps
CPU time 25.45 seconds
Started Jul 24 05:29:12 PM PDT 24
Finished Jul 24 05:29:38 PM PDT 24
Peak memory 206964 kb
Host smart-dde88d1e-e398-457a-b4fe-cb0cda813d16
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3587159195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.3587159195
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.3861029282
Short name T2116
Test name
Test status
Simulation time 242125448 ps
CPU time 0.89 seconds
Started Jul 24 05:29:07 PM PDT 24
Finished Jul 24 05:29:08 PM PDT 24
Peak memory 206592 kb
Host smart-20ad8d8e-cd3b-44e1-8e80-f71eb62ee441
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3861029282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.3861029282
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.2255861305
Short name T923
Test name
Test status
Simulation time 197369974 ps
CPU time 0.86 seconds
Started Jul 24 05:28:55 PM PDT 24
Finished Jul 24 05:28:56 PM PDT 24
Peak memory 206584 kb
Host smart-e0fda788-1525-4dea-880e-172387ce156d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22558
61305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.2255861305
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.930428222
Short name T651
Test name
Test status
Simulation time 3674328288 ps
CPU time 26.35 seconds
Started Jul 24 05:28:56 PM PDT 24
Finished Jul 24 05:29:23 PM PDT 24
Peak memory 206908 kb
Host smart-d1560564-081c-4136-9896-f032f88b71af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93042
8222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.930428222
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.694827836
Short name T916
Test name
Test status
Simulation time 6051096848 ps
CPU time 55.96 seconds
Started Jul 24 05:29:11 PM PDT 24
Finished Jul 24 05:30:08 PM PDT 24
Peak memory 206888 kb
Host smart-ce6cd6ae-ce43-4c8f-8bb2-691e80c80f3a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=694827836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.694827836
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.2999907522
Short name T2337
Test name
Test status
Simulation time 171227534 ps
CPU time 0.81 seconds
Started Jul 24 05:29:08 PM PDT 24
Finished Jul 24 05:29:09 PM PDT 24
Peak memory 206592 kb
Host smart-f050d78e-dd99-4440-8259-ecb87fa54f72
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2999907522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.2999907522
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.274943242
Short name T2251
Test name
Test status
Simulation time 176278819 ps
CPU time 0.8 seconds
Started Jul 24 05:29:03 PM PDT 24
Finished Jul 24 05:29:04 PM PDT 24
Peak memory 206604 kb
Host smart-38fe8710-7fa9-4e30-b9af-e179390f049c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27494
3242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.274943242
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.1900592780
Short name T2499
Test name
Test status
Simulation time 182015691 ps
CPU time 0.81 seconds
Started Jul 24 05:29:03 PM PDT 24
Finished Jul 24 05:29:05 PM PDT 24
Peak memory 206600 kb
Host smart-17061006-b7d1-4ca9-bb13-696f2c6e94cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19005
92780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.1900592780
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.164430059
Short name T2211
Test name
Test status
Simulation time 157085889 ps
CPU time 0.78 seconds
Started Jul 24 05:29:05 PM PDT 24
Finished Jul 24 05:29:06 PM PDT 24
Peak memory 206556 kb
Host smart-ca292ab8-4506-4092-a29d-002afd80c5e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16443
0059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.164430059
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.1581035028
Short name T970
Test name
Test status
Simulation time 184020857 ps
CPU time 0.78 seconds
Started Jul 24 05:29:08 PM PDT 24
Finished Jul 24 05:29:10 PM PDT 24
Peak memory 206556 kb
Host smart-fe51b6aa-487d-4921-93ea-683d683a8171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15810
35028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.1581035028
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.104857389
Short name T636
Test name
Test status
Simulation time 175903871 ps
CPU time 0.77 seconds
Started Jul 24 05:29:24 PM PDT 24
Finished Jul 24 05:29:25 PM PDT 24
Peak memory 206572 kb
Host smart-e333d37f-39e1-4281-bc3d-9233a0a3adbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10485
7389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.104857389
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.863835259
Short name T517
Test name
Test status
Simulation time 148098904 ps
CPU time 0.77 seconds
Started Jul 24 05:29:09 PM PDT 24
Finished Jul 24 05:29:10 PM PDT 24
Peak memory 206580 kb
Host smart-7d6135f0-ca4c-422f-8393-d6d7a75eb7d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86383
5259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.863835259
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.4180209661
Short name T789
Test name
Test status
Simulation time 224141145 ps
CPU time 0.9 seconds
Started Jul 24 05:29:04 PM PDT 24
Finished Jul 24 05:29:05 PM PDT 24
Peak memory 206604 kb
Host smart-e6e7dab9-1b0f-4326-847b-6030751097c5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4180209661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.4180209661
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.2559383029
Short name T384
Test name
Test status
Simulation time 140152922 ps
CPU time 0.74 seconds
Started Jul 24 05:29:12 PM PDT 24
Finished Jul 24 05:29:13 PM PDT 24
Peak memory 206584 kb
Host smart-c5406e4c-683b-4035-a7e9-86ba111bf928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25593
83029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.2559383029
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.1146347635
Short name T496
Test name
Test status
Simulation time 39056690 ps
CPU time 0.65 seconds
Started Jul 24 05:29:02 PM PDT 24
Finished Jul 24 05:29:03 PM PDT 24
Peak memory 206648 kb
Host smart-be09a413-f4c6-49d9-989c-c24a68cc3eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11463
47635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.1146347635
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.2207913507
Short name T1937
Test name
Test status
Simulation time 22598986064 ps
CPU time 49.18 seconds
Started Jul 24 05:29:04 PM PDT 24
Finished Jul 24 05:29:54 PM PDT 24
Peak memory 215180 kb
Host smart-934699d0-efa8-4921-82df-fceca82bd181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22079
13507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.2207913507
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.1522227828
Short name T1705
Test name
Test status
Simulation time 199502038 ps
CPU time 0.88 seconds
Started Jul 24 05:29:03 PM PDT 24
Finished Jul 24 05:29:04 PM PDT 24
Peak memory 206528 kb
Host smart-e9a8a699-9b27-431e-b82c-69fe7e74028a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15222
27828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.1522227828
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.774531915
Short name T682
Test name
Test status
Simulation time 211226951 ps
CPU time 0.87 seconds
Started Jul 24 05:28:52 PM PDT 24
Finished Jul 24 05:28:53 PM PDT 24
Peak memory 206632 kb
Host smart-62a6eed1-bca4-4aca-be70-caa7d0558e2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77453
1915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.774531915
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.1520180188
Short name T2184
Test name
Test status
Simulation time 201117556 ps
CPU time 0.85 seconds
Started Jul 24 05:29:02 PM PDT 24
Finished Jul 24 05:29:04 PM PDT 24
Peak memory 206560 kb
Host smart-5b087c7b-cd24-4355-889c-c874a1f17229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15201
80188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.1520180188
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.1151654354
Short name T1964
Test name
Test status
Simulation time 173547684 ps
CPU time 0.78 seconds
Started Jul 24 05:29:16 PM PDT 24
Finished Jul 24 05:29:17 PM PDT 24
Peak memory 206572 kb
Host smart-5d8016ab-12d8-4a36-bfb6-48c7ad917527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11516
54354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.1151654354
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.186687809
Short name T2713
Test name
Test status
Simulation time 176026404 ps
CPU time 0.85 seconds
Started Jul 24 05:28:53 PM PDT 24
Finished Jul 24 05:28:54 PM PDT 24
Peak memory 206556 kb
Host smart-02f205ce-2cc8-469e-8f39-94def42e4619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18668
7809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.186687809
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.182860753
Short name T475
Test name
Test status
Simulation time 160825191 ps
CPU time 0.75 seconds
Started Jul 24 05:29:04 PM PDT 24
Finished Jul 24 05:29:06 PM PDT 24
Peak memory 206580 kb
Host smart-813382d2-db9c-43d2-b792-8fc4d413506d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18286
0753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.182860753
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.586914666
Short name T1677
Test name
Test status
Simulation time 154239956 ps
CPU time 0.87 seconds
Started Jul 24 05:29:05 PM PDT 24
Finished Jul 24 05:29:06 PM PDT 24
Peak memory 206568 kb
Host smart-031fce4b-378b-47e7-9f02-4f6a7d9705f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58691
4666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.586914666
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.1085550876
Short name T1264
Test name
Test status
Simulation time 241833578 ps
CPU time 0.96 seconds
Started Jul 24 05:29:02 PM PDT 24
Finished Jul 24 05:29:04 PM PDT 24
Peak memory 206388 kb
Host smart-997561c9-8746-4027-99dc-0e1023e30945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10855
50876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.1085550876
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.1884374135
Short name T1166
Test name
Test status
Simulation time 4725650491 ps
CPU time 127.33 seconds
Started Jul 24 05:29:13 PM PDT 24
Finished Jul 24 05:31:20 PM PDT 24
Peak memory 206924 kb
Host smart-542b32b9-1bcf-47bc-9e1a-e7b1858e6941
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1884374135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.1884374135
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.1299308895
Short name T1494
Test name
Test status
Simulation time 186096916 ps
CPU time 0.85 seconds
Started Jul 24 05:29:23 PM PDT 24
Finished Jul 24 05:29:24 PM PDT 24
Peak memory 206596 kb
Host smart-c181716d-77ce-4f15-a391-4e494d98aa69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12993
08895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.1299308895
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.3753165877
Short name T1802
Test name
Test status
Simulation time 239916636 ps
CPU time 0.88 seconds
Started Jul 24 05:29:03 PM PDT 24
Finished Jul 24 05:29:05 PM PDT 24
Peak memory 206576 kb
Host smart-283abeb4-0a29-45a1-a4a8-2ed64e2c24bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37531
65877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.3753165877
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.985844797
Short name T2592
Test name
Test status
Simulation time 1406611512 ps
CPU time 2.77 seconds
Started Jul 24 05:29:00 PM PDT 24
Finished Jul 24 05:29:03 PM PDT 24
Peak memory 206828 kb
Host smart-394ab578-93a5-4882-8786-d62e973a6c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98584
4797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.985844797
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.3777268695
Short name T652
Test name
Test status
Simulation time 4143360641 ps
CPU time 38.69 seconds
Started Jul 24 05:29:00 PM PDT 24
Finished Jul 24 05:29:39 PM PDT 24
Peak memory 206880 kb
Host smart-2f2f4601-f113-4797-8d0e-63115013179a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37772
68695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.3777268695
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.1881750316
Short name T2685
Test name
Test status
Simulation time 61733774 ps
CPU time 0.68 seconds
Started Jul 24 05:29:29 PM PDT 24
Finished Jul 24 05:29:30 PM PDT 24
Peak memory 206512 kb
Host smart-feab3522-4e40-4e62-95b5-dfa42975e76c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1881750316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.1881750316
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.4134358709
Short name T2623
Test name
Test status
Simulation time 3642412714 ps
CPU time 4.31 seconds
Started Jul 24 05:29:13 PM PDT 24
Finished Jul 24 05:29:18 PM PDT 24
Peak memory 206608 kb
Host smart-761e8726-f057-40fd-a724-d0161c6adfbc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4134358709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.4134358709
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.2036902725
Short name T1921
Test name
Test status
Simulation time 13323906833 ps
CPU time 14.1 seconds
Started Jul 24 05:29:13 PM PDT 24
Finished Jul 24 05:29:28 PM PDT 24
Peak memory 206716 kb
Host smart-dadc62f6-c731-42d3-ae78-35bfa438a15e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2036902725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.2036902725
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.1907515972
Short name T1068
Test name
Test status
Simulation time 23353904144 ps
CPU time 22.2 seconds
Started Jul 24 05:29:03 PM PDT 24
Finished Jul 24 05:29:25 PM PDT 24
Peak memory 206928 kb
Host smart-46205f4d-ced9-470b-88c4-d0d5eead781d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1907515972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.1907515972
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.652939837
Short name T296
Test name
Test status
Simulation time 191910965 ps
CPU time 0.86 seconds
Started Jul 24 05:29:05 PM PDT 24
Finished Jul 24 05:29:07 PM PDT 24
Peak memory 206544 kb
Host smart-46c4da62-896c-4d92-9510-1d1adc0cfc19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65293
9837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.652939837
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.3501121823
Short name T713
Test name
Test status
Simulation time 187632091 ps
CPU time 0.85 seconds
Started Jul 24 05:29:15 PM PDT 24
Finished Jul 24 05:29:16 PM PDT 24
Peak memory 206564 kb
Host smart-2ff19544-6134-47ed-b399-a76617287368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35011
21823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.3501121823
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.1944386758
Short name T820
Test name
Test status
Simulation time 218866656 ps
CPU time 0.97 seconds
Started Jul 24 05:29:10 PM PDT 24
Finished Jul 24 05:29:11 PM PDT 24
Peak memory 206564 kb
Host smart-b0f390f0-9a8d-413b-8d5d-62fd3c6d9c66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19443
86758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.1944386758
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.437615816
Short name T656
Test name
Test status
Simulation time 1321760807 ps
CPU time 2.83 seconds
Started Jul 24 05:28:59 PM PDT 24
Finished Jul 24 05:29:02 PM PDT 24
Peak memory 206764 kb
Host smart-3dcb7049-f0c0-403e-989b-09ac6d806eed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43761
5816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.437615816
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.3091639669
Short name T1585
Test name
Test status
Simulation time 16257609976 ps
CPU time 30.64 seconds
Started Jul 24 05:29:12 PM PDT 24
Finished Jul 24 05:29:43 PM PDT 24
Peak memory 206924 kb
Host smart-e2d9630f-f55d-40c3-a238-9c77a664ed6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30916
39669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.3091639669
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.506074360
Short name T1929
Test name
Test status
Simulation time 406920529 ps
CPU time 1.25 seconds
Started Jul 24 05:29:06 PM PDT 24
Finished Jul 24 05:29:07 PM PDT 24
Peak memory 206576 kb
Host smart-3972d1dc-cbc0-46a8-b613-6733b202a72a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50607
4360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.506074360
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.2988597881
Short name T950
Test name
Test status
Simulation time 176554038 ps
CPU time 0.79 seconds
Started Jul 24 05:29:01 PM PDT 24
Finished Jul 24 05:29:02 PM PDT 24
Peak memory 206568 kb
Host smart-af9a4dbd-d844-4d5f-8dc7-f0b00bf42fde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29885
97881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.2988597881
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.713835060
Short name T844
Test name
Test status
Simulation time 33951224 ps
CPU time 0.67 seconds
Started Jul 24 05:29:04 PM PDT 24
Finished Jul 24 05:29:06 PM PDT 24
Peak memory 206540 kb
Host smart-874b4889-dc6e-45e6-b530-ceb3533b6d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71383
5060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.713835060
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.883963570
Short name T2596
Test name
Test status
Simulation time 1003658898 ps
CPU time 2.43 seconds
Started Jul 24 05:29:03 PM PDT 24
Finished Jul 24 05:29:06 PM PDT 24
Peak memory 206892 kb
Host smart-333d59c2-0c90-4459-a0ce-85c424dafd19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88396
3570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.883963570
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.350805665
Short name T499
Test name
Test status
Simulation time 247518360 ps
CPU time 1.85 seconds
Started Jul 24 05:28:54 PM PDT 24
Finished Jul 24 05:28:56 PM PDT 24
Peak memory 206736 kb
Host smart-5a0f0925-a5ec-4c9d-b5c0-d9664ebe5c41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35080
5665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.350805665
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.4281778653
Short name T2030
Test name
Test status
Simulation time 182288633 ps
CPU time 0.84 seconds
Started Jul 24 05:29:02 PM PDT 24
Finished Jul 24 05:29:03 PM PDT 24
Peak memory 206576 kb
Host smart-5e7dfd9e-f701-43da-bd3b-c862d75452c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42817
78653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.4281778653
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.1493269104
Short name T1095
Test name
Test status
Simulation time 169478776 ps
CPU time 0.81 seconds
Started Jul 24 05:29:11 PM PDT 24
Finished Jul 24 05:29:12 PM PDT 24
Peak memory 206592 kb
Host smart-d5864683-24f3-4074-abf9-9da2f99ce49d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14932
69104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.1493269104
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.501003719
Short name T701
Test name
Test status
Simulation time 218161608 ps
CPU time 0.9 seconds
Started Jul 24 05:29:11 PM PDT 24
Finished Jul 24 05:29:12 PM PDT 24
Peak memory 206532 kb
Host smart-df935a23-cf9a-49f1-ac0f-ecd15d92591a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50100
3719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.501003719
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_invalid_sync.594703827
Short name T2539
Test name
Test status
Simulation time 8163912591 ps
CPU time 223.95 seconds
Started Jul 24 05:29:07 PM PDT 24
Finished Jul 24 05:32:52 PM PDT 24
Peak memory 206896 kb
Host smart-7948d9c1-56d9-44b5-9b63-5c07fc7ee988
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=594703827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.594703827
Directory /workspace/41.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/41.usbdev_iso_retraction.3170617762
Short name T1999
Test name
Test status
Simulation time 6126215157 ps
CPU time 22.55 seconds
Started Jul 24 05:29:08 PM PDT 24
Finished Jul 24 05:29:31 PM PDT 24
Peak memory 206912 kb
Host smart-6fdd2efe-1f26-4abd-bef6-fdd934ca9380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31706
17762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.3170617762
Directory /workspace/41.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.2521306007
Short name T445
Test name
Test status
Simulation time 231698266 ps
CPU time 0.87 seconds
Started Jul 24 05:29:12 PM PDT 24
Finished Jul 24 05:29:13 PM PDT 24
Peak memory 206520 kb
Host smart-b1dbbec2-41a7-4f6e-9bb4-791168e92193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25213
06007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.2521306007
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.3209857948
Short name T315
Test name
Test status
Simulation time 23350578382 ps
CPU time 23.91 seconds
Started Jul 24 05:29:06 PM PDT 24
Finished Jul 24 05:29:30 PM PDT 24
Peak memory 206552 kb
Host smart-b2ca9034-6629-4cc0-8365-d02bb8057647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32098
57948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.3209857948
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.257973091
Short name T1375
Test name
Test status
Simulation time 3282580418 ps
CPU time 3.93 seconds
Started Jul 24 05:29:30 PM PDT 24
Finished Jul 24 05:29:34 PM PDT 24
Peak memory 206648 kb
Host smart-352617cf-4a5c-447a-ad05-18b28e05af90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25797
3091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.257973091
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.908231692
Short name T143
Test name
Test status
Simulation time 8504320353 ps
CPU time 226.99 seconds
Started Jul 24 05:29:17 PM PDT 24
Finished Jul 24 05:33:04 PM PDT 24
Peak memory 206980 kb
Host smart-585a0117-7e18-4ad9-86b4-4cdf947fee28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90823
1692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.908231692
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.1160086734
Short name T1262
Test name
Test status
Simulation time 3523951377 ps
CPU time 23.95 seconds
Started Jul 24 05:29:05 PM PDT 24
Finished Jul 24 05:29:29 PM PDT 24
Peak memory 206956 kb
Host smart-f67c82e6-84ab-4e67-8e04-a447a000d0c1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1160086734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.1160086734
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.3638539372
Short name T1931
Test name
Test status
Simulation time 267130536 ps
CPU time 0.91 seconds
Started Jul 24 05:29:03 PM PDT 24
Finished Jul 24 05:29:04 PM PDT 24
Peak memory 206528 kb
Host smart-d3ef5c89-5653-42e4-8c43-3308e2a8f37d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3638539372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.3638539372
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.54106591
Short name T587
Test name
Test status
Simulation time 202266050 ps
CPU time 0.84 seconds
Started Jul 24 05:29:07 PM PDT 24
Finished Jul 24 05:29:08 PM PDT 24
Peak memory 206600 kb
Host smart-ad016b9a-08ac-4d93-84ff-c5853add3707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54106
591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.54106591
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.1542140903
Short name T1427
Test name
Test status
Simulation time 4075684666 ps
CPU time 118.77 seconds
Started Jul 24 05:29:02 PM PDT 24
Finished Jul 24 05:31:01 PM PDT 24
Peak memory 206820 kb
Host smart-50808163-058c-4278-aa4d-6285cf088dc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15421
40903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.1542140903
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.436437100
Short name T2403
Test name
Test status
Simulation time 4078349102 ps
CPU time 39.52 seconds
Started Jul 24 05:29:18 PM PDT 24
Finished Jul 24 05:29:58 PM PDT 24
Peak memory 206916 kb
Host smart-774b92c2-a02f-4a6b-ba81-f5b74f725291
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=436437100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.436437100
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.1907423705
Short name T788
Test name
Test status
Simulation time 148876288 ps
CPU time 0.85 seconds
Started Jul 24 05:29:10 PM PDT 24
Finished Jul 24 05:29:12 PM PDT 24
Peak memory 206600 kb
Host smart-794fbac8-a4e7-4b78-9faf-371603e7983f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1907423705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.1907423705
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.2694730935
Short name T297
Test name
Test status
Simulation time 161623024 ps
CPU time 0.78 seconds
Started Jul 24 05:29:02 PM PDT 24
Finished Jul 24 05:29:04 PM PDT 24
Peak memory 206616 kb
Host smart-898ab5ec-cf5f-405f-88ee-fa959f4e3414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26947
30935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.2694730935
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.2795284410
Short name T113
Test name
Test status
Simulation time 244165963 ps
CPU time 0.9 seconds
Started Jul 24 05:28:59 PM PDT 24
Finished Jul 24 05:29:00 PM PDT 24
Peak memory 206596 kb
Host smart-d09f8b63-f53e-4996-aee7-d0c62e80c93a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27952
84410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.2795284410
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.1522828349
Short name T2295
Test name
Test status
Simulation time 179539002 ps
CPU time 0.81 seconds
Started Jul 24 05:29:01 PM PDT 24
Finished Jul 24 05:29:02 PM PDT 24
Peak memory 206580 kb
Host smart-236dc67b-819d-4a33-a809-e9fcd68902e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15228
28349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.1522828349
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.2820031023
Short name T822
Test name
Test status
Simulation time 196409389 ps
CPU time 0.86 seconds
Started Jul 24 05:29:14 PM PDT 24
Finished Jul 24 05:29:15 PM PDT 24
Peak memory 206564 kb
Host smart-976440d7-68a4-44f4-ae23-0cc96bbbad53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28200
31023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.2820031023
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.2234039893
Short name T908
Test name
Test status
Simulation time 147838743 ps
CPU time 0.72 seconds
Started Jul 24 05:29:15 PM PDT 24
Finished Jul 24 05:29:16 PM PDT 24
Peak memory 206552 kb
Host smart-fd8aebac-d931-49e3-b8a5-5d648834c665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22340
39893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.2234039893
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.2076744355
Short name T161
Test name
Test status
Simulation time 147305137 ps
CPU time 0.79 seconds
Started Jul 24 05:29:06 PM PDT 24
Finished Jul 24 05:29:07 PM PDT 24
Peak memory 206536 kb
Host smart-3d6d71c4-2275-4b27-9b2b-a30a90428757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20767
44355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.2076744355
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.3723899698
Short name T1889
Test name
Test status
Simulation time 200631312 ps
CPU time 0.89 seconds
Started Jul 24 05:29:11 PM PDT 24
Finished Jul 24 05:29:18 PM PDT 24
Peak memory 206544 kb
Host smart-8f7688b7-03e9-4dc6-a859-c5f022f24fba
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3723899698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.3723899698
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.4013119497
Short name T2404
Test name
Test status
Simulation time 145775368 ps
CPU time 0.77 seconds
Started Jul 24 05:29:08 PM PDT 24
Finished Jul 24 05:29:10 PM PDT 24
Peak memory 206568 kb
Host smart-921b8707-a597-4985-9c06-dc88f0112b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40131
19497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.4013119497
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.2290562725
Short name T23
Test name
Test status
Simulation time 37102924 ps
CPU time 0.63 seconds
Started Jul 24 05:29:23 PM PDT 24
Finished Jul 24 05:29:23 PM PDT 24
Peak memory 206592 kb
Host smart-640f572f-7c94-4ecc-808e-67cf02c196ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22905
62725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.2290562725
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.2774226801
Short name T920
Test name
Test status
Simulation time 11379982084 ps
CPU time 23.8 seconds
Started Jul 24 05:29:08 PM PDT 24
Finished Jul 24 05:29:33 PM PDT 24
Peak memory 215196 kb
Host smart-24975b0e-4c86-4931-b5bc-eb1793928b60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27742
26801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.2774226801
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.3254256918
Short name T1330
Test name
Test status
Simulation time 168575898 ps
CPU time 0.81 seconds
Started Jul 24 05:29:19 PM PDT 24
Finished Jul 24 05:29:20 PM PDT 24
Peak memory 206556 kb
Host smart-114483d9-b2cc-4114-bb70-57f31f2629aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32542
56918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.3254256918
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.3078996318
Short name T1637
Test name
Test status
Simulation time 223540372 ps
CPU time 0.9 seconds
Started Jul 24 05:29:12 PM PDT 24
Finished Jul 24 05:29:13 PM PDT 24
Peak memory 206508 kb
Host smart-709f13e1-19d1-48f6-8abb-376559765379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30789
96318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.3078996318
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.1213340335
Short name T538
Test name
Test status
Simulation time 189999712 ps
CPU time 0.84 seconds
Started Jul 24 05:29:05 PM PDT 24
Finished Jul 24 05:29:07 PM PDT 24
Peak memory 206600 kb
Host smart-bbd6fc63-61e6-4963-85f7-6970f2b2c860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12133
40335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.1213340335
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.3820925317
Short name T2513
Test name
Test status
Simulation time 156052312 ps
CPU time 0.81 seconds
Started Jul 24 05:29:23 PM PDT 24
Finished Jul 24 05:29:24 PM PDT 24
Peak memory 206600 kb
Host smart-7cf39064-b88c-4747-8439-c6a6a366fef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38209
25317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.3820925317
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.740463296
Short name T586
Test name
Test status
Simulation time 142541882 ps
CPU time 0.79 seconds
Started Jul 24 05:29:11 PM PDT 24
Finished Jul 24 05:29:13 PM PDT 24
Peak memory 206588 kb
Host smart-cd60d421-5112-4ed4-be9a-4d355afbb662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74046
3296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.740463296
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.2312642991
Short name T1759
Test name
Test status
Simulation time 157754807 ps
CPU time 0.77 seconds
Started Jul 24 05:29:01 PM PDT 24
Finished Jul 24 05:29:02 PM PDT 24
Peak memory 206472 kb
Host smart-9f097c5f-f684-4ff7-906c-64c95b032f3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23126
42991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.2312642991
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.1569486669
Short name T1466
Test name
Test status
Simulation time 159358073 ps
CPU time 0.77 seconds
Started Jul 24 05:29:18 PM PDT 24
Finished Jul 24 05:29:19 PM PDT 24
Peak memory 206492 kb
Host smart-60887ddf-937c-4c8c-846d-3c4ad307470b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15694
86669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.1569486669
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.4138705307
Short name T2389
Test name
Test status
Simulation time 221498637 ps
CPU time 0.97 seconds
Started Jul 24 05:29:13 PM PDT 24
Finished Jul 24 05:29:14 PM PDT 24
Peak memory 206528 kb
Host smart-77ea0fc6-228f-4581-b660-1fbda3b1ce16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41387
05307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.4138705307
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.2975540177
Short name T2294
Test name
Test status
Simulation time 5337743006 ps
CPU time 48.86 seconds
Started Jul 24 05:29:24 PM PDT 24
Finished Jul 24 05:30:13 PM PDT 24
Peak memory 206896 kb
Host smart-18f1d734-1e4e-4071-8a3e-32789a404d35
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2975540177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.2975540177
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.1943346713
Short name T344
Test name
Test status
Simulation time 177399458 ps
CPU time 0.89 seconds
Started Jul 24 05:29:17 PM PDT 24
Finished Jul 24 05:29:19 PM PDT 24
Peak memory 206580 kb
Host smart-f1ba5b6f-a37f-4b24-9407-d9da42be8c4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19433
46713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.1943346713
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.777246500
Short name T722
Test name
Test status
Simulation time 158235439 ps
CPU time 0.75 seconds
Started Jul 24 05:29:10 PM PDT 24
Finished Jul 24 05:29:10 PM PDT 24
Peak memory 206580 kb
Host smart-eb8779fc-ff4d-4194-b163-5ac055228b25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77724
6500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.777246500
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.598316219
Short name T2332
Test name
Test status
Simulation time 1069289607 ps
CPU time 2.46 seconds
Started Jul 24 05:29:11 PM PDT 24
Finished Jul 24 05:29:13 PM PDT 24
Peak memory 206788 kb
Host smart-98986307-b1e7-46c9-b9b8-0b7edd2e4b08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59831
6219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.598316219
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.2655224936
Short name T1820
Test name
Test status
Simulation time 3036990666 ps
CPU time 27.94 seconds
Started Jul 24 05:29:12 PM PDT 24
Finished Jul 24 05:29:40 PM PDT 24
Peak memory 206912 kb
Host smart-0be861aa-c67b-49f1-bd74-c9aba4f729f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26552
24936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.2655224936
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.2248678048
Short name T2740
Test name
Test status
Simulation time 73921250 ps
CPU time 0.7 seconds
Started Jul 24 05:29:16 PM PDT 24
Finished Jul 24 05:29:17 PM PDT 24
Peak memory 206616 kb
Host smart-f7a3f895-7da1-4349-9246-b8f8590a9fbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2248678048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.2248678048
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.1149964610
Short name T843
Test name
Test status
Simulation time 3886257141 ps
CPU time 4.45 seconds
Started Jul 24 05:29:20 PM PDT 24
Finished Jul 24 05:29:25 PM PDT 24
Peak memory 206608 kb
Host smart-f5514016-12c5-4172-b28f-0de9b6453e88
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1149964610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.1149964610
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.3914652527
Short name T1092
Test name
Test status
Simulation time 13315620896 ps
CPU time 14.74 seconds
Started Jul 24 05:29:05 PM PDT 24
Finished Jul 24 05:29:20 PM PDT 24
Peak memory 206768 kb
Host smart-6408c4bc-e228-4979-bfd8-a466975315ee
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3914652527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.3914652527
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.3240743550
Short name T1565
Test name
Test status
Simulation time 23335797006 ps
CPU time 23.37 seconds
Started Jul 24 05:29:10 PM PDT 24
Finished Jul 24 05:29:34 PM PDT 24
Peak memory 206636 kb
Host smart-f34eee67-14b6-41d9-8c6a-aacb902f9ff2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3240743550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.3240743550
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.1438894651
Short name T2049
Test name
Test status
Simulation time 232379541 ps
CPU time 0.86 seconds
Started Jul 24 05:29:19 PM PDT 24
Finished Jul 24 05:29:20 PM PDT 24
Peak memory 206608 kb
Host smart-1d799e63-0127-430f-997d-6d43a4e7443d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14388
94651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.1438894651
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.586654673
Short name T2105
Test name
Test status
Simulation time 171703100 ps
CPU time 0.76 seconds
Started Jul 24 05:29:20 PM PDT 24
Finished Jul 24 05:29:21 PM PDT 24
Peak memory 206492 kb
Host smart-4fce0eeb-89ba-4a61-98ed-5e4a8b32fd54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58665
4673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.586654673
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.3573883121
Short name T1950
Test name
Test status
Simulation time 388870747 ps
CPU time 1.23 seconds
Started Jul 24 05:29:09 PM PDT 24
Finished Jul 24 05:29:10 PM PDT 24
Peak memory 206544 kb
Host smart-f8254547-1024-4577-b8b8-9d187a051b5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35738
83121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.3573883121
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.2979218526
Short name T731
Test name
Test status
Simulation time 1054292884 ps
CPU time 2.31 seconds
Started Jul 24 05:29:14 PM PDT 24
Finished Jul 24 05:29:17 PM PDT 24
Peak memory 206848 kb
Host smart-b6592a40-6ee8-4156-b6c9-ea6c29faa6cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29792
18526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.2979218526
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.1158158228
Short name T2321
Test name
Test status
Simulation time 8143545926 ps
CPU time 14.7 seconds
Started Jul 24 05:29:16 PM PDT 24
Finished Jul 24 05:29:31 PM PDT 24
Peak memory 206872 kb
Host smart-6cc27552-acb8-4d17-addd-509a17b5cf0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11581
58228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.1158158228
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.75904487
Short name T1771
Test name
Test status
Simulation time 505246158 ps
CPU time 1.44 seconds
Started Jul 24 05:29:17 PM PDT 24
Finished Jul 24 05:29:19 PM PDT 24
Peak memory 206620 kb
Host smart-7677bffe-1230-4247-b46a-e082b9127c60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75904
487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.75904487
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.2174650135
Short name T2426
Test name
Test status
Simulation time 162694775 ps
CPU time 0.78 seconds
Started Jul 24 05:29:02 PM PDT 24
Finished Jul 24 05:29:04 PM PDT 24
Peak memory 206604 kb
Host smart-481ba27d-807c-4411-b44a-76b1a54ae0b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21746
50135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.2174650135
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.3624057925
Short name T2164
Test name
Test status
Simulation time 47539888 ps
CPU time 0.66 seconds
Started Jul 24 05:29:03 PM PDT 24
Finished Jul 24 05:29:05 PM PDT 24
Peak memory 206608 kb
Host smart-58e02f0a-f7a5-4633-a9d8-e2e8814df269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36240
57925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.3624057925
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.2419775920
Short name T2691
Test name
Test status
Simulation time 978427664 ps
CPU time 2.04 seconds
Started Jul 24 05:29:18 PM PDT 24
Finished Jul 24 05:29:20 PM PDT 24
Peak memory 206856 kb
Host smart-f6a9df1b-5dcf-4d6f-9990-ce4af7f0f38e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24197
75920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.2419775920
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.1730104088
Short name T692
Test name
Test status
Simulation time 182392124 ps
CPU time 1.96 seconds
Started Jul 24 05:28:59 PM PDT 24
Finished Jul 24 05:29:01 PM PDT 24
Peak memory 206788 kb
Host smart-7a64e1d2-bf42-454a-bda0-be19e4e7a0d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17301
04088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.1730104088
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.1865083890
Short name T1560
Test name
Test status
Simulation time 193873843 ps
CPU time 0.84 seconds
Started Jul 24 05:29:04 PM PDT 24
Finished Jul 24 05:29:05 PM PDT 24
Peak memory 206568 kb
Host smart-0b304425-615e-4f66-8527-42dd2b71af81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18650
83890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.1865083890
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.1564373073
Short name T2482
Test name
Test status
Simulation time 193883886 ps
CPU time 0.84 seconds
Started Jul 24 05:29:10 PM PDT 24
Finished Jul 24 05:29:12 PM PDT 24
Peak memory 206644 kb
Host smart-7101975f-4090-4451-a93b-07f5165498d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15643
73073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.1564373073
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.2747917228
Short name T1785
Test name
Test status
Simulation time 271524787 ps
CPU time 0.88 seconds
Started Jul 24 05:29:04 PM PDT 24
Finished Jul 24 05:29:05 PM PDT 24
Peak memory 206388 kb
Host smart-32b89f2a-d5fd-4af4-9670-2c4cb4ca15e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27479
17228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.2747917228
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_iso_retraction.2038616230
Short name T850
Test name
Test status
Simulation time 9171026632 ps
CPU time 77.13 seconds
Started Jul 24 05:29:17 PM PDT 24
Finished Jul 24 05:30:35 PM PDT 24
Peak memory 206888 kb
Host smart-ac8706f8-b83c-4715-98cf-097d86611fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20386
16230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_iso_retraction.2038616230
Directory /workspace/42.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.3527913687
Short name T375
Test name
Test status
Simulation time 278843673 ps
CPU time 0.9 seconds
Started Jul 24 05:29:08 PM PDT 24
Finished Jul 24 05:29:09 PM PDT 24
Peak memory 206592 kb
Host smart-b8b9336b-dea7-4b08-a26b-f9e65739cdcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35279
13687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.3527913687
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.2154383555
Short name T868
Test name
Test status
Simulation time 23303853963 ps
CPU time 22.72 seconds
Started Jul 24 05:29:14 PM PDT 24
Finished Jul 24 05:29:37 PM PDT 24
Peak memory 206720 kb
Host smart-89291b7d-9b31-42b0-a54b-2568fb5f8876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21543
83555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.2154383555
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.2354777999
Short name T560
Test name
Test status
Simulation time 3331280073 ps
CPU time 3.84 seconds
Started Jul 24 05:29:18 PM PDT 24
Finished Jul 24 05:29:22 PM PDT 24
Peak memory 206700 kb
Host smart-8376325f-750f-4335-b5c7-08fcf7d8f9f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23547
77999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.2354777999
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.3144932556
Short name T1605
Test name
Test status
Simulation time 8880302575 ps
CPU time 79.91 seconds
Started Jul 24 05:29:10 PM PDT 24
Finished Jul 24 05:30:31 PM PDT 24
Peak memory 206884 kb
Host smart-310619d4-7ff8-434a-9293-8e08ee6210ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31449
32556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.3144932556
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.1814350607
Short name T2504
Test name
Test status
Simulation time 5509764401 ps
CPU time 156.76 seconds
Started Jul 24 05:29:18 PM PDT 24
Finished Jul 24 05:31:55 PM PDT 24
Peak memory 206892 kb
Host smart-5f49c44b-c313-4d01-ba9b-c5f49967b37b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1814350607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.1814350607
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.1703869678
Short name T1712
Test name
Test status
Simulation time 264255058 ps
CPU time 0.99 seconds
Started Jul 24 05:29:30 PM PDT 24
Finished Jul 24 05:29:31 PM PDT 24
Peak memory 206520 kb
Host smart-25c89f1d-43e4-48b5-8d9b-5f062454b8c3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1703869678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.1703869678
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.3029939665
Short name T780
Test name
Test status
Simulation time 183562643 ps
CPU time 0.83 seconds
Started Jul 24 05:29:17 PM PDT 24
Finished Jul 24 05:29:18 PM PDT 24
Peak memory 206580 kb
Host smart-cbfe34e8-9f71-46d7-a999-f589df925d37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30299
39665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.3029939665
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.710398946
Short name T2362
Test name
Test status
Simulation time 5719378402 ps
CPU time 156.81 seconds
Started Jul 24 05:29:12 PM PDT 24
Finished Jul 24 05:31:49 PM PDT 24
Peak memory 206884 kb
Host smart-2fb1eeae-763f-488c-aca0-12dce201a4f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71039
8946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.710398946
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.3023838752
Short name T1104
Test name
Test status
Simulation time 4193732785 ps
CPU time 38.54 seconds
Started Jul 24 05:29:03 PM PDT 24
Finished Jul 24 05:29:48 PM PDT 24
Peak memory 206920 kb
Host smart-d6fce5ea-f439-42d7-8c9e-ade64e704ffc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3023838752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.3023838752
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.915557977
Short name T934
Test name
Test status
Simulation time 143126881 ps
CPU time 0.77 seconds
Started Jul 24 05:29:17 PM PDT 24
Finished Jul 24 05:29:18 PM PDT 24
Peak memory 206612 kb
Host smart-396db9a0-30c7-4020-93ec-000d46887ac9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=915557977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.915557977
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.1138111066
Short name T2464
Test name
Test status
Simulation time 211102543 ps
CPU time 0.81 seconds
Started Jul 24 05:29:22 PM PDT 24
Finished Jul 24 05:29:22 PM PDT 24
Peak memory 206572 kb
Host smart-50ef9b21-1cea-40db-912f-f9e7c958db13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11381
11066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.1138111066
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.3068027307
Short name T2058
Test name
Test status
Simulation time 206727050 ps
CPU time 0.81 seconds
Started Jul 24 05:29:20 PM PDT 24
Finished Jul 24 05:29:21 PM PDT 24
Peak memory 206612 kb
Host smart-9f1bdb83-30a0-405d-a797-b0d3a2a7b279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30680
27307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.3068027307
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.1627458631
Short name T862
Test name
Test status
Simulation time 151687203 ps
CPU time 0.76 seconds
Started Jul 24 05:29:29 PM PDT 24
Finished Jul 24 05:29:30 PM PDT 24
Peak memory 206596 kb
Host smart-0001d6fa-b247-4eb2-a546-13d3c54b368f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16274
58631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.1627458631
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.4146564542
Short name T1349
Test name
Test status
Simulation time 202076135 ps
CPU time 0.84 seconds
Started Jul 24 05:29:16 PM PDT 24
Finished Jul 24 05:29:16 PM PDT 24
Peak memory 206612 kb
Host smart-988aa83f-6eff-4247-9e79-8c12af5d6bc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41465
64542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.4146564542
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.3947657810
Short name T892
Test name
Test status
Simulation time 157374904 ps
CPU time 0.79 seconds
Started Jul 24 05:29:33 PM PDT 24
Finished Jul 24 05:29:34 PM PDT 24
Peak memory 206384 kb
Host smart-bd7398d1-06cd-409c-99f5-787d1ec73d94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39476
57810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.3947657810
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.1723546853
Short name T1471
Test name
Test status
Simulation time 154091346 ps
CPU time 0.76 seconds
Started Jul 24 05:29:21 PM PDT 24
Finished Jul 24 05:29:22 PM PDT 24
Peak memory 206632 kb
Host smart-013f9d29-1eb7-4789-8fdc-c3105fde189c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17235
46853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.1723546853
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.3500338064
Short name T1470
Test name
Test status
Simulation time 237638459 ps
CPU time 0.91 seconds
Started Jul 24 05:29:27 PM PDT 24
Finished Jul 24 05:29:28 PM PDT 24
Peak memory 206592 kb
Host smart-1367bac0-5a92-4898-bdac-3690245aa126
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3500338064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.3500338064
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.4284446002
Short name T1930
Test name
Test status
Simulation time 138199733 ps
CPU time 0.73 seconds
Started Jul 24 05:29:31 PM PDT 24
Finished Jul 24 05:29:32 PM PDT 24
Peak memory 206552 kb
Host smart-d5f4ed28-6fdc-48a9-b5b6-328cd4661453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42844
46002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.4284446002
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.4213323965
Short name T898
Test name
Test status
Simulation time 30080392 ps
CPU time 0.63 seconds
Started Jul 24 05:29:33 PM PDT 24
Finished Jul 24 05:29:34 PM PDT 24
Peak memory 206584 kb
Host smart-dbf56682-db74-4ec7-b115-6f9410e5af2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42133
23965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.4213323965
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.4103647760
Short name T2223
Test name
Test status
Simulation time 22138232521 ps
CPU time 52.97 seconds
Started Jul 24 05:29:17 PM PDT 24
Finished Jul 24 05:30:10 PM PDT 24
Peak memory 206948 kb
Host smart-a6396732-4e20-4e88-b85a-57ebb59e6c90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41036
47760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.4103647760
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.3009587580
Short name T2258
Test name
Test status
Simulation time 166526780 ps
CPU time 0.79 seconds
Started Jul 24 05:29:26 PM PDT 24
Finished Jul 24 05:29:27 PM PDT 24
Peak memory 206596 kb
Host smart-714dafe8-cb1b-4560-9cd9-1f95d3e69461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30095
87580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.3009587580
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.2045067366
Short name T1973
Test name
Test status
Simulation time 176884861 ps
CPU time 0.84 seconds
Started Jul 24 05:29:21 PM PDT 24
Finished Jul 24 05:29:22 PM PDT 24
Peak memory 206612 kb
Host smart-0814ed25-6b23-410a-9f2b-ebe7db51c4f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20450
67366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.2045067366
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.4167489727
Short name T954
Test name
Test status
Simulation time 163460918 ps
CPU time 0.76 seconds
Started Jul 24 05:29:30 PM PDT 24
Finished Jul 24 05:29:30 PM PDT 24
Peak memory 206584 kb
Host smart-318de180-87bd-4e87-9fb8-602e91b09ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41674
89727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.4167489727
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.3574690728
Short name T736
Test name
Test status
Simulation time 213533449 ps
CPU time 0.89 seconds
Started Jul 24 05:29:15 PM PDT 24
Finished Jul 24 05:29:16 PM PDT 24
Peak memory 206600 kb
Host smart-03d0e3ae-e4f7-4792-9636-1947ec88ad09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35746
90728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.3574690728
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.923183606
Short name T2635
Test name
Test status
Simulation time 204851782 ps
CPU time 0.81 seconds
Started Jul 24 05:29:32 PM PDT 24
Finished Jul 24 05:29:33 PM PDT 24
Peak memory 206540 kb
Host smart-fd5fa361-469d-4504-bf4e-0c9ff78cb7ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92318
3606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.923183606
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.454156321
Short name T2466
Test name
Test status
Simulation time 149946341 ps
CPU time 0.77 seconds
Started Jul 24 05:29:17 PM PDT 24
Finished Jul 24 05:29:18 PM PDT 24
Peak memory 206576 kb
Host smart-69df986b-4246-4a5c-9628-f0d3639f11f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45415
6321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.454156321
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.1025221906
Short name T2129
Test name
Test status
Simulation time 163389237 ps
CPU time 0.79 seconds
Started Jul 24 05:29:18 PM PDT 24
Finished Jul 24 05:29:19 PM PDT 24
Peak memory 206604 kb
Host smart-7e762828-0bd7-4a8b-a1be-72b3c366cc03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10252
21906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.1025221906
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.2952331125
Short name T406
Test name
Test status
Simulation time 194910972 ps
CPU time 0.86 seconds
Started Jul 24 05:29:11 PM PDT 24
Finished Jul 24 05:29:12 PM PDT 24
Peak memory 206580 kb
Host smart-6e1677ff-8961-4cfd-827e-b3dbab4a237b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29523
31125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.2952331125
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.4257768867
Short name T1972
Test name
Test status
Simulation time 4461250880 ps
CPU time 40.08 seconds
Started Jul 24 05:29:08 PM PDT 24
Finished Jul 24 05:29:49 PM PDT 24
Peak memory 206904 kb
Host smart-6a11c00f-827f-4cd3-b489-e3fbef99c689
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4257768867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.4257768867
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.201697692
Short name T2391
Test name
Test status
Simulation time 233324921 ps
CPU time 0.9 seconds
Started Jul 24 05:29:21 PM PDT 24
Finished Jul 24 05:29:22 PM PDT 24
Peak memory 206556 kb
Host smart-ec66721b-9300-466f-b38a-32003440344e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20169
7692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.201697692
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.3838812581
Short name T874
Test name
Test status
Simulation time 194441226 ps
CPU time 0.83 seconds
Started Jul 24 05:29:35 PM PDT 24
Finished Jul 24 05:29:36 PM PDT 24
Peak memory 206648 kb
Host smart-d1f8df23-ef75-4321-8bb3-ff6ea4a4e2a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38388
12581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.3838812581
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.887090405
Short name T552
Test name
Test status
Simulation time 451090064 ps
CPU time 1.27 seconds
Started Jul 24 05:29:14 PM PDT 24
Finished Jul 24 05:29:15 PM PDT 24
Peak memory 206584 kb
Host smart-0b12c056-a452-4abe-986d-c2314e910ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88709
0405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.887090405
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.3331527410
Short name T2618
Test name
Test status
Simulation time 6243610453 ps
CPU time 164.8 seconds
Started Jul 24 05:29:27 PM PDT 24
Finished Jul 24 05:32:12 PM PDT 24
Peak memory 206888 kb
Host smart-5d9e94f5-4dbb-49d2-a36c-14d4cddb31ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33315
27410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.3331527410
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.3574201819
Short name T2621
Test name
Test status
Simulation time 52694216 ps
CPU time 0.65 seconds
Started Jul 24 05:29:29 PM PDT 24
Finished Jul 24 05:29:30 PM PDT 24
Peak memory 206568 kb
Host smart-a824eeef-13d0-4e97-8f9b-6f94c702de9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3574201819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.3574201819
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.4163925870
Short name T8
Test name
Test status
Simulation time 3767610275 ps
CPU time 4.44 seconds
Started Jul 24 05:29:28 PM PDT 24
Finished Jul 24 05:29:33 PM PDT 24
Peak memory 206720 kb
Host smart-bb72ad54-33bb-49b1-ac09-5b4684f68b28
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4163925870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.4163925870
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.4005878663
Short name T1398
Test name
Test status
Simulation time 13361284126 ps
CPU time 11.73 seconds
Started Jul 24 05:29:23 PM PDT 24
Finished Jul 24 05:29:35 PM PDT 24
Peak memory 206872 kb
Host smart-19e1affb-08a9-4a50-9506-0510520eb137
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4005878663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.4005878663
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.3186839644
Short name T2534
Test name
Test status
Simulation time 23371279003 ps
CPU time 24.27 seconds
Started Jul 24 05:29:21 PM PDT 24
Finished Jul 24 05:29:45 PM PDT 24
Peak memory 206704 kb
Host smart-5596f898-b653-4f3b-a5f8-c17f1776104e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3186839644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.3186839644
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.2428188138
Short name T540
Test name
Test status
Simulation time 170688797 ps
CPU time 0.81 seconds
Started Jul 24 05:29:23 PM PDT 24
Finished Jul 24 05:29:24 PM PDT 24
Peak memory 206596 kb
Host smart-3dee5039-3b66-42ba-8ba5-233d00519da2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24281
88138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.2428188138
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.2014896969
Short name T1569
Test name
Test status
Simulation time 152044433 ps
CPU time 0.84 seconds
Started Jul 24 05:29:35 PM PDT 24
Finished Jul 24 05:29:36 PM PDT 24
Peak memory 206568 kb
Host smart-cdf119e0-13d5-4808-8284-7877041ed49b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20148
96969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.2014896969
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.958459571
Short name T977
Test name
Test status
Simulation time 279592882 ps
CPU time 1.13 seconds
Started Jul 24 05:29:24 PM PDT 24
Finished Jul 24 05:29:26 PM PDT 24
Peak memory 206656 kb
Host smart-4329ac87-7416-48cf-afe3-f39c69e5566f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95845
9571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.958459571
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.2739437354
Short name T102
Test name
Test status
Simulation time 1495382436 ps
CPU time 3.08 seconds
Started Jul 24 05:29:40 PM PDT 24
Finished Jul 24 05:29:43 PM PDT 24
Peak memory 206772 kb
Host smart-261e43f4-f802-40e1-982e-7777d3de2b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27394
37354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.2739437354
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.228596703
Short name T89
Test name
Test status
Simulation time 14023347228 ps
CPU time 23.49 seconds
Started Jul 24 05:29:31 PM PDT 24
Finished Jul 24 05:29:54 PM PDT 24
Peak memory 206908 kb
Host smart-13f6e5df-5f6a-4fad-9cc9-a53faf8571c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22859
6703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.228596703
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.3269064042
Short name T1057
Test name
Test status
Simulation time 333956982 ps
CPU time 1.12 seconds
Started Jul 24 05:29:25 PM PDT 24
Finished Jul 24 05:29:26 PM PDT 24
Peak memory 206596 kb
Host smart-71018733-fe78-4a53-87cf-83103a44e9de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32690
64042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.3269064042
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.2266462360
Short name T2050
Test name
Test status
Simulation time 162553997 ps
CPU time 0.81 seconds
Started Jul 24 05:29:20 PM PDT 24
Finished Jul 24 05:29:21 PM PDT 24
Peak memory 206556 kb
Host smart-e304ba41-f933-4939-8bc2-b0a5df2ab196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22664
62360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.2266462360
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.3799640017
Short name T329
Test name
Test status
Simulation time 45299483 ps
CPU time 0.67 seconds
Started Jul 24 05:29:33 PM PDT 24
Finished Jul 24 05:29:34 PM PDT 24
Peak memory 206548 kb
Host smart-bce0ce6d-acad-45ba-93b5-2598c5a05430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37996
40017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.3799640017
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.1851771082
Short name T452
Test name
Test status
Simulation time 978213530 ps
CPU time 2.39 seconds
Started Jul 24 05:29:32 PM PDT 24
Finished Jul 24 05:29:35 PM PDT 24
Peak memory 206888 kb
Host smart-ea336016-b968-4dbf-b238-6fd491b52e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18517
71082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.1851771082
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.2318991334
Short name T2186
Test name
Test status
Simulation time 217117415 ps
CPU time 1.24 seconds
Started Jul 24 05:29:17 PM PDT 24
Finished Jul 24 05:29:18 PM PDT 24
Peak memory 206832 kb
Host smart-d51423e4-de02-493f-a124-147337c9c29e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23189
91334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.2318991334
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.3954793067
Short name T1464
Test name
Test status
Simulation time 222974314 ps
CPU time 0.85 seconds
Started Jul 24 05:29:31 PM PDT 24
Finished Jul 24 05:29:32 PM PDT 24
Peak memory 206548 kb
Host smart-33994184-59da-4c3b-879b-fe6cb7451796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39547
93067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.3954793067
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.3002706535
Short name T1671
Test name
Test status
Simulation time 166400742 ps
CPU time 0.81 seconds
Started Jul 24 05:29:31 PM PDT 24
Finished Jul 24 05:29:32 PM PDT 24
Peak memory 206588 kb
Host smart-e749e846-0da4-4bd7-b573-3045dc729951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30027
06535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.3002706535
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.138379533
Short name T1160
Test name
Test status
Simulation time 246611890 ps
CPU time 0.9 seconds
Started Jul 24 05:29:32 PM PDT 24
Finished Jul 24 05:29:33 PM PDT 24
Peak memory 206576 kb
Host smart-f1589286-91f7-4066-90b3-16336228921d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13837
9533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.138379533
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.325668460
Short name T1090
Test name
Test status
Simulation time 8258212166 ps
CPU time 58.81 seconds
Started Jul 24 05:29:30 PM PDT 24
Finished Jul 24 05:30:29 PM PDT 24
Peak memory 206920 kb
Host smart-c5f398f7-eb7b-4638-9f71-01888ea5e923
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=325668460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.325668460
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_iso_retraction.546508994
Short name T658
Test name
Test status
Simulation time 10084137179 ps
CPU time 37.16 seconds
Started Jul 24 05:29:39 PM PDT 24
Finished Jul 24 05:30:16 PM PDT 24
Peak memory 206924 kb
Host smart-0c286560-2df5-496c-9e93-942ac993eab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54650
8994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_iso_retraction.546508994
Directory /workspace/43.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.1756899074
Short name T1944
Test name
Test status
Simulation time 186495464 ps
CPU time 0.83 seconds
Started Jul 24 05:29:34 PM PDT 24
Finished Jul 24 05:29:35 PM PDT 24
Peak memory 206376 kb
Host smart-719a7e3d-6f42-4dea-9a8d-bafbd622b54d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17568
99074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.1756899074
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.2502490534
Short name T2537
Test name
Test status
Simulation time 23308837508 ps
CPU time 29.27 seconds
Started Jul 24 05:29:36 PM PDT 24
Finished Jul 24 05:30:05 PM PDT 24
Peak memory 206712 kb
Host smart-90ac704c-0b20-49da-b155-df137a47392b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25024
90534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.2502490534
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.375608921
Short name T2587
Test name
Test status
Simulation time 3344501909 ps
CPU time 4.29 seconds
Started Jul 24 05:29:23 PM PDT 24
Finished Jul 24 05:29:27 PM PDT 24
Peak memory 206508 kb
Host smart-31e5e87a-dda3-44c4-8799-15ae3d612393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37560
8921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.375608921
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.113497554
Short name T1170
Test name
Test status
Simulation time 14464509687 ps
CPU time 418.06 seconds
Started Jul 24 05:30:11 PM PDT 24
Finished Jul 24 05:37:09 PM PDT 24
Peak memory 207040 kb
Host smart-e833ab17-4759-478f-ac40-03495b47bb47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11349
7554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.113497554
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.427082763
Short name T1354
Test name
Test status
Simulation time 4092428031 ps
CPU time 108.65 seconds
Started Jul 24 05:29:24 PM PDT 24
Finished Jul 24 05:31:13 PM PDT 24
Peak memory 206900 kb
Host smart-6ad6dcbc-bd13-468a-ad41-f7c0bbf1328f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=427082763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.427082763
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.2638680400
Short name T2708
Test name
Test status
Simulation time 238988366 ps
CPU time 0.92 seconds
Started Jul 24 05:29:27 PM PDT 24
Finished Jul 24 05:29:28 PM PDT 24
Peak memory 206576 kb
Host smart-8e51e316-0e8f-47b5-82f9-49123ce149ac
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2638680400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.2638680400
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.488531890
Short name T611
Test name
Test status
Simulation time 187694498 ps
CPU time 0.85 seconds
Started Jul 24 05:29:37 PM PDT 24
Finished Jul 24 05:29:38 PM PDT 24
Peak memory 206592 kb
Host smart-e1a9cf0e-0514-4eb1-80bc-0e062d028e40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48853
1890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.488531890
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.729353941
Short name T2462
Test name
Test status
Simulation time 5794028613 ps
CPU time 42.07 seconds
Started Jul 24 05:29:33 PM PDT 24
Finished Jul 24 05:30:15 PM PDT 24
Peak memory 206860 kb
Host smart-1250a060-d023-4364-8d9d-b799a7540390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72935
3941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.729353941
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.2093523942
Short name T1234
Test name
Test status
Simulation time 6044894476 ps
CPU time 41.65 seconds
Started Jul 24 05:29:28 PM PDT 24
Finished Jul 24 05:30:10 PM PDT 24
Peak memory 206900 kb
Host smart-0d89d37b-4f72-4780-8d39-9f43c083b369
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2093523942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.2093523942
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.2410701006
Short name T2742
Test name
Test status
Simulation time 173514899 ps
CPU time 0.78 seconds
Started Jul 24 05:29:29 PM PDT 24
Finished Jul 24 05:29:30 PM PDT 24
Peak memory 206568 kb
Host smart-857c46dc-e9a2-4e7c-a27a-50f854740a2e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2410701006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.2410701006
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.3099245455
Short name T1849
Test name
Test status
Simulation time 178866956 ps
CPU time 0.77 seconds
Started Jul 24 05:29:29 PM PDT 24
Finished Jul 24 05:29:30 PM PDT 24
Peak memory 206544 kb
Host smart-44bdc63c-7c4b-4eff-94cb-0ec514681cb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30992
45455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.3099245455
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.4037230023
Short name T135
Test name
Test status
Simulation time 221489914 ps
CPU time 0.81 seconds
Started Jul 24 05:29:41 PM PDT 24
Finished Jul 24 05:29:42 PM PDT 24
Peak memory 206548 kb
Host smart-34aaa6f5-8ded-4b16-95ab-2d6ec49ce0a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40372
30023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.4037230023
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.267842497
Short name T1003
Test name
Test status
Simulation time 180314125 ps
CPU time 0.88 seconds
Started Jul 24 05:29:29 PM PDT 24
Finished Jul 24 05:29:30 PM PDT 24
Peak memory 206772 kb
Host smart-661d177a-9ba8-4641-aea2-d8cc868d2ba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26784
2497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.267842497
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.343395851
Short name T393
Test name
Test status
Simulation time 150258819 ps
CPU time 0.76 seconds
Started Jul 24 05:29:34 PM PDT 24
Finished Jul 24 05:29:35 PM PDT 24
Peak memory 206560 kb
Host smart-3c593929-403a-44f6-b7d1-4f47fe4aaf49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34339
5851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.343395851
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.3886592228
Short name T766
Test name
Test status
Simulation time 188403697 ps
CPU time 0.79 seconds
Started Jul 24 05:29:32 PM PDT 24
Finished Jul 24 05:29:33 PM PDT 24
Peak memory 206548 kb
Host smart-17b00285-c67f-45e7-8641-08a883295fda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38865
92228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.3886592228
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.2994195042
Short name T2235
Test name
Test status
Simulation time 206741237 ps
CPU time 0.83 seconds
Started Jul 24 05:29:33 PM PDT 24
Finished Jul 24 05:29:34 PM PDT 24
Peak memory 206552 kb
Host smart-3d85cb6b-0aa7-45bb-ac25-b26c2f4529a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29941
95042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.2994195042
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.849702886
Short name T609
Test name
Test status
Simulation time 186496714 ps
CPU time 0.85 seconds
Started Jul 24 05:29:31 PM PDT 24
Finished Jul 24 05:29:32 PM PDT 24
Peak memory 206552 kb
Host smart-3031c1d8-5233-492f-8c6a-94419333c7ee
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=849702886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.849702886
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.1593790123
Short name T2091
Test name
Test status
Simulation time 144822384 ps
CPU time 0.74 seconds
Started Jul 24 05:29:32 PM PDT 24
Finished Jul 24 05:29:33 PM PDT 24
Peak memory 206616 kb
Host smart-dcbef31d-8b6d-4841-a6c9-4872a5f8f0b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15937
90123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.1593790123
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.1165695580
Short name T2597
Test name
Test status
Simulation time 53304255 ps
CPU time 0.66 seconds
Started Jul 24 05:29:34 PM PDT 24
Finished Jul 24 05:29:35 PM PDT 24
Peak memory 206596 kb
Host smart-c400dae7-21e8-48b9-84d4-684429ce8cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11656
95580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.1165695580
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.4237205763
Short name T265
Test name
Test status
Simulation time 16997746239 ps
CPU time 37.06 seconds
Started Jul 24 05:29:34 PM PDT 24
Finished Jul 24 05:30:17 PM PDT 24
Peak memory 215220 kb
Host smart-692d3028-4ff8-4789-b535-3ed15503399e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42372
05763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.4237205763
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.3472418543
Short name T1333
Test name
Test status
Simulation time 222316200 ps
CPU time 0.88 seconds
Started Jul 24 05:29:34 PM PDT 24
Finished Jul 24 05:29:35 PM PDT 24
Peak memory 206576 kb
Host smart-d36fc087-5928-4df8-ade1-11e2a2dd3d46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34724
18543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.3472418543
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.1256231457
Short name T779
Test name
Test status
Simulation time 164585929 ps
CPU time 0.77 seconds
Started Jul 24 05:29:35 PM PDT 24
Finished Jul 24 05:29:36 PM PDT 24
Peak memory 206596 kb
Host smart-ed1e6334-81ee-4e25-af18-de7e58345142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12562
31457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.1256231457
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.1726236901
Short name T2040
Test name
Test status
Simulation time 172467541 ps
CPU time 0.79 seconds
Started Jul 24 05:29:27 PM PDT 24
Finished Jul 24 05:29:28 PM PDT 24
Peak memory 206644 kb
Host smart-71809025-229b-414c-b275-013bfc626ed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17262
36901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.1726236901
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.2975232557
Short name T1454
Test name
Test status
Simulation time 221116473 ps
CPU time 0.85 seconds
Started Jul 24 05:29:23 PM PDT 24
Finished Jul 24 05:29:24 PM PDT 24
Peak memory 206616 kb
Host smart-ba5eff3d-b917-4fdc-b864-2ca82791315c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29752
32557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.2975232557
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.3360529432
Short name T1691
Test name
Test status
Simulation time 163308316 ps
CPU time 0.81 seconds
Started Jul 24 05:29:27 PM PDT 24
Finished Jul 24 05:29:28 PM PDT 24
Peak memory 206528 kb
Host smart-4fe9ea23-30d4-4af2-a514-818fbed68aa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33605
29432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.3360529432
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.4229291151
Short name T2658
Test name
Test status
Simulation time 147571074 ps
CPU time 0.75 seconds
Started Jul 24 05:29:38 PM PDT 24
Finished Jul 24 05:29:39 PM PDT 24
Peak memory 206552 kb
Host smart-6bd08fc6-c82c-44c2-8355-7de8bd99c9f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42292
91151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.4229291151
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.2964824712
Short name T1176
Test name
Test status
Simulation time 148182772 ps
CPU time 0.81 seconds
Started Jul 24 05:30:11 PM PDT 24
Finished Jul 24 05:30:12 PM PDT 24
Peak memory 206524 kb
Host smart-4666a51d-c122-4de0-b0b3-11a3b0f7f723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29648
24712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.2964824712
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.2875682454
Short name T857
Test name
Test status
Simulation time 238353665 ps
CPU time 0.97 seconds
Started Jul 24 05:29:36 PM PDT 24
Finished Jul 24 05:29:38 PM PDT 24
Peak memory 206564 kb
Host smart-5c29380f-a084-440c-a0e0-7ff0b9782487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28756
82454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.2875682454
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.2078183022
Short name T1938
Test name
Test status
Simulation time 6866664217 ps
CPU time 195.63 seconds
Started Jul 24 05:29:38 PM PDT 24
Finished Jul 24 05:32:54 PM PDT 24
Peak memory 206872 kb
Host smart-07d511e0-fc63-4df7-b0b2-076288e148e2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2078183022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.2078183022
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.3816852466
Short name T2528
Test name
Test status
Simulation time 189787247 ps
CPU time 0.84 seconds
Started Jul 24 05:29:44 PM PDT 24
Finished Jul 24 05:29:45 PM PDT 24
Peak memory 206652 kb
Host smart-0bfd43cf-1006-46f0-b658-bf40243bdc94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38168
52466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.3816852466
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.3295515792
Short name T1184
Test name
Test status
Simulation time 186641720 ps
CPU time 0.84 seconds
Started Jul 24 05:29:42 PM PDT 24
Finished Jul 24 05:29:43 PM PDT 24
Peak memory 206580 kb
Host smart-8c00c9e0-4240-4279-a86b-90084332e629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32955
15792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.3295515792
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.1686008649
Short name T477
Test name
Test status
Simulation time 860980462 ps
CPU time 2 seconds
Started Jul 24 05:29:28 PM PDT 24
Finished Jul 24 05:29:31 PM PDT 24
Peak memory 206760 kb
Host smart-487af991-0a33-4c72-a08e-5e065292c41c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16860
08649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.1686008649
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.3931125054
Short name T2645
Test name
Test status
Simulation time 3800659888 ps
CPU time 37.31 seconds
Started Jul 24 05:29:42 PM PDT 24
Finished Jul 24 05:30:19 PM PDT 24
Peak memory 206904 kb
Host smart-6b67836a-c9e7-497f-aed6-dd20a5be1ff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39311
25054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.3931125054
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.256848782
Short name T176
Test name
Test status
Simulation time 46396413 ps
CPU time 0.65 seconds
Started Jul 24 05:29:41 PM PDT 24
Finished Jul 24 05:29:42 PM PDT 24
Peak memory 206584 kb
Host smart-9306d138-e9db-41f5-98e6-4535d5a66425
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=256848782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.256848782
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.3682993824
Short name T1737
Test name
Test status
Simulation time 4208322193 ps
CPU time 4.39 seconds
Started Jul 24 05:29:32 PM PDT 24
Finished Jul 24 05:29:36 PM PDT 24
Peak memory 207004 kb
Host smart-0ba39bb6-3b92-4071-b59b-08f8fac43c0c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3682993824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.3682993824
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.696708079
Short name T2001
Test name
Test status
Simulation time 13295838462 ps
CPU time 11.64 seconds
Started Jul 24 05:29:37 PM PDT 24
Finished Jul 24 05:29:49 PM PDT 24
Peak memory 206940 kb
Host smart-9f4fc99d-ce13-4131-8d84-cb6e00d081e8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=696708079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.696708079
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.2260058131
Short name T2248
Test name
Test status
Simulation time 23368476797 ps
CPU time 23.36 seconds
Started Jul 24 05:29:29 PM PDT 24
Finished Jul 24 05:29:52 PM PDT 24
Peak memory 206692 kb
Host smart-8546ee4f-cd4c-4baa-9f7c-bbe4c06c73e2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2260058131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.2260058131
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.2301227005
Short name T994
Test name
Test status
Simulation time 147882048 ps
CPU time 0.79 seconds
Started Jul 24 05:29:34 PM PDT 24
Finished Jul 24 05:29:35 PM PDT 24
Peak memory 206536 kb
Host smart-9b89f44b-b238-48af-ae7c-511fe0a8fd82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23012
27005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.2301227005
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.2934680764
Short name T1505
Test name
Test status
Simulation time 154772387 ps
CPU time 0.78 seconds
Started Jul 24 05:29:35 PM PDT 24
Finished Jul 24 05:29:36 PM PDT 24
Peak memory 206588 kb
Host smart-c31f93db-b36a-4eff-9180-afd44048c3a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29346
80764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.2934680764
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.2628765270
Short name T2433
Test name
Test status
Simulation time 405889786 ps
CPU time 1.22 seconds
Started Jul 24 05:29:33 PM PDT 24
Finished Jul 24 05:29:35 PM PDT 24
Peak memory 206516 kb
Host smart-6b78c333-8460-475e-9ba5-a1fd7791d483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26287
65270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.2628765270
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.227877604
Short name T2096
Test name
Test status
Simulation time 339857794 ps
CPU time 1.09 seconds
Started Jul 24 05:29:30 PM PDT 24
Finished Jul 24 05:29:31 PM PDT 24
Peak memory 206592 kb
Host smart-0e340629-2ea4-4639-84d4-4635a6dd58e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22787
7604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.227877604
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.904124961
Short name T2175
Test name
Test status
Simulation time 8866273836 ps
CPU time 16.97 seconds
Started Jul 24 05:29:39 PM PDT 24
Finished Jul 24 05:29:56 PM PDT 24
Peak memory 206860 kb
Host smart-3631269b-dfda-424f-9e21-14d37f4c38ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90412
4961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.904124961
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.3130275218
Short name T233
Test name
Test status
Simulation time 424928671 ps
CPU time 1.2 seconds
Started Jul 24 05:29:47 PM PDT 24
Finished Jul 24 05:29:48 PM PDT 24
Peak memory 206596 kb
Host smart-ff9a53e3-aeff-445f-bf11-89902228a6be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31302
75218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.3130275218
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.2784886618
Short name T2182
Test name
Test status
Simulation time 146078995 ps
CPU time 0.75 seconds
Started Jul 24 05:29:37 PM PDT 24
Finished Jul 24 05:29:38 PM PDT 24
Peak memory 206380 kb
Host smart-0f60ab22-0f46-4c82-ba9f-f239e7cd952f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27848
86618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.2784886618
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.3762092235
Short name T1239
Test name
Test status
Simulation time 43618901 ps
CPU time 0.63 seconds
Started Jul 24 05:29:36 PM PDT 24
Finished Jul 24 05:29:37 PM PDT 24
Peak memory 206556 kb
Host smart-5f3ccc08-147f-4c2b-b46a-4bfaece52998
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37620
92235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.3762092235
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.3890165654
Short name T316
Test name
Test status
Simulation time 1058481667 ps
CPU time 2.44 seconds
Started Jul 24 05:29:27 PM PDT 24
Finished Jul 24 05:29:30 PM PDT 24
Peak memory 206760 kb
Host smart-72d47ef0-770a-492d-93f0-9c14ea65be2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38901
65654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.3890165654
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.1079522763
Short name T434
Test name
Test status
Simulation time 190828919 ps
CPU time 2.19 seconds
Started Jul 24 05:29:41 PM PDT 24
Finished Jul 24 05:29:44 PM PDT 24
Peak memory 206780 kb
Host smart-eb5ce4de-3c07-4655-bbf2-e9bc0dc6c2de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10795
22763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.1079522763
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.465401607
Short name T2245
Test name
Test status
Simulation time 227390581 ps
CPU time 0.89 seconds
Started Jul 24 05:29:34 PM PDT 24
Finished Jul 24 05:29:35 PM PDT 24
Peak memory 206632 kb
Host smart-0ed18155-4ad6-4641-8fc5-de90577403bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46540
1607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.465401607
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.2581245350
Short name T1002
Test name
Test status
Simulation time 185060100 ps
CPU time 0.82 seconds
Started Jul 24 05:29:36 PM PDT 24
Finished Jul 24 05:29:37 PM PDT 24
Peak memory 206552 kb
Host smart-5d99a750-7674-49ac-abc1-ecf4ed1c59e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25812
45350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.2581245350
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.1972840100
Short name T2185
Test name
Test status
Simulation time 220790670 ps
CPU time 0.86 seconds
Started Jul 24 05:29:31 PM PDT 24
Finished Jul 24 05:29:32 PM PDT 24
Peak memory 206644 kb
Host smart-84c13f46-7252-495c-a5da-d0fe1f68db01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19728
40100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.1972840100
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.1691629181
Short name T2013
Test name
Test status
Simulation time 7827835562 ps
CPU time 222.56 seconds
Started Jul 24 05:29:38 PM PDT 24
Finished Jul 24 05:33:20 PM PDT 24
Peak memory 206896 kb
Host smart-8c977428-2fce-47fa-9e61-f9a6a74ad8f3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1691629181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.1691629181
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_iso_retraction.2191459531
Short name T1886
Test name
Test status
Simulation time 8698525771 ps
CPU time 70.99 seconds
Started Jul 24 05:29:50 PM PDT 24
Finished Jul 24 05:31:01 PM PDT 24
Peak memory 206920 kb
Host smart-dfb66128-77f6-4da8-b64c-45ff562bb013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21914
59531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_iso_retraction.2191459531
Directory /workspace/44.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.1952984577
Short name T1115
Test name
Test status
Simulation time 226147940 ps
CPU time 0.89 seconds
Started Jul 24 05:29:37 PM PDT 24
Finished Jul 24 05:29:39 PM PDT 24
Peak memory 206388 kb
Host smart-c7c99e5a-9f75-45e3-b47c-46207607f463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19529
84577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.1952984577
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.973585079
Short name T1909
Test name
Test status
Simulation time 23323063844 ps
CPU time 22.27 seconds
Started Jul 24 05:29:36 PM PDT 24
Finished Jul 24 05:29:59 PM PDT 24
Peak memory 206664 kb
Host smart-ae8903d3-e133-4f66-98b8-432e9cde7db1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97358
5079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.973585079
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.3458240876
Short name T1240
Test name
Test status
Simulation time 3330511008 ps
CPU time 3.9 seconds
Started Jul 24 05:29:32 PM PDT 24
Finished Jul 24 05:29:36 PM PDT 24
Peak memory 206676 kb
Host smart-03b43b85-3bc0-40bb-9073-262c664dd466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34582
40876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.3458240876
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.3129484376
Short name T2572
Test name
Test status
Simulation time 9094756988 ps
CPU time 66.86 seconds
Started Jul 24 05:29:25 PM PDT 24
Finished Jul 24 05:30:32 PM PDT 24
Peak memory 206972 kb
Host smart-2532c6c9-8e82-4e9f-b9d7-1647bae20e83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31294
84376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.3129484376
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.633616630
Short name T2098
Test name
Test status
Simulation time 4520374044 ps
CPU time 42.24 seconds
Started Jul 24 05:29:31 PM PDT 24
Finished Jul 24 05:30:18 PM PDT 24
Peak memory 206900 kb
Host smart-dcf3abe5-08ba-4bb0-a924-a58c844ab719
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=633616630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.633616630
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.4059875655
Short name T1926
Test name
Test status
Simulation time 248397981 ps
CPU time 0.93 seconds
Started Jul 24 05:29:36 PM PDT 24
Finished Jul 24 05:29:37 PM PDT 24
Peak memory 206584 kb
Host smart-d783435d-cfbd-4044-8103-be23a4ddedce
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4059875655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.4059875655
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.1243885110
Short name T937
Test name
Test status
Simulation time 197888354 ps
CPU time 0.89 seconds
Started Jul 24 05:29:32 PM PDT 24
Finished Jul 24 05:29:33 PM PDT 24
Peak memory 206520 kb
Host smart-9f7aa6be-4591-4ac2-881c-5e9a85479234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12438
85110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.1243885110
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.1481440217
Short name T1660
Test name
Test status
Simulation time 4017432550 ps
CPU time 37.41 seconds
Started Jul 24 05:29:34 PM PDT 24
Finished Jul 24 05:30:12 PM PDT 24
Peak memory 206864 kb
Host smart-fb548781-c0fb-4a54-99e3-9c9224d6aa6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14814
40217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.1481440217
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.4121897781
Short name T1512
Test name
Test status
Simulation time 3834392713 ps
CPU time 35.69 seconds
Started Jul 24 05:29:34 PM PDT 24
Finished Jul 24 05:30:14 PM PDT 24
Peak memory 206760 kb
Host smart-a8205ecb-a7be-42e2-b99d-873ed5ebf5fb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4121897781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.4121897781
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.2652776559
Short name T1430
Test name
Test status
Simulation time 155957915 ps
CPU time 0.77 seconds
Started Jul 24 05:29:29 PM PDT 24
Finished Jul 24 05:29:30 PM PDT 24
Peak memory 206600 kb
Host smart-03dd3014-3382-4ee1-94a3-3611cd92194a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2652776559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.2652776559
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.1738510510
Short name T2062
Test name
Test status
Simulation time 152642101 ps
CPU time 0.75 seconds
Started Jul 24 05:29:49 PM PDT 24
Finished Jul 24 05:29:49 PM PDT 24
Peak memory 206552 kb
Host smart-61a8d706-78d1-4a0a-9264-fac67cce72c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17385
10510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.1738510510
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.4054904444
Short name T118
Test name
Test status
Simulation time 171673357 ps
CPU time 0.78 seconds
Started Jul 24 05:29:42 PM PDT 24
Finished Jul 24 05:29:43 PM PDT 24
Peak memory 206568 kb
Host smart-e52e9e45-38c7-4f33-bc51-03d7bfded95f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40549
04444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.4054904444
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.856421769
Short name T1050
Test name
Test status
Simulation time 194978392 ps
CPU time 0.8 seconds
Started Jul 24 05:29:34 PM PDT 24
Finished Jul 24 05:29:35 PM PDT 24
Peak memory 206516 kb
Host smart-4e32803c-068d-4e49-bf0b-d108a7b68d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85642
1769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.856421769
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.228977005
Short name T1042
Test name
Test status
Simulation time 190812664 ps
CPU time 0.78 seconds
Started Jul 24 05:29:50 PM PDT 24
Finished Jul 24 05:29:51 PM PDT 24
Peak memory 206596 kb
Host smart-8aecb9be-d198-4816-9bfb-384dd635ec31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22897
7005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.228977005
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.3347344460
Short name T2696
Test name
Test status
Simulation time 175094660 ps
CPU time 0.78 seconds
Started Jul 24 05:29:35 PM PDT 24
Finished Jul 24 05:29:36 PM PDT 24
Peak memory 206496 kb
Host smart-b5995ed0-5ad2-4553-8219-06cda1d9deaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33473
44460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.3347344460
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.1345246130
Short name T1318
Test name
Test status
Simulation time 160924533 ps
CPU time 0.78 seconds
Started Jul 24 05:29:41 PM PDT 24
Finished Jul 24 05:29:42 PM PDT 24
Peak memory 206560 kb
Host smart-d8603057-90cf-4824-b8d2-4b7e3debffc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13452
46130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.1345246130
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.1614387155
Short name T1263
Test name
Test status
Simulation time 240200876 ps
CPU time 0.91 seconds
Started Jul 24 05:29:52 PM PDT 24
Finished Jul 24 05:29:53 PM PDT 24
Peak memory 206568 kb
Host smart-5239502f-c14f-4f35-8fd6-ad1fbb1d8f70
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1614387155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.1614387155
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.73574455
Short name T1228
Test name
Test status
Simulation time 174210923 ps
CPU time 0.76 seconds
Started Jul 24 05:29:37 PM PDT 24
Finished Jul 24 05:29:38 PM PDT 24
Peak memory 206544 kb
Host smart-353b6e3d-c71e-431c-83bb-751926dbf18b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73574
455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.73574455
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.745811356
Short name T1515
Test name
Test status
Simulation time 40349624 ps
CPU time 0.67 seconds
Started Jul 24 05:29:47 PM PDT 24
Finished Jul 24 05:29:48 PM PDT 24
Peak memory 206540 kb
Host smart-c8202ef1-dcad-4f3f-a106-8f7024b29652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74581
1356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.745811356
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.2905833747
Short name T2615
Test name
Test status
Simulation time 6515770812 ps
CPU time 15.18 seconds
Started Jul 24 05:29:41 PM PDT 24
Finished Jul 24 05:29:56 PM PDT 24
Peak memory 206924 kb
Host smart-c8f47f12-3fd3-442c-a32d-2b40167cff5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29058
33747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.2905833747
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.2818710365
Short name T234
Test name
Test status
Simulation time 167871553 ps
CPU time 0.8 seconds
Started Jul 24 05:29:48 PM PDT 24
Finished Jul 24 05:29:49 PM PDT 24
Peak memory 206584 kb
Host smart-51691581-efcc-4e97-a9f1-d95f741b5fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28187
10365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.2818710365
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.2849271680
Short name T2090
Test name
Test status
Simulation time 194068337 ps
CPU time 0.83 seconds
Started Jul 24 05:29:41 PM PDT 24
Finished Jul 24 05:29:42 PM PDT 24
Peak memory 206640 kb
Host smart-822fb61c-c24f-4e0e-ac51-d4a1ba3ff2de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28492
71680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.2849271680
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.2694600155
Short name T627
Test name
Test status
Simulation time 166032694 ps
CPU time 0.86 seconds
Started Jul 24 05:29:45 PM PDT 24
Finished Jul 24 05:29:46 PM PDT 24
Peak memory 206452 kb
Host smart-b3a73f73-bfeb-4e1a-b1f1-5da73c633a35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26946
00155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.2694600155
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.1092028665
Short name T1247
Test name
Test status
Simulation time 155389999 ps
CPU time 0.74 seconds
Started Jul 24 05:29:36 PM PDT 24
Finished Jul 24 05:29:36 PM PDT 24
Peak memory 206544 kb
Host smart-609e2763-e803-4165-97b5-910b305986e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10920
28665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.1092028665
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.1575632953
Short name T1130
Test name
Test status
Simulation time 134788221 ps
CPU time 0.74 seconds
Started Jul 24 05:29:43 PM PDT 24
Finished Jul 24 05:29:44 PM PDT 24
Peak memory 206596 kb
Host smart-ab1105d7-a48c-4f8c-896d-94092de14bd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15756
32953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.1575632953
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.413922253
Short name T1636
Test name
Test status
Simulation time 151207488 ps
CPU time 0.74 seconds
Started Jul 24 05:29:42 PM PDT 24
Finished Jul 24 05:29:43 PM PDT 24
Peak memory 206572 kb
Host smart-65e504f8-08b4-4b2a-9efd-70f0103a794d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41392
2253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.413922253
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.1495916261
Short name T502
Test name
Test status
Simulation time 156456849 ps
CPU time 0.77 seconds
Started Jul 24 05:29:47 PM PDT 24
Finished Jul 24 05:29:48 PM PDT 24
Peak memory 206600 kb
Host smart-21e8d095-af70-47ad-b9a6-129503b2b473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14959
16261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.1495916261
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.1123231798
Short name T2640
Test name
Test status
Simulation time 232124902 ps
CPU time 0.91 seconds
Started Jul 24 05:29:38 PM PDT 24
Finished Jul 24 05:29:39 PM PDT 24
Peak memory 206564 kb
Host smart-671ffd8b-b6e1-4392-8b1a-580c5f99519f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11232
31798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.1123231798
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.4270838686
Short name T1871
Test name
Test status
Simulation time 182426584 ps
CPU time 0.8 seconds
Started Jul 24 05:29:54 PM PDT 24
Finished Jul 24 05:29:55 PM PDT 24
Peak memory 206580 kb
Host smart-ba2c21fe-3e71-49d2-89e5-3d2fea44dd8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42708
38686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.4270838686
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.3931531082
Short name T373
Test name
Test status
Simulation time 200883794 ps
CPU time 0.83 seconds
Started Jul 24 05:29:47 PM PDT 24
Finished Jul 24 05:29:48 PM PDT 24
Peak memory 206588 kb
Host smart-51a0d592-da33-4bbf-a701-6b4966e97072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39315
31082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.3931531082
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.1378795316
Short name T1777
Test name
Test status
Simulation time 682014326 ps
CPU time 1.64 seconds
Started Jul 24 05:29:44 PM PDT 24
Finished Jul 24 05:29:46 PM PDT 24
Peak memory 206568 kb
Host smart-cfa46950-7b86-4994-8fce-41af1c42e49c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13787
95316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.1378795316
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.1325306999
Short name T754
Test name
Test status
Simulation time 4459299838 ps
CPU time 118.42 seconds
Started Jul 24 05:29:38 PM PDT 24
Finished Jul 24 05:31:37 PM PDT 24
Peak memory 206808 kb
Host smart-b14bdce8-ca7f-466c-85a2-174b5cd44178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13253
06999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.1325306999
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.2128331805
Short name T2505
Test name
Test status
Simulation time 80461795 ps
CPU time 0.68 seconds
Started Jul 24 05:29:46 PM PDT 24
Finished Jul 24 05:29:47 PM PDT 24
Peak memory 206576 kb
Host smart-6b71c2a1-401e-4345-9bad-117f9cd7bdd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2128331805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.2128331805
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.833225342
Short name T842
Test name
Test status
Simulation time 4206542433 ps
CPU time 5.33 seconds
Started Jul 24 05:29:50 PM PDT 24
Finished Jul 24 05:29:56 PM PDT 24
Peak memory 206968 kb
Host smart-16507ec9-cee6-4515-8a8e-fb7162e66002
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=833225342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.833225342
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.3926929791
Short name T1226
Test name
Test status
Simulation time 13369729424 ps
CPU time 12.36 seconds
Started Jul 24 05:29:53 PM PDT 24
Finished Jul 24 05:30:05 PM PDT 24
Peak memory 206872 kb
Host smart-67501343-5c30-4b9e-bee6-9d336244f372
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3926929791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.3926929791
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.1554444676
Short name T626
Test name
Test status
Simulation time 23392150244 ps
CPU time 23.87 seconds
Started Jul 24 05:29:52 PM PDT 24
Finished Jul 24 05:30:16 PM PDT 24
Peak memory 206724 kb
Host smart-f8aafdb8-68ec-4b78-af8c-933bb4e3781c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1554444676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.1554444676
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.3117262250
Short name T2627
Test name
Test status
Simulation time 159282054 ps
CPU time 0.78 seconds
Started Jul 24 05:29:48 PM PDT 24
Finished Jul 24 05:29:49 PM PDT 24
Peak memory 206480 kb
Host smart-b7a0305d-0b77-42d5-89c7-790634ccc85b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31172
62250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.3117262250
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.1178317169
Short name T1298
Test name
Test status
Simulation time 164413513 ps
CPU time 0.78 seconds
Started Jul 24 05:29:47 PM PDT 24
Finished Jul 24 05:29:48 PM PDT 24
Peak memory 206572 kb
Host smart-2d2c2e25-672c-411b-b2ac-6d93ded53a6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11783
17169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.1178317169
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.1446384733
Short name T2516
Test name
Test status
Simulation time 383245868 ps
CPU time 1.28 seconds
Started Jul 24 05:29:40 PM PDT 24
Finished Jul 24 05:29:41 PM PDT 24
Peak memory 206636 kb
Host smart-6821a7af-4a19-4efc-9ea0-2ae8d3a0c8b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14463
84733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.1446384733
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.681439754
Short name T2739
Test name
Test status
Simulation time 1067611076 ps
CPU time 2.57 seconds
Started Jul 24 05:29:34 PM PDT 24
Finished Jul 24 05:29:37 PM PDT 24
Peak memory 206644 kb
Host smart-0057a3ce-01c5-459a-b431-1cef92482ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68143
9754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.681439754
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.2362706524
Short name T618
Test name
Test status
Simulation time 12889214055 ps
CPU time 25.46 seconds
Started Jul 24 05:29:46 PM PDT 24
Finished Jul 24 05:30:11 PM PDT 24
Peak memory 206968 kb
Host smart-464e6f50-1120-4970-9458-75f2dd590d2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23627
06524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.2362706524
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.1121012472
Short name T942
Test name
Test status
Simulation time 367316587 ps
CPU time 1.21 seconds
Started Jul 24 05:29:52 PM PDT 24
Finished Jul 24 05:29:59 PM PDT 24
Peak memory 206552 kb
Host smart-bbb381c3-1831-42c0-8aa2-dcd7e7ae053d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11210
12472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.1121012472
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.1007015774
Short name T1448
Test name
Test status
Simulation time 134590717 ps
CPU time 0.74 seconds
Started Jul 24 05:29:33 PM PDT 24
Finished Jul 24 05:29:34 PM PDT 24
Peak memory 206620 kb
Host smart-da1f3964-3400-4100-8bed-6b718780723d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10070
15774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.1007015774
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.3363591914
Short name T2171
Test name
Test status
Simulation time 33227570 ps
CPU time 0.64 seconds
Started Jul 24 05:29:35 PM PDT 24
Finished Jul 24 05:29:35 PM PDT 24
Peak memory 206612 kb
Host smart-6b686fcb-02a4-44a6-9fc8-d45440534996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33635
91914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.3363591914
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.361948201
Short name T431
Test name
Test status
Simulation time 814637601 ps
CPU time 2.11 seconds
Started Jul 24 05:29:47 PM PDT 24
Finished Jul 24 05:29:50 PM PDT 24
Peak memory 206716 kb
Host smart-1b794212-2e72-4bd2-be67-5726a6a186b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36194
8201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.361948201
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.1883674615
Short name T2162
Test name
Test status
Simulation time 323403466 ps
CPU time 2.37 seconds
Started Jul 24 05:29:42 PM PDT 24
Finished Jul 24 05:29:50 PM PDT 24
Peak memory 206792 kb
Host smart-3cf8dbd1-fb6b-4c9f-856c-0d9f4b14d0e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18836
74615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.1883674615
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.924185137
Short name T2291
Test name
Test status
Simulation time 239927050 ps
CPU time 1 seconds
Started Jul 24 05:29:45 PM PDT 24
Finished Jul 24 05:29:46 PM PDT 24
Peak memory 206576 kb
Host smart-ca70fef2-3f99-4213-a643-7fe517732086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92418
5137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.924185137
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.1279400100
Short name T1204
Test name
Test status
Simulation time 144650560 ps
CPU time 0.76 seconds
Started Jul 24 05:29:39 PM PDT 24
Finished Jul 24 05:29:40 PM PDT 24
Peak memory 206640 kb
Host smart-bb878df8-91b2-4cb8-a7a8-30e759f69462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12794
00100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.1279400100
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.1175681798
Short name T1627
Test name
Test status
Simulation time 207973277 ps
CPU time 0.86 seconds
Started Jul 24 05:29:48 PM PDT 24
Finished Jul 24 05:29:49 PM PDT 24
Peak memory 206508 kb
Host smart-68edf4c7-9dbd-4877-a494-b418c9a36b63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11756
81798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.1175681798
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_iso_retraction.1623184663
Short name T1575
Test name
Test status
Simulation time 4476144609 ps
CPU time 36.65 seconds
Started Jul 24 05:29:37 PM PDT 24
Finished Jul 24 05:30:14 PM PDT 24
Peak memory 206856 kb
Host smart-d1981bed-cbab-4a37-8f84-133390cf3b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16231
84663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_iso_retraction.1623184663
Directory /workspace/45.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.992504680
Short name T2350
Test name
Test status
Simulation time 224393457 ps
CPU time 0.88 seconds
Started Jul 24 05:29:40 PM PDT 24
Finished Jul 24 05:29:41 PM PDT 24
Peak memory 206516 kb
Host smart-412679b9-59c1-4373-a70e-889388fbaf2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99250
4680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.992504680
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.1983905435
Short name T1137
Test name
Test status
Simulation time 23304556915 ps
CPU time 24.8 seconds
Started Jul 24 05:29:47 PM PDT 24
Finished Jul 24 05:30:12 PM PDT 24
Peak memory 206672 kb
Host smart-dce004c9-ca49-4b2d-b39a-58ed20205e77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19839
05435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.1983905435
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.3213848299
Short name T1549
Test name
Test status
Simulation time 3305004479 ps
CPU time 3.82 seconds
Started Jul 24 05:29:37 PM PDT 24
Finished Jul 24 05:29:41 PM PDT 24
Peak memory 206596 kb
Host smart-583a9045-fe4d-46db-86da-2be5154a77f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32138
48299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.3213848299
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.513639955
Short name T2530
Test name
Test status
Simulation time 6927378926 ps
CPU time 191.56 seconds
Started Jul 24 05:29:42 PM PDT 24
Finished Jul 24 05:32:54 PM PDT 24
Peak memory 207048 kb
Host smart-09ce7bc6-98a9-429c-ad40-d3ff3f7f15b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51363
9955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.513639955
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.1673089674
Short name T1647
Test name
Test status
Simulation time 7422286342 ps
CPU time 69.95 seconds
Started Jul 24 05:29:49 PM PDT 24
Finished Jul 24 05:30:59 PM PDT 24
Peak memory 206944 kb
Host smart-2e4a1ff8-10a7-40fd-a563-362384433c9f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1673089674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.1673089674
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.2229870803
Short name T2659
Test name
Test status
Simulation time 233643525 ps
CPU time 0.86 seconds
Started Jul 24 05:29:50 PM PDT 24
Finished Jul 24 05:29:51 PM PDT 24
Peak memory 206636 kb
Host smart-03469a0b-af98-4bb4-b7b9-f112ef49a86d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2229870803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.2229870803
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.1984466555
Short name T1025
Test name
Test status
Simulation time 198654248 ps
CPU time 0.88 seconds
Started Jul 24 05:29:42 PM PDT 24
Finished Jul 24 05:29:43 PM PDT 24
Peak memory 206572 kb
Host smart-1132fe0a-34cc-430e-8cc5-654901b67f38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19844
66555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.1984466555
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.4187747245
Short name T2479
Test name
Test status
Simulation time 4331442075 ps
CPU time 39.63 seconds
Started Jul 24 05:29:47 PM PDT 24
Finished Jul 24 05:30:27 PM PDT 24
Peak memory 206852 kb
Host smart-17c2186c-75f9-4efc-92b3-a17f3f1d6078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41877
47245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.4187747245
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.3504913613
Short name T673
Test name
Test status
Simulation time 4171232782 ps
CPU time 36.9 seconds
Started Jul 24 05:29:38 PM PDT 24
Finished Jul 24 05:30:15 PM PDT 24
Peak memory 206840 kb
Host smart-0830deda-4134-4842-a549-bd1d66045ad1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3504913613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.3504913613
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.1290947917
Short name T2481
Test name
Test status
Simulation time 179882613 ps
CPU time 0.8 seconds
Started Jul 24 05:29:51 PM PDT 24
Finished Jul 24 05:29:52 PM PDT 24
Peak memory 206484 kb
Host smart-dca1bfe7-559c-4ebe-b989-07650a960573
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1290947917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.1290947917
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.2394039988
Short name T1395
Test name
Test status
Simulation time 179023154 ps
CPU time 0.79 seconds
Started Jul 24 05:29:43 PM PDT 24
Finished Jul 24 05:29:44 PM PDT 24
Peak memory 206464 kb
Host smart-2e8e0b34-c997-4e8d-9d2f-118616d7851b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23940
39988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.2394039988
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.2138408124
Short name T130
Test name
Test status
Simulation time 201451062 ps
CPU time 0.83 seconds
Started Jul 24 05:29:38 PM PDT 24
Finished Jul 24 05:29:39 PM PDT 24
Peak memory 206508 kb
Host smart-ad1edb22-8f86-4129-afe3-655a23a2403c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21384
08124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.2138408124
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.801159194
Short name T2233
Test name
Test status
Simulation time 142568417 ps
CPU time 0.76 seconds
Started Jul 24 05:29:53 PM PDT 24
Finished Jul 24 05:29:54 PM PDT 24
Peak memory 206488 kb
Host smart-77c988c4-f70e-42fc-b47f-e59fd0f358cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80115
9194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.801159194
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.1427293645
Short name T891
Test name
Test status
Simulation time 183741042 ps
CPU time 0.81 seconds
Started Jul 24 05:29:51 PM PDT 24
Finished Jul 24 05:29:52 PM PDT 24
Peak memory 206600 kb
Host smart-afe30f8f-3401-4652-ab1f-9e54f8613f8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14272
93645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.1427293645
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.4138073461
Short name T1504
Test name
Test status
Simulation time 172636410 ps
CPU time 0.77 seconds
Started Jul 24 05:29:48 PM PDT 24
Finished Jul 24 05:29:49 PM PDT 24
Peak memory 206576 kb
Host smart-ef723780-3947-4cbe-89fe-9f90ca347882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41380
73461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.4138073461
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.2837588617
Short name T1063
Test name
Test status
Simulation time 163635484 ps
CPU time 0.77 seconds
Started Jul 24 05:29:35 PM PDT 24
Finished Jul 24 05:29:36 PM PDT 24
Peak memory 206472 kb
Host smart-19418a51-733f-435d-b52d-4c8f6b34513c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28375
88617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.2837588617
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.2362048251
Short name T41
Test name
Test status
Simulation time 209817274 ps
CPU time 0.91 seconds
Started Jul 24 05:29:45 PM PDT 24
Finished Jul 24 05:29:46 PM PDT 24
Peak memory 206580 kb
Host smart-721167f3-329b-4ca5-93b6-692c897ed0bd
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2362048251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.2362048251
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.733225147
Short name T720
Test name
Test status
Simulation time 160842707 ps
CPU time 0.77 seconds
Started Jul 24 05:29:57 PM PDT 24
Finished Jul 24 05:29:58 PM PDT 24
Peak memory 206472 kb
Host smart-9fa8e44f-a7e2-46c0-b2e2-54751406a28f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73322
5147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.733225147
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.4280832921
Short name T697
Test name
Test status
Simulation time 50756640 ps
CPU time 0.65 seconds
Started Jul 24 05:29:54 PM PDT 24
Finished Jul 24 05:29:55 PM PDT 24
Peak memory 206584 kb
Host smart-f46927b0-99a8-4e90-acf7-096b8187679b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42808
32921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.4280832921
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.880817039
Short name T1626
Test name
Test status
Simulation time 10233361444 ps
CPU time 21.85 seconds
Started Jul 24 05:29:52 PM PDT 24
Finished Jul 24 05:30:14 PM PDT 24
Peak memory 206984 kb
Host smart-0bec3f78-dbf4-49ee-9718-7bf53a11ac18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88081
7039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.880817039
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.4271871008
Short name T2378
Test name
Test status
Simulation time 161496180 ps
CPU time 0.81 seconds
Started Jul 24 05:29:50 PM PDT 24
Finished Jul 24 05:29:51 PM PDT 24
Peak memory 206600 kb
Host smart-062c6d38-bd35-4fa5-834f-9f5c73b7e819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42718
71008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.4271871008
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.3139351032
Short name T785
Test name
Test status
Simulation time 252202794 ps
CPU time 0.89 seconds
Started Jul 24 05:29:42 PM PDT 24
Finished Jul 24 05:29:43 PM PDT 24
Peak memory 206580 kb
Host smart-4ff39ef9-ad10-4173-a555-29ead8bd713f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31393
51032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.3139351032
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.2062044341
Short name T2379
Test name
Test status
Simulation time 200818362 ps
CPU time 0.84 seconds
Started Jul 24 05:29:43 PM PDT 24
Finished Jul 24 05:29:44 PM PDT 24
Peak memory 206560 kb
Host smart-97f68cb0-0c27-4632-a677-588481effb00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20620
44341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.2062044341
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.2467863593
Short name T2610
Test name
Test status
Simulation time 211289289 ps
CPU time 0.86 seconds
Started Jul 24 05:29:49 PM PDT 24
Finished Jul 24 05:29:51 PM PDT 24
Peak memory 206612 kb
Host smart-78d379ae-233a-4049-b1a9-f79f1b16f8d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24678
63593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.2467863593
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.744996955
Short name T83
Test name
Test status
Simulation time 195470321 ps
CPU time 0.8 seconds
Started Jul 24 05:29:55 PM PDT 24
Finished Jul 24 05:29:56 PM PDT 24
Peak memory 206580 kb
Host smart-ddf7e099-3796-46f8-b900-76e32ac4019a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74499
6955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.744996955
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.4290952691
Short name T613
Test name
Test status
Simulation time 159318673 ps
CPU time 0.77 seconds
Started Jul 24 05:29:36 PM PDT 24
Finished Jul 24 05:29:37 PM PDT 24
Peak memory 206548 kb
Host smart-99eed320-2326-4bbe-888f-e2c7dd4470ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42909
52691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.4290952691
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.1882550536
Short name T737
Test name
Test status
Simulation time 164054519 ps
CPU time 0.78 seconds
Started Jul 24 05:29:49 PM PDT 24
Finished Jul 24 05:29:50 PM PDT 24
Peak memory 206504 kb
Host smart-2acdbf49-b49b-4ac8-be89-0c3d38b7882a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18825
50536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.1882550536
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.2672257492
Short name T893
Test name
Test status
Simulation time 263186698 ps
CPU time 1 seconds
Started Jul 24 05:29:40 PM PDT 24
Finished Jul 24 05:29:41 PM PDT 24
Peak memory 206556 kb
Host smart-c2a0ddd3-3258-4a9b-b4bf-51e93eddc83c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26722
57492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.2672257492
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.4053707534
Short name T1527
Test name
Test status
Simulation time 6525243875 ps
CPU time 57.31 seconds
Started Jul 24 05:29:47 PM PDT 24
Finished Jul 24 05:30:44 PM PDT 24
Peak memory 206948 kb
Host smart-acee5775-ade6-43f3-89be-29373f6b0856
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4053707534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.4053707534
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.223295513
Short name T2563
Test name
Test status
Simulation time 161088516 ps
CPU time 0.84 seconds
Started Jul 24 05:29:52 PM PDT 24
Finished Jul 24 05:29:53 PM PDT 24
Peak memory 206644 kb
Host smart-408bb421-cf5c-46a0-8d56-12de2f8118e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22329
5513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.223295513
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.1641306505
Short name T1750
Test name
Test status
Simulation time 221055055 ps
CPU time 0.85 seconds
Started Jul 24 05:29:47 PM PDT 24
Finished Jul 24 05:29:48 PM PDT 24
Peak memory 206660 kb
Host smart-c3bf3d2b-f960-4899-9d5b-12b062a33809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16413
06505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.1641306505
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.2342048087
Short name T2709
Test name
Test status
Simulation time 680032187 ps
CPU time 1.6 seconds
Started Jul 24 05:29:53 PM PDT 24
Finished Jul 24 05:29:54 PM PDT 24
Peak memory 206852 kb
Host smart-cbfb49d5-1988-4ba0-94b8-a3700072578b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23420
48087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.2342048087
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.116171862
Short name T681
Test name
Test status
Simulation time 5412594514 ps
CPU time 39.11 seconds
Started Jul 24 05:29:59 PM PDT 24
Finished Jul 24 05:30:39 PM PDT 24
Peak memory 206888 kb
Host smart-30b5ed5b-c49b-4fe4-8bad-54e4919d912c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11617
1862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.116171862
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.1791436211
Short name T1978
Test name
Test status
Simulation time 97527155 ps
CPU time 0.71 seconds
Started Jul 24 05:29:54 PM PDT 24
Finished Jul 24 05:29:55 PM PDT 24
Peak memory 206624 kb
Host smart-f797b74b-348a-4c35-a817-0244263df3f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1791436211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.1791436211
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.1548164702
Short name T1819
Test name
Test status
Simulation time 3446492255 ps
CPU time 4.37 seconds
Started Jul 24 05:29:45 PM PDT 24
Finished Jul 24 05:29:49 PM PDT 24
Peak memory 206928 kb
Host smart-7838d657-dd71-4e72-a1f8-013a617303b0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1548164702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.1548164702
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.2918709680
Short name T2076
Test name
Test status
Simulation time 13413775930 ps
CPU time 14.78 seconds
Started Jul 24 05:29:47 PM PDT 24
Finished Jul 24 05:30:02 PM PDT 24
Peak memory 206768 kb
Host smart-b7edaf17-783e-4171-bd0e-eb270af3c7db
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2918709680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.2918709680
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.1435622962
Short name T2684
Test name
Test status
Simulation time 23393229933 ps
CPU time 28.49 seconds
Started Jul 24 05:29:53 PM PDT 24
Finished Jul 24 05:30:22 PM PDT 24
Peak memory 206700 kb
Host smart-bd0a4674-34ca-4f36-92cd-80431fbb2302
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1435622962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.1435622962
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.2581166197
Short name T959
Test name
Test status
Simulation time 157687038 ps
CPU time 0.83 seconds
Started Jul 24 05:29:46 PM PDT 24
Finished Jul 24 05:29:47 PM PDT 24
Peak memory 206640 kb
Host smart-1abf69bc-573f-4620-bbdf-0d7a8b319538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25811
66197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.2581166197
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.2120697961
Short name T621
Test name
Test status
Simulation time 181267340 ps
CPU time 0.79 seconds
Started Jul 24 05:29:48 PM PDT 24
Finished Jul 24 05:29:49 PM PDT 24
Peak memory 206576 kb
Host smart-01aa06fa-f376-4a31-80a0-cdea027935f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21206
97961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.2120697961
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.130084337
Short name T2546
Test name
Test status
Simulation time 387111331 ps
CPU time 1.24 seconds
Started Jul 24 05:29:52 PM PDT 24
Finished Jul 24 05:29:54 PM PDT 24
Peak memory 206572 kb
Host smart-13eafd17-cb93-4546-bddb-ee8ffadab087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13008
4337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.130084337
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.690899225
Short name T2490
Test name
Test status
Simulation time 395830453 ps
CPU time 1.16 seconds
Started Jul 24 05:30:05 PM PDT 24
Finished Jul 24 05:30:06 PM PDT 24
Peak memory 206580 kb
Host smart-bd4df9fb-0f16-4cc2-a2ec-313fdb553c59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69089
9225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.690899225
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.3458499053
Short name T594
Test name
Test status
Simulation time 9734223179 ps
CPU time 18.64 seconds
Started Jul 24 05:29:48 PM PDT 24
Finished Jul 24 05:30:07 PM PDT 24
Peak memory 206912 kb
Host smart-d6f116fe-8251-4422-9d22-821b8739111c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34584
99053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.3458499053
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.4016050394
Short name T1852
Test name
Test status
Simulation time 450251433 ps
CPU time 1.31 seconds
Started Jul 24 05:29:50 PM PDT 24
Finished Jul 24 05:29:51 PM PDT 24
Peak memory 206472 kb
Host smart-481856ac-1968-4fc2-a13a-1ce99f87ee5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40160
50394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.4016050394
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.3172406950
Short name T2689
Test name
Test status
Simulation time 152207518 ps
CPU time 0.82 seconds
Started Jul 24 05:29:45 PM PDT 24
Finished Jul 24 05:29:46 PM PDT 24
Peak memory 206568 kb
Host smart-a1276507-fd58-433c-90e9-811c4d25860f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31724
06950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.3172406950
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.854935622
Short name T1644
Test name
Test status
Simulation time 42653259 ps
CPU time 0.68 seconds
Started Jul 24 05:29:38 PM PDT 24
Finished Jul 24 05:29:39 PM PDT 24
Peak memory 206384 kb
Host smart-b2e05170-cc7e-48a2-9f78-f284ad884f37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85493
5622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.854935622
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.1665673252
Short name T852
Test name
Test status
Simulation time 892424000 ps
CPU time 2.09 seconds
Started Jul 24 05:29:41 PM PDT 24
Finished Jul 24 05:29:43 PM PDT 24
Peak memory 206752 kb
Host smart-55e13a70-7927-44ea-86f7-c2af5ff6b305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16656
73252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.1665673252
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.308143422
Short name T1209
Test name
Test status
Simulation time 381011770 ps
CPU time 2.29 seconds
Started Jul 24 05:29:49 PM PDT 24
Finished Jul 24 05:29:51 PM PDT 24
Peak memory 206780 kb
Host smart-79f206aa-c60e-4fdf-a172-e06b5b01b0da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30814
3422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.308143422
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.3412726639
Short name T402
Test name
Test status
Simulation time 241961176 ps
CPU time 0.91 seconds
Started Jul 24 05:29:41 PM PDT 24
Finished Jul 24 05:29:42 PM PDT 24
Peak memory 206528 kb
Host smart-91821b2d-37f0-441d-a16c-a7e9444565d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34127
26639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.3412726639
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.3820132294
Short name T2450
Test name
Test status
Simulation time 150771971 ps
CPU time 0.75 seconds
Started Jul 24 05:29:54 PM PDT 24
Finished Jul 24 05:29:55 PM PDT 24
Peak memory 206552 kb
Host smart-db572ea8-ab69-4904-9c49-0121a7e333d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38201
32294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.3820132294
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.665825227
Short name T1496
Test name
Test status
Simulation time 185972942 ps
CPU time 0.82 seconds
Started Jul 24 05:29:56 PM PDT 24
Finished Jul 24 05:29:57 PM PDT 24
Peak memory 206580 kb
Host smart-928b081c-ddca-43e6-bccc-56ba77451d85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66582
5227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.665825227
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_iso_retraction.2833659522
Short name T1353
Test name
Test status
Simulation time 8016304830 ps
CPU time 69.92 seconds
Started Jul 24 05:29:37 PM PDT 24
Finished Jul 24 05:30:47 PM PDT 24
Peak memory 206876 kb
Host smart-807c834d-5a8d-414d-874e-bf41eb9465ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28336
59522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.2833659522
Directory /workspace/46.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.858566177
Short name T1324
Test name
Test status
Simulation time 239261710 ps
CPU time 0.86 seconds
Started Jul 24 05:29:53 PM PDT 24
Finished Jul 24 05:29:54 PM PDT 24
Peak memory 206580 kb
Host smart-e5b61480-89b2-49ef-b643-bb9655793d35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85856
6177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.858566177
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.854103363
Short name T1493
Test name
Test status
Simulation time 23271550188 ps
CPU time 23.5 seconds
Started Jul 24 05:29:56 PM PDT 24
Finished Jul 24 05:30:20 PM PDT 24
Peak memory 206700 kb
Host smart-564a5554-6375-4f19-b766-8f2deaba1efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85410
3363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.854103363
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.1840906119
Short name T686
Test name
Test status
Simulation time 3321953600 ps
CPU time 3.8 seconds
Started Jul 24 05:30:05 PM PDT 24
Finished Jul 24 05:30:09 PM PDT 24
Peak memory 206700 kb
Host smart-a1fd374a-0041-456f-9092-05455b760b0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18409
06119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.1840906119
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.1480053084
Short name T1890
Test name
Test status
Simulation time 7759224578 ps
CPU time 207.04 seconds
Started Jul 24 05:29:51 PM PDT 24
Finished Jul 24 05:33:19 PM PDT 24
Peak memory 206920 kb
Host smart-f045c2fa-1231-46ac-b5b0-308f42669412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14800
53084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.1480053084
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.1001077566
Short name T800
Test name
Test status
Simulation time 8024378593 ps
CPU time 235.36 seconds
Started Jul 24 05:29:57 PM PDT 24
Finished Jul 24 05:33:53 PM PDT 24
Peak memory 206860 kb
Host smart-1287cc9c-0814-4a54-895b-f7b20d63bda1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1001077566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.1001077566
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.3644052192
Short name T629
Test name
Test status
Simulation time 240299414 ps
CPU time 0.93 seconds
Started Jul 24 05:29:44 PM PDT 24
Finished Jul 24 05:29:45 PM PDT 24
Peak memory 206612 kb
Host smart-7f0327a7-2323-4a79-8d75-fe856aab7c3a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3644052192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.3644052192
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.3628199122
Short name T2322
Test name
Test status
Simulation time 188139772 ps
CPU time 0.84 seconds
Started Jul 24 05:30:01 PM PDT 24
Finished Jul 24 05:30:02 PM PDT 24
Peak memory 206516 kb
Host smart-8ef572b3-b212-4552-ad00-ee2017df6a43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36281
99122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.3628199122
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.3522860182
Short name T2743
Test name
Test status
Simulation time 6573743679 ps
CPU time 186.94 seconds
Started Jul 24 05:30:00 PM PDT 24
Finished Jul 24 05:33:08 PM PDT 24
Peak memory 206920 kb
Host smart-cc393b53-0550-4892-a2c1-e364a21204ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35228
60182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.3522860182
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.1791088725
Short name T304
Test name
Test status
Simulation time 5279361857 ps
CPU time 35.58 seconds
Started Jul 24 05:29:51 PM PDT 24
Finished Jul 24 05:30:26 PM PDT 24
Peak memory 206920 kb
Host smart-b6f8a32f-3156-4e01-bcc7-8a4dbe2d15d3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1791088725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.1791088725
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.2361292080
Short name T1548
Test name
Test status
Simulation time 148139092 ps
CPU time 0.75 seconds
Started Jul 24 05:29:44 PM PDT 24
Finished Jul 24 05:29:45 PM PDT 24
Peak memory 206572 kb
Host smart-1adf5f77-fec7-4a7f-8e8f-0c6b36863362
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2361292080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.2361292080
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.1594905326
Short name T1258
Test name
Test status
Simulation time 153107879 ps
CPU time 0.73 seconds
Started Jul 24 05:29:51 PM PDT 24
Finished Jul 24 05:29:52 PM PDT 24
Peak memory 206516 kb
Host smart-5ad3d33e-9793-4000-a8c6-1b1a35004c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15949
05326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.1594905326
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.3490032173
Short name T2392
Test name
Test status
Simulation time 205973284 ps
CPU time 0.85 seconds
Started Jul 24 05:29:45 PM PDT 24
Finished Jul 24 05:29:46 PM PDT 24
Peak memory 206596 kb
Host smart-155fc76e-5866-4e5e-b03f-87f037dd855a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34900
32173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.3490032173
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.188901634
Short name T92
Test name
Test status
Simulation time 164720630 ps
CPU time 0.85 seconds
Started Jul 24 05:29:48 PM PDT 24
Finished Jul 24 05:29:49 PM PDT 24
Peak memory 206628 kb
Host smart-0a6d674f-0442-46fb-b254-41393cfe628f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18890
1634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.188901634
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.1835538771
Short name T2195
Test name
Test status
Simulation time 179588727 ps
CPU time 0.78 seconds
Started Jul 24 05:30:03 PM PDT 24
Finished Jul 24 05:30:04 PM PDT 24
Peak memory 206508 kb
Host smart-a928f50f-e12b-413a-99ca-59ae582dec81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18355
38771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.1835538771
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.3638518852
Short name T2127
Test name
Test status
Simulation time 209930337 ps
CPU time 0.77 seconds
Started Jul 24 05:29:39 PM PDT 24
Finished Jul 24 05:29:40 PM PDT 24
Peak memory 206548 kb
Host smart-3b6f7981-50f6-4d43-9370-a511d0add2ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36385
18852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.3638518852
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.1050081144
Short name T2484
Test name
Test status
Simulation time 157800076 ps
CPU time 0.79 seconds
Started Jul 24 05:29:57 PM PDT 24
Finished Jul 24 05:29:59 PM PDT 24
Peak memory 206464 kb
Host smart-76ac34f7-9893-4d7b-a163-2c02bb576870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10500
81144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.1050081144
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.2743624226
Short name T650
Test name
Test status
Simulation time 206447575 ps
CPU time 0.83 seconds
Started Jul 24 05:29:47 PM PDT 24
Finished Jul 24 05:29:48 PM PDT 24
Peak memory 206576 kb
Host smart-d40c8ca2-8e6a-4f90-9763-8136948cd6f6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2743624226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.2743624226
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.1663809772
Short name T2574
Test name
Test status
Simulation time 170857670 ps
CPU time 0.81 seconds
Started Jul 24 05:30:00 PM PDT 24
Finished Jul 24 05:30:01 PM PDT 24
Peak memory 206564 kb
Host smart-37374e3a-6f33-4487-a7ea-48bd8dd45055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16638
09772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.1663809772
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.1433663300
Short name T1403
Test name
Test status
Simulation time 49511196 ps
CPU time 0.67 seconds
Started Jul 24 05:29:47 PM PDT 24
Finished Jul 24 05:29:48 PM PDT 24
Peak memory 206596 kb
Host smart-bf991ec4-f2f9-42bc-94cd-0b8ca4433c10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14336
63300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.1433663300
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.1989873440
Short name T787
Test name
Test status
Simulation time 19668083677 ps
CPU time 43.79 seconds
Started Jul 24 05:29:47 PM PDT 24
Finished Jul 24 05:30:31 PM PDT 24
Peak memory 206928 kb
Host smart-dc251cd2-96f5-4a6c-ad34-e82c7e650a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19898
73440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.1989873440
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.994640798
Short name T698
Test name
Test status
Simulation time 197402963 ps
CPU time 0.88 seconds
Started Jul 24 05:29:57 PM PDT 24
Finished Jul 24 05:29:58 PM PDT 24
Peak memory 206552 kb
Host smart-94e94a24-7f9d-4af5-a733-8c0ec2aed00d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99464
0798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.994640798
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.2226971513
Short name T2556
Test name
Test status
Simulation time 251513975 ps
CPU time 0.88 seconds
Started Jul 24 05:29:56 PM PDT 24
Finished Jul 24 05:29:57 PM PDT 24
Peak memory 206608 kb
Host smart-118fb53e-8613-4d69-9b92-e2e05e0eb6cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22269
71513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.2226971513
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.304920848
Short name T1462
Test name
Test status
Simulation time 244367287 ps
CPU time 0.87 seconds
Started Jul 24 05:30:00 PM PDT 24
Finished Jul 24 05:30:01 PM PDT 24
Peak memory 206584 kb
Host smart-13c2f382-245a-44e0-830b-766960a37134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30492
0848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.304920848
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.3072020359
Short name T1875
Test name
Test status
Simulation time 152049639 ps
CPU time 0.75 seconds
Started Jul 24 05:29:50 PM PDT 24
Finished Jul 24 05:29:51 PM PDT 24
Peak memory 206556 kb
Host smart-536a0a7e-8742-4316-9ce3-7664ef3b1223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30720
20359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.3072020359
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.1592047355
Short name T1458
Test name
Test status
Simulation time 171948992 ps
CPU time 0.82 seconds
Started Jul 24 05:29:50 PM PDT 24
Finished Jul 24 05:29:51 PM PDT 24
Peak memory 206624 kb
Host smart-9fde6c46-7fa3-4309-90bb-00a6e4fd1332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15920
47355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.1592047355
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.1251954893
Short name T107
Test name
Test status
Simulation time 150349201 ps
CPU time 0.76 seconds
Started Jul 24 05:29:52 PM PDT 24
Finished Jul 24 05:29:53 PM PDT 24
Peak memory 206576 kb
Host smart-e21c990f-0df3-4f04-897d-3e5a07ada56f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12519
54893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.1251954893
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.1635409874
Short name T865
Test name
Test status
Simulation time 149843680 ps
CPU time 0.74 seconds
Started Jul 24 05:29:59 PM PDT 24
Finished Jul 24 05:30:00 PM PDT 24
Peak memory 206588 kb
Host smart-e4aba8fd-9ec4-4471-bafb-9834cbdf4a2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16354
09874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.1635409874
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.2203813503
Short name T638
Test name
Test status
Simulation time 207193450 ps
CPU time 0.88 seconds
Started Jul 24 05:30:00 PM PDT 24
Finished Jul 24 05:30:01 PM PDT 24
Peak memory 206592 kb
Host smart-b0c49fc9-0201-4359-a84b-57727a222ec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22038
13503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.2203813503
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.3432224541
Short name T529
Test name
Test status
Simulation time 5983291630 ps
CPU time 56.98 seconds
Started Jul 24 05:29:43 PM PDT 24
Finished Jul 24 05:30:40 PM PDT 24
Peak memory 206856 kb
Host smart-b1e29974-1032-44af-b038-e11a78b0b4b5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3432224541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.3432224541
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.4261963992
Short name T1976
Test name
Test status
Simulation time 168346303 ps
CPU time 0.81 seconds
Started Jul 24 05:29:44 PM PDT 24
Finished Jul 24 05:29:45 PM PDT 24
Peak memory 206528 kb
Host smart-f7675c54-6e8c-4c27-bfdf-686a21d68c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42619
63992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.4261963992
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.2873441156
Short name T2331
Test name
Test status
Simulation time 162627747 ps
CPU time 0.8 seconds
Started Jul 24 05:30:03 PM PDT 24
Finished Jul 24 05:30:04 PM PDT 24
Peak memory 206540 kb
Host smart-034dda03-2459-4309-ac10-f3d1ec2e4619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28734
41156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.2873441156
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.2525340632
Short name T2745
Test name
Test status
Simulation time 464058224 ps
CPU time 1.29 seconds
Started Jul 24 05:29:53 PM PDT 24
Finished Jul 24 05:29:55 PM PDT 24
Peak memory 206592 kb
Host smart-de897164-fdd8-44a3-9cc6-794be9575fbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25253
40632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.2525340632
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.3840161584
Short name T1094
Test name
Test status
Simulation time 4265876645 ps
CPU time 29.14 seconds
Started Jul 24 05:29:55 PM PDT 24
Finished Jul 24 05:30:25 PM PDT 24
Peak memory 206868 kb
Host smart-c255c213-d64c-403c-8ce8-4fe2f261bcda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38401
61584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.3840161584
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.614390034
Short name T556
Test name
Test status
Simulation time 72081872 ps
CPU time 0.67 seconds
Started Jul 24 05:30:16 PM PDT 24
Finished Jul 24 05:30:17 PM PDT 24
Peak memory 206616 kb
Host smart-6cbab4be-79bc-4608-bbd4-6da193f44d40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=614390034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.614390034
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.3746062071
Short name T1758
Test name
Test status
Simulation time 4057929267 ps
CPU time 4.87 seconds
Started Jul 24 05:29:56 PM PDT 24
Finished Jul 24 05:30:01 PM PDT 24
Peak memory 206712 kb
Host smart-ccfd15d3-81e6-4f6b-a1ba-b19fafe5bf9c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3746062071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.3746062071
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.2712450696
Short name T712
Test name
Test status
Simulation time 13363148856 ps
CPU time 12.58 seconds
Started Jul 24 05:30:01 PM PDT 24
Finished Jul 24 05:30:13 PM PDT 24
Peak memory 206968 kb
Host smart-f97daa4e-1564-4ca8-b607-2c0a807d9f34
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2712450696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.2712450696
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.1202575050
Short name T1915
Test name
Test status
Simulation time 150478848 ps
CPU time 0.77 seconds
Started Jul 24 05:29:51 PM PDT 24
Finished Jul 24 05:29:52 PM PDT 24
Peak memory 206568 kb
Host smart-79231583-aab5-4588-be73-eea55e83926c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12025
75050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.1202575050
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.337621916
Short name T1984
Test name
Test status
Simulation time 174794239 ps
CPU time 0.78 seconds
Started Jul 24 05:29:58 PM PDT 24
Finished Jul 24 05:29:59 PM PDT 24
Peak memory 206512 kb
Host smart-081ecd71-a2bd-49e3-b627-50bc15c5af37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33762
1916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.337621916
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.534225698
Short name T2025
Test name
Test status
Simulation time 244816271 ps
CPU time 0.96 seconds
Started Jul 24 05:29:38 PM PDT 24
Finished Jul 24 05:29:39 PM PDT 24
Peak memory 206592 kb
Host smart-ec0db721-4ba2-41f7-bc8a-417cec349a15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53422
5698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.534225698
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.4088515965
Short name T2693
Test name
Test status
Simulation time 933901209 ps
CPU time 2.1 seconds
Started Jul 24 05:29:57 PM PDT 24
Finished Jul 24 05:30:00 PM PDT 24
Peak memory 206756 kb
Host smart-e61f4d1e-1e93-45b1-93ca-4c862ddf90bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40885
15965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.4088515965
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.2644615927
Short name T1451
Test name
Test status
Simulation time 22627452117 ps
CPU time 39.02 seconds
Started Jul 24 05:29:59 PM PDT 24
Finished Jul 24 05:30:38 PM PDT 24
Peak memory 206776 kb
Host smart-4c6981b7-527a-44ae-9ca0-06838a8d40fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26446
15927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.2644615927
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.2018088270
Short name T2225
Test name
Test status
Simulation time 336018146 ps
CPU time 1.21 seconds
Started Jul 24 05:29:57 PM PDT 24
Finished Jul 24 05:29:58 PM PDT 24
Peak memory 206600 kb
Host smart-d46b2f20-235e-456a-9583-eb7deed9d06f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20180
88270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.2018088270
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.2084442838
Short name T751
Test name
Test status
Simulation time 137046123 ps
CPU time 0.75 seconds
Started Jul 24 05:30:05 PM PDT 24
Finished Jul 24 05:30:06 PM PDT 24
Peak memory 206540 kb
Host smart-9cef445f-963a-4171-98f2-1f8be9de0923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20844
42838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.2084442838
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.3468384620
Short name T2269
Test name
Test status
Simulation time 40513309 ps
CPU time 0.65 seconds
Started Jul 24 05:29:52 PM PDT 24
Finished Jul 24 05:29:53 PM PDT 24
Peak memory 206584 kb
Host smart-fc2bd2af-57e3-4192-baec-926656e32c6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34683
84620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.3468384620
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.3647504206
Short name T2710
Test name
Test status
Simulation time 991335226 ps
CPU time 2.26 seconds
Started Jul 24 05:30:04 PM PDT 24
Finished Jul 24 05:30:07 PM PDT 24
Peak memory 206716 kb
Host smart-26f77ece-2f10-4142-80ae-a2e1124c0bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36475
04206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.3647504206
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.3980673265
Short name T2544
Test name
Test status
Simulation time 256630899 ps
CPU time 1.59 seconds
Started Jul 24 05:29:55 PM PDT 24
Finished Jul 24 05:29:57 PM PDT 24
Peak memory 206836 kb
Host smart-be020a64-9a60-4c2d-a9a4-cf48ca232452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39806
73265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.3980673265
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.2848107780
Short name T1076
Test name
Test status
Simulation time 170781374 ps
CPU time 0.8 seconds
Started Jul 24 05:29:54 PM PDT 24
Finished Jul 24 05:29:55 PM PDT 24
Peak memory 206600 kb
Host smart-d33680b5-c782-4de8-abaa-ddf0bfd3a146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28481
07780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.2848107780
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.929732984
Short name T2665
Test name
Test status
Simulation time 153137949 ps
CPU time 0.78 seconds
Started Jul 24 05:30:06 PM PDT 24
Finished Jul 24 05:30:07 PM PDT 24
Peak memory 206548 kb
Host smart-250f371b-c340-4b92-a1ce-1de78f96aa3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92973
2984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.929732984
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.2326524875
Short name T2273
Test name
Test status
Simulation time 232206065 ps
CPU time 0.91 seconds
Started Jul 24 05:30:04 PM PDT 24
Finished Jul 24 05:30:05 PM PDT 24
Peak memory 206592 kb
Host smart-199d5842-7dbc-4901-b156-9bfad6ec295a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23265
24875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.2326524875
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.2847631995
Short name T2261
Test name
Test status
Simulation time 10656695060 ps
CPU time 297.1 seconds
Started Jul 24 05:29:49 PM PDT 24
Finished Jul 24 05:34:46 PM PDT 24
Peak memory 206984 kb
Host smart-2ecdd4d8-19c2-4999-8d2d-06b2a5deecd7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2847631995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.2847631995
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_iso_retraction.1190435943
Short name T2371
Test name
Test status
Simulation time 11589756744 ps
CPU time 105.34 seconds
Started Jul 24 05:29:48 PM PDT 24
Finished Jul 24 05:31:34 PM PDT 24
Peak memory 206912 kb
Host smart-ffe132b6-496a-46a5-a8bb-3300040938c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11904
35943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.1190435943
Directory /workspace/47.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.4285050986
Short name T1291
Test name
Test status
Simulation time 226806342 ps
CPU time 0.84 seconds
Started Jul 24 05:29:51 PM PDT 24
Finished Jul 24 05:29:52 PM PDT 24
Peak memory 206588 kb
Host smart-12158593-7337-4ebe-9fd0-7acde561c127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42850
50986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.4285050986
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.865316640
Short name T1038
Test name
Test status
Simulation time 23304325538 ps
CPU time 22.69 seconds
Started Jul 24 05:30:12 PM PDT 24
Finished Jul 24 05:30:35 PM PDT 24
Peak memory 206680 kb
Host smart-18b18cc5-1465-4a90-8297-fccaec2a88bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86531
6640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.865316640
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.2773839998
Short name T1958
Test name
Test status
Simulation time 3317449966 ps
CPU time 4.16 seconds
Started Jul 24 05:29:54 PM PDT 24
Finished Jul 24 05:29:58 PM PDT 24
Peak memory 206700 kb
Host smart-80faf297-c6da-487a-8f87-9f1f632153a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27738
39998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.2773839998
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.1139238394
Short name T515
Test name
Test status
Simulation time 12749459244 ps
CPU time 95.74 seconds
Started Jul 24 05:30:09 PM PDT 24
Finished Jul 24 05:31:45 PM PDT 24
Peak memory 206948 kb
Host smart-2ca66044-7444-4162-a119-c31d0b9e878b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11392
38394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.1139238394
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.2490757153
Short name T1689
Test name
Test status
Simulation time 4948887530 ps
CPU time 136.87 seconds
Started Jul 24 05:29:57 PM PDT 24
Finished Jul 24 05:32:14 PM PDT 24
Peak memory 206852 kb
Host smart-eb128117-1a17-4474-9540-9390a1dd4803
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2490757153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.2490757153
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.3459394827
Short name T323
Test name
Test status
Simulation time 244389708 ps
CPU time 0.9 seconds
Started Jul 24 05:29:59 PM PDT 24
Finished Jul 24 05:30:00 PM PDT 24
Peak memory 206588 kb
Host smart-251c0516-8374-4976-ba65-8cc081e9e4bc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3459394827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.3459394827
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.2659776911
Short name T2017
Test name
Test status
Simulation time 192152112 ps
CPU time 0.84 seconds
Started Jul 24 05:30:00 PM PDT 24
Finished Jul 24 05:30:01 PM PDT 24
Peak memory 206532 kb
Host smart-4e616298-d8f2-488d-98ae-4cc9f16a20ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26597
76911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.2659776911
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.804004740
Short name T2328
Test name
Test status
Simulation time 5474086547 ps
CPU time 152.66 seconds
Started Jul 24 05:29:56 PM PDT 24
Finished Jul 24 05:32:29 PM PDT 24
Peak memory 206944 kb
Host smart-6905cd83-0415-4778-b248-d77f6d518f78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80400
4740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.804004740
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.2820295774
Short name T887
Test name
Test status
Simulation time 5298782585 ps
CPU time 143.29 seconds
Started Jul 24 05:29:57 PM PDT 24
Finished Jul 24 05:32:21 PM PDT 24
Peak memory 206888 kb
Host smart-04325038-9936-43fe-820a-91f45c956995
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2820295774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.2820295774
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.1613163147
Short name T2666
Test name
Test status
Simulation time 205101202 ps
CPU time 0.86 seconds
Started Jul 24 05:29:58 PM PDT 24
Finished Jul 24 05:29:59 PM PDT 24
Peak memory 206620 kb
Host smart-e49fa05d-958f-411c-948f-36eb00665d37
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1613163147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.1613163147
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.4187151462
Short name T635
Test name
Test status
Simulation time 169897278 ps
CPU time 0.78 seconds
Started Jul 24 05:30:04 PM PDT 24
Finished Jul 24 05:30:05 PM PDT 24
Peak memory 206616 kb
Host smart-3e20a646-b0e8-447e-8763-3999e8554680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41871
51462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.4187151462
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.1496351013
Short name T128
Test name
Test status
Simulation time 232553603 ps
CPU time 0.88 seconds
Started Jul 24 05:30:05 PM PDT 24
Finished Jul 24 05:30:06 PM PDT 24
Peak memory 206640 kb
Host smart-ef20a523-bcc8-4427-bf77-42a14fb869d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14963
51013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.1496351013
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.2025309466
Short name T749
Test name
Test status
Simulation time 187970207 ps
CPU time 0.88 seconds
Started Jul 24 05:29:53 PM PDT 24
Finished Jul 24 05:29:54 PM PDT 24
Peak memory 206620 kb
Host smart-0b64274e-cd7f-47a3-82ba-74928f59ba48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20253
09466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.2025309466
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.3722870084
Short name T1316
Test name
Test status
Simulation time 161232372 ps
CPU time 0.81 seconds
Started Jul 24 05:30:07 PM PDT 24
Finished Jul 24 05:30:08 PM PDT 24
Peak memory 206556 kb
Host smart-035c50b9-d1cd-457a-bb64-a94bc7f00623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37228
70084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.3722870084
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.1585246310
Short name T980
Test name
Test status
Simulation time 145652543 ps
CPU time 0.76 seconds
Started Jul 24 05:30:00 PM PDT 24
Finished Jul 24 05:30:01 PM PDT 24
Peak memory 206580 kb
Host smart-12810b61-1984-4abd-9d5e-053d744ce85b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15852
46310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.1585246310
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.2307465101
Short name T2111
Test name
Test status
Simulation time 173021666 ps
CPU time 0.81 seconds
Started Jul 24 05:30:11 PM PDT 24
Finished Jul 24 05:30:12 PM PDT 24
Peak memory 206608 kb
Host smart-401df4c1-ba24-4f87-92f1-9893d9671a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23074
65101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.2307465101
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.4262012169
Short name T332
Test name
Test status
Simulation time 210781160 ps
CPU time 0.9 seconds
Started Jul 24 05:29:56 PM PDT 24
Finished Jul 24 05:29:58 PM PDT 24
Peak memory 206580 kb
Host smart-d8116a1e-b5b2-4021-b2b4-01b2eb6152f1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4262012169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.4262012169
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.3705322128
Short name T839
Test name
Test status
Simulation time 156414434 ps
CPU time 0.78 seconds
Started Jul 24 05:30:07 PM PDT 24
Finished Jul 24 05:30:08 PM PDT 24
Peak memory 206600 kb
Host smart-05ef62be-e274-4c62-be8e-aebe47f1c30a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37053
22128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.3705322128
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.2081301536
Short name T1896
Test name
Test status
Simulation time 36891871 ps
CPU time 0.73 seconds
Started Jul 24 05:29:57 PM PDT 24
Finished Jul 24 05:29:58 PM PDT 24
Peak memory 206584 kb
Host smart-f9684d68-4560-4f5b-b5e4-588b2264670c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20813
01536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.2081301536
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.2198929749
Short name T242
Test name
Test status
Simulation time 13887380257 ps
CPU time 28.25 seconds
Started Jul 24 05:29:56 PM PDT 24
Finished Jul 24 05:30:24 PM PDT 24
Peak memory 206996 kb
Host smart-1c2d69c9-aac8-4aa9-9928-2b15d2de223f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21989
29749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.2198929749
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.2686663753
Short name T1047
Test name
Test status
Simulation time 184114753 ps
CPU time 0.82 seconds
Started Jul 24 05:30:11 PM PDT 24
Finished Jul 24 05:30:12 PM PDT 24
Peak memory 206604 kb
Host smart-8cd2ae0c-784a-44c8-a211-539bc4764ac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26866
63753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.2686663753
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.3604076764
Short name T1885
Test name
Test status
Simulation time 235948468 ps
CPU time 0.89 seconds
Started Jul 24 05:29:59 PM PDT 24
Finished Jul 24 05:30:00 PM PDT 24
Peak memory 206572 kb
Host smart-3fb642ad-6bbf-430c-ab7e-8d1ebbb1fb74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36040
76764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.3604076764
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.374754105
Short name T1959
Test name
Test status
Simulation time 214099373 ps
CPU time 0.91 seconds
Started Jul 24 05:30:08 PM PDT 24
Finished Jul 24 05:30:09 PM PDT 24
Peak memory 206560 kb
Host smart-3a63e852-a4ab-45e2-9db2-49559657849e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37475
4105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.374754105
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.3651276751
Short name T1557
Test name
Test status
Simulation time 207152815 ps
CPU time 0.85 seconds
Started Jul 24 05:30:21 PM PDT 24
Finished Jul 24 05:30:22 PM PDT 24
Peak memory 206392 kb
Host smart-94a187d6-d8f8-41da-b00e-eda3bdfc8d09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36512
76751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.3651276751
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.1031716548
Short name T1187
Test name
Test status
Simulation time 180667488 ps
CPU time 0.8 seconds
Started Jul 24 05:29:51 PM PDT 24
Finished Jul 24 05:29:52 PM PDT 24
Peak memory 206584 kb
Host smart-f1850b15-03b8-4a06-9ebe-dd061fbb4332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10317
16548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.1031716548
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.2611530233
Short name T2694
Test name
Test status
Simulation time 151253465 ps
CPU time 0.75 seconds
Started Jul 24 05:30:20 PM PDT 24
Finished Jul 24 05:30:21 PM PDT 24
Peak memory 206524 kb
Host smart-7213b3ff-a358-420e-8c00-0b8af469e96d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26115
30233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.2611530233
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.1976447776
Short name T2206
Test name
Test status
Simulation time 152329846 ps
CPU time 0.75 seconds
Started Jul 24 05:29:58 PM PDT 24
Finished Jul 24 05:29:59 PM PDT 24
Peak memory 206584 kb
Host smart-8333ad71-bd3f-4bc4-8a39-6a619a0a413f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19764
47776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.1976447776
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.1964690795
Short name T2580
Test name
Test status
Simulation time 240505965 ps
CPU time 0.97 seconds
Started Jul 24 05:30:04 PM PDT 24
Finished Jul 24 05:30:05 PM PDT 24
Peak memory 206592 kb
Host smart-21a35f85-61f0-4342-a4c8-7d6d5c24a9f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19646
90795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.1964690795
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.265254203
Short name T1894
Test name
Test status
Simulation time 4382639521 ps
CPU time 32.01 seconds
Started Jul 24 05:30:09 PM PDT 24
Finished Jul 24 05:30:41 PM PDT 24
Peak memory 206924 kb
Host smart-2360df22-4880-4def-b450-471c605d1112
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=265254203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.265254203
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.1397992776
Short name T398
Test name
Test status
Simulation time 212450274 ps
CPU time 0.85 seconds
Started Jul 24 05:29:58 PM PDT 24
Finished Jul 24 05:29:59 PM PDT 24
Peak memory 206580 kb
Host smart-cc73d2a2-fd6c-4feb-b149-8c6d3f4e77f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13979
92776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.1397992776
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.2728188186
Short name T630
Test name
Test status
Simulation time 192079098 ps
CPU time 0.79 seconds
Started Jul 24 05:30:18 PM PDT 24
Finished Jul 24 05:30:19 PM PDT 24
Peak memory 206616 kb
Host smart-0f88b3f0-efe0-4e81-a140-de90755d6199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27281
88186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.2728188186
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.2374035884
Short name T1520
Test name
Test status
Simulation time 498625526 ps
CPU time 1.27 seconds
Started Jul 24 05:29:56 PM PDT 24
Finished Jul 24 05:29:58 PM PDT 24
Peak memory 206588 kb
Host smart-214f0a88-1d3c-4436-b7c9-312252e24868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23740
35884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.2374035884
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.317017060
Short name T1180
Test name
Test status
Simulation time 5819682985 ps
CPU time 53.59 seconds
Started Jul 24 05:30:10 PM PDT 24
Finished Jul 24 05:31:04 PM PDT 24
Peak memory 206908 kb
Host smart-0d60b4be-836d-45f0-b120-48e2bb0ef420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31701
7060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.317017060
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.995100521
Short name T728
Test name
Test status
Simulation time 59255808 ps
CPU time 0.69 seconds
Started Jul 24 05:30:11 PM PDT 24
Finished Jul 24 05:30:12 PM PDT 24
Peak memory 206616 kb
Host smart-a305e66c-f5e6-45bc-8583-17a8877a6f6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=995100521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.995100521
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.2725262466
Short name T446
Test name
Test status
Simulation time 3763902837 ps
CPU time 4.39 seconds
Started Jul 24 05:30:40 PM PDT 24
Finished Jul 24 05:30:44 PM PDT 24
Peak memory 206924 kb
Host smart-e57184e3-d409-4692-9b48-8c30b0b54082
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2725262466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.2725262466
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.2005374683
Short name T2581
Test name
Test status
Simulation time 13333265080 ps
CPU time 11.77 seconds
Started Jul 24 05:30:05 PM PDT 24
Finished Jul 24 05:30:17 PM PDT 24
Peak memory 206972 kb
Host smart-b3a301e0-1a96-4d89-b451-4242ccc30a1f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2005374683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.2005374683
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.496553869
Short name T1731
Test name
Test status
Simulation time 23389220939 ps
CPU time 26.42 seconds
Started Jul 24 05:29:55 PM PDT 24
Finished Jul 24 05:30:22 PM PDT 24
Peak memory 206684 kb
Host smart-68b0bf6b-974e-434b-9618-a13c88bce8aa
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=496553869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.496553869
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.702745819
Short name T1224
Test name
Test status
Simulation time 183058482 ps
CPU time 0.84 seconds
Started Jul 24 05:29:57 PM PDT 24
Finished Jul 24 05:29:59 PM PDT 24
Peak memory 206640 kb
Host smart-939acdd2-2bf7-4fc3-90fd-a3c5d7851e7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70274
5819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.702745819
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.946157677
Short name T1237
Test name
Test status
Simulation time 159493976 ps
CPU time 0.75 seconds
Started Jul 24 05:30:05 PM PDT 24
Finished Jul 24 05:30:06 PM PDT 24
Peak memory 206548 kb
Host smart-462c47ab-2e84-4d66-bdb9-ed7d82e6beef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94615
7677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.946157677
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.1153376753
Short name T579
Test name
Test status
Simulation time 465002380 ps
CPU time 1.45 seconds
Started Jul 24 05:29:57 PM PDT 24
Finished Jul 24 05:29:59 PM PDT 24
Peak memory 206832 kb
Host smart-dcb46c69-b460-4808-8031-1cf7a57ac453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11533
76753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.1153376753
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.1173957756
Short name T1144
Test name
Test status
Simulation time 1143009941 ps
CPU time 2.5 seconds
Started Jul 24 05:30:04 PM PDT 24
Finished Jul 24 05:30:07 PM PDT 24
Peak memory 206624 kb
Host smart-e75918b7-c172-4bc1-a817-22de515c9463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11739
57756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.1173957756
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.2333218911
Short name T1738
Test name
Test status
Simulation time 10371542364 ps
CPU time 19.26 seconds
Started Jul 24 05:29:53 PM PDT 24
Finished Jul 24 05:30:12 PM PDT 24
Peak memory 206844 kb
Host smart-f7b4393b-ac92-4733-86a2-a29329a26dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23332
18911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.2333218911
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.1381023268
Short name T2508
Test name
Test status
Simulation time 380589926 ps
CPU time 1.31 seconds
Started Jul 24 05:29:55 PM PDT 24
Finished Jul 24 05:29:56 PM PDT 24
Peak memory 206608 kb
Host smart-bc9a7073-2f73-4444-a825-caad9b914b78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13810
23268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.1381023268
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.4218849994
Short name T1245
Test name
Test status
Simulation time 194097727 ps
CPU time 0.83 seconds
Started Jul 24 05:29:59 PM PDT 24
Finished Jul 24 05:30:00 PM PDT 24
Peak memory 206556 kb
Host smart-a45849f3-6088-4fd0-9cf0-d2ace379b698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42188
49994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.4218849994
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.316763410
Short name T484
Test name
Test status
Simulation time 42221350 ps
CPU time 0.68 seconds
Started Jul 24 05:29:52 PM PDT 24
Finished Jul 24 05:29:53 PM PDT 24
Peak memory 206588 kb
Host smart-78b19d7d-c03b-42a7-b213-38fce1a69b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31676
3410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.316763410
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.4231246248
Short name T478
Test name
Test status
Simulation time 944888661 ps
CPU time 2.25 seconds
Started Jul 24 05:30:05 PM PDT 24
Finished Jul 24 05:30:08 PM PDT 24
Peak memory 206764 kb
Host smart-c5d0ed50-5a5b-486f-bf0f-1fb22d871668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42312
46248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.4231246248
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.2506207046
Short name T1498
Test name
Test status
Simulation time 162595505 ps
CPU time 1.42 seconds
Started Jul 24 05:30:00 PM PDT 24
Finished Jul 24 05:30:02 PM PDT 24
Peak memory 206704 kb
Host smart-7e850fc9-c1e0-4ea1-b821-51f268e828bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25062
07046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.2506207046
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.1536092781
Short name T2517
Test name
Test status
Simulation time 181140041 ps
CPU time 0.85 seconds
Started Jul 24 05:30:06 PM PDT 24
Finished Jul 24 05:30:07 PM PDT 24
Peak memory 206504 kb
Host smart-2bbaaea2-0040-455a-ac15-8bd9dfc8ea61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15360
92781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.1536092781
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.858661589
Short name T314
Test name
Test status
Simulation time 139968816 ps
CPU time 0.72 seconds
Started Jul 24 05:29:55 PM PDT 24
Finished Jul 24 05:29:55 PM PDT 24
Peak memory 206524 kb
Host smart-e550e1b6-0f34-4e5a-a7e6-67e2b5a3e417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85866
1589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.858661589
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.1363538291
Short name T2117
Test name
Test status
Simulation time 230849175 ps
CPU time 0.87 seconds
Started Jul 24 05:29:54 PM PDT 24
Finished Jul 24 05:29:55 PM PDT 24
Peak memory 206576 kb
Host smart-c7f8731b-3776-4ddf-8d28-13ac664f3783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13635
38291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.1363538291
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_iso_retraction.1834998708
Short name T488
Test name
Test status
Simulation time 5636105758 ps
CPU time 21.44 seconds
Started Jul 24 05:29:56 PM PDT 24
Finished Jul 24 05:30:17 PM PDT 24
Peak memory 206992 kb
Host smart-f2788324-d5e6-4798-baad-6b63f9e31e0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18349
98708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_iso_retraction.1834998708
Directory /workspace/48.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.581799123
Short name T365
Test name
Test status
Simulation time 194369210 ps
CPU time 0.87 seconds
Started Jul 24 05:29:59 PM PDT 24
Finished Jul 24 05:30:00 PM PDT 24
Peak memory 206596 kb
Host smart-da22193a-ca3c-4e72-a93c-58515473f19f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58179
9123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.581799123
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.2805802544
Short name T2173
Test name
Test status
Simulation time 23380119303 ps
CPU time 23.66 seconds
Started Jul 24 05:30:03 PM PDT 24
Finished Jul 24 05:30:27 PM PDT 24
Peak memory 206764 kb
Host smart-da92cfcd-b623-42ef-b092-6f47c0883b7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28058
02544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.2805802544
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.1612301567
Short name T1026
Test name
Test status
Simulation time 3368361513 ps
CPU time 3.66 seconds
Started Jul 24 05:30:04 PM PDT 24
Finished Jul 24 05:30:08 PM PDT 24
Peak memory 206552 kb
Host smart-07da5bb5-ebc5-4139-a5f7-dcbc7ef724f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16123
01567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.1612301567
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.3657715803
Short name T223
Test name
Test status
Simulation time 7447172357 ps
CPU time 56 seconds
Started Jul 24 05:30:16 PM PDT 24
Finished Jul 24 05:31:13 PM PDT 24
Peak memory 215096 kb
Host smart-0ed35e4f-5463-490f-8168-ebb9e0c70788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36577
15803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.3657715803
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.796009407
Short name T1704
Test name
Test status
Simulation time 4716896434 ps
CPU time 41.27 seconds
Started Jul 24 05:30:06 PM PDT 24
Finished Jul 24 05:30:47 PM PDT 24
Peak memory 206840 kb
Host smart-731aa920-492a-4e42-ade4-f02d0587ad67
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=796009407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.796009407
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.1790803513
Short name T417
Test name
Test status
Simulation time 247619561 ps
CPU time 1.03 seconds
Started Jul 24 05:30:12 PM PDT 24
Finished Jul 24 05:30:13 PM PDT 24
Peak memory 206600 kb
Host smart-b6daa0be-5289-4c46-8905-4911855b4610
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1790803513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.1790803513
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.1870622498
Short name T1030
Test name
Test status
Simulation time 182922759 ps
CPU time 0.87 seconds
Started Jul 24 05:29:55 PM PDT 24
Finished Jul 24 05:30:01 PM PDT 24
Peak memory 206556 kb
Host smart-a46db0c5-1a57-4de4-b118-5cee2407273c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18706
22498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.1870622498
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.2391626398
Short name T1449
Test name
Test status
Simulation time 5666819530 ps
CPU time 156.17 seconds
Started Jul 24 05:29:58 PM PDT 24
Finished Jul 24 05:32:34 PM PDT 24
Peak memory 206872 kb
Host smart-300ee26b-14c7-4e75-9428-3bb7cd54817d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23916
26398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.2391626398
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.2063891394
Short name T1374
Test name
Test status
Simulation time 4461261927 ps
CPU time 30.34 seconds
Started Jul 24 05:30:15 PM PDT 24
Finished Jul 24 05:30:46 PM PDT 24
Peak memory 206896 kb
Host smart-6bb7aba9-0c6f-433f-8abb-f7f16112fbd7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2063891394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.2063891394
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.1038547020
Short name T345
Test name
Test status
Simulation time 204882297 ps
CPU time 0.86 seconds
Started Jul 24 05:30:17 PM PDT 24
Finished Jul 24 05:30:18 PM PDT 24
Peak memory 206600 kb
Host smart-5c9d7eb6-131c-438f-b834-844c21b4b31e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1038547020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.1038547020
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.2170231178
Short name T1720
Test name
Test status
Simulation time 162819099 ps
CPU time 0.77 seconds
Started Jul 24 05:29:57 PM PDT 24
Finished Jul 24 05:29:58 PM PDT 24
Peak memory 206556 kb
Host smart-e0bc13fe-f04c-4f97-b470-a180baf43623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21702
31178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.2170231178
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.534008347
Short name T2411
Test name
Test status
Simulation time 197998661 ps
CPU time 0.86 seconds
Started Jul 24 05:30:09 PM PDT 24
Finished Jul 24 05:30:10 PM PDT 24
Peak memory 206620 kb
Host smart-b3ebca4d-3b29-46be-9b58-dbb5c1cad4c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53400
8347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.534008347
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.151622565
Short name T809
Test name
Test status
Simulation time 197853686 ps
CPU time 0.89 seconds
Started Jul 24 05:29:56 PM PDT 24
Finished Jul 24 05:30:02 PM PDT 24
Peak memory 206528 kb
Host smart-ed268fa9-9dc5-4321-87e4-160fb4992dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15162
2565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.151622565
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.687715900
Short name T1562
Test name
Test status
Simulation time 156484133 ps
CPU time 0.87 seconds
Started Jul 24 05:30:04 PM PDT 24
Finished Jul 24 05:30:05 PM PDT 24
Peak memory 206616 kb
Host smart-3f08b448-2d90-4f5c-b7cc-fcf2fab48304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68771
5900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.687715900
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.2509539760
Short name T561
Test name
Test status
Simulation time 190469676 ps
CPU time 0.83 seconds
Started Jul 24 05:30:08 PM PDT 24
Finished Jul 24 05:30:09 PM PDT 24
Peak memory 206788 kb
Host smart-33fc0117-91ee-4f1e-b9c6-cb22db610bcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25095
39760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.2509539760
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.4098090342
Short name T1609
Test name
Test status
Simulation time 155490927 ps
CPU time 0.78 seconds
Started Jul 24 05:30:10 PM PDT 24
Finished Jul 24 05:30:11 PM PDT 24
Peak memory 206600 kb
Host smart-2d0c0d26-d3ef-4885-890c-e21bc7a1a05e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40980
90342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.4098090342
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.1361517477
Short name T1033
Test name
Test status
Simulation time 227353989 ps
CPU time 0.91 seconds
Started Jul 24 05:30:14 PM PDT 24
Finished Jul 24 05:30:15 PM PDT 24
Peak memory 206580 kb
Host smart-fc233709-9576-4f5c-9ce0-d266f7da9e34
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1361517477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.1361517477
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.304123279
Short name T633
Test name
Test status
Simulation time 158190764 ps
CPU time 0.78 seconds
Started Jul 24 05:29:56 PM PDT 24
Finished Jul 24 05:29:57 PM PDT 24
Peak memory 206584 kb
Host smart-f15f6d29-e66a-403a-aac0-ca4f99d0ce57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30412
3279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.304123279
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.4119431253
Short name T1304
Test name
Test status
Simulation time 40442003 ps
CPU time 0.64 seconds
Started Jul 24 05:29:58 PM PDT 24
Finished Jul 24 05:29:59 PM PDT 24
Peak memory 206544 kb
Host smart-bf97def1-31d4-4c67-abd6-45eec1e48e29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41194
31253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.4119431253
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.1604324940
Short name T1916
Test name
Test status
Simulation time 15883763354 ps
CPU time 34.84 seconds
Started Jul 24 05:30:11 PM PDT 24
Finished Jul 24 05:30:46 PM PDT 24
Peak memory 207184 kb
Host smart-32815720-8bc8-4282-9f90-33a481f3efbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16043
24940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.1604324940
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.1131456086
Short name T1741
Test name
Test status
Simulation time 162878186 ps
CPU time 0.84 seconds
Started Jul 24 05:29:52 PM PDT 24
Finished Jul 24 05:29:53 PM PDT 24
Peak memory 206564 kb
Host smart-af4ef137-d7ec-4c5b-8ad7-2fbfc812e61f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11314
56086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.1131456086
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.3825853422
Short name T1858
Test name
Test status
Simulation time 189274281 ps
CPU time 0.87 seconds
Started Jul 24 05:29:57 PM PDT 24
Finished Jul 24 05:29:58 PM PDT 24
Peak memory 206588 kb
Host smart-0f23e2b3-69a3-4cbf-9652-70ad24177eeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38258
53422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.3825853422
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.1486776464
Short name T1730
Test name
Test status
Simulation time 191051584 ps
CPU time 0.86 seconds
Started Jul 24 05:30:10 PM PDT 24
Finished Jul 24 05:30:11 PM PDT 24
Peak memory 206520 kb
Host smart-2017fd98-8d0e-491a-8c47-8900343ec3a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14867
76464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.1486776464
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.1736018802
Short name T1054
Test name
Test status
Simulation time 147257659 ps
CPU time 0.76 seconds
Started Jul 24 05:30:06 PM PDT 24
Finished Jul 24 05:30:07 PM PDT 24
Peak memory 206596 kb
Host smart-ca71c597-b67a-486e-abc4-40acd6528078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17360
18802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.1736018802
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.1771763719
Short name T489
Test name
Test status
Simulation time 149365761 ps
CPU time 0.76 seconds
Started Jul 24 05:29:56 PM PDT 24
Finished Jul 24 05:29:57 PM PDT 24
Peak memory 206572 kb
Host smart-01fdd6b0-8458-4802-b613-043a89a33fb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17717
63719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.1771763719
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.10710484
Short name T995
Test name
Test status
Simulation time 163352954 ps
CPU time 0.78 seconds
Started Jul 24 05:30:11 PM PDT 24
Finished Jul 24 05:30:12 PM PDT 24
Peak memory 206576 kb
Host smart-95d69a5e-2ed5-4b11-bfd5-78484d82098a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10710
484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.10710484
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.1576604198
Short name T1161
Test name
Test status
Simulation time 150446340 ps
CPU time 0.77 seconds
Started Jul 24 05:30:12 PM PDT 24
Finished Jul 24 05:30:13 PM PDT 24
Peak memory 206600 kb
Host smart-26578d64-2e2e-4308-a0aa-138699463543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15766
04198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.1576604198
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.1465379085
Short name T1197
Test name
Test status
Simulation time 243152935 ps
CPU time 0.95 seconds
Started Jul 24 05:30:03 PM PDT 24
Finished Jul 24 05:30:05 PM PDT 24
Peak memory 206532 kb
Host smart-da67261e-fd10-43e1-8cde-333ad90ad107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14653
79085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1465379085
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.110506642
Short name T1396
Test name
Test status
Simulation time 4453798446 ps
CPU time 33.28 seconds
Started Jul 24 05:30:04 PM PDT 24
Finished Jul 24 05:30:38 PM PDT 24
Peak memory 206964 kb
Host smart-546118e1-1340-4122-a8a5-49d87b6fd174
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=110506642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.110506642
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.571573091
Short name T2698
Test name
Test status
Simulation time 162971999 ps
CPU time 0.82 seconds
Started Jul 24 05:30:08 PM PDT 24
Finished Jul 24 05:30:09 PM PDT 24
Peak memory 206780 kb
Host smart-0f7d6ee1-0bfd-4491-80ce-1e57deec48dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57157
3091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.571573091
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.732580310
Short name T1123
Test name
Test status
Simulation time 171339116 ps
CPU time 0.78 seconds
Started Jul 24 05:30:06 PM PDT 24
Finished Jul 24 05:30:07 PM PDT 24
Peak memory 206780 kb
Host smart-213dc9bf-f24f-44ff-88b1-f98c5eec4bce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73258
0310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.732580310
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.2946980165
Short name T1132
Test name
Test status
Simulation time 1315546077 ps
CPU time 2.75 seconds
Started Jul 24 05:30:05 PM PDT 24
Finished Jul 24 05:30:08 PM PDT 24
Peak memory 206764 kb
Host smart-181d1d99-08f6-45db-81b5-3ffa6428e357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29469
80165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.2946980165
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.3615095461
Short name T1249
Test name
Test status
Simulation time 3571530901 ps
CPU time 25.33 seconds
Started Jul 24 05:30:00 PM PDT 24
Finished Jul 24 05:30:25 PM PDT 24
Peak memory 206840 kb
Host smart-7766683c-55b8-4e75-86cd-cba35ab307f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36150
95461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.3615095461
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.3026318680
Short name T559
Test name
Test status
Simulation time 68059229 ps
CPU time 0.68 seconds
Started Jul 24 05:30:13 PM PDT 24
Finished Jul 24 05:30:13 PM PDT 24
Peak memory 206600 kb
Host smart-77f2b1e2-8468-45b6-909b-918910596d69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3026318680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.3026318680
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.3968999972
Short name T10
Test name
Test status
Simulation time 3823811603 ps
CPU time 5.58 seconds
Started Jul 24 05:30:09 PM PDT 24
Finished Jul 24 05:30:15 PM PDT 24
Peak memory 206884 kb
Host smart-35959572-44b1-4f56-9558-88c9e7c5879a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3968999972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.3968999972
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.3425385848
Short name T361
Test name
Test status
Simulation time 13388845162 ps
CPU time 11.83 seconds
Started Jul 24 05:30:09 PM PDT 24
Finished Jul 24 05:30:21 PM PDT 24
Peak memory 206840 kb
Host smart-502293dc-c7b9-4a9f-a2fb-eeda3fcdde55
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3425385848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.3425385848
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.536901751
Short name T178
Test name
Test status
Simulation time 23350091102 ps
CPU time 23.02 seconds
Started Jul 24 05:30:05 PM PDT 24
Finished Jul 24 05:30:29 PM PDT 24
Peak memory 206764 kb
Host smart-89cbaac5-ae13-443d-8910-47ced1d8b7c0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=536901751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.536901751
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.4211475140
Short name T464
Test name
Test status
Simulation time 164299593 ps
CPU time 0.81 seconds
Started Jul 24 05:30:00 PM PDT 24
Finished Jul 24 05:30:01 PM PDT 24
Peak memory 206608 kb
Host smart-5a030fe5-9b59-4923-ad30-2fdc1692a9b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42114
75140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.4211475140
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.1927239335
Short name T2139
Test name
Test status
Simulation time 221879810 ps
CPU time 0.82 seconds
Started Jul 24 05:30:10 PM PDT 24
Finished Jul 24 05:30:11 PM PDT 24
Peak memory 206776 kb
Host smart-d6912109-3d7b-46d5-bfff-6498941989f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19272
39335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.1927239335
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.3943557842
Short name T548
Test name
Test status
Simulation time 408105463 ps
CPU time 1.41 seconds
Started Jul 24 05:30:03 PM PDT 24
Finished Jul 24 05:30:05 PM PDT 24
Peak memory 206612 kb
Host smart-600c1c37-866f-4222-9c0a-868a17ca7ae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39435
57842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.3943557842
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.1889008555
Short name T591
Test name
Test status
Simulation time 602090957 ps
CPU time 1.53 seconds
Started Jul 24 05:30:05 PM PDT 24
Finished Jul 24 05:30:07 PM PDT 24
Peak memory 206784 kb
Host smart-4e57f15a-37bb-4acf-9282-19c2becbf67d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18890
08555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.1889008555
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.1016007470
Short name T88
Test name
Test status
Simulation time 12340640644 ps
CPU time 22.52 seconds
Started Jul 24 05:29:57 PM PDT 24
Finished Jul 24 05:30:20 PM PDT 24
Peak memory 206864 kb
Host smart-e0f1cf52-0d4d-4740-ad00-88c5e692ee9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10160
07470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.1016007470
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.2295466395
Short name T665
Test name
Test status
Simulation time 320658561 ps
CPU time 1.14 seconds
Started Jul 24 05:30:16 PM PDT 24
Finished Jul 24 05:30:18 PM PDT 24
Peak memory 206608 kb
Host smart-333283e4-706f-4b1c-b350-1dfb38b725e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22954
66395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.2295466395
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.1640688777
Short name T2382
Test name
Test status
Simulation time 133948104 ps
CPU time 0.73 seconds
Started Jul 24 05:30:08 PM PDT 24
Finished Jul 24 05:30:09 PM PDT 24
Peak memory 206588 kb
Host smart-2277c1ec-2f98-4245-a959-bf9e5488d7cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16406
88777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.1640688777
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.2125997559
Short name T2080
Test name
Test status
Simulation time 129439812 ps
CPU time 0.76 seconds
Started Jul 24 05:29:59 PM PDT 24
Finished Jul 24 05:29:59 PM PDT 24
Peak memory 206552 kb
Host smart-024f2681-5bf4-491c-87da-0f29b4498255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21259
97559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.2125997559
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.3906410965
Short name T2208
Test name
Test status
Simulation time 826394366 ps
CPU time 2.25 seconds
Started Jul 24 05:29:51 PM PDT 24
Finished Jul 24 05:29:54 PM PDT 24
Peak memory 206772 kb
Host smart-bb4f0c19-bcdf-4381-9382-08d3b39ba410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39064
10965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.3906410965
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.3563553329
Short name T879
Test name
Test status
Simulation time 180779941 ps
CPU time 1.89 seconds
Started Jul 24 05:29:57 PM PDT 24
Finished Jul 24 05:29:59 PM PDT 24
Peak memory 206832 kb
Host smart-bb93014a-0106-4965-9a86-88380b37d9f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35635
53329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.3563553329
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.1640736502
Short name T1912
Test name
Test status
Simulation time 221539716 ps
CPU time 0.88 seconds
Started Jul 24 05:30:23 PM PDT 24
Finished Jul 24 05:30:24 PM PDT 24
Peak memory 206600 kb
Host smart-0b6e0834-6cb4-4ae4-a5c4-715f6de4df23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16407
36502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.1640736502
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.3333174640
Short name T506
Test name
Test status
Simulation time 172112888 ps
CPU time 0.75 seconds
Started Jul 24 05:29:52 PM PDT 24
Finished Jul 24 05:29:53 PM PDT 24
Peak memory 206384 kb
Host smart-97e2c293-6ed8-4317-95d2-946380beaab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33331
74640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.3333174640
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.4004139477
Short name T902
Test name
Test status
Simulation time 236618234 ps
CPU time 0.92 seconds
Started Jul 24 05:30:22 PM PDT 24
Finished Jul 24 05:30:23 PM PDT 24
Peak memory 206604 kb
Host smart-e6ddc80b-e5ac-4005-ac3a-7e1fcdb9cf52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40041
39477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.4004139477
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_iso_retraction.2412079991
Short name T1662
Test name
Test status
Simulation time 9509770651 ps
CPU time 30.05 seconds
Started Jul 24 05:30:19 PM PDT 24
Finished Jul 24 05:30:49 PM PDT 24
Peak memory 206968 kb
Host smart-9bd6a2d9-45a2-459f-bdff-1cb17f4697b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24120
79991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_iso_retraction.2412079991
Directory /workspace/49.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.3994264204
Short name T827
Test name
Test status
Simulation time 193981366 ps
CPU time 0.8 seconds
Started Jul 24 05:30:27 PM PDT 24
Finished Jul 24 05:30:28 PM PDT 24
Peak memory 206604 kb
Host smart-0ec403db-5c4e-4f5c-9934-8d4445b0076d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39942
64204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.3994264204
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.3162625332
Short name T177
Test name
Test status
Simulation time 23293368907 ps
CPU time 26.16 seconds
Started Jul 24 05:30:15 PM PDT 24
Finished Jul 24 05:30:41 PM PDT 24
Peak memory 206724 kb
Host smart-ea788663-f47f-4ee3-a17d-c665eac61fae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31626
25332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.3162625332
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.256248146
Short name T1808
Test name
Test status
Simulation time 3299975964 ps
CPU time 3.7 seconds
Started Jul 24 05:30:08 PM PDT 24
Finished Jul 24 05:30:12 PM PDT 24
Peak memory 206708 kb
Host smart-2bdc23e0-7e1c-474b-9d01-822ffc61b61e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25624
8146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.256248146
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.2962044515
Short name T2275
Test name
Test status
Simulation time 6210606348 ps
CPU time 41.29 seconds
Started Jul 24 05:29:57 PM PDT 24
Finished Jul 24 05:30:39 PM PDT 24
Peak memory 206972 kb
Host smart-4de28ca1-48e1-498c-9440-e2056b3d3dfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29620
44515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.2962044515
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.4032306405
Short name T1008
Test name
Test status
Simulation time 5565861423 ps
CPU time 152.34 seconds
Started Jul 24 05:30:22 PM PDT 24
Finished Jul 24 05:32:55 PM PDT 24
Peak memory 206924 kb
Host smart-b2bf9861-3c5a-4ae1-ab03-d02fd3fb8689
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4032306405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.4032306405
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.1883463794
Short name T2036
Test name
Test status
Simulation time 272631171 ps
CPU time 0.93 seconds
Started Jul 24 05:30:19 PM PDT 24
Finished Jul 24 05:30:20 PM PDT 24
Peak memory 206616 kb
Host smart-40d4a27b-fd81-4ac2-a7d5-1cb2ccf7b3bd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1883463794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.1883463794
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.2081498773
Short name T958
Test name
Test status
Simulation time 194498772 ps
CPU time 0.91 seconds
Started Jul 24 05:29:53 PM PDT 24
Finished Jul 24 05:29:54 PM PDT 24
Peak memory 206632 kb
Host smart-a272ea9d-c9ce-4c24-840e-5f3f529a4fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20814
98773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.2081498773
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.634457020
Short name T1078
Test name
Test status
Simulation time 5095469820 ps
CPU time 46.63 seconds
Started Jul 24 05:30:16 PM PDT 24
Finished Jul 24 05:31:03 PM PDT 24
Peak memory 206908 kb
Host smart-eada174d-dec8-4252-9135-e9c3048fcadf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63445
7020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.634457020
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.3509614559
Short name T2515
Test name
Test status
Simulation time 6754826405 ps
CPU time 64.14 seconds
Started Jul 24 05:30:01 PM PDT 24
Finished Jul 24 05:31:05 PM PDT 24
Peak memory 206840 kb
Host smart-223884a3-9149-4b33-b3c0-3641ba65d077
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3509614559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.3509614559
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.1035789985
Short name T1655
Test name
Test status
Simulation time 161591833 ps
CPU time 0.77 seconds
Started Jul 24 05:30:00 PM PDT 24
Finished Jul 24 05:30:01 PM PDT 24
Peak memory 206616 kb
Host smart-ca19a533-a8c3-4505-b057-80c79ff0484c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1035789985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.1035789985
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.198910588
Short name T2026
Test name
Test status
Simulation time 140895058 ps
CPU time 0.73 seconds
Started Jul 24 05:29:53 PM PDT 24
Finished Jul 24 05:29:54 PM PDT 24
Peak memory 206516 kb
Host smart-1f926faa-52e0-4acc-a5d1-bd06ac457107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19891
0588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.198910588
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.3833688667
Short name T122
Test name
Test status
Simulation time 237738112 ps
CPU time 0.88 seconds
Started Jul 24 05:29:56 PM PDT 24
Finished Jul 24 05:29:58 PM PDT 24
Peak memory 206340 kb
Host smart-a6d7a216-50d1-4b7c-a2bc-7ff4b114f2b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38336
88667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.3833688667
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.4077530606
Short name T1639
Test name
Test status
Simulation time 173568599 ps
CPU time 0.81 seconds
Started Jul 24 05:30:03 PM PDT 24
Finished Jul 24 05:30:04 PM PDT 24
Peak memory 206652 kb
Host smart-66d8537f-e543-48db-aedc-b4d7c64eab46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40775
30606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.4077530606
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.675499327
Short name T443
Test name
Test status
Simulation time 207439469 ps
CPU time 0.8 seconds
Started Jul 24 05:30:08 PM PDT 24
Finished Jul 24 05:30:09 PM PDT 24
Peak memory 206572 kb
Host smart-161df9fc-dc01-45ad-a622-cdd680ef7adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67549
9327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.675499327
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.231754161
Short name T1518
Test name
Test status
Simulation time 239648912 ps
CPU time 0.8 seconds
Started Jul 24 05:29:59 PM PDT 24
Finished Jul 24 05:30:00 PM PDT 24
Peak memory 206372 kb
Host smart-75d9a727-79ff-4466-9da1-2ad68d92c262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23175
4161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.231754161
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.1284998506
Short name T1876
Test name
Test status
Simulation time 181317598 ps
CPU time 0.79 seconds
Started Jul 24 05:30:09 PM PDT 24
Finished Jul 24 05:30:10 PM PDT 24
Peak memory 206596 kb
Host smart-ef5e8579-fff8-4e53-9b41-cefe14f21362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12849
98506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.1284998506
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.2946621456
Short name T2410
Test name
Test status
Simulation time 261350819 ps
CPU time 1 seconds
Started Jul 24 05:30:05 PM PDT 24
Finished Jul 24 05:30:09 PM PDT 24
Peak memory 206596 kb
Host smart-72dc55e9-e6e2-4932-9529-d40da13a9e17
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2946621456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.2946621456
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.1890345851
Short name T1842
Test name
Test status
Simulation time 151032774 ps
CPU time 0.78 seconds
Started Jul 24 05:30:26 PM PDT 24
Finished Jul 24 05:30:27 PM PDT 24
Peak memory 206604 kb
Host smart-1986a4cc-e526-4a10-8cba-9f3bdf1fe4b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18903
45851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.1890345851
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.7737569
Short name T847
Test name
Test status
Simulation time 36109950 ps
CPU time 0.66 seconds
Started Jul 24 05:30:00 PM PDT 24
Finished Jul 24 05:30:01 PM PDT 24
Peak memory 206580 kb
Host smart-7640ff56-6ad0-4524-9393-d4630863ab19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77375
69 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.7737569
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.2925620433
Short name T2160
Test name
Test status
Simulation time 6978132802 ps
CPU time 16.02 seconds
Started Jul 24 05:30:26 PM PDT 24
Finished Jul 24 05:30:42 PM PDT 24
Peak memory 215088 kb
Host smart-89f14fec-fec4-4491-b85a-947189e47fe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29256
20433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.2925620433
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.1012530685
Short name T2136
Test name
Test status
Simulation time 199733480 ps
CPU time 0.9 seconds
Started Jul 24 05:30:21 PM PDT 24
Finished Jul 24 05:30:22 PM PDT 24
Peak memory 206528 kb
Host smart-0bb7d00a-7223-4838-bcc6-2c7fa5cbfebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10125
30685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.1012530685
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.707237363
Short name T2493
Test name
Test status
Simulation time 177233129 ps
CPU time 0.8 seconds
Started Jul 24 05:30:16 PM PDT 24
Finished Jul 24 05:30:17 PM PDT 24
Peak memory 206560 kb
Host smart-0911d590-d5ab-4600-a291-c7a5af17d52a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70723
7363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.707237363
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.2082916156
Short name T2480
Test name
Test status
Simulation time 189337641 ps
CPU time 0.79 seconds
Started Jul 24 05:29:59 PM PDT 24
Finished Jul 24 05:30:00 PM PDT 24
Peak memory 206568 kb
Host smart-b92cae28-2553-4b1b-a07e-75756e2b98d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20829
16156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.2082916156
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.95644364
Short name T867
Test name
Test status
Simulation time 190539593 ps
CPU time 0.79 seconds
Started Jul 24 05:30:07 PM PDT 24
Finished Jul 24 05:30:08 PM PDT 24
Peak memory 206544 kb
Host smart-2a5e57fd-0b77-4144-836d-33090a316b01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95644
364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.95644364
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.2630001003
Short name T2551
Test name
Test status
Simulation time 185254295 ps
CPU time 0.8 seconds
Started Jul 24 05:30:16 PM PDT 24
Finished Jul 24 05:30:17 PM PDT 24
Peak memory 206552 kb
Host smart-cb7dc49b-e1f1-4637-8963-23ffa582d5fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26300
01003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.2630001003
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.2793247829
Short name T1881
Test name
Test status
Simulation time 158390295 ps
CPU time 0.75 seconds
Started Jul 24 05:30:30 PM PDT 24
Finished Jul 24 05:30:31 PM PDT 24
Peak memory 206472 kb
Host smart-29b79bdf-fd07-4b51-a87a-0064a8db5c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27932
47829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.2793247829
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.334911548
Short name T1985
Test name
Test status
Simulation time 152873648 ps
CPU time 0.81 seconds
Started Jul 24 05:30:05 PM PDT 24
Finished Jul 24 05:30:09 PM PDT 24
Peak memory 206576 kb
Host smart-dcd624fd-3c19-4b58-b556-39747fe8fec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33491
1548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.334911548
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.1283311049
Short name T1274
Test name
Test status
Simulation time 215047113 ps
CPU time 0.96 seconds
Started Jul 24 05:30:14 PM PDT 24
Finished Jul 24 05:30:15 PM PDT 24
Peak memory 206580 kb
Host smart-2b473589-01f1-47d0-8c94-3f2bad2cc8a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12833
11049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.1283311049
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.4124231987
Short name T1503
Test name
Test status
Simulation time 4984797770 ps
CPU time 129.95 seconds
Started Jul 24 05:30:00 PM PDT 24
Finished Jul 24 05:32:10 PM PDT 24
Peak memory 206960 kb
Host smart-760383a9-10f1-4c50-952d-7eb0293d6f62
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4124231987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.4124231987
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.3569685394
Short name T507
Test name
Test status
Simulation time 165151433 ps
CPU time 0.76 seconds
Started Jul 24 05:30:23 PM PDT 24
Finished Jul 24 05:30:23 PM PDT 24
Peak memory 206548 kb
Host smart-434c0b33-e483-4224-aacc-e526bd799cd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35696
85394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.3569685394
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.1475303208
Short name T1138
Test name
Test status
Simulation time 145464761 ps
CPU time 0.77 seconds
Started Jul 24 05:29:59 PM PDT 24
Finished Jul 24 05:30:00 PM PDT 24
Peak memory 206572 kb
Host smart-a0c89eb1-23b8-486f-9d43-15131c1f438f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14753
03208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.1475303208
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.1910825073
Short name T427
Test name
Test status
Simulation time 1400332437 ps
CPU time 3 seconds
Started Jul 24 05:30:07 PM PDT 24
Finished Jul 24 05:30:10 PM PDT 24
Peak memory 206824 kb
Host smart-9781e217-2625-494c-b81d-bd1986f247a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19108
25073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.1910825073
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.2109691854
Short name T1056
Test name
Test status
Simulation time 5122215576 ps
CPU time 143.54 seconds
Started Jul 24 05:30:17 PM PDT 24
Finished Jul 24 05:32:41 PM PDT 24
Peak memory 206856 kb
Host smart-80a2268b-a30c-43c9-9f84-be5b7b3e2ea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21096
91854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.2109691854
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.467619008
Short name T1924
Test name
Test status
Simulation time 56623087 ps
CPU time 0.74 seconds
Started Jul 24 05:24:26 PM PDT 24
Finished Jul 24 05:24:27 PM PDT 24
Peak memory 206612 kb
Host smart-af15264c-9314-440e-b27e-f1d3dd854d5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=467619008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.467619008
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.1930334050
Short name T1854
Test name
Test status
Simulation time 3694513453 ps
CPU time 4.47 seconds
Started Jul 24 05:24:28 PM PDT 24
Finished Jul 24 05:24:33 PM PDT 24
Peak memory 206896 kb
Host smart-04362184-119f-4079-bd29-2f4c42bda359
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1930334050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.1930334050
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.3469421306
Short name T2663
Test name
Test status
Simulation time 13354710005 ps
CPU time 12.05 seconds
Started Jul 24 05:24:17 PM PDT 24
Finished Jul 24 05:24:30 PM PDT 24
Peak memory 206956 kb
Host smart-bfacfd12-629c-4efe-a761-901b6ded501d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3469421306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.3469421306
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.471831725
Short name T1084
Test name
Test status
Simulation time 23348430070 ps
CPU time 24.24 seconds
Started Jul 24 05:24:37 PM PDT 24
Finished Jul 24 05:25:02 PM PDT 24
Peak memory 206704 kb
Host smart-d4fe4f28-8162-4e7f-9f2f-d81b558557f2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=471831725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.471831725
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.3264682240
Short name T1898
Test name
Test status
Simulation time 159681682 ps
CPU time 0.81 seconds
Started Jul 24 05:24:36 PM PDT 24
Finished Jul 24 05:24:37 PM PDT 24
Peak memory 206508 kb
Host smart-231378b0-ec1a-4ae5-a4b7-e72720b411a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32646
82240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.3264682240
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.2962122293
Short name T2536
Test name
Test status
Simulation time 172909163 ps
CPU time 0.87 seconds
Started Jul 24 05:24:20 PM PDT 24
Finished Jul 24 05:24:21 PM PDT 24
Peak memory 206556 kb
Host smart-4da7af59-22d7-42ac-91a2-4cf10f94b2cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29621
22293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.2962122293
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.725490452
Short name T2474
Test name
Test status
Simulation time 372189779 ps
CPU time 1.17 seconds
Started Jul 24 05:24:21 PM PDT 24
Finished Jul 24 05:24:23 PM PDT 24
Peak memory 206584 kb
Host smart-7fecaa1f-77b2-4246-80ef-f6ab1e59a7ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72549
0452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.725490452
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.3729808518
Short name T996
Test name
Test status
Simulation time 772703098 ps
CPU time 2.04 seconds
Started Jul 24 05:24:19 PM PDT 24
Finished Jul 24 05:24:21 PM PDT 24
Peak memory 206824 kb
Host smart-ef63089b-a669-46a7-85c6-0b479a4d2dfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37298
08518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.3729808518
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.4165653397
Short name T2227
Test name
Test status
Simulation time 19468603610 ps
CPU time 38.71 seconds
Started Jul 24 05:24:28 PM PDT 24
Finished Jul 24 05:25:07 PM PDT 24
Peak memory 206856 kb
Host smart-1600ccaa-6bb0-4f0d-922f-62572dce94ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41656
53397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.4165653397
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.384540303
Short name T230
Test name
Test status
Simulation time 545895910 ps
CPU time 1.43 seconds
Started Jul 24 05:24:26 PM PDT 24
Finished Jul 24 05:24:28 PM PDT 24
Peak memory 206508 kb
Host smart-3dda58be-6dee-4a09-9d38-465b101d4ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38454
0303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.384540303
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.1870953062
Short name T1358
Test name
Test status
Simulation time 149292553 ps
CPU time 0.74 seconds
Started Jul 24 05:24:28 PM PDT 24
Finished Jul 24 05:24:29 PM PDT 24
Peak memory 206572 kb
Host smart-097c1f36-8dfd-47c0-9bbc-23cb836336c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18709
53062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.1870953062
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.3577324205
Short name T2307
Test name
Test status
Simulation time 38285690 ps
CPU time 0.64 seconds
Started Jul 24 05:24:41 PM PDT 24
Finished Jul 24 05:24:42 PM PDT 24
Peak memory 206512 kb
Host smart-d8bd0957-80e7-49a3-9042-26cb7f263e1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35773
24205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.3577324205
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.1038172516
Short name T753
Test name
Test status
Simulation time 989095810 ps
CPU time 2.04 seconds
Started Jul 24 05:24:18 PM PDT 24
Finished Jul 24 05:24:21 PM PDT 24
Peak memory 206696 kb
Host smart-404cf489-5127-4e09-8214-79b6a1e2b5c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10381
72516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.1038172516
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.1936520695
Short name T1851
Test name
Test status
Simulation time 431780888 ps
CPU time 2.64 seconds
Started Jul 24 05:24:44 PM PDT 24
Finished Jul 24 05:24:47 PM PDT 24
Peak memory 206800 kb
Host smart-d339deb9-c071-445c-9d75-f5d4eba0b75b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19365
20695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.1936520695
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.2335772396
Short name T1384
Test name
Test status
Simulation time 182401422 ps
CPU time 0.83 seconds
Started Jul 24 05:24:41 PM PDT 24
Finished Jul 24 05:24:42 PM PDT 24
Peak memory 206572 kb
Host smart-066bbdaf-a7f4-41f9-994f-bbb5d23a31f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23357
72396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.2335772396
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.1543652200
Short name T640
Test name
Test status
Simulation time 161903336 ps
CPU time 0.75 seconds
Started Jul 24 05:24:33 PM PDT 24
Finished Jul 24 05:24:34 PM PDT 24
Peak memory 206536 kb
Host smart-8b5e1f08-1417-42b0-b027-b6c70127b35f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15436
52200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.1543652200
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.1007956913
Short name T1422
Test name
Test status
Simulation time 202720684 ps
CPU time 0.91 seconds
Started Jul 24 05:24:33 PM PDT 24
Finished Jul 24 05:24:34 PM PDT 24
Peak memory 206600 kb
Host smart-41d5ee72-9b48-4ce9-82f0-649785a0e944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10079
56913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.1007956913
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.345511268
Short name T95
Test name
Test status
Simulation time 8165624800 ps
CPU time 227.8 seconds
Started Jul 24 05:24:30 PM PDT 24
Finished Jul 24 05:28:18 PM PDT 24
Peak memory 206980 kb
Host smart-18312b33-3384-4279-9f3f-d5ae13a6d0be
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=345511268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.345511268
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_iso_retraction.2046375542
Short name T624
Test name
Test status
Simulation time 10357783206 ps
CPU time 93.19 seconds
Started Jul 24 05:24:29 PM PDT 24
Finished Jul 24 05:26:02 PM PDT 24
Peak memory 206860 kb
Host smart-97e2efd0-a7d1-42d5-a824-b9f5d5db94b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20463
75542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.2046375542
Directory /workspace/5.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.1696196170
Short name T1497
Test name
Test status
Simulation time 220976280 ps
CPU time 0.93 seconds
Started Jul 24 05:24:40 PM PDT 24
Finished Jul 24 05:24:41 PM PDT 24
Peak memory 206580 kb
Host smart-2a86d88c-345a-4dc8-9f96-72ec63189aa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16961
96170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.1696196170
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.2568080275
Short name T2561
Test name
Test status
Simulation time 23286142707 ps
CPU time 27.91 seconds
Started Jul 24 05:24:26 PM PDT 24
Finished Jul 24 05:24:54 PM PDT 24
Peak memory 206640 kb
Host smart-bbac00ce-c8aa-4c49-9697-8afd69f31468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25680
80275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.2568080275
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.2594984942
Short name T674
Test name
Test status
Simulation time 3374450948 ps
CPU time 3.82 seconds
Started Jul 24 05:24:36 PM PDT 24
Finished Jul 24 05:24:40 PM PDT 24
Peak memory 206672 kb
Host smart-5c0acac0-e7bd-4661-92f6-900f1c720949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25949
84942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.2594984942
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.3388839675
Short name T1037
Test name
Test status
Simulation time 5330589905 ps
CPU time 143.95 seconds
Started Jul 24 05:24:24 PM PDT 24
Finished Jul 24 05:26:48 PM PDT 24
Peak memory 206900 kb
Host smart-c9d0ce09-dc0a-4bf4-9b2e-14ee69b61adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33888
39675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.3388839675
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.889610432
Short name T2109
Test name
Test status
Simulation time 7363383895 ps
CPU time 209.9 seconds
Started Jul 24 05:24:19 PM PDT 24
Finished Jul 24 05:27:49 PM PDT 24
Peak memory 206880 kb
Host smart-8f869f68-e327-4dee-b06b-7b5185dd26b9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=889610432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.889610432
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.220218463
Short name T1182
Test name
Test status
Simulation time 240381269 ps
CPU time 0.9 seconds
Started Jul 24 05:24:25 PM PDT 24
Finished Jul 24 05:24:26 PM PDT 24
Peak memory 206584 kb
Host smart-eddd1e82-d5f6-40b8-bee5-07ff6812f99d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=220218463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.220218463
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.2015218025
Short name T1692
Test name
Test status
Simulation time 190612096 ps
CPU time 0.86 seconds
Started Jul 24 05:24:24 PM PDT 24
Finished Jul 24 05:24:25 PM PDT 24
Peak memory 206592 kb
Host smart-b14052e9-d0c4-40d4-8fc2-1d6b869c4a9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20152
18025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.2015218025
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.569049849
Short name T1356
Test name
Test status
Simulation time 3526424961 ps
CPU time 24.21 seconds
Started Jul 24 05:24:27 PM PDT 24
Finished Jul 24 05:24:52 PM PDT 24
Peak memory 206908 kb
Host smart-fbdd0d68-303e-432c-8344-70ec81bc6345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56904
9849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.569049849
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.763133507
Short name T877
Test name
Test status
Simulation time 5367025954 ps
CPU time 42.21 seconds
Started Jul 24 05:24:38 PM PDT 24
Finished Jul 24 05:25:21 PM PDT 24
Peak memory 206992 kb
Host smart-81280427-8758-470b-bf97-d61010a09ac6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=763133507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.763133507
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.2069789291
Short name T2448
Test name
Test status
Simulation time 145499658 ps
CPU time 0.73 seconds
Started Jul 24 05:24:27 PM PDT 24
Finished Jul 24 05:24:28 PM PDT 24
Peak memory 206592 kb
Host smart-3d4faa77-07d3-4fdc-83f9-b9cab1d0c5fb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2069789291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.2069789291
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.223237677
Short name T1433
Test name
Test status
Simulation time 148830267 ps
CPU time 0.76 seconds
Started Jul 24 05:24:28 PM PDT 24
Finished Jul 24 05:24:29 PM PDT 24
Peak memory 206596 kb
Host smart-6352d01d-bce6-4a45-9995-0bff7d0f0e50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22323
7677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.223237677
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.3713974151
Short name T2088
Test name
Test status
Simulation time 218544756 ps
CPU time 0.85 seconds
Started Jul 24 05:24:36 PM PDT 24
Finished Jul 24 05:24:37 PM PDT 24
Peak memory 206616 kb
Host smart-d4d6cf11-1fc4-4d23-8f0f-b47a551c06bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37139
74151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.3713974151
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.425633572
Short name T1386
Test name
Test status
Simulation time 180207431 ps
CPU time 0.81 seconds
Started Jul 24 05:24:31 PM PDT 24
Finished Jul 24 05:24:32 PM PDT 24
Peak memory 206584 kb
Host smart-49deac34-ced9-4c1e-a3f5-dbefd087a86a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42563
3572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.425633572
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.3618541443
Short name T1058
Test name
Test status
Simulation time 193414084 ps
CPU time 0.9 seconds
Started Jul 24 05:24:54 PM PDT 24
Finished Jul 24 05:24:55 PM PDT 24
Peak memory 206596 kb
Host smart-e1c4669d-2837-482d-b07d-04b025095888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36185
41443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.3618541443
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.1370744454
Short name T352
Test name
Test status
Simulation time 168520219 ps
CPU time 0.82 seconds
Started Jul 24 05:24:31 PM PDT 24
Finished Jul 24 05:24:33 PM PDT 24
Peak memory 206588 kb
Host smart-d4f2b455-b0f9-4537-8916-443752802972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13707
44454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.1370744454
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.3229799355
Short name T163
Test name
Test status
Simulation time 151897429 ps
CPU time 0.77 seconds
Started Jul 24 05:24:27 PM PDT 24
Finished Jul 24 05:24:28 PM PDT 24
Peak memory 206516 kb
Host smart-4cf0b7d5-3375-4949-8406-7ca054aa63f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32297
99355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.3229799355
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.2946891517
Short name T2060
Test name
Test status
Simulation time 221237809 ps
CPU time 0.93 seconds
Started Jul 24 05:24:22 PM PDT 24
Finished Jul 24 05:24:23 PM PDT 24
Peak memory 206588 kb
Host smart-072a6518-a222-4753-9cd9-8d0bfd295650
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2946891517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.2946891517
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.4289824432
Short name T363
Test name
Test status
Simulation time 156898765 ps
CPU time 0.89 seconds
Started Jul 24 05:24:42 PM PDT 24
Finished Jul 24 05:24:44 PM PDT 24
Peak memory 206596 kb
Host smart-ae0140d5-997c-44b5-a876-8bfd2808da0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42898
24432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.4289824432
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.3477861205
Short name T1920
Test name
Test status
Simulation time 40428462 ps
CPU time 0.69 seconds
Started Jul 24 05:24:34 PM PDT 24
Finished Jul 24 05:24:35 PM PDT 24
Peak memory 206520 kb
Host smart-1ffeccd9-88b5-4c0c-9805-f9d8cf55b989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34778
61205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.3477861205
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.2802846363
Short name T2210
Test name
Test status
Simulation time 21846748789 ps
CPU time 46.04 seconds
Started Jul 24 05:24:35 PM PDT 24
Finished Jul 24 05:25:21 PM PDT 24
Peak memory 206980 kb
Host smart-b014505d-0c2d-4175-ab52-3ab78d80ab3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28028
46363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.2802846363
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.557572144
Short name T2094
Test name
Test status
Simulation time 191968513 ps
CPU time 0.86 seconds
Started Jul 24 05:24:41 PM PDT 24
Finished Jul 24 05:24:42 PM PDT 24
Peak memory 206596 kb
Host smart-7ba15ac3-2ba9-4e3a-ba56-9b210703a400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55757
2144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.557572144
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.2822184378
Short name T1125
Test name
Test status
Simulation time 238753809 ps
CPU time 0.86 seconds
Started Jul 24 05:24:37 PM PDT 24
Finished Jul 24 05:24:38 PM PDT 24
Peak memory 206576 kb
Host smart-ba5614fe-534f-43b2-8e4c-4d56fcad3018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28221
84378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.2822184378
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.3664013787
Short name T1670
Test name
Test status
Simulation time 7132694109 ps
CPU time 50.42 seconds
Started Jul 24 05:24:30 PM PDT 24
Finished Jul 24 05:25:21 PM PDT 24
Peak memory 207036 kb
Host smart-0e111b4c-c236-4ef7-86e6-e54883c0a1f4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3664013787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.3664013787
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.1120501210
Short name T742
Test name
Test status
Simulation time 13402128082 ps
CPU time 264.23 seconds
Started Jul 24 05:24:28 PM PDT 24
Finished Jul 24 05:28:53 PM PDT 24
Peak memory 206984 kb
Host smart-30a5ae8d-bd7e-47e5-9374-1a056fd75369
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1120501210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.1120501210
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.2298184103
Short name T913
Test name
Test status
Simulation time 6891278614 ps
CPU time 31.49 seconds
Started Jul 24 05:24:32 PM PDT 24
Finished Jul 24 05:25:03 PM PDT 24
Peak memory 206856 kb
Host smart-1ebe0607-caa3-4f66-9311-500b90f3cef2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2298184103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.2298184103
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.166483502
Short name T1332
Test name
Test status
Simulation time 215957771 ps
CPU time 0.86 seconds
Started Jul 24 05:24:27 PM PDT 24
Finished Jul 24 05:24:28 PM PDT 24
Peak memory 206608 kb
Host smart-677ccda4-e0e2-4d92-bd21-4882e10325af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16648
3502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.166483502
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.3012044727
Short name T1175
Test name
Test status
Simulation time 153689163 ps
CPU time 0.76 seconds
Started Jul 24 05:24:29 PM PDT 24
Finished Jul 24 05:24:31 PM PDT 24
Peak memory 206516 kb
Host smart-bde5d3c5-67d6-4f44-adc7-f20d2c1bb085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30120
44727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.3012044727
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.3832408902
Short name T2032
Test name
Test status
Simulation time 139826024 ps
CPU time 0.74 seconds
Started Jul 24 05:24:39 PM PDT 24
Finished Jul 24 05:24:40 PM PDT 24
Peak memory 206640 kb
Host smart-2e5cd2ff-2212-49b0-82b7-922fa33a46d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38324
08902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.3832408902
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.3506914803
Short name T974
Test name
Test status
Simulation time 175842211 ps
CPU time 0.77 seconds
Started Jul 24 05:24:38 PM PDT 24
Finished Jul 24 05:24:38 PM PDT 24
Peak memory 206592 kb
Host smart-8a2f9801-ec7e-48c1-a2da-e30b1d95d81a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35069
14803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.3506914803
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.1971257813
Short name T1806
Test name
Test status
Simulation time 153044028 ps
CPU time 0.8 seconds
Started Jul 24 05:24:35 PM PDT 24
Finished Jul 24 05:24:36 PM PDT 24
Peak memory 206560 kb
Host smart-d34d7f39-9f5d-4696-b537-8f348a96cab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19712
57813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.1971257813
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.3336368950
Short name T2308
Test name
Test status
Simulation time 271333830 ps
CPU time 0.95 seconds
Started Jul 24 05:24:36 PM PDT 24
Finished Jul 24 05:24:37 PM PDT 24
Peak memory 206596 kb
Host smart-7aef01c2-e079-4fe7-a064-caa0839ed889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33363
68950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.3336368950
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.254351387
Short name T2177
Test name
Test status
Simulation time 3391010063 ps
CPU time 24.6 seconds
Started Jul 24 05:24:49 PM PDT 24
Finished Jul 24 05:25:13 PM PDT 24
Peak memory 206820 kb
Host smart-193bf39b-b66b-47dc-a007-ff64985d0b90
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=254351387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.254351387
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.2529614544
Short name T2153
Test name
Test status
Simulation time 150673511 ps
CPU time 0.78 seconds
Started Jul 24 05:24:40 PM PDT 24
Finished Jul 24 05:24:41 PM PDT 24
Peak memory 206600 kb
Host smart-613d78a7-3a83-4459-92fd-9abae0e9948e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25296
14544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.2529614544
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.2083420396
Short name T2662
Test name
Test status
Simulation time 174975997 ps
CPU time 0.79 seconds
Started Jul 24 05:24:25 PM PDT 24
Finished Jul 24 05:24:26 PM PDT 24
Peak memory 206516 kb
Host smart-fb494c62-fdb8-45ca-a220-0da4ecd23e5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20834
20396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.2083420396
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.1215157623
Short name T2222
Test name
Test status
Simulation time 374026789 ps
CPU time 1.08 seconds
Started Jul 24 05:24:41 PM PDT 24
Finished Jul 24 05:24:42 PM PDT 24
Peak memory 206568 kb
Host smart-dbbca7e4-f491-4918-b82a-c8bdf979e6ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12151
57623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.1215157623
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.4247171105
Short name T1193
Test name
Test status
Simulation time 3134883329 ps
CPU time 84.92 seconds
Started Jul 24 05:24:37 PM PDT 24
Finished Jul 24 05:26:02 PM PDT 24
Peak memory 206904 kb
Host smart-4e9b42b7-423a-4acd-98af-e05759c94e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42471
71105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.4247171105
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.1852882321
Short name T1004
Test name
Test status
Simulation time 61139050 ps
CPU time 0.68 seconds
Started Jul 24 05:24:41 PM PDT 24
Finished Jul 24 05:24:42 PM PDT 24
Peak memory 206572 kb
Host smart-326d4345-fe3f-4a73-86bf-e9e60e5fbb01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1852882321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.1852882321
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.2754364144
Short name T2241
Test name
Test status
Simulation time 4169419697 ps
CPU time 4.67 seconds
Started Jul 24 05:24:30 PM PDT 24
Finished Jul 24 05:24:35 PM PDT 24
Peak memory 206764 kb
Host smart-24fafecd-9ae2-4d79-91db-91b3675b879c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2754364144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.2754364144
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.1599461649
Short name T1746
Test name
Test status
Simulation time 13374981821 ps
CPU time 11.98 seconds
Started Jul 24 05:24:36 PM PDT 24
Finished Jul 24 05:24:48 PM PDT 24
Peak memory 206808 kb
Host smart-0a1d3473-3753-4412-ba2c-aace1c7262f7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1599461649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.1599461649
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.2435875793
Short name T2637
Test name
Test status
Simulation time 23371307220 ps
CPU time 28.1 seconds
Started Jul 24 05:24:33 PM PDT 24
Finished Jul 24 05:25:01 PM PDT 24
Peak memory 206788 kb
Host smart-bea84ba7-6f7e-4b9a-9df6-2ed7dd438d72
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2435875793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.2435875793
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.1213843718
Short name T1757
Test name
Test status
Simulation time 180093629 ps
CPU time 0.81 seconds
Started Jul 24 05:24:29 PM PDT 24
Finished Jul 24 05:24:30 PM PDT 24
Peak memory 206604 kb
Host smart-ae39b942-3e65-431d-9516-764e63689543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12138
43718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.1213843718
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.383904611
Short name T597
Test name
Test status
Simulation time 149961348 ps
CPU time 0.74 seconds
Started Jul 24 05:24:44 PM PDT 24
Finished Jul 24 05:24:45 PM PDT 24
Peak memory 206624 kb
Host smart-db5aaba4-6393-4f5c-b84a-9b073e682130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38390
4611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.383904611
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.712695665
Short name T969
Test name
Test status
Simulation time 381448237 ps
CPU time 1.23 seconds
Started Jul 24 05:24:33 PM PDT 24
Finished Jul 24 05:24:34 PM PDT 24
Peak memory 206560 kb
Host smart-997aa978-0097-4577-8102-ffd90ca323cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71269
5665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.712695665
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.338952072
Short name T1535
Test name
Test status
Simulation time 379426184 ps
CPU time 1.1 seconds
Started Jul 24 05:24:29 PM PDT 24
Finished Jul 24 05:24:31 PM PDT 24
Peak memory 206564 kb
Host smart-88280a6a-3354-4683-a72c-b381c6cc556b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33895
2072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.338952072
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.1831073886
Short name T505
Test name
Test status
Simulation time 12995907420 ps
CPU time 25.26 seconds
Started Jul 24 05:24:39 PM PDT 24
Finished Jul 24 05:25:05 PM PDT 24
Peak memory 206960 kb
Host smart-37fc3fee-82d5-480b-b3be-2eaf6f6b3d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18310
73886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.1831073886
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.2880589633
Short name T2626
Test name
Test status
Simulation time 329430704 ps
CPU time 1.16 seconds
Started Jul 24 05:24:43 PM PDT 24
Finished Jul 24 05:24:44 PM PDT 24
Peak memory 206548 kb
Host smart-c1604483-a3eb-4104-957e-9afd1c708021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28805
89633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.2880589633
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.1017583540
Short name T1845
Test name
Test status
Simulation time 141497144 ps
CPU time 0.75 seconds
Started Jul 24 05:24:35 PM PDT 24
Finished Jul 24 05:24:36 PM PDT 24
Peak memory 206552 kb
Host smart-272f7299-79b8-4804-a945-66f810063976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10175
83540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.1017583540
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.827767402
Short name T2650
Test name
Test status
Simulation time 49439012 ps
CPU time 0.66 seconds
Started Jul 24 05:24:41 PM PDT 24
Finished Jul 24 05:24:43 PM PDT 24
Peak memory 206576 kb
Host smart-05dd586e-e6be-4e0a-8fea-232385b10292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82776
7402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.827767402
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.2719400411
Short name T1511
Test name
Test status
Simulation time 775247463 ps
CPU time 1.88 seconds
Started Jul 24 05:24:33 PM PDT 24
Finished Jul 24 05:24:35 PM PDT 24
Peak memory 206824 kb
Host smart-f052c098-098a-44d4-b7f1-1605570ef3a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27194
00411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.2719400411
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.1396309926
Short name T2279
Test name
Test status
Simulation time 185260450 ps
CPU time 2.05 seconds
Started Jul 24 05:24:28 PM PDT 24
Finished Jul 24 05:24:30 PM PDT 24
Peak memory 206660 kb
Host smart-59f49b1c-8f2d-48e7-8c43-a4fb39e5c2ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13963
09926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.1396309926
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.95381097
Short name T1715
Test name
Test status
Simulation time 162204851 ps
CPU time 0.77 seconds
Started Jul 24 05:24:47 PM PDT 24
Finished Jul 24 05:24:48 PM PDT 24
Peak memory 206488 kb
Host smart-37dc32ed-1dd6-4a7b-9115-c80f12d6afcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95381
097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.95381097
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.145303715
Short name T460
Test name
Test status
Simulation time 167249564 ps
CPU time 0.75 seconds
Started Jul 24 05:24:40 PM PDT 24
Finished Jul 24 05:24:41 PM PDT 24
Peak memory 206572 kb
Host smart-59b59132-2f1d-4df1-a20a-f7de775d7a7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14530
3715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.145303715
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.1010431582
Short name T790
Test name
Test status
Simulation time 221649508 ps
CPU time 0.87 seconds
Started Jul 24 05:24:34 PM PDT 24
Finished Jul 24 05:24:35 PM PDT 24
Peak memory 206620 kb
Host smart-02bd5107-749f-42d6-b572-5f665dd00951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10104
31582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.1010431582
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_iso_retraction.3376183009
Short name T832
Test name
Test status
Simulation time 6673373823 ps
CPU time 57.08 seconds
Started Jul 24 05:24:37 PM PDT 24
Finished Jul 24 05:25:35 PM PDT 24
Peak memory 206860 kb
Host smart-dccc7a03-ef33-436f-98b0-95fdbf1eb297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33761
83009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_iso_retraction.3376183009
Directory /workspace/6.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.2370353166
Short name T16
Test name
Test status
Simulation time 240039697 ps
CPU time 0.87 seconds
Started Jul 24 05:24:38 PM PDT 24
Finished Jul 24 05:24:39 PM PDT 24
Peak memory 206580 kb
Host smart-618e7876-162b-46a9-8660-892ec826f47d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23703
53166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.2370353166
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.237640848
Short name T2172
Test name
Test status
Simulation time 23291620877 ps
CPU time 25.09 seconds
Started Jul 24 05:24:40 PM PDT 24
Finished Jul 24 05:25:06 PM PDT 24
Peak memory 206708 kb
Host smart-17a97689-0008-4edc-8481-d9ed14551c83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23764
0848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.237640848
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.576918250
Short name T491
Test name
Test status
Simulation time 3279768706 ps
CPU time 4.41 seconds
Started Jul 24 05:25:00 PM PDT 24
Finished Jul 24 05:25:05 PM PDT 24
Peak memory 206716 kb
Host smart-238bacba-cab3-4e89-9543-46088100f46b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57691
8250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.576918250
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.3171777034
Short name T699
Test name
Test status
Simulation time 5788327477 ps
CPU time 159.13 seconds
Started Jul 24 05:24:29 PM PDT 24
Finished Jul 24 05:27:08 PM PDT 24
Peak memory 206916 kb
Host smart-14203bc4-e14d-44d5-9b5e-d0e166d28ad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31717
77034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.3171777034
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.3284520610
Short name T2230
Test name
Test status
Simulation time 4309945888 ps
CPU time 119.35 seconds
Started Jul 24 05:24:48 PM PDT 24
Finished Jul 24 05:26:47 PM PDT 24
Peak memory 206832 kb
Host smart-2aa19f9c-237f-41d1-b235-a3094ac26d19
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3284520610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.3284520610
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.2052776305
Short name T1576
Test name
Test status
Simulation time 272689704 ps
CPU time 0.9 seconds
Started Jul 24 05:24:42 PM PDT 24
Finished Jul 24 05:24:43 PM PDT 24
Peak memory 206496 kb
Host smart-2d7ef532-3a5c-4a29-9eb9-6022e8910f69
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2052776305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.2052776305
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.2778971131
Short name T2451
Test name
Test status
Simulation time 195647688 ps
CPU time 0.81 seconds
Started Jul 24 05:24:35 PM PDT 24
Finished Jul 24 05:24:36 PM PDT 24
Peak memory 206588 kb
Host smart-82b571b8-5083-4a48-8194-5f65eda1e780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27789
71131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.2778971131
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.1337543764
Short name T1053
Test name
Test status
Simulation time 4445088944 ps
CPU time 31.91 seconds
Started Jul 24 05:24:28 PM PDT 24
Finished Jul 24 05:25:00 PM PDT 24
Peak memory 206916 kb
Host smart-98f2dd58-218d-4e9d-a734-f9bc3ce64b74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13375
43764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.1337543764
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.1828529185
Short name T2174
Test name
Test status
Simulation time 4753137053 ps
CPU time 132.92 seconds
Started Jul 24 05:24:36 PM PDT 24
Finished Jul 24 05:26:49 PM PDT 24
Peak memory 206912 kb
Host smart-00ced082-9960-40e2-9ca1-fd63604a1c0b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1828529185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.1828529185
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.2195443700
Short name T1659
Test name
Test status
Simulation time 166029358 ps
CPU time 0.83 seconds
Started Jul 24 05:24:33 PM PDT 24
Finished Jul 24 05:24:34 PM PDT 24
Peak memory 206552 kb
Host smart-dff6caf3-c480-4416-ab64-b16cd9c9942b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2195443700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.2195443700
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.595915502
Short name T768
Test name
Test status
Simulation time 166521652 ps
CPU time 0.83 seconds
Started Jul 24 05:24:35 PM PDT 24
Finished Jul 24 05:24:36 PM PDT 24
Peak memory 206780 kb
Host smart-c36d19ad-9be0-4c82-aa73-0962ad24b383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59591
5502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.595915502
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.2037749954
Short name T134
Test name
Test status
Simulation time 220109401 ps
CPU time 0.87 seconds
Started Jul 24 05:24:49 PM PDT 24
Finished Jul 24 05:24:50 PM PDT 24
Peak memory 206640 kb
Host smart-123da66f-919f-476b-9906-4639305d2133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20377
49954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.2037749954
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.2079173481
Short name T2449
Test name
Test status
Simulation time 252760415 ps
CPU time 0.88 seconds
Started Jul 24 05:24:51 PM PDT 24
Finished Jul 24 05:24:52 PM PDT 24
Peak memory 206520 kb
Host smart-f947db13-331e-4c92-ac5f-1da592d765be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20791
73481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.2079173481
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.3461025249
Short name T414
Test name
Test status
Simulation time 164222963 ps
CPU time 0.8 seconds
Started Jul 24 05:24:38 PM PDT 24
Finished Jul 24 05:24:39 PM PDT 24
Peak memory 206572 kb
Host smart-f8a4e1c1-ba5e-47ae-a739-7b99c974ae5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34610
25249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.3461025249
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.2981102708
Short name T1171
Test name
Test status
Simulation time 203889735 ps
CPU time 0.85 seconds
Started Jul 24 05:24:45 PM PDT 24
Finished Jul 24 05:24:46 PM PDT 24
Peak memory 206556 kb
Host smart-64afb2f9-995d-481d-879a-97853ba09e1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29811
02708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.2981102708
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.2573000411
Short name T1553
Test name
Test status
Simulation time 147052014 ps
CPU time 0.81 seconds
Started Jul 24 05:24:35 PM PDT 24
Finished Jul 24 05:24:36 PM PDT 24
Peak memory 206628 kb
Host smart-05cb046f-bcd3-4d94-943c-b190cc6cd789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25730
00411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.2573000411
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.1222333475
Short name T2652
Test name
Test status
Simulation time 209198100 ps
CPU time 0.88 seconds
Started Jul 24 05:24:38 PM PDT 24
Finished Jul 24 05:24:39 PM PDT 24
Peak memory 206588 kb
Host smart-71ebde51-dc2c-453d-8b37-cea3e315ed36
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1222333475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.1222333475
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.3360608139
Short name T598
Test name
Test status
Simulation time 167722971 ps
CPU time 0.76 seconds
Started Jul 24 05:24:34 PM PDT 24
Finished Jul 24 05:24:35 PM PDT 24
Peak memory 206572 kb
Host smart-2aca4e05-c873-4fe3-a3db-ffd81f11c88b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33606
08139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.3360608139
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.2845189001
Short name T1726
Test name
Test status
Simulation time 51779600 ps
CPU time 0.72 seconds
Started Jul 24 05:24:41 PM PDT 24
Finished Jul 24 05:24:42 PM PDT 24
Peak memory 206544 kb
Host smart-e61db9ea-5a7d-4c6e-a35d-56df2f4f6fb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28451
89001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.2845189001
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.1554024869
Short name T227
Test name
Test status
Simulation time 9666054459 ps
CPU time 21.91 seconds
Started Jul 24 05:24:39 PM PDT 24
Finished Jul 24 05:25:01 PM PDT 24
Peak memory 207124 kb
Host smart-ef8d8107-08b8-4772-b6f0-dc61bef7144f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15540
24869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.1554024869
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.3328917
Short name T1154
Test name
Test status
Simulation time 235295705 ps
CPU time 0.92 seconds
Started Jul 24 05:24:30 PM PDT 24
Finished Jul 24 05:24:31 PM PDT 24
Peak memory 206592 kb
Host smart-d0aecf1e-8db9-4e28-9f07-03c81f8ca090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33289
17 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.3328917
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.2793852491
Short name T1652
Test name
Test status
Simulation time 249949970 ps
CPU time 0.89 seconds
Started Jul 24 05:24:35 PM PDT 24
Finished Jul 24 05:24:36 PM PDT 24
Peak memory 206580 kb
Host smart-80bd8d59-ce1e-4f4e-b989-9ea15a2ddb85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27938
52491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.2793852491
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.3014402169
Short name T166
Test name
Test status
Simulation time 9683666393 ps
CPU time 243.41 seconds
Started Jul 24 05:24:35 PM PDT 24
Finished Jul 24 05:28:38 PM PDT 24
Peak memory 207032 kb
Host smart-b0462242-08e3-4488-80fd-f95819d8ae71
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3014402169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.3014402169
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.372750892
Short name T675
Test name
Test status
Simulation time 7746790724 ps
CPU time 31.68 seconds
Started Jul 24 05:24:51 PM PDT 24
Finished Jul 24 05:25:23 PM PDT 24
Peak memory 206976 kb
Host smart-8d13e40c-a280-4c02-bc9d-e040946a3123
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=372750892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.372750892
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.4196756249
Short name T2569
Test name
Test status
Simulation time 12660640840 ps
CPU time 85.11 seconds
Started Jul 24 05:24:39 PM PDT 24
Finished Jul 24 05:26:04 PM PDT 24
Peak memory 206888 kb
Host smart-e5c731de-93d9-4e08-b0da-6900c74e6bb4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4196756249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.4196756249
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.2749031897
Short name T2752
Test name
Test status
Simulation time 201849730 ps
CPU time 0.83 seconds
Started Jul 24 05:24:36 PM PDT 24
Finished Jul 24 05:24:38 PM PDT 24
Peak memory 206576 kb
Host smart-e98d67f8-fcad-4a11-8edd-17d15936995a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27490
31897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.2749031897
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.3136058689
Short name T2012
Test name
Test status
Simulation time 165052791 ps
CPU time 0.78 seconds
Started Jul 24 05:24:37 PM PDT 24
Finished Jul 24 05:24:38 PM PDT 24
Peak memory 206592 kb
Host smart-4964d3da-e167-4b5b-92c6-2afee715f077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31360
58689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.3136058689
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.1702983591
Short name T1925
Test name
Test status
Simulation time 156615969 ps
CPU time 0.74 seconds
Started Jul 24 05:24:38 PM PDT 24
Finished Jul 24 05:24:39 PM PDT 24
Peak memory 206476 kb
Host smart-e407d7e8-b618-421d-96b9-1c0cf6311fce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17029
83591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.1702983591
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.4060911967
Short name T2527
Test name
Test status
Simulation time 141558252 ps
CPU time 0.75 seconds
Started Jul 24 05:24:46 PM PDT 24
Finished Jul 24 05:24:47 PM PDT 24
Peak memory 206636 kb
Host smart-dc7f56dd-2034-45d7-84a8-4f9403e92bb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40609
11967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.4060911967
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.3903093776
Short name T2150
Test name
Test status
Simulation time 163938932 ps
CPU time 0.83 seconds
Started Jul 24 05:24:54 PM PDT 24
Finished Jul 24 05:24:56 PM PDT 24
Peak memory 206584 kb
Host smart-fe50214b-3a17-4f5b-9e0b-bd3f1fdddf13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39030
93776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.3903093776
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.308263746
Short name T1558
Test name
Test status
Simulation time 256422738 ps
CPU time 0.94 seconds
Started Jul 24 05:24:38 PM PDT 24
Finished Jul 24 05:24:40 PM PDT 24
Peak memory 206644 kb
Host smart-9e6284ab-dfa8-4134-901a-dc1f623b7525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30826
3746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.308263746
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.3915747510
Short name T2452
Test name
Test status
Simulation time 4941753735 ps
CPU time 47 seconds
Started Jul 24 05:24:58 PM PDT 24
Finished Jul 24 05:25:45 PM PDT 24
Peak memory 206804 kb
Host smart-74858421-e3b0-44c9-ad8a-ae74fc092de6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3915747510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.3915747510
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.1496930235
Short name T1736
Test name
Test status
Simulation time 177911852 ps
CPU time 0.78 seconds
Started Jul 24 05:24:48 PM PDT 24
Finished Jul 24 05:24:49 PM PDT 24
Peak memory 206588 kb
Host smart-f36500a2-fbfd-410c-8be2-4d95fefa7edb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14969
30235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.1496930235
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.806699307
Short name T2656
Test name
Test status
Simulation time 222364019 ps
CPU time 0.88 seconds
Started Jul 24 05:24:43 PM PDT 24
Finished Jul 24 05:24:44 PM PDT 24
Peak memory 206472 kb
Host smart-90f97aaf-f514-461d-8cfe-d8fc9386216b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80669
9307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.806699307
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.92166560
Short name T340
Test name
Test status
Simulation time 721828970 ps
CPU time 1.54 seconds
Started Jul 24 05:24:56 PM PDT 24
Finished Jul 24 05:24:58 PM PDT 24
Peak memory 206820 kb
Host smart-601905c9-0471-4360-a926-afbd618ce833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92166
560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.92166560
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.2383620390
Short name T1127
Test name
Test status
Simulation time 5417616018 ps
CPU time 38.45 seconds
Started Jul 24 05:24:41 PM PDT 24
Finished Jul 24 05:25:20 PM PDT 24
Peak memory 206908 kb
Host smart-010e4d98-9263-401d-98d5-f0a824311b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23836
20390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.2383620390
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.4108888621
Short name T1612
Test name
Test status
Simulation time 116347469 ps
CPU time 0.74 seconds
Started Jul 24 05:24:50 PM PDT 24
Finished Jul 24 05:24:51 PM PDT 24
Peak memory 206616 kb
Host smart-93a6c7f1-ad09-43b0-9faf-e3f48311a297
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4108888621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.4108888621
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.3930110365
Short name T481
Test name
Test status
Simulation time 3867996380 ps
CPU time 4.59 seconds
Started Jul 24 05:24:41 PM PDT 24
Finished Jul 24 05:24:46 PM PDT 24
Peak memory 206692 kb
Host smart-06691fe6-626d-4bbd-8baa-790d72fdb406
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3930110365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.3930110365
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.624066678
Short name T1641
Test name
Test status
Simulation time 13344935274 ps
CPU time 16.27 seconds
Started Jul 24 05:24:49 PM PDT 24
Finished Jul 24 05:25:05 PM PDT 24
Peak memory 206732 kb
Host smart-312c8b4e-3cf3-4d7a-9d26-4454e0e68f9e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=624066678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.624066678
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.2824577331
Short name T2300
Test name
Test status
Simulation time 23418714737 ps
CPU time 21.65 seconds
Started Jul 24 05:24:41 PM PDT 24
Finished Jul 24 05:25:03 PM PDT 24
Peak memory 207028 kb
Host smart-8021b0d8-09a2-42da-a823-62dc56f0a6dd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2824577331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.2824577331
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.2962106063
Short name T2011
Test name
Test status
Simulation time 200274787 ps
CPU time 0.8 seconds
Started Jul 24 05:24:44 PM PDT 24
Finished Jul 24 05:24:45 PM PDT 24
Peak memory 206592 kb
Host smart-39a0c459-bee2-4310-95db-861559538fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29621
06063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2962106063
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.135102299
Short name T1191
Test name
Test status
Simulation time 190375143 ps
CPU time 0.77 seconds
Started Jul 24 05:24:46 PM PDT 24
Finished Jul 24 05:24:47 PM PDT 24
Peak memory 206592 kb
Host smart-f85551a8-32f1-4c65-95f3-300001bb2266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13510
2299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.135102299
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.2074770259
Short name T883
Test name
Test status
Simulation time 492609863 ps
CPU time 1.51 seconds
Started Jul 24 05:24:43 PM PDT 24
Finished Jul 24 05:24:45 PM PDT 24
Peak memory 206776 kb
Host smart-298dfa92-8183-4da5-871d-742b4a673c26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20747
70259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.2074770259
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.1749992884
Short name T2454
Test name
Test status
Simulation time 1368476329 ps
CPU time 2.88 seconds
Started Jul 24 05:24:44 PM PDT 24
Finished Jul 24 05:24:47 PM PDT 24
Peak memory 206808 kb
Host smart-35009d60-1dcf-4229-b358-9b4c19e48b24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17499
92884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.1749992884
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.246109125
Short name T2252
Test name
Test status
Simulation time 12580335011 ps
CPU time 26.13 seconds
Started Jul 24 05:25:01 PM PDT 24
Finished Jul 24 05:25:27 PM PDT 24
Peak memory 206996 kb
Host smart-6c5f1e3a-0ca5-417d-9917-d61bc0a67b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24610
9125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.246109125
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.1810585204
Short name T756
Test name
Test status
Simulation time 445460754 ps
CPU time 1.21 seconds
Started Jul 24 05:24:42 PM PDT 24
Finished Jul 24 05:24:44 PM PDT 24
Peak memory 206572 kb
Host smart-0bd6d468-d325-4637-b20d-fc2eecb8df3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18105
85204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.1810585204
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.3424870772
Short name T1979
Test name
Test status
Simulation time 139319211 ps
CPU time 0.74 seconds
Started Jul 24 05:24:50 PM PDT 24
Finished Jul 24 05:24:50 PM PDT 24
Peak memory 206532 kb
Host smart-57fb03b6-ea8e-4ede-9eb2-1faf5992dda9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34248
70772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.3424870772
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.2283186206
Short name T2134
Test name
Test status
Simulation time 37221353 ps
CPU time 0.67 seconds
Started Jul 24 05:24:38 PM PDT 24
Finished Jul 24 05:24:39 PM PDT 24
Peak memory 206600 kb
Host smart-91ddab04-15d6-40ed-854b-fd1b2c06deb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22831
86206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.2283186206
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.612224697
Short name T1424
Test name
Test status
Simulation time 964522055 ps
CPU time 2.22 seconds
Started Jul 24 05:24:38 PM PDT 24
Finished Jul 24 05:24:41 PM PDT 24
Peak memory 206844 kb
Host smart-7e12c2ac-a7e5-48db-94a8-abd6aed8531b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61222
4697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.612224697
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.640951445
Short name T1987
Test name
Test status
Simulation time 237949168 ps
CPU time 1.63 seconds
Started Jul 24 05:24:41 PM PDT 24
Finished Jul 24 05:24:43 PM PDT 24
Peak memory 206800 kb
Host smart-6c7fb259-9b4b-400c-afdb-d782d8798391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64095
1445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.640951445
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.2042620999
Short name T2037
Test name
Test status
Simulation time 220526630 ps
CPU time 0.88 seconds
Started Jul 24 05:24:39 PM PDT 24
Finished Jul 24 05:24:40 PM PDT 24
Peak memory 206576 kb
Host smart-831557cd-9c18-449d-ab21-cee03b4005bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20426
20999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.2042620999
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.3068724200
Short name T2700
Test name
Test status
Simulation time 151226250 ps
CPU time 0.8 seconds
Started Jul 24 05:24:44 PM PDT 24
Finished Jul 24 05:24:45 PM PDT 24
Peak memory 206576 kb
Host smart-b9ebb763-1c9e-4b45-88b8-1c2f2b6d8cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30687
24200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.3068724200
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.2427497866
Short name T1106
Test name
Test status
Simulation time 187934578 ps
CPU time 0.86 seconds
Started Jul 24 05:25:02 PM PDT 24
Finished Jul 24 05:25:03 PM PDT 24
Peak memory 206432 kb
Host smart-53ef4b9b-e202-49dc-8cdb-b051c0266dd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24274
97866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.2427497866
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_iso_retraction.2767132430
Short name T2465
Test name
Test status
Simulation time 4446816743 ps
CPU time 33.94 seconds
Started Jul 24 05:24:44 PM PDT 24
Finished Jul 24 05:25:18 PM PDT 24
Peak memory 206948 kb
Host smart-861d1be2-92cd-4144-8ca9-290ddafdd69a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27671
32430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.2767132430
Directory /workspace/7.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.3998412077
Short name T1581
Test name
Test status
Simulation time 232683347 ps
CPU time 0.91 seconds
Started Jul 24 05:24:42 PM PDT 24
Finished Jul 24 05:24:43 PM PDT 24
Peak memory 206504 kb
Host smart-b3e9c289-f57b-40da-99b6-dbbe669e6def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39984
12077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.3998412077
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.3952853499
Short name T670
Test name
Test status
Simulation time 23309873365 ps
CPU time 23.22 seconds
Started Jul 24 05:24:45 PM PDT 24
Finished Jul 24 05:25:08 PM PDT 24
Peak memory 206708 kb
Host smart-1987047b-58c9-47cb-b310-1098688b67a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39528
53499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.3952853499
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.1207725364
Short name T2682
Test name
Test status
Simulation time 3353416534 ps
CPU time 4.21 seconds
Started Jul 24 05:24:53 PM PDT 24
Finished Jul 24 05:24:57 PM PDT 24
Peak memory 206716 kb
Host smart-74c6c602-c074-4767-a17d-f77c578d6463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12077
25364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.1207725364
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.3901439994
Short name T2491
Test name
Test status
Simulation time 9126531528 ps
CPU time 85.69 seconds
Started Jul 24 05:25:05 PM PDT 24
Finished Jul 24 05:26:31 PM PDT 24
Peak memory 206936 kb
Host smart-f9ab32a5-6fa3-4f3a-8956-0cdd73acbc03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39014
39994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.3901439994
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.2205897884
Short name T2420
Test name
Test status
Simulation time 5081332972 ps
CPU time 42.52 seconds
Started Jul 24 05:24:58 PM PDT 24
Finished Jul 24 05:25:40 PM PDT 24
Peak memory 206880 kb
Host smart-9eb86f66-ed4f-48dd-937a-f9006f421c8b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2205897884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.2205897884
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.3875033681
Short name T1399
Test name
Test status
Simulation time 257956731 ps
CPU time 0.89 seconds
Started Jul 24 05:24:38 PM PDT 24
Finished Jul 24 05:24:39 PM PDT 24
Peak memory 206560 kb
Host smart-0f176142-09eb-4e67-829c-8e4ef5d43ed0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3875033681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.3875033681
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.13384452
Short name T1848
Test name
Test status
Simulation time 211019618 ps
CPU time 0.86 seconds
Started Jul 24 05:24:44 PM PDT 24
Finished Jul 24 05:24:45 PM PDT 24
Peak memory 206588 kb
Host smart-4e32ef54-26ae-4331-9c64-bc672425363d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13384
452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.13384452
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.966641447
Short name T33
Test name
Test status
Simulation time 5731872206 ps
CPU time 161.99 seconds
Started Jul 24 05:24:57 PM PDT 24
Finished Jul 24 05:27:39 PM PDT 24
Peak memory 206976 kb
Host smart-31d941b0-d03a-48c5-bc21-555868cd85a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96664
1447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.966641447
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.1539062924
Short name T2146
Test name
Test status
Simulation time 3490696653 ps
CPU time 22.71 seconds
Started Jul 24 05:24:41 PM PDT 24
Finished Jul 24 05:25:04 PM PDT 24
Peak memory 206992 kb
Host smart-1071449b-2a4f-4cd4-9491-9bc547cfa7e6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1539062924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.1539062924
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.3112686016
Short name T1902
Test name
Test status
Simulation time 234149556 ps
CPU time 0.87 seconds
Started Jul 24 05:24:50 PM PDT 24
Finished Jul 24 05:24:51 PM PDT 24
Peak memory 206752 kb
Host smart-e0ae5cd4-68bd-4c7d-922c-facbf83821c8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3112686016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.3112686016
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.3885670062
Short name T231
Test name
Test status
Simulation time 167910539 ps
CPU time 0.77 seconds
Started Jul 24 05:24:41 PM PDT 24
Finished Jul 24 05:24:42 PM PDT 24
Peak memory 206600 kb
Host smart-e6bda954-8e1c-43d1-b725-4983fff247c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38856
70062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.3885670062
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.3465648384
Short name T1408
Test name
Test status
Simulation time 236957790 ps
CPU time 0.88 seconds
Started Jul 24 05:24:45 PM PDT 24
Finished Jul 24 05:24:47 PM PDT 24
Peak memory 206588 kb
Host smart-da946d8f-3e43-48e3-ba95-89339bdaa194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34656
48384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.3465648384
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.1957870797
Short name T2236
Test name
Test status
Simulation time 189837141 ps
CPU time 0.84 seconds
Started Jul 24 05:24:56 PM PDT 24
Finished Jul 24 05:24:57 PM PDT 24
Peak memory 206592 kb
Host smart-966e4a3a-8e48-4a02-8db6-f5d176d220ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19578
70797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.1957870797
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.1208117867
Short name T1495
Test name
Test status
Simulation time 191016462 ps
CPU time 0.77 seconds
Started Jul 24 05:25:06 PM PDT 24
Finished Jul 24 05:25:07 PM PDT 24
Peak memory 206616 kb
Host smart-6d585683-3989-4c3a-b613-4cd2a006123c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12081
17867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.1208117867
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.922870446
Short name T724
Test name
Test status
Simulation time 189053274 ps
CPU time 0.82 seconds
Started Jul 24 05:24:58 PM PDT 24
Finished Jul 24 05:24:59 PM PDT 24
Peak memory 206596 kb
Host smart-47658b47-6687-4034-abe4-cad16ca5d27b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92287
0446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.922870446
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.2611862291
Short name T2024
Test name
Test status
Simulation time 151701911 ps
CPU time 0.78 seconds
Started Jul 24 05:24:54 PM PDT 24
Finished Jul 24 05:24:55 PM PDT 24
Peak memory 206548 kb
Host smart-096591f6-0e10-45f7-a66e-b12f1d37a983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26118
62291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.2611862291
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.1177422763
Short name T1288
Test name
Test status
Simulation time 230213366 ps
CPU time 0.92 seconds
Started Jul 24 05:24:48 PM PDT 24
Finished Jul 24 05:24:49 PM PDT 24
Peak memory 206656 kb
Host smart-136452ee-15a6-4d17-a29c-b5d0937832ab
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1177422763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.1177422763
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.4093371274
Short name T376
Test name
Test status
Simulation time 182618997 ps
CPU time 0.83 seconds
Started Jul 24 05:24:56 PM PDT 24
Finished Jul 24 05:24:56 PM PDT 24
Peak memory 206580 kb
Host smart-3b3ad279-f475-48b4-86b0-82d5a36a0234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40933
71274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.4093371274
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.1258370796
Short name T2055
Test name
Test status
Simulation time 49351414 ps
CPU time 0.67 seconds
Started Jul 24 05:24:43 PM PDT 24
Finished Jul 24 05:24:44 PM PDT 24
Peak memory 206572 kb
Host smart-430bf794-d1ef-4d38-9f51-d5a9de31985c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12583
70796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.1258370796
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.1903332013
Short name T2325
Test name
Test status
Simulation time 20563105929 ps
CPU time 52.67 seconds
Started Jul 24 05:24:40 PM PDT 24
Finished Jul 24 05:25:33 PM PDT 24
Peak memory 206996 kb
Host smart-aed046d3-e109-4e78-8ac2-390a4419c162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19033
32013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.1903332013
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.2224618330
Short name T1389
Test name
Test status
Simulation time 180121271 ps
CPU time 0.82 seconds
Started Jul 24 05:24:48 PM PDT 24
Finished Jul 24 05:24:49 PM PDT 24
Peak memory 206624 kb
Host smart-31bd8370-45a8-4d0c-b5d3-877f34f0001f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22246
18330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.2224618330
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.1408147614
Short name T625
Test name
Test status
Simulation time 211339519 ps
CPU time 0.86 seconds
Started Jul 24 05:24:55 PM PDT 24
Finished Jul 24 05:24:56 PM PDT 24
Peak memory 206776 kb
Host smart-5194b7a2-9d48-4734-bd7c-cf6da4acaa20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14081
47614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.1408147614
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.2749858962
Short name T1568
Test name
Test status
Simulation time 12625529659 ps
CPU time 65.58 seconds
Started Jul 24 05:24:40 PM PDT 24
Finished Jul 24 05:25:46 PM PDT 24
Peak memory 207000 kb
Host smart-16d985ef-4382-48ac-8a08-34890370e4ea
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2749858962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.2749858962
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.1972511485
Short name T2748
Test name
Test status
Simulation time 7232684061 ps
CPU time 37.74 seconds
Started Jul 24 05:24:54 PM PDT 24
Finished Jul 24 05:25:32 PM PDT 24
Peak memory 206848 kb
Host smart-4dd37fe5-eae8-4f4b-8bdf-c830f53ee698
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1972511485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.1972511485
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.2581097338
Short name T1616
Test name
Test status
Simulation time 11464575034 ps
CPU time 227.13 seconds
Started Jul 24 05:24:55 PM PDT 24
Finished Jul 24 05:28:43 PM PDT 24
Peak memory 206844 kb
Host smart-b10745c4-68e9-4b48-9d3c-a80b5dde1412
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2581097338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.2581097338
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.1731206805
Short name T1485
Test name
Test status
Simulation time 239727929 ps
CPU time 0.86 seconds
Started Jul 24 05:24:49 PM PDT 24
Finished Jul 24 05:24:50 PM PDT 24
Peak memory 206600 kb
Host smart-2e5409a3-a9b6-4e90-971f-77c9c60984f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17312
06805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.1731206805
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.1898263956
Short name T1023
Test name
Test status
Simulation time 151892086 ps
CPU time 0.86 seconds
Started Jul 24 05:24:41 PM PDT 24
Finished Jul 24 05:24:43 PM PDT 24
Peak memory 206592 kb
Host smart-125eb21c-8d5f-4aa2-9b21-8e0934657244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18982
63956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.1898263956
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.1380723290
Short name T872
Test name
Test status
Simulation time 172397070 ps
CPU time 0.78 seconds
Started Jul 24 05:24:41 PM PDT 24
Finished Jul 24 05:24:42 PM PDT 24
Peak memory 206608 kb
Host smart-b63b7ed3-e2b7-49de-8e6d-ffab38a23bdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13807
23290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.1380723290
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.1718175880
Short name T1163
Test name
Test status
Simulation time 154641212 ps
CPU time 0.81 seconds
Started Jul 24 05:24:49 PM PDT 24
Finished Jul 24 05:24:50 PM PDT 24
Peak memory 206532 kb
Host smart-d6a729bc-9e94-4a8f-8fe6-b45923d94ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17181
75880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.1718175880
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.2592105540
Short name T1917
Test name
Test status
Simulation time 158997788 ps
CPU time 0.76 seconds
Started Jul 24 05:24:39 PM PDT 24
Finished Jul 24 05:24:41 PM PDT 24
Peak memory 206580 kb
Host smart-11fa0b94-0381-4621-a2cf-8bfd1fb88b71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25921
05540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.2592105540
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.227908548
Short name T730
Test name
Test status
Simulation time 211130329 ps
CPU time 0.91 seconds
Started Jul 24 05:24:42 PM PDT 24
Finished Jul 24 05:24:44 PM PDT 24
Peak memory 206392 kb
Host smart-f2e89952-ac23-400f-8b05-29a181745763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22790
8548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.227908548
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.2383931708
Short name T1994
Test name
Test status
Simulation time 3683544681 ps
CPU time 104.05 seconds
Started Jul 24 05:24:40 PM PDT 24
Finished Jul 24 05:26:24 PM PDT 24
Peak memory 206984 kb
Host smart-61980a31-3117-48d6-b1cb-09686381359c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2383931708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.2383931708
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.1624813900
Short name T378
Test name
Test status
Simulation time 175493769 ps
CPU time 0.8 seconds
Started Jul 24 05:24:44 PM PDT 24
Finished Jul 24 05:24:45 PM PDT 24
Peak memory 206592 kb
Host smart-86a0278c-056d-410b-a3fd-44ac16176449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16248
13900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.1624813900
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.2627467008
Short name T2390
Test name
Test status
Simulation time 782641955 ps
CPU time 1.75 seconds
Started Jul 24 05:24:45 PM PDT 24
Finished Jul 24 05:24:47 PM PDT 24
Peak memory 206828 kb
Host smart-499694ac-d957-4c75-8673-9937514881ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26274
67008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.2627467008
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.1961125109
Short name T856
Test name
Test status
Simulation time 3859805536 ps
CPU time 97.22 seconds
Started Jul 24 05:24:45 PM PDT 24
Finished Jul 24 05:26:23 PM PDT 24
Peak memory 206896 kb
Host smart-a2d61ea1-e99b-4c3e-84e4-cd2cdb101a1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19611
25109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.1961125109
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.1856431132
Short name T2678
Test name
Test status
Simulation time 91679158 ps
CPU time 0.7 seconds
Started Jul 24 05:24:46 PM PDT 24
Finished Jul 24 05:24:47 PM PDT 24
Peak memory 206572 kb
Host smart-d310d0ec-cf83-4346-9aae-8c9fb0758e07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1856431132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.1856431132
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.2214978353
Short name T2559
Test name
Test status
Simulation time 4213777989 ps
CPU time 4.51 seconds
Started Jul 24 05:24:52 PM PDT 24
Finished Jul 24 05:24:57 PM PDT 24
Peak memory 206848 kb
Host smart-9767f9e8-0ddc-4dd0-9110-93d86bec60bd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2214978353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.2214978353
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.3636260516
Short name T503
Test name
Test status
Simulation time 13304587634 ps
CPU time 12.07 seconds
Started Jul 24 05:24:49 PM PDT 24
Finished Jul 24 05:25:01 PM PDT 24
Peak memory 206720 kb
Host smart-865d94f9-8cce-46ec-a470-78879b6cd9c0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3636260516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.3636260516
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.2099814631
Short name T1528
Test name
Test status
Simulation time 23306757916 ps
CPU time 23.71 seconds
Started Jul 24 05:25:05 PM PDT 24
Finished Jul 24 05:25:29 PM PDT 24
Peak memory 206684 kb
Host smart-1fe04497-0c4b-44d8-8989-f3a2d25e8c18
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2099814631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.2099814631
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.1467061840
Short name T2363
Test name
Test status
Simulation time 154674053 ps
CPU time 0.76 seconds
Started Jul 24 05:25:03 PM PDT 24
Finished Jul 24 05:25:04 PM PDT 24
Peak memory 206596 kb
Host smart-9680bea1-d9b0-4a01-ad06-ab1d3d9b0070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14670
61840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.1467061840
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.509328607
Short name T492
Test name
Test status
Simulation time 149657776 ps
CPU time 0.75 seconds
Started Jul 24 05:24:52 PM PDT 24
Finished Jul 24 05:24:52 PM PDT 24
Peak memory 206620 kb
Host smart-119a5f60-433b-4d6c-8056-83d9936d6530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50932
8607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.509328607
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.3199800873
Short name T1864
Test name
Test status
Simulation time 381996058 ps
CPU time 1.21 seconds
Started Jul 24 05:24:51 PM PDT 24
Finished Jul 24 05:24:53 PM PDT 24
Peak memory 206592 kb
Host smart-b3492443-2cc3-45c0-8167-b02ccfd7d817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31998
00873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.3199800873
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_device_address.530265477
Short name T2137
Test name
Test status
Simulation time 14794206689 ps
CPU time 27.7 seconds
Started Jul 24 05:24:47 PM PDT 24
Finished Jul 24 05:25:15 PM PDT 24
Peak memory 206988 kb
Host smart-e30f9f4f-e50f-4c42-b00a-4366b4e86e5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53026
5477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.530265477
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.2798297944
Short name T1510
Test name
Test status
Simulation time 348037590 ps
CPU time 1.18 seconds
Started Jul 24 05:24:44 PM PDT 24
Finished Jul 24 05:24:45 PM PDT 24
Peak memory 206376 kb
Host smart-cf904163-a9c0-47f4-9226-1458615bfb2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27982
97944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.2798297944
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.1170722451
Short name T2145
Test name
Test status
Simulation time 179719307 ps
CPU time 0.77 seconds
Started Jul 24 05:24:47 PM PDT 24
Finished Jul 24 05:24:47 PM PDT 24
Peak memory 206544 kb
Host smart-225838ac-eced-46fc-8585-fcfabbce914b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11707
22451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.1170722451
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.3887103397
Short name T2066
Test name
Test status
Simulation time 61085531 ps
CPU time 0.67 seconds
Started Jul 24 05:24:52 PM PDT 24
Finished Jul 24 05:24:53 PM PDT 24
Peak memory 206552 kb
Host smart-5e843fe5-b1a8-4856-afa5-14636cc498c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38871
03397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.3887103397
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.1528011747
Short name T1032
Test name
Test status
Simulation time 981866927 ps
CPU time 2.16 seconds
Started Jul 24 05:24:44 PM PDT 24
Finished Jul 24 05:24:47 PM PDT 24
Peak memory 206796 kb
Host smart-c9e8cff6-a61b-4b1f-b251-b27029e9320f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15280
11747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.1528011747
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.3832101983
Short name T606
Test name
Test status
Simulation time 189023521 ps
CPU time 1.26 seconds
Started Jul 24 05:24:52 PM PDT 24
Finished Jul 24 05:24:54 PM PDT 24
Peak memory 206788 kb
Host smart-47fac811-3f7a-40e5-82e9-835df077b9f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38321
01983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.3832101983
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.1851272698
Short name T1360
Test name
Test status
Simulation time 272461989 ps
CPU time 0.91 seconds
Started Jul 24 05:25:04 PM PDT 24
Finished Jul 24 05:25:05 PM PDT 24
Peak memory 206552 kb
Host smart-8c5e82ac-0675-4141-a24e-6628ed782e65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18512
72698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.1851272698
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.1300962845
Short name T2704
Test name
Test status
Simulation time 138847424 ps
CPU time 0.79 seconds
Started Jul 24 05:25:01 PM PDT 24
Finished Jul 24 05:25:02 PM PDT 24
Peak memory 206600 kb
Host smart-82b7bc93-f5ff-4db7-8743-f5e5c7024cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13009
62845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.1300962845
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.3191398629
Short name T1645
Test name
Test status
Simulation time 241337720 ps
CPU time 0.91 seconds
Started Jul 24 05:25:02 PM PDT 24
Finished Jul 24 05:25:03 PM PDT 24
Peak memory 206476 kb
Host smart-5efd8a86-07dd-4264-be3e-676ad9395d05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31913
98629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.3191398629
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.3805858644
Short name T1663
Test name
Test status
Simulation time 179218385 ps
CPU time 0.9 seconds
Started Jul 24 05:25:03 PM PDT 24
Finished Jul 24 05:25:04 PM PDT 24
Peak memory 206584 kb
Host smart-030f0f24-2376-4a53-b121-45517824f8dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38058
58644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.3805858644
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.2845653967
Short name T521
Test name
Test status
Simulation time 23301692552 ps
CPU time 21.67 seconds
Started Jul 24 05:24:50 PM PDT 24
Finished Jul 24 05:25:12 PM PDT 24
Peak memory 206640 kb
Host smart-be2b1915-ecf7-44f5-89f7-064e16c06a85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28456
53967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.2845653967
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.553978353
Short name T2266
Test name
Test status
Simulation time 3291809350 ps
CPU time 3.93 seconds
Started Jul 24 05:24:54 PM PDT 24
Finished Jul 24 05:24:58 PM PDT 24
Peak memory 206716 kb
Host smart-607153e0-aaa4-44d9-bf53-4b849d550dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55397
8353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.553978353
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.3853647702
Short name T696
Test name
Test status
Simulation time 11790485625 ps
CPU time 84.9 seconds
Started Jul 24 05:24:53 PM PDT 24
Finished Jul 24 05:26:19 PM PDT 24
Peak memory 206952 kb
Host smart-d8c125ca-2322-400b-b476-c4e89b8c2e80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38536
47702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.3853647702
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.3582223626
Short name T2564
Test name
Test status
Simulation time 4289715399 ps
CPU time 40.4 seconds
Started Jul 24 05:25:07 PM PDT 24
Finished Jul 24 05:25:47 PM PDT 24
Peak memory 206848 kb
Host smart-945eda6b-39d5-43c4-9d16-c9ae6965222c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3582223626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.3582223626
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.32664496
Short name T1339
Test name
Test status
Simulation time 242024416 ps
CPU time 0.9 seconds
Started Jul 24 05:24:47 PM PDT 24
Finished Jul 24 05:24:48 PM PDT 24
Peak memory 206408 kb
Host smart-b0b6a3f5-08d7-4254-94fd-872ce5034e7c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=32664496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.32664496
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.1701531344
Short name T2730
Test name
Test status
Simulation time 191292259 ps
CPU time 0.92 seconds
Started Jul 24 05:25:02 PM PDT 24
Finished Jul 24 05:25:03 PM PDT 24
Peak memory 206580 kb
Host smart-bf087ead-d8b2-4524-9b5b-fdf70998d12e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17015
31344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.1701531344
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.1933892762
Short name T806
Test name
Test status
Simulation time 6146751367 ps
CPU time 42.76 seconds
Started Jul 24 05:24:58 PM PDT 24
Finished Jul 24 05:25:41 PM PDT 24
Peak memory 206996 kb
Host smart-c88e02ac-3e5d-447b-8c55-f56a0a39b545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19338
92762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.1933892762
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.3257164306
Short name T1578
Test name
Test status
Simulation time 7275297328 ps
CPU time 67.7 seconds
Started Jul 24 05:24:56 PM PDT 24
Finished Jul 24 05:26:04 PM PDT 24
Peak memory 206908 kb
Host smart-29e0bab2-5b50-40ad-8769-e08525aa5702
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3257164306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.3257164306
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.711428626
Short name T1814
Test name
Test status
Simulation time 162556983 ps
CPU time 0.77 seconds
Started Jul 24 05:25:04 PM PDT 24
Finished Jul 24 05:25:04 PM PDT 24
Peak memory 206576 kb
Host smart-3e6d0375-4c36-41ef-9e74-3d36b2e6d497
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=711428626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.711428626
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.3501989071
Short name T1335
Test name
Test status
Simulation time 156610074 ps
CPU time 0.78 seconds
Started Jul 24 05:25:06 PM PDT 24
Finished Jul 24 05:25:07 PM PDT 24
Peak memory 206612 kb
Host smart-f5084359-cd4b-40f2-8227-c650b9831910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35019
89071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.3501989071
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.1703309969
Short name T2653
Test name
Test status
Simulation time 202768317 ps
CPU time 0.83 seconds
Started Jul 24 05:25:03 PM PDT 24
Finished Jul 24 05:25:04 PM PDT 24
Peak memory 206592 kb
Host smart-c5cac305-d9d1-4d9c-a028-ea807dd2e9cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17033
09969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.1703309969
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.1303021819
Short name T707
Test name
Test status
Simulation time 179762676 ps
CPU time 0.82 seconds
Started Jul 24 05:25:00 PM PDT 24
Finished Jul 24 05:25:01 PM PDT 24
Peak memory 206428 kb
Host smart-700ee409-5512-43a8-b829-20b21f5ce724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13030
21819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.1303021819
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.3940320307
Short name T1708
Test name
Test status
Simulation time 154196555 ps
CPU time 0.77 seconds
Started Jul 24 05:24:52 PM PDT 24
Finished Jul 24 05:24:53 PM PDT 24
Peak memory 206504 kb
Host smart-26df8754-f089-4b49-9d75-323d9893b5b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39403
20307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.3940320307
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.3373481944
Short name T2212
Test name
Test status
Simulation time 170178528 ps
CPU time 0.81 seconds
Started Jul 24 05:25:05 PM PDT 24
Finished Jul 24 05:25:06 PM PDT 24
Peak memory 206604 kb
Host smart-c3917ab3-1809-47d3-a884-7386dd3993f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33734
81944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.3373481944
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.487900622
Short name T838
Test name
Test status
Simulation time 145927087 ps
CPU time 0.78 seconds
Started Jul 24 05:25:07 PM PDT 24
Finished Jul 24 05:25:08 PM PDT 24
Peak memory 206524 kb
Host smart-d95949fa-c341-42f9-a8f0-6a113daef5d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48790
0622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.487900622
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.2472426095
Short name T1112
Test name
Test status
Simulation time 229030239 ps
CPU time 1 seconds
Started Jul 24 05:25:03 PM PDT 24
Finished Jul 24 05:25:04 PM PDT 24
Peak memory 206500 kb
Host smart-06c06c70-ad3b-4774-993e-6e765d222785
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2472426095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.2472426095
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.3181794877
Short name T459
Test name
Test status
Simulation time 198704770 ps
CPU time 0.82 seconds
Started Jul 24 05:25:01 PM PDT 24
Finished Jul 24 05:25:02 PM PDT 24
Peak memory 206628 kb
Host smart-1301d5bb-67d1-403f-a539-ded54bec884b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31817
94877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.3181794877
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.229433794
Short name T683
Test name
Test status
Simulation time 36810871 ps
CPU time 0.64 seconds
Started Jul 24 05:25:00 PM PDT 24
Finished Jul 24 05:25:01 PM PDT 24
Peak memory 206396 kb
Host smart-dfe8dbe7-9263-4b5b-81a0-685ea24044d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22943
3794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.229433794
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.2510168091
Short name T1071
Test name
Test status
Simulation time 13099688228 ps
CPU time 29.12 seconds
Started Jul 24 05:24:46 PM PDT 24
Finished Jul 24 05:25:16 PM PDT 24
Peak memory 215072 kb
Host smart-05875494-88d6-4611-bb95-0655cae744d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25101
68091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.2510168091
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.2024447679
Short name T2305
Test name
Test status
Simulation time 203419972 ps
CPU time 0.84 seconds
Started Jul 24 05:24:47 PM PDT 24
Finished Jul 24 05:24:48 PM PDT 24
Peak memory 206564 kb
Host smart-42b4d6c2-69b8-4b9a-af22-95957b746c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20244
47679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.2024447679
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.2480359791
Short name T441
Test name
Test status
Simulation time 180058795 ps
CPU time 0.79 seconds
Started Jul 24 05:24:50 PM PDT 24
Finished Jul 24 05:24:51 PM PDT 24
Peak memory 206508 kb
Host smart-92d98321-f93e-4d91-ad41-7a47465fead8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24803
59791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.2480359791
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.3265185953
Short name T1257
Test name
Test status
Simulation time 5515835100 ps
CPU time 44.64 seconds
Started Jul 24 05:25:01 PM PDT 24
Finished Jul 24 05:25:46 PM PDT 24
Peak memory 206864 kb
Host smart-a6f48a7c-dd80-4907-b77d-b6bef0e03ed8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3265185953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.3265185953
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.3212800107
Short name T157
Test name
Test status
Simulation time 12238341088 ps
CPU time 86.8 seconds
Started Jul 24 05:24:58 PM PDT 24
Finished Jul 24 05:26:25 PM PDT 24
Peak memory 207000 kb
Host smart-a49de459-a072-4203-a62c-c971aefc7cf9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3212800107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.3212800107
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.1854280885
Short name T2715
Test name
Test status
Simulation time 12253728512 ps
CPU time 65.19 seconds
Started Jul 24 05:24:52 PM PDT 24
Finished Jul 24 05:25:58 PM PDT 24
Peak memory 206972 kb
Host smart-686ed580-288f-4c63-9286-5bbbd0ea4c47
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1854280885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.1854280885
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.1843088058
Short name T1103
Test name
Test status
Simulation time 159194964 ps
CPU time 0.8 seconds
Started Jul 24 05:24:50 PM PDT 24
Finished Jul 24 05:24:51 PM PDT 24
Peak memory 206556 kb
Host smart-18ef848e-4aef-4dec-bd10-1ef87834f1c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18430
88058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.1843088058
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.2323040836
Short name T948
Test name
Test status
Simulation time 195692370 ps
CPU time 0.84 seconds
Started Jul 24 05:25:01 PM PDT 24
Finished Jul 24 05:25:02 PM PDT 24
Peak memory 206616 kb
Host smart-14b171ee-3c9b-45fc-8ca7-2307d0404fe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23230
40836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.2323040836
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.3211184710
Short name T1914
Test name
Test status
Simulation time 194939145 ps
CPU time 0.79 seconds
Started Jul 24 05:25:04 PM PDT 24
Finished Jul 24 05:25:05 PM PDT 24
Peak memory 206580 kb
Host smart-f68f2820-6ef2-441b-8b83-ba8027eac77f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32111
84710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.3211184710
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.4036815936
Short name T360
Test name
Test status
Simulation time 170015937 ps
CPU time 0.78 seconds
Started Jul 24 05:24:51 PM PDT 24
Finished Jul 24 05:24:52 PM PDT 24
Peak memory 206576 kb
Host smart-39a78232-836d-4a16-9224-72317e823ad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40368
15936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.4036815936
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.3159486602
Short name T2240
Test name
Test status
Simulation time 248758177 ps
CPU time 0.95 seconds
Started Jul 24 05:25:07 PM PDT 24
Finished Jul 24 05:25:08 PM PDT 24
Peak memory 206516 kb
Host smart-871a951b-c893-4488-adaa-2dbdd010b55e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31594
86602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.3159486602
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.484233738
Short name T74
Test name
Test status
Simulation time 3718838249 ps
CPU time 25.8 seconds
Started Jul 24 05:24:51 PM PDT 24
Finished Jul 24 05:25:17 PM PDT 24
Peak memory 206804 kb
Host smart-680b2c89-3431-4b5f-81d8-a82f04c5bf7d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=484233738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.484233738
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.1754248328
Short name T1646
Test name
Test status
Simulation time 162006442 ps
CPU time 0.8 seconds
Started Jul 24 05:25:00 PM PDT 24
Finished Jul 24 05:25:01 PM PDT 24
Peak memory 206468 kb
Host smart-022ba9f0-0a5f-4ba6-bdb4-0fb555b42ab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17542
48328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.1754248328
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.1555005261
Short name T1946
Test name
Test status
Simulation time 175965464 ps
CPU time 0.8 seconds
Started Jul 24 05:25:00 PM PDT 24
Finished Jul 24 05:25:01 PM PDT 24
Peak memory 206532 kb
Host smart-157f1469-d785-4da6-8faf-6faca68cd901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15550
05261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.1555005261
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.974204235
Short name T2207
Test name
Test status
Simulation time 495262992 ps
CPU time 1.29 seconds
Started Jul 24 05:24:57 PM PDT 24
Finished Jul 24 05:24:59 PM PDT 24
Peak memory 206496 kb
Host smart-c5d8ab5a-5807-4506-8006-0bb3b617f0eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97420
4235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.974204235
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.3002975105
Short name T659
Test name
Test status
Simulation time 3642921132 ps
CPU time 24.85 seconds
Started Jul 24 05:24:55 PM PDT 24
Finished Jul 24 05:25:20 PM PDT 24
Peak memory 206800 kb
Host smart-be74b6ee-11ef-40df-a1ce-bb186ef987a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30029
75105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.3002975105
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.4121462705
Short name T173
Test name
Test status
Simulation time 34701953 ps
CPU time 0.67 seconds
Started Jul 24 05:25:02 PM PDT 24
Finished Jul 24 05:25:03 PM PDT 24
Peak memory 206648 kb
Host smart-bf52cfb6-339d-44a5-a2b6-367d3baf9064
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4121462705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.4121462705
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.1393294265
Short name T11
Test name
Test status
Simulation time 4243822362 ps
CPU time 4.86 seconds
Started Jul 24 05:25:01 PM PDT 24
Finished Jul 24 05:25:06 PM PDT 24
Peak memory 206912 kb
Host smart-6db97980-3cc8-4071-9cb4-08468dfd7f3c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1393294265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.1393294265
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.1587129682
Short name T1337
Test name
Test status
Simulation time 13412705467 ps
CPU time 15.19 seconds
Started Jul 24 05:24:48 PM PDT 24
Finished Jul 24 05:25:04 PM PDT 24
Peak memory 206712 kb
Host smart-1b0a54ba-3092-4e39-b965-0a144ca9551c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1587129682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.1587129682
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.58988256
Short name T1074
Test name
Test status
Simulation time 23326051654 ps
CPU time 27.44 seconds
Started Jul 24 05:24:53 PM PDT 24
Finished Jul 24 05:25:21 PM PDT 24
Peak memory 206808 kb
Host smart-5bb5de96-e5d3-4d3c-af12-32719b43ad75
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=58988256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.58988256
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.2295650860
Short name T1029
Test name
Test status
Simulation time 184199986 ps
CPU time 0.85 seconds
Started Jul 24 05:24:55 PM PDT 24
Finished Jul 24 05:24:56 PM PDT 24
Peak memory 206600 kb
Host smart-4237f062-1be0-4451-a67a-c8c76caff55e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22956
50860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.2295650860
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.1614630252
Short name T2712
Test name
Test status
Simulation time 148591891 ps
CPU time 0.76 seconds
Started Jul 24 05:24:55 PM PDT 24
Finished Jul 24 05:24:56 PM PDT 24
Peak memory 206532 kb
Host smart-a55db8d5-2592-4c9b-8e72-fa84cc675f18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16146
30252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.1614630252
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.116939206
Short name T1580
Test name
Test status
Simulation time 624462389 ps
CPU time 1.63 seconds
Started Jul 24 05:24:57 PM PDT 24
Finished Jul 24 05:24:59 PM PDT 24
Peak memory 206700 kb
Host smart-b70b70e6-fa6a-49c8-a281-c3e3cd0df77d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11693
9206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.116939206
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.1637110821
Short name T1582
Test name
Test status
Simulation time 557535958 ps
CPU time 1.49 seconds
Started Jul 24 05:25:14 PM PDT 24
Finished Jul 24 05:25:15 PM PDT 24
Peak memory 206584 kb
Host smart-804c6d29-6e84-447b-ae1f-117292447fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16371
10821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.1637110821
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.2299392843
Short name T1167
Test name
Test status
Simulation time 18818603697 ps
CPU time 35.62 seconds
Started Jul 24 05:25:04 PM PDT 24
Finished Jul 24 05:25:40 PM PDT 24
Peak memory 206912 kb
Host smart-37f29c86-979c-463b-9e87-916710096840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22993
92843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.2299392843
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.1453318588
Short name T2751
Test name
Test status
Simulation time 383229521 ps
CPU time 1.17 seconds
Started Jul 24 05:25:05 PM PDT 24
Finished Jul 24 05:25:07 PM PDT 24
Peak memory 206612 kb
Host smart-91d69a8d-3ee8-4c29-b1f6-f3468c305b22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14533
18588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.1453318588
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.1334449020
Short name T1696
Test name
Test status
Simulation time 143778368 ps
CPU time 0.8 seconds
Started Jul 24 05:24:58 PM PDT 24
Finished Jul 24 05:24:59 PM PDT 24
Peak memory 206564 kb
Host smart-c6f48b42-d569-4f75-8245-772b60be1403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13344
49020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.1334449020
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.1232978684
Short name T1289
Test name
Test status
Simulation time 56175965 ps
CPU time 0.65 seconds
Started Jul 24 05:25:13 PM PDT 24
Finished Jul 24 05:25:14 PM PDT 24
Peak memory 206480 kb
Host smart-4fe947b5-e3c4-4fe5-84c0-7457bf38fda8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12329
78684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.1232978684
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.290416419
Short name T655
Test name
Test status
Simulation time 737514740 ps
CPU time 1.76 seconds
Started Jul 24 05:25:06 PM PDT 24
Finished Jul 24 05:25:08 PM PDT 24
Peak memory 206744 kb
Host smart-b31cfa08-3ec0-43d2-b3de-8b0de33bc30b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29041
6419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.290416419
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.3521779902
Short name T1259
Test name
Test status
Simulation time 175644143 ps
CPU time 1.35 seconds
Started Jul 24 05:25:04 PM PDT 24
Finished Jul 24 05:25:06 PM PDT 24
Peak memory 206716 kb
Host smart-5ca0bb6b-9573-4a00-b194-b5fd77a075e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35217
79902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.3521779902
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.3048170016
Short name T1406
Test name
Test status
Simulation time 207867219 ps
CPU time 0.85 seconds
Started Jul 24 05:25:02 PM PDT 24
Finished Jul 24 05:25:03 PM PDT 24
Peak memory 206588 kb
Host smart-22c13a4c-c1f2-42b3-b25e-a8a53d4ecc65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30481
70016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.3048170016
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.2471477290
Short name T325
Test name
Test status
Simulation time 148602798 ps
CPU time 0.74 seconds
Started Jul 24 05:25:11 PM PDT 24
Finished Jul 24 05:25:12 PM PDT 24
Peak memory 206616 kb
Host smart-04c0c806-9fe0-4c54-8b17-ff7745a98a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24714
77290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.2471477290
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.4115621708
Short name T351
Test name
Test status
Simulation time 173610522 ps
CPU time 0.87 seconds
Started Jul 24 05:25:02 PM PDT 24
Finished Jul 24 05:25:03 PM PDT 24
Peak memory 206532 kb
Host smart-5ce0e484-6a5f-4bf3-948f-e7ec1a515289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41156
21708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.4115621708
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_iso_retraction.3829952422
Short name T1178
Test name
Test status
Simulation time 7815275554 ps
CPU time 31.47 seconds
Started Jul 24 05:25:05 PM PDT 24
Finished Jul 24 05:25:37 PM PDT 24
Peak memory 206844 kb
Host smart-4fba881e-1f96-4a6e-8a7e-398f8076a416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38299
52422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.3829952422
Directory /workspace/9.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.1108333959
Short name T2429
Test name
Test status
Simulation time 192367672 ps
CPU time 0.83 seconds
Started Jul 24 05:25:04 PM PDT 24
Finished Jul 24 05:25:06 PM PDT 24
Peak memory 206588 kb
Host smart-0fb91508-e3be-46ca-b99b-143cd3fc4fda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11083
33959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.1108333959
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.1327594613
Short name T1051
Test name
Test status
Simulation time 23313874495 ps
CPU time 20.97 seconds
Started Jul 24 05:25:03 PM PDT 24
Finished Jul 24 05:25:24 PM PDT 24
Peak memory 206496 kb
Host smart-8605b36b-36ef-47ea-bc3d-a808edbc3aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13275
94613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.1327594613
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.2572627474
Short name T306
Test name
Test status
Simulation time 3284713877 ps
CPU time 3.62 seconds
Started Jul 24 05:25:06 PM PDT 24
Finished Jul 24 05:25:09 PM PDT 24
Peak memory 206612 kb
Host smart-68b1a5cc-1f50-41f7-8478-8969f25ee0d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25726
27474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.2572627474
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.2706497230
Short name T678
Test name
Test status
Simulation time 9037677644 ps
CPU time 62.22 seconds
Started Jul 24 05:25:02 PM PDT 24
Finished Jul 24 05:26:05 PM PDT 24
Peak memory 206948 kb
Host smart-13354cfe-2c49-476b-b3ff-03c342200486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27064
97230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.2706497230
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.4271887437
Short name T2155
Test name
Test status
Simulation time 4391471271 ps
CPU time 113.17 seconds
Started Jul 24 05:25:01 PM PDT 24
Finished Jul 24 05:26:55 PM PDT 24
Peak memory 206896 kb
Host smart-99b3a252-3ca6-453b-9eb3-a46091d6a149
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4271887437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.4271887437
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.822082705
Short name T2138
Test name
Test status
Simulation time 255132309 ps
CPU time 0.95 seconds
Started Jul 24 05:25:03 PM PDT 24
Finished Jul 24 05:25:04 PM PDT 24
Peak memory 206604 kb
Host smart-90afeb78-2bba-4d23-a70b-04a11487008a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=822082705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.822082705
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.3169657509
Short name T1168
Test name
Test status
Simulation time 250577736 ps
CPU time 0.88 seconds
Started Jul 24 05:25:08 PM PDT 24
Finished Jul 24 05:25:09 PM PDT 24
Peak memory 206580 kb
Host smart-9140c507-7d84-4ba7-903f-0434d180e336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31696
57509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.3169657509
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.4076393342
Short name T146
Test name
Test status
Simulation time 4159961926 ps
CPU time 36.87 seconds
Started Jul 24 05:25:09 PM PDT 24
Finished Jul 24 05:25:46 PM PDT 24
Peak memory 206848 kb
Host smart-a58e6bd1-b7f2-4093-b853-425405f0fae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40763
93342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.4076393342
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.1363356057
Short name T307
Test name
Test status
Simulation time 6507553065 ps
CPU time 191.21 seconds
Started Jul 24 05:25:10 PM PDT 24
Finished Jul 24 05:28:21 PM PDT 24
Peak memory 206920 kb
Host smart-e66d3b09-007d-4157-8d95-7f74677b5b00
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1363356057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.1363356057
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.3718363821
Short name T1420
Test name
Test status
Simulation time 199033747 ps
CPU time 0.79 seconds
Started Jul 24 05:25:10 PM PDT 24
Finished Jul 24 05:25:11 PM PDT 24
Peak memory 206548 kb
Host smart-37dcdf8b-8ebb-4df5-9eff-6e5f24cc9de9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3718363821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.3718363821
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.3813694912
Short name T2352
Test name
Test status
Simulation time 155218557 ps
CPU time 0.77 seconds
Started Jul 24 05:25:09 PM PDT 24
Finished Jul 24 05:25:10 PM PDT 24
Peak memory 206596 kb
Host smart-2ab2969b-9f23-455a-a4ae-8e542c8330de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38136
94912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.3813694912
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.28897700
Short name T2336
Test name
Test status
Simulation time 218024753 ps
CPU time 0.87 seconds
Started Jul 24 05:25:07 PM PDT 24
Finished Jul 24 05:25:08 PM PDT 24
Peak memory 206548 kb
Host smart-d91946d9-0f80-4da3-8854-57135575cd09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28897
700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.28897700
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.2174032176
Short name T1385
Test name
Test status
Simulation time 159569335 ps
CPU time 0.75 seconds
Started Jul 24 05:25:20 PM PDT 24
Finished Jul 24 05:25:21 PM PDT 24
Peak memory 206588 kb
Host smart-176a550b-ac6d-44f5-8983-e002e1cfce6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21740
32176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.2174032176
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.4156994277
Short name T389
Test name
Test status
Simulation time 182886737 ps
CPU time 0.86 seconds
Started Jul 24 05:25:04 PM PDT 24
Finished Jul 24 05:25:05 PM PDT 24
Peak memory 206576 kb
Host smart-00458140-3003-4477-a54f-e1f3711ed072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41569
94277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.4156994277
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.1739765601
Short name T2296
Test name
Test status
Simulation time 185272394 ps
CPU time 0.85 seconds
Started Jul 24 05:25:05 PM PDT 24
Finished Jul 24 05:25:06 PM PDT 24
Peak memory 206564 kb
Host smart-01be999a-1f54-47cf-8640-c963b8500611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17397
65601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.1739765601
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.4175515271
Short name T169
Test name
Test status
Simulation time 159331832 ps
CPU time 0.76 seconds
Started Jul 24 05:25:03 PM PDT 24
Finished Jul 24 05:25:04 PM PDT 24
Peak memory 206576 kb
Host smart-61de2a85-af5c-459e-830d-684f23cd61be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41755
15271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.4175515271
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.3153177774
Short name T1779
Test name
Test status
Simulation time 236908615 ps
CPU time 0.96 seconds
Started Jul 24 05:25:06 PM PDT 24
Finished Jul 24 05:25:07 PM PDT 24
Peak memory 206556 kb
Host smart-a1b2e329-e96c-4e28-8d61-223af939e247
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3153177774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.3153177774
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.3212581966
Short name T1811
Test name
Test status
Simulation time 167962341 ps
CPU time 0.78 seconds
Started Jul 24 05:25:07 PM PDT 24
Finished Jul 24 05:25:08 PM PDT 24
Peak memory 206572 kb
Host smart-4f377198-aa82-4f3f-9573-5526a2172d27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32125
81966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.3212581966
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.1607524407
Short name T27
Test name
Test status
Simulation time 57659541 ps
CPU time 0.64 seconds
Started Jul 24 05:25:05 PM PDT 24
Finished Jul 24 05:25:06 PM PDT 24
Peak memory 206376 kb
Host smart-de2bbf50-cb68-42dc-bbfc-d1775c608dc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16075
24407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.1607524407
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.4089919346
Short name T1701
Test name
Test status
Simulation time 6877618693 ps
CPU time 16.42 seconds
Started Jul 24 05:25:06 PM PDT 24
Finished Jul 24 05:25:22 PM PDT 24
Peak memory 215096 kb
Host smart-c535753a-b4a6-422f-9f01-fbf9238511e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40899
19346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.4089919346
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.1867969412
Short name T1613
Test name
Test status
Simulation time 211899622 ps
CPU time 0.87 seconds
Started Jul 24 05:25:08 PM PDT 24
Finished Jul 24 05:25:09 PM PDT 24
Peak memory 206548 kb
Host smart-c59350c6-a454-4f63-8ae0-19f0cfca1eb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18679
69412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.1867969412
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.3960026188
Short name T1666
Test name
Test status
Simulation time 234182070 ps
CPU time 0.87 seconds
Started Jul 24 05:25:09 PM PDT 24
Finished Jul 24 05:25:10 PM PDT 24
Peak memory 206592 kb
Host smart-dc673f42-fe17-48f9-a76b-38ea9b69284a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39600
26188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.3960026188
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.4290504344
Short name T2067
Test name
Test status
Simulation time 13511848475 ps
CPU time 91.74 seconds
Started Jul 24 05:25:17 PM PDT 24
Finished Jul 24 05:26:49 PM PDT 24
Peak memory 206924 kb
Host smart-828b7b11-7ae3-4b7d-b338-aaf3f655f4c2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4290504344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.4290504344
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.3181549454
Short name T153
Test name
Test status
Simulation time 10332210787 ps
CPU time 62.2 seconds
Started Jul 24 05:25:03 PM PDT 24
Finished Jul 24 05:26:06 PM PDT 24
Peak memory 206864 kb
Host smart-068b2c15-e88c-4c40-99bc-083255d52717
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3181549454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.3181549454
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.2329690366
Short name T819
Test name
Test status
Simulation time 6939517355 ps
CPU time 97.4 seconds
Started Jul 24 05:24:58 PM PDT 24
Finished Jul 24 05:26:36 PM PDT 24
Peak memory 206896 kb
Host smart-27aa0151-88fd-443c-b9f9-02ec8a53e055
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2329690366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.2329690366
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.1964453703
Short name T2029
Test name
Test status
Simulation time 310463923 ps
CPU time 0.94 seconds
Started Jul 24 05:25:08 PM PDT 24
Finished Jul 24 05:25:10 PM PDT 24
Peak memory 206536 kb
Host smart-ba9bdd68-f4f9-43e4-a263-4dd0d1c3c7f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19644
53703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.1964453703
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.2343736130
Short name T341
Test name
Test status
Simulation time 138394717 ps
CPU time 0.75 seconds
Started Jul 24 05:25:06 PM PDT 24
Finished Jul 24 05:25:07 PM PDT 24
Peak memory 206568 kb
Host smart-a00735bd-33ac-4cdb-9d06-faea8c77ff2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23437
36130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.2343736130
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.2234442327
Short name T423
Test name
Test status
Simulation time 142192199 ps
CPU time 0.75 seconds
Started Jul 24 05:25:06 PM PDT 24
Finished Jul 24 05:25:07 PM PDT 24
Peak memory 206636 kb
Host smart-089b4e6b-48bc-47e9-bc3d-04e4c6d2463f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22344
42327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.2234442327
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.825778333
Short name T405
Test name
Test status
Simulation time 157312503 ps
CPU time 0.76 seconds
Started Jul 24 05:25:10 PM PDT 24
Finished Jul 24 05:25:11 PM PDT 24
Peak memory 206568 kb
Host smart-f7690cde-f4ed-45d7-beb4-2be2448aa3f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82577
8333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.825778333
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.1233733045
Short name T1194
Test name
Test status
Simulation time 154454426 ps
CPU time 0.75 seconds
Started Jul 24 05:25:10 PM PDT 24
Finished Jul 24 05:25:11 PM PDT 24
Peak memory 206224 kb
Host smart-10b98c9e-a423-4c68-9e7e-737ae8cf138e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12337
33045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.1233733045
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.1410812344
Short name T1413
Test name
Test status
Simulation time 222287997 ps
CPU time 0.87 seconds
Started Jul 24 05:25:09 PM PDT 24
Finished Jul 24 05:25:10 PM PDT 24
Peak memory 206544 kb
Host smart-7ccb431f-1665-49b6-8fb0-865523cd91dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14108
12344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.1410812344
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.635598164
Short name T2498
Test name
Test status
Simulation time 6168792616 ps
CPU time 60.03 seconds
Started Jul 24 05:25:06 PM PDT 24
Finished Jul 24 05:26:07 PM PDT 24
Peak memory 206880 kb
Host smart-d40bb750-767e-402c-9c52-ffd5eb6b2217
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=635598164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.635598164
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.2333721990
Short name T1882
Test name
Test status
Simulation time 197366205 ps
CPU time 0.81 seconds
Started Jul 24 05:25:04 PM PDT 24
Finished Jul 24 05:25:06 PM PDT 24
Peak memory 206568 kb
Host smart-3572d404-25bb-40ee-980e-15baeb96324a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23337
21990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.2333721990
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.3861307253
Short name T1361
Test name
Test status
Simulation time 220538492 ps
CPU time 0.92 seconds
Started Jul 24 05:25:11 PM PDT 24
Finished Jul 24 05:25:12 PM PDT 24
Peak memory 206640 kb
Host smart-838ccf29-c6aa-405f-8794-0ba743e444aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38613
07253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.3861307253
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.3672507320
Short name T309
Test name
Test status
Simulation time 1179361003 ps
CPU time 2.47 seconds
Started Jul 24 05:25:04 PM PDT 24
Finished Jul 24 05:25:07 PM PDT 24
Peak memory 206820 kb
Host smart-986ae746-7fa6-4a60-ae3c-046a00390051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36725
07320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.3672507320
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.1086410393
Short name T1203
Test name
Test status
Simulation time 5338920883 ps
CPU time 47.72 seconds
Started Jul 24 05:25:07 PM PDT 24
Finished Jul 24 05:25:55 PM PDT 24
Peak memory 206960 kb
Host smart-edc22f4a-79b3-474a-8cc6-ae564f34222b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10864
10393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.1086410393
Directory /workspace/9.usbdev_streaming_out/latest
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