Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	170255	1		T1	3		T2	5		T3	4
all_values[1]	170255	1		T1	3		T2	5		T3	4
all_values[2]	170255	1		T1	3		T2	5		T3	4
all_values[3]	170255	1		T1	3		T2	5		T3	4
all_values[4]	170255	1		T1	3		T2	5		T3	4
all_values[5]	170255	1		T1	3		T2	5		T3	4
all_values[6]	170255	1		T1	3		T2	5		T3	4
all_values[7]	170255	1		T1	3		T2	5		T3	4
all_values[8]	170255	1		T1	3		T2	5		T3	4
all_values[9]	170255	1		T1	3		T2	5		T3	4
all_values[10]	170255	1		T1	3		T2	5		T3	4
all_values[11]	170255	1		T1	3		T2	5		T3	4
all_values[12]	170255	1		T1	3		T2	5		T3	4
all_values[13]	170255	1		T1	3		T2	5		T3	4
all_values[14]	170255	1		T1	3		T2	5		T3	4
all_values[15]	170255	1		T1	3		T2	5		T3	4
all_values[16]	170255	1		T1	3		T2	5		T3	4
all_values[17]	170255	1		T1	3		T2	5		T3	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5441329	1		T1	96		T2	158		T3	128
auto[1]	6831	1		T2	2		T30	14		T56	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4663422	1		T1	80		T2	131		T3	110
auto[1]	784738	1		T1	16		T2	29		T3	18

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	143460	1		T2	5		T3	3		T29	2
all_values[0]	auto[0]	auto[1]	25975	1		T1	3		T3	1		T31	2
all_values[0]	auto[1]	auto[0]	726	1		T56	3		T36	3		T58	3
all_values[0]	auto[1]	auto[1]	94	1		T327	1		T328	1		T329	1
all_values[1]	auto[0]	auto[0]	167018	1		T1	2		T2	3		T3	4
all_values[1]	auto[0]	auto[1]	1551	1		T1	1		T32	3		T33	2
all_values[1]	auto[1]	auto[0]	677	1		T2	1		T30	2		T60	2
all_values[1]	auto[1]	auto[1]	1009	1		T2	1		T30	12		T60	12
all_values[2]	auto[0]	auto[0]	2964	1		T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	167047	1		T1	2		T2	4		T3	3
all_values[2]	auto[1]	auto[0]	142	1		T51	1		T52	1		T53	1
all_values[2]	auto[1]	auto[1]	102	1		T51	1		T52	1		T53	1
all_values[3]	auto[0]	auto[0]	168114	1		T1	3		T2	5		T3	4
all_values[3]	auto[0]	auto[1]	530	1		T33	1		T4	1		T5	1
all_values[3]	auto[1]	auto[0]	1549	1		T74	1430		T222	4		T223	3
all_values[3]	auto[1]	auto[1]	62	1		T74	1		T225	1		T222	3
all_values[4]	auto[0]	auto[0]	2946	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	167139	1		T1	2		T2	4		T3	3
all_values[4]	auto[1]	auto[0]	109	1		T75	1		T222	1		T223	1
all_values[4]	auto[1]	auto[1]	61	1		T75	1		T225	1		T223	3
all_values[5]	auto[0]	auto[0]	169765	1		T1	3		T2	4		T3	4
all_values[5]	auto[0]	auto[1]	334	1		T2	1		T42	1		T43	1
all_values[5]	auto[1]	auto[0]	111	1		T225	1		T222	4		T223	1
all_values[5]	auto[1]	auto[1]	45	1		T222	1		T224	1		T317	2
all_values[6]	auto[0]	auto[0]	169831	1		T1	3		T2	3		T3	4
all_values[6]	auto[0]	auto[1]	260	1		T2	2		T43	1		T48	2
all_values[6]	auto[1]	auto[0]	89	1		T225	1		T223	3		T224	2
all_values[6]	auto[1]	auto[1]	75	1		T225	3		T222	3		T223	1
all_values[7]	auto[0]	auto[0]	114091	1		T34	2		T76	2		T4	2
all_values[7]	auto[0]	auto[1]	56007	1		T1	3		T2	5		T3	4
all_values[7]	auto[1]	auto[0]	105	1		T61	1		T62	1		T63	1
all_values[7]	auto[1]	auto[1]	52	1		T61	1		T62	1		T63	1
all_values[8]	auto[0]	auto[0]	170021	1		T1	3		T2	5		T3	4
all_values[8]	auto[0]	auto[1]	59	1		T222	1		T224	3		T314	3
all_values[8]	auto[1]	auto[0]	119	1		T67	10		T225	2		T222	4
all_values[8]	auto[1]	auto[1]	56	1		T67	1		T225	2		T222	2
all_values[9]	auto[0]	auto[0]	170000	1		T1	3		T2	5		T3	4
all_values[9]	auto[0]	auto[1]	64	1		T224	1		T318	4		T321	1
all_values[9]	auto[1]	auto[0]	113	1		T71	3		T72	3		T73	3
all_values[9]	auto[1]	auto[1]	78	1		T71	2		T72	2		T73	2
all_values[10]	auto[0]	auto[0]	169804	1		T1	3		T2	5		T3	4
all_values[10]	auto[0]	auto[1]	316	1		T29	1		T69	1		T70	2
all_values[10]	auto[1]	auto[0]	83	1		T222	2		T223	1		T317	2
all_values[10]	auto[1]	auto[1]	52	1		T225	2		T222	1		T223	3
all_values[11]	auto[0]	auto[0]	169846	1		T1	3		T2	5		T3	4
all_values[11]	auto[0]	auto[1]	137	1		T81	1		T82	1		T85	1
all_values[11]	auto[1]	auto[0]	157	1		T57	1		T83	1		T84	1
all_values[11]	auto[1]	auto[1]	115	1		T57	1		T83	1		T84	1
all_values[12]	auto[0]	auto[0]	170015	1		T1	3		T2	5		T3	4
all_values[12]	auto[0]	auto[1]	68	1		T86	1		T90	1		T91	1
all_values[12]	auto[1]	auto[0]	108	1		T87	2		T88	2		T89	2
all_values[12]	auto[1]	auto[1]	64	1		T87	1		T88	1		T89	1
all_values[13]	auto[0]	auto[0]	169947	1		T1	3		T2	5		T3	4
all_values[13]	auto[0]	auto[1]	67	1		T86	1		T90	1		T91	1
all_values[13]	auto[1]	auto[0]	136	1		T81	1		T82	1		T85	1
all_values[13]	auto[1]	auto[1]	105	1		T81	1		T82	1		T85	1
all_values[14]	auto[0]	auto[0]	31826	1		T1	3		T2	2		T3	4
all_values[14]	auto[0]	auto[1]	138257	1		T2	3		T33	1		T4	1
all_values[14]	auto[1]	auto[0]	102	1		T222	1		T223	3		T224	3
all_values[14]	auto[1]	auto[1]	70	1		T225	1		T222	3		T317	2
all_values[15]	auto[0]	auto[0]	2986	1		T1	1		T2	1		T3	1
all_values[15]	auto[0]	auto[1]	167112	1		T1	2		T2	4		T3	3
all_values[15]	auto[1]	auto[0]	96	1		T222	1		T223	1		T224	3
all_values[15]	auto[1]	auto[1]	61	1		T222	4		T224	1		T317	3
all_values[16]	auto[0]	auto[0]	169651	1		T1	3		T2	5		T3	4
all_values[16]	auto[0]	auto[1]	422	1		T34	1		T76	1		T77	1
all_values[16]	auto[1]	auto[0]	109	1		T78	4		T79	4		T80	4
all_values[16]	auto[1]	auto[1]	73	1		T78	4		T79	4		T80	4
all_values[17]	auto[0]	auto[0]	112959	1		T4	2		T5	2		T6	2
all_values[17]	auto[0]	auto[1]	57170	1		T1	3		T2	5		T3	4
all_values[17]	auto[1]	auto[0]	77	1		T68	1		T222	1		T223	1
all_values[17]	auto[1]	auto[1]	49	1		T68	1		T223	1		T224	2