Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::address_cg

Group : usbdev_env_pkg::usbdev_env_cov::address_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	14	0	14	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::address_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_address	7	0	7	100.00	100	1	1	0
cp_endp	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_address_X_endp	14	0	14	100.00	100	1	1	0

Summary for Variable cp_address

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_address

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	1616	1		T120	1		T94	6		T20	15
range_16_to_126	184862	1		T1	2		T2	2		T29	2
fifteen	785	1		T31	1		T94	4		T118	165
range_2_to_14	23066	1		T3	1		T108	1		T5	177
seven	758	1		T250	2		T94	3		T238	1
one	1080	1		T103	1		T120	1		T93	1
zero	1633	1		T94	1		T82	1		T162	1

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Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
seven	15786	1		T30	2		T33	30		T5	3
three	17312	1		T30	2		T33	38		T5	31

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Summary for Cross cr_address_X_endp

Samples crossed: cp_address cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	0	14	100.00

Automatically Generated Cross Bins for cr_address_X_endp

Bins

cp_address	cp_endp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	seven	28	1		T331	3		T174	1		T332	1
range_127	three	29	1		T99	1		T176	1		T331	1
range_16_to_126	seven	14110	1		T30	2		T33	30		T5	3
range_16_to_126	three	13289	1		T30	2		T33	38		T5	1
fifteen	seven	44	1		T94	1		T100	1		T332	1
fifteen	three	39	1		T176	1		T309	1		T190	1
range_2_to_14	seven	1451	1		T120	1		T333	157		T94	30
range_2_to_14	three	3822	1		T5	30		T93	3		T94	37
seven	seven	60	1		T334	2		T176	1		T335	2
seven	three	40	1		T238	1		T334	2		T129	1
one	seven	84	1		T336	2		T13	2		T99	2
one	three	76	1		T336	2		T176	2		T177	1
zero	seven	69	1		T238	1		T129	1		T177	1
zero	three	57	1		T100	1		T181	1		T174	1