Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	134724	1		T1	1		T2	1		T3	1
auto[1]	61396	1		T1	1		T2	1		T29	2

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
sixty_four	31026	1		T3	1		T32	2		T33	3
sixty_three	1220	1		T33	4		T5	2		T6	2
sixty_two	1175	1		T33	8		T4	2		T5	2
sixty_one	1181	1		T33	3		T4	4		T5	2
five	1493	1		T33	5		T5	4		T6	4
four	1559	1		T30	2		T33	12		T4	2
three	1501	1		T33	5		T5	4		T6	4
one	1567	1		T33	11		T4	6		T5	1
zero	11711	1		T29	2		T33	143		T109	1

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
sixty_four	auto[0]	25497	1		T3	1		T32	1		T33	3
sixty_four	auto[1]	5529	1		T32	1		T6	1		T50	136
sixty_three	auto[0]	773	1		T33	4		T5	1		T6	1
sixty_three	auto[1]	447	1		T5	1		T6	1		T110	1
sixty_two	auto[0]	744	1		T33	7		T4	1		T5	1
sixty_two	auto[1]	431	1		T33	1		T4	1		T5	1
sixty_one	auto[0]	753	1		T33	3		T4	2		T5	1
sixty_one	auto[1]	428	1		T4	2		T5	1		T110	2
five	auto[0]	793	1		T33	2		T5	3		T6	2
five	auto[1]	700	1		T33	3		T5	1		T6	2
four	auto[0]	835	1		T30	1		T33	7		T4	1
four	auto[1]	724	1		T30	1		T33	5		T4	1
three	auto[0]	761	1		T33	3		T5	2		T6	2
three	auto[1]	740	1		T33	2		T5	2		T6	2
one	auto[0]	769	1		T33	5		T4	3		T5	1
one	auto[1]	798	1		T33	6		T4	3		T6	2
zero	auto[0]	973	1		T33	5		T109	1		T5	1
zero	auto[1]	10738	1		T29	2		T33	138		T6	1