Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
42.67	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	6	16	72.73
Crosses	128	80	48	37.50

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	16	4	12	75.00	100	1	1	16
cp_pid	4	2	2	50.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	128	80	48	37.50	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	87974	1		T1	1		T2	1		T3	1
auto[1]	56013	1		T2	1		T29	2		T30	12

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	16	4	12	75.00

Automatically Generated Bins for cp_endp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[12] - auto[15]]	--	--	4

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	15391	1		T3	1		T29	2		T30	2
auto[1]	13622	1		T2	2		T30	2		T33	41
auto[2]	11102	1		T1	1		T30	2		T33	34
auto[3]	13465	1		T30	2		T33	38		T5	28
auto[4]	9604	1		T30	2		T33	47		T60	2
auto[5]	11329	1		T30	2		T33	46		T4	212
auto[6]	12228	1		T30	2		T33	36		T76	1
auto[7]	11847	1		T30	2		T33	30		T60	2
auto[8]	10217	1		T30	2		T32	2		T33	42
auto[9]	9657	1		T30	2		T33	37		T6	26
auto[10]	13336	1		T30	2		T33	36		T109	1
auto[11]	12189	1		T30	2		T33	41		T5	28

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	2	2	50.00

User Defined Bins for cp_pid

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
nak	0	1	1
ack	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
data1	67506	1		T33	227		T4	106		T36	2
data0	76468	1		T1	1		T2	2		T3	1

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	80	48	37.50	80

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Element holes

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	NUMBER
[nak , ack]	*	*	--	--	64
[data1 , data0]	*	[auto[12] - auto[15]]	--	--	16

Covered bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
data1	auto[0]	auto[0]	4938	1		T33	10		T36	1		T5	7
data1	auto[0]	auto[1]	3647	1		T33	13		T43	4		T19	62
data1	auto[0]	auto[2]	2598	1		T33	10		T5	7		T6	3
data1	auto[0]	auto[3]	3918	1		T33	10		T5	5		T6	6
data1	auto[0]	auto[4]	2252	1		T33	10		T114	5		T115	13
data1	auto[0]	auto[5]	2651	1		T33	10		T4	36		T6	6
data1	auto[0]	auto[6]	3153	1		T33	9		T5	4		T6	6
data1	auto[0]	auto[7]	3013	1		T33	8		T111	7		T114	2
data1	auto[0]	auto[8]	2169	1		T33	10		T115	8		T69	1
data1	auto[0]	auto[9]	2377	1		T33	8		T6	6		T114	5
data1	auto[0]	auto[10]	3452	1		T33	10		T5	7		T6	6
data1	auto[0]	auto[11]	3181	1		T33	12		T5	3		T6	4
data1	auto[1]	auto[0]	2361	1		T33	8		T36	1		T5	7
data1	auto[1]	auto[1]	2765	1		T33	7		T43	9		T19	62
data1	auto[1]	auto[2]	2514	1		T33	7		T5	7		T6	10
data1	auto[1]	auto[3]	2499	1		T33	9		T5	9		T6	6
data1	auto[1]	auto[4]	2226	1		T33	13		T114	6		T115	13
data1	auto[1]	auto[5]	2608	1		T33	12		T4	70		T6	6
data1	auto[1]	auto[6]	2626	1		T33	8		T5	10		T6	6
data1	auto[1]	auto[7]	2542	1		T33	7		T114	8		T98	6
data1	auto[1]	auto[8]	2546	1		T33	10		T115	19		T69	1
data1	auto[1]	auto[9]	2121	1		T33	10		T6	6		T114	5
data1	auto[1]	auto[10]	2790	1		T33	8		T5	7		T6	7
data1	auto[1]	auto[11]	2559	1		T33	8		T5	11		T6	9
data0	auto[0]	auto[0]	6081	1		T3	1		T30	1		T31	1
data0	auto[0]	auto[1]	4865	1		T2	1		T30	1		T33	13
data0	auto[0]	auto[2]	3812	1		T1	1		T30	1		T33	10
data0	auto[0]	auto[3]	4946	1		T30	1		T33	10		T5	9
data0	auto[0]	auto[4]	3223	1		T30	1		T33	10		T60	1
data0	auto[0]	auto[5]	3909	1		T30	1		T33	11		T4	70
data0	auto[0]	auto[6]	4153	1		T30	1		T33	10		T76	1
data0	auto[0]	auto[7]	4079	1		T30	1		T33	8		T60	1
data0	auto[0]	auto[8]	3307	1		T30	1		T32	1		T33	11
data0	auto[0]	auto[9]	3301	1		T30	1		T33	9		T6	7
data0	auto[0]	auto[10]	4764	1		T30	1		T33	10		T109	1
data0	auto[0]	auto[11]	4172	1		T30	1		T33	12		T5	11
data0	auto[1]	auto[0]	2009	1		T29	2		T30	1		T33	8
data0	auto[1]	auto[1]	2343	1		T2	1		T30	1		T33	8
data0	auto[1]	auto[2]	2177	1		T30	1		T33	7		T5	7
data0	auto[1]	auto[3]	2102	1		T30	1		T33	9		T5	5
data0	auto[1]	auto[4]	1902	1		T30	1		T33	14		T60	1
data0	auto[1]	auto[5]	2161	1		T30	1		T33	13		T4	36
data0	auto[1]	auto[6]	2292	1		T30	1		T33	9		T5	4
data0	auto[1]	auto[7]	2213	1		T30	1		T33	7		T60	1
data0	auto[1]	auto[8]	2195	1		T30	1		T32	1		T33	11
data0	auto[1]	auto[9]	1856	1		T30	1		T33	10		T6	7
data0	auto[1]	auto[10]	2330	1		T30	1		T33	8		T5	7
data0	auto[1]	auto[11]	2276	1		T30	1		T33	9		T5	3