Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	170255	1		T1	3		T2	5		T3	4
all_pins[1]	170255	1		T1	3		T2	5		T3	4
all_pins[2]	170255	1		T1	3		T2	5		T3	4
all_pins[3]	170255	1		T1	3		T2	5		T3	4
all_pins[4]	170255	1		T1	3		T2	5		T3	4
all_pins[5]	170255	1		T1	3		T2	5		T3	4
all_pins[6]	170255	1		T1	3		T2	5		T3	4
all_pins[7]	170255	1		T1	3		T2	5		T3	4
all_pins[8]	170255	1		T1	3		T2	5		T3	4
all_pins[9]	170255	1		T1	3		T2	5		T3	4
all_pins[10]	170255	1		T1	3		T2	5		T3	4
all_pins[11]	170255	1		T1	3		T2	5		T3	4
all_pins[12]	170255	1		T1	3		T2	5		T3	4
all_pins[13]	170255	1		T1	3		T2	5		T3	4
all_pins[14]	170255	1		T1	3		T2	5		T3	4
all_pins[15]	170255	1		T1	3		T2	5		T3	4
all_pins[16]	170255	1		T1	3		T2	5		T3	4
all_pins[17]	170255	1		T1	3		T2	5		T3	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	5445937	1		T1	96		T2	159		T3	128
values[0x1]	2223	1		T2	1		T30	12		T60	12
transitions[0x0=>0x1]	1989	1		T2	1		T30	12		T60	12
transitions[0x1=>0x0]	1989	1		T2	1		T30	12		T60	12

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	170161	1		T1	3		T2	5		T3	4
all_pins[0]	values[0x1]	94	1		T327	1		T328	1		T329	1
all_pins[0]	transitions[0x0=>0x1]	76	1		T327	1		T328	1		T329	1
all_pins[0]	transitions[0x1=>0x0]	991	1		T2	1		T30	12		T60	12
all_pins[1]	values[0x0]	169246	1		T1	3		T2	4		T3	4
all_pins[1]	values[0x1]	1009	1		T2	1		T30	12		T60	12
all_pins[1]	transitions[0x0=>0x1]	998	1		T2	1		T30	12		T60	12
all_pins[1]	transitions[0x1=>0x0]	91	1		T51	1		T52	1		T53	1
all_pins[2]	values[0x0]	170153	1		T1	3		T2	5		T3	4
all_pins[2]	values[0x1]	102	1		T51	1		T52	1		T53	1
all_pins[2]	transitions[0x0=>0x1]	91	1		T51	1		T52	1		T53	1
all_pins[2]	transitions[0x1=>0x0]	51	1		T74	1		T225	1		T222	2
all_pins[3]	values[0x0]	170193	1		T1	3		T2	5		T3	4
all_pins[3]	values[0x1]	62	1		T74	1		T225	1		T222	3
all_pins[3]	transitions[0x0=>0x1]	51	1		T74	1		T222	3		T318	1
all_pins[3]	transitions[0x1=>0x0]	50	1		T75	1		T223	3		T224	2
all_pins[4]	values[0x0]	170194	1		T1	3		T2	5		T3	4
all_pins[4]	values[0x1]	61	1		T75	1		T225	1		T223	3
all_pins[4]	transitions[0x0=>0x1]	45	1		T75	1		T225	1		T223	3
all_pins[4]	transitions[0x1=>0x0]	29	1		T222	1		T224	1		T320	1
all_pins[5]	values[0x0]	170210	1		T1	3		T2	5		T3	4
all_pins[5]	values[0x1]	45	1		T222	1		T224	1		T317	2
all_pins[5]	transitions[0x0=>0x1]	34	1		T222	1		T224	1		T317	2
all_pins[5]	transitions[0x1=>0x0]	64	1		T225	3		T222	3		T223	1
all_pins[6]	values[0x0]	170180	1		T1	3		T2	5		T3	4
all_pins[6]	values[0x1]	75	1		T225	3		T222	3		T223	1
all_pins[6]	transitions[0x0=>0x1]	66	1		T225	3		T222	3		T223	1
all_pins[6]	transitions[0x1=>0x0]	43	1		T61	1		T62	1		T63	1
all_pins[7]	values[0x0]	170203	1		T1	3		T2	5		T3	4
all_pins[7]	values[0x1]	52	1		T61	1		T62	1		T63	1
all_pins[7]	transitions[0x0=>0x1]	42	1		T61	1		T62	1		T63	1
all_pins[7]	transitions[0x1=>0x0]	46	1		T67	1		T225	2		T222	2
all_pins[8]	values[0x0]	170199	1		T1	3		T2	5		T3	4
all_pins[8]	values[0x1]	56	1		T67	1		T225	2		T222	2
all_pins[8]	transitions[0x0=>0x1]	37	1		T67	1		T225	2		T222	1
all_pins[8]	transitions[0x1=>0x0]	59	1		T71	2		T72	2		T73	2
all_pins[9]	values[0x0]	170177	1		T1	3		T2	5		T3	4
all_pins[9]	values[0x1]	78	1		T71	2		T72	2		T73	2
all_pins[9]	transitions[0x0=>0x1]	61	1		T71	2		T72	2		T73	2
all_pins[9]	transitions[0x1=>0x0]	35	1		T225	1		T222	1		T223	2
all_pins[10]	values[0x0]	170203	1		T1	3		T2	5		T3	4
all_pins[10]	values[0x1]	52	1		T225	2		T222	1		T223	3
all_pins[10]	transitions[0x0=>0x1]	37	1		T225	1		T222	1		T223	3
all_pins[10]	transitions[0x1=>0x0]	100	1		T57	1		T83	1		T84	1
all_pins[11]	values[0x0]	170140	1		T1	3		T2	5		T3	4
all_pins[11]	values[0x1]	115	1		T57	1		T83	1		T84	1
all_pins[11]	transitions[0x0=>0x1]	100	1		T57	1		T83	1		T84	1
all_pins[11]	transitions[0x1=>0x0]	49	1		T87	1		T88	1		T89	1
all_pins[12]	values[0x0]	170191	1		T1	3		T2	5		T3	4
all_pins[12]	values[0x1]	64	1		T87	1		T88	1		T89	1
all_pins[12]	transitions[0x0=>0x1]	53	1		T87	1		T88	1		T89	1
all_pins[12]	transitions[0x1=>0x0]	94	1		T81	1		T82	1		T85	1
all_pins[13]	values[0x0]	170150	1		T1	3		T2	5		T3	4
all_pins[13]	values[0x1]	105	1		T81	1		T82	1		T85	1
all_pins[13]	transitions[0x0=>0x1]	93	1		T81	1		T82	1		T85	1
all_pins[13]	transitions[0x1=>0x0]	58	1		T225	1		T222	2		T317	2
all_pins[14]	values[0x0]	170185	1		T1	3		T2	5		T3	4
all_pins[14]	values[0x1]	70	1		T225	1		T222	3		T317	2
all_pins[14]	transitions[0x0=>0x1]	52	1		T225	1		T222	1		T314	2
all_pins[14]	transitions[0x1=>0x0]	43	1		T222	2		T224	1		T317	1
all_pins[15]	values[0x0]	170194	1		T1	3		T2	5		T3	4
all_pins[15]	values[0x1]	61	1		T222	4		T224	1		T317	3
all_pins[15]	transitions[0x0=>0x1]	44	1		T222	2		T317	1		T321	1
all_pins[15]	transitions[0x1=>0x0]	56	1		T78	4		T79	4		T80	4
all_pins[16]	values[0x0]	170182	1		T1	3		T2	5		T3	4
all_pins[16]	values[0x1]	73	1		T78	4		T79	4		T80	4
all_pins[16]	transitions[0x0=>0x1]	60	1		T78	4		T79	4		T80	4
all_pins[16]	transitions[0x1=>0x0]	36	1		T68	1		T223	1		T224	1
all_pins[17]	values[0x0]	170206	1		T1	3		T2	5		T3	4
all_pins[17]	values[0x1]	49	1		T68	1		T223	1		T224	2
all_pins[17]	transitions[0x0=>0x1]	49	1		T68	1		T223	1		T224	2