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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.52 97.79 93.72 97.44 71.88 96.17 98.17 71.47


Total test records in report: 2976
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T2817 /workspace/coverage/default/5.usbdev_enable.2878231572 Jul 25 07:01:27 PM PDT 24 Jul 25 07:01:29 PM PDT 24 95009674 ps
T2818 /workspace/coverage/default/6.usbdev_out_iso.1976791027 Jul 25 07:01:44 PM PDT 24 Jul 25 07:01:45 PM PDT 24 156250815 ps
T2819 /workspace/coverage/default/35.usbdev_spurious_pids_ignored.2576480981 Jul 25 07:06:54 PM PDT 24 Jul 25 07:07:50 PM PDT 24 5418458282 ps
T2820 /workspace/coverage/default/25.usbdev_rx_crc_err.3575825314 Jul 25 07:05:15 PM PDT 24 Jul 25 07:05:16 PM PDT 24 168484834 ps
T2821 /workspace/coverage/default/8.usbdev_stall_priority_over_nak.4270773594 Jul 25 07:02:15 PM PDT 24 Jul 25 07:02:16 PM PDT 24 182327861 ps
T2822 /workspace/coverage/default/27.usbdev_fifo_rst.1355144848 Jul 25 07:05:34 PM PDT 24 Jul 25 07:05:36 PM PDT 24 167000531 ps
T2823 /workspace/coverage/default/2.usbdev_endpoint_access.1199249510 Jul 25 07:00:41 PM PDT 24 Jul 25 07:00:44 PM PDT 24 832890414 ps
T2824 /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.2420311210 Jul 25 07:03:54 PM PDT 24 Jul 25 07:03:55 PM PDT 24 136232982 ps
T2825 /workspace/coverage/default/47.usbdev_nak_trans.1982210010 Jul 25 07:08:43 PM PDT 24 Jul 25 07:08:44 PM PDT 24 235949498 ps
T2826 /workspace/coverage/default/34.usbdev_random_length_out_transaction.1656135535 Jul 25 07:06:44 PM PDT 24 Jul 25 07:06:45 PM PDT 24 193521395 ps
T2827 /workspace/coverage/default/11.usbdev_phy_pins_sense.1609485473 Jul 25 07:02:54 PM PDT 24 Jul 25 07:02:55 PM PDT 24 31763919 ps
T2828 /workspace/coverage/default/44.usbdev_spurious_pids_ignored.2857017451 Jul 25 07:08:11 PM PDT 24 Jul 25 07:08:41 PM PDT 24 4021180039 ps
T2829 /workspace/coverage/default/25.usbdev_in_stall.4270420584 Jul 25 07:05:14 PM PDT 24 Jul 25 07:05:16 PM PDT 24 150897469 ps
T2830 /workspace/coverage/default/0.usbdev_rand_bus_disconnects.2454843452 Jul 25 07:00:22 PM PDT 24 Jul 25 07:02:26 PM PDT 24 4743159746 ps
T2831 /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.4173821342 Jul 25 07:01:28 PM PDT 24 Jul 25 07:04:42 PM PDT 24 6502372841 ps
T2832 /workspace/coverage/default/11.usbdev_min_length_out_transaction.1660588578 Jul 25 07:03:02 PM PDT 24 Jul 25 07:03:03 PM PDT 24 156560192 ps
T2833 /workspace/coverage/default/13.usbdev_max_length_out_transaction.1135754835 Jul 25 07:03:17 PM PDT 24 Jul 25 07:03:18 PM PDT 24 217675378 ps
T2834 /workspace/coverage/default/23.usbdev_spurious_pids_ignored.1157552480 Jul 25 07:05:07 PM PDT 24 Jul 25 07:05:39 PM PDT 24 3703714443 ps
T2835 /workspace/coverage/default/3.usbdev_setup_priority.1329357790 Jul 25 07:01:12 PM PDT 24 Jul 25 07:01:14 PM PDT 24 471986137 ps
T2836 /workspace/coverage/default/18.usbdev_phy_config_pinflip.120243049 Jul 25 07:04:14 PM PDT 24 Jul 25 07:04:15 PM PDT 24 240431243 ps
T2837 /workspace/coverage/default/45.usbdev_in_stall.2300334737 Jul 25 07:08:02 PM PDT 24 Jul 25 07:08:03 PM PDT 24 147082943 ps
T2838 /workspace/coverage/default/18.usbdev_in_iso.1161590955 Jul 25 07:04:07 PM PDT 24 Jul 25 07:04:08 PM PDT 24 192402879 ps
T2839 /workspace/coverage/default/28.usbdev_in_trans.848534061 Jul 25 07:05:55 PM PDT 24 Jul 25 07:05:56 PM PDT 24 244515152 ps
T2840 /workspace/coverage/default/1.usbdev_aon_wake_reset.291441904 Jul 25 07:00:36 PM PDT 24 Jul 25 07:00:51 PM PDT 24 13311155133 ps
T2841 /workspace/coverage/default/44.usbdev_data_toggle_clear.3107955272 Jul 25 07:07:54 PM PDT 24 Jul 25 07:07:55 PM PDT 24 147725256 ps
T2842 /workspace/coverage/default/21.usbdev_invalid_sync.576231482 Jul 25 07:05:34 PM PDT 24 Jul 25 07:08:34 PM PDT 24 6365331547 ps
T2843 /workspace/coverage/default/36.usbdev_aon_wake_reset.4228259240 Jul 25 07:07:01 PM PDT 24 Jul 25 07:07:17 PM PDT 24 13340337690 ps
T2844 /workspace/coverage/default/31.usbdev_random_length_out_transaction.3135787312 Jul 25 07:06:15 PM PDT 24 Jul 25 07:06:16 PM PDT 24 165889115 ps
T2845 /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.1061594001 Jul 25 07:07:20 PM PDT 24 Jul 25 07:08:06 PM PDT 24 4471733111 ps
T2846 /workspace/coverage/default/34.usbdev_timeout_missing_host_handshake.35486812 Jul 25 07:06:33 PM PDT 24 Jul 25 07:07:12 PM PDT 24 5641786001 ps
T2847 /workspace/coverage/default/32.usbdev_out_iso.657742031 Jul 25 07:06:22 PM PDT 24 Jul 25 07:06:23 PM PDT 24 180391384 ps
T2848 /workspace/coverage/default/37.usbdev_stream_len_max.3393008468 Jul 25 07:07:03 PM PDT 24 Jul 25 07:07:05 PM PDT 24 672177734 ps
T2849 /workspace/coverage/default/7.usbdev_alert_test.1677214975 Jul 25 07:02:05 PM PDT 24 Jul 25 07:02:06 PM PDT 24 93145106 ps
T2850 /workspace/coverage/default/11.usbdev_out_iso.348213834 Jul 25 07:02:54 PM PDT 24 Jul 25 07:02:55 PM PDT 24 185531273 ps
T2851 /workspace/coverage/default/37.usbdev_in_trans.3661544439 Jul 25 07:07:03 PM PDT 24 Jul 25 07:07:04 PM PDT 24 194747316 ps
T2852 /workspace/coverage/default/0.usbdev_min_length_out_transaction.2565143487 Jul 25 07:00:26 PM PDT 24 Jul 25 07:00:27 PM PDT 24 170123404 ps
T2853 /workspace/coverage/default/47.usbdev_enable.3614415299 Jul 25 07:08:30 PM PDT 24 Jul 25 07:08:31 PM PDT 24 37297161 ps
T2854 /workspace/coverage/default/15.usbdev_min_length_out_transaction.3855797345 Jul 25 07:03:37 PM PDT 24 Jul 25 07:03:38 PM PDT 24 143085108 ps
T2855 /workspace/coverage/default/35.usbdev_invalid_sync.2107586934 Jul 25 07:06:51 PM PDT 24 Jul 25 07:08:04 PM PDT 24 7119026178 ps
T2856 /workspace/coverage/default/26.usbdev_link_in_err.3466222319 Jul 25 07:05:24 PM PDT 24 Jul 25 07:05:25 PM PDT 24 233355186 ps
T157 /workspace/coverage/default/37.usbdev_nak_trans.124178693 Jul 25 07:07:09 PM PDT 24 Jul 25 07:07:10 PM PDT 24 196528382 ps
T2857 /workspace/coverage/default/39.usbdev_rx_crc_err.3130353289 Jul 25 07:07:30 PM PDT 24 Jul 25 07:07:31 PM PDT 24 161984283 ps
T2858 /workspace/coverage/default/22.usbdev_streaming_out.3547900095 Jul 25 07:04:57 PM PDT 24 Jul 25 07:05:29 PM PDT 24 3681975553 ps
T2859 /workspace/coverage/default/43.usbdev_invalid_sync.1716981108 Jul 25 07:08:01 PM PDT 24 Jul 25 07:09:22 PM PDT 24 8198187664 ps
T2860 /workspace/coverage/default/10.usbdev_in_iso.2642520239 Jul 25 07:02:35 PM PDT 24 Jul 25 07:02:37 PM PDT 24 234985974 ps
T2861 /workspace/coverage/default/36.usbdev_rx_crc_err.871597055 Jul 25 07:06:56 PM PDT 24 Jul 25 07:06:58 PM PDT 24 190592892 ps
T2862 /workspace/coverage/default/28.usbdev_max_length_in_transaction.3049234141 Jul 25 07:05:43 PM PDT 24 Jul 25 07:05:44 PM PDT 24 246365666 ps
T2863 /workspace/coverage/default/23.usbdev_aon_wake_reset.1545698961 Jul 25 07:04:56 PM PDT 24 Jul 25 07:05:14 PM PDT 24 13434532731 ps
T2864 /workspace/coverage/default/29.usbdev_random_length_out_transaction.1823632628 Jul 25 07:06:02 PM PDT 24 Jul 25 07:06:03 PM PDT 24 175562435 ps
T2865 /workspace/coverage/default/39.usbdev_fifo_rst.3007245873 Jul 25 07:07:16 PM PDT 24 Jul 25 07:07:18 PM PDT 24 192413709 ps
T2866 /workspace/coverage/default/9.usbdev_data_toggle_clear.2157283166 Jul 25 07:02:24 PM PDT 24 Jul 25 07:02:25 PM PDT 24 511284682 ps
T215 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1392597120 Jul 25 04:43:52 PM PDT 24 Jul 25 04:43:54 PM PDT 24 229011500 ps
T251 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2875238376 Jul 25 04:43:12 PM PDT 24 Jul 25 04:43:13 PM PDT 24 79444889 ps
T211 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3563807725 Jul 25 04:43:21 PM PDT 24 Jul 25 04:43:23 PM PDT 24 83903933 ps
T225 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3532445171 Jul 25 04:43:54 PM PDT 24 Jul 25 04:43:55 PM PDT 24 93075637 ps
T222 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.4260961546 Jul 25 04:43:49 PM PDT 24 Jul 25 04:43:50 PM PDT 24 61884530 ps
T223 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.767468350 Jul 25 04:43:43 PM PDT 24 Jul 25 04:43:44 PM PDT 24 39305954 ps
T216 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1138891066 Jul 25 04:43:38 PM PDT 24 Jul 25 04:43:44 PM PDT 24 1018735941 ps
T217 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2138688362 Jul 25 04:43:07 PM PDT 24 Jul 25 04:43:09 PM PDT 24 100728757 ps
T224 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3012820783 Jul 25 04:43:49 PM PDT 24 Jul 25 04:43:50 PM PDT 24 53730680 ps
T317 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.1212348999 Jul 25 04:43:08 PM PDT 24 Jul 25 04:43:09 PM PDT 24 41582781 ps
T274 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3085751107 Jul 25 04:43:32 PM PDT 24 Jul 25 04:43:33 PM PDT 24 89115764 ps
T314 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1029889259 Jul 25 04:43:49 PM PDT 24 Jul 25 04:43:50 PM PDT 24 32457888 ps
T212 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.4197064867 Jul 25 04:43:51 PM PDT 24 Jul 25 04:43:53 PM PDT 24 81618710 ps
T213 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2235213911 Jul 25 04:43:30 PM PDT 24 Jul 25 04:43:35 PM PDT 24 933129020 ps
T318 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1848814400 Jul 25 04:43:25 PM PDT 24 Jul 25 04:43:25 PM PDT 24 57089359 ps
T299 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3460098671 Jul 25 04:43:41 PM PDT 24 Jul 25 04:43:42 PM PDT 24 41957246 ps
T235 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2362688019 Jul 25 04:43:53 PM PDT 24 Jul 25 04:43:55 PM PDT 24 239479751 ps
T288 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2494773802 Jul 25 04:43:09 PM PDT 24 Jul 25 04:43:11 PM PDT 24 107443718 ps
T240 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1494335320 Jul 25 04:43:29 PM PDT 24 Jul 25 04:43:32 PM PDT 24 390711113 ps
T236 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.122287085 Jul 25 04:43:42 PM PDT 24 Jul 25 04:43:49 PM PDT 24 1895810761 ps
T275 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.338264081 Jul 25 04:43:09 PM PDT 24 Jul 25 04:43:14 PM PDT 24 863873064 ps
T321 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1177552849 Jul 25 04:43:40 PM PDT 24 Jul 25 04:43:41 PM PDT 24 72969669 ps
T252 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.568593110 Jul 25 04:43:40 PM PDT 24 Jul 25 04:43:42 PM PDT 24 469534125 ps
T241 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3318093593 Jul 25 04:43:54 PM PDT 24 Jul 25 04:43:56 PM PDT 24 158834980 ps
T276 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.559741545 Jul 25 04:43:46 PM PDT 24 Jul 25 04:43:47 PM PDT 24 67422257 ps
T277 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1589859716 Jul 25 04:43:48 PM PDT 24 Jul 25 04:43:49 PM PDT 24 91310249 ps
T289 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2335826321 Jul 25 04:43:11 PM PDT 24 Jul 25 04:43:17 PM PDT 24 93199205 ps
T315 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2543396794 Jul 25 04:43:38 PM PDT 24 Jul 25 04:43:39 PM PDT 24 88012567 ps
T316 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3700771078 Jul 25 04:43:39 PM PDT 24 Jul 25 04:43:40 PM PDT 24 39792666 ps
T320 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2008107876 Jul 25 04:43:47 PM PDT 24 Jul 25 04:43:48 PM PDT 24 79572867 ps
T2867 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1190882535 Jul 25 04:43:05 PM PDT 24 Jul 25 04:43:06 PM PDT 24 69259157 ps
T290 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3021719430 Jul 25 04:43:41 PM PDT 24 Jul 25 04:43:43 PM PDT 24 95307305 ps
T291 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.951831419 Jul 25 04:43:42 PM PDT 24 Jul 25 04:43:43 PM PDT 24 136562749 ps
T319 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3246993302 Jul 25 04:43:34 PM PDT 24 Jul 25 04:43:35 PM PDT 24 68651857 ps
T2868 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.3813156366 Jul 25 04:43:53 PM PDT 24 Jul 25 04:43:54 PM PDT 24 51284913 ps
T278 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2128191623 Jul 25 04:43:49 PM PDT 24 Jul 25 04:43:50 PM PDT 24 55819187 ps
T2869 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.790699387 Jul 25 04:43:07 PM PDT 24 Jul 25 04:43:09 PM PDT 24 252017497 ps
T2870 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1310657168 Jul 25 04:43:27 PM PDT 24 Jul 25 04:43:28 PM PDT 24 59563942 ps
T2871 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1170144911 Jul 25 04:43:45 PM PDT 24 Jul 25 04:43:46 PM PDT 24 40014167 ps
T253 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1105404848 Jul 25 04:43:12 PM PDT 24 Jul 25 04:43:17 PM PDT 24 949215351 ps
T295 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.365092701 Jul 25 04:43:08 PM PDT 24 Jul 25 04:43:11 PM PDT 24 577004538 ps
T248 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2602014389 Jul 25 04:43:34 PM PDT 24 Jul 25 04:43:36 PM PDT 24 108120364 ps
T254 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2070776697 Jul 25 04:43:16 PM PDT 24 Jul 25 04:43:17 PM PDT 24 80181296 ps
T296 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3517306126 Jul 25 04:43:40 PM PDT 24 Jul 25 04:43:42 PM PDT 24 248684807 ps
T279 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2744308857 Jul 25 04:43:06 PM PDT 24 Jul 25 04:43:07 PM PDT 24 89344523 ps
T2872 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2429583884 Jul 25 04:43:37 PM PDT 24 Jul 25 04:43:38 PM PDT 24 35620996 ps
T257 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2113076355 Jul 25 04:43:42 PM PDT 24 Jul 25 04:43:49 PM PDT 24 2901482227 ps
T242 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2409219815 Jul 25 04:43:41 PM PDT 24 Jul 25 04:43:44 PM PDT 24 247007761 ps
T256 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.4057495517 Jul 25 04:43:42 PM PDT 24 Jul 25 04:43:45 PM PDT 24 619009500 ps
T2873 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.1948274370 Jul 25 04:43:54 PM PDT 24 Jul 25 04:43:55 PM PDT 24 76531462 ps
T2874 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1740917375 Jul 25 04:43:48 PM PDT 24 Jul 25 04:43:49 PM PDT 24 90478423 ps
T297 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1577641729 Jul 25 04:43:10 PM PDT 24 Jul 25 04:43:12 PM PDT 24 285062067 ps
T255 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3044056641 Jul 25 04:43:52 PM PDT 24 Jul 25 04:43:54 PM PDT 24 102176593 ps
T2875 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3250959872 Jul 25 04:43:09 PM PDT 24 Jul 25 04:43:10 PM PDT 24 44894042 ps
T2876 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2471969608 Jul 25 04:43:44 PM PDT 24 Jul 25 04:43:45 PM PDT 24 26946175 ps
T2877 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2502730149 Jul 25 04:43:50 PM PDT 24 Jul 25 04:43:51 PM PDT 24 41507440 ps
T2878 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3809471938 Jul 25 04:43:44 PM PDT 24 Jul 25 04:43:45 PM PDT 24 48729496 ps
T2879 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.3575373862 Jul 25 04:43:10 PM PDT 24 Jul 25 04:43:11 PM PDT 24 36760004 ps
T2880 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.50459845 Jul 25 04:43:54 PM PDT 24 Jul 25 04:43:55 PM PDT 24 50416245 ps
T298 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.469089038 Jul 25 04:43:33 PM PDT 24 Jul 25 04:43:35 PM PDT 24 108015450 ps
T322 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3073236301 Jul 25 04:43:47 PM PDT 24 Jul 25 04:43:52 PM PDT 24 1571902784 ps
T280 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1461024305 Jul 25 04:43:10 PM PDT 24 Jul 25 04:43:18 PM PDT 24 1102825369 ps
T2881 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.517780006 Jul 25 04:44:06 PM PDT 24 Jul 25 04:44:07 PM PDT 24 50523291 ps
T2882 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3259916771 Jul 25 04:43:49 PM PDT 24 Jul 25 04:43:53 PM PDT 24 451342934 ps
T2883 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2738436538 Jul 25 04:43:27 PM PDT 24 Jul 25 04:43:28 PM PDT 24 35101138 ps
T300 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3594615334 Jul 25 04:43:40 PM PDT 24 Jul 25 04:43:42 PM PDT 24 103475185 ps
T244 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2588200048 Jul 25 04:43:35 PM PDT 24 Jul 25 04:43:37 PM PDT 24 64507234 ps
T2884 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.55290695 Jul 25 04:43:43 PM PDT 24 Jul 25 04:43:45 PM PDT 24 255579111 ps
T2885 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3831844985 Jul 25 04:43:45 PM PDT 24 Jul 25 04:43:46 PM PDT 24 119094572 ps
T2886 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3110564352 Jul 25 04:43:38 PM PDT 24 Jul 25 04:43:40 PM PDT 24 79326914 ps
T2887 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2022535064 Jul 25 04:43:14 PM PDT 24 Jul 25 04:43:17 PM PDT 24 106067146 ps
T2888 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.461792299 Jul 25 04:43:14 PM PDT 24 Jul 25 04:43:17 PM PDT 24 262938108 ps
T2889 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1022787116 Jul 25 04:43:41 PM PDT 24 Jul 25 04:43:42 PM PDT 24 68772287 ps
T2890 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.48171496 Jul 25 04:43:44 PM PDT 24 Jul 25 04:43:46 PM PDT 24 104212641 ps
T2891 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1490234017 Jul 25 04:43:08 PM PDT 24 Jul 25 04:43:11 PM PDT 24 594492634 ps
T247 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1003990150 Jul 25 04:43:10 PM PDT 24 Jul 25 04:43:13 PM PDT 24 89021399 ps
T2892 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1872856902 Jul 25 04:43:40 PM PDT 24 Jul 25 04:43:41 PM PDT 24 59217406 ps
T245 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.648503456 Jul 25 04:43:17 PM PDT 24 Jul 25 04:43:20 PM PDT 24 110116875 ps
T2893 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.923953120 Jul 25 04:43:29 PM PDT 24 Jul 25 04:43:31 PM PDT 24 77579540 ps
T323 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2080334201 Jul 25 04:43:39 PM PDT 24 Jul 25 04:43:44 PM PDT 24 959036482 ps
T281 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3052677084 Jul 25 04:43:37 PM PDT 24 Jul 25 04:43:41 PM PDT 24 294277989 ps
T2894 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1623864931 Jul 25 04:43:37 PM PDT 24 Jul 25 04:43:38 PM PDT 24 53801140 ps
T2895 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1257732598 Jul 25 04:43:31 PM PDT 24 Jul 25 04:43:32 PM PDT 24 77582212 ps
T246 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3713805082 Jul 25 04:43:17 PM PDT 24 Jul 25 04:43:18 PM PDT 24 128138781 ps
T2896 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.492613774 Jul 25 04:43:28 PM PDT 24 Jul 25 04:43:29 PM PDT 24 180219023 ps
T249 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3323417816 Jul 25 04:43:36 PM PDT 24 Jul 25 04:43:38 PM PDT 24 66530162 ps
T2897 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2265141446 Jul 25 04:43:30 PM PDT 24 Jul 25 04:43:32 PM PDT 24 146408523 ps
T2898 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.744895651 Jul 25 04:43:35 PM PDT 24 Jul 25 04:43:37 PM PDT 24 111491433 ps
T2899 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3918121934 Jul 25 04:43:35 PM PDT 24 Jul 25 04:43:40 PM PDT 24 794094942 ps
T2900 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2366556336 Jul 25 04:43:44 PM PDT 24 Jul 25 04:43:45 PM PDT 24 115850463 ps
T2901 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.218520760 Jul 25 04:43:13 PM PDT 24 Jul 25 04:43:14 PM PDT 24 95977018 ps
T282 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1623012265 Jul 25 04:43:06 PM PDT 24 Jul 25 04:43:14 PM PDT 24 182356726 ps
T283 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1237432369 Jul 25 04:43:40 PM PDT 24 Jul 25 04:43:41 PM PDT 24 68973674 ps
T284 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2869930943 Jul 25 04:43:05 PM PDT 24 Jul 25 04:43:07 PM PDT 24 99119953 ps
T285 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2200435355 Jul 25 04:43:34 PM PDT 24 Jul 25 04:43:36 PM PDT 24 57812479 ps
T2902 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.4084568792 Jul 25 04:43:39 PM PDT 24 Jul 25 04:43:44 PM PDT 24 757860586 ps
T324 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2292551338 Jul 25 04:43:40 PM PDT 24 Jul 25 04:43:44 PM PDT 24 801573923 ps
T286 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2317216213 Jul 25 04:43:11 PM PDT 24 Jul 25 04:43:12 PM PDT 24 131098647 ps
T2903 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2803902926 Jul 25 04:43:45 PM PDT 24 Jul 25 04:43:46 PM PDT 24 44667012 ps
T2904 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1013989978 Jul 25 04:43:37 PM PDT 24 Jul 25 04:43:38 PM PDT 24 34217920 ps
T2905 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1256783434 Jul 25 04:43:25 PM PDT 24 Jul 25 04:43:27 PM PDT 24 180486215 ps
T2906 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2155658152 Jul 25 04:43:34 PM PDT 24 Jul 25 04:43:44 PM PDT 24 1263712233 ps
T2907 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.577124010 Jul 25 04:43:10 PM PDT 24 Jul 25 04:43:11 PM PDT 24 73468402 ps
T2908 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3403332727 Jul 25 04:43:24 PM PDT 24 Jul 25 04:43:26 PM PDT 24 217733995 ps
T2909 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.584701375 Jul 25 04:43:25 PM PDT 24 Jul 25 04:43:27 PM PDT 24 138350432 ps
T2910 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1713739830 Jul 25 04:43:10 PM PDT 24 Jul 25 04:43:13 PM PDT 24 256405420 ps
T2911 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3449266260 Jul 25 04:43:36 PM PDT 24 Jul 25 04:43:37 PM PDT 24 42571933 ps
T2912 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2661291490 Jul 25 04:43:32 PM PDT 24 Jul 25 04:43:34 PM PDT 24 184546752 ps
T2913 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.4062409700 Jul 25 04:43:44 PM PDT 24 Jul 25 04:43:45 PM PDT 24 57594375 ps
T2914 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1428256981 Jul 25 04:43:33 PM PDT 24 Jul 25 04:43:34 PM PDT 24 56990940 ps
T2915 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1357624711 Jul 25 04:43:39 PM PDT 24 Jul 25 04:43:40 PM PDT 24 49525025 ps
T2916 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.895598723 Jul 25 04:43:47 PM PDT 24 Jul 25 04:43:49 PM PDT 24 171241531 ps
T2917 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.4228643131 Jul 25 04:43:07 PM PDT 24 Jul 25 04:43:10 PM PDT 24 253562388 ps
T2918 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2191525566 Jul 25 04:43:22 PM PDT 24 Jul 25 04:43:25 PM PDT 24 170289792 ps
T2919 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.431496256 Jul 25 04:43:56 PM PDT 24 Jul 25 04:43:57 PM PDT 24 99351407 ps
T2920 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3720337852 Jul 25 04:43:13 PM PDT 24 Jul 25 04:43:14 PM PDT 24 121646866 ps
T2921 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.73533526 Jul 25 04:43:07 PM PDT 24 Jul 25 04:43:11 PM PDT 24 623956606 ps
T2922 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2747230616 Jul 25 04:43:41 PM PDT 24 Jul 25 04:43:42 PM PDT 24 37130646 ps
T2923 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2629207648 Jul 25 04:43:08 PM PDT 24 Jul 25 04:43:09 PM PDT 24 36487067 ps
T2924 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2508708577 Jul 25 04:43:49 PM PDT 24 Jul 25 04:43:50 PM PDT 24 69640065 ps
T2925 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.127709491 Jul 25 04:43:39 PM PDT 24 Jul 25 04:43:40 PM PDT 24 43272079 ps
T2926 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.637239653 Jul 25 04:43:54 PM PDT 24 Jul 25 04:43:59 PM PDT 24 169672912 ps
T2927 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2302262037 Jul 25 04:43:52 PM PDT 24 Jul 25 04:43:53 PM PDT 24 60108364 ps
T2928 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3218348363 Jul 25 04:43:27 PM PDT 24 Jul 25 04:43:31 PM PDT 24 285881056 ps
T2929 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.527365711 Jul 25 04:43:36 PM PDT 24 Jul 25 04:43:39 PM PDT 24 301398273 ps
T2930 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1912881996 Jul 25 04:43:05 PM PDT 24 Jul 25 04:43:09 PM PDT 24 293104510 ps
T287 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.648492232 Jul 25 04:43:04 PM PDT 24 Jul 25 04:43:08 PM PDT 24 375142034 ps
T326 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1329796516 Jul 25 04:43:44 PM PDT 24 Jul 25 04:43:49 PM PDT 24 1347102855 ps
T2931 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.648320169 Jul 25 04:43:42 PM PDT 24 Jul 25 04:43:43 PM PDT 24 79492100 ps
T2932 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3984743104 Jul 25 04:43:55 PM PDT 24 Jul 25 04:43:56 PM PDT 24 37396950 ps
T325 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1002670775 Jul 25 04:43:21 PM PDT 24 Jul 25 04:43:25 PM PDT 24 967938964 ps
T2933 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1349895720 Jul 25 04:43:26 PM PDT 24 Jul 25 04:43:28 PM PDT 24 60877928 ps
T2934 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1844936164 Jul 25 04:43:31 PM PDT 24 Jul 25 04:43:32 PM PDT 24 41982198 ps
T2935 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2460054058 Jul 25 04:43:36 PM PDT 24 Jul 25 04:43:41 PM PDT 24 615878160 ps
T2936 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.236518269 Jul 25 04:43:56 PM PDT 24 Jul 25 04:43:59 PM PDT 24 279694785 ps
T2937 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.199677026 Jul 25 04:43:05 PM PDT 24 Jul 25 04:43:08 PM PDT 24 88585133 ps
T2938 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1864478430 Jul 25 04:43:11 PM PDT 24 Jul 25 04:43:13 PM PDT 24 126289896 ps
T2939 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.515539375 Jul 25 04:43:10 PM PDT 24 Jul 25 04:43:12 PM PDT 24 97196693 ps
T2940 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2474756774 Jul 25 04:43:44 PM PDT 24 Jul 25 04:43:45 PM PDT 24 44943622 ps
T2941 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3496092657 Jul 25 04:43:29 PM PDT 24 Jul 25 04:43:35 PM PDT 24 41191953 ps
T2942 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3993657243 Jul 25 04:43:35 PM PDT 24 Jul 25 04:43:36 PM PDT 24 44632563 ps
T2943 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1418693673 Jul 25 04:43:46 PM PDT 24 Jul 25 04:43:48 PM PDT 24 192205260 ps
T2944 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1200989489 Jul 25 04:43:05 PM PDT 24 Jul 25 04:43:06 PM PDT 24 79506168 ps
T2945 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3688688147 Jul 25 04:43:30 PM PDT 24 Jul 25 04:43:32 PM PDT 24 130769290 ps
T2946 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.864053660 Jul 25 04:43:40 PM PDT 24 Jul 25 04:43:42 PM PDT 24 74806153 ps
T2947 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3989856040 Jul 25 04:43:48 PM PDT 24 Jul 25 04:43:49 PM PDT 24 77377819 ps
T2948 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1105933277 Jul 25 04:43:09 PM PDT 24 Jul 25 04:43:10 PM PDT 24 47959753 ps
T2949 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3978930906 Jul 25 04:43:07 PM PDT 24 Jul 25 04:43:09 PM PDT 24 79319677 ps
T2950 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1621746268 Jul 25 04:43:44 PM PDT 24 Jul 25 04:43:45 PM PDT 24 40130769 ps
T2951 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3291003188 Jul 25 04:43:33 PM PDT 24 Jul 25 04:43:35 PM PDT 24 82159038 ps
T2952 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2406023117 Jul 25 04:43:41 PM PDT 24 Jul 25 04:43:42 PM PDT 24 46675030 ps
T2953 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1046392457 Jul 25 04:43:21 PM PDT 24 Jul 25 04:43:23 PM PDT 24 322263019 ps
T2954 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.498682987 Jul 25 04:43:45 PM PDT 24 Jul 25 04:43:48 PM PDT 24 167549368 ps
T2955 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3953152264 Jul 25 04:43:43 PM PDT 24 Jul 25 04:43:44 PM PDT 24 56691101 ps
T2956 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.535853976 Jul 25 04:43:06 PM PDT 24 Jul 25 04:43:07 PM PDT 24 67896077 ps
T2957 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.4098769529 Jul 25 04:43:46 PM PDT 24 Jul 25 04:43:47 PM PDT 24 39137383 ps
T2958 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2692354078 Jul 25 04:43:19 PM PDT 24 Jul 25 04:43:20 PM PDT 24 51390247 ps
T2959 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.270564675 Jul 25 04:43:11 PM PDT 24 Jul 25 04:43:14 PM PDT 24 345370732 ps
T2960 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.590487341 Jul 25 04:43:44 PM PDT 24 Jul 25 04:43:45 PM PDT 24 54344388 ps
T2961 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2662487511 Jul 25 04:43:42 PM PDT 24 Jul 25 04:43:43 PM PDT 24 57980818 ps
T2962 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.679836623 Jul 25 04:43:07 PM PDT 24 Jul 25 04:43:10 PM PDT 24 182949695 ps
T2963 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.623059133 Jul 25 04:43:10 PM PDT 24 Jul 25 04:43:12 PM PDT 24 88305005 ps
T2964 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3089859909 Jul 25 04:43:54 PM PDT 24 Jul 25 04:43:56 PM PDT 24 248282184 ps
T2965 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.290204534 Jul 25 04:43:23 PM PDT 24 Jul 25 04:43:29 PM PDT 24 118078687 ps
T2966 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.310340838 Jul 25 04:43:26 PM PDT 24 Jul 25 04:43:28 PM PDT 24 66039755 ps
T2967 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3567872558 Jul 25 04:43:25 PM PDT 24 Jul 25 04:43:28 PM PDT 24 178594670 ps
T2968 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3634895863 Jul 25 04:43:09 PM PDT 24 Jul 25 04:43:10 PM PDT 24 74534352 ps
T2969 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.96489130 Jul 25 04:43:52 PM PDT 24 Jul 25 04:43:53 PM PDT 24 50455425 ps
T2970 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1389603029 Jul 25 04:43:07 PM PDT 24 Jul 25 04:43:12 PM PDT 24 476255535 ps
T2971 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.611336270 Jul 25 04:43:23 PM PDT 24 Jul 25 04:43:26 PM PDT 24 239294249 ps
T2972 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2738428525 Jul 25 04:43:37 PM PDT 24 Jul 25 04:43:39 PM PDT 24 87589885 ps
T2973 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.430865294 Jul 25 04:43:51 PM PDT 24 Jul 25 04:43:53 PM PDT 24 148114396 ps
T2974 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1473448412 Jul 25 04:43:54 PM PDT 24 Jul 25 04:43:57 PM PDT 24 108666479 ps
T2975 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2610822877 Jul 25 04:43:14 PM PDT 24 Jul 25 04:43:17 PM PDT 24 689999659 ps
T2976 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2162452349 Jul 25 04:43:44 PM PDT 24 Jul 25 04:43:45 PM PDT 24 134922385 ps

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.3546158942
Short name T33
Test name
Test status
Simulation time 10182554244 ps
CPU time 28.37 seconds
Started Jul 25 07:06:24 PM PDT 24
Finished Jul 25 07:06:52 PM PDT 24
Peak memory 215556 kb
Host smart-6c8a6927-5afb-474b-ac14-b01fc641d74f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35461
58942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.3546158942
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.2702185603
Short name T6
Test name
Test status
Simulation time 5050080727 ps
CPU time 50.57 seconds
Started Jul 25 07:05:24 PM PDT 24
Finished Jul 25 07:06:14 PM PDT 24
Peak memory 215568 kb
Host smart-e5af8c08-3632-49fa-be21-5165a904f29a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27021
85603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.2702185603
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.2549371283
Short name T12
Test name
Test status
Simulation time 13363916252 ps
CPU time 15.65 seconds
Started Jul 25 07:04:18 PM PDT 24
Finished Jul 25 07:04:34 PM PDT 24
Peak memory 207412 kb
Host smart-4e2ba58a-a156-427a-99d8-1a27469edcca
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549371283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.2549371283
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3012820783
Short name T224
Test name
Test status
Simulation time 53730680 ps
CPU time 0.76 seconds
Started Jul 25 04:43:49 PM PDT 24
Finished Jul 25 04:43:50 PM PDT 24
Peak memory 206032 kb
Host smart-8f0cdabe-4d26-4fb1-bcb9-f2aa77d8ee7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3012820783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.3012820783
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/default/32.usbdev_device_address.127607298
Short name T94
Test name
Test status
Simulation time 12028776521 ps
CPU time 25.76 seconds
Started Jul 25 07:06:19 PM PDT 24
Finished Jul 25 07:06:45 PM PDT 24
Peak memory 207388 kb
Host smart-fad64477-cf95-4084-a551-597ec1aefeee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12760
7298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.127607298
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.2797726583
Short name T81
Test name
Test status
Simulation time 150340308 ps
CPU time 0.84 seconds
Started Jul 25 07:01:47 PM PDT 24
Finished Jul 25 07:01:48 PM PDT 24
Peak memory 207104 kb
Host smart-b91f104c-2701-438d-a552-a79854aa9914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27977
26583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.2797726583
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_iso_retraction.4143499441
Short name T101
Test name
Test status
Simulation time 6137982807 ps
CPU time 47.04 seconds
Started Jul 25 07:04:28 PM PDT 24
Finished Jul 25 07:05:15 PM PDT 24
Peak memory 207344 kb
Host smart-b4f77b53-5492-444f-a51b-7a216ce65fc0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4143499441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.4143499441
Directory /workspace/20.usbdev_iso_retraction/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2235213911
Short name T213
Test name
Test status
Simulation time 933129020 ps
CPU time 4.85 seconds
Started Jul 25 04:43:30 PM PDT 24
Finished Jul 25 04:43:35 PM PDT 24
Peak memory 206308 kb
Host smart-7d438366-2a9b-45e2-bf3e-31bf8e7be9fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2235213911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.2235213911
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.1495173068
Short name T125
Test name
Test status
Simulation time 187454434 ps
CPU time 0.98 seconds
Started Jul 25 07:00:55 PM PDT 24
Finished Jul 25 07:00:56 PM PDT 24
Peak memory 207140 kb
Host smart-f2c2e6d6-eab2-490d-9dee-521bfc13b907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14951
73068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.1495173068
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.790737006
Short name T52
Test name
Test status
Simulation time 137930813 ps
CPU time 0.88 seconds
Started Jul 25 07:02:46 PM PDT 24
Finished Jul 25 07:02:47 PM PDT 24
Peak memory 207092 kb
Host smart-5f434a4f-a885-4be0-81d9-6cbd9d157a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79073
7006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.790737006
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.4021956939
Short name T208
Test name
Test status
Simulation time 229107410 ps
CPU time 1.06 seconds
Started Jul 25 07:00:31 PM PDT 24
Finished Jul 25 07:00:32 PM PDT 24
Peak memory 223044 kb
Host smart-fe08e669-ee25-4fe4-ae5c-1802c3812005
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4021956939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.4021956939
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.3046608754
Short name T7
Test name
Test status
Simulation time 13415935135 ps
CPU time 14.91 seconds
Started Jul 25 07:06:47 PM PDT 24
Finished Jul 25 07:07:02 PM PDT 24
Peak memory 207420 kb
Host smart-dcad7f9f-827e-4535-8383-c3bc9d9c436f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046608754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.3046608754
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.2308198753
Short name T128
Test name
Test status
Simulation time 266180197 ps
CPU time 1.05 seconds
Started Jul 25 07:01:12 PM PDT 24
Finished Jul 25 07:01:13 PM PDT 24
Peak memory 207124 kb
Host smart-5bed3520-8cb5-4020-bba1-92c0e1268235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23081
98753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.2308198753
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.4260961546
Short name T222
Test name
Test status
Simulation time 61884530 ps
CPU time 0.8 seconds
Started Jul 25 04:43:49 PM PDT 24
Finished Jul 25 04:43:50 PM PDT 24
Peak memory 206020 kb
Host smart-92007aab-71f6-4e43-a1b6-86dd91175677
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4260961546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.4260961546
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2875238376
Short name T251
Test name
Test status
Simulation time 79444889 ps
CPU time 1.01 seconds
Started Jul 25 04:43:12 PM PDT 24
Finished Jul 25 04:43:13 PM PDT 24
Peak memory 206120 kb
Host smart-159076be-1503-47fa-b3e7-d4c3384920c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2875238376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2875238376
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.320964376
Short name T69
Test name
Test status
Simulation time 1569073864 ps
CPU time 3.9 seconds
Started Jul 25 07:04:22 PM PDT 24
Finished Jul 25 07:04:26 PM PDT 24
Peak memory 207304 kb
Host smart-e81686e5-09ad-445c-b69d-e8a41df053e4
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=320964376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.320964376
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.3785092275
Short name T27
Test name
Test status
Simulation time 82759183 ps
CPU time 0.75 seconds
Started Jul 25 07:06:53 PM PDT 24
Finished Jul 25 07:06:54 PM PDT 24
Peak memory 207088 kb
Host smart-605bf36b-f790-4f40-8887-470f81f754ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37850
92275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.3785092275
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2362688019
Short name T235
Test name
Test status
Simulation time 239479751 ps
CPU time 2.07 seconds
Started Jul 25 04:43:53 PM PDT 24
Finished Jul 25 04:43:55 PM PDT 24
Peak memory 206356 kb
Host smart-55f95032-4eec-40e2-b5ec-f273e4d17ae3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2362688019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.2362688019
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.1231289139
Short name T92
Test name
Test status
Simulation time 345569512 ps
CPU time 1.19 seconds
Started Jul 25 07:00:22 PM PDT 24
Finished Jul 25 07:00:24 PM PDT 24
Peak memory 207104 kb
Host smart-74641984-9fde-44e4-a6f6-927a8cad1c47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12312
89139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.1231289139
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.2417733078
Short name T54
Test name
Test status
Simulation time 20208303088 ps
CPU time 25.41 seconds
Started Jul 25 07:00:24 PM PDT 24
Finished Jul 25 07:00:50 PM PDT 24
Peak memory 207152 kb
Host smart-d08cea78-899e-4f83-b42f-51f93d949993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24177
33078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.2417733078
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.2182217348
Short name T13
Test name
Test status
Simulation time 3615220436 ps
CPU time 5.32 seconds
Started Jul 25 07:03:52 PM PDT 24
Finished Jul 25 07:03:58 PM PDT 24
Peak memory 207368 kb
Host smart-dea2b8e3-7ae9-4465-9fe5-39655920e295
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182217348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_a
on_wake_disconnect.2182217348
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_device_address.3851203299
Short name T129
Test name
Test status
Simulation time 18881536326 ps
CPU time 43.41 seconds
Started Jul 25 07:03:58 PM PDT 24
Finished Jul 25 07:04:42 PM PDT 24
Peak memory 207380 kb
Host smart-8d5b1e63-5def-4233-8b54-98b837f1ebce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38512
03299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.3851203299
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.1794914838
Short name T84
Test name
Test status
Simulation time 141553983 ps
CPU time 0.83 seconds
Started Jul 25 07:04:59 PM PDT 24
Finished Jul 25 07:05:00 PM PDT 24
Peak memory 207044 kb
Host smart-185f202a-0edf-4e94-ab4f-1be65dd38297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17949
14838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.1794914838
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_device_address.2981218019
Short name T176
Test name
Test status
Simulation time 13135132147 ps
CPU time 29.54 seconds
Started Jul 25 07:08:44 PM PDT 24
Finished Jul 25 07:09:14 PM PDT 24
Peak memory 207404 kb
Host smart-ce0648f7-66f8-4c9c-abe7-eef746f365d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29812
18019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.2981218019
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.2045898399
Short name T64
Test name
Test status
Simulation time 390447931 ps
CPU time 1.32 seconds
Started Jul 25 07:01:27 PM PDT 24
Finished Jul 25 07:01:29 PM PDT 24
Peak memory 207108 kb
Host smart-6a98b448-5d42-4497-b18b-4067ad1b0c1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20458
98399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.2045898399
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.1871619513
Short name T327
Test name
Test status
Simulation time 174904742 ps
CPU time 0.91 seconds
Started Jul 25 07:05:17 PM PDT 24
Finished Jul 25 07:05:18 PM PDT 24
Peak memory 207152 kb
Host smart-d0495767-b108-4991-adfb-2d3db9da1746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18716
19513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.1871619513
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.3476736911
Short name T90
Test name
Test status
Simulation time 9493234960 ps
CPU time 172.11 seconds
Started Jul 25 07:00:34 PM PDT 24
Finished Jul 25 07:03:26 PM PDT 24
Peak memory 215604 kb
Host smart-ecd77979-5746-4cff-a474-2b35c07f565b
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476736911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.3476736911
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.889058138
Short name T3
Test name
Test status
Simulation time 203764424 ps
CPU time 0.99 seconds
Started Jul 25 07:01:56 PM PDT 24
Finished Jul 25 07:01:57 PM PDT 24
Peak memory 207112 kb
Host smart-e1e9e742-5fdd-471c-be63-9a4bb55fdbd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88905
8138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.889058138
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.560851146
Short name T79
Test name
Test status
Simulation time 487053127 ps
CPU time 1.46 seconds
Started Jul 25 07:00:21 PM PDT 24
Finished Jul 25 07:00:23 PM PDT 24
Peak memory 207136 kb
Host smart-69ce5547-a777-4ace-9251-5e07ce644671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56085
1146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.560851146
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/default/30.usbdev_device_address.39670929
Short name T936
Test name
Test status
Simulation time 20796488769 ps
CPU time 46.62 seconds
Started Jul 25 07:05:59 PM PDT 24
Finished Jul 25 07:06:46 PM PDT 24
Peak memory 207292 kb
Host smart-4817aaa0-0f69-45bb-ad89-9591b7c948ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39670
929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.39670929
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1848814400
Short name T318
Test name
Test status
Simulation time 57089359 ps
CPU time 0.72 seconds
Started Jul 25 04:43:25 PM PDT 24
Finished Jul 25 04:43:25 PM PDT 24
Peak memory 206008 kb
Host smart-2c5569c3-e304-4f07-8cc3-247c860b68b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1848814400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.1848814400
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.2347112858
Short name T790
Test name
Test status
Simulation time 68763358 ps
CPU time 0.74 seconds
Started Jul 25 07:00:55 PM PDT 24
Finished Jul 25 07:00:56 PM PDT 24
Peak memory 207208 kb
Host smart-0a469758-647a-4d6b-8514-e3c06801be09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2347112858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.2347112858
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.3242685191
Short name T169
Test name
Test status
Simulation time 7357631423 ps
CPU time 52.88 seconds
Started Jul 25 07:01:28 PM PDT 24
Finished Jul 25 07:02:21 PM PDT 24
Peak memory 223684 kb
Host smart-fe5df0a8-97fd-4ea4-9860-e728d96f1ac2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3242685191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.3242685191
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.648503456
Short name T245
Test name
Test status
Simulation time 110116875 ps
CPU time 2.77 seconds
Started Jul 25 04:43:17 PM PDT 24
Finished Jul 25 04:43:20 PM PDT 24
Peak memory 214540 kb
Host smart-eb2a69fd-67be-4b18-a28d-819c4ae26fb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=648503456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.648503456
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1105404848
Short name T253
Test name
Test status
Simulation time 949215351 ps
CPU time 4.51 seconds
Started Jul 25 04:43:12 PM PDT 24
Finished Jul 25 04:43:17 PM PDT 24
Peak memory 206328 kb
Host smart-21d282e4-1f88-40f3-9455-3fdb05ad51ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1105404848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.1105404848
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.2165374673
Short name T337
Test name
Test status
Simulation time 115194216155 ps
CPU time 189.26 seconds
Started Jul 25 07:00:30 PM PDT 24
Finished Jul 25 07:03:40 PM PDT 24
Peak memory 207380 kb
Host smart-e8d1ccd2-0a92-4187-97c3-64054da00527
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2165374673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.2165374673
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.4197861759
Short name T271
Test name
Test status
Simulation time 19655820281 ps
CPU time 50.62 seconds
Started Jul 25 07:00:55 PM PDT 24
Finished Jul 25 07:01:45 PM PDT 24
Peak memory 215556 kb
Host smart-dc125342-feb1-4900-abef-b048e0a108b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41978
61759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.4197861759
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.169399537
Short name T166
Test name
Test status
Simulation time 6073119882 ps
CPU time 63.02 seconds
Started Jul 25 07:04:42 PM PDT 24
Finished Jul 25 07:05:45 PM PDT 24
Peak memory 215584 kb
Host smart-aeb2d9e4-2cca-4f7b-a494-2306e7c1dbc1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=169399537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.169399537
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.4082775157
Short name T91
Test name
Test status
Simulation time 16894725040 ps
CPU time 128.54 seconds
Started Jul 25 07:00:59 PM PDT 24
Finished Jul 25 07:03:08 PM PDT 24
Peak memory 215572 kb
Host smart-f012fcb1-edb9-4ab7-85fe-df002b77a3a2
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082775157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.4082775157
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.3918347662
Short name T72
Test name
Test status
Simulation time 137664940 ps
CPU time 0.83 seconds
Started Jul 25 07:00:13 PM PDT 24
Finished Jul 25 07:00:14 PM PDT 24
Peak memory 207088 kb
Host smart-be6e3c54-e05c-4e48-952a-cd78fc99f53d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39183
47662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.3918347662
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.166160331
Short name T428
Test name
Test status
Simulation time 148085269 ps
CPU time 0.87 seconds
Started Jul 25 07:00:39 PM PDT 24
Finished Jul 25 07:00:40 PM PDT 24
Peak memory 207088 kb
Host smart-42eaa38b-4abf-4a4c-a80d-fbdded5110ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16616
0331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.166160331
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.3958206423
Short name T67
Test name
Test status
Simulation time 249775342 ps
CPU time 1.08 seconds
Started Jul 25 07:00:26 PM PDT 24
Finished Jul 25 07:00:28 PM PDT 24
Peak memory 207052 kb
Host smart-b1fce239-eb27-4d50-8d77-270ba0616267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39582
06423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.3958206423
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.4065049410
Short name T312
Test name
Test status
Simulation time 6842035101 ps
CPU time 49.44 seconds
Started Jul 25 07:04:58 PM PDT 24
Finished Jul 25 07:05:47 PM PDT 24
Peak memory 217564 kb
Host smart-73cd1aeb-f2eb-426b-9dea-91b13ee14d8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40650
49410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.4065049410
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_device_address.875512310
Short name T174
Test name
Test status
Simulation time 14381821447 ps
CPU time 33.36 seconds
Started Jul 25 07:00:31 PM PDT 24
Finished Jul 25 07:01:05 PM PDT 24
Peak memory 207364 kb
Host smart-60f0a86d-0722-48de-a325-8ed7d9d4c835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87551
2310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.875512310
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.282935947
Short name T163
Test name
Test status
Simulation time 231734831 ps
CPU time 1.03 seconds
Started Jul 25 07:01:25 PM PDT 24
Finished Jul 25 07:01:26 PM PDT 24
Peak memory 207132 kb
Host smart-10412269-d0a8-4b91-9053-d01a810b2500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28293
5947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.282935947
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1713739830
Short name T2910
Test name
Test status
Simulation time 256405420 ps
CPU time 2.41 seconds
Started Jul 25 04:43:10 PM PDT 24
Finished Jul 25 04:43:13 PM PDT 24
Peak memory 206348 kb
Host smart-a9abe166-1e16-4054-b0cd-e77702160cf0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1713739830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.1713739830
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1494335320
Short name T240
Test name
Test status
Simulation time 390711113 ps
CPU time 2.65 seconds
Started Jul 25 04:43:29 PM PDT 24
Finished Jul 25 04:43:32 PM PDT 24
Peak memory 206376 kb
Host smart-c555aac8-b1b0-4f3e-ab67-f96baa2f4a0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1494335320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.1494335320
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1002670775
Short name T325
Test name
Test status
Simulation time 967938964 ps
CPU time 3.39 seconds
Started Jul 25 04:43:21 PM PDT 24
Finished Jul 25 04:43:25 PM PDT 24
Peak memory 206384 kb
Host smart-8ce5b9da-8561-4ba2-9ff2-a7e796957788
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1002670775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.1002670775
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2543396794
Short name T315
Test name
Test status
Simulation time 88012567 ps
CPU time 0.8 seconds
Started Jul 25 04:43:38 PM PDT 24
Finished Jul 25 04:43:39 PM PDT 24
Peak memory 206044 kb
Host smart-e0734ff7-6dc2-4311-8051-597b391e3ca2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2543396794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.2543396794
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.3015090943
Short name T343
Test name
Test status
Simulation time 5122462554 ps
CPU time 151.27 seconds
Started Jul 25 07:00:22 PM PDT 24
Finished Jul 25 07:02:54 PM PDT 24
Peak memory 215596 kb
Host smart-8b963fe7-9d3e-431c-bd5f-29990b82e597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30150
90943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.3015090943
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.355721064
Short name T346
Test name
Test status
Simulation time 85151581196 ps
CPU time 131.3 seconds
Started Jul 25 07:00:21 PM PDT 24
Finished Jul 25 07:02:33 PM PDT 24
Peak memory 207372 kb
Host smart-d477f1ca-d8f4-4797-9ce4-f329a70f40f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355721064 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.355721064
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.3411317053
Short name T56
Test name
Test status
Simulation time 142433896 ps
CPU time 0.88 seconds
Started Jul 25 07:00:23 PM PDT 24
Finished Jul 25 07:00:25 PM PDT 24
Peak memory 207192 kb
Host smart-4fe0214e-b91b-4c67-b605-108b41419fe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34113
17053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.3411317053
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.3322458510
Short name T162
Test name
Test status
Simulation time 195470547 ps
CPU time 0.94 seconds
Started Jul 25 07:02:47 PM PDT 24
Finished Jul 25 07:02:48 PM PDT 24
Peak memory 207116 kb
Host smart-f3365804-1b4e-4ab3-a737-662f75377339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33224
58510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.3322458510
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.2000611772
Short name T38
Test name
Test status
Simulation time 43660851 ps
CPU time 0.7 seconds
Started Jul 25 07:00:25 PM PDT 24
Finished Jul 25 07:00:26 PM PDT 24
Peak memory 207092 kb
Host smart-058def2d-1a76-4e4a-8f1e-01766a0f4ec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20006
11772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.2000611772
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.2839041779
Short name T627
Test name
Test status
Simulation time 242380113 ps
CPU time 1.58 seconds
Started Jul 25 07:03:28 PM PDT 24
Finished Jul 25 07:03:30 PM PDT 24
Peak memory 207328 kb
Host smart-0f2147b2-244a-4cd8-afd9-6bf30b9d6a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28390
41779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.2839041779
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.1753427125
Short name T73
Test name
Test status
Simulation time 140559207 ps
CPU time 0.86 seconds
Started Jul 25 07:00:40 PM PDT 24
Finished Jul 25 07:00:41 PM PDT 24
Peak memory 207152 kb
Host smart-ec091f4e-cd89-49a9-a959-d6d915097fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17534
27125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.1753427125
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.199677026
Short name T2937
Test name
Test status
Simulation time 88585133 ps
CPU time 2.1 seconds
Started Jul 25 04:43:05 PM PDT 24
Finished Jul 25 04:43:08 PM PDT 24
Peak memory 221900 kb
Host smart-3f8a98c3-b818-4bce-a03b-664e733eeb66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=199677026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.199677026
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.1268576101
Short name T62
Test name
Test status
Simulation time 188359094 ps
CPU time 1.01 seconds
Started Jul 25 07:00:13 PM PDT 24
Finished Jul 25 07:00:15 PM PDT 24
Peak memory 207120 kb
Host smart-596f78c2-2825-439c-9d6c-8ec176738191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12685
76101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.1268576101
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.1896077899
Short name T74
Test name
Test status
Simulation time 4160639835 ps
CPU time 10.72 seconds
Started Jul 25 07:00:26 PM PDT 24
Finished Jul 25 07:00:37 PM PDT 24
Peak memory 207476 kb
Host smart-8c7c64e3-a3fc-47d1-9a08-dba1ed60f503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18960
77899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.1896077899
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.2460399224
Short name T75
Test name
Test status
Simulation time 173212090 ps
CPU time 0.85 seconds
Started Jul 25 07:00:24 PM PDT 24
Finished Jul 25 07:00:25 PM PDT 24
Peak memory 207060 kb
Host smart-4a0c7c4e-d403-4a28-8688-0dab9f49868a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24603
99224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.2460399224
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.819123570
Short name T179
Test name
Test status
Simulation time 9237143958 ps
CPU time 165.67 seconds
Started Jul 25 07:00:22 PM PDT 24
Finished Jul 25 07:03:08 PM PDT 24
Peak memory 215556 kb
Host smart-8406dbdc-6c50-45cc-a46e-0ab0e4e2c668
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=819123570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.819123570
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.3974180906
Short name T88
Test name
Test status
Simulation time 141536785 ps
CPU time 0.85 seconds
Started Jul 25 07:00:23 PM PDT 24
Finished Jul 25 07:00:24 PM PDT 24
Peak memory 207108 kb
Host smart-d023b5e7-895a-451d-b327-f063a67b9202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39741
80906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.3974180906
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.1344213629
Short name T333
Test name
Test status
Simulation time 4712494032 ps
CPU time 138.87 seconds
Started Jul 25 07:03:13 PM PDT 24
Finished Jul 25 07:05:32 PM PDT 24
Peak memory 215628 kb
Host smart-bbfb110f-7202-45f1-b1e7-dfc09b8264a5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1344213629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.1344213629
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.1551676052
Short name T68
Test name
Test status
Simulation time 156959093 ps
CPU time 0.89 seconds
Started Jul 25 07:01:01 PM PDT 24
Finished Jul 25 07:01:02 PM PDT 24
Peak memory 207116 kb
Host smart-d5a3cbc3-f594-4f7f-84ba-93792465af40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15516
76052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.1551676052
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.1947856621
Short name T175
Test name
Test status
Simulation time 16731515701 ps
CPU time 133.01 seconds
Started Jul 25 07:01:13 PM PDT 24
Finished Jul 25 07:03:26 PM PDT 24
Peak memory 218460 kb
Host smart-885f527f-cbf5-4c06-b0ce-e30226efb0b2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1947856621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.1947856621
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.2960945946
Short name T145
Test name
Test status
Simulation time 186549568 ps
CPU time 0.84 seconds
Started Jul 25 07:00:23 PM PDT 24
Finished Jul 25 07:00:24 PM PDT 24
Peak memory 207080 kb
Host smart-4c18af5f-4ee8-432a-bba8-c9e429b3bcc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29609
45946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.2960945946
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.2185160912
Short name T143
Test name
Test status
Simulation time 293695737 ps
CPU time 1.1 seconds
Started Jul 25 07:00:34 PM PDT 24
Finished Jul 25 07:00:35 PM PDT 24
Peak memory 207124 kb
Host smart-c7f08fa5-be0b-4149-8ad6-f3bba335f12e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21851
60912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.2185160912
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.3654608008
Short name T2239
Test name
Test status
Simulation time 284294610 ps
CPU time 1.01 seconds
Started Jul 25 07:02:46 PM PDT 24
Finished Jul 25 07:02:47 PM PDT 24
Peak memory 207188 kb
Host smart-26f285f6-9e9c-4626-9cae-17a7ba1be5a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36546
08008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.3654608008
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.4100077308
Short name T137
Test name
Test status
Simulation time 192949468 ps
CPU time 0.98 seconds
Started Jul 25 07:02:53 PM PDT 24
Finished Jul 25 07:02:54 PM PDT 24
Peak memory 207124 kb
Host smart-2bb8ac60-d40d-4620-a339-aac160050f96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41000
77308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.4100077308
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.1712242773
Short name T140
Test name
Test status
Simulation time 244284905 ps
CPU time 0.94 seconds
Started Jul 25 07:03:04 PM PDT 24
Finished Jul 25 07:03:05 PM PDT 24
Peak memory 207188 kb
Host smart-2afd4f6d-87df-449a-bf5d-8dca40556d0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17122
42773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.1712242773
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.784251749
Short name T2633
Test name
Test status
Simulation time 169527132 ps
CPU time 0.85 seconds
Started Jul 25 07:03:37 PM PDT 24
Finished Jul 25 07:03:38 PM PDT 24
Peak memory 207140 kb
Host smart-cfec5b80-07d5-4dd7-8bbc-bdd6e0f75661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78425
1749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.784251749
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.362850902
Short name T151
Test name
Test status
Simulation time 209396341 ps
CPU time 0.95 seconds
Started Jul 25 07:03:50 PM PDT 24
Finished Jul 25 07:03:51 PM PDT 24
Peak memory 207148 kb
Host smart-42803fcb-7c0b-48a1-ac80-215ebc57f0a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36285
0902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.362850902
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.972857109
Short name T122
Test name
Test status
Simulation time 9975249404 ps
CPU time 76.96 seconds
Started Jul 25 07:03:53 PM PDT 24
Finished Jul 25 07:05:10 PM PDT 24
Peak memory 215564 kb
Host smart-61dc4056-5535-4991-acce-5d3a9872393b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=972857109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.972857109
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.1754475574
Short name T158
Test name
Test status
Simulation time 212076776 ps
CPU time 0.92 seconds
Started Jul 25 07:04:55 PM PDT 24
Finished Jul 25 07:04:56 PM PDT 24
Peak memory 207112 kb
Host smart-24ff8a62-0c7c-4839-bd51-761ebd12aa16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17544
75574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.1754475574
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.1558316043
Short name T2770
Test name
Test status
Simulation time 206639054 ps
CPU time 0.96 seconds
Started Jul 25 07:05:53 PM PDT 24
Finished Jul 25 07:05:54 PM PDT 24
Peak memory 207212 kb
Host smart-ca63a316-caa5-4bf9-9b04-3a5c02e2bd5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15583
16043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.1558316043
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.158759156
Short name T156
Test name
Test status
Simulation time 236883847 ps
CPU time 1.08 seconds
Started Jul 25 07:06:50 PM PDT 24
Finished Jul 25 07:06:52 PM PDT 24
Peak memory 207208 kb
Host smart-d6261525-6029-4632-8d71-02e705e04907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15875
9156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.158759156
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.1016346797
Short name T139
Test name
Test status
Simulation time 229909201 ps
CPU time 1.04 seconds
Started Jul 25 07:02:19 PM PDT 24
Finished Jul 25 07:02:20 PM PDT 24
Peak memory 207128 kb
Host smart-65950f71-5644-49c6-8fe2-31e008969b5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10163
46797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.1016346797
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.270564675
Short name T2959
Test name
Test status
Simulation time 345370732 ps
CPU time 3.36 seconds
Started Jul 25 04:43:11 PM PDT 24
Finished Jul 25 04:43:14 PM PDT 24
Peak memory 206236 kb
Host smart-5017201a-689e-46c9-a45e-c4654a3c4652
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=270564675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.270564675
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1138891066
Short name T216
Test name
Test status
Simulation time 1018735941 ps
CPU time 5.28 seconds
Started Jul 25 04:43:38 PM PDT 24
Finished Jul 25 04:43:44 PM PDT 24
Peak memory 206364 kb
Host smart-925c91ab-5b52-457d-931f-f59e7312b25d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1138891066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1138891066
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1200989489
Short name T2944
Test name
Test status
Simulation time 79506168 ps
CPU time 0.82 seconds
Started Jul 25 04:43:05 PM PDT 24
Finished Jul 25 04:43:06 PM PDT 24
Peak memory 206020 kb
Host smart-c7553135-ab71-4660-8b61-a73a2e23f4e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1200989489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1200989489
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.744895651
Short name T2898
Test name
Test status
Simulation time 111491433 ps
CPU time 1.98 seconds
Started Jul 25 04:43:35 PM PDT 24
Finished Jul 25 04:43:37 PM PDT 24
Peak memory 218444 kb
Host smart-46e83f83-41ae-4255-ba6a-ce6c66164565
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744895651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev
_csr_mem_rw_with_rand_reset.744895651
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.535853976
Short name T2956
Test name
Test status
Simulation time 67896077 ps
CPU time 0.79 seconds
Started Jul 25 04:43:06 PM PDT 24
Finished Jul 25 04:43:07 PM PDT 24
Peak memory 206156 kb
Host smart-480f3808-17ce-47ba-a620-b185e6408f1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=535853976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.535853976
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1190882535
Short name T2867
Test name
Test status
Simulation time 69259157 ps
CPU time 0.76 seconds
Started Jul 25 04:43:05 PM PDT 24
Finished Jul 25 04:43:06 PM PDT 24
Peak memory 206064 kb
Host smart-1dc2c7ee-a37f-4bbb-b3ba-0a81e0c16cdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1190882535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.1190882535
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1623012265
Short name T282
Test name
Test status
Simulation time 182356726 ps
CPU time 2.25 seconds
Started Jul 25 04:43:06 PM PDT 24
Finished Jul 25 04:43:14 PM PDT 24
Peak memory 206300 kb
Host smart-27cb7272-ca23-4424-a57e-540d34b9a5dd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1623012265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.1623012265
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2022535064
Short name T2887
Test name
Test status
Simulation time 106067146 ps
CPU time 2.32 seconds
Started Jul 25 04:43:14 PM PDT 24
Finished Jul 25 04:43:17 PM PDT 24
Peak memory 206256 kb
Host smart-0970bd41-d05a-4028-b584-513066971d48
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2022535064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.2022535064
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.895598723
Short name T2916
Test name
Test status
Simulation time 171241531 ps
CPU time 1.75 seconds
Started Jul 25 04:43:47 PM PDT 24
Finished Jul 25 04:43:49 PM PDT 24
Peak memory 206336 kb
Host smart-43291609-f90e-4b37-8eb6-033ddc9ccfbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=895598723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.895598723
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.648492232
Short name T287
Test name
Test status
Simulation time 375142034 ps
CPU time 3.46 seconds
Started Jul 25 04:43:04 PM PDT 24
Finished Jul 25 04:43:08 PM PDT 24
Peak memory 206304 kb
Host smart-10427d80-2a77-4868-8aa3-35b573b9118c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=648492232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.648492232
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3918121934
Short name T2899
Test name
Test status
Simulation time 794094942 ps
CPU time 4.56 seconds
Started Jul 25 04:43:35 PM PDT 24
Finished Jul 25 04:43:40 PM PDT 24
Peak memory 206284 kb
Host smart-87f31c41-20a0-4024-b69a-d778d2b1f259
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3918121934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.3918121934
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3634895863
Short name T2968
Test name
Test status
Simulation time 74534352 ps
CPU time 0.81 seconds
Started Jul 25 04:43:09 PM PDT 24
Finished Jul 25 04:43:10 PM PDT 24
Peak memory 206024 kb
Host smart-92ea3c32-f61e-490a-94bd-8eace17f0833
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3634895863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.3634895863
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3318093593
Short name T241
Test name
Test status
Simulation time 158834980 ps
CPU time 1.59 seconds
Started Jul 25 04:43:54 PM PDT 24
Finished Jul 25 04:43:56 PM PDT 24
Peak memory 214568 kb
Host smart-a0ef56bb-eec9-498f-aedd-7f99dcba3ece
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318093593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.3318093593
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2744308857
Short name T279
Test name
Test status
Simulation time 89344523 ps
CPU time 1 seconds
Started Jul 25 04:43:06 PM PDT 24
Finished Jul 25 04:43:07 PM PDT 24
Peak memory 205980 kb
Host smart-182c11f6-ffa7-4e24-8c43-d31b3e63cb9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2744308857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.2744308857
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2629207648
Short name T2923
Test name
Test status
Simulation time 36487067 ps
CPU time 0.69 seconds
Started Jul 25 04:43:08 PM PDT 24
Finished Jul 25 04:43:09 PM PDT 24
Peak memory 205996 kb
Host smart-baa6d8ac-b81a-4aba-bfb4-a22574184769
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2629207648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.2629207648
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2869930943
Short name T284
Test name
Test status
Simulation time 99119953 ps
CPU time 1.39 seconds
Started Jul 25 04:43:05 PM PDT 24
Finished Jul 25 04:43:07 PM PDT 24
Peak memory 214520 kb
Host smart-f8d9a446-96d8-4203-a045-607cff7d4eef
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2869930943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2869930943
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1389603029
Short name T2970
Test name
Test status
Simulation time 476255535 ps
CPU time 4.2 seconds
Started Jul 25 04:43:07 PM PDT 24
Finished Jul 25 04:43:12 PM PDT 24
Peak memory 206248 kb
Host smart-b28faaee-6afb-4078-8742-3bd09539b43c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1389603029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.1389603029
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2494773802
Short name T288
Test name
Test status
Simulation time 107443718 ps
CPU time 1.12 seconds
Started Jul 25 04:43:09 PM PDT 24
Finished Jul 25 04:43:11 PM PDT 24
Peak memory 206148 kb
Host smart-c9263880-3c34-4174-9f48-64aaa145528f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2494773802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.2494773802
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1912881996
Short name T2930
Test name
Test status
Simulation time 293104510 ps
CPU time 3.81 seconds
Started Jul 25 04:43:05 PM PDT 24
Finished Jul 25 04:43:09 PM PDT 24
Peak memory 222032 kb
Host smart-b1a173c9-6d33-4ee0-af74-c32a78253543
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1912881996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1912881996
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1046392457
Short name T2953
Test name
Test status
Simulation time 322263019 ps
CPU time 2.34 seconds
Started Jul 25 04:43:21 PM PDT 24
Finished Jul 25 04:43:23 PM PDT 24
Peak memory 206344 kb
Host smart-48de5241-a1f4-48e5-8544-e87e47b830d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1046392457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.1046392457
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3989856040
Short name T2947
Test name
Test status
Simulation time 77377819 ps
CPU time 1.35 seconds
Started Jul 25 04:43:48 PM PDT 24
Finished Jul 25 04:43:49 PM PDT 24
Peak memory 214524 kb
Host smart-af5aaf4f-73d9-4c71-bda0-236581d710d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989856040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.3989856040
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3085751107
Short name T274
Test name
Test status
Simulation time 89115764 ps
CPU time 1.09 seconds
Started Jul 25 04:43:32 PM PDT 24
Finished Jul 25 04:43:33 PM PDT 24
Peak memory 205968 kb
Host smart-e52ae7be-3415-4f94-829b-5c7fd709fba3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3085751107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.3085751107
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2508708577
Short name T2924
Test name
Test status
Simulation time 69640065 ps
CPU time 0.77 seconds
Started Jul 25 04:43:49 PM PDT 24
Finished Jul 25 04:43:50 PM PDT 24
Peak memory 206024 kb
Host smart-bd31a71d-9c52-41d8-baeb-75836735d61e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2508708577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.2508708577
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1740917375
Short name T2874
Test name
Test status
Simulation time 90478423 ps
CPU time 1.11 seconds
Started Jul 25 04:43:48 PM PDT 24
Finished Jul 25 04:43:49 PM PDT 24
Peak memory 206192 kb
Host smart-cd6aa7c5-a830-4818-a12d-fcf327fcdd21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1740917375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.1740917375
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3323417816
Short name T249
Test name
Test status
Simulation time 66530162 ps
CPU time 1.78 seconds
Started Jul 25 04:43:36 PM PDT 24
Finished Jul 25 04:43:38 PM PDT 24
Peak memory 206304 kb
Host smart-3ad0ddfe-10ee-4e27-bf6d-bda03eb2f175
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3323417816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.3323417816
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3044056641
Short name T255
Test name
Test status
Simulation time 102176593 ps
CPU time 1.16 seconds
Started Jul 25 04:43:52 PM PDT 24
Finished Jul 25 04:43:54 PM PDT 24
Peak memory 214380 kb
Host smart-ac648d5d-5ad5-446b-aef2-bbc023a378bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044056641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.3044056641
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.590487341
Short name T2960
Test name
Test status
Simulation time 54344388 ps
CPU time 0.81 seconds
Started Jul 25 04:43:44 PM PDT 24
Finished Jul 25 04:43:45 PM PDT 24
Peak memory 206032 kb
Host smart-60acb462-22dd-4c32-bf2c-903f524851f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=590487341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.590487341
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3250959872
Short name T2875
Test name
Test status
Simulation time 44894042 ps
CPU time 0.69 seconds
Started Jul 25 04:43:09 PM PDT 24
Finished Jul 25 04:43:10 PM PDT 24
Peak memory 206056 kb
Host smart-ec3f151b-f3e3-46d6-802c-0fc3b538240d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3250959872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.3250959872
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3517306126
Short name T296
Test name
Test status
Simulation time 248684807 ps
CPU time 1.88 seconds
Started Jul 25 04:43:40 PM PDT 24
Finished Jul 25 04:43:42 PM PDT 24
Peak memory 206392 kb
Host smart-fe3e5729-5ca3-4254-b194-90ad3bf73656
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3517306126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.3517306126
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2191525566
Short name T2918
Test name
Test status
Simulation time 170289792 ps
CPU time 2.37 seconds
Started Jul 25 04:43:22 PM PDT 24
Finished Jul 25 04:43:25 PM PDT 24
Peak memory 206244 kb
Host smart-d15f9266-7c10-44bc-9d8c-6498b45530c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2191525566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.2191525566
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2113076355
Short name T257
Test name
Test status
Simulation time 2901482227 ps
CPU time 6.06 seconds
Started Jul 25 04:43:42 PM PDT 24
Finished Jul 25 04:43:49 PM PDT 24
Peak memory 206388 kb
Host smart-00156b53-8fb3-4aa9-a9d8-434f205632a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2113076355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.2113076355
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.469089038
Short name T298
Test name
Test status
Simulation time 108015450 ps
CPU time 1.34 seconds
Started Jul 25 04:43:33 PM PDT 24
Finished Jul 25 04:43:35 PM PDT 24
Peak memory 214800 kb
Host smart-27842d7e-ff1f-4af4-9cdd-1c6d98462392
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469089038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbde
v_csr_mem_rw_with_rand_reset.469089038
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1589859716
Short name T277
Test name
Test status
Simulation time 91310249 ps
CPU time 0.93 seconds
Started Jul 25 04:43:48 PM PDT 24
Finished Jul 25 04:43:49 PM PDT 24
Peak memory 206016 kb
Host smart-cdfb0bff-e9a4-477b-bedc-222525ae717b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1589859716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.1589859716
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2302262037
Short name T2927
Test name
Test status
Simulation time 60108364 ps
CPU time 0.79 seconds
Started Jul 25 04:43:52 PM PDT 24
Finished Jul 25 04:43:53 PM PDT 24
Peak memory 206224 kb
Host smart-c2e72c70-fd23-4074-a93d-b88f6179c79b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2302262037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.2302262037
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2138688362
Short name T217
Test name
Test status
Simulation time 100728757 ps
CPU time 1.4 seconds
Started Jul 25 04:43:07 PM PDT 24
Finished Jul 25 04:43:09 PM PDT 24
Peak memory 206356 kb
Host smart-7bff1271-5030-41cc-8d5f-4b298a694add
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2138688362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.2138688362
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.4197064867
Short name T212
Test name
Test status
Simulation time 81618710 ps
CPU time 1.74 seconds
Started Jul 25 04:43:51 PM PDT 24
Finished Jul 25 04:43:53 PM PDT 24
Peak memory 206356 kb
Host smart-747b8b43-5e15-424b-b98b-c8b9b8d7afb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4197064867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.4197064867
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.923953120
Short name T2893
Test name
Test status
Simulation time 77579540 ps
CPU time 1.87 seconds
Started Jul 25 04:43:29 PM PDT 24
Finished Jul 25 04:43:31 PM PDT 24
Peak memory 214608 kb
Host smart-833e547d-6ecc-4522-8ffe-ddef7a821b60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923953120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbde
v_csr_mem_rw_with_rand_reset.923953120
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2335826321
Short name T289
Test name
Test status
Simulation time 93199205 ps
CPU time 0.84 seconds
Started Jul 25 04:43:11 PM PDT 24
Finished Jul 25 04:43:17 PM PDT 24
Peak memory 206020 kb
Host smart-71b8d5d5-3289-4459-9839-52f1a3512b1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2335826321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.2335826321
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.790699387
Short name T2869
Test name
Test status
Simulation time 252017497 ps
CPU time 1.61 seconds
Started Jul 25 04:43:07 PM PDT 24
Finished Jul 25 04:43:09 PM PDT 24
Peak memory 206328 kb
Host smart-fec7730a-eb5a-4182-96ae-493d33c4bcc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=790699387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.790699387
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2588200048
Short name T244
Test name
Test status
Simulation time 64507234 ps
CPU time 1.44 seconds
Started Jul 25 04:43:35 PM PDT 24
Finished Jul 25 04:43:37 PM PDT 24
Peak memory 206384 kb
Host smart-11bf6178-2417-4296-998a-4d3b8e2f5981
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2588200048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.2588200048
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.430865294
Short name T2973
Test name
Test status
Simulation time 148114396 ps
CPU time 1.75 seconds
Started Jul 25 04:43:51 PM PDT 24
Finished Jul 25 04:43:53 PM PDT 24
Peak memory 214512 kb
Host smart-17cf4df3-629b-41f5-935c-d229321145b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430865294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbde
v_csr_mem_rw_with_rand_reset.430865294
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3809471938
Short name T2878
Test name
Test status
Simulation time 48729496 ps
CPU time 0.87 seconds
Started Jul 25 04:43:44 PM PDT 24
Finished Jul 25 04:43:45 PM PDT 24
Peak memory 206048 kb
Host smart-d67576d2-b425-4e3a-8672-2ad78be41c3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3809471938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.3809471938
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3532445171
Short name T225
Test name
Test status
Simulation time 93075637 ps
CPU time 0.76 seconds
Started Jul 25 04:43:54 PM PDT 24
Finished Jul 25 04:43:55 PM PDT 24
Peak memory 206008 kb
Host smart-bb0f886c-6312-494c-8876-6657b7d0f064
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3532445171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3532445171
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1392597120
Short name T215
Test name
Test status
Simulation time 229011500 ps
CPU time 1.74 seconds
Started Jul 25 04:43:52 PM PDT 24
Finished Jul 25 04:43:54 PM PDT 24
Peak memory 206368 kb
Host smart-a60cbcf6-83a5-405b-b363-fc93db169465
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1392597120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.1392597120
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2080334201
Short name T323
Test name
Test status
Simulation time 959036482 ps
CPU time 5.39 seconds
Started Jul 25 04:43:39 PM PDT 24
Finished Jul 25 04:43:44 PM PDT 24
Peak memory 206320 kb
Host smart-0f661021-07df-481c-b67d-5991e25bb7a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2080334201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.2080334201
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.584701375
Short name T2909
Test name
Test status
Simulation time 138350432 ps
CPU time 1.17 seconds
Started Jul 25 04:43:25 PM PDT 24
Finished Jul 25 04:43:27 PM PDT 24
Peak memory 222076 kb
Host smart-ea76bdcc-4467-48bc-a1ac-af265547afcc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584701375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbde
v_csr_mem_rw_with_rand_reset.584701375
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1237432369
Short name T283
Test name
Test status
Simulation time 68973674 ps
CPU time 0.88 seconds
Started Jul 25 04:43:40 PM PDT 24
Finished Jul 25 04:43:41 PM PDT 24
Peak memory 206132 kb
Host smart-144ab8a5-dfe4-48b5-ae3b-814520d245ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1237432369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.1237432369
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.3575373862
Short name T2879
Test name
Test status
Simulation time 36760004 ps
CPU time 0.7 seconds
Started Jul 25 04:43:10 PM PDT 24
Finished Jul 25 04:43:11 PM PDT 24
Peak memory 205996 kb
Host smart-f44545d8-797b-47d2-8d2a-57f132494fc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3575373862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.3575373862
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.48171496
Short name T2890
Test name
Test status
Simulation time 104212641 ps
CPU time 1.23 seconds
Started Jul 25 04:43:44 PM PDT 24
Finished Jul 25 04:43:46 PM PDT 24
Peak memory 206148 kb
Host smart-e5aeb7f7-9a3c-4f42-b974-f39b62657550
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=48171496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.48171496
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.611336270
Short name T2971
Test name
Test status
Simulation time 239294249 ps
CPU time 2.86 seconds
Started Jul 25 04:43:23 PM PDT 24
Finished Jul 25 04:43:26 PM PDT 24
Peak memory 206376 kb
Host smart-e99680ad-4f86-4c4f-8dbe-c28b48b4fdd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=611336270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.611336270
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.4057495517
Short name T256
Test name
Test status
Simulation time 619009500 ps
CPU time 2.79 seconds
Started Jul 25 04:43:42 PM PDT 24
Finished Jul 25 04:43:45 PM PDT 24
Peak memory 206280 kb
Host smart-233ba398-c2d3-42a3-be38-865df1e0e433
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4057495517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.4057495517
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1428256981
Short name T2914
Test name
Test status
Simulation time 56990940 ps
CPU time 1.43 seconds
Started Jul 25 04:43:33 PM PDT 24
Finished Jul 25 04:43:34 PM PDT 24
Peak memory 214544 kb
Host smart-8152f4eb-f369-4173-848b-d9af343e2504
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428256981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.1428256981
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2692354078
Short name T2958
Test name
Test status
Simulation time 51390247 ps
CPU time 0.85 seconds
Started Jul 25 04:43:19 PM PDT 24
Finished Jul 25 04:43:20 PM PDT 24
Peak memory 205992 kb
Host smart-30b25b7f-38d3-43eb-8551-efb76f460242
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2692354078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2692354078
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1170144911
Short name T2871
Test name
Test status
Simulation time 40014167 ps
CPU time 0.72 seconds
Started Jul 25 04:43:45 PM PDT 24
Finished Jul 25 04:43:46 PM PDT 24
Peak memory 206072 kb
Host smart-5d5025ca-370c-4d6d-9182-d854f4cd2265
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1170144911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.1170144911
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.951831419
Short name T291
Test name
Test status
Simulation time 136562749 ps
CPU time 1.3 seconds
Started Jul 25 04:43:42 PM PDT 24
Finished Jul 25 04:43:43 PM PDT 24
Peak memory 206428 kb
Host smart-b00f583e-9a14-42f6-9745-896c21dc0e90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=951831419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.951831419
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3110564352
Short name T2886
Test name
Test status
Simulation time 79326914 ps
CPU time 2.22 seconds
Started Jul 25 04:43:38 PM PDT 24
Finished Jul 25 04:43:40 PM PDT 24
Peak memory 206304 kb
Host smart-a491652d-9bd5-48c3-8a8f-9e747a69858c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3110564352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3110564352
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1329796516
Short name T326
Test name
Test status
Simulation time 1347102855 ps
CPU time 5.22 seconds
Started Jul 25 04:43:44 PM PDT 24
Finished Jul 25 04:43:49 PM PDT 24
Peak memory 206188 kb
Host smart-53af4f4e-5e27-4d82-8cd9-ea6375ebd899
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1329796516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.1329796516
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2661291490
Short name T2912
Test name
Test status
Simulation time 184546752 ps
CPU time 1.81 seconds
Started Jul 25 04:43:32 PM PDT 24
Finished Jul 25 04:43:34 PM PDT 24
Peak memory 214624 kb
Host smart-0b049125-d51d-4edd-9e02-7c72e338a44b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661291490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.2661291490
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.559741545
Short name T276
Test name
Test status
Simulation time 67422257 ps
CPU time 1.03 seconds
Started Jul 25 04:43:46 PM PDT 24
Finished Jul 25 04:43:47 PM PDT 24
Peak memory 206152 kb
Host smart-8bdbfab5-1588-441b-8612-cdab6f679fa5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=559741545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.559741545
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1844936164
Short name T2934
Test name
Test status
Simulation time 41982198 ps
CPU time 0.72 seconds
Started Jul 25 04:43:31 PM PDT 24
Finished Jul 25 04:43:32 PM PDT 24
Peak memory 206224 kb
Host smart-bd6e20df-b019-4fb4-9417-8ff58c151811
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1844936164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.1844936164
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3831844985
Short name T2885
Test name
Test status
Simulation time 119094572 ps
CPU time 1.06 seconds
Started Jul 25 04:43:45 PM PDT 24
Finished Jul 25 04:43:46 PM PDT 24
Peak memory 206124 kb
Host smart-1c6334a8-b721-46e7-8c64-7736914c27f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3831844985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.3831844985
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3713805082
Short name T246
Test name
Test status
Simulation time 128138781 ps
CPU time 1.71 seconds
Started Jul 25 04:43:17 PM PDT 24
Finished Jul 25 04:43:18 PM PDT 24
Peak memory 206344 kb
Host smart-5f123f52-6874-46fa-9f7c-7eff45646693
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3713805082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.3713805082
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.498682987
Short name T2954
Test name
Test status
Simulation time 167549368 ps
CPU time 1.95 seconds
Started Jul 25 04:43:45 PM PDT 24
Finished Jul 25 04:43:48 PM PDT 24
Peak memory 214648 kb
Host smart-b6afa9f0-6ed8-4880-b6b4-d92fc704ca52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498682987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbde
v_csr_mem_rw_with_rand_reset.498682987
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.4062409700
Short name T2913
Test name
Test status
Simulation time 57594375 ps
CPU time 0.84 seconds
Started Jul 25 04:43:44 PM PDT 24
Finished Jul 25 04:43:45 PM PDT 24
Peak memory 206160 kb
Host smart-ea998a5c-2657-4614-b6f7-d2f2a8c369ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4062409700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.4062409700
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.648320169
Short name T2931
Test name
Test status
Simulation time 79492100 ps
CPU time 0.77 seconds
Started Jul 25 04:43:42 PM PDT 24
Finished Jul 25 04:43:43 PM PDT 24
Peak memory 206016 kb
Host smart-6488202a-559e-4cd6-a5d1-07fc85ebd435
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=648320169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.648320169
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.55290695
Short name T2884
Test name
Test status
Simulation time 255579111 ps
CPU time 1.97 seconds
Started Jul 25 04:43:43 PM PDT 24
Finished Jul 25 04:43:45 PM PDT 24
Peak memory 206384 kb
Host smart-b496eee1-1e5b-4e51-82b0-8a034c074738
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=55290695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.55290695
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.864053660
Short name T2946
Test name
Test status
Simulation time 74806153 ps
CPU time 2.01 seconds
Started Jul 25 04:43:40 PM PDT 24
Finished Jul 25 04:43:42 PM PDT 24
Peak memory 206416 kb
Host smart-7fc7523e-097d-4195-9c89-2f23faa5164b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=864053660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.864053660
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.122287085
Short name T236
Test name
Test status
Simulation time 1895810761 ps
CPU time 6.24 seconds
Started Jul 25 04:43:42 PM PDT 24
Finished Jul 25 04:43:49 PM PDT 24
Peak memory 206260 kb
Host smart-fa1138ff-0ac6-4854-aec7-59d13248ed78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=122287085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.122287085
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2602014389
Short name T248
Test name
Test status
Simulation time 108120364 ps
CPU time 2.33 seconds
Started Jul 25 04:43:34 PM PDT 24
Finished Jul 25 04:43:36 PM PDT 24
Peak memory 214492 kb
Host smart-4abaf30b-ee43-4a2f-8b86-193834f4b1a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602014389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.2602014389
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2474756774
Short name T2940
Test name
Test status
Simulation time 44943622 ps
CPU time 1.02 seconds
Started Jul 25 04:43:44 PM PDT 24
Finished Jul 25 04:43:45 PM PDT 24
Peak memory 206144 kb
Host smart-e715139c-af67-47dc-b5d2-aaa8e5c5c5cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2474756774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.2474756774
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2471969608
Short name T2876
Test name
Test status
Simulation time 26946175 ps
CPU time 0.7 seconds
Started Jul 25 04:43:44 PM PDT 24
Finished Jul 25 04:43:45 PM PDT 24
Peak memory 206036 kb
Host smart-686d32df-e088-4086-9c60-6a3543a931bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2471969608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.2471969608
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2265141446
Short name T2897
Test name
Test status
Simulation time 146408523 ps
CPU time 1.56 seconds
Started Jul 25 04:43:30 PM PDT 24
Finished Jul 25 04:43:32 PM PDT 24
Peak memory 206392 kb
Host smart-7c61f9fc-2e64-48ce-899f-a9ea379ada02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2265141446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.2265141446
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.568593110
Short name T252
Test name
Test status
Simulation time 469534125 ps
CPU time 2.62 seconds
Started Jul 25 04:43:40 PM PDT 24
Finished Jul 25 04:43:42 PM PDT 24
Peak memory 206412 kb
Host smart-0ed330c0-a61b-4bdd-b88f-af1aaecd1d25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=568593110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.568593110
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.623059133
Short name T2963
Test name
Test status
Simulation time 88305005 ps
CPU time 1.91 seconds
Started Jul 25 04:43:10 PM PDT 24
Finished Jul 25 04:43:12 PM PDT 24
Peak memory 206228 kb
Host smart-ef21b303-1107-4696-8e56-b05446700828
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=623059133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.623059133
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1461024305
Short name T280
Test name
Test status
Simulation time 1102825369 ps
CPU time 8.27 seconds
Started Jul 25 04:43:10 PM PDT 24
Finished Jul 25 04:43:18 PM PDT 24
Peak memory 206284 kb
Host smart-7a20e8b8-d7a1-4639-8fd6-495ac2ac8381
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1461024305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.1461024305
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2162452349
Short name T2976
Test name
Test status
Simulation time 134922385 ps
CPU time 0.98 seconds
Started Jul 25 04:43:44 PM PDT 24
Finished Jul 25 04:43:45 PM PDT 24
Peak memory 206012 kb
Host smart-323a4f23-fa44-4573-bd61-791eeb4df562
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2162452349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.2162452349
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.218520760
Short name T2901
Test name
Test status
Simulation time 95977018 ps
CPU time 1.51 seconds
Started Jul 25 04:43:13 PM PDT 24
Finished Jul 25 04:43:14 PM PDT 24
Peak memory 214712 kb
Host smart-5c259768-701a-473d-ad04-6f16f73d0bcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218520760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev
_csr_mem_rw_with_rand_reset.218520760
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1105933277
Short name T2948
Test name
Test status
Simulation time 47959753 ps
CPU time 0.78 seconds
Started Jul 25 04:43:09 PM PDT 24
Finished Jul 25 04:43:10 PM PDT 24
Peak memory 206144 kb
Host smart-0f18dc15-67f2-46d2-951a-85d38a999299
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1105933277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.1105933277
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1864478430
Short name T2938
Test name
Test status
Simulation time 126289896 ps
CPU time 1.49 seconds
Started Jul 25 04:43:11 PM PDT 24
Finished Jul 25 04:43:13 PM PDT 24
Peak memory 214544 kb
Host smart-9d96179b-174e-408b-bf11-5228aa2ff707
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1864478430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.1864478430
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2460054058
Short name T2935
Test name
Test status
Simulation time 615878160 ps
CPU time 4.25 seconds
Started Jul 25 04:43:36 PM PDT 24
Finished Jul 25 04:43:41 PM PDT 24
Peak memory 206264 kb
Host smart-26c13393-68fa-403b-8749-6336da32d432
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2460054058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.2460054058
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1577641729
Short name T297
Test name
Test status
Simulation time 285062067 ps
CPU time 1.72 seconds
Started Jul 25 04:43:10 PM PDT 24
Finished Jul 25 04:43:12 PM PDT 24
Peak memory 206340 kb
Host smart-781f9b73-676b-4fa5-8127-cc9cd7e3123b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1577641729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.1577641729
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1003990150
Short name T247
Test name
Test status
Simulation time 89021399 ps
CPU time 2.38 seconds
Started Jul 25 04:43:10 PM PDT 24
Finished Jul 25 04:43:13 PM PDT 24
Peak memory 214580 kb
Host smart-5ac1b981-e303-4157-8ce2-a32c0cab3839
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1003990150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1003990150
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.73533526
Short name T2921
Test name
Test status
Simulation time 623956606 ps
CPU time 2.8 seconds
Started Jul 25 04:43:07 PM PDT 24
Finished Jul 25 04:43:11 PM PDT 24
Peak memory 206376 kb
Host smart-da18908d-cdb8-4cae-b91d-75ff97b6664b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=73533526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.73533526
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3993657243
Short name T2942
Test name
Test status
Simulation time 44632563 ps
CPU time 0.72 seconds
Started Jul 25 04:43:35 PM PDT 24
Finished Jul 25 04:43:36 PM PDT 24
Peak memory 206000 kb
Host smart-54f5f441-021d-44ca-b81f-011c03f69e75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3993657243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.3993657243
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1310657168
Short name T2870
Test name
Test status
Simulation time 59563942 ps
CPU time 0.73 seconds
Started Jul 25 04:43:27 PM PDT 24
Finished Jul 25 04:43:28 PM PDT 24
Peak memory 206048 kb
Host smart-f0a7448e-9732-4ec4-a9c8-013e5c7cfd29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1310657168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.1310657168
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1177552849
Short name T321
Test name
Test status
Simulation time 72969669 ps
CPU time 0.75 seconds
Started Jul 25 04:43:40 PM PDT 24
Finished Jul 25 04:43:41 PM PDT 24
Peak memory 206036 kb
Host smart-1dd9ee95-6875-43fd-a93d-48e67d1a9275
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1177552849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.1177552849
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.431496256
Short name T2919
Test name
Test status
Simulation time 99351407 ps
CPU time 0.76 seconds
Started Jul 25 04:43:56 PM PDT 24
Finished Jul 25 04:43:57 PM PDT 24
Peak memory 206028 kb
Host smart-49a1f8a9-8b7f-4f18-9297-f8303fa3074c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=431496256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.431496256
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1621746268
Short name T2950
Test name
Test status
Simulation time 40130769 ps
CPU time 0.75 seconds
Started Jul 25 04:43:44 PM PDT 24
Finished Jul 25 04:43:45 PM PDT 24
Peak memory 205996 kb
Host smart-5f1b0188-6eb1-4f14-8b3e-b10bd39421fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1621746268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.1621746268
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2803902926
Short name T2903
Test name
Test status
Simulation time 44667012 ps
CPU time 0.73 seconds
Started Jul 25 04:43:45 PM PDT 24
Finished Jul 25 04:43:46 PM PDT 24
Peak memory 206028 kb
Host smart-0e6eb6bf-6ef4-4cd8-b86e-113f0ca0448e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2803902926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.2803902926
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3460098671
Short name T299
Test name
Test status
Simulation time 41957246 ps
CPU time 0.71 seconds
Started Jul 25 04:43:41 PM PDT 24
Finished Jul 25 04:43:42 PM PDT 24
Peak memory 206064 kb
Host smart-476d5d7a-afe2-479d-a52f-a35bd5cfe8c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3460098671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.3460098671
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3700771078
Short name T316
Test name
Test status
Simulation time 39792666 ps
CPU time 0.73 seconds
Started Jul 25 04:43:39 PM PDT 24
Finished Jul 25 04:43:40 PM PDT 24
Peak memory 206032 kb
Host smart-82c4cf19-b341-4ba7-841a-34551162ab91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3700771078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.3700771078
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.517780006
Short name T2881
Test name
Test status
Simulation time 50523291 ps
CPU time 0.78 seconds
Started Jul 25 04:44:06 PM PDT 24
Finished Jul 25 04:44:07 PM PDT 24
Peak memory 206132 kb
Host smart-84512166-d8b9-4b91-8c2f-bd8bdb2b46eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=517780006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.517780006
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3052677084
Short name T281
Test name
Test status
Simulation time 294277989 ps
CPU time 3.65 seconds
Started Jul 25 04:43:37 PM PDT 24
Finished Jul 25 04:43:41 PM PDT 24
Peak memory 206340 kb
Host smart-ddc0feff-cd0a-468a-bb4c-f18a9e9f8da6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3052677084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3052677084
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2155658152
Short name T2906
Test name
Test status
Simulation time 1263712233 ps
CPU time 8.96 seconds
Started Jul 25 04:43:34 PM PDT 24
Finished Jul 25 04:43:44 PM PDT 24
Peak memory 206316 kb
Host smart-cd82f11c-51dc-41ca-a3e9-137240f7f948
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2155658152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.2155658152
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3978930906
Short name T2949
Test name
Test status
Simulation time 79319677 ps
CPU time 0.92 seconds
Started Jul 25 04:43:07 PM PDT 24
Finished Jul 25 04:43:09 PM PDT 24
Peak memory 206124 kb
Host smart-892f1ca3-a090-46e4-86bd-5ab09133f1b0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3978930906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3978930906
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3563807725
Short name T211
Test name
Test status
Simulation time 83903933 ps
CPU time 1.76 seconds
Started Jul 25 04:43:21 PM PDT 24
Finished Jul 25 04:43:23 PM PDT 24
Peak memory 214588 kb
Host smart-4b7634a8-496a-4458-8f79-ffc9a3a34090
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563807725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.3563807725
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2738428525
Short name T2972
Test name
Test status
Simulation time 87589885 ps
CPU time 1.01 seconds
Started Jul 25 04:43:37 PM PDT 24
Finished Jul 25 04:43:39 PM PDT 24
Peak memory 206108 kb
Host smart-81bfdd7f-a351-45fc-85ec-c50b72bb52df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2738428525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2738428525
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1022787116
Short name T2889
Test name
Test status
Simulation time 68772287 ps
CPU time 0.77 seconds
Started Jul 25 04:43:41 PM PDT 24
Finished Jul 25 04:43:42 PM PDT 24
Peak memory 206012 kb
Host smart-7a847fcf-db96-4d67-870c-845df99bffbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1022787116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.1022787116
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.492613774
Short name T2896
Test name
Test status
Simulation time 180219023 ps
CPU time 1.55 seconds
Started Jul 25 04:43:28 PM PDT 24
Finished Jul 25 04:43:29 PM PDT 24
Peak memory 206252 kb
Host smart-7883f26a-6ee7-4ab9-811e-c1322ae27140
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=492613774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.492613774
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.461792299
Short name T2888
Test name
Test status
Simulation time 262938108 ps
CPU time 2.65 seconds
Started Jul 25 04:43:14 PM PDT 24
Finished Jul 25 04:43:17 PM PDT 24
Peak memory 206272 kb
Host smart-30c019bc-5ccb-4170-bfc1-ed5eaa19d43b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=461792299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.461792299
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.679836623
Short name T2962
Test name
Test status
Simulation time 182949695 ps
CPU time 1.75 seconds
Started Jul 25 04:43:07 PM PDT 24
Finished Jul 25 04:43:10 PM PDT 24
Peak memory 206348 kb
Host smart-6eab5b78-32c5-479b-9a4c-087a53da354b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=679836623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.679836623
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.4228643131
Short name T2917
Test name
Test status
Simulation time 253562388 ps
CPU time 2.85 seconds
Started Jul 25 04:43:07 PM PDT 24
Finished Jul 25 04:43:10 PM PDT 24
Peak memory 206296 kb
Host smart-b3cfaa98-3362-4e4e-b710-6240aa3ea80b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4228643131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.4228643131
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.365092701
Short name T295
Test name
Test status
Simulation time 577004538 ps
CPU time 2.74 seconds
Started Jul 25 04:43:08 PM PDT 24
Finished Jul 25 04:43:11 PM PDT 24
Peak memory 206352 kb
Host smart-d785bbed-22c2-4f1c-96e1-d90982dee7fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=365092701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.365092701
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.50459845
Short name T2880
Test name
Test status
Simulation time 50416245 ps
CPU time 0.69 seconds
Started Jul 25 04:43:54 PM PDT 24
Finished Jul 25 04:43:55 PM PDT 24
Peak memory 206012 kb
Host smart-37d24207-b6f0-428f-ad78-77f3de5ae3fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=50459845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.50459845
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.1948274370
Short name T2873
Test name
Test status
Simulation time 76531462 ps
CPU time 0.74 seconds
Started Jul 25 04:43:54 PM PDT 24
Finished Jul 25 04:43:55 PM PDT 24
Peak memory 206032 kb
Host smart-e35771df-479c-4466-9362-84421029c2f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1948274370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.1948274370
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3449266260
Short name T2911
Test name
Test status
Simulation time 42571933 ps
CPU time 0.7 seconds
Started Jul 25 04:43:36 PM PDT 24
Finished Jul 25 04:43:37 PM PDT 24
Peak memory 206016 kb
Host smart-4fd1bf65-3d77-458d-bbd4-7d491bc111d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3449266260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.3449266260
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2429583884
Short name T2872
Test name
Test status
Simulation time 35620996 ps
CPU time 0.73 seconds
Started Jul 25 04:43:37 PM PDT 24
Finished Jul 25 04:43:38 PM PDT 24
Peak memory 206032 kb
Host smart-dcfd6228-d927-43fa-8094-3c2cb17ddfb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2429583884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.2429583884
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1872856902
Short name T2892
Test name
Test status
Simulation time 59217406 ps
CPU time 0.79 seconds
Started Jul 25 04:43:40 PM PDT 24
Finished Jul 25 04:43:41 PM PDT 24
Peak memory 206056 kb
Host smart-b07b2d5c-08dc-4378-8617-b2b510b64d81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1872856902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.1872856902
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2366556336
Short name T2900
Test name
Test status
Simulation time 115850463 ps
CPU time 0.81 seconds
Started Jul 25 04:43:44 PM PDT 24
Finished Jul 25 04:43:45 PM PDT 24
Peak memory 206024 kb
Host smart-8009239d-b3f2-4536-a8c0-6199cf2df848
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2366556336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.2366556336
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1623864931
Short name T2894
Test name
Test status
Simulation time 53801140 ps
CPU time 0.8 seconds
Started Jul 25 04:43:37 PM PDT 24
Finished Jul 25 04:43:38 PM PDT 24
Peak memory 206060 kb
Host smart-10a0359d-4b39-45da-9fff-cbf4c405f1fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1623864931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.1623864931
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2502730149
Short name T2877
Test name
Test status
Simulation time 41507440 ps
CPU time 0.75 seconds
Started Jul 25 04:43:50 PM PDT 24
Finished Jul 25 04:43:51 PM PDT 24
Peak memory 206028 kb
Host smart-f6c9659a-90e9-4ae1-ad3c-bc87b9a0ca33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2502730149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.2502730149
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.96489130
Short name T2969
Test name
Test status
Simulation time 50455425 ps
CPU time 0.73 seconds
Started Jul 25 04:43:52 PM PDT 24
Finished Jul 25 04:43:53 PM PDT 24
Peak memory 205976 kb
Host smart-50e6829c-0884-4acc-a53c-8dd411fc9b09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=96489130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.96489130
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3246993302
Short name T319
Test name
Test status
Simulation time 68651857 ps
CPU time 0.77 seconds
Started Jul 25 04:43:34 PM PDT 24
Finished Jul 25 04:43:35 PM PDT 24
Peak memory 206028 kb
Host smart-f552b36f-3423-43fe-8056-fe12e989b888
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3246993302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3246993302
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.527365711
Short name T2929
Test name
Test status
Simulation time 301398273 ps
CPU time 3.55 seconds
Started Jul 25 04:43:36 PM PDT 24
Finished Jul 25 04:43:39 PM PDT 24
Peak memory 206336 kb
Host smart-0a434fdb-218e-4e3c-b1de-9d1f5abce9af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=527365711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.527365711
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.338264081
Short name T275
Test name
Test status
Simulation time 863873064 ps
CPU time 4.48 seconds
Started Jul 25 04:43:09 PM PDT 24
Finished Jul 25 04:43:14 PM PDT 24
Peak memory 206320 kb
Host smart-dabc5577-7d7e-4294-acb7-c1ae6f1c37b2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=338264081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.338264081
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1357624711
Short name T2915
Test name
Test status
Simulation time 49525025 ps
CPU time 0.87 seconds
Started Jul 25 04:43:39 PM PDT 24
Finished Jul 25 04:43:40 PM PDT 24
Peak memory 206112 kb
Host smart-ef225ff8-52f8-4efd-8d4d-e6998bc45210
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1357624711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.1357624711
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3594615334
Short name T300
Test name
Test status
Simulation time 103475185 ps
CPU time 1.31 seconds
Started Jul 25 04:43:40 PM PDT 24
Finished Jul 25 04:43:42 PM PDT 24
Peak memory 214528 kb
Host smart-457a29e4-0b1a-4639-a1c0-917e4e56f713
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594615334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.3594615334
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2200435355
Short name T285
Test name
Test status
Simulation time 57812479 ps
CPU time 0.83 seconds
Started Jul 25 04:43:34 PM PDT 24
Finished Jul 25 04:43:36 PM PDT 24
Peak memory 206116 kb
Host smart-2a908cb1-d880-4df3-867f-0f4bf7d4ee9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2200435355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.2200435355
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.4098769529
Short name T2957
Test name
Test status
Simulation time 39137383 ps
CPU time 0.7 seconds
Started Jul 25 04:43:46 PM PDT 24
Finished Jul 25 04:43:47 PM PDT 24
Peak memory 206040 kb
Host smart-1daf252b-6008-45e4-82f1-7baffddfb4f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4098769529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.4098769529
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2317216213
Short name T286
Test name
Test status
Simulation time 131098647 ps
CPU time 1.56 seconds
Started Jul 25 04:43:11 PM PDT 24
Finished Jul 25 04:43:12 PM PDT 24
Peak memory 206180 kb
Host smart-e904412c-f384-487c-add7-b18207b07daa
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2317216213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2317216213
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.637239653
Short name T2926
Test name
Test status
Simulation time 169672912 ps
CPU time 3.98 seconds
Started Jul 25 04:43:54 PM PDT 24
Finished Jul 25 04:43:59 PM PDT 24
Peak memory 206252 kb
Host smart-1d9c6381-66a8-4732-be1d-004b81be9272
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=637239653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.637239653
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3089859909
Short name T2964
Test name
Test status
Simulation time 248282184 ps
CPU time 1.68 seconds
Started Jul 25 04:43:54 PM PDT 24
Finished Jul 25 04:43:56 PM PDT 24
Peak memory 206336 kb
Host smart-ad4cd835-20c8-4d31-9639-62f6871e515c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3089859909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.3089859909
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3403332727
Short name T2908
Test name
Test status
Simulation time 217733995 ps
CPU time 2.27 seconds
Started Jul 25 04:43:24 PM PDT 24
Finished Jul 25 04:43:26 PM PDT 24
Peak memory 222452 kb
Host smart-c29e43b7-a974-4b47-a2d4-10e51ed7b0cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3403332727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3403332727
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2610822877
Short name T2975
Test name
Test status
Simulation time 689999659 ps
CPU time 2.97 seconds
Started Jul 25 04:43:14 PM PDT 24
Finished Jul 25 04:43:17 PM PDT 24
Peak memory 206336 kb
Host smart-9d35336c-5105-41a5-9a9f-62e63c20dc29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2610822877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.2610822877
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1029889259
Short name T314
Test name
Test status
Simulation time 32457888 ps
CPU time 0.69 seconds
Started Jul 25 04:43:49 PM PDT 24
Finished Jul 25 04:43:50 PM PDT 24
Peak memory 206036 kb
Host smart-2d707a1c-6bd2-46f6-95c9-b61b3ef3878d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1029889259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.1029889259
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2008107876
Short name T320
Test name
Test status
Simulation time 79572867 ps
CPU time 0.83 seconds
Started Jul 25 04:43:47 PM PDT 24
Finished Jul 25 04:43:48 PM PDT 24
Peak memory 206028 kb
Host smart-913e29c6-bc36-4f69-abd4-d3147817bb4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2008107876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.2008107876
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3953152264
Short name T2955
Test name
Test status
Simulation time 56691101 ps
CPU time 0.78 seconds
Started Jul 25 04:43:43 PM PDT 24
Finished Jul 25 04:43:44 PM PDT 24
Peak memory 206008 kb
Host smart-bba3fa24-52a0-4361-9cd8-f491b14c726d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3953152264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3953152264
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2662487511
Short name T2961
Test name
Test status
Simulation time 57980818 ps
CPU time 0.74 seconds
Started Jul 25 04:43:42 PM PDT 24
Finished Jul 25 04:43:43 PM PDT 24
Peak memory 205992 kb
Host smart-937062f2-97ca-46b1-84ca-aa5354d54a82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2662487511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.2662487511
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.3813156366
Short name T2868
Test name
Test status
Simulation time 51284913 ps
CPU time 0.73 seconds
Started Jul 25 04:43:53 PM PDT 24
Finished Jul 25 04:43:54 PM PDT 24
Peak memory 206000 kb
Host smart-09f95ff4-5c8c-448f-9c1e-d7d1ec38829e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3813156366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.3813156366
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3984743104
Short name T2932
Test name
Test status
Simulation time 37396950 ps
CPU time 0.66 seconds
Started Jul 25 04:43:55 PM PDT 24
Finished Jul 25 04:43:56 PM PDT 24
Peak memory 206020 kb
Host smart-2772ed54-af2b-4ac0-a522-458415f6fef5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3984743104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.3984743104
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.767468350
Short name T223
Test name
Test status
Simulation time 39305954 ps
CPU time 0.72 seconds
Started Jul 25 04:43:43 PM PDT 24
Finished Jul 25 04:43:44 PM PDT 24
Peak memory 206064 kb
Host smart-30cbe09a-84ee-4539-a7ff-80b5080c056c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=767468350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.767468350
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3496092657
Short name T2941
Test name
Test status
Simulation time 41191953 ps
CPU time 0.72 seconds
Started Jul 25 04:43:29 PM PDT 24
Finished Jul 25 04:43:35 PM PDT 24
Peak memory 206036 kb
Host smart-f53ef612-bf15-4e55-a7f3-7a9ec48f14ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3496092657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.3496092657
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2406023117
Short name T2952
Test name
Test status
Simulation time 46675030 ps
CPU time 0.82 seconds
Started Jul 25 04:43:41 PM PDT 24
Finished Jul 25 04:43:42 PM PDT 24
Peak memory 206020 kb
Host smart-9edb337b-9650-4702-a351-5875710e48a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2406023117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.2406023117
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.515539375
Short name T2939
Test name
Test status
Simulation time 97196693 ps
CPU time 1.35 seconds
Started Jul 25 04:43:10 PM PDT 24
Finished Jul 25 04:43:12 PM PDT 24
Peak memory 222808 kb
Host smart-1dcea121-cb5e-4c7a-a3e3-6d6fae0c9b1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515539375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev
_csr_mem_rw_with_rand_reset.515539375
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2747230616
Short name T2922
Test name
Test status
Simulation time 37130646 ps
CPU time 0.78 seconds
Started Jul 25 04:43:41 PM PDT 24
Finished Jul 25 04:43:42 PM PDT 24
Peak memory 206016 kb
Host smart-8cee7384-f567-4b3a-bcb1-5347aedae473
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2747230616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.2747230616
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.127709491
Short name T2925
Test name
Test status
Simulation time 43272079 ps
CPU time 0.75 seconds
Started Jul 25 04:43:39 PM PDT 24
Finished Jul 25 04:43:40 PM PDT 24
Peak memory 206044 kb
Host smart-7ceead8a-4dd3-4d10-9a3c-e454e8f629cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=127709491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.127709491
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.290204534
Short name T2965
Test name
Test status
Simulation time 118078687 ps
CPU time 1.18 seconds
Started Jul 25 04:43:23 PM PDT 24
Finished Jul 25 04:43:29 PM PDT 24
Peak memory 206036 kb
Host smart-d5c58669-186d-4485-85c3-7f23b7cb049d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=290204534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.290204534
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3218348363
Short name T2928
Test name
Test status
Simulation time 285881056 ps
CPU time 3.54 seconds
Started Jul 25 04:43:27 PM PDT 24
Finished Jul 25 04:43:31 PM PDT 24
Peak memory 220264 kb
Host smart-fcd0b585-bc41-48ed-9b5f-7138becc5846
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3218348363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.3218348363
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3073236301
Short name T322
Test name
Test status
Simulation time 1571902784 ps
CPU time 5.18 seconds
Started Jul 25 04:43:47 PM PDT 24
Finished Jul 25 04:43:52 PM PDT 24
Peak memory 206324 kb
Host smart-c53326f5-f773-40ff-b982-97f1ba5bca85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3073236301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.3073236301
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3688688147
Short name T2945
Test name
Test status
Simulation time 130769290 ps
CPU time 1.74 seconds
Started Jul 25 04:43:30 PM PDT 24
Finished Jul 25 04:43:32 PM PDT 24
Peak memory 214664 kb
Host smart-8a242976-c5b5-4575-8e01-4ba69c7961d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688688147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.3688688147
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1257732598
Short name T2895
Test name
Test status
Simulation time 77582212 ps
CPU time 1.02 seconds
Started Jul 25 04:43:31 PM PDT 24
Finished Jul 25 04:43:32 PM PDT 24
Peak memory 206136 kb
Host smart-70bdc426-b562-4fdb-8006-b327fa8a7c70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1257732598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1257732598
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2738436538
Short name T2883
Test name
Test status
Simulation time 35101138 ps
CPU time 0.69 seconds
Started Jul 25 04:43:27 PM PDT 24
Finished Jul 25 04:43:28 PM PDT 24
Peak memory 206004 kb
Host smart-140801e4-209a-4d9f-9612-f3c9622e4ed0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2738436538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.2738436538
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3021719430
Short name T290
Test name
Test status
Simulation time 95307305 ps
CPU time 1.25 seconds
Started Jul 25 04:43:41 PM PDT 24
Finished Jul 25 04:43:43 PM PDT 24
Peak memory 206600 kb
Host smart-a6bf8842-d8e8-44b5-ad3f-8a689d337ff9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3021719430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.3021719430
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1473448412
Short name T2974
Test name
Test status
Simulation time 108666479 ps
CPU time 2.92 seconds
Started Jul 25 04:43:54 PM PDT 24
Finished Jul 25 04:43:57 PM PDT 24
Peak memory 206344 kb
Host smart-97396f88-b230-4ec6-813d-bdeede53dc6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1473448412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1473448412
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2292551338
Short name T324
Test name
Test status
Simulation time 801573923 ps
CPU time 2.96 seconds
Started Jul 25 04:43:40 PM PDT 24
Finished Jul 25 04:43:44 PM PDT 24
Peak memory 206392 kb
Host smart-0404c177-3fa2-47cc-be7f-382445530caf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2292551338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.2292551338
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.310340838
Short name T2966
Test name
Test status
Simulation time 66039755 ps
CPU time 1.54 seconds
Started Jul 25 04:43:26 PM PDT 24
Finished Jul 25 04:43:28 PM PDT 24
Peak memory 214616 kb
Host smart-a5ae4bcb-c05f-4c2c-bd89-b5986841b1c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310340838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev
_csr_mem_rw_with_rand_reset.310340838
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1349895720
Short name T2933
Test name
Test status
Simulation time 60877928 ps
CPU time 0.89 seconds
Started Jul 25 04:43:26 PM PDT 24
Finished Jul 25 04:43:28 PM PDT 24
Peak memory 206036 kb
Host smart-ac8b39a2-2e25-42e2-874f-d18a3bc8bdb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1349895720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.1349895720
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.1212348999
Short name T317
Test name
Test status
Simulation time 41582781 ps
CPU time 0.71 seconds
Started Jul 25 04:43:08 PM PDT 24
Finished Jul 25 04:43:09 PM PDT 24
Peak memory 206032 kb
Host smart-3a576ae8-b874-4e0f-8902-fd3f068a8443
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1212348999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.1212348999
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1418693673
Short name T2943
Test name
Test status
Simulation time 192205260 ps
CPU time 1.34 seconds
Started Jul 25 04:43:46 PM PDT 24
Finished Jul 25 04:43:48 PM PDT 24
Peak memory 206296 kb
Host smart-a7a97d46-21fa-4d64-b1e3-84e9c021cb51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1418693673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.1418693673
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3567872558
Short name T2967
Test name
Test status
Simulation time 178594670 ps
CPU time 2.39 seconds
Started Jul 25 04:43:25 PM PDT 24
Finished Jul 25 04:43:28 PM PDT 24
Peak memory 206304 kb
Host smart-08df0bd5-123e-4ccf-aa84-24210a62c2bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3567872558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.3567872558
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.4084568792
Short name T2902
Test name
Test status
Simulation time 757860586 ps
CPU time 4.74 seconds
Started Jul 25 04:43:39 PM PDT 24
Finished Jul 25 04:43:44 PM PDT 24
Peak memory 206244 kb
Host smart-b0200f10-f432-4d96-9a58-2eb260bce127
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4084568792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.4084568792
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2070776697
Short name T254
Test name
Test status
Simulation time 80181296 ps
CPU time 1.2 seconds
Started Jul 25 04:43:16 PM PDT 24
Finished Jul 25 04:43:17 PM PDT 24
Peak memory 214368 kb
Host smart-9c462641-6dd6-4af2-8a46-4b64ac80ec2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070776697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.2070776697
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1013989978
Short name T2904
Test name
Test status
Simulation time 34217920 ps
CPU time 0.74 seconds
Started Jul 25 04:43:37 PM PDT 24
Finished Jul 25 04:43:38 PM PDT 24
Peak memory 206048 kb
Host smart-55e0bf60-e7f5-41a4-8051-20a97a1c0c20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1013989978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.1013989978
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3720337852
Short name T2920
Test name
Test status
Simulation time 121646866 ps
CPU time 1.07 seconds
Started Jul 25 04:43:13 PM PDT 24
Finished Jul 25 04:43:14 PM PDT 24
Peak memory 206144 kb
Host smart-caf14596-7b72-4887-94d9-cbfa70796277
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3720337852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.3720337852
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2409219815
Short name T242
Test name
Test status
Simulation time 247007761 ps
CPU time 2.44 seconds
Started Jul 25 04:43:41 PM PDT 24
Finished Jul 25 04:43:44 PM PDT 24
Peak memory 214528 kb
Host smart-b0d5f833-6af3-4579-ae57-e85952ab7b3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2409219815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.2409219815
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1490234017
Short name T2891
Test name
Test status
Simulation time 594492634 ps
CPU time 2.61 seconds
Started Jul 25 04:43:08 PM PDT 24
Finished Jul 25 04:43:11 PM PDT 24
Peak memory 206388 kb
Host smart-bb188c12-e2ae-46db-aae2-f19d7cb9d971
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1490234017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.1490234017
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3291003188
Short name T2951
Test name
Test status
Simulation time 82159038 ps
CPU time 1.69 seconds
Started Jul 25 04:43:33 PM PDT 24
Finished Jul 25 04:43:35 PM PDT 24
Peak memory 214608 kb
Host smart-2f1b033b-6d6b-4e4f-80de-31e2fd2404f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291003188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.3291003188
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2128191623
Short name T278
Test name
Test status
Simulation time 55819187 ps
CPU time 0.8 seconds
Started Jul 25 04:43:49 PM PDT 24
Finished Jul 25 04:43:50 PM PDT 24
Peak memory 206120 kb
Host smart-5241ba9f-ce20-41a0-ad59-d05879d058e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2128191623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2128191623
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.577124010
Short name T2907
Test name
Test status
Simulation time 73468402 ps
CPU time 0.75 seconds
Started Jul 25 04:43:10 PM PDT 24
Finished Jul 25 04:43:11 PM PDT 24
Peak memory 206044 kb
Host smart-4c4591f6-f139-41e0-8726-d63012930183
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=577124010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.577124010
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1256783434
Short name T2905
Test name
Test status
Simulation time 180486215 ps
CPU time 1.76 seconds
Started Jul 25 04:43:25 PM PDT 24
Finished Jul 25 04:43:27 PM PDT 24
Peak memory 206380 kb
Host smart-318cb03a-e7fc-40dd-9df0-bc44d4698296
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1256783434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.1256783434
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.236518269
Short name T2936
Test name
Test status
Simulation time 279694785 ps
CPU time 2.87 seconds
Started Jul 25 04:43:56 PM PDT 24
Finished Jul 25 04:43:59 PM PDT 24
Peak memory 206376 kb
Host smart-8a59bf47-05e5-4c2d-9e31-047593bb18f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=236518269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.236518269
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3259916771
Short name T2882
Test name
Test status
Simulation time 451342934 ps
CPU time 3.22 seconds
Started Jul 25 04:43:49 PM PDT 24
Finished Jul 25 04:43:53 PM PDT 24
Peak memory 206356 kb
Host smart-6c23a72f-eafc-457a-9bc1-69d393fc3c3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3259916771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.3259916771
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.1909537524
Short name T1418
Test name
Test status
Simulation time 41403201 ps
CPU time 0.69 seconds
Started Jul 25 07:00:37 PM PDT 24
Finished Jul 25 07:00:38 PM PDT 24
Peak memory 207160 kb
Host smart-f35eba94-09cb-4f41-a25f-dfbbd6d3516e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1909537524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.1909537524
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.1993180562
Short name T1335
Test name
Test status
Simulation time 4010430542 ps
CPU time 6.3 seconds
Started Jul 25 07:00:14 PM PDT 24
Finished Jul 25 07:00:20 PM PDT 24
Peak memory 207364 kb
Host smart-7497212c-e612-4235-bbd8-e13208f0b861
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993180562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_disconnect.1993180562
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.2915559284
Short name T906
Test name
Test status
Simulation time 13361708216 ps
CPU time 18.43 seconds
Started Jul 25 07:00:13 PM PDT 24
Finished Jul 25 07:00:33 PM PDT 24
Peak memory 207396 kb
Host smart-6ce12b5d-5ada-48f5-b007-2756362dca47
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915559284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.2915559284
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.3998950393
Short name T2487
Test name
Test status
Simulation time 23331550673 ps
CPU time 25.51 seconds
Started Jul 25 07:00:13 PM PDT 24
Finished Jul 25 07:00:39 PM PDT 24
Peak memory 207376 kb
Host smart-4afcaa7b-2dbd-414b-bee6-f48f0fa24d6e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998950393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_resume.3998950393
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.4219092081
Short name T1780
Test name
Test status
Simulation time 174389798 ps
CPU time 0.88 seconds
Started Jul 25 07:00:11 PM PDT 24
Finished Jul 25 07:00:12 PM PDT 24
Peak memory 207084 kb
Host smart-604c4461-0ac1-4a84-82d6-9d621288aa94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42190
92081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.4219092081
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.3351385633
Short name T822
Test name
Test status
Simulation time 146856314 ps
CPU time 0.83 seconds
Started Jul 25 07:00:12 PM PDT 24
Finished Jul 25 07:00:13 PM PDT 24
Peak memory 207156 kb
Host smart-4ab1d0be-5688-4a7b-8ff3-69c6e73b97be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33513
85633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.3351385633
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.4176781502
Short name T411
Test name
Test status
Simulation time 170165806 ps
CPU time 0.87 seconds
Started Jul 25 07:00:13 PM PDT 24
Finished Jul 25 07:00:14 PM PDT 24
Peak memory 207092 kb
Host smart-cbdeaa34-da0e-4a67-af6b-9a4925db414c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41767
81502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.4176781502
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.3322079605
Short name T2512
Test name
Test status
Simulation time 403062145 ps
CPU time 1.28 seconds
Started Jul 25 07:00:12 PM PDT 24
Finished Jul 25 07:00:14 PM PDT 24
Peak memory 207124 kb
Host smart-0a91b8d8-333c-4347-936c-03cebacdb039
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3322079605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.3322079605
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.1903017696
Short name T1611
Test name
Test status
Simulation time 19231229859 ps
CPU time 44.55 seconds
Started Jul 25 07:00:14 PM PDT 24
Finished Jul 25 07:00:59 PM PDT 24
Peak memory 207368 kb
Host smart-0077c24f-51df-4e6f-abe3-db8015785417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19030
17696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.1903017696
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_device_timeout.578544888
Short name T1410
Test name
Test status
Simulation time 4330368638 ps
CPU time 29.02 seconds
Started Jul 25 07:00:15 PM PDT 24
Finished Jul 25 07:00:44 PM PDT 24
Peak memory 207412 kb
Host smart-fc624f9c-ecb6-4438-aabe-33f8f35fd0aa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578544888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_timeout.578544888
Directory /workspace/0.usbdev_device_timeout/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.4000884468
Short name T2111
Test name
Test status
Simulation time 485926507 ps
CPU time 1.55 seconds
Started Jul 25 07:00:27 PM PDT 24
Finished Jul 25 07:00:29 PM PDT 24
Peak memory 207068 kb
Host smart-c3253bc8-71a2-4faf-b758-988d9f47123c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40008
84468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.4000884468
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.1559875903
Short name T2153
Test name
Test status
Simulation time 168441551 ps
CPU time 0.85 seconds
Started Jul 25 07:00:21 PM PDT 24
Finished Jul 25 07:00:22 PM PDT 24
Peak memory 207104 kb
Host smart-5ae259b4-7df7-49e8-8050-e621988e4cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15598
75903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.1559875903
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_enable.2137981736
Short name T2720
Test name
Test status
Simulation time 58646368 ps
CPU time 0.72 seconds
Started Jul 25 07:00:25 PM PDT 24
Finished Jul 25 07:00:26 PM PDT 24
Peak memory 207060 kb
Host smart-4ba92eb0-222b-416e-a3ed-5da6544a4b37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21379
81736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.2137981736
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.2128208405
Short name T1995
Test name
Test status
Simulation time 893052455 ps
CPU time 2.5 seconds
Started Jul 25 07:00:25 PM PDT 24
Finished Jul 25 07:00:28 PM PDT 24
Peak memory 207388 kb
Host smart-4f115ab5-0b1b-4900-aaab-1dd722adb0ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21282
08405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.2128208405
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.914607680
Short name T1361
Test name
Test status
Simulation time 171405011 ps
CPU time 1.81 seconds
Started Jul 25 07:00:23 PM PDT 24
Finished Jul 25 07:00:25 PM PDT 24
Peak memory 207332 kb
Host smart-1748f5f8-b231-4422-b4ae-7d92b16e6764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91460
7680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.914607680
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.948521304
Short name T339
Test name
Test status
Simulation time 96239420048 ps
CPU time 160.01 seconds
Started Jul 25 07:00:20 PM PDT 24
Finished Jul 25 07:03:00 PM PDT 24
Peak memory 207468 kb
Host smart-c06f6b5b-c15c-4002-89d1-50d74b8fff50
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=948521304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.948521304
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.545281381
Short name T1323
Test name
Test status
Simulation time 99112602884 ps
CPU time 161.66 seconds
Started Jul 25 07:00:23 PM PDT 24
Finished Jul 25 07:03:05 PM PDT 24
Peak memory 207372 kb
Host smart-bccd1d4f-3045-4345-a0a3-bba32c810e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545281381 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.545281381
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.3225801454
Short name T2093
Test name
Test status
Simulation time 110112472735 ps
CPU time 174.81 seconds
Started Jul 25 07:00:23 PM PDT 24
Finished Jul 25 07:03:18 PM PDT 24
Peak memory 207384 kb
Host smart-3aa5b4af-970f-42b0-b735-f6dd368f2dfe
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3225801454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.3225801454
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.3938555458
Short name T2309
Test name
Test status
Simulation time 116249452017 ps
CPU time 176.23 seconds
Started Jul 25 07:00:25 PM PDT 24
Finished Jul 25 07:03:21 PM PDT 24
Peak memory 207312 kb
Host smart-adc6eb8e-dcd9-4da6-a196-0f3fb8964cfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39385
55458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.3938555458
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.93843452
Short name T865
Test name
Test status
Simulation time 178424352 ps
CPU time 0.93 seconds
Started Jul 25 07:00:21 PM PDT 24
Finished Jul 25 07:00:22 PM PDT 24
Peak memory 207140 kb
Host smart-19ea93e8-6e75-4140-bae0-f97e4e93947d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=93843452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.93843452
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.577958216
Short name T1043
Test name
Test status
Simulation time 161828454 ps
CPU time 0.87 seconds
Started Jul 25 07:00:22 PM PDT 24
Finished Jul 25 07:00:23 PM PDT 24
Peak memory 207040 kb
Host smart-fc5ca3ef-babb-4f9c-a5e0-e04379c4b66e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57795
8216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.577958216
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.2416130417
Short name T2740
Test name
Test status
Simulation time 175555674 ps
CPU time 0.95 seconds
Started Jul 25 07:00:24 PM PDT 24
Finished Jul 25 07:00:25 PM PDT 24
Peak memory 207104 kb
Host smart-64d7aeab-413e-4c9d-9b8e-e2ff4d313065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24161
30417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.2416130417
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.3497879312
Short name T1350
Test name
Test status
Simulation time 7148717973 ps
CPU time 54.25 seconds
Started Jul 25 07:00:26 PM PDT 24
Finished Jul 25 07:01:20 PM PDT 24
Peak memory 215572 kb
Host smart-04c962ee-b8de-40a7-9f1b-bd67a136c127
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3497879312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.3497879312
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_iso_retraction.832516417
Short name T1013
Test name
Test status
Simulation time 12749173946 ps
CPU time 84.13 seconds
Started Jul 25 07:00:24 PM PDT 24
Finished Jul 25 07:01:49 PM PDT 24
Peak memory 207348 kb
Host smart-501e1454-5802-4ea1-8420-25585a508e0c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=832516417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.832516417
Directory /workspace/0.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.3079208249
Short name T1922
Test name
Test status
Simulation time 239905527 ps
CPU time 1.03 seconds
Started Jul 25 07:00:23 PM PDT 24
Finished Jul 25 07:00:25 PM PDT 24
Peak memory 207152 kb
Host smart-c20c922e-bc9c-4b93-9ae2-2657c9fceb46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30792
08249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.3079208249
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.2990708295
Short name T78
Test name
Test status
Simulation time 522973986 ps
CPU time 1.61 seconds
Started Jul 25 07:00:23 PM PDT 24
Finished Jul 25 07:00:25 PM PDT 24
Peak memory 207128 kb
Host smart-04d68479-6221-4d8a-b7f7-660ede41afbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29907
08295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.2990708295
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.4135713286
Short name T2763
Test name
Test status
Simulation time 23335652728 ps
CPU time 30.87 seconds
Started Jul 25 07:00:23 PM PDT 24
Finished Jul 25 07:00:54 PM PDT 24
Peak memory 207304 kb
Host smart-ae0e15b6-dd4b-40a1-9b41-585f1276baf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41357
13286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.4135713286
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.2601767339
Short name T2143
Test name
Test status
Simulation time 3312020930 ps
CPU time 6.03 seconds
Started Jul 25 07:00:22 PM PDT 24
Finished Jul 25 07:00:28 PM PDT 24
Peak memory 207440 kb
Host smart-64e7c67f-79a8-44db-9008-a26176a11821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26017
67339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.2601767339
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.23876248
Short name T5
Test name
Test status
Simulation time 6401804235 ps
CPU time 195.96 seconds
Started Jul 25 07:00:23 PM PDT 24
Finished Jul 25 07:03:39 PM PDT 24
Peak memory 215456 kb
Host smart-eea50739-b5c4-4ec3-b88c-786b4803901a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23876
248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.23876248
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.2573678262
Short name T1393
Test name
Test status
Simulation time 6211259057 ps
CPU time 191.34 seconds
Started Jul 25 07:00:22 PM PDT 24
Finished Jul 25 07:03:34 PM PDT 24
Peak memory 215592 kb
Host smart-c4309125-0b00-4c14-9eb0-9ab19281d47d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2573678262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.2573678262
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.195455987
Short name T579
Test name
Test status
Simulation time 279161205 ps
CPU time 1.16 seconds
Started Jul 25 07:00:19 PM PDT 24
Finished Jul 25 07:00:20 PM PDT 24
Peak memory 207124 kb
Host smart-0f82fa41-cfe5-4bff-87d5-967f7f097995
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=195455987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.195455987
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.1142620651
Short name T457
Test name
Test status
Simulation time 228356492 ps
CPU time 0.94 seconds
Started Jul 25 07:00:23 PM PDT 24
Finished Jul 25 07:00:25 PM PDT 24
Peak memory 207144 kb
Host smart-82f0db1d-f140-4d88-b8a6-3cdec210dc8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11426
20651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.1142620651
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.418384281
Short name T488
Test name
Test status
Simulation time 5508539525 ps
CPU time 154.09 seconds
Started Jul 25 07:00:23 PM PDT 24
Finished Jul 25 07:02:57 PM PDT 24
Peak memory 215600 kb
Host smart-815c2481-f608-4f40-a7ef-cbc3eddf236f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41838
4281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.418384281
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.986616060
Short name T990
Test name
Test status
Simulation time 3168427819 ps
CPU time 87.85 seconds
Started Jul 25 07:00:26 PM PDT 24
Finished Jul 25 07:01:54 PM PDT 24
Peak memory 215612 kb
Host smart-32c37bff-9291-4893-8acd-b1fff846df5f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=986616060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.986616060
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.4185902043
Short name T2198
Test name
Test status
Simulation time 155460102 ps
CPU time 0.91 seconds
Started Jul 25 07:00:27 PM PDT 24
Finished Jul 25 07:00:28 PM PDT 24
Peak memory 207108 kb
Host smart-8ba1cb34-e1d6-455b-9f9d-09a82cd7a6a2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4185902043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.4185902043
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.2565143487
Short name T2852
Test name
Test status
Simulation time 170123404 ps
CPU time 0.92 seconds
Started Jul 25 07:00:26 PM PDT 24
Finished Jul 25 07:00:27 PM PDT 24
Peak memory 207228 kb
Host smart-c1774038-35b0-42e3-a5fb-0a3195137b82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25651
43487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.2565143487
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.3540616496
Short name T80
Test name
Test status
Simulation time 407622263 ps
CPU time 1.32 seconds
Started Jul 25 07:00:26 PM PDT 24
Finished Jul 25 07:00:27 PM PDT 24
Peak memory 207152 kb
Host smart-34a0922b-f8ec-4d4c-ae29-9b0f1187d071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35406
16496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.3540616496
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.1697693314
Short name T1422
Test name
Test status
Simulation time 162664320 ps
CPU time 0.87 seconds
Started Jul 25 07:00:21 PM PDT 24
Finished Jul 25 07:00:22 PM PDT 24
Peak memory 207140 kb
Host smart-20bb1775-b340-4d30-bf6a-1c89f4f43101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16976
93314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.1697693314
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.2520751722
Short name T365
Test name
Test status
Simulation time 157165586 ps
CPU time 0.85 seconds
Started Jul 25 07:00:23 PM PDT 24
Finished Jul 25 07:00:24 PM PDT 24
Peak memory 207108 kb
Host smart-8376b724-3c0c-49c3-a8e1-0c1d6854858d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25207
51722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.2520751722
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.453513899
Short name T787
Test name
Test status
Simulation time 204390790 ps
CPU time 0.96 seconds
Started Jul 25 07:00:25 PM PDT 24
Finished Jul 25 07:00:27 PM PDT 24
Peak memory 207152 kb
Host smart-1c05e587-315e-445d-835b-5b05024244f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45351
3899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.453513899
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.1553685690
Short name T184
Test name
Test status
Simulation time 205501486 ps
CPU time 0.9 seconds
Started Jul 25 07:00:23 PM PDT 24
Finished Jul 25 07:00:24 PM PDT 24
Peak memory 207136 kb
Host smart-c247417e-76b4-4946-9e87-27a7b8c615d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15536
85690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.1553685690
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.4205111224
Short name T2332
Test name
Test status
Simulation time 183611383 ps
CPU time 0.91 seconds
Started Jul 25 07:00:23 PM PDT 24
Finished Jul 25 07:00:24 PM PDT 24
Peak memory 207124 kb
Host smart-7f899961-709c-412e-9e5a-c69fbbca3186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42051
11224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.4205111224
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.3164221041
Short name T2096
Test name
Test status
Simulation time 230110566 ps
CPU time 1.01 seconds
Started Jul 25 07:00:22 PM PDT 24
Finished Jul 25 07:00:23 PM PDT 24
Peak memory 207096 kb
Host smart-f52ef1e6-d4c9-4849-a61b-2807c3ca00e2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3164221041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.3164221041
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.1140881767
Short name T219
Test name
Test status
Simulation time 189631801 ps
CPU time 0.96 seconds
Started Jul 25 07:00:23 PM PDT 24
Finished Jul 25 07:00:24 PM PDT 24
Peak memory 207128 kb
Host smart-3ac2a087-5825-4f27-9cb7-0f861c77f16f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11408
81767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.1140881767
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.1884641998
Short name T2719
Test name
Test status
Simulation time 234356986 ps
CPU time 1.02 seconds
Started Jul 25 07:00:24 PM PDT 24
Finished Jul 25 07:00:25 PM PDT 24
Peak memory 207152 kb
Host smart-3c98a478-1b6f-4f7e-bff1-e80a805dd469
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1884641998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.1884641998
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.184952829
Short name T218
Test name
Test status
Simulation time 249503320 ps
CPU time 1.12 seconds
Started Jul 25 07:00:20 PM PDT 24
Finished Jul 25 07:00:22 PM PDT 24
Peak memory 207144 kb
Host smart-4fe8603b-70e8-4bcd-b2d6-213ff6e071e3
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=184952829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.184952829
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.3501394256
Short name T2361
Test name
Test status
Simulation time 197798996 ps
CPU time 0.89 seconds
Started Jul 25 07:00:22 PM PDT 24
Finished Jul 25 07:00:23 PM PDT 24
Peak memory 207108 kb
Host smart-b3366cf0-a1cb-4ba8-ab64-bf2b0f7bbc4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35013
94256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.3501394256
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.1621638437
Short name T691
Test name
Test status
Simulation time 11378562407 ps
CPU time 26.63 seconds
Started Jul 25 07:00:25 PM PDT 24
Finished Jul 25 07:00:52 PM PDT 24
Peak memory 215516 kb
Host smart-4ba8b0b7-c7e6-4ea3-9752-fc930658915c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16216
38437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.1621638437
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.1644748646
Short name T769
Test name
Test status
Simulation time 163024848 ps
CPU time 0.9 seconds
Started Jul 25 07:00:25 PM PDT 24
Finished Jul 25 07:00:26 PM PDT 24
Peak memory 207112 kb
Host smart-8860cac5-d647-4f0f-aeca-7c1fe8b6dcbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16447
48646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.1644748646
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.3322839083
Short name T1162
Test name
Test status
Simulation time 240177088 ps
CPU time 0.94 seconds
Started Jul 25 07:00:24 PM PDT 24
Finished Jul 25 07:00:25 PM PDT 24
Peak memory 207092 kb
Host smart-cccd92e3-dccc-473f-8094-96645139a301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33228
39083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.3322839083
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.2454843452
Short name T2830
Test name
Test status
Simulation time 4743159746 ps
CPU time 123.5 seconds
Started Jul 25 07:00:22 PM PDT 24
Finished Jul 25 07:02:26 PM PDT 24
Peak memory 215648 kb
Host smart-8e98f83c-8013-48b9-8bd0-c421cfb52341
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454843452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.2454843452
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.3265961455
Short name T490
Test name
Test status
Simulation time 15163354241 ps
CPU time 332.33 seconds
Started Jul 25 07:00:25 PM PDT 24
Finished Jul 25 07:05:58 PM PDT 24
Peak memory 215628 kb
Host smart-976bc9fa-8d06-4114-a1f5-3645b8231a08
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265961455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.3265961455
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.744793837
Short name T639
Test name
Test status
Simulation time 254737350 ps
CPU time 0.93 seconds
Started Jul 25 07:00:26 PM PDT 24
Finished Jul 25 07:00:27 PM PDT 24
Peak memory 207140 kb
Host smart-afa1e696-1e59-4e24-8294-734dbbef55a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74479
3837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.744793837
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.913616289
Short name T912
Test name
Test status
Simulation time 155166335 ps
CPU time 0.87 seconds
Started Jul 25 07:00:23 PM PDT 24
Finished Jul 25 07:00:25 PM PDT 24
Peak memory 207116 kb
Host smart-09df762a-9ce6-42dd-88f6-30cebe2f0579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91361
6289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.913616289
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.2233878587
Short name T2219
Test name
Test status
Simulation time 160943543 ps
CPU time 0.8 seconds
Started Jul 25 07:00:24 PM PDT 24
Finished Jul 25 07:00:25 PM PDT 24
Peak memory 207088 kb
Host smart-8e2284ed-6d76-47b5-a240-eb0b7ea9477c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22338
78587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.2233878587
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.2703426574
Short name T66
Test name
Test status
Simulation time 381521380 ps
CPU time 1.42 seconds
Started Jul 25 07:00:23 PM PDT 24
Finished Jul 25 07:00:24 PM PDT 24
Peak memory 207144 kb
Host smart-708e2cc6-a43b-4859-9207-e98f22335f0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27034
26574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.2703426574
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.3667740138
Short name T1268
Test name
Test status
Simulation time 243410633 ps
CPU time 0.98 seconds
Started Jul 25 07:00:21 PM PDT 24
Finished Jul 25 07:00:22 PM PDT 24
Peak memory 207076 kb
Host smart-7c6d69e0-6edb-461d-aa2a-fd6b81c61fa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36677
40138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.3667740138
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.2653071353
Short name T2556
Test name
Test status
Simulation time 181330932 ps
CPU time 0.91 seconds
Started Jul 25 07:00:26 PM PDT 24
Finished Jul 25 07:00:27 PM PDT 24
Peak memory 207196 kb
Host smart-2b71751f-fe22-4ea9-a1f0-b1a89e09415d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26530
71353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.2653071353
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1137429259
Short name T1974
Test name
Test status
Simulation time 194494875 ps
CPU time 0.97 seconds
Started Jul 25 07:00:23 PM PDT 24
Finished Jul 25 07:00:24 PM PDT 24
Peak memory 207124 kb
Host smart-8a20165c-eebf-489c-9e6e-1fddf71998fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11374
29259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1137429259
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.3794733177
Short name T994
Test name
Test status
Simulation time 3670108941 ps
CPU time 103.55 seconds
Started Jul 25 07:00:23 PM PDT 24
Finished Jul 25 07:02:07 PM PDT 24
Peak memory 215476 kb
Host smart-348a37d0-3f35-40e0-929f-e0eae4d03940
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3794733177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.3794733177
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.615549306
Short name T1757
Test name
Test status
Simulation time 221826725 ps
CPU time 0.92 seconds
Started Jul 25 07:00:25 PM PDT 24
Finished Jul 25 07:00:26 PM PDT 24
Peak memory 207096 kb
Host smart-7729faac-f21a-4529-b1bb-b8378168bbad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61554
9306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.615549306
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.651195806
Short name T928
Test name
Test status
Simulation time 139527250 ps
CPU time 0.8 seconds
Started Jul 25 07:00:23 PM PDT 24
Finished Jul 25 07:00:24 PM PDT 24
Peak memory 207156 kb
Host smart-37ba2384-695a-41cf-b2b5-0cd420f204d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65119
5806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.651195806
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.546251633
Short name T1607
Test name
Test status
Simulation time 746135866 ps
CPU time 2.07 seconds
Started Jul 25 07:00:26 PM PDT 24
Finished Jul 25 07:00:28 PM PDT 24
Peak memory 207020 kb
Host smart-8236ea30-7aa4-46e9-a705-1986f1368d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54625
1633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.546251633
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.750938776
Short name T1421
Test name
Test status
Simulation time 6740143878 ps
CPU time 64.48 seconds
Started Jul 25 07:00:21 PM PDT 24
Finished Jul 25 07:01:26 PM PDT 24
Peak memory 207432 kb
Host smart-1c3bae54-81f8-4e5a-9091-2a03be64b363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75093
8776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.750938776
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_timeout_missing_host_handshake.239496828
Short name T423
Test name
Test status
Simulation time 151860003 ps
CPU time 0.87 seconds
Started Jul 25 07:00:16 PM PDT 24
Finished Jul 25 07:00:17 PM PDT 24
Peak memory 207104 kb
Host smart-a183a2a1-f444-45de-af47-774801411d14
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239496828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_timeout_missing_host_
handshake.239496828
Directory /workspace/0.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.2824516765
Short name T2708
Test name
Test status
Simulation time 3849533113 ps
CPU time 5.99 seconds
Started Jul 25 07:00:36 PM PDT 24
Finished Jul 25 07:00:43 PM PDT 24
Peak memory 207360 kb
Host smart-50e8e45b-d316-4fd5-8dae-ab5082381b1b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824516765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ao
n_wake_disconnect.2824516765
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.291441904
Short name T2840
Test name
Test status
Simulation time 13311155133 ps
CPU time 15.59 seconds
Started Jul 25 07:00:36 PM PDT 24
Finished Jul 25 07:00:51 PM PDT 24
Peak memory 207392 kb
Host smart-c4d07d5c-ae05-4405-a6fe-1c8b6ea4b53b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=291441904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.291441904
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.3357007324
Short name T1654
Test name
Test status
Simulation time 23442518272 ps
CPU time 35.82 seconds
Started Jul 25 07:00:31 PM PDT 24
Finished Jul 25 07:01:07 PM PDT 24
Peak memory 207440 kb
Host smart-10a00443-6d28-4b50-ae4e-32822494a039
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357007324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ao
n_wake_resume.3357007324
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.2667958186
Short name T2518
Test name
Test status
Simulation time 191236621 ps
CPU time 0.91 seconds
Started Jul 25 07:00:32 PM PDT 24
Finished Jul 25 07:00:33 PM PDT 24
Peak memory 207144 kb
Host smart-5e0ce902-a641-4928-b5bf-a4bf8c511f3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26679
58186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.2667958186
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.2190256733
Short name T61
Test name
Test status
Simulation time 178990259 ps
CPU time 0.92 seconds
Started Jul 25 07:00:34 PM PDT 24
Finished Jul 25 07:00:35 PM PDT 24
Peak memory 207116 kb
Host smart-921c70c9-1e94-47f4-aa15-284be944e5d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21902
56733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.2190256733
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.3735439790
Short name T113
Test name
Test status
Simulation time 192012738 ps
CPU time 0.97 seconds
Started Jul 25 07:01:09 PM PDT 24
Finished Jul 25 07:01:10 PM PDT 24
Peak memory 207096 kb
Host smart-ec8d5bae-66c5-4b38-829c-6baee7a62af9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37354
39790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.3735439790
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.2031229488
Short name T1880
Test name
Test status
Simulation time 158717776 ps
CPU time 0.8 seconds
Started Jul 25 07:00:30 PM PDT 24
Finished Jul 25 07:00:31 PM PDT 24
Peak memory 207064 kb
Host smart-2900f365-1e19-43bb-b32d-0d3e7c30f5b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20312
29488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.2031229488
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.3513257810
Short name T1899
Test name
Test status
Simulation time 514928938 ps
CPU time 1.89 seconds
Started Jul 25 07:00:32 PM PDT 24
Finished Jul 25 07:00:34 PM PDT 24
Peak memory 207128 kb
Host smart-a4d9af8b-a0d3-4537-8f7c-d33c1b090ebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35132
57810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.3513257810
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.1990277429
Short name T2403
Test name
Test status
Simulation time 874406275 ps
CPU time 2.53 seconds
Started Jul 25 07:00:32 PM PDT 24
Finished Jul 25 07:00:34 PM PDT 24
Peak memory 207348 kb
Host smart-e9f432e3-5646-4119-b08e-266c3028eb8e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1990277429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.1990277429
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_timeout.3582697100
Short name T1539
Test name
Test status
Simulation time 4323949216 ps
CPU time 37.89 seconds
Started Jul 25 07:00:42 PM PDT 24
Finished Jul 25 07:01:21 PM PDT 24
Peak memory 207468 kb
Host smart-400187ab-2069-4bd5-97e9-384fb267a649
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582697100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_timeout.3582697100
Directory /workspace/1.usbdev_device_timeout/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.2382821634
Short name T1764
Test name
Test status
Simulation time 365982103 ps
CPU time 1.45 seconds
Started Jul 25 07:00:30 PM PDT 24
Finished Jul 25 07:00:32 PM PDT 24
Peak memory 207056 kb
Host smart-931bc8a2-8731-49bd-9420-e8d26de67101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23828
21634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.2382821634
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.2050043871
Short name T1413
Test name
Test status
Simulation time 145322601 ps
CPU time 0.91 seconds
Started Jul 25 07:00:29 PM PDT 24
Finished Jul 25 07:00:30 PM PDT 24
Peak memory 207088 kb
Host smart-ed6bfaad-a6f1-488d-ae57-e7432c54bf15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20500
43871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.2050043871
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.1605954613
Short name T1176
Test name
Test status
Simulation time 70009347 ps
CPU time 0.71 seconds
Started Jul 25 07:00:29 PM PDT 24
Finished Jul 25 07:00:30 PM PDT 24
Peak memory 207088 kb
Host smart-827b7a29-5ece-421d-b405-4c2ffc44f638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16059
54613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.1605954613
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.1028893065
Short name T1847
Test name
Test status
Simulation time 918363788 ps
CPU time 2.42 seconds
Started Jul 25 07:00:33 PM PDT 24
Finished Jul 25 07:00:36 PM PDT 24
Peak memory 207404 kb
Host smart-1e5f2e02-966b-4ca7-9bd7-66a3e9c8ae2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10288
93065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.1028893065
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.1537184762
Short name T1267
Test name
Test status
Simulation time 410916619 ps
CPU time 3.29 seconds
Started Jul 25 07:00:33 PM PDT 24
Finished Jul 25 07:00:36 PM PDT 24
Peak memory 207268 kb
Host smart-539eac8a-5f84-4aff-a9f2-dc131296c771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15371
84762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.1537184762
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.2750568382
Short name T1214
Test name
Test status
Simulation time 109360015708 ps
CPU time 203.47 seconds
Started Jul 25 07:00:32 PM PDT 24
Finished Jul 25 07:03:55 PM PDT 24
Peak memory 207384 kb
Host smart-0aa0f5e3-2cf5-4b82-ad93-7ef5ebaf69f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750568382 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.2750568382
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.3284359226
Short name T1814
Test name
Test status
Simulation time 114106512018 ps
CPU time 204.98 seconds
Started Jul 25 07:00:32 PM PDT 24
Finished Jul 25 07:03:57 PM PDT 24
Peak memory 207336 kb
Host smart-49d2d4a2-fad2-4924-9cd1-3d60cb5aaf84
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3284359226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.3284359226
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.1073422243
Short name T747
Test name
Test status
Simulation time 118208385056 ps
CPU time 209.83 seconds
Started Jul 25 07:00:33 PM PDT 24
Finished Jul 25 07:04:04 PM PDT 24
Peak memory 207328 kb
Host smart-87015103-6b82-45c4-9673-8180ed8d75e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073422243 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.1073422243
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.2233181193
Short name T983
Test name
Test status
Simulation time 119136035044 ps
CPU time 213.79 seconds
Started Jul 25 07:00:34 PM PDT 24
Finished Jul 25 07:04:08 PM PDT 24
Peak memory 207380 kb
Host smart-410f475a-db1c-4d92-9c57-d72807027d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22331
81193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.2233181193
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.2531244165
Short name T1499
Test name
Test status
Simulation time 160692579 ps
CPU time 0.91 seconds
Started Jul 25 07:00:30 PM PDT 24
Finished Jul 25 07:00:31 PM PDT 24
Peak memory 207160 kb
Host smart-501233b2-8758-4b8f-80ae-520a2e5d697d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2531244165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.2531244165
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.1531359415
Short name T1338
Test name
Test status
Simulation time 164043283 ps
CPU time 0.89 seconds
Started Jul 25 07:00:33 PM PDT 24
Finished Jul 25 07:00:34 PM PDT 24
Peak memory 207132 kb
Host smart-ac60d04c-88b0-41da-a290-79f5391bbefa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15313
59415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.1531359415
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.3268897085
Short name T748
Test name
Test status
Simulation time 230674721 ps
CPU time 0.99 seconds
Started Jul 25 07:00:29 PM PDT 24
Finished Jul 25 07:00:31 PM PDT 24
Peak memory 207144 kb
Host smart-5180085f-b115-4943-8df2-111041cd500e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32688
97085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.3268897085
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.2426365767
Short name T1227
Test name
Test status
Simulation time 9037176311 ps
CPU time 68 seconds
Started Jul 25 07:00:31 PM PDT 24
Finished Jul 25 07:01:39 PM PDT 24
Peak memory 215640 kb
Host smart-ff83570e-5c17-46a9-be9a-7adba2691573
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2426365767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.2426365767
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_iso_retraction.3863137473
Short name T1918
Test name
Test status
Simulation time 5574910130 ps
CPU time 39.43 seconds
Started Jul 25 07:00:36 PM PDT 24
Finished Jul 25 07:01:15 PM PDT 24
Peak memory 207344 kb
Host smart-44d6c171-9c25-4822-8a6e-3fe87c0bd95c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3863137473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.3863137473
Directory /workspace/1.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.663960606
Short name T1772
Test name
Test status
Simulation time 172827067 ps
CPU time 0.94 seconds
Started Jul 25 07:00:32 PM PDT 24
Finished Jul 25 07:00:33 PM PDT 24
Peak memory 207176 kb
Host smart-523907ee-ff25-4a10-88e8-d92de7bd37fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66396
0606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.663960606
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.3516119144
Short name T842
Test name
Test status
Simulation time 23340543953 ps
CPU time 28.88 seconds
Started Jul 25 07:00:31 PM PDT 24
Finished Jul 25 07:01:00 PM PDT 24
Peak memory 207440 kb
Host smart-9de186d9-5ac5-4526-ba8e-8706284da51d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35161
19144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.3516119144
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.4090539720
Short name T2331
Test name
Test status
Simulation time 3329369232 ps
CPU time 5.06 seconds
Started Jul 25 07:00:30 PM PDT 24
Finished Jul 25 07:00:35 PM PDT 24
Peak memory 207356 kb
Host smart-50f31107-cd0c-4ec8-97a4-3345928ac978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40905
39720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.4090539720
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.2667177266
Short name T2126
Test name
Test status
Simulation time 8334156145 ps
CPU time 87.98 seconds
Started Jul 25 07:00:34 PM PDT 24
Finished Jul 25 07:02:02 PM PDT 24
Peak memory 217400 kb
Host smart-0603479e-0ad7-4054-85d3-9bb06503bc9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26671
77266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.2667177266
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.3360047733
Short name T757
Test name
Test status
Simulation time 3070195671 ps
CPU time 29.45 seconds
Started Jul 25 07:00:31 PM PDT 24
Finished Jul 25 07:01:01 PM PDT 24
Peak memory 217108 kb
Host smart-9b173ec3-2f95-47e2-a71c-f46d475f0810
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3360047733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.3360047733
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.1448513931
Short name T2742
Test name
Test status
Simulation time 243152516 ps
CPU time 1.04 seconds
Started Jul 25 07:00:33 PM PDT 24
Finished Jul 25 07:00:34 PM PDT 24
Peak memory 207152 kb
Host smart-8cd1d922-8821-4530-9c43-2d65c8273711
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1448513931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.1448513931
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.2787677567
Short name T2034
Test name
Test status
Simulation time 249505196 ps
CPU time 1.01 seconds
Started Jul 25 07:00:29 PM PDT 24
Finished Jul 25 07:00:30 PM PDT 24
Peak memory 207128 kb
Host smart-a4a1cda7-e870-4724-b5d1-8b259fae8b25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27876
77567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.2787677567
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.287705431
Short name T930
Test name
Test status
Simulation time 4659327307 ps
CPU time 135.21 seconds
Started Jul 25 07:00:29 PM PDT 24
Finished Jul 25 07:02:44 PM PDT 24
Peak memory 215620 kb
Host smart-989c9b69-9e7e-4e03-bec5-ebd03d5b0370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28770
5431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.287705431
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.3394627310
Short name T2759
Test name
Test status
Simulation time 6109934751 ps
CPU time 179.56 seconds
Started Jul 25 07:00:33 PM PDT 24
Finished Jul 25 07:03:33 PM PDT 24
Peak memory 215616 kb
Host smart-878951ab-9e7f-4686-b196-bdf1aa212630
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3394627310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.3394627310
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.3435322513
Short name T2362
Test name
Test status
Simulation time 163820557 ps
CPU time 0.87 seconds
Started Jul 25 07:00:30 PM PDT 24
Finished Jul 25 07:00:31 PM PDT 24
Peak memory 207124 kb
Host smart-98eb113d-c7d8-49ba-a647-3d731dd375eb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3435322513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.3435322513
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.4008083955
Short name T2536
Test name
Test status
Simulation time 181008187 ps
CPU time 0.87 seconds
Started Jul 25 07:00:31 PM PDT 24
Finished Jul 25 07:00:32 PM PDT 24
Peak memory 207232 kb
Host smart-6950db0f-babd-4c43-8ae1-ef8fc99eb241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40080
83955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.4008083955
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.3063196738
Short name T2673
Test name
Test status
Simulation time 183046634 ps
CPU time 0.92 seconds
Started Jul 25 07:00:33 PM PDT 24
Finished Jul 25 07:00:34 PM PDT 24
Peak memory 207116 kb
Host smart-de998bd2-bdc4-4d49-b979-b5567aba29d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30631
96738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.3063196738
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.91118708
Short name T875
Test name
Test status
Simulation time 172903296 ps
CPU time 0.9 seconds
Started Jul 25 07:00:33 PM PDT 24
Finished Jul 25 07:00:34 PM PDT 24
Peak memory 207124 kb
Host smart-8e8acc1e-cb51-4305-9ba8-41cb30b5017a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91118
708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.91118708
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.236652700
Short name T1103
Test name
Test status
Simulation time 167362556 ps
CPU time 0.9 seconds
Started Jul 25 07:00:28 PM PDT 24
Finished Jul 25 07:00:29 PM PDT 24
Peak memory 207148 kb
Host smart-77c0e7d9-848c-433c-a0a4-ec921e80173c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23665
2700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.236652700
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.3907346564
Short name T1183
Test name
Test status
Simulation time 245161581 ps
CPU time 0.98 seconds
Started Jul 25 07:00:37 PM PDT 24
Finished Jul 25 07:00:38 PM PDT 24
Peak memory 207124 kb
Host smart-fe37caad-a241-417a-9e40-cdb6176559c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39073
46564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.3907346564
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.236396536
Short name T1409
Test name
Test status
Simulation time 260179425 ps
CPU time 1.04 seconds
Started Jul 25 07:00:30 PM PDT 24
Finished Jul 25 07:00:31 PM PDT 24
Peak memory 207172 kb
Host smart-07dd87f7-d180-4a4f-9005-ca50a18c0f2b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=236396536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.236396536
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.3592657444
Short name T879
Test name
Test status
Simulation time 248739235 ps
CPU time 1.05 seconds
Started Jul 25 07:00:33 PM PDT 24
Finished Jul 25 07:00:34 PM PDT 24
Peak memory 207160 kb
Host smart-d97a66af-8247-403e-a2af-36a4f0eecf40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35926
57444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.3592657444
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.2442654811
Short name T853
Test name
Test status
Simulation time 33953781 ps
CPU time 0.67 seconds
Started Jul 25 07:00:40 PM PDT 24
Finished Jul 25 07:00:41 PM PDT 24
Peak memory 207128 kb
Host smart-977ede01-9086-403a-9ad4-23557e4f6b9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24426
54811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.2442654811
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.2906984020
Short name T1825
Test name
Test status
Simulation time 10607110511 ps
CPU time 25.65 seconds
Started Jul 25 07:00:39 PM PDT 24
Finished Jul 25 07:01:05 PM PDT 24
Peak memory 223792 kb
Host smart-89007c4d-871f-4b64-acd7-b7a2afd83848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29069
84020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.2906984020
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.2232775737
Short name T1939
Test name
Test status
Simulation time 160020275 ps
CPU time 0.92 seconds
Started Jul 25 07:00:41 PM PDT 24
Finished Jul 25 07:00:42 PM PDT 24
Peak memory 207076 kb
Host smart-c94262ea-ab21-45d8-86de-ff5983c5a4fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22327
75737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.2232775737
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.2152117489
Short name T1665
Test name
Test status
Simulation time 239393245 ps
CPU time 1.05 seconds
Started Jul 25 07:00:41 PM PDT 24
Finished Jul 25 07:00:42 PM PDT 24
Peak memory 207100 kb
Host smart-f33909e0-b9d2-449d-9d53-eb15f1cafc03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21521
17489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.2152117489
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.1058045384
Short name T194
Test name
Test status
Simulation time 8907603582 ps
CPU time 43.58 seconds
Started Jul 25 07:00:41 PM PDT 24
Finished Jul 25 07:01:24 PM PDT 24
Peak memory 218700 kb
Host smart-e1dc4041-ccc3-4448-b816-8a4e5b5d22b6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058045384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.1058045384
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.3422205876
Short name T2168
Test name
Test status
Simulation time 19937407300 ps
CPU time 156.4 seconds
Started Jul 25 07:00:41 PM PDT 24
Finished Jul 25 07:03:18 PM PDT 24
Peak memory 217992 kb
Host smart-7d713925-7c99-4145-badf-d681294e8b20
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422205876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.3422205876
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.1684402250
Short name T492
Test name
Test status
Simulation time 206172754 ps
CPU time 0.92 seconds
Started Jul 25 07:00:40 PM PDT 24
Finished Jul 25 07:00:41 PM PDT 24
Peak memory 207108 kb
Host smart-14c2a104-3c3e-4f97-a8f2-4a81c1acbfdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16844
02250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.1684402250
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.4105109048
Short name T1724
Test name
Test status
Simulation time 144576226 ps
CPU time 0.81 seconds
Started Jul 25 07:00:40 PM PDT 24
Finished Jul 25 07:00:41 PM PDT 24
Peak memory 207128 kb
Host smart-e3d40ee0-1e00-42b8-a953-72005572dca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41051
09048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.4105109048
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.3144239964
Short name T2753
Test name
Test status
Simulation time 143743618 ps
CPU time 0.81 seconds
Started Jul 25 07:00:40 PM PDT 24
Finished Jul 25 07:00:41 PM PDT 24
Peak memory 207076 kb
Host smart-f5a0a405-155e-4277-8a18-f970d955201b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31442
39964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.3144239964
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.1384211617
Short name T89
Test name
Test status
Simulation time 182757568 ps
CPU time 0.9 seconds
Started Jul 25 07:00:40 PM PDT 24
Finished Jul 25 07:00:41 PM PDT 24
Peak memory 207164 kb
Host smart-c510003c-9df8-4988-831f-4e04f2914bdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13842
11617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.1384211617
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.2590078819
Short name T209
Test name
Test status
Simulation time 319836107 ps
CPU time 1.14 seconds
Started Jul 25 07:00:42 PM PDT 24
Finished Jul 25 07:00:44 PM PDT 24
Peak memory 222956 kb
Host smart-960440b5-2ad5-451e-9dee-3606256fa67d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2590078819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.2590078819
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.3766621479
Short name T65
Test name
Test status
Simulation time 481458958 ps
CPU time 1.54 seconds
Started Jul 25 07:00:39 PM PDT 24
Finished Jul 25 07:00:41 PM PDT 24
Peak memory 207100 kb
Host smart-40fcb5da-1b10-4bb5-b6fc-d717709b1de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37666
21479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.3766621479
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.1072401236
Short name T192
Test name
Test status
Simulation time 228000013 ps
CPU time 1.03 seconds
Started Jul 25 07:00:43 PM PDT 24
Finished Jul 25 07:00:44 PM PDT 24
Peak memory 207136 kb
Host smart-ab95c23e-a028-40fc-bc65-c5ef61006e63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10724
01236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.1072401236
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.1478022563
Short name T817
Test name
Test status
Simulation time 157587317 ps
CPU time 0.83 seconds
Started Jul 25 07:00:39 PM PDT 24
Finished Jul 25 07:00:40 PM PDT 24
Peak memory 207104 kb
Host smart-b30d2e6c-dcde-42f2-8e5e-c5bd7faaa04c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14780
22563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.1478022563
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.1544144006
Short name T562
Test name
Test status
Simulation time 178050967 ps
CPU time 0.91 seconds
Started Jul 25 07:00:43 PM PDT 24
Finished Jul 25 07:00:44 PM PDT 24
Peak memory 207164 kb
Host smart-20e34c9b-930e-4a07-940e-9ae34f2967fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15441
44006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.1544144006
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.3629965744
Short name T2517
Test name
Test status
Simulation time 188783539 ps
CPU time 0.96 seconds
Started Jul 25 07:00:40 PM PDT 24
Finished Jul 25 07:00:41 PM PDT 24
Peak memory 207112 kb
Host smart-d7ed4c9e-c070-406f-9240-663dbb5f456e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36299
65744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.3629965744
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.2066946943
Short name T1661
Test name
Test status
Simulation time 4520280033 ps
CPU time 131.1 seconds
Started Jul 25 07:00:41 PM PDT 24
Finished Jul 25 07:02:52 PM PDT 24
Peak memory 215628 kb
Host smart-08b2268d-d8da-438d-a86f-bd802f0e639d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2066946943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.2066946943
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.1884151219
Short name T2406
Test name
Test status
Simulation time 160430487 ps
CPU time 0.87 seconds
Started Jul 25 07:00:40 PM PDT 24
Finished Jul 25 07:00:41 PM PDT 24
Peak memory 207124 kb
Host smart-73d7c7fa-e98a-4b98-a023-fa738c50a4a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18841
51219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.1884151219
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.11364586
Short name T2172
Test name
Test status
Simulation time 190079877 ps
CPU time 0.86 seconds
Started Jul 25 07:00:44 PM PDT 24
Finished Jul 25 07:00:45 PM PDT 24
Peak memory 207168 kb
Host smart-93863e62-e48b-41b0-902f-d29edb80f86d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11364
586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.11364586
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.2083229703
Short name T1692
Test name
Test status
Simulation time 1223677385 ps
CPU time 3.11 seconds
Started Jul 25 07:00:41 PM PDT 24
Finished Jul 25 07:00:45 PM PDT 24
Peak memory 207424 kb
Host smart-63806c1a-2203-430d-9c8a-4a7b1f215ae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20832
29703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.2083229703
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.4125384416
Short name T2288
Test name
Test status
Simulation time 6188632454 ps
CPU time 182.05 seconds
Started Jul 25 07:00:38 PM PDT 24
Finished Jul 25 07:03:40 PM PDT 24
Peak memory 215540 kb
Host smart-d9229222-7434-40c3-9ccf-b4d8137c5cee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41253
84416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.4125384416
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.2314267381
Short name T96
Test name
Test status
Simulation time 20066788949 ps
CPU time 169.46 seconds
Started Jul 25 07:00:42 PM PDT 24
Finished Jul 25 07:03:32 PM PDT 24
Peak memory 215600 kb
Host smart-d9297541-4472-48c5-9458-35717a69d4bf
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314267381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.2314267381
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_timeout_missing_host_handshake.4290910339
Short name T368
Test name
Test status
Simulation time 4342931457 ps
CPU time 40.19 seconds
Started Jul 25 07:00:30 PM PDT 24
Finished Jul 25 07:01:10 PM PDT 24
Peak memory 207312 kb
Host smart-dc1c8ab5-9772-4267-aaec-fc3994006486
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290910339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_timeout_missing_host
_handshake.4290910339
Directory /workspace/1.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.4053950249
Short name T2306
Test name
Test status
Simulation time 52381750 ps
CPU time 0.67 seconds
Started Jul 25 07:02:46 PM PDT 24
Finished Jul 25 07:02:47 PM PDT 24
Peak memory 207216 kb
Host smart-4e86553e-6293-495b-89f2-b56413df9dbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4053950249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.4053950249
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.700016834
Short name T16
Test name
Test status
Simulation time 4002171385 ps
CPU time 5.76 seconds
Started Jul 25 07:02:36 PM PDT 24
Finished Jul 25 07:02:42 PM PDT 24
Peak memory 207372 kb
Host smart-22311bbd-9592-4315-8a94-d267d0b2bcd8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700016834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_ao
n_wake_disconnect.700016834
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.1674412236
Short name T2127
Test name
Test status
Simulation time 13339569226 ps
CPU time 17.86 seconds
Started Jul 25 07:02:36 PM PDT 24
Finished Jul 25 07:02:54 PM PDT 24
Peak memory 207428 kb
Host smart-db28529c-26ab-4701-980f-975b494ddbe7
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674412236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.1674412236
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.641484732
Short name T550
Test name
Test status
Simulation time 23413696956 ps
CPU time 28 seconds
Started Jul 25 07:02:35 PM PDT 24
Finished Jul 25 07:03:03 PM PDT 24
Peak memory 207364 kb
Host smart-c07ec07d-4113-47cd-9087-5846744212e3
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641484732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_ao
n_wake_resume.641484732
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.899533508
Short name T2508
Test name
Test status
Simulation time 158380334 ps
CPU time 0.84 seconds
Started Jul 25 07:02:38 PM PDT 24
Finished Jul 25 07:02:39 PM PDT 24
Peak memory 207108 kb
Host smart-2a7bc2f7-0e28-40dd-9d81-ad7d7951788a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89953
3508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.899533508
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.2532288217
Short name T2561
Test name
Test status
Simulation time 179511547 ps
CPU time 0.89 seconds
Started Jul 25 07:02:36 PM PDT 24
Finished Jul 25 07:02:37 PM PDT 24
Peak memory 207092 kb
Host smart-7080a8aa-8fa1-4b21-bd46-68d1d0e3d483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25322
88217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.2532288217
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.4003580730
Short name T935
Test name
Test status
Simulation time 233496876 ps
CPU time 1.1 seconds
Started Jul 25 07:02:35 PM PDT 24
Finished Jul 25 07:02:36 PM PDT 24
Peak memory 207144 kb
Host smart-9c9a677e-0437-4832-8df3-777be01c9f37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40035
80730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.4003580730
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.2501140422
Short name T1347
Test name
Test status
Simulation time 425733203 ps
CPU time 1.31 seconds
Started Jul 25 07:02:38 PM PDT 24
Finished Jul 25 07:02:39 PM PDT 24
Peak memory 207056 kb
Host smart-996eddcc-4287-4307-a117-aeaf64723d30
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2501140422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.2501140422
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.2300303259
Short name T2743
Test name
Test status
Simulation time 19241836393 ps
CPU time 38.58 seconds
Started Jul 25 07:02:35 PM PDT 24
Finished Jul 25 07:03:14 PM PDT 24
Peak memory 207344 kb
Host smart-127575dd-4f42-41ed-8178-652b5ca7a9c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23003
03259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.2300303259
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_device_timeout.4277141220
Short name T1256
Test name
Test status
Simulation time 878074082 ps
CPU time 18.6 seconds
Started Jul 25 07:02:37 PM PDT 24
Finished Jul 25 07:02:56 PM PDT 24
Peak memory 207408 kb
Host smart-df32a3fe-058f-432f-b8b5-57ef38478e73
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277141220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_timeout.4277141220
Directory /workspace/10.usbdev_device_timeout/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.2157919907
Short name T1436
Test name
Test status
Simulation time 498611956 ps
CPU time 1.63 seconds
Started Jul 25 07:02:34 PM PDT 24
Finished Jul 25 07:02:36 PM PDT 24
Peak memory 207052 kb
Host smart-57daf9ab-9440-4d18-a48c-5d903e36f77b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21579
19907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.2157919907
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.668712396
Short name T1112
Test name
Test status
Simulation time 133818367 ps
CPU time 0.81 seconds
Started Jul 25 07:02:35 PM PDT 24
Finished Jul 25 07:02:36 PM PDT 24
Peak memory 207116 kb
Host smart-5c67999b-c471-44da-a1bb-246f7fc12c68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66871
2396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.668712396
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.2180196198
Short name T430
Test name
Test status
Simulation time 83979950 ps
CPU time 0.75 seconds
Started Jul 25 07:02:35 PM PDT 24
Finished Jul 25 07:02:36 PM PDT 24
Peak memory 207200 kb
Host smart-d78a0d61-89e9-4e62-8a61-2a594a71e4b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21801
96198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.2180196198
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.470173724
Short name T1123
Test name
Test status
Simulation time 1008372722 ps
CPU time 2.37 seconds
Started Jul 25 07:02:35 PM PDT 24
Finished Jul 25 07:02:38 PM PDT 24
Peak memory 207320 kb
Host smart-924832c8-6a07-4b23-bb68-82dfcd8e3800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47017
3724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.470173724
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.1464091638
Short name T735
Test name
Test status
Simulation time 205165499 ps
CPU time 2.12 seconds
Started Jul 25 07:02:36 PM PDT 24
Finished Jul 25 07:02:38 PM PDT 24
Peak memory 207224 kb
Host smart-39582727-3cfb-4f43-b382-aa379d522b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14640
91638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.1464091638
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.2642520239
Short name T2860
Test name
Test status
Simulation time 234985974 ps
CPU time 1.22 seconds
Started Jul 25 07:02:35 PM PDT 24
Finished Jul 25 07:02:37 PM PDT 24
Peak memory 215528 kb
Host smart-337eaa3e-9fa4-4f01-a6a4-01c6254bf646
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2642520239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.2642520239
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.1338243309
Short name T1417
Test name
Test status
Simulation time 135654565 ps
CPU time 0.8 seconds
Started Jul 25 07:02:37 PM PDT 24
Finished Jul 25 07:02:37 PM PDT 24
Peak memory 207108 kb
Host smart-887e4949-cbae-42bc-8f61-10519ef6d3bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13382
43309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.1338243309
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.87225284
Short name T1441
Test name
Test status
Simulation time 308810985 ps
CPU time 1.11 seconds
Started Jul 25 07:02:35 PM PDT 24
Finished Jul 25 07:02:36 PM PDT 24
Peak memory 207096 kb
Host smart-fae4c4ed-235f-4f6e-8352-4da81bf25fb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87225
284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.87225284
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_invalid_sync.4045475030
Short name T2046
Test name
Test status
Simulation time 6792317112 ps
CPU time 201.94 seconds
Started Jul 25 07:02:34 PM PDT 24
Finished Jul 25 07:05:56 PM PDT 24
Peak memory 215584 kb
Host smart-4c769bd9-6d41-4044-b41a-45a270a33d98
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4045475030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.4045475030
Directory /workspace/10.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_iso_retraction.371057458
Short name T1308
Test name
Test status
Simulation time 8090935927 ps
CPU time 58.97 seconds
Started Jul 25 07:02:36 PM PDT 24
Finished Jul 25 07:03:35 PM PDT 24
Peak memory 207368 kb
Host smart-03aba4b0-7d50-4e8a-8e43-25672cdfc1f1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=371057458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.371057458
Directory /workspace/10.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.4289040993
Short name T861
Test name
Test status
Simulation time 178877246 ps
CPU time 0.85 seconds
Started Jul 25 07:02:37 PM PDT 24
Finished Jul 25 07:02:38 PM PDT 24
Peak memory 207120 kb
Host smart-4f25a53e-429e-446c-9eb3-b6fba7b618fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42890
40993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.4289040993
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.3912129832
Short name T2734
Test name
Test status
Simulation time 23294140086 ps
CPU time 25.32 seconds
Started Jul 25 07:02:49 PM PDT 24
Finished Jul 25 07:03:15 PM PDT 24
Peak memory 207420 kb
Host smart-a8b17a72-f7d8-4f7d-8ea2-9b2f4be3e811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39121
29832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.3912129832
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.2666734069
Short name T791
Test name
Test status
Simulation time 3307011773 ps
CPU time 5.04 seconds
Started Jul 25 07:02:44 PM PDT 24
Finished Jul 25 07:02:49 PM PDT 24
Peak memory 207372 kb
Host smart-da6a3e3f-eeac-4d99-b5dd-2b9d1fac259d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26667
34069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.2666734069
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.1915161949
Short name T1664
Test name
Test status
Simulation time 8758762104 ps
CPU time 262.96 seconds
Started Jul 25 07:02:45 PM PDT 24
Finished Jul 25 07:07:08 PM PDT 24
Peak memory 215552 kb
Host smart-4d66c816-f399-4e42-b319-3737880a99eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19151
61949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.1915161949
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.1089199000
Short name T2002
Test name
Test status
Simulation time 6850636414 ps
CPU time 75.8 seconds
Started Jul 25 07:02:45 PM PDT 24
Finished Jul 25 07:04:01 PM PDT 24
Peak memory 207352 kb
Host smart-29bb1720-de30-45e3-a4e7-9facbb4f15f5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1089199000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.1089199000
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.1603772475
Short name T927
Test name
Test status
Simulation time 247982027 ps
CPU time 1.03 seconds
Started Jul 25 07:02:45 PM PDT 24
Finished Jul 25 07:02:46 PM PDT 24
Peak memory 207236 kb
Host smart-fb602efa-ba3c-4d77-bb3d-c9f366c0ff07
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1603772475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.1603772475
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.242801356
Short name T783
Test name
Test status
Simulation time 207474071 ps
CPU time 0.95 seconds
Started Jul 25 07:02:46 PM PDT 24
Finished Jul 25 07:02:47 PM PDT 24
Peak memory 207156 kb
Host smart-a52657bc-4aac-4dd1-a8cd-1f58686f082e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24280
1356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.242801356
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.1051570037
Short name T1919
Test name
Test status
Simulation time 4219659994 ps
CPU time 126.45 seconds
Started Jul 25 07:02:44 PM PDT 24
Finished Jul 25 07:04:51 PM PDT 24
Peak memory 215612 kb
Host smart-47618611-9364-413f-9812-4cca9ec0c48e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10515
70037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.1051570037
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.1817864392
Short name T403
Test name
Test status
Simulation time 5860078205 ps
CPU time 43.96 seconds
Started Jul 25 07:02:46 PM PDT 24
Finished Jul 25 07:03:31 PM PDT 24
Peak memory 207276 kb
Host smart-682821c2-84ae-41d7-a547-97906942b1d0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1817864392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.1817864392
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.1403163931
Short name T475
Test name
Test status
Simulation time 220954208 ps
CPU time 0.94 seconds
Started Jul 25 07:02:44 PM PDT 24
Finished Jul 25 07:02:46 PM PDT 24
Peak memory 207144 kb
Host smart-ea49c122-a4fd-4a91-94a6-248259fb27c2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1403163931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.1403163931
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.2996979612
Short name T2792
Test name
Test status
Simulation time 137877529 ps
CPU time 0.83 seconds
Started Jul 25 07:02:46 PM PDT 24
Finished Jul 25 07:02:46 PM PDT 24
Peak memory 207144 kb
Host smart-ff567d2f-fbd3-4c02-bba7-ce8acd2b360d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29969
79612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.2996979612
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.916314341
Short name T2276
Test name
Test status
Simulation time 196549366 ps
CPU time 0.96 seconds
Started Jul 25 07:02:43 PM PDT 24
Finished Jul 25 07:02:44 PM PDT 24
Peak memory 207112 kb
Host smart-00f980cc-586b-4698-a1e7-81e71556f10c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91631
4341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.916314341
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.3048657925
Short name T130
Test name
Test status
Simulation time 170811447 ps
CPU time 0.89 seconds
Started Jul 25 07:02:46 PM PDT 24
Finished Jul 25 07:02:47 PM PDT 24
Peak memory 207148 kb
Host smart-95e99575-9c91-4c63-9055-3a40f94de020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30486
57925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.3048657925
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.3981662112
Short name T630
Test name
Test status
Simulation time 146132614 ps
CPU time 0.83 seconds
Started Jul 25 07:02:44 PM PDT 24
Finished Jul 25 07:02:45 PM PDT 24
Peak memory 207116 kb
Host smart-b2d69155-c968-4015-9610-8adcd2526a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39816
62112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.3981662112
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.2841415137
Short name T1114
Test name
Test status
Simulation time 161685426 ps
CPU time 0.87 seconds
Started Jul 25 07:02:49 PM PDT 24
Finished Jul 25 07:02:50 PM PDT 24
Peak memory 207140 kb
Host smart-7632a1ca-c460-484f-8089-c5247c2ba4e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28414
15137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.2841415137
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.913959804
Short name T2345
Test name
Test status
Simulation time 221469627 ps
CPU time 1.03 seconds
Started Jul 25 07:02:45 PM PDT 24
Finished Jul 25 07:02:46 PM PDT 24
Peak memory 207132 kb
Host smart-fda7bb98-7c2a-4807-b228-42c061c80b6b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=913959804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.913959804
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.3304834660
Short name T2257
Test name
Test status
Simulation time 147543755 ps
CPU time 0.8 seconds
Started Jul 25 07:02:44 PM PDT 24
Finished Jul 25 07:02:45 PM PDT 24
Peak memory 207088 kb
Host smart-ddb4cc6b-8857-4ad1-9be4-9941b64982a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33048
34660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.3304834660
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.1848740218
Short name T500
Test name
Test status
Simulation time 40651272 ps
CPU time 0.7 seconds
Started Jul 25 07:02:47 PM PDT 24
Finished Jul 25 07:02:47 PM PDT 24
Peak memory 207156 kb
Host smart-b7e5aa04-a156-459a-bf35-ec5c861b63b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18487
40218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.1848740218
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.3012958810
Short name T1682
Test name
Test status
Simulation time 12860207558 ps
CPU time 33.48 seconds
Started Jul 25 07:02:46 PM PDT 24
Finished Jul 25 07:03:19 PM PDT 24
Peak memory 223776 kb
Host smart-97747b6d-024f-4d21-b1d9-600d1adda39c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30129
58810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.3012958810
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.4001031208
Short name T2416
Test name
Test status
Simulation time 218628993 ps
CPU time 0.98 seconds
Started Jul 25 07:02:47 PM PDT 24
Finished Jul 25 07:02:48 PM PDT 24
Peak memory 207112 kb
Host smart-91c5cc2d-bb1d-4754-8f9e-be96ea6489cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40010
31208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.4001031208
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.3963942326
Short name T2603
Test name
Test status
Simulation time 228736520 ps
CPU time 0.96 seconds
Started Jul 25 07:02:45 PM PDT 24
Finished Jul 25 07:02:46 PM PDT 24
Peak memory 207120 kb
Host smart-04e0f1df-799c-47c1-a6a4-00260c308c89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39639
42326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.3963942326
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.1113131063
Short name T2739
Test name
Test status
Simulation time 168569342 ps
CPU time 0.94 seconds
Started Jul 25 07:02:47 PM PDT 24
Finished Jul 25 07:02:48 PM PDT 24
Peak memory 207136 kb
Host smart-7764aa0d-667d-4699-9900-6de3ffcc57b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11131
31063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.1113131063
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.3349505673
Short name T763
Test name
Test status
Simulation time 175695895 ps
CPU time 0.94 seconds
Started Jul 25 07:02:53 PM PDT 24
Finished Jul 25 07:02:54 PM PDT 24
Peak memory 207112 kb
Host smart-758f21b7-e12b-4f4f-9606-5282e6721642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33495
05673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.3349505673
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.3498244028
Short name T480
Test name
Test status
Simulation time 189516560 ps
CPU time 0.93 seconds
Started Jul 25 07:02:47 PM PDT 24
Finished Jul 25 07:02:48 PM PDT 24
Peak memory 207124 kb
Host smart-c3a3b245-a430-4a32-938f-9dddbc3b1d4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34982
44028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.3498244028
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.1971900428
Short name T1407
Test name
Test status
Simulation time 162139008 ps
CPU time 0.87 seconds
Started Jul 25 07:02:44 PM PDT 24
Finished Jul 25 07:02:45 PM PDT 24
Peak memory 207092 kb
Host smart-e08a9d9f-5fa7-4577-91ac-a24a34f293e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19719
00428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.1971900428
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.655869643
Short name T1174
Test name
Test status
Simulation time 150310919 ps
CPU time 0.88 seconds
Started Jul 25 07:02:49 PM PDT 24
Finished Jul 25 07:02:50 PM PDT 24
Peak memory 207132 kb
Host smart-63828e3a-8599-4eb1-a879-a825f06508fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65586
9643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.655869643
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.4188793155
Short name T2635
Test name
Test status
Simulation time 215065702 ps
CPU time 0.96 seconds
Started Jul 25 07:02:47 PM PDT 24
Finished Jul 25 07:02:48 PM PDT 24
Peak memory 207124 kb
Host smart-b5113180-64af-4ff7-bfdc-d1fb941d448c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41887
93155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.4188793155
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.2878779873
Short name T1620
Test name
Test status
Simulation time 5285085163 ps
CPU time 39.5 seconds
Started Jul 25 07:02:44 PM PDT 24
Finished Jul 25 07:03:24 PM PDT 24
Peak memory 215588 kb
Host smart-54667b4b-5758-4b94-822b-97a4b50759d5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2878779873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.2878779873
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.3760373271
Short name T76
Test name
Test status
Simulation time 187714962 ps
CPU time 0.88 seconds
Started Jul 25 07:02:46 PM PDT 24
Finished Jul 25 07:02:47 PM PDT 24
Peak memory 207168 kb
Host smart-45a6954c-24c4-4a31-9369-0b8eb1e822b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37603
73271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.3760373271
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.2467281400
Short name T1943
Test name
Test status
Simulation time 666265388 ps
CPU time 1.83 seconds
Started Jul 25 07:02:44 PM PDT 24
Finished Jul 25 07:02:46 PM PDT 24
Peak memory 207040 kb
Host smart-45ead344-c513-487c-a7a2-9568fb6a30b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24672
81400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.2467281400
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.3891508429
Short name T724
Test name
Test status
Simulation time 4092547321 ps
CPU time 41.76 seconds
Started Jul 25 07:02:49 PM PDT 24
Finished Jul 25 07:03:31 PM PDT 24
Peak memory 217088 kb
Host smart-0fac8f51-4b68-446a-957f-5338cba74e57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38915
08429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.3891508429
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_timeout_missing_host_handshake.3820604209
Short name T2462
Test name
Test status
Simulation time 4287255112 ps
CPU time 38.69 seconds
Started Jul 25 07:02:34 PM PDT 24
Finished Jul 25 07:03:13 PM PDT 24
Peak memory 207436 kb
Host smart-f458fb2f-cd74-46f5-8b73-7fdac54c92e2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820604209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_timeout_missing_hos
t_handshake.3820604209
Directory /workspace/10.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.1075051839
Short name T1171
Test name
Test status
Simulation time 44244032 ps
CPU time 0.68 seconds
Started Jul 25 07:02:59 PM PDT 24
Finished Jul 25 07:03:00 PM PDT 24
Peak memory 207140 kb
Host smart-0a100a46-2a0a-48bf-b1e4-cfbc7848e829
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1075051839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.1075051839
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.93308456
Short name T2477
Test name
Test status
Simulation time 3481488196 ps
CPU time 5.32 seconds
Started Jul 25 07:02:47 PM PDT 24
Finished Jul 25 07:02:52 PM PDT 24
Peak memory 207368 kb
Host smart-724f291a-6829-43e8-a77e-7b904c5bef58
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93308456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon
_wake_disconnect.93308456
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.2782939568
Short name T556
Test name
Test status
Simulation time 13442471989 ps
CPU time 17.39 seconds
Started Jul 25 07:02:47 PM PDT 24
Finished Jul 25 07:03:05 PM PDT 24
Peak memory 207440 kb
Host smart-3576cafb-4d14-445e-81fe-c3becc24cb29
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782939568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.2782939568
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.211304971
Short name T1803
Test name
Test status
Simulation time 23428233836 ps
CPU time 29.94 seconds
Started Jul 25 07:02:45 PM PDT 24
Finished Jul 25 07:03:15 PM PDT 24
Peak memory 207388 kb
Host smart-8667e9f5-d4bd-406e-9189-29cb6136230b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211304971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_ao
n_wake_resume.211304971
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.4021137146
Short name T2217
Test name
Test status
Simulation time 147562248 ps
CPU time 0.81 seconds
Started Jul 25 07:02:46 PM PDT 24
Finished Jul 25 07:02:47 PM PDT 24
Peak memory 207168 kb
Host smart-058030e9-77c1-425d-869b-e78b4f693a75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40211
37146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.4021137146
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.1117980366
Short name T1937
Test name
Test status
Simulation time 141878190 ps
CPU time 0.8 seconds
Started Jul 25 07:02:46 PM PDT 24
Finished Jul 25 07:02:47 PM PDT 24
Peak memory 207116 kb
Host smart-efbec1c9-8690-49ad-ac2a-a3cc9b04521a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11179
80366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.1117980366
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.1711381232
Short name T2119
Test name
Test status
Simulation time 647213876 ps
CPU time 2.12 seconds
Started Jul 25 07:02:45 PM PDT 24
Finished Jul 25 07:02:48 PM PDT 24
Peak memory 207144 kb
Host smart-ca8b1a28-982b-4786-bf2e-f898a31a900f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17113
81232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.1711381232
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.1015996823
Short name T2567
Test name
Test status
Simulation time 443785019 ps
CPU time 1.41 seconds
Started Jul 25 07:02:47 PM PDT 24
Finished Jul 25 07:02:49 PM PDT 24
Peak memory 207112 kb
Host smart-eef5dc71-6f0e-42ba-abaf-cab865e28e21
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1015996823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.1015996823
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.2745272773
Short name T1448
Test name
Test status
Simulation time 10133944644 ps
CPU time 22.22 seconds
Started Jul 25 07:02:53 PM PDT 24
Finished Jul 25 07:03:16 PM PDT 24
Peak memory 207412 kb
Host smart-89815ac4-518b-43c0-9ee4-d710da94819c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27452
72773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.2745272773
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_device_timeout.3212849122
Short name T622
Test name
Test status
Simulation time 5604616599 ps
CPU time 38.25 seconds
Started Jul 25 07:02:47 PM PDT 24
Finished Jul 25 07:03:26 PM PDT 24
Peak memory 207424 kb
Host smart-6075215c-4e1e-432c-919a-2925350d1725
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212849122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_timeout.3212849122
Directory /workspace/11.usbdev_device_timeout/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.183884321
Short name T1767
Test name
Test status
Simulation time 386071277 ps
CPU time 1.34 seconds
Started Jul 25 07:02:47 PM PDT 24
Finished Jul 25 07:02:48 PM PDT 24
Peak memory 207104 kb
Host smart-5b53a5ec-551d-46cd-97b8-93cd3af18be9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18388
4321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.183884321
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_enable.3389660661
Short name T2032
Test name
Test status
Simulation time 26227077 ps
CPU time 0.7 seconds
Started Jul 25 07:02:50 PM PDT 24
Finished Jul 25 07:02:51 PM PDT 24
Peak memory 207152 kb
Host smart-60e6e88c-3a1d-418b-8c08-2c6edaaaed7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33896
60661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.3389660661
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.1474470615
Short name T2016
Test name
Test status
Simulation time 889773312 ps
CPU time 2.59 seconds
Started Jul 25 07:02:53 PM PDT 24
Finished Jul 25 07:02:56 PM PDT 24
Peak memory 207376 kb
Host smart-153da15b-1e49-4e1b-b5f0-6616407c72ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14744
70615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.1474470615
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.2456290197
Short name T1631
Test name
Test status
Simulation time 183658976 ps
CPU time 2.43 seconds
Started Jul 25 07:02:49 PM PDT 24
Finished Jul 25 07:02:51 PM PDT 24
Peak memory 207284 kb
Host smart-af1d0b20-75a4-47e3-9cc8-c0b42e30843a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24562
90197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.2456290197
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.3154673518
Short name T1531
Test name
Test status
Simulation time 166638281 ps
CPU time 0.92 seconds
Started Jul 25 07:02:44 PM PDT 24
Finished Jul 25 07:02:45 PM PDT 24
Peak memory 207084 kb
Host smart-e3b14b88-7319-402a-af4f-2177ccb6cb69
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3154673518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.3154673518
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.742611188
Short name T1032
Test name
Test status
Simulation time 151986996 ps
CPU time 0.8 seconds
Started Jul 25 07:02:45 PM PDT 24
Finished Jul 25 07:02:46 PM PDT 24
Peak memory 207132 kb
Host smart-4ee2e777-3002-43ba-ac00-ce8dea7271a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74261
1188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.742611188
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.4104130642
Short name T1303
Test name
Test status
Simulation time 161668096 ps
CPU time 0.88 seconds
Started Jul 25 07:02:53 PM PDT 24
Finished Jul 25 07:02:54 PM PDT 24
Peak memory 207112 kb
Host smart-410c9128-9b90-4733-89c1-7fad5f56f8b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41041
30642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.4104130642
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_invalid_sync.1084511646
Short name T2003
Test name
Test status
Simulation time 7216793606 ps
CPU time 74.14 seconds
Started Jul 25 07:03:00 PM PDT 24
Finished Jul 25 07:04:15 PM PDT 24
Peak memory 217156 kb
Host smart-362c48bc-fc89-467c-81d5-7997c213b294
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1084511646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.1084511646
Directory /workspace/11.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/11.usbdev_iso_retraction.1771799371
Short name T2760
Test name
Test status
Simulation time 5980924384 ps
CPU time 77.57 seconds
Started Jul 25 07:02:47 PM PDT 24
Finished Jul 25 07:04:05 PM PDT 24
Peak memory 207340 kb
Host smart-2c836d50-5803-4e4e-a7d0-940ed0f0c3aa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1771799371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.1771799371
Directory /workspace/11.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.1391484932
Short name T2346
Test name
Test status
Simulation time 246820593 ps
CPU time 1.05 seconds
Started Jul 25 07:02:44 PM PDT 24
Finished Jul 25 07:02:45 PM PDT 24
Peak memory 207108 kb
Host smart-2cfc80c2-b9e2-4799-9b4c-8f56180a9355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13914
84932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.1391484932
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.3281706714
Short name T2366
Test name
Test status
Simulation time 23313365053 ps
CPU time 27.42 seconds
Started Jul 25 07:02:48 PM PDT 24
Finished Jul 25 07:03:16 PM PDT 24
Peak memory 207392 kb
Host smart-4df560f8-f695-4327-b499-8e74c29711bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32817
06714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.3281706714
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.3951964075
Short name T646
Test name
Test status
Simulation time 3305014913 ps
CPU time 5.19 seconds
Started Jul 25 07:02:49 PM PDT 24
Finished Jul 25 07:02:54 PM PDT 24
Peak memory 207440 kb
Host smart-1b83108f-6576-4908-bdc1-06febad2a42e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39519
64075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.3951964075
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.1285294530
Short name T238
Test name
Test status
Simulation time 8736832267 ps
CPU time 68.32 seconds
Started Jul 25 07:02:50 PM PDT 24
Finished Jul 25 07:03:58 PM PDT 24
Peak memory 217596 kb
Host smart-b0150b83-d0fb-4d42-9430-5f7caf4e8580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12852
94530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.1285294530
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.3399996622
Short name T2747
Test name
Test status
Simulation time 3342533412 ps
CPU time 34.35 seconds
Started Jul 25 07:02:48 PM PDT 24
Finished Jul 25 07:03:23 PM PDT 24
Peak memory 216864 kb
Host smart-3c4dccda-b8a3-4050-ba02-c55666807687
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3399996622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.3399996622
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.521286590
Short name T1223
Test name
Test status
Simulation time 245936208 ps
CPU time 1.05 seconds
Started Jul 25 07:02:50 PM PDT 24
Finished Jul 25 07:02:51 PM PDT 24
Peak memory 207196 kb
Host smart-3ffb1ac9-6cbf-4995-bafd-a44947c4e919
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=521286590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.521286590
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.2260989647
Short name T940
Test name
Test status
Simulation time 194229308 ps
CPU time 1.01 seconds
Started Jul 25 07:02:49 PM PDT 24
Finished Jul 25 07:02:50 PM PDT 24
Peak memory 207124 kb
Host smart-e2648344-94b6-4eba-8e6b-952188519f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22609
89647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.2260989647
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.481239964
Short name T404
Test name
Test status
Simulation time 6018623130 ps
CPU time 170.43 seconds
Started Jul 25 07:02:55 PM PDT 24
Finished Jul 25 07:05:46 PM PDT 24
Peak memory 215592 kb
Host smart-e9f0f139-6ff2-40b4-a11f-d851b072575d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48123
9964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.481239964
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.727330736
Short name T1964
Test name
Test status
Simulation time 3314538280 ps
CPU time 33.39 seconds
Started Jul 25 07:02:58 PM PDT 24
Finished Jul 25 07:03:31 PM PDT 24
Peak memory 217024 kb
Host smart-9d27914d-403e-4f9d-b947-5b2666dd1341
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=727330736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.727330736
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.1166943198
Short name T1313
Test name
Test status
Simulation time 188400038 ps
CPU time 0.94 seconds
Started Jul 25 07:03:03 PM PDT 24
Finished Jul 25 07:03:05 PM PDT 24
Peak memory 207152 kb
Host smart-e14baf35-f5c5-4355-b12f-eae6890728a8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1166943198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.1166943198
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.1660588578
Short name T2832
Test name
Test status
Simulation time 156560192 ps
CPU time 0.86 seconds
Started Jul 25 07:03:02 PM PDT 24
Finished Jul 25 07:03:03 PM PDT 24
Peak memory 207148 kb
Host smart-86021872-ea13-43cf-b494-e8b24a5fd7bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16605
88578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.1660588578
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.348213834
Short name T2850
Test name
Test status
Simulation time 185531273 ps
CPU time 0.88 seconds
Started Jul 25 07:02:54 PM PDT 24
Finished Jul 25 07:02:55 PM PDT 24
Peak memory 207144 kb
Host smart-3bdf417a-166b-40d8-843d-3a5be572fc5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34821
3834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.348213834
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.1245632774
Short name T778
Test name
Test status
Simulation time 199300376 ps
CPU time 0.88 seconds
Started Jul 25 07:02:55 PM PDT 24
Finished Jul 25 07:02:56 PM PDT 24
Peak memory 207192 kb
Host smart-abf309a3-1db3-4ea4-b7d5-672854b8b2ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12456
32774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.1245632774
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.4010876101
Short name T2775
Test name
Test status
Simulation time 155311515 ps
CPU time 0.84 seconds
Started Jul 25 07:02:55 PM PDT 24
Finished Jul 25 07:02:56 PM PDT 24
Peak memory 207152 kb
Host smart-2e0cd462-4a2d-42a7-ae28-108409254bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40108
76101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.4010876101
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.2947712183
Short name T1179
Test name
Test status
Simulation time 181906865 ps
CPU time 0.9 seconds
Started Jul 25 07:02:53 PM PDT 24
Finished Jul 25 07:02:54 PM PDT 24
Peak memory 207120 kb
Host smart-a732fb28-3467-4f15-92aa-526fd6e6ebc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29477
12183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.2947712183
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.4080614329
Short name T2663
Test name
Test status
Simulation time 232535277 ps
CPU time 0.97 seconds
Started Jul 25 07:02:54 PM PDT 24
Finished Jul 25 07:02:55 PM PDT 24
Peak memory 207164 kb
Host smart-5994dfb7-0a28-41ed-a3c8-df88788b8593
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4080614329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.4080614329
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.1064263223
Short name T2525
Test name
Test status
Simulation time 140916755 ps
CPU time 0.85 seconds
Started Jul 25 07:02:56 PM PDT 24
Finished Jul 25 07:02:57 PM PDT 24
Peak memory 207064 kb
Host smart-cf0aed12-85ce-4a7a-b3ff-932db8599c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10642
63223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.1064263223
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.1609485473
Short name T2827
Test name
Test status
Simulation time 31763919 ps
CPU time 0.68 seconds
Started Jul 25 07:02:54 PM PDT 24
Finished Jul 25 07:02:55 PM PDT 24
Peak memory 207020 kb
Host smart-1422e882-0663-481b-942d-3893eba29a58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16094
85473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.1609485473
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.3673300374
Short name T1973
Test name
Test status
Simulation time 21983043879 ps
CPU time 59.55 seconds
Started Jul 25 07:03:05 PM PDT 24
Finished Jul 25 07:04:04 PM PDT 24
Peak memory 215652 kb
Host smart-cbf84b59-e237-4037-9988-f98ea0f283a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36733
00374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.3673300374
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.3755455571
Short name T451
Test name
Test status
Simulation time 188945722 ps
CPU time 0.97 seconds
Started Jul 25 07:03:02 PM PDT 24
Finished Jul 25 07:03:03 PM PDT 24
Peak memory 207128 kb
Host smart-3b4ea2d2-7667-45fd-bc51-70073991a80d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37554
55571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.3755455571
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.2391208366
Short name T686
Test name
Test status
Simulation time 274376521 ps
CPU time 1.02 seconds
Started Jul 25 07:03:03 PM PDT 24
Finished Jul 25 07:03:04 PM PDT 24
Peak memory 207072 kb
Host smart-65d174fc-a50b-4641-9046-68ff33a88211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23912
08366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.2391208366
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.872416730
Short name T2781
Test name
Test status
Simulation time 203607268 ps
CPU time 0.92 seconds
Started Jul 25 07:02:53 PM PDT 24
Finished Jul 25 07:02:54 PM PDT 24
Peak memory 207160 kb
Host smart-bd92c3d8-d5f6-4612-a239-b072ff5eea78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87241
6730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.872416730
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.566432032
Short name T1253
Test name
Test status
Simulation time 167969052 ps
CPU time 0.88 seconds
Started Jul 25 07:02:53 PM PDT 24
Finished Jul 25 07:02:54 PM PDT 24
Peak memory 207124 kb
Host smart-50341b47-a7d4-4eb3-80d1-a7ebfaee45c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56643
2032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.566432032
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.1280505014
Short name T1516
Test name
Test status
Simulation time 188781906 ps
CPU time 0.95 seconds
Started Jul 25 07:03:03 PM PDT 24
Finished Jul 25 07:03:04 PM PDT 24
Peak memory 207092 kb
Host smart-0f1b685e-6a1c-41a2-8ed0-4cff6e17222c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12805
05014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.1280505014
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.1161168612
Short name T2100
Test name
Test status
Simulation time 151371566 ps
CPU time 0.82 seconds
Started Jul 25 07:02:53 PM PDT 24
Finished Jul 25 07:02:54 PM PDT 24
Peak memory 207104 kb
Host smart-8b5c90c0-f513-4b78-8365-f9362c01a03e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11611
68612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.1161168612
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.2593895295
Short name T870
Test name
Test status
Simulation time 163736568 ps
CPU time 0.85 seconds
Started Jul 25 07:02:55 PM PDT 24
Finished Jul 25 07:02:56 PM PDT 24
Peak memory 207152 kb
Host smart-81af057b-413b-47ae-818c-aecd94c9d3d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25938
95295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.2593895295
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.3608502809
Short name T1524
Test name
Test status
Simulation time 213256532 ps
CPU time 0.98 seconds
Started Jul 25 07:02:56 PM PDT 24
Finished Jul 25 07:02:57 PM PDT 24
Peak memory 207152 kb
Host smart-d6f4f1fd-7832-4729-86cb-f78df595a8a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36085
02809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.3608502809
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.1168695811
Short name T441
Test name
Test status
Simulation time 4365889580 ps
CPU time 131.86 seconds
Started Jul 25 07:02:54 PM PDT 24
Finished Jul 25 07:05:06 PM PDT 24
Peak memory 215588 kb
Host smart-aaac2ca9-1f9f-4be3-9d00-54e8ddfff231
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1168695811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.1168695811
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.2295459339
Short name T878
Test name
Test status
Simulation time 152502340 ps
CPU time 0.84 seconds
Started Jul 25 07:02:55 PM PDT 24
Finished Jul 25 07:02:56 PM PDT 24
Peak memory 207168 kb
Host smart-1a6c18f5-2ac6-4fb1-a1ec-12a9b845a675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22954
59339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.2295459339
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.170033130
Short name T1903
Test name
Test status
Simulation time 150601756 ps
CPU time 0.84 seconds
Started Jul 25 07:02:54 PM PDT 24
Finished Jul 25 07:02:55 PM PDT 24
Peak memory 207116 kb
Host smart-66b1bc6c-6ec6-49a9-8224-62014e212986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17003
3130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.170033130
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.415777790
Short name T1588
Test name
Test status
Simulation time 704705818 ps
CPU time 2.22 seconds
Started Jul 25 07:02:54 PM PDT 24
Finished Jul 25 07:02:57 PM PDT 24
Peak memory 207076 kb
Host smart-34a60456-50be-40ab-93f1-12ad40ba1d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41577
7790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.415777790
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.334889864
Short name T2293
Test name
Test status
Simulation time 3554321779 ps
CPU time 28.41 seconds
Started Jul 25 07:03:00 PM PDT 24
Finished Jul 25 07:03:29 PM PDT 24
Peak memory 216980 kb
Host smart-2564828f-fb74-43e2-a044-278c57c73210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33488
9864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.334889864
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_timeout_missing_host_handshake.1839234562
Short name T2079
Test name
Test status
Simulation time 1519656391 ps
CPU time 13.29 seconds
Started Jul 25 07:02:50 PM PDT 24
Finished Jul 25 07:03:04 PM PDT 24
Peak memory 207372 kb
Host smart-ac4cdcd5-a09a-43fd-9821-728e9c82d3d7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839234562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_timeout_missing_hos
t_handshake.1839234562
Directory /workspace/11.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.710117432
Short name T1290
Test name
Test status
Simulation time 57053729 ps
CPU time 0.66 seconds
Started Jul 25 07:03:06 PM PDT 24
Finished Jul 25 07:03:07 PM PDT 24
Peak memory 207160 kb
Host smart-696f697c-16a8-40b7-a5f7-791efaa1c0bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=710117432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.710117432
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.3980844780
Short name T1251
Test name
Test status
Simulation time 4024267275 ps
CPU time 6.58 seconds
Started Jul 25 07:03:03 PM PDT 24
Finished Jul 25 07:03:10 PM PDT 24
Peak memory 207344 kb
Host smart-3250d136-1050-4fd3-81dd-a59f6df825e3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980844780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_a
on_wake_disconnect.3980844780
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.234508271
Short name T2326
Test name
Test status
Simulation time 13448454994 ps
CPU time 16.52 seconds
Started Jul 25 07:02:56 PM PDT 24
Finished Jul 25 07:03:13 PM PDT 24
Peak memory 207348 kb
Host smart-1a49a368-bf60-4204-8640-b6fdd3f20b59
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=234508271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.234508271
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.887297900
Short name T2269
Test name
Test status
Simulation time 23342081249 ps
CPU time 29.44 seconds
Started Jul 25 07:02:53 PM PDT 24
Finished Jul 25 07:03:23 PM PDT 24
Peak memory 207480 kb
Host smart-e285b32f-9b4a-40bd-97a8-3b5cd68dbeb6
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887297900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_ao
n_wake_resume.887297900
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.1349049793
Short name T2744
Test name
Test status
Simulation time 176751730 ps
CPU time 0.85 seconds
Started Jul 25 07:03:01 PM PDT 24
Finished Jul 25 07:03:02 PM PDT 24
Peak memory 207084 kb
Host smart-753962c8-c665-48fc-9a29-070a4d3068c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13490
49793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.1349049793
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.2348877121
Short name T2070
Test name
Test status
Simulation time 194214928 ps
CPU time 0.89 seconds
Started Jul 25 07:03:08 PM PDT 24
Finished Jul 25 07:03:09 PM PDT 24
Peak memory 207092 kb
Host smart-aeb6fdce-4058-4a1e-a09d-baeaa832b612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23488
77121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.2348877121
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.1030609207
Short name T1144
Test name
Test status
Simulation time 347443328 ps
CPU time 1.29 seconds
Started Jul 25 07:03:05 PM PDT 24
Finished Jul 25 07:03:07 PM PDT 24
Peak memory 207168 kb
Host smart-4104fa3d-1dc1-4388-9dc8-ed97f004c883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10306
09207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.1030609207
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.3153279836
Short name T2766
Test name
Test status
Simulation time 533300529 ps
CPU time 1.71 seconds
Started Jul 25 07:03:03 PM PDT 24
Finished Jul 25 07:03:05 PM PDT 24
Peak memory 207120 kb
Host smart-7d17f152-4cbd-47a6-bf98-069e9bfa8e63
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3153279836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.3153279836
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.2442562589
Short name T99
Test name
Test status
Simulation time 7240156531 ps
CPU time 16.93 seconds
Started Jul 25 07:03:03 PM PDT 24
Finished Jul 25 07:03:20 PM PDT 24
Peak memory 207324 kb
Host smart-971f2eae-9806-41ba-915e-bf30dd199f11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24425
62589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.2442562589
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_device_timeout.1451663865
Short name T1307
Test name
Test status
Simulation time 1587454114 ps
CPU time 12.79 seconds
Started Jul 25 07:03:10 PM PDT 24
Finished Jul 25 07:03:23 PM PDT 24
Peak memory 207268 kb
Host smart-003e11fd-fc80-46d8-a708-e6c9f634d3f5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451663865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_timeout.1451663865
Directory /workspace/12.usbdev_device_timeout/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.2793045750
Short name T772
Test name
Test status
Simulation time 397154759 ps
CPU time 1.3 seconds
Started Jul 25 07:03:04 PM PDT 24
Finished Jul 25 07:03:05 PM PDT 24
Peak memory 207096 kb
Host smart-54657a1c-3888-40ff-86f9-b35875efc309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27930
45750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.2793045750
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.3591981671
Short name T2483
Test name
Test status
Simulation time 147814776 ps
CPU time 0.86 seconds
Started Jul 25 07:03:04 PM PDT 24
Finished Jul 25 07:03:05 PM PDT 24
Peak memory 207076 kb
Host smart-5a7f5503-db27-47b4-84bf-7840c44bc764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35919
81671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.3591981671
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.1469734315
Short name T1106
Test name
Test status
Simulation time 38239564 ps
CPU time 0.7 seconds
Started Jul 25 07:03:06 PM PDT 24
Finished Jul 25 07:03:07 PM PDT 24
Peak memory 207080 kb
Host smart-c39683c3-c5fb-422f-aa58-3109d8f640de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14697
34315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.1469734315
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.766707662
Short name T741
Test name
Test status
Simulation time 1039526952 ps
CPU time 2.72 seconds
Started Jul 25 07:03:02 PM PDT 24
Finished Jul 25 07:03:05 PM PDT 24
Peak memory 207360 kb
Host smart-4421a61a-3d63-41bb-9712-a76498cca157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76670
7662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.766707662
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.3316408902
Short name T1881
Test name
Test status
Simulation time 226470640 ps
CPU time 1.99 seconds
Started Jul 25 07:03:05 PM PDT 24
Finished Jul 25 07:03:07 PM PDT 24
Peak memory 207328 kb
Host smart-2854f6ae-b5fe-4e25-982b-de1feed90c6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33164
08902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.3316408902
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.3185962956
Short name T1157
Test name
Test status
Simulation time 224920856 ps
CPU time 1.21 seconds
Started Jul 25 07:03:06 PM PDT 24
Finished Jul 25 07:03:08 PM PDT 24
Peak memory 207320 kb
Host smart-8bc8ff69-f321-4082-9563-17547a1f4403
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3185962956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.3185962956
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.3012841262
Short name T1343
Test name
Test status
Simulation time 184114863 ps
CPU time 0.88 seconds
Started Jul 25 07:03:07 PM PDT 24
Finished Jul 25 07:03:08 PM PDT 24
Peak memory 207112 kb
Host smart-39e8a73b-0388-4db6-8823-7680d712efea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30128
41262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.3012841262
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.1856482223
Short name T2275
Test name
Test status
Simulation time 189894348 ps
CPU time 0.97 seconds
Started Jul 25 07:03:02 PM PDT 24
Finished Jul 25 07:03:03 PM PDT 24
Peak memory 207160 kb
Host smart-fac94dd1-c493-4fe8-a2a1-92934e58ead4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18564
82223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.1856482223
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.3213536328
Short name T2312
Test name
Test status
Simulation time 8839398475 ps
CPU time 65.53 seconds
Started Jul 25 07:03:02 PM PDT 24
Finished Jul 25 07:04:08 PM PDT 24
Peak memory 215572 kb
Host smart-8345ccda-b45e-4ff1-8453-8272fdf30b33
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3213536328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.3213536328
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/12.usbdev_iso_retraction.2889174877
Short name T1629
Test name
Test status
Simulation time 3980018579 ps
CPU time 28.63 seconds
Started Jul 25 07:03:09 PM PDT 24
Finished Jul 25 07:03:37 PM PDT 24
Peak memory 207368 kb
Host smart-cf1b346f-ed2a-4608-b947-9c5146052dda
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2889174877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.2889174877
Directory /workspace/12.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.1647474372
Short name T1330
Test name
Test status
Simulation time 263471140 ps
CPU time 1.06 seconds
Started Jul 25 07:03:07 PM PDT 24
Finished Jul 25 07:03:08 PM PDT 24
Peak memory 207128 kb
Host smart-ed02df34-0f7e-456a-bb47-0023edba898a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16474
74372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.1647474372
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.1750148897
Short name T1817
Test name
Test status
Simulation time 23302666352 ps
CPU time 28.86 seconds
Started Jul 25 07:03:02 PM PDT 24
Finished Jul 25 07:03:31 PM PDT 24
Peak memory 207392 kb
Host smart-8576fd1d-f255-45cb-b322-524953cabc91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17501
48897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.1750148897
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.3316750274
Short name T774
Test name
Test status
Simulation time 3296121041 ps
CPU time 5.22 seconds
Started Jul 25 07:03:05 PM PDT 24
Finished Jul 25 07:03:11 PM PDT 24
Peak memory 207368 kb
Host smart-c7ccf9ae-dfa2-4b53-9098-8d320382ea7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33167
50274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.3316750274
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.1276033631
Short name T2593
Test name
Test status
Simulation time 7853978978 ps
CPU time 236.18 seconds
Started Jul 25 07:03:06 PM PDT 24
Finished Jul 25 07:07:02 PM PDT 24
Peak memory 215524 kb
Host smart-9e769caa-8ad4-4a59-b9ff-bd52466d17fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12760
33631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.1276033631
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.1156648711
Short name T937
Test name
Test status
Simulation time 4949015938 ps
CPU time 50.68 seconds
Started Jul 25 07:03:04 PM PDT 24
Finished Jul 25 07:03:55 PM PDT 24
Peak memory 207388 kb
Host smart-cab15666-a3c4-41ae-9e58-2ac3f7f82faa
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1156648711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.1156648711
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.3500561262
Short name T810
Test name
Test status
Simulation time 253676160 ps
CPU time 0.98 seconds
Started Jul 25 07:03:10 PM PDT 24
Finished Jul 25 07:03:11 PM PDT 24
Peak memory 207136 kb
Host smart-96aae1b5-19ea-4653-bddf-78017562ed8a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3500561262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.3500561262
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.797874744
Short name T2451
Test name
Test status
Simulation time 184132149 ps
CPU time 0.94 seconds
Started Jul 25 07:03:06 PM PDT 24
Finished Jul 25 07:03:07 PM PDT 24
Peak memory 207156 kb
Host smart-5a2a09d5-3935-49b0-9c4a-ad6447d24b74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79787
4744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.797874744
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.1388082373
Short name T750
Test name
Test status
Simulation time 7007554061 ps
CPU time 52.22 seconds
Started Jul 25 07:03:02 PM PDT 24
Finished Jul 25 07:03:55 PM PDT 24
Peak memory 215592 kb
Host smart-5d7f14cc-2940-4d40-8db8-ed1289b9836c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13880
82373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.1388082373
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.2027518285
Short name T1861
Test name
Test status
Simulation time 3500096951 ps
CPU time 94.17 seconds
Started Jul 25 07:03:01 PM PDT 24
Finished Jul 25 07:04:36 PM PDT 24
Peak memory 223492 kb
Host smart-9232d2ac-b4b6-4d27-b268-472a7da6e592
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2027518285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.2027518285
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.2337906948
Short name T1743
Test name
Test status
Simulation time 177961387 ps
CPU time 0.92 seconds
Started Jul 25 07:03:03 PM PDT 24
Finished Jul 25 07:03:04 PM PDT 24
Peak memory 207084 kb
Host smart-bb4905d1-930e-493e-8d99-aa2872b94f28
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2337906948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.2337906948
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.9923601
Short name T1843
Test name
Test status
Simulation time 147734476 ps
CPU time 0.88 seconds
Started Jul 25 07:03:03 PM PDT 24
Finished Jul 25 07:03:04 PM PDT 24
Peak memory 207120 kb
Host smart-7307c8b1-75ae-452f-ac68-1cfe2e5ee3d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99236
01 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.9923601
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.2131132785
Short name T1180
Test name
Test status
Simulation time 193104011 ps
CPU time 0.95 seconds
Started Jul 25 07:03:02 PM PDT 24
Finished Jul 25 07:03:03 PM PDT 24
Peak memory 207112 kb
Host smart-d47b0b33-3211-4923-9cc2-9dc4505c24b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21311
32785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.2131132785
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.3681333960
Short name T1655
Test name
Test status
Simulation time 187456551 ps
CPU time 0.86 seconds
Started Jul 25 07:03:05 PM PDT 24
Finished Jul 25 07:03:06 PM PDT 24
Peak memory 207164 kb
Host smart-e80b218f-f776-44ef-b703-a30a57a6cf86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36813
33960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.3681333960
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.2316703226
Short name T407
Test name
Test status
Simulation time 167365376 ps
CPU time 0.85 seconds
Started Jul 25 07:03:07 PM PDT 24
Finished Jul 25 07:03:08 PM PDT 24
Peak memory 207144 kb
Host smart-d1f6cd2f-3949-4e4a-9ff8-5f64190001d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23167
03226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.2316703226
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.2149367667
Short name T182
Test name
Test status
Simulation time 197808368 ps
CPU time 0.87 seconds
Started Jul 25 07:03:09 PM PDT 24
Finished Jul 25 07:03:10 PM PDT 24
Peak memory 207104 kb
Host smart-c9ac6a69-2e25-43e5-acfd-0d163d59b557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21493
67667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.2149367667
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.567319556
Short name T2305
Test name
Test status
Simulation time 239861134 ps
CPU time 1 seconds
Started Jul 25 07:03:07 PM PDT 24
Finished Jul 25 07:03:08 PM PDT 24
Peak memory 207140 kb
Host smart-f8d4265f-6db0-473f-8115-e6e4eb57c209
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=567319556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.567319556
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.1150553866
Short name T1212
Test name
Test status
Simulation time 150876352 ps
CPU time 0.98 seconds
Started Jul 25 07:03:02 PM PDT 24
Finished Jul 25 07:03:03 PM PDT 24
Peak memory 207096 kb
Host smart-9057802a-8685-4132-b867-8856a6402ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11505
53866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.1150553866
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.4187358057
Short name T1920
Test name
Test status
Simulation time 73304561 ps
CPU time 0.73 seconds
Started Jul 25 07:03:13 PM PDT 24
Finished Jul 25 07:03:14 PM PDT 24
Peak memory 207076 kb
Host smart-987bedb6-410f-4a69-a9c1-7dbd94a96971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41873
58057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.4187358057
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.70953487
Short name T2459
Test name
Test status
Simulation time 12015692263 ps
CPU time 30.84 seconds
Started Jul 25 07:03:07 PM PDT 24
Finished Jul 25 07:03:38 PM PDT 24
Peak memory 215556 kb
Host smart-bf39fe22-4416-4900-9a55-6f806da8ca96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70953
487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.70953487
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.1607945657
Short name T832
Test name
Test status
Simulation time 206261294 ps
CPU time 1.01 seconds
Started Jul 25 07:03:04 PM PDT 24
Finished Jul 25 07:03:05 PM PDT 24
Peak memory 207136 kb
Host smart-0f84e9be-b647-450a-bdab-4fbc9f2e8d7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16079
45657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.1607945657
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.2679750850
Short name T2687
Test name
Test status
Simulation time 278464686 ps
CPU time 1.01 seconds
Started Jul 25 07:03:04 PM PDT 24
Finished Jul 25 07:03:06 PM PDT 24
Peak memory 207160 kb
Host smart-3cd3874c-1d96-4489-862a-a3a11a1244b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26797
50850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2679750850
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.3788179714
Short name T2244
Test name
Test status
Simulation time 215569837 ps
CPU time 0.97 seconds
Started Jul 25 07:03:05 PM PDT 24
Finished Jul 25 07:03:06 PM PDT 24
Peak memory 207152 kb
Host smart-976d3a23-eb0d-4efa-80fc-ea4e7c0baed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37881
79714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.3788179714
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.4161153489
Short name T375
Test name
Test status
Simulation time 216681910 ps
CPU time 0.93 seconds
Started Jul 25 07:03:05 PM PDT 24
Finished Jul 25 07:03:06 PM PDT 24
Peak memory 207152 kb
Host smart-b6dced9e-ef2a-48ac-9d66-47875a912264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41611
53489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.4161153489
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.531213606
Short name T946
Test name
Test status
Simulation time 157822825 ps
CPU time 0.85 seconds
Started Jul 25 07:05:43 PM PDT 24
Finished Jul 25 07:05:44 PM PDT 24
Peak memory 207080 kb
Host smart-19faeff0-7648-4b53-a485-9efd725635c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53121
3606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.531213606
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.325121601
Short name T371
Test name
Test status
Simulation time 154296188 ps
CPU time 0.84 seconds
Started Jul 25 07:03:06 PM PDT 24
Finished Jul 25 07:03:07 PM PDT 24
Peak memory 207080 kb
Host smart-1c840164-17c3-46aa-b36a-80564b063edb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32512
1601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.325121601
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.659806258
Short name T1464
Test name
Test status
Simulation time 164869528 ps
CPU time 0.86 seconds
Started Jul 25 07:03:05 PM PDT 24
Finished Jul 25 07:03:06 PM PDT 24
Peak memory 207132 kb
Host smart-2cca06c4-8b8f-489b-812a-af2aa9338072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65980
6258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.659806258
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.3633755792
Short name T770
Test name
Test status
Simulation time 232627755 ps
CPU time 1.04 seconds
Started Jul 25 07:03:06 PM PDT 24
Finished Jul 25 07:03:07 PM PDT 24
Peak memory 207116 kb
Host smart-b26e4a59-75b6-4f16-bc74-ad66759467aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36337
55792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.3633755792
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.3521517518
Short name T2592
Test name
Test status
Simulation time 7375186883 ps
CPU time 56.99 seconds
Started Jul 25 07:03:02 PM PDT 24
Finished Jul 25 07:04:00 PM PDT 24
Peak memory 217044 kb
Host smart-3548761b-66b2-4a82-a9e7-cd5364699242
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3521517518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.3521517518
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.766169981
Short name T776
Test name
Test status
Simulation time 168865178 ps
CPU time 0.86 seconds
Started Jul 25 07:03:13 PM PDT 24
Finished Jul 25 07:03:14 PM PDT 24
Peak memory 207112 kb
Host smart-27b89410-6bfd-49c7-89f0-0a22df59625c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76616
9981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.766169981
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.3754315306
Short name T2182
Test name
Test status
Simulation time 202907142 ps
CPU time 0.87 seconds
Started Jul 25 07:03:10 PM PDT 24
Finished Jul 25 07:03:11 PM PDT 24
Peak memory 207112 kb
Host smart-e0f05b4e-e19b-4104-a1bb-d569190ee24d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37543
15306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.3754315306
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.1584215694
Short name T2005
Test name
Test status
Simulation time 1340060537 ps
CPU time 3.08 seconds
Started Jul 25 07:03:07 PM PDT 24
Finished Jul 25 07:03:11 PM PDT 24
Peak memory 207344 kb
Host smart-17944cf6-2dac-44dd-a879-33b38e9acb50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15842
15694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.1584215694
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.312071807
Short name T2784
Test name
Test status
Simulation time 4233498341 ps
CPU time 118.99 seconds
Started Jul 25 07:03:13 PM PDT 24
Finished Jul 25 07:05:12 PM PDT 24
Peak memory 215572 kb
Host smart-f4f21c04-8add-4e1b-88a4-7d390c20ac26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31207
1807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.312071807
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_timeout_missing_host_handshake.2011587811
Short name T1337
Test name
Test status
Simulation time 1569922507 ps
CPU time 38.66 seconds
Started Jul 25 07:03:04 PM PDT 24
Finished Jul 25 07:03:43 PM PDT 24
Peak memory 207344 kb
Host smart-d80148d3-49db-4a93-9f99-68ec85d3c4f2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011587811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_timeout_missing_hos
t_handshake.2011587811
Directory /workspace/12.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.2203608858
Short name T1998
Test name
Test status
Simulation time 82318390 ps
CPU time 0.74 seconds
Started Jul 25 07:03:27 PM PDT 24
Finished Jul 25 07:03:28 PM PDT 24
Peak memory 207168 kb
Host smart-9f04cc9c-c7bc-4a0d-9f54-acc41fbffe2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2203608858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.2203608858
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.1777520051
Short name T237
Test name
Test status
Simulation time 3918520755 ps
CPU time 6.87 seconds
Started Jul 25 07:03:08 PM PDT 24
Finished Jul 25 07:03:15 PM PDT 24
Peak memory 207384 kb
Host smart-039eae0d-45b8-48c4-a662-6227e8b2b2da
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777520051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_a
on_wake_disconnect.1777520051
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.4218460344
Short name T886
Test name
Test status
Simulation time 13432044873 ps
CPU time 18.15 seconds
Started Jul 25 07:03:13 PM PDT 24
Finished Jul 25 07:03:32 PM PDT 24
Peak memory 207336 kb
Host smart-4c103f9c-faa0-4f70-8f3f-88bd90f2331a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218460344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.4218460344
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.502818144
Short name T1576
Test name
Test status
Simulation time 23509923832 ps
CPU time 28.62 seconds
Started Jul 25 07:03:13 PM PDT 24
Finished Jul 25 07:03:42 PM PDT 24
Peak memory 207392 kb
Host smart-68999fe7-69a3-42cf-802d-b79acdaa3be7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502818144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_ao
n_wake_resume.502818144
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.2770267327
Short name T1196
Test name
Test status
Simulation time 152512675 ps
CPU time 0.82 seconds
Started Jul 25 07:03:12 PM PDT 24
Finished Jul 25 07:03:13 PM PDT 24
Peak memory 207120 kb
Host smart-2ed065c5-7b76-4b29-9d91-62fa7193e85c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27702
67327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.2770267327
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.3508592814
Short name T1455
Test name
Test status
Simulation time 150545530 ps
CPU time 0.81 seconds
Started Jul 25 07:03:12 PM PDT 24
Finished Jul 25 07:03:13 PM PDT 24
Peak memory 207052 kb
Host smart-05b1662b-2c32-45bf-bbbb-ed8195419edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35085
92814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.3508592814
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.3649765350
Short name T980
Test name
Test status
Simulation time 264062338 ps
CPU time 1.11 seconds
Started Jul 25 07:03:17 PM PDT 24
Finished Jul 25 07:03:18 PM PDT 24
Peak memory 207212 kb
Host smart-85858f4e-9499-42c2-b655-e35adfa45f76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36497
65350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.3649765350
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.1615489787
Short name T1616
Test name
Test status
Simulation time 1056798311 ps
CPU time 2.77 seconds
Started Jul 25 07:03:17 PM PDT 24
Finished Jul 25 07:03:20 PM PDT 24
Peak memory 207380 kb
Host smart-447b01d3-fb36-42ca-ab4a-8941db230452
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1615489787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.1615489787
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.3769798608
Short name T1392
Test name
Test status
Simulation time 12154906423 ps
CPU time 29.71 seconds
Started Jul 25 07:03:13 PM PDT 24
Finished Jul 25 07:03:43 PM PDT 24
Peak memory 207372 kb
Host smart-1258b289-ea02-400e-88a9-4b8419312186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37697
98608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.3769798608
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_device_timeout.1123372274
Short name T2701
Test name
Test status
Simulation time 2459744882 ps
CPU time 21.7 seconds
Started Jul 25 07:03:13 PM PDT 24
Finished Jul 25 07:03:35 PM PDT 24
Peak memory 207416 kb
Host smart-6e8e3586-e390-4f71-ba2e-83c97effb1ac
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123372274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_timeout.1123372274
Directory /workspace/13.usbdev_device_timeout/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.493276450
Short name T305
Test name
Test status
Simulation time 421923605 ps
CPU time 1.44 seconds
Started Jul 25 07:03:17 PM PDT 24
Finished Jul 25 07:03:18 PM PDT 24
Peak memory 207092 kb
Host smart-dbe113ef-b148-42fc-80be-7458d188bdc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49327
6450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.493276450
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.3791644449
Short name T458
Test name
Test status
Simulation time 145537673 ps
CPU time 0.81 seconds
Started Jul 25 07:03:13 PM PDT 24
Finished Jul 25 07:03:14 PM PDT 24
Peak memory 207120 kb
Host smart-7e5071d6-b4eb-4526-8d84-3ea6910d13c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37916
44449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.3791644449
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.120616590
Short name T913
Test name
Test status
Simulation time 37169952 ps
CPU time 0.72 seconds
Started Jul 25 07:03:17 PM PDT 24
Finished Jul 25 07:03:18 PM PDT 24
Peak memory 207172 kb
Host smart-672b51ae-8c59-4540-a48b-c69973758742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12061
6590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.120616590
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.4043563909
Short name T1401
Test name
Test status
Simulation time 925247656 ps
CPU time 2.44 seconds
Started Jul 25 07:03:16 PM PDT 24
Finished Jul 25 07:03:18 PM PDT 24
Peak memory 207420 kb
Host smart-ce12ca9e-4752-4580-b161-4f98c1535d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40435
63909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.4043563909
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.618179220
Short name T1911
Test name
Test status
Simulation time 183888555 ps
CPU time 2.22 seconds
Started Jul 25 07:03:19 PM PDT 24
Finished Jul 25 07:03:22 PM PDT 24
Peak memory 207332 kb
Host smart-ce0cae68-0384-4eb3-bc98-fc95494f76a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61817
9220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.618179220
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.2785853363
Short name T1540
Test name
Test status
Simulation time 222128126 ps
CPU time 1.13 seconds
Started Jul 25 07:03:12 PM PDT 24
Finished Jul 25 07:03:14 PM PDT 24
Peak memory 215464 kb
Host smart-de99e261-91cd-49b4-9d52-e285009984cb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2785853363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.2785853363
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.3406913389
Short name T353
Test name
Test status
Simulation time 164373492 ps
CPU time 0.83 seconds
Started Jul 25 07:03:14 PM PDT 24
Finished Jul 25 07:03:15 PM PDT 24
Peak memory 207080 kb
Host smart-01ad1b09-154c-4d25-bcd6-671cb9e60d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34069
13389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.3406913389
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.840610366
Short name T734
Test name
Test status
Simulation time 168614184 ps
CPU time 0.88 seconds
Started Jul 25 07:03:13 PM PDT 24
Finished Jul 25 07:03:14 PM PDT 24
Peak memory 207112 kb
Host smart-acdf9d1b-0b0d-4aa9-8dbd-56b08fe67353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84061
0366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.840610366
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_invalid_sync.3652377223
Short name T1952
Test name
Test status
Simulation time 6680547405 ps
CPU time 54.45 seconds
Started Jul 25 07:03:12 PM PDT 24
Finished Jul 25 07:04:07 PM PDT 24
Peak memory 216864 kb
Host smart-bb17a12f-5550-4ccb-8bdf-031a7eed3ccb
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3652377223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.3652377223
Directory /workspace/13.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.1263361419
Short name T1349
Test name
Test status
Simulation time 194412815 ps
CPU time 0.86 seconds
Started Jul 25 07:03:13 PM PDT 24
Finished Jul 25 07:03:14 PM PDT 24
Peak memory 207116 kb
Host smart-7418a43b-a76d-4d36-b658-b5afae3fcc69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12633
61419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.1263361419
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.2987972511
Short name T2675
Test name
Test status
Simulation time 23280220159 ps
CPU time 29.14 seconds
Started Jul 25 07:03:18 PM PDT 24
Finished Jul 25 07:03:47 PM PDT 24
Peak memory 207484 kb
Host smart-af30937a-9c52-4fcf-9d38-88d9b5230e71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29879
72511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.2987972511
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.1672271096
Short name T2160
Test name
Test status
Simulation time 3424990100 ps
CPU time 5.42 seconds
Started Jul 25 07:03:13 PM PDT 24
Finished Jul 25 07:03:19 PM PDT 24
Peak memory 207372 kb
Host smart-c9f1f8a0-46cc-4e13-a299-dac37413b2a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16722
71096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.1672271096
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.277781508
Short name T2500
Test name
Test status
Simulation time 6870146825 ps
CPU time 205.81 seconds
Started Jul 25 07:03:12 PM PDT 24
Finished Jul 25 07:06:38 PM PDT 24
Peak memory 215660 kb
Host smart-f36d116c-1bb2-476c-aaff-dc8eb441a2bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27778
1508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.277781508
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.414511723
Short name T1226
Test name
Test status
Simulation time 5664804816 ps
CPU time 165.78 seconds
Started Jul 25 07:03:16 PM PDT 24
Finished Jul 25 07:06:01 PM PDT 24
Peak memory 215584 kb
Host smart-86a2f9d2-460f-437d-aee7-3db9a1da6c00
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=414511723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.414511723
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.1872249026
Short name T1311
Test name
Test status
Simulation time 259616726 ps
CPU time 1.05 seconds
Started Jul 25 07:03:17 PM PDT 24
Finished Jul 25 07:03:19 PM PDT 24
Peak memory 207148 kb
Host smart-99646a29-a556-42c5-b667-7fe3f98db50b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1872249026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.1872249026
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.1135754835
Short name T2833
Test name
Test status
Simulation time 217675378 ps
CPU time 0.99 seconds
Started Jul 25 07:03:17 PM PDT 24
Finished Jul 25 07:03:18 PM PDT 24
Peak memory 207216 kb
Host smart-e50b8352-6129-42fb-ae76-823637ed9d52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11357
54835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.1135754835
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.375719224
Short name T981
Test name
Test status
Simulation time 4131515952 ps
CPU time 124.93 seconds
Started Jul 25 07:03:14 PM PDT 24
Finished Jul 25 07:05:19 PM PDT 24
Peak memory 215556 kb
Host smart-ab048463-ecb8-4bdf-991c-63aa8de7a711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37571
9224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.375719224
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.1760074919
Short name T903
Test name
Test status
Simulation time 238990526 ps
CPU time 0.95 seconds
Started Jul 25 07:03:17 PM PDT 24
Finished Jul 25 07:03:18 PM PDT 24
Peak memory 207136 kb
Host smart-7b7fa7f3-04ac-4acb-b0a0-fbd23dedf3cd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1760074919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.1760074919
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.1929966160
Short name T1120
Test name
Test status
Simulation time 141167101 ps
CPU time 0.85 seconds
Started Jul 25 07:03:15 PM PDT 24
Finished Jul 25 07:03:16 PM PDT 24
Peak memory 207192 kb
Host smart-dbd76d83-9ba4-490c-b882-ac0f65eb1789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19299
66160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.1929966160
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.3541282751
Short name T131
Test name
Test status
Simulation time 229694933 ps
CPU time 0.97 seconds
Started Jul 25 07:03:14 PM PDT 24
Finished Jul 25 07:03:15 PM PDT 24
Peak memory 207128 kb
Host smart-d6285de0-d6e2-4caf-af45-fe6b19ee28a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35412
82751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.3541282751
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.1241377645
Short name T1029
Test name
Test status
Simulation time 172639463 ps
CPU time 0.87 seconds
Started Jul 25 07:03:12 PM PDT 24
Finished Jul 25 07:03:14 PM PDT 24
Peak memory 207116 kb
Host smart-594a8862-15b1-4132-b829-bfe69f2ce993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12413
77645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.1241377645
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.1465227743
Short name T1533
Test name
Test status
Simulation time 209144141 ps
CPU time 0.91 seconds
Started Jul 25 07:03:17 PM PDT 24
Finished Jul 25 07:03:19 PM PDT 24
Peak memory 207160 kb
Host smart-03335813-4855-49b5-88d1-11e0a52f5036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14652
27743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.1465227743
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.2578787469
Short name T77
Test name
Test status
Simulation time 235394162 ps
CPU time 0.92 seconds
Started Jul 25 07:03:12 PM PDT 24
Finished Jul 25 07:03:13 PM PDT 24
Peak memory 207152 kb
Host smart-14722f3c-4ebc-4945-8f62-e771642714fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25787
87469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.2578787469
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.3358349778
Short name T1230
Test name
Test status
Simulation time 195682056 ps
CPU time 0.89 seconds
Started Jul 25 07:03:17 PM PDT 24
Finished Jul 25 07:03:18 PM PDT 24
Peak memory 207140 kb
Host smart-e7203c81-b342-4931-95cd-6d59a9c90fe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33583
49778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.3358349778
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.3845357874
Short name T2021
Test name
Test status
Simulation time 250181715 ps
CPU time 1.18 seconds
Started Jul 25 07:03:15 PM PDT 24
Finished Jul 25 07:03:16 PM PDT 24
Peak memory 207140 kb
Host smart-4c005f94-de8e-4ab4-9e8d-91e2daa9436f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3845357874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.3845357874
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.3199306074
Short name T207
Test name
Test status
Simulation time 147636171 ps
CPU time 0.87 seconds
Started Jul 25 07:03:12 PM PDT 24
Finished Jul 25 07:03:14 PM PDT 24
Peak memory 207084 kb
Host smart-0e57fab6-25bd-4d5b-87d2-fa048f5654eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31993
06074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.3199306074
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.1320049234
Short name T2779
Test name
Test status
Simulation time 38629967 ps
CPU time 0.66 seconds
Started Jul 25 07:03:26 PM PDT 24
Finished Jul 25 07:03:27 PM PDT 24
Peak memory 207092 kb
Host smart-cb7b7800-cdb8-4091-9115-49ae132d9057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13200
49234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.1320049234
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.3793600099
Short name T272
Test name
Test status
Simulation time 16392592946 ps
CPU time 41.3 seconds
Started Jul 25 07:03:29 PM PDT 24
Finished Jul 25 07:04:10 PM PDT 24
Peak memory 215628 kb
Host smart-0f96138d-a610-4698-a747-38c29cc9686d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37936
00099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.3793600099
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.2899592307
Short name T922
Test name
Test status
Simulation time 219219830 ps
CPU time 0.98 seconds
Started Jul 25 07:03:27 PM PDT 24
Finished Jul 25 07:03:28 PM PDT 24
Peak memory 207128 kb
Host smart-e6b2b4bb-3bb5-43c2-969b-4a9a16f46a4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28995
92307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.2899592307
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.1154001652
Short name T1052
Test name
Test status
Simulation time 295498609 ps
CPU time 1.02 seconds
Started Jul 25 07:03:24 PM PDT 24
Finished Jul 25 07:03:25 PM PDT 24
Peak memory 207048 kb
Host smart-71f0f151-cfb1-4d6c-b6d3-f1c1ba1a1771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11540
01652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.1154001652
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.2108362378
Short name T2733
Test name
Test status
Simulation time 185394172 ps
CPU time 0.91 seconds
Started Jul 25 07:03:26 PM PDT 24
Finished Jul 25 07:03:27 PM PDT 24
Peak memory 206852 kb
Host smart-25a19d87-98d2-4438-8cca-d83a2584acfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21083
62378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.2108362378
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.3966011437
Short name T363
Test name
Test status
Simulation time 159667855 ps
CPU time 0.9 seconds
Started Jul 25 07:03:24 PM PDT 24
Finished Jul 25 07:03:25 PM PDT 24
Peak memory 207116 kb
Host smart-b05fa093-e0db-4c25-9ac8-6e45f73fcaf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39660
11437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.3966011437
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.3141954618
Short name T1316
Test name
Test status
Simulation time 193529332 ps
CPU time 0.87 seconds
Started Jul 25 07:03:24 PM PDT 24
Finished Jul 25 07:03:25 PM PDT 24
Peak memory 207052 kb
Host smart-4aa0acdb-6fd3-45dc-a1c7-8058aada39d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31419
54618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.3141954618
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.1878379380
Short name T867
Test name
Test status
Simulation time 158209022 ps
CPU time 0.83 seconds
Started Jul 25 07:03:24 PM PDT 24
Finished Jul 25 07:03:25 PM PDT 24
Peak memory 207100 kb
Host smart-3aaaa0cc-14ea-433b-a172-afccb05a2fbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18783
79380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.1878379380
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.3078720965
Short name T1662
Test name
Test status
Simulation time 149762558 ps
CPU time 0.86 seconds
Started Jul 25 07:03:26 PM PDT 24
Finished Jul 25 07:03:27 PM PDT 24
Peak memory 207064 kb
Host smart-4fcd637f-2b93-4fff-975b-6dd9a6edf3e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30787
20965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.3078720965
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.2551465157
Short name T541
Test name
Test status
Simulation time 236402571 ps
CPU time 1.06 seconds
Started Jul 25 07:03:24 PM PDT 24
Finished Jul 25 07:03:25 PM PDT 24
Peak memory 207160 kb
Host smart-4acd5259-a662-4261-aa0e-30151ff37313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25514
65157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.2551465157
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.3722218738
Short name T2661
Test name
Test status
Simulation time 6394649317 ps
CPU time 52.03 seconds
Started Jul 25 07:03:27 PM PDT 24
Finished Jul 25 07:04:19 PM PDT 24
Peak memory 216752 kb
Host smart-725d19b4-6f46-40da-9d6d-07d03043717a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3722218738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.3722218738
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.1750607559
Short name T2514
Test name
Test status
Simulation time 216368902 ps
CPU time 0.95 seconds
Started Jul 25 07:03:29 PM PDT 24
Finished Jul 25 07:03:30 PM PDT 24
Peak memory 207144 kb
Host smart-daa9ac05-f2b6-4cf9-8a86-1d24ebb169a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17506
07559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.1750607559
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.3963447336
Short name T1315
Test name
Test status
Simulation time 176163027 ps
CPU time 0.97 seconds
Started Jul 25 07:03:34 PM PDT 24
Finished Jul 25 07:03:35 PM PDT 24
Peak memory 207128 kb
Host smart-35a3b886-6f06-444a-8f20-47b3379aec59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39634
47336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.3963447336
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.1612080271
Short name T2573
Test name
Test status
Simulation time 317768408 ps
CPU time 1.17 seconds
Started Jul 25 07:03:29 PM PDT 24
Finished Jul 25 07:03:30 PM PDT 24
Peak memory 207096 kb
Host smart-b8eb7f2b-89a9-411f-9668-9205be528ce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16120
80271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.1612080271
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.3119230548
Short name T452
Test name
Test status
Simulation time 5020676774 ps
CPU time 50.9 seconds
Started Jul 25 07:03:25 PM PDT 24
Finished Jul 25 07:04:16 PM PDT 24
Peak memory 207324 kb
Host smart-1029d53c-67d3-46fc-a81b-5a7a5bb3796c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31192
30548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.3119230548
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_timeout_missing_host_handshake.3045478232
Short name T674
Test name
Test status
Simulation time 5743885918 ps
CPU time 37.38 seconds
Started Jul 25 07:03:14 PM PDT 24
Finished Jul 25 07:03:52 PM PDT 24
Peak memory 207428 kb
Host smart-bc0eb038-9180-4128-bf46-92c9c8b6822e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045478232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_timeout_missing_hos
t_handshake.3045478232
Directory /workspace/13.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.3272526054
Short name T1498
Test name
Test status
Simulation time 124743527 ps
CPU time 0.76 seconds
Started Jul 25 07:03:37 PM PDT 24
Finished Jul 25 07:03:38 PM PDT 24
Peak memory 207168 kb
Host smart-7a568086-f5ae-4ea6-9f2c-43680bd591b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3272526054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.3272526054
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.2061037076
Short name T793
Test name
Test status
Simulation time 4316455876 ps
CPU time 6.28 seconds
Started Jul 25 07:03:27 PM PDT 24
Finished Jul 25 07:03:34 PM PDT 24
Peak memory 207364 kb
Host smart-48987d26-7387-4950-b056-3f127b934eab
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061037076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_a
on_wake_disconnect.2061037076
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.2055198879
Short name T2391
Test name
Test status
Simulation time 13334374381 ps
CPU time 19.46 seconds
Started Jul 25 07:03:28 PM PDT 24
Finished Jul 25 07:03:47 PM PDT 24
Peak memory 207388 kb
Host smart-48d59f3c-5cff-4f1e-952f-030ee2ad2f97
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055198879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.2055198879
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.4203045482
Short name T1208
Test name
Test status
Simulation time 23495223063 ps
CPU time 28.33 seconds
Started Jul 25 07:03:26 PM PDT 24
Finished Jul 25 07:03:54 PM PDT 24
Peak memory 207252 kb
Host smart-02af44b2-42e5-483a-b86b-15adfdacbc63
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203045482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_a
on_wake_resume.4203045482
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.3374821644
Short name T408
Test name
Test status
Simulation time 144024548 ps
CPU time 0.82 seconds
Started Jul 25 07:03:24 PM PDT 24
Finished Jul 25 07:03:25 PM PDT 24
Peak memory 207124 kb
Host smart-aedbee1c-f459-4292-b7ed-452ce18ecb84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33748
21644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.3374821644
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.2671590921
Short name T1501
Test name
Test status
Simulation time 150572058 ps
CPU time 0.86 seconds
Started Jul 25 07:03:29 PM PDT 24
Finished Jul 25 07:03:30 PM PDT 24
Peak memory 207156 kb
Host smart-ba3ce404-9e67-467a-8806-02c6bf4a636f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26715
90921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.2671590921
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.1690687563
Short name T1844
Test name
Test status
Simulation time 187149303 ps
CPU time 0.92 seconds
Started Jul 25 07:03:26 PM PDT 24
Finished Jul 25 07:03:27 PM PDT 24
Peak memory 206948 kb
Host smart-b4879857-4cde-494d-a3e5-2ffdae4fe77b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16906
87563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.1690687563
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.3053457902
Short name T1067
Test name
Test status
Simulation time 685925346 ps
CPU time 1.9 seconds
Started Jul 25 07:03:26 PM PDT 24
Finished Jul 25 07:03:28 PM PDT 24
Peak memory 207152 kb
Host smart-915a8267-16ec-4e88-a241-759c14f2aca4
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3053457902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.3053457902
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.4232993425
Short name T1667
Test name
Test status
Simulation time 15991790936 ps
CPU time 32.72 seconds
Started Jul 25 07:03:26 PM PDT 24
Finished Jul 25 07:03:59 PM PDT 24
Peak memory 207064 kb
Host smart-62ca3157-4733-4725-8beb-0b3ea5de99e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42329
93425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.4232993425
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_device_timeout.142386938
Short name T797
Test name
Test status
Simulation time 1291641523 ps
CPU time 30.59 seconds
Started Jul 25 07:03:24 PM PDT 24
Finished Jul 25 07:03:55 PM PDT 24
Peak memory 207344 kb
Host smart-5bb39643-ae57-487e-964d-d8e61a00bb25
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142386938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_timeout.142386938
Directory /workspace/14.usbdev_device_timeout/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.1025442178
Short name T607
Test name
Test status
Simulation time 344171122 ps
CPU time 1.39 seconds
Started Jul 25 07:03:26 PM PDT 24
Finished Jul 25 07:03:27 PM PDT 24
Peak memory 207032 kb
Host smart-708a03fc-2f7d-4251-aa1c-831cc5ef1b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10254
42178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.1025442178
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.1868811558
Short name T1799
Test name
Test status
Simulation time 148044817 ps
CPU time 0.88 seconds
Started Jul 25 07:03:27 PM PDT 24
Finished Jul 25 07:03:28 PM PDT 24
Peak memory 207080 kb
Host smart-9f3f74f3-c65c-4479-b573-e26a93524fab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18688
11558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.1868811558
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.879530347
Short name T1382
Test name
Test status
Simulation time 76968120 ps
CPU time 0.73 seconds
Started Jul 25 07:03:27 PM PDT 24
Finished Jul 25 07:03:28 PM PDT 24
Peak memory 207088 kb
Host smart-82b2ebee-1e5e-41f9-8ce2-679604ad2e34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87953
0347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.879530347
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.411247711
Short name T1744
Test name
Test status
Simulation time 985497912 ps
CPU time 2.69 seconds
Started Jul 25 07:03:27 PM PDT 24
Finished Jul 25 07:03:30 PM PDT 24
Peak memory 207352 kb
Host smart-7641fdaf-c45e-42f6-b709-8210754850b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41124
7711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.411247711
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.1138802971
Short name T1414
Test name
Test status
Simulation time 211573183 ps
CPU time 1.06 seconds
Started Jul 25 07:03:29 PM PDT 24
Finished Jul 25 07:03:30 PM PDT 24
Peak memory 215532 kb
Host smart-52d10303-bf44-43ac-b692-f45cd651852e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1138802971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.1138802971
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.698668220
Short name T105
Test name
Test status
Simulation time 170151514 ps
CPU time 0.83 seconds
Started Jul 25 07:03:27 PM PDT 24
Finished Jul 25 07:03:28 PM PDT 24
Peak memory 207160 kb
Host smart-d370bae5-684d-4d27-8198-c2e60993b990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69866
8220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.698668220
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.526338332
Short name T666
Test name
Test status
Simulation time 262554448 ps
CPU time 1.08 seconds
Started Jul 25 07:03:24 PM PDT 24
Finished Jul 25 07:03:25 PM PDT 24
Peak memory 207164 kb
Host smart-0ac936d8-e80e-43f8-be3d-40f118a5aea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52633
8332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.526338332
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.888635447
Short name T98
Test name
Test status
Simulation time 4117776049 ps
CPU time 31.4 seconds
Started Jul 25 07:03:26 PM PDT 24
Finished Jul 25 07:03:58 PM PDT 24
Peak memory 215668 kb
Host smart-bd6bc720-ce62-48c3-bac9-59da2a14d873
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=888635447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.888635447
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_iso_retraction.1913756745
Short name T1851
Test name
Test status
Simulation time 13823377684 ps
CPU time 94.04 seconds
Started Jul 25 07:03:26 PM PDT 24
Finished Jul 25 07:05:00 PM PDT 24
Peak memory 207360 kb
Host smart-21bcbef7-3c45-45fb-bc92-55432069ab50
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1913756745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.1913756745
Directory /workspace/14.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.1846356011
Short name T1630
Test name
Test status
Simulation time 213511919 ps
CPU time 0.91 seconds
Started Jul 25 07:03:27 PM PDT 24
Finished Jul 25 07:03:28 PM PDT 24
Peak memory 207128 kb
Host smart-ba75723c-3b62-4ea9-b2c6-76b66fad5d0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18463
56011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.1846356011
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.1577851008
Short name T1006
Test name
Test status
Simulation time 23320712562 ps
CPU time 27.52 seconds
Started Jul 25 07:03:28 PM PDT 24
Finished Jul 25 07:03:56 PM PDT 24
Peak memory 207372 kb
Host smart-b4876a7b-cca3-4367-a757-f947f3373b59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15778
51008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.1577851008
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.4168020948
Short name T2402
Test name
Test status
Simulation time 3316714025 ps
CPU time 4.8 seconds
Started Jul 25 07:03:24 PM PDT 24
Finished Jul 25 07:03:29 PM PDT 24
Peak memory 207300 kb
Host smart-96c089f9-cba5-4451-a6e6-694391540a79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41680
20948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.4168020948
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.4044792610
Short name T2548
Test name
Test status
Simulation time 6314720764 ps
CPU time 64.01 seconds
Started Jul 25 07:03:28 PM PDT 24
Finished Jul 25 07:04:32 PM PDT 24
Peak memory 217552 kb
Host smart-50fa4572-5861-4bd0-9b9f-b0a490846be8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40447
92610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.4044792610
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.4100913121
Short name T849
Test name
Test status
Simulation time 4659513848 ps
CPU time 137.3 seconds
Started Jul 25 07:03:25 PM PDT 24
Finished Jul 25 07:05:43 PM PDT 24
Peak memory 215616 kb
Host smart-b1a736ad-cfc9-497f-9e6e-25a81bedef8a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4100913121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.4100913121
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.1925431389
Short name T2024
Test name
Test status
Simulation time 254179362 ps
CPU time 1.1 seconds
Started Jul 25 07:03:26 PM PDT 24
Finished Jul 25 07:03:27 PM PDT 24
Peak memory 207132 kb
Host smart-212dc57e-1510-423b-aaae-940c7880cc93
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1925431389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.1925431389
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.1759825839
Short name T1480
Test name
Test status
Simulation time 189533409 ps
CPU time 0.96 seconds
Started Jul 25 07:03:29 PM PDT 24
Finished Jul 25 07:03:30 PM PDT 24
Peak memory 207112 kb
Host smart-ebaf2e3c-cfce-42b9-8943-22f4469aa6eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17598
25839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.1759825839
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.3375635321
Short name T1003
Test name
Test status
Simulation time 2986573033 ps
CPU time 88.28 seconds
Started Jul 25 07:03:27 PM PDT 24
Finished Jul 25 07:04:55 PM PDT 24
Peak memory 215596 kb
Host smart-c4f9d4cc-6251-4c08-956d-79edd9fa0371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33756
35321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.3375635321
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.2174324305
Short name T1507
Test name
Test status
Simulation time 4407636642 ps
CPU time 32.78 seconds
Started Jul 25 07:03:35 PM PDT 24
Finished Jul 25 07:04:08 PM PDT 24
Peak memory 207356 kb
Host smart-b61472f4-136e-4572-adc9-124e06a911fe
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2174324305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.2174324305
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.3694678194
Short name T538
Test name
Test status
Simulation time 244333108 ps
CPU time 0.98 seconds
Started Jul 25 07:03:37 PM PDT 24
Finished Jul 25 07:03:38 PM PDT 24
Peak memory 207100 kb
Host smart-fa9dcf17-6eaa-4993-9560-3681adc7f237
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3694678194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.3694678194
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.1503551906
Short name T703
Test name
Test status
Simulation time 138589085 ps
CPU time 0.84 seconds
Started Jul 25 07:03:39 PM PDT 24
Finished Jul 25 07:03:40 PM PDT 24
Peak memory 207048 kb
Host smart-b517269f-ea0d-440f-8f24-9641f1aa6571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15035
51906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.1503551906
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.2911927389
Short name T1587
Test name
Test status
Simulation time 174032060 ps
CPU time 0.94 seconds
Started Jul 25 07:03:42 PM PDT 24
Finished Jul 25 07:03:43 PM PDT 24
Peak memory 207080 kb
Host smart-ae8221d5-a19b-47ba-8fc7-f38de4cc0d4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29119
27389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.2911927389
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.1640179558
Short name T262
Test name
Test status
Simulation time 164336398 ps
CPU time 0.81 seconds
Started Jul 25 07:03:36 PM PDT 24
Finished Jul 25 07:03:36 PM PDT 24
Peak memory 207164 kb
Host smart-a277fbc5-c517-4a5c-9507-059d9fa7322e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16401
79558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.1640179558
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.2084311600
Short name T907
Test name
Test status
Simulation time 184344631 ps
CPU time 0.9 seconds
Started Jul 25 07:03:43 PM PDT 24
Finished Jul 25 07:03:44 PM PDT 24
Peak memory 207152 kb
Host smart-59b4ed7f-d822-4851-b967-b71dfdf348cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20843
11600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.2084311600
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.2318063797
Short name T1057
Test name
Test status
Simulation time 153437002 ps
CPU time 0.9 seconds
Started Jul 25 07:03:38 PM PDT 24
Finished Jul 25 07:03:39 PM PDT 24
Peak memory 207120 kb
Host smart-b952ba34-77a7-41a8-af8a-b5db22a46a48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23180
63797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.2318063797
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.2362814306
Short name T2549
Test name
Test status
Simulation time 241426192 ps
CPU time 1.09 seconds
Started Jul 25 07:03:49 PM PDT 24
Finished Jul 25 07:03:50 PM PDT 24
Peak memory 207112 kb
Host smart-36dcc1df-8b01-44ed-a0f7-cbeb7b726c92
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2362814306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.2362814306
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.2339359339
Short name T1509
Test name
Test status
Simulation time 168031020 ps
CPU time 0.86 seconds
Started Jul 25 07:03:37 PM PDT 24
Finished Jul 25 07:03:38 PM PDT 24
Peak memory 207072 kb
Host smart-3f7eab4a-deec-445c-bf8b-c84385976dd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23393
59339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.2339359339
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.2121282600
Short name T1133
Test name
Test status
Simulation time 46066472 ps
CPU time 0.71 seconds
Started Jul 25 07:03:38 PM PDT 24
Finished Jul 25 07:03:39 PM PDT 24
Peak memory 207104 kb
Host smart-b1b297cc-d030-44b1-ba26-a5aa4247e934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21212
82600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.2121282600
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.3192250895
Short name T1603
Test name
Test status
Simulation time 7423435696 ps
CPU time 18.6 seconds
Started Jul 25 07:03:36 PM PDT 24
Finished Jul 25 07:03:55 PM PDT 24
Peak memory 215576 kb
Host smart-07d03956-8527-4b19-87dc-ae3df5b707a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31922
50895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.3192250895
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.2384865866
Short name T1094
Test name
Test status
Simulation time 191107885 ps
CPU time 1 seconds
Started Jul 25 07:03:48 PM PDT 24
Finished Jul 25 07:03:49 PM PDT 24
Peak memory 207120 kb
Host smart-817d0905-914c-46d6-aa13-3cc378c7c517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23848
65866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.2384865866
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.2451195647
Short name T438
Test name
Test status
Simulation time 224751914 ps
CPU time 0.97 seconds
Started Jul 25 07:03:47 PM PDT 24
Finished Jul 25 07:03:48 PM PDT 24
Peak memory 207100 kb
Host smart-31a2c485-79c5-4e1e-9c97-4ece93437a1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24511
95647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.2451195647
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.3968327497
Short name T2450
Test name
Test status
Simulation time 318000677 ps
CPU time 1.01 seconds
Started Jul 25 07:03:38 PM PDT 24
Finished Jul 25 07:03:40 PM PDT 24
Peak memory 207052 kb
Host smart-3c0a7fe8-a127-4c45-bbea-6662306ddd65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39683
27497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.3968327497
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.1782638748
Short name T2177
Test name
Test status
Simulation time 188883836 ps
CPU time 0.97 seconds
Started Jul 25 07:03:37 PM PDT 24
Finished Jul 25 07:03:38 PM PDT 24
Peak memory 207132 kb
Host smart-4103c415-a545-4721-979d-a48456e2d0cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17826
38748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.1782638748
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.3712974631
Short name T2588
Test name
Test status
Simulation time 155396741 ps
CPU time 0.85 seconds
Started Jul 25 07:03:43 PM PDT 24
Finished Jul 25 07:03:44 PM PDT 24
Peak memory 207104 kb
Host smart-ef88501b-3120-4d54-bc19-1a7818f12784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37129
74631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.3712974631
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.948159046
Short name T1221
Test name
Test status
Simulation time 152996731 ps
CPU time 0.84 seconds
Started Jul 25 07:03:45 PM PDT 24
Finished Jul 25 07:03:46 PM PDT 24
Peak memory 207092 kb
Host smart-65ceeaf1-527c-4164-958b-7220c12ec1ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94815
9046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.948159046
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.2066885465
Short name T888
Test name
Test status
Simulation time 144511338 ps
CPU time 0.83 seconds
Started Jul 25 07:03:47 PM PDT 24
Finished Jul 25 07:03:48 PM PDT 24
Peak memory 207132 kb
Host smart-007da2ff-a576-4494-b2fe-7e44f1f83d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20668
85465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.2066885465
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.4257179276
Short name T1679
Test name
Test status
Simulation time 262157470 ps
CPU time 1.09 seconds
Started Jul 25 07:03:42 PM PDT 24
Finished Jul 25 07:03:44 PM PDT 24
Peak memory 207112 kb
Host smart-5f85b26c-7638-4865-a65d-e95b13446f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42571
79276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.4257179276
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.1764773721
Short name T1797
Test name
Test status
Simulation time 5161562355 ps
CPU time 52.38 seconds
Started Jul 25 07:03:36 PM PDT 24
Finished Jul 25 07:04:28 PM PDT 24
Peak memory 217212 kb
Host smart-712f603a-d0a6-45ac-a335-602229dc7c06
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1764773721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.1764773721
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.3417290663
Short name T2636
Test name
Test status
Simulation time 179215691 ps
CPU time 0.94 seconds
Started Jul 25 07:03:46 PM PDT 24
Finished Jul 25 07:03:47 PM PDT 24
Peak memory 207136 kb
Host smart-4cda36dc-7e7a-4e18-92da-eeae60c8eaf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34172
90663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.3417290663
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.203641901
Short name T401
Test name
Test status
Simulation time 172099325 ps
CPU time 0.87 seconds
Started Jul 25 07:03:39 PM PDT 24
Finished Jul 25 07:03:40 PM PDT 24
Peak memory 207124 kb
Host smart-8144f08b-894a-44dd-8f89-0e782fcd8988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20364
1901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.203641901
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.3900744112
Short name T1547
Test name
Test status
Simulation time 370392643 ps
CPU time 1.25 seconds
Started Jul 25 07:03:47 PM PDT 24
Finished Jul 25 07:03:49 PM PDT 24
Peak memory 207088 kb
Host smart-11a6f411-9220-4c6a-a22e-b502583633e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39007
44112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.3900744112
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.2186821737
Short name T653
Test name
Test status
Simulation time 5133839105 ps
CPU time 147.88 seconds
Started Jul 25 07:03:36 PM PDT 24
Finished Jul 25 07:06:04 PM PDT 24
Peak memory 215588 kb
Host smart-56baac7a-80c6-45f5-98cb-914fe7eef5ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21868
21737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.2186821737
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_timeout_missing_host_handshake.1387855337
Short name T902
Test name
Test status
Simulation time 818255518 ps
CPU time 5.33 seconds
Started Jul 25 07:03:26 PM PDT 24
Finished Jul 25 07:03:31 PM PDT 24
Peak memory 207312 kb
Host smart-1b2e83c9-82aa-4be7-a55d-9b72ddb57121
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387855337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_timeout_missing_hos
t_handshake.1387855337
Directory /workspace/14.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.410570847
Short name T1784
Test name
Test status
Simulation time 97023627 ps
CPU time 0.74 seconds
Started Jul 25 07:03:44 PM PDT 24
Finished Jul 25 07:03:45 PM PDT 24
Peak memory 207136 kb
Host smart-05b3a455-df8c-4d9c-ac3d-0ab82e20c768
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=410570847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.410570847
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.345450950
Short name T2397
Test name
Test status
Simulation time 4235130460 ps
CPU time 6.25 seconds
Started Jul 25 07:03:36 PM PDT 24
Finished Jul 25 07:03:42 PM PDT 24
Peak memory 207384 kb
Host smart-42d17f60-8e3a-42cc-ae3f-3a1309539f0b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345450950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_ao
n_wake_disconnect.345450950
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.2812076471
Short name T2773
Test name
Test status
Simulation time 13460181229 ps
CPU time 20.17 seconds
Started Jul 25 07:03:41 PM PDT 24
Finished Jul 25 07:04:01 PM PDT 24
Peak memory 207416 kb
Host smart-18e9641a-8163-4705-b1ad-180a6e92d564
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812076471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.2812076471
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.2168585340
Short name T467
Test name
Test status
Simulation time 23400767368 ps
CPU time 29.06 seconds
Started Jul 25 07:03:37 PM PDT 24
Finished Jul 25 07:04:06 PM PDT 24
Peak memory 207396 kb
Host smart-b29e60b8-9104-4649-94e9-7333dda6a358
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168585340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_resume.2168585340
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.1715938548
Short name T1898
Test name
Test status
Simulation time 234432470 ps
CPU time 1.01 seconds
Started Jul 25 07:03:38 PM PDT 24
Finished Jul 25 07:03:40 PM PDT 24
Peak memory 207148 kb
Host smart-3ba3d4c0-2297-49ba-bd09-4747ebe26667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17159
38548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.1715938548
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.2523040661
Short name T1367
Test name
Test status
Simulation time 152480903 ps
CPU time 0.86 seconds
Started Jul 25 07:03:45 PM PDT 24
Finished Jul 25 07:03:46 PM PDT 24
Peak memory 207088 kb
Host smart-12cf87b1-c8cf-4b92-8671-6b93df3dfe60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25230
40661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.2523040661
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.262855731
Short name T767
Test name
Test status
Simulation time 391638520 ps
CPU time 1.48 seconds
Started Jul 25 07:03:48 PM PDT 24
Finished Jul 25 07:03:50 PM PDT 24
Peak memory 207124 kb
Host smart-30b56c11-51f4-4968-9b2d-7b74ac361856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26285
5731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.262855731
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.3621820921
Short name T1868
Test name
Test status
Simulation time 1093007896 ps
CPU time 2.87 seconds
Started Jul 25 07:03:37 PM PDT 24
Finished Jul 25 07:03:40 PM PDT 24
Peak memory 207412 kb
Host smart-564adf53-3dad-4b03-958b-9957b0efcbbf
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3621820921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.3621820921
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.3069437560
Short name T1802
Test name
Test status
Simulation time 13847624892 ps
CPU time 31.17 seconds
Started Jul 25 07:03:44 PM PDT 24
Finished Jul 25 07:04:16 PM PDT 24
Peak memory 207388 kb
Host smart-f04b423d-3e5a-45ef-abe5-a13833ab2282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30694
37560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.3069437560
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_device_timeout.1378397322
Short name T749
Test name
Test status
Simulation time 1550438889 ps
CPU time 37.09 seconds
Started Jul 25 07:03:36 PM PDT 24
Finished Jul 25 07:04:14 PM PDT 24
Peak memory 207368 kb
Host smart-c559bc9b-e57b-4251-8517-949189dd1115
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378397322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_timeout.1378397322
Directory /workspace/15.usbdev_device_timeout/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.2864668455
Short name T2570
Test name
Test status
Simulation time 498723477 ps
CPU time 1.52 seconds
Started Jul 25 07:03:37 PM PDT 24
Finished Jul 25 07:03:39 PM PDT 24
Peak memory 207032 kb
Host smart-5a1d0269-5018-4ab8-8ddd-93a8350f100d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28646
68455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.2864668455
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.1697793608
Short name T2599
Test name
Test status
Simulation time 182528920 ps
CPU time 0.86 seconds
Started Jul 25 07:03:34 PM PDT 24
Finished Jul 25 07:03:35 PM PDT 24
Peak memory 207124 kb
Host smart-5c744ea6-ef8b-4d81-abb7-b0e9d72c9f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16977
93608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.1697793608
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.1159571454
Short name T2780
Test name
Test status
Simulation time 37736841 ps
CPU time 0.71 seconds
Started Jul 25 07:03:41 PM PDT 24
Finished Jul 25 07:03:42 PM PDT 24
Peak memory 207080 kb
Host smart-22a36c21-660c-4770-9188-26cf41d9f94c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11595
71454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.1159571454
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.2846985081
Short name T1668
Test name
Test status
Simulation time 924433754 ps
CPU time 2.24 seconds
Started Jul 25 07:03:45 PM PDT 24
Finished Jul 25 07:03:48 PM PDT 24
Peak memory 207372 kb
Host smart-5b6b8580-bc89-4da2-a43a-9ccea99ce5f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28469
85081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.2846985081
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.637493338
Short name T1561
Test name
Test status
Simulation time 240872702 ps
CPU time 2.41 seconds
Started Jul 25 07:03:46 PM PDT 24
Finished Jul 25 07:03:49 PM PDT 24
Peak memory 207276 kb
Host smart-bc2aa8bf-9621-452b-9ca8-17298a3efd82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63749
3338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.637493338
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.2248819198
Short name T499
Test name
Test status
Simulation time 195032513 ps
CPU time 1.04 seconds
Started Jul 25 07:03:41 PM PDT 24
Finished Jul 25 07:03:43 PM PDT 24
Peak memory 215548 kb
Host smart-f24f6c26-17a3-497a-8055-a679d23cfdfc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2248819198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.2248819198
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.3345986144
Short name T1364
Test name
Test status
Simulation time 158976635 ps
CPU time 0.88 seconds
Started Jul 25 07:03:43 PM PDT 24
Finished Jul 25 07:03:44 PM PDT 24
Peak memory 207092 kb
Host smart-bef56403-e35e-44f9-9cf6-2bbbc9e757b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33459
86144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.3345986144
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.573618613
Short name T1113
Test name
Test status
Simulation time 233224887 ps
CPU time 1.05 seconds
Started Jul 25 07:03:47 PM PDT 24
Finished Jul 25 07:03:48 PM PDT 24
Peak memory 207116 kb
Host smart-60373910-e7ad-4307-9c0f-89c02bc143ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57361
8613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.573618613
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.2842055582
Short name T2727
Test name
Test status
Simulation time 8812251027 ps
CPU time 84.69 seconds
Started Jul 25 07:03:42 PM PDT 24
Finished Jul 25 07:05:07 PM PDT 24
Peak memory 215608 kb
Host smart-29ff2f8b-d170-44ca-91bc-86a471511b62
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2842055582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.2842055582
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_iso_retraction.2866906510
Short name T2341
Test name
Test status
Simulation time 5952844773 ps
CPU time 73.21 seconds
Started Jul 25 07:03:35 PM PDT 24
Finished Jul 25 07:04:48 PM PDT 24
Peak memory 207360 kb
Host smart-2ca1c998-8932-4a3d-82e2-01bdf89c6e68
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2866906510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.2866906510
Directory /workspace/15.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.2884084190
Short name T2242
Test name
Test status
Simulation time 220117263 ps
CPU time 0.96 seconds
Started Jul 25 07:03:37 PM PDT 24
Finished Jul 25 07:03:38 PM PDT 24
Peak memory 207108 kb
Host smart-b88acd1e-718e-49ff-9e94-7de76673e0c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28840
84190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.2884084190
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.1904779127
Short name T989
Test name
Test status
Simulation time 23321126372 ps
CPU time 28.92 seconds
Started Jul 25 07:03:47 PM PDT 24
Finished Jul 25 07:04:16 PM PDT 24
Peak memory 207364 kb
Host smart-e39cc9bd-286a-4ab1-9682-93bfa7840412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19047
79127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.1904779127
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.3477136477
Short name T2722
Test name
Test status
Simulation time 3362369283 ps
CPU time 4.78 seconds
Started Jul 25 07:03:37 PM PDT 24
Finished Jul 25 07:03:42 PM PDT 24
Peak memory 207476 kb
Host smart-49b5dacb-f57a-4379-bc7f-0af706f3600d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34771
36477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.3477136477
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.154834611
Short name T1292
Test name
Test status
Simulation time 4257633382 ps
CPU time 127.48 seconds
Started Jul 25 07:03:42 PM PDT 24
Finished Jul 25 07:05:50 PM PDT 24
Peak memory 215584 kb
Host smart-e04e4ba7-cd1d-420a-aca3-967e65746be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15483
4611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.154834611
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.1223381145
Short name T1199
Test name
Test status
Simulation time 3672202810 ps
CPU time 104.12 seconds
Started Jul 25 07:03:37 PM PDT 24
Finished Jul 25 07:05:21 PM PDT 24
Peak memory 215584 kb
Host smart-8f5a0557-4516-4540-9e22-76a32d79cf5c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1223381145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.1223381145
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.2644240164
Short name T837
Test name
Test status
Simulation time 269179061 ps
CPU time 0.97 seconds
Started Jul 25 07:03:36 PM PDT 24
Finished Jul 25 07:03:37 PM PDT 24
Peak memory 207160 kb
Host smart-d596cba0-eb1f-4a6b-a3d6-d2e2e7fdc6af
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2644240164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.2644240164
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.1415650688
Short name T2420
Test name
Test status
Simulation time 213433670 ps
CPU time 0.98 seconds
Started Jul 25 07:03:46 PM PDT 24
Finished Jul 25 07:03:47 PM PDT 24
Peak memory 207172 kb
Host smart-0b58c9fb-4a16-420d-8d7f-74b5677cd1bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14156
50688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.1415650688
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.332488801
Short name T2074
Test name
Test status
Simulation time 6350882129 ps
CPU time 64.41 seconds
Started Jul 25 07:03:36 PM PDT 24
Finished Jul 25 07:04:41 PM PDT 24
Peak memory 217116 kb
Host smart-71bee8d6-1f40-466b-a03c-ad68480622e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33248
8801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.332488801
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.2944871338
Short name T2521
Test name
Test status
Simulation time 6259373346 ps
CPU time 174.36 seconds
Started Jul 25 07:03:47 PM PDT 24
Finished Jul 25 07:06:41 PM PDT 24
Peak memory 215604 kb
Host smart-46bb66f3-650f-445e-a877-17d72b73a9bc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2944871338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.2944871338
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.1797164715
Short name T2228
Test name
Test status
Simulation time 166869232 ps
CPU time 0.87 seconds
Started Jul 25 07:03:42 PM PDT 24
Finished Jul 25 07:03:44 PM PDT 24
Peak memory 207132 kb
Host smart-d68b1267-1af7-4cb6-883e-d809793c35b7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1797164715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.1797164715
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.3855797345
Short name T2854
Test name
Test status
Simulation time 143085108 ps
CPU time 0.8 seconds
Started Jul 25 07:03:37 PM PDT 24
Finished Jul 25 07:03:38 PM PDT 24
Peak memory 207104 kb
Host smart-573b1f3e-b36a-4e3b-9ad7-3a0a00ee1911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38557
97345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.3855797345
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.3931718445
Short name T146
Test name
Test status
Simulation time 170559705 ps
CPU time 0.88 seconds
Started Jul 25 07:03:36 PM PDT 24
Finished Jul 25 07:03:37 PM PDT 24
Peak memory 207176 kb
Host smart-44744646-b08e-4c2a-bbfa-24b2489a92a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39317
18445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.3931718445
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.2162917032
Short name T2480
Test name
Test status
Simulation time 188436705 ps
CPU time 0.94 seconds
Started Jul 25 07:03:35 PM PDT 24
Finished Jul 25 07:03:36 PM PDT 24
Peak memory 207128 kb
Host smart-322ab569-0c08-436d-968f-c01c5b988fcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21629
17032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.2162917032
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.3719057038
Short name T1451
Test name
Test status
Simulation time 168242741 ps
CPU time 0.87 seconds
Started Jul 25 07:03:45 PM PDT 24
Finished Jul 25 07:03:46 PM PDT 24
Peak memory 207124 kb
Host smart-e4f83958-3277-48e4-84d2-6975f4948eb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37190
57038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.3719057038
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.3055552581
Short name T1520
Test name
Test status
Simulation time 173963611 ps
CPU time 0.89 seconds
Started Jul 25 07:03:45 PM PDT 24
Finished Jul 25 07:03:47 PM PDT 24
Peak memory 207136 kb
Host smart-03323bd6-1ebe-4f76-a024-a1dee13a4706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30555
52581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.3055552581
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.2984819827
Short name T186
Test name
Test status
Simulation time 165079693 ps
CPU time 0.88 seconds
Started Jul 25 07:03:41 PM PDT 24
Finished Jul 25 07:03:42 PM PDT 24
Peak memory 207144 kb
Host smart-d5a51dda-d495-4cda-a277-32c62e3c2e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29848
19827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.2984819827
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.4246962707
Short name T512
Test name
Test status
Simulation time 225676854 ps
CPU time 1.06 seconds
Started Jul 25 07:03:36 PM PDT 24
Finished Jul 25 07:03:37 PM PDT 24
Peak memory 207144 kb
Host smart-56e6aab6-7da0-4179-897e-5cbe1100eafc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4246962707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.4246962707
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.4025388779
Short name T381
Test name
Test status
Simulation time 147917165 ps
CPU time 0.84 seconds
Started Jul 25 07:03:46 PM PDT 24
Finished Jul 25 07:03:47 PM PDT 24
Peak memory 207112 kb
Host smart-db2ae662-7932-45c1-a966-241505bc0ca2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40253
88779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.4025388779
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.3944343168
Short name T926
Test name
Test status
Simulation time 37944350 ps
CPU time 0.73 seconds
Started Jul 25 07:03:41 PM PDT 24
Finished Jul 25 07:03:42 PM PDT 24
Peak memory 207116 kb
Host smart-4488511d-a328-4560-ac94-cc7a3cfcb2ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39443
43168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.3944343168
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.493635358
Short name T2130
Test name
Test status
Simulation time 14739105829 ps
CPU time 39.96 seconds
Started Jul 25 07:03:48 PM PDT 24
Finished Jul 25 07:04:28 PM PDT 24
Peak memory 215616 kb
Host smart-be558f2e-6b0b-472e-9ad7-a3c289803e86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49363
5358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.493635358
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.4191780777
Short name T1886
Test name
Test status
Simulation time 160428626 ps
CPU time 0.91 seconds
Started Jul 25 07:03:46 PM PDT 24
Finished Jul 25 07:03:47 PM PDT 24
Peak memory 207120 kb
Host smart-0b334a5b-b9b9-402d-b1eb-7e8585bd9e42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41917
80777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.4191780777
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.3149650382
Short name T644
Test name
Test status
Simulation time 214854081 ps
CPU time 1.07 seconds
Started Jul 25 07:03:47 PM PDT 24
Finished Jul 25 07:03:48 PM PDT 24
Peak memory 207156 kb
Host smart-e9753744-edbe-4ddc-89c3-985cc0dccf2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31496
50382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.3149650382
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.3140037777
Short name T1332
Test name
Test status
Simulation time 235328975 ps
CPU time 0.97 seconds
Started Jul 25 07:03:48 PM PDT 24
Finished Jul 25 07:03:50 PM PDT 24
Peak memory 207112 kb
Host smart-19613bf2-ebf3-4a8b-886e-e99c9e16f0e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31400
37777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.3140037777
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.3449197338
Short name T1205
Test name
Test status
Simulation time 151822871 ps
CPU time 0.86 seconds
Started Jul 25 07:03:41 PM PDT 24
Finished Jul 25 07:03:42 PM PDT 24
Peak memory 207152 kb
Host smart-fa300a93-1103-4966-a604-ae06b812cf72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34491
97338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.3449197338
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.2604648078
Short name T1640
Test name
Test status
Simulation time 144063253 ps
CPU time 0.83 seconds
Started Jul 25 07:03:48 PM PDT 24
Finished Jul 25 07:03:49 PM PDT 24
Peak memory 207128 kb
Host smart-2c52f10c-e0ca-470a-8074-04cb8188d646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26046
48078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.2604648078
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.701206886
Short name T1940
Test name
Test status
Simulation time 201101126 ps
CPU time 0.97 seconds
Started Jul 25 07:03:51 PM PDT 24
Finished Jul 25 07:03:53 PM PDT 24
Peak memory 207032 kb
Host smart-f20b9b21-28bc-41f3-9db7-93c6ab531d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70120
6886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.701206886
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.2567419830
Short name T1597
Test name
Test status
Simulation time 163191028 ps
CPU time 0.91 seconds
Started Jul 25 07:03:48 PM PDT 24
Finished Jul 25 07:03:50 PM PDT 24
Peak memory 207116 kb
Host smart-8272c5e3-56f4-480e-ab7c-9108b641cd45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25674
19830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.2567419830
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.3191563756
Short name T1325
Test name
Test status
Simulation time 253539641 ps
CPU time 1.05 seconds
Started Jul 25 07:03:44 PM PDT 24
Finished Jul 25 07:03:45 PM PDT 24
Peak memory 207132 kb
Host smart-9a1dc7eb-5717-42bd-ba28-d0e2f9e56113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31915
63756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.3191563756
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.276343913
Short name T1473
Test name
Test status
Simulation time 4692160306 ps
CPU time 136.84 seconds
Started Jul 25 07:03:46 PM PDT 24
Finished Jul 25 07:06:03 PM PDT 24
Peak memory 215656 kb
Host smart-adb5c269-e1f8-4177-8d6d-3257a5363389
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=276343913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.276343913
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.343134713
Short name T2031
Test name
Test status
Simulation time 181290635 ps
CPU time 0.91 seconds
Started Jul 25 07:03:46 PM PDT 24
Finished Jul 25 07:03:47 PM PDT 24
Peak memory 207196 kb
Host smart-016d64a7-6ccb-446d-b6b1-a165d6e5c05e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34313
4713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.343134713
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.2070062253
Short name T1055
Test name
Test status
Simulation time 173762818 ps
CPU time 0.86 seconds
Started Jul 25 07:03:48 PM PDT 24
Finished Jul 25 07:03:49 PM PDT 24
Peak memory 207128 kb
Host smart-92e51107-afec-4628-af6e-47c50dc6d87b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20700
62253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.2070062253
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.543913078
Short name T465
Test name
Test status
Simulation time 1084841137 ps
CPU time 2.59 seconds
Started Jul 25 07:03:44 PM PDT 24
Finished Jul 25 07:03:47 PM PDT 24
Peak memory 207280 kb
Host smart-5afc5f78-e203-4670-9098-24c0dae0f5a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54391
3078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.543913078
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.1566987025
Short name T754
Test name
Test status
Simulation time 6446871583 ps
CPU time 65.83 seconds
Started Jul 25 07:03:49 PM PDT 24
Finished Jul 25 07:04:55 PM PDT 24
Peak memory 207428 kb
Host smart-77036a2d-d522-4103-aa32-b1775b3d9803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15669
87025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.1566987025
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_timeout_missing_host_handshake.744749339
Short name T780
Test name
Test status
Simulation time 434931319 ps
CPU time 7.83 seconds
Started Jul 25 07:03:38 PM PDT 24
Finished Jul 25 07:03:46 PM PDT 24
Peak memory 207412 kb
Host smart-2f0fbf39-98c8-4fef-9bfd-aa3b0858ff8f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744749339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_timeout_missing_host
_handshake.744749339
Directory /workspace/15.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.1088756849
Short name T1245
Test name
Test status
Simulation time 98579617 ps
CPU time 0.73 seconds
Started Jul 25 07:03:57 PM PDT 24
Finished Jul 25 07:03:58 PM PDT 24
Peak memory 207144 kb
Host smart-9ed7977f-c1c8-46d2-a8b3-c9198951dc24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1088756849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.1088756849
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.1352249356
Short name T559
Test name
Test status
Simulation time 13528031409 ps
CPU time 15.82 seconds
Started Jul 25 07:03:48 PM PDT 24
Finished Jul 25 07:04:04 PM PDT 24
Peak memory 207396 kb
Host smart-3010eda9-d63c-4323-a614-d14fbb2705af
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352249356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.1352249356
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.2418897376
Short name T10
Test name
Test status
Simulation time 23456426462 ps
CPU time 28.89 seconds
Started Jul 25 07:03:49 PM PDT 24
Finished Jul 25 07:04:18 PM PDT 24
Peak memory 207360 kb
Host smart-dcc732d4-0d80-472c-8350-013227288d78
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418897376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_a
on_wake_resume.2418897376
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.3410158095
Short name T2691
Test name
Test status
Simulation time 170506525 ps
CPU time 0.89 seconds
Started Jul 25 07:03:49 PM PDT 24
Finished Jul 25 07:03:51 PM PDT 24
Peak memory 207144 kb
Host smart-135ddfb4-236d-44c8-933a-7abad06c0a6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34101
58095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.3410158095
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.3946736933
Short name T1969
Test name
Test status
Simulation time 145619654 ps
CPU time 0.8 seconds
Started Jul 25 07:03:46 PM PDT 24
Finished Jul 25 07:03:47 PM PDT 24
Peak memory 207020 kb
Host smart-2dfcfd7c-9832-4508-8bac-656d1b7ccc70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39467
36933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.3946736933
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.2592839652
Short name T1568
Test name
Test status
Simulation time 251865371 ps
CPU time 1.02 seconds
Started Jul 25 07:03:46 PM PDT 24
Finished Jul 25 07:03:47 PM PDT 24
Peak memory 207112 kb
Host smart-7912c315-dc94-4fa1-9fe0-429c400d60c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25928
39652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.2592839652
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.3787728241
Short name T2505
Test name
Test status
Simulation time 1277120173 ps
CPU time 3.38 seconds
Started Jul 25 07:03:48 PM PDT 24
Finished Jul 25 07:03:52 PM PDT 24
Peak memory 207396 kb
Host smart-e627cff6-fd90-4aad-bc78-413d5b23a47d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3787728241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.3787728241
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.1018896501
Short name T2466
Test name
Test status
Simulation time 20427350493 ps
CPU time 42 seconds
Started Jul 25 07:03:45 PM PDT 24
Finished Jul 25 07:04:27 PM PDT 24
Peak memory 207440 kb
Host smart-7ff75ed4-0a2a-4fe6-9b29-321e41b388b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10188
96501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.1018896501
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_device_timeout.1152285056
Short name T366
Test name
Test status
Simulation time 2484343473 ps
CPU time 22.09 seconds
Started Jul 25 07:03:51 PM PDT 24
Finished Jul 25 07:04:14 PM PDT 24
Peak memory 207420 kb
Host smart-afb167fb-b930-4df2-8f5e-dc1599998bdb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152285056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_timeout.1152285056
Directory /workspace/16.usbdev_device_timeout/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.119320004
Short name T1727
Test name
Test status
Simulation time 383548289 ps
CPU time 1.34 seconds
Started Jul 25 07:03:48 PM PDT 24
Finished Jul 25 07:03:50 PM PDT 24
Peak memory 207116 kb
Host smart-29b243fd-d393-4a86-9d22-61f72721f072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11932
0004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.119320004
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.2093758438
Short name T1552
Test name
Test status
Simulation time 157393094 ps
CPU time 0.84 seconds
Started Jul 25 07:03:48 PM PDT 24
Finished Jul 25 07:03:49 PM PDT 24
Peak memory 207120 kb
Host smart-30813320-39d1-431c-bdfb-a50867ec3fa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20937
58438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.2093758438
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.1251893487
Short name T47
Test name
Test status
Simulation time 30086588 ps
CPU time 0.75 seconds
Started Jul 25 07:03:51 PM PDT 24
Finished Jul 25 07:03:52 PM PDT 24
Peak memory 207152 kb
Host smart-16ab1923-d386-45e5-b4f2-c59e4223eef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12518
93487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.1251893487
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.3551680470
Short name T2539
Test name
Test status
Simulation time 922873002 ps
CPU time 2.31 seconds
Started Jul 25 07:03:43 PM PDT 24
Finished Jul 25 07:03:45 PM PDT 24
Peak memory 207412 kb
Host smart-28f1d7bb-6eaf-411a-9d7c-7eea36b7991d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35516
80470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.3551680470
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.2923598461
Short name T200
Test name
Test status
Simulation time 268164467 ps
CPU time 2.31 seconds
Started Jul 25 07:03:50 PM PDT 24
Finished Jul 25 07:03:52 PM PDT 24
Peak memory 207312 kb
Host smart-a1167ff3-1d40-4505-afa4-f8d34c5b452e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29235
98461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.2923598461
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.3266317033
Short name T460
Test name
Test status
Simulation time 251290486 ps
CPU time 1.19 seconds
Started Jul 25 07:03:50 PM PDT 24
Finished Jul 25 07:03:52 PM PDT 24
Peak memory 207324 kb
Host smart-d17dcc8f-7224-4886-abec-205a673c1e08
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3266317033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.3266317033
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.2758641588
Short name T395
Test name
Test status
Simulation time 142808856 ps
CPU time 0.88 seconds
Started Jul 25 07:03:51 PM PDT 24
Finished Jul 25 07:03:52 PM PDT 24
Peak memory 207180 kb
Host smart-77c10896-e486-4603-888f-d2f8f0a013aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27586
41588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.2758641588
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.2730615333
Short name T2161
Test name
Test status
Simulation time 241821685 ps
CPU time 1 seconds
Started Jul 25 07:03:45 PM PDT 24
Finished Jul 25 07:03:46 PM PDT 24
Peak memory 207120 kb
Host smart-4f33b040-eff2-4986-a7de-805a5a2e44a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27306
15333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.2730615333
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.2809596676
Short name T1243
Test name
Test status
Simulation time 7247454469 ps
CPU time 74.36 seconds
Started Jul 25 07:03:49 PM PDT 24
Finished Jul 25 07:05:04 PM PDT 24
Peak memory 215608 kb
Host smart-c52cbb3f-b5a1-40c5-a667-94c06a05a170
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2809596676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.2809596676
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/16.usbdev_iso_retraction.3962122150
Short name T1968
Test name
Test status
Simulation time 13661177634 ps
CPU time 98.47 seconds
Started Jul 25 07:03:46 PM PDT 24
Finished Jul 25 07:05:25 PM PDT 24
Peak memory 207364 kb
Host smart-6ea189d4-cd2c-4559-a847-f96ea3d8bce4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3962122150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.3962122150
Directory /workspace/16.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.3663481985
Short name T951
Test name
Test status
Simulation time 211344270 ps
CPU time 1 seconds
Started Jul 25 07:03:51 PM PDT 24
Finished Jul 25 07:03:53 PM PDT 24
Peak memory 207120 kb
Host smart-014627cb-354e-4283-a61d-dd3cdbe7420f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36634
81985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.3663481985
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.3674606023
Short name T2702
Test name
Test status
Simulation time 23326076682 ps
CPU time 28.62 seconds
Started Jul 25 07:03:51 PM PDT 24
Finished Jul 25 07:04:20 PM PDT 24
Peak memory 207304 kb
Host smart-16023676-d8af-4d83-a9e1-b313fdc193c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36746
06023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.3674606023
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.2255443526
Short name T1495
Test name
Test status
Simulation time 3267587193 ps
CPU time 4.99 seconds
Started Jul 25 07:03:46 PM PDT 24
Finished Jul 25 07:03:52 PM PDT 24
Peak memory 207300 kb
Host smart-0de827f1-19da-4dbe-a4a3-c72aec07d126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22554
43526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.2255443526
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.2790589987
Short name T2522
Test name
Test status
Simulation time 8646311743 ps
CPU time 258.7 seconds
Started Jul 25 07:03:46 PM PDT 24
Finished Jul 25 07:08:05 PM PDT 24
Peak memory 215576 kb
Host smart-186fd774-8346-48d0-b7fc-7c05ffe6ae3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27905
89987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.2790589987
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.1396491998
Short name T2301
Test name
Test status
Simulation time 4125232852 ps
CPU time 40.47 seconds
Started Jul 25 07:03:46 PM PDT 24
Finished Jul 25 07:04:27 PM PDT 24
Peak memory 207416 kb
Host smart-90c8a7e4-0cac-4446-b1fd-c3ea32c8871d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1396491998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.1396491998
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.2748273154
Short name T1822
Test name
Test status
Simulation time 244996417 ps
CPU time 0.99 seconds
Started Jul 25 07:03:45 PM PDT 24
Finished Jul 25 07:03:46 PM PDT 24
Peak memory 207116 kb
Host smart-bfe353d8-9940-4718-b334-cf9f6b15ac22
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2748273154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.2748273154
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.3705834879
Short name T1997
Test name
Test status
Simulation time 197297675 ps
CPU time 0.92 seconds
Started Jul 25 07:03:46 PM PDT 24
Finished Jul 25 07:03:47 PM PDT 24
Peak memory 207128 kb
Host smart-929cb818-64aa-4347-8b87-b87ae2093793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37058
34879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.3705834879
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.1781426541
Short name T2434
Test name
Test status
Simulation time 5229683831 ps
CPU time 154.2 seconds
Started Jul 25 07:03:47 PM PDT 24
Finished Jul 25 07:06:22 PM PDT 24
Peak memory 215548 kb
Host smart-4f965aa8-0c61-4728-ad2b-a2e4927eb098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17814
26541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.1781426541
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.2386190536
Short name T2496
Test name
Test status
Simulation time 5008933122 ps
CPU time 37.84 seconds
Started Jul 25 07:03:49 PM PDT 24
Finished Jul 25 07:04:27 PM PDT 24
Peak memory 217108 kb
Host smart-ab33c563-d34d-427c-8c85-5d929b72ea90
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2386190536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.2386190536
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.3333698852
Short name T1885
Test name
Test status
Simulation time 156571471 ps
CPU time 0.91 seconds
Started Jul 25 07:03:47 PM PDT 24
Finished Jul 25 07:03:48 PM PDT 24
Peak memory 207152 kb
Host smart-bc6dc44c-c2be-4715-9fb5-3bb2471f1457
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3333698852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.3333698852
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.4042000714
Short name T1296
Test name
Test status
Simulation time 151856731 ps
CPU time 0.84 seconds
Started Jul 25 07:03:47 PM PDT 24
Finished Jul 25 07:03:48 PM PDT 24
Peak memory 207140 kb
Host smart-085c84f8-d04f-42ca-9c01-9711ad6e391c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40420
00714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.4042000714
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.2057182155
Short name T2356
Test name
Test status
Simulation time 179052018 ps
CPU time 0.88 seconds
Started Jul 25 07:03:50 PM PDT 24
Finished Jul 25 07:03:51 PM PDT 24
Peak memory 207132 kb
Host smart-95920b8b-e997-4015-a01b-df78a4013661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20571
82155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.2057182155
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.2390336244
Short name T565
Test name
Test status
Simulation time 209551076 ps
CPU time 0.94 seconds
Started Jul 25 07:03:51 PM PDT 24
Finished Jul 25 07:03:53 PM PDT 24
Peak memory 207120 kb
Host smart-5652bb64-5e2b-40d8-9bbc-3cee7e8ba981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23903
36244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.2390336244
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.1112269822
Short name T2166
Test name
Test status
Simulation time 160093472 ps
CPU time 0.88 seconds
Started Jul 25 07:03:51 PM PDT 24
Finished Jul 25 07:03:52 PM PDT 24
Peak memory 207196 kb
Host smart-fd8ae7ff-1b49-4a5a-8ad9-605bff0cd76b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11122
69822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.1112269822
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.2462503079
Short name T618
Test name
Test status
Simulation time 208961089 ps
CPU time 0.96 seconds
Started Jul 25 07:03:46 PM PDT 24
Finished Jul 25 07:03:47 PM PDT 24
Peak memory 207152 kb
Host smart-d8f6458c-8612-422c-832e-35c564f97e54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24625
03079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.2462503079
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.1930406510
Short name T2531
Test name
Test status
Simulation time 253232205 ps
CPU time 1.17 seconds
Started Jul 25 07:03:47 PM PDT 24
Finished Jul 25 07:03:48 PM PDT 24
Peak memory 207120 kb
Host smart-8aeffcd0-0507-418f-86ef-56187d0e4478
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1930406510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.1930406510
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.3102959464
Short name T648
Test name
Test status
Simulation time 154790126 ps
CPU time 0.86 seconds
Started Jul 25 07:03:50 PM PDT 24
Finished Jul 25 07:03:51 PM PDT 24
Peak memory 207092 kb
Host smart-de275f9e-6d7d-408e-b0aa-4a32b5308f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31029
59464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.3102959464
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.2187613713
Short name T2029
Test name
Test status
Simulation time 83866731 ps
CPU time 0.73 seconds
Started Jul 25 07:03:52 PM PDT 24
Finished Jul 25 07:03:53 PM PDT 24
Peak memory 207092 kb
Host smart-39f0ecce-9665-4492-b622-f283e1de70ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21876
13713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.2187613713
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.1529339423
Short name T294
Test name
Test status
Simulation time 9714428655 ps
CPU time 25.48 seconds
Started Jul 25 07:03:49 PM PDT 24
Finished Jul 25 07:04:14 PM PDT 24
Peak memory 215616 kb
Host smart-f4436f09-8daf-4266-be96-cb44daa93319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15293
39423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.1529339423
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.2531915230
Short name T845
Test name
Test status
Simulation time 174055615 ps
CPU time 0.89 seconds
Started Jul 25 07:03:44 PM PDT 24
Finished Jul 25 07:03:45 PM PDT 24
Peak memory 207140 kb
Host smart-2205d7e6-4387-4cd9-9acc-93dce1d6a534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25319
15230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.2531915230
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.3686513074
Short name T2337
Test name
Test status
Simulation time 233783839 ps
CPU time 0.97 seconds
Started Jul 25 07:03:50 PM PDT 24
Finished Jul 25 07:03:51 PM PDT 24
Peak memory 207108 kb
Host smart-e2553ad8-7d50-45f4-a5c7-b9d3d8e5125f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36865
13074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.3686513074
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.1418653576
Short name T2394
Test name
Test status
Simulation time 212824901 ps
CPU time 0.98 seconds
Started Jul 25 07:03:48 PM PDT 24
Finished Jul 25 07:03:49 PM PDT 24
Peak memory 207192 kb
Host smart-90aef2f3-5559-4e7e-bb35-820a5f15537a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14186
53576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.1418653576
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.2351787164
Short name T2641
Test name
Test status
Simulation time 182264617 ps
CPU time 0.94 seconds
Started Jul 25 07:03:50 PM PDT 24
Finished Jul 25 07:03:51 PM PDT 24
Peak memory 207152 kb
Host smart-9263491b-c52d-471b-a22e-34ac91c211d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23517
87164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.2351787164
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.1491309039
Short name T1435
Test name
Test status
Simulation time 152068108 ps
CPU time 0.82 seconds
Started Jul 25 07:03:45 PM PDT 24
Finished Jul 25 07:03:45 PM PDT 24
Peak memory 207080 kb
Host smart-4c7c152d-ce31-46b7-be45-74ebb8026b6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14913
09039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.1491309039
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.658414588
Short name T2417
Test name
Test status
Simulation time 158760536 ps
CPU time 0.83 seconds
Started Jul 25 07:04:34 PM PDT 24
Finished Jul 25 07:04:35 PM PDT 24
Peak memory 207096 kb
Host smart-7b7eec08-23eb-4742-a517-79f50482236d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65841
4588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.658414588
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.1858736761
Short name T1818
Test name
Test status
Simulation time 143830920 ps
CPU time 0.82 seconds
Started Jul 25 07:03:52 PM PDT 24
Finished Jul 25 07:03:53 PM PDT 24
Peak memory 207132 kb
Host smart-b86ef366-ccb8-46d9-8800-8828b04e1e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18587
36761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.1858736761
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.3793911748
Short name T1132
Test name
Test status
Simulation time 268419271 ps
CPU time 1.06 seconds
Started Jul 25 07:03:52 PM PDT 24
Finished Jul 25 07:03:53 PM PDT 24
Peak memory 207128 kb
Host smart-2f7d603f-c798-4136-8dd8-9ef36b2ea1d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37939
11748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.3793911748
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.2678688300
Short name T737
Test name
Test status
Simulation time 4504275077 ps
CPU time 32.79 seconds
Started Jul 25 07:03:49 PM PDT 24
Finished Jul 25 07:04:22 PM PDT 24
Peak memory 217216 kb
Host smart-a8535831-d37e-4aea-9084-6fffc684e955
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2678688300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.2678688300
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.2756344751
Short name T479
Test name
Test status
Simulation time 169321160 ps
CPU time 0.88 seconds
Started Jul 25 07:03:50 PM PDT 24
Finished Jul 25 07:03:51 PM PDT 24
Peak memory 207156 kb
Host smart-2748f866-54a9-467f-8d20-e96936ff9d0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27563
44751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.2756344751
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.1748660005
Short name T1491
Test name
Test status
Simulation time 208263357 ps
CPU time 1.05 seconds
Started Jul 25 07:03:50 PM PDT 24
Finished Jul 25 07:03:51 PM PDT 24
Peak memory 207108 kb
Host smart-2e642361-efe6-4df3-910f-e667ac928e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17486
60005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.1748660005
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.3764569579
Short name T1416
Test name
Test status
Simulation time 386991127 ps
CPU time 1.34 seconds
Started Jul 25 07:03:54 PM PDT 24
Finished Jul 25 07:03:55 PM PDT 24
Peak memory 207132 kb
Host smart-805e23c0-7cb1-4249-b8d6-91a22cb26410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37645
69579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.3764569579
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.2685277319
Short name T616
Test name
Test status
Simulation time 6683794075 ps
CPU time 190.49 seconds
Started Jul 25 07:03:55 PM PDT 24
Finished Jul 25 07:07:05 PM PDT 24
Peak memory 215576 kb
Host smart-677a6a3e-dcb9-41be-967e-91915a1de65c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26852
77319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.2685277319
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_timeout_missing_host_handshake.3643553811
Short name T2412
Test name
Test status
Simulation time 143609001 ps
CPU time 0.83 seconds
Started Jul 25 07:03:44 PM PDT 24
Finished Jul 25 07:03:45 PM PDT 24
Peak memory 207104 kb
Host smart-98f1a898-0964-467f-baea-d00fd098e4eb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643553811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_timeout_missing_hos
t_handshake.3643553811
Directory /workspace/16.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.1521820928
Short name T1465
Test name
Test status
Simulation time 37047416 ps
CPU time 0.67 seconds
Started Jul 25 07:04:04 PM PDT 24
Finished Jul 25 07:04:05 PM PDT 24
Peak memory 207176 kb
Host smart-6b04608b-6f5a-4b0f-9196-dc1bca184681
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1521820928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.1521820928
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.136197388
Short name T563
Test name
Test status
Simulation time 4196129044 ps
CPU time 6.54 seconds
Started Jul 25 07:04:03 PM PDT 24
Finished Jul 25 07:04:09 PM PDT 24
Peak memory 207392 kb
Host smart-2547a3a6-8353-4028-8f81-ff8fd3b6e1fa
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136197388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_ao
n_wake_disconnect.136197388
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.1321961248
Short name T1240
Test name
Test status
Simulation time 13376230744 ps
CPU time 15.45 seconds
Started Jul 25 07:03:57 PM PDT 24
Finished Jul 25 07:04:13 PM PDT 24
Peak memory 207424 kb
Host smart-6857dfb2-4b3b-403a-a5aa-a0f98c55657f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321961248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.1321961248
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.3144822088
Short name T1151
Test name
Test status
Simulation time 23453996209 ps
CPU time 28.94 seconds
Started Jul 25 07:03:55 PM PDT 24
Finished Jul 25 07:04:24 PM PDT 24
Peak memory 207400 kb
Host smart-819643e2-de20-449b-8680-d4e4133577a4
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144822088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_a
on_wake_resume.3144822088
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.2719185445
Short name T900
Test name
Test status
Simulation time 159070539 ps
CPU time 0.86 seconds
Started Jul 25 07:04:03 PM PDT 24
Finished Jul 25 07:04:04 PM PDT 24
Peak memory 207092 kb
Host smart-4558b39a-09f5-49ca-860c-8df8b40f7163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27191
85445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.2719185445
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.1666202640
Short name T932
Test name
Test status
Simulation time 161763336 ps
CPU time 0.83 seconds
Started Jul 25 07:04:04 PM PDT 24
Finished Jul 25 07:04:05 PM PDT 24
Peak memory 207076 kb
Host smart-6f2fbd4c-8a00-4423-87b8-1646db8cadfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16662
02640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.1666202640
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.3051266732
Short name T502
Test name
Test status
Simulation time 441032257 ps
CPU time 1.63 seconds
Started Jul 25 07:04:03 PM PDT 24
Finished Jul 25 07:04:05 PM PDT 24
Peak memory 207068 kb
Host smart-1ea2c0c8-8507-4185-8c5d-871942a8262a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30512
66732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.3051266732
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.4244479732
Short name T2475
Test name
Test status
Simulation time 1271548854 ps
CPU time 3.26 seconds
Started Jul 25 07:04:04 PM PDT 24
Finished Jul 25 07:04:07 PM PDT 24
Peak memory 207324 kb
Host smart-5e13e63d-f1b4-425c-97ec-6b400da31549
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4244479732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.4244479732
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.4088265367
Short name T2535
Test name
Test status
Simulation time 14560740818 ps
CPU time 33.48 seconds
Started Jul 25 07:03:54 PM PDT 24
Finished Jul 25 07:04:28 PM PDT 24
Peak memory 207396 kb
Host smart-d5d36ca3-c282-4ecd-a887-953e6367e3d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40882
65367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.4088265367
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_device_timeout.3661953961
Short name T1996
Test name
Test status
Simulation time 2249425970 ps
CPU time 14.04 seconds
Started Jul 25 07:04:06 PM PDT 24
Finished Jul 25 07:04:20 PM PDT 24
Peak memory 207376 kb
Host smart-e479f114-5ca6-44fb-993b-920caed2f8d1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661953961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_timeout.3661953961
Directory /workspace/17.usbdev_device_timeout/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.1683614791
Short name T1657
Test name
Test status
Simulation time 475899336 ps
CPU time 1.54 seconds
Started Jul 25 07:03:53 PM PDT 24
Finished Jul 25 07:03:55 PM PDT 24
Peak memory 207164 kb
Host smart-abc76b57-2b5c-466a-b418-36a7f332d500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16836
14791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.1683614791
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.3592657545
Short name T549
Test name
Test status
Simulation time 146455414 ps
CPU time 0.83 seconds
Started Jul 25 07:03:57 PM PDT 24
Finished Jul 25 07:03:59 PM PDT 24
Peak memory 207092 kb
Host smart-be40ea71-2990-4966-a404-31f27ab7970b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35926
57545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.3592657545
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.1003828938
Short name T701
Test name
Test status
Simulation time 28715174 ps
CPU time 0.67 seconds
Started Jul 25 07:03:56 PM PDT 24
Finished Jul 25 07:03:57 PM PDT 24
Peak memory 207092 kb
Host smart-64c24909-82e4-475a-bb25-144a0037e42f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10038
28938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.1003828938
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.917638283
Short name T503
Test name
Test status
Simulation time 975887393 ps
CPU time 2.31 seconds
Started Jul 25 07:03:52 PM PDT 24
Finished Jul 25 07:03:55 PM PDT 24
Peak memory 207304 kb
Host smart-edaf79e2-00a2-496b-83dd-c79e53d45d50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91763
8283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.917638283
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.1515579589
Short name T1892
Test name
Test status
Simulation time 308301899 ps
CPU time 2.18 seconds
Started Jul 25 07:04:03 PM PDT 24
Finished Jul 25 07:04:06 PM PDT 24
Peak memory 207228 kb
Host smart-d9724728-fe76-419e-8929-a9ab53290fbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15155
79589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.1515579589
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.2890203773
Short name T2584
Test name
Test status
Simulation time 181853509 ps
CPU time 1.06 seconds
Started Jul 25 07:04:03 PM PDT 24
Finished Jul 25 07:04:04 PM PDT 24
Peak memory 207336 kb
Host smart-e2ef3b88-3199-467c-bdb2-3a16d313855f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2890203773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.2890203773
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.1872587697
Short name T938
Test name
Test status
Simulation time 142812020 ps
CPU time 0.85 seconds
Started Jul 25 07:04:06 PM PDT 24
Finished Jul 25 07:04:07 PM PDT 24
Peak memory 207076 kb
Host smart-e8576f81-1214-48e0-98cb-f8c48ed6e2b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18725
87697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.1872587697
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.2588089374
Short name T1453
Test name
Test status
Simulation time 186910380 ps
CPU time 0.99 seconds
Started Jul 25 07:04:03 PM PDT 24
Finished Jul 25 07:04:04 PM PDT 24
Peak memory 207108 kb
Host smart-35dbcd39-c23c-4873-86dc-d741567f1014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25880
89374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.2588089374
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_iso_retraction.2015338615
Short name T1276
Test name
Test status
Simulation time 4812483821 ps
CPU time 32.55 seconds
Started Jul 25 07:03:56 PM PDT 24
Finished Jul 25 07:04:29 PM PDT 24
Peak memory 207340 kb
Host smart-92e37e0f-8062-4f11-8e08-eb0fac851250
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2015338615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.2015338615
Directory /workspace/17.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.3065498680
Short name T1293
Test name
Test status
Simulation time 264462389 ps
CPU time 1.04 seconds
Started Jul 25 07:04:05 PM PDT 24
Finished Jul 25 07:04:06 PM PDT 24
Peak memory 207108 kb
Host smart-8af2351c-a63d-4a36-8d3b-30f9a7ce37b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30654
98680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.3065498680
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.212761014
Short name T264
Test name
Test status
Simulation time 23364966216 ps
CPU time 33.22 seconds
Started Jul 25 07:03:55 PM PDT 24
Finished Jul 25 07:04:29 PM PDT 24
Peak memory 207372 kb
Host smart-11ffa487-441b-401c-aa8a-453b53bdd1ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21276
1014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.212761014
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.2505006384
Short name T1156
Test name
Test status
Simulation time 3381356082 ps
CPU time 4.59 seconds
Started Jul 25 07:03:57 PM PDT 24
Finished Jul 25 07:04:02 PM PDT 24
Peak memory 207488 kb
Host smart-745d66c3-a297-4c06-b673-af2381298047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25050
06384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.2505006384
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.3342314503
Short name T2745
Test name
Test status
Simulation time 7988506521 ps
CPU time 81.76 seconds
Started Jul 25 07:03:58 PM PDT 24
Finished Jul 25 07:05:20 PM PDT 24
Peak memory 217588 kb
Host smart-6f332f50-8aa2-48d6-93c7-85b3ba143619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33423
14503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.3342314503
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.2622607949
Short name T2814
Test name
Test status
Simulation time 2963445449 ps
CPU time 89.43 seconds
Started Jul 25 07:04:03 PM PDT 24
Finished Jul 25 07:05:32 PM PDT 24
Peak memory 215644 kb
Host smart-cc2b55ea-56e2-4d47-b5f6-0b888a45dcae
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2622607949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.2622607949
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.2393796720
Short name T1096
Test name
Test status
Simulation time 286765904 ps
CPU time 1.04 seconds
Started Jul 25 07:03:55 PM PDT 24
Finished Jul 25 07:03:56 PM PDT 24
Peak memory 207156 kb
Host smart-998d8df2-25f4-46a0-b912-62ba31334679
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2393796720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.2393796720
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.4086131168
Short name T2705
Test name
Test status
Simulation time 234646631 ps
CPU time 0.97 seconds
Started Jul 25 07:03:57 PM PDT 24
Finished Jul 25 07:03:58 PM PDT 24
Peak memory 207172 kb
Host smart-f97edd08-ec77-4aed-970b-00df33c8feab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40861
31168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.4086131168
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.4071330840
Short name T731
Test name
Test status
Simulation time 5093906685 ps
CPU time 150.47 seconds
Started Jul 25 07:04:05 PM PDT 24
Finished Jul 25 07:06:35 PM PDT 24
Peak memory 215588 kb
Host smart-793616a7-2aa2-49bf-a9ca-69fe4ef359af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40713
30840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.4071330840
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.694087698
Short name T2432
Test name
Test status
Simulation time 7024567085 ps
CPU time 208.01 seconds
Started Jul 25 07:04:02 PM PDT 24
Finished Jul 25 07:07:30 PM PDT 24
Peak memory 215648 kb
Host smart-9d83ef39-3138-4285-b779-fe107d0853f1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=694087698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.694087698
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.3815066786
Short name T1034
Test name
Test status
Simulation time 157086392 ps
CPU time 0.88 seconds
Started Jul 25 07:04:03 PM PDT 24
Finished Jul 25 07:04:04 PM PDT 24
Peak memory 207136 kb
Host smart-140c9bb1-4a69-45b4-951b-6c66fd9a5cd7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3815066786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.3815066786
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.2855489786
Short name T2285
Test name
Test status
Simulation time 149788556 ps
CPU time 0.81 seconds
Started Jul 25 07:03:56 PM PDT 24
Finished Jul 25 07:03:57 PM PDT 24
Peak memory 207260 kb
Host smart-68045fac-e040-45f0-bb57-f42fc23b5e54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28554
89786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.2855489786
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.4008867094
Short name T141
Test name
Test status
Simulation time 235381107 ps
CPU time 0.97 seconds
Started Jul 25 07:04:05 PM PDT 24
Finished Jul 25 07:04:06 PM PDT 24
Peak memory 207124 kb
Host smart-720cf4d0-09bd-42d0-b2c0-14fc97f7b72a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40088
67094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.4008867094
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.2395924147
Short name T1819
Test name
Test status
Simulation time 165401429 ps
CPU time 0.93 seconds
Started Jul 25 07:04:03 PM PDT 24
Finished Jul 25 07:04:04 PM PDT 24
Peak memory 207148 kb
Host smart-c9654d9e-544c-4f54-81d7-09b32f8d0a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23959
24147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.2395924147
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.782299378
Short name T2653
Test name
Test status
Simulation time 208491029 ps
CPU time 0.91 seconds
Started Jul 25 07:03:57 PM PDT 24
Finished Jul 25 07:03:58 PM PDT 24
Peak memory 207112 kb
Host smart-fd6d2f52-7adf-4768-8c6f-fa801460033c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78229
9378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.782299378
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.1622848537
Short name T534
Test name
Test status
Simulation time 172635590 ps
CPU time 0.97 seconds
Started Jul 25 07:03:57 PM PDT 24
Finished Jul 25 07:03:58 PM PDT 24
Peak memory 207120 kb
Host smart-8d44b4c6-9413-48c0-abcf-487c5269f345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16228
48537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.1622848537
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.1284656940
Short name T1220
Test name
Test status
Simulation time 149118616 ps
CPU time 0.85 seconds
Started Jul 25 07:04:02 PM PDT 24
Finished Jul 25 07:04:03 PM PDT 24
Peak memory 206452 kb
Host smart-02cdac72-e6e8-42f6-a866-a6647d80c02c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12846
56940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.1284656940
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.657667153
Short name T1938
Test name
Test status
Simulation time 225631413 ps
CPU time 1.08 seconds
Started Jul 25 07:04:03 PM PDT 24
Finished Jul 25 07:04:04 PM PDT 24
Peak memory 207108 kb
Host smart-11bd0edc-74be-43c1-8af6-9e7ff4c26857
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=657667153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.657667153
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.2420311210
Short name T2824
Test name
Test status
Simulation time 136232982 ps
CPU time 0.79 seconds
Started Jul 25 07:03:54 PM PDT 24
Finished Jul 25 07:03:55 PM PDT 24
Peak memory 207072 kb
Host smart-d1326412-eb09-4e1c-9c6d-754338d55a00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24203
11210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.2420311210
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.4100279557
Short name T1287
Test name
Test status
Simulation time 40290287 ps
CPU time 0.72 seconds
Started Jul 25 07:03:55 PM PDT 24
Finished Jul 25 07:03:56 PM PDT 24
Peak memory 207088 kb
Host smart-224fd203-9115-47eb-9de3-b092f24cf584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41002
79557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.4100279557
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.2269334176
Short name T1977
Test name
Test status
Simulation time 17172862263 ps
CPU time 39.26 seconds
Started Jul 25 07:04:04 PM PDT 24
Finished Jul 25 07:04:43 PM PDT 24
Peak memory 220376 kb
Host smart-9dbd438c-897b-4fa4-ac58-f52bbb515987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22693
34176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.2269334176
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.2368845801
Short name T831
Test name
Test status
Simulation time 175225701 ps
CPU time 0.92 seconds
Started Jul 25 07:04:03 PM PDT 24
Finished Jul 25 07:04:04 PM PDT 24
Peak memory 207072 kb
Host smart-f6bcbb07-0458-4ad0-a88d-520151d26711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23688
45801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.2368845801
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.378261353
Short name T2372
Test name
Test status
Simulation time 210430674 ps
CPU time 0.94 seconds
Started Jul 25 07:03:55 PM PDT 24
Finished Jul 25 07:03:56 PM PDT 24
Peak memory 207040 kb
Host smart-4fd6e1da-2000-4fba-8540-5b9589393fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37826
1353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.378261353
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.839437458
Short name T515
Test name
Test status
Simulation time 243079740 ps
CPU time 1.02 seconds
Started Jul 25 07:03:57 PM PDT 24
Finished Jul 25 07:03:59 PM PDT 24
Peak memory 207108 kb
Host smart-2f75b948-a29e-491c-a4d4-2df15afd7cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83943
7458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.839437458
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.1761660606
Short name T2415
Test name
Test status
Simulation time 167047260 ps
CPU time 0.86 seconds
Started Jul 25 07:03:57 PM PDT 24
Finished Jul 25 07:03:58 PM PDT 24
Peak memory 207192 kb
Host smart-adf64c9a-02e3-4e2c-b529-3320ccb8e63c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17616
60606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.1761660606
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.907576136
Short name T1011
Test name
Test status
Simulation time 177557481 ps
CPU time 0.88 seconds
Started Jul 25 07:04:06 PM PDT 24
Finished Jul 25 07:04:07 PM PDT 24
Peak memory 207124 kb
Host smart-a30b7aaa-2534-4747-9315-3f9c979372b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90757
6136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.907576136
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.1194970259
Short name T1136
Test name
Test status
Simulation time 149625572 ps
CPU time 0.82 seconds
Started Jul 25 07:03:56 PM PDT 24
Finished Jul 25 07:03:57 PM PDT 24
Peak memory 207228 kb
Host smart-990f562e-fc2e-4e1c-bd4c-77dca69ed756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11949
70259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.1194970259
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.731850962
Short name T1467
Test name
Test status
Simulation time 146860363 ps
CPU time 0.84 seconds
Started Jul 25 07:03:55 PM PDT 24
Finished Jul 25 07:03:56 PM PDT 24
Peak memory 207076 kb
Host smart-2a4ff02e-7eed-4afd-9e6d-89893cd32ceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73185
0962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.731850962
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.2048884225
Short name T2197
Test name
Test status
Simulation time 223289033 ps
CPU time 1.07 seconds
Started Jul 25 07:04:02 PM PDT 24
Finished Jul 25 07:04:04 PM PDT 24
Peak memory 206368 kb
Host smart-99256e35-4386-4f8b-9481-0364a9624eda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20488
84225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.2048884225
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.2290863003
Short name T1608
Test name
Test status
Simulation time 4995243822 ps
CPU time 39.92 seconds
Started Jul 25 07:03:57 PM PDT 24
Finished Jul 25 07:04:37 PM PDT 24
Peak memory 215620 kb
Host smart-b10f455b-743c-45be-8a07-48a529d60e65
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2290863003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.2290863003
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.1448907635
Short name T560
Test name
Test status
Simulation time 192998632 ps
CPU time 0.9 seconds
Started Jul 25 07:04:03 PM PDT 24
Finished Jul 25 07:04:04 PM PDT 24
Peak memory 207152 kb
Host smart-7c903996-b120-49c8-b5da-85c18ab934f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14489
07635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.1448907635
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.2109484738
Short name T1213
Test name
Test status
Simulation time 231145905 ps
CPU time 0.89 seconds
Started Jul 25 07:04:04 PM PDT 24
Finished Jul 25 07:04:05 PM PDT 24
Peak memory 207112 kb
Host smart-03882e23-e081-47e6-b3ba-78587cb8862e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21094
84738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.2109484738
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.2603254895
Short name T2256
Test name
Test status
Simulation time 487671474 ps
CPU time 1.45 seconds
Started Jul 25 07:04:04 PM PDT 24
Finished Jul 25 07:04:06 PM PDT 24
Peak memory 207064 kb
Host smart-ba856113-2756-4859-a449-265f824678f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26032
54895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.2603254895
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.1479762589
Short name T1609
Test name
Test status
Simulation time 4365755491 ps
CPU time 126.48 seconds
Started Jul 25 07:04:06 PM PDT 24
Finished Jul 25 07:06:12 PM PDT 24
Peak memory 215536 kb
Host smart-60b3f799-1bdd-4d90-be8a-8b5b3e2bea77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14797
62589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.1479762589
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_timeout_missing_host_handshake.1898126653
Short name T1077
Test name
Test status
Simulation time 643088027 ps
CPU time 5.19 seconds
Started Jul 25 07:04:03 PM PDT 24
Finished Jul 25 07:04:08 PM PDT 24
Peak memory 207316 kb
Host smart-2c2083b3-ce58-4aa2-9493-623a89dc10e9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898126653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_timeout_missing_hos
t_handshake.1898126653
Directory /workspace/17.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.3910120133
Short name T1776
Test name
Test status
Simulation time 113592508 ps
CPU time 0.75 seconds
Started Jul 25 07:04:16 PM PDT 24
Finished Jul 25 07:04:17 PM PDT 24
Peak memory 207140 kb
Host smart-a1b7271f-d3d0-4308-beb5-f48cebbb9bd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3910120133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.3910120133
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.776139679
Short name T2595
Test name
Test status
Simulation time 4185021110 ps
CPU time 6.21 seconds
Started Jul 25 07:04:05 PM PDT 24
Finished Jul 25 07:04:11 PM PDT 24
Peak memory 207364 kb
Host smart-887c48b8-aea8-4a35-a8ce-0bd8ed8ac8d2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776139679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_ao
n_wake_disconnect.776139679
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.1130448420
Short name T1615
Test name
Test status
Simulation time 13376922841 ps
CPU time 15.86 seconds
Started Jul 25 07:04:03 PM PDT 24
Finished Jul 25 07:04:19 PM PDT 24
Peak memory 207464 kb
Host smart-25c4fa1a-47cb-4940-b217-8c4c7e607fe8
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130448420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.1130448420
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.3498631426
Short name T2806
Test name
Test status
Simulation time 23380489308 ps
CPU time 29.9 seconds
Started Jul 25 07:04:03 PM PDT 24
Finished Jul 25 07:04:33 PM PDT 24
Peak memory 207376 kb
Host smart-08d57dd3-23a4-4daf-882d-0826c486493d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498631426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_a
on_wake_resume.3498631426
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.2551209798
Short name T1812
Test name
Test status
Simulation time 161322142 ps
CPU time 0.84 seconds
Started Jul 25 07:04:05 PM PDT 24
Finished Jul 25 07:04:06 PM PDT 24
Peak memory 207184 kb
Host smart-2c5aaa21-6df4-4863-a22d-36306da7d7a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25512
09798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.2551209798
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.2732143601
Short name T1139
Test name
Test status
Simulation time 189266943 ps
CPU time 0.87 seconds
Started Jul 25 07:04:10 PM PDT 24
Finished Jul 25 07:04:11 PM PDT 24
Peak memory 207036 kb
Host smart-f9e14246-a7fe-4219-987a-188260d8ef94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27321
43601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.2732143601
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.1906808538
Short name T1725
Test name
Test status
Simulation time 559478368 ps
CPU time 1.76 seconds
Started Jul 25 07:04:05 PM PDT 24
Finished Jul 25 07:04:07 PM PDT 24
Peak memory 207140 kb
Host smart-2a1e83e6-2006-4c48-94a0-434f6f223851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19068
08538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.1906808538
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.1117380307
Short name T1257
Test name
Test status
Simulation time 336513133 ps
CPU time 1.11 seconds
Started Jul 25 07:04:05 PM PDT 24
Finished Jul 25 07:04:06 PM PDT 24
Peak memory 207124 kb
Host smart-bc3ae873-272a-47f2-836f-4ba93ed6ae67
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1117380307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.1117380307
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.4271448405
Short name T2789
Test name
Test status
Simulation time 16308045554 ps
CPU time 40.29 seconds
Started Jul 25 07:04:05 PM PDT 24
Finished Jul 25 07:04:46 PM PDT 24
Peak memory 207284 kb
Host smart-e8167552-4d28-465c-a534-274c3ace2595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42714
48405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.4271448405
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_device_timeout.987055842
Short name T2365
Test name
Test status
Simulation time 1544896873 ps
CPU time 13.58 seconds
Started Jul 25 07:04:06 PM PDT 24
Finished Jul 25 07:04:20 PM PDT 24
Peak memory 207296 kb
Host smart-402311dc-8ebb-4625-b996-e256106105cd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987055842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_timeout.987055842
Directory /workspace/18.usbdev_device_timeout/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.1122053849
Short name T751
Test name
Test status
Simulation time 368454480 ps
CPU time 1.26 seconds
Started Jul 25 07:04:06 PM PDT 24
Finished Jul 25 07:04:08 PM PDT 24
Peak memory 207088 kb
Host smart-addbad96-76b7-41f6-9e42-7bbd7a20c973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11220
53849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.1122053849
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.1734047000
Short name T643
Test name
Test status
Simulation time 148799418 ps
CPU time 0.84 seconds
Started Jul 25 07:04:04 PM PDT 24
Finished Jul 25 07:04:05 PM PDT 24
Peak memory 207092 kb
Host smart-89157a10-bccc-492d-a923-c661bb835695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17340
47000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.1734047000
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.855557755
Short name T1941
Test name
Test status
Simulation time 47946808 ps
CPU time 0.78 seconds
Started Jul 25 07:04:07 PM PDT 24
Finished Jul 25 07:04:08 PM PDT 24
Peak memory 207068 kb
Host smart-4b2eec64-9b61-4e33-b2ca-0df4a8126855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85555
7755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.855557755
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.2027459090
Short name T1458
Test name
Test status
Simulation time 705752544 ps
CPU time 2.06 seconds
Started Jul 25 07:04:05 PM PDT 24
Finished Jul 25 07:04:07 PM PDT 24
Peak memory 207264 kb
Host smart-00dfee5a-6e48-458c-943f-2bcc2edd80be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20274
59090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.2027459090
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.44107195
Short name T2408
Test name
Test status
Simulation time 156846181 ps
CPU time 1.37 seconds
Started Jul 25 07:04:08 PM PDT 24
Finished Jul 25 07:04:09 PM PDT 24
Peak memory 207272 kb
Host smart-01da12c5-6c17-4e2a-a313-ebcab3070ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44107
195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.44107195
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.1161590955
Short name T2838
Test name
Test status
Simulation time 192402879 ps
CPU time 0.95 seconds
Started Jul 25 07:04:07 PM PDT 24
Finished Jul 25 07:04:08 PM PDT 24
Peak memory 215540 kb
Host smart-cb2ea1d8-98e7-48a8-8c22-b6b78ed8b465
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1161590955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.1161590955
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.333052652
Short name T2464
Test name
Test status
Simulation time 161594911 ps
CPU time 0.82 seconds
Started Jul 25 07:04:07 PM PDT 24
Finished Jul 25 07:04:08 PM PDT 24
Peak memory 207108 kb
Host smart-8252fd64-5926-4870-be76-e0b3cec8cbbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33305
2652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.333052652
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.3507132752
Short name T2078
Test name
Test status
Simulation time 207935577 ps
CPU time 0.9 seconds
Started Jul 25 07:04:05 PM PDT 24
Finished Jul 25 07:04:06 PM PDT 24
Peak memory 207188 kb
Host smart-8765ac1c-64e1-4fe1-b1d0-a7924874ac7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35071
32752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.3507132752
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.3455612540
Short name T1816
Test name
Test status
Simulation time 7711214236 ps
CPU time 82.99 seconds
Started Jul 25 07:04:06 PM PDT 24
Finished Jul 25 07:05:29 PM PDT 24
Peak memory 215604 kb
Host smart-93d1f3d7-1979-4f0e-bc7d-47fa406a9dc7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3455612540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.3455612540
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_iso_retraction.3058199260
Short name T117
Test name
Test status
Simulation time 8472713444 ps
CPU time 54.17 seconds
Started Jul 25 07:04:07 PM PDT 24
Finished Jul 25 07:05:01 PM PDT 24
Peak memory 207412 kb
Host smart-4afe2e34-77a2-41a9-8ece-a67fbd7d4b82
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3058199260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_iso_retraction.3058199260
Directory /workspace/18.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.4051606619
Short name T2490
Test name
Test status
Simulation time 240375621 ps
CPU time 1.03 seconds
Started Jul 25 07:04:10 PM PDT 24
Finished Jul 25 07:04:11 PM PDT 24
Peak memory 207068 kb
Host smart-ef2b1b73-ae6b-4a42-8a32-2fd6f89607b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40516
06619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.4051606619
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.1194342141
Short name T2004
Test name
Test status
Simulation time 23354045786 ps
CPU time 28.27 seconds
Started Jul 25 07:04:08 PM PDT 24
Finished Jul 25 07:04:37 PM PDT 24
Peak memory 207420 kb
Host smart-722bca4a-f61c-4109-9deb-24c8c882be91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11943
42141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.1194342141
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.3588473734
Short name T2138
Test name
Test status
Simulation time 3297248224 ps
CPU time 5.25 seconds
Started Jul 25 07:04:05 PM PDT 24
Finished Jul 25 07:04:11 PM PDT 24
Peak memory 207380 kb
Host smart-5a3d2eb9-39ed-4842-8db5-e1f5a6b4aa3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35884
73734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.3588473734
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.1347738940
Short name T1405
Test name
Test status
Simulation time 7402616656 ps
CPU time 213.65 seconds
Started Jul 25 07:04:07 PM PDT 24
Finished Jul 25 07:07:41 PM PDT 24
Peak memory 215556 kb
Host smart-1c81ac9c-0724-4a77-a3c0-d71d8bc753de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13477
38940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.1347738940
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.1843011128
Short name T934
Test name
Test status
Simulation time 7678929689 ps
CPU time 222.74 seconds
Started Jul 25 07:04:06 PM PDT 24
Finished Jul 25 07:07:49 PM PDT 24
Peak memory 215612 kb
Host smart-be16672f-2bae-46fc-b340-0bf6cb692f4a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1843011128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.1843011128
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.2357579062
Short name T1200
Test name
Test status
Simulation time 244450247 ps
CPU time 1.07 seconds
Started Jul 25 07:04:06 PM PDT 24
Finished Jul 25 07:04:07 PM PDT 24
Peak memory 207136 kb
Host smart-dfc4e10d-4130-4d71-80f3-3f2a6ace3cec
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2357579062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.2357579062
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.2719824341
Short name T1298
Test name
Test status
Simulation time 241720438 ps
CPU time 0.98 seconds
Started Jul 25 07:04:04 PM PDT 24
Finished Jul 25 07:04:05 PM PDT 24
Peak memory 207116 kb
Host smart-1d782299-4ec7-49f6-91e1-fed3379ccc44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27198
24341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.2719824341
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.837445750
Short name T2246
Test name
Test status
Simulation time 4057153037 ps
CPU time 30.48 seconds
Started Jul 25 07:04:07 PM PDT 24
Finished Jul 25 07:04:38 PM PDT 24
Peak memory 215560 kb
Host smart-d539ee30-4d7a-4288-8a0c-ad8216779d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83744
5750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.837445750
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.1679287753
Short name T988
Test name
Test status
Simulation time 3794664172 ps
CPU time 38.89 seconds
Started Jul 25 07:04:04 PM PDT 24
Finished Jul 25 07:04:44 PM PDT 24
Peak memory 216832 kb
Host smart-66b53950-47cf-4846-8544-816ef628e60a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1679287753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.1679287753
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.3695644302
Short name T1648
Test name
Test status
Simulation time 198635798 ps
CPU time 0.89 seconds
Started Jul 25 07:04:06 PM PDT 24
Finished Jul 25 07:04:07 PM PDT 24
Peak memory 207148 kb
Host smart-974854f8-2cc2-4c7e-87da-3deb56eb7819
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3695644302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.3695644302
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.150638335
Short name T2413
Test name
Test status
Simulation time 178280604 ps
CPU time 0.92 seconds
Started Jul 25 07:04:04 PM PDT 24
Finished Jul 25 07:04:05 PM PDT 24
Peak memory 207152 kb
Host smart-4e1b8948-5f77-40ae-854d-de2c89840a75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15063
8335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.150638335
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.182422258
Short name T134
Test name
Test status
Simulation time 191636182 ps
CPU time 0.96 seconds
Started Jul 25 07:04:03 PM PDT 24
Finished Jul 25 07:04:04 PM PDT 24
Peak memory 207160 kb
Host smart-fcf33f7e-9718-4651-9199-004ce77967a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18242
2258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.182422258
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.406014203
Short name T2669
Test name
Test status
Simulation time 207135272 ps
CPU time 0.94 seconds
Started Jul 25 07:04:06 PM PDT 24
Finished Jul 25 07:04:07 PM PDT 24
Peak memory 207136 kb
Host smart-6425bda3-3222-4ebf-918a-48e6a56947eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40601
4203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.406014203
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.1865635521
Short name T1807
Test name
Test status
Simulation time 181531706 ps
CPU time 0.98 seconds
Started Jul 25 07:04:11 PM PDT 24
Finished Jul 25 07:04:12 PM PDT 24
Peak memory 207088 kb
Host smart-724034cc-d549-43fb-a823-6301e06b8f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18656
35521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.1865635521
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.2649054157
Short name T1334
Test name
Test status
Simulation time 207785998 ps
CPU time 0.93 seconds
Started Jul 25 07:04:17 PM PDT 24
Finished Jul 25 07:04:18 PM PDT 24
Peak memory 207232 kb
Host smart-2beb6af6-5fcb-450c-9979-3120c42d988d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26490
54157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.2649054157
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.306753721
Short name T167
Test name
Test status
Simulation time 161675222 ps
CPU time 0.82 seconds
Started Jul 25 07:04:14 PM PDT 24
Finished Jul 25 07:04:15 PM PDT 24
Peak memory 207136 kb
Host smart-3dd555b2-8afe-41fe-a1e0-b20eafd1de9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30675
3721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.306753721
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.120243049
Short name T2836
Test name
Test status
Simulation time 240431243 ps
CPU time 0.99 seconds
Started Jul 25 07:04:14 PM PDT 24
Finished Jul 25 07:04:15 PM PDT 24
Peak memory 207100 kb
Host smart-f0ee8a47-d928-4af9-830c-e39c6c3e427c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=120243049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.120243049
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.3753586420
Short name T1653
Test name
Test status
Simulation time 147521388 ps
CPU time 0.89 seconds
Started Jul 25 07:04:17 PM PDT 24
Finished Jul 25 07:04:18 PM PDT 24
Peak memory 207116 kb
Host smart-5c4550a9-4f83-4111-b309-4e6a8aa5d698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37535
86420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.3753586420
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.860892352
Short name T537
Test name
Test status
Simulation time 42891082 ps
CPU time 0.69 seconds
Started Jul 25 07:04:17 PM PDT 24
Finished Jul 25 07:04:17 PM PDT 24
Peak memory 207104 kb
Host smart-542b1ff1-0102-445e-95f1-80287101765f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86089
2352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.860892352
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.1532218469
Short name T1762
Test name
Test status
Simulation time 15328725760 ps
CPU time 40.61 seconds
Started Jul 25 07:04:19 PM PDT 24
Finished Jul 25 07:05:00 PM PDT 24
Peak memory 220264 kb
Host smart-3deeab8c-81bb-4129-ac44-cee95bca23e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15322
18469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.1532218469
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.1698250845
Short name T2530
Test name
Test status
Simulation time 143811446 ps
CPU time 0.89 seconds
Started Jul 25 07:04:19 PM PDT 24
Finished Jul 25 07:04:20 PM PDT 24
Peak memory 207144 kb
Host smart-1c8ff111-7fdd-4895-9cd1-9d058682b0d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16982
50845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.1698250845
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.3723620832
Short name T1558
Test name
Test status
Simulation time 237738804 ps
CPU time 1.01 seconds
Started Jul 25 07:04:16 PM PDT 24
Finished Jul 25 07:04:17 PM PDT 24
Peak memory 207108 kb
Host smart-5048af0b-313c-4ddb-a020-848366828b9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37236
20832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.3723620832
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.3014643592
Short name T519
Test name
Test status
Simulation time 180260283 ps
CPU time 0.89 seconds
Started Jul 25 07:04:15 PM PDT 24
Finished Jul 25 07:04:16 PM PDT 24
Peak memory 207108 kb
Host smart-510017ea-3c18-4bc8-abc5-1ef56614bc7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30146
43592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.3014643592
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.3838000686
Short name T1430
Test name
Test status
Simulation time 153686133 ps
CPU time 0.91 seconds
Started Jul 25 07:04:14 PM PDT 24
Finished Jul 25 07:04:16 PM PDT 24
Peak memory 207116 kb
Host smart-952e3e6c-7b3d-4a10-be6a-52498c340a34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38380
00686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.3838000686
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.3231679463
Short name T2359
Test name
Test status
Simulation time 157620761 ps
CPU time 0.86 seconds
Started Jul 25 07:04:16 PM PDT 24
Finished Jul 25 07:04:17 PM PDT 24
Peak memory 207136 kb
Host smart-23da6d3e-106e-4c3f-a76c-bcb1351d6006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32316
79463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.3231679463
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.1949339129
Short name T2504
Test name
Test status
Simulation time 156021995 ps
CPU time 0.83 seconds
Started Jul 25 07:04:13 PM PDT 24
Finished Jul 25 07:04:14 PM PDT 24
Peak memory 207076 kb
Host smart-d46f26a4-6876-46cd-9c28-86980e92b3fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19493
39129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.1949339129
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.2762855866
Short name T571
Test name
Test status
Simulation time 149495282 ps
CPU time 0.88 seconds
Started Jul 25 07:04:16 PM PDT 24
Finished Jul 25 07:04:17 PM PDT 24
Peak memory 207228 kb
Host smart-56457099-009d-449d-8f97-e2b465ef32a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27628
55866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.2762855866
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.2049946761
Short name T1328
Test name
Test status
Simulation time 209331624 ps
CPU time 0.99 seconds
Started Jul 25 07:04:13 PM PDT 24
Finished Jul 25 07:04:14 PM PDT 24
Peak memory 207148 kb
Host smart-9e3db855-dab0-47f1-92de-f657d28003ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20499
46761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.2049946761
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.1926100404
Short name T1146
Test name
Test status
Simulation time 6020642843 ps
CPU time 45.44 seconds
Started Jul 25 07:04:14 PM PDT 24
Finished Jul 25 07:04:59 PM PDT 24
Peak memory 215568 kb
Host smart-18805d3a-bf46-4242-aec5-f429e4fb3842
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1926100404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.1926100404
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.1542772130
Short name T1148
Test name
Test status
Simulation time 172014940 ps
CPU time 0.92 seconds
Started Jul 25 07:04:16 PM PDT 24
Finished Jul 25 07:04:17 PM PDT 24
Peak memory 207192 kb
Host smart-d91aa669-b421-403a-8ff4-8dbdad967eb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15427
72130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.1542772130
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.925744970
Short name T2012
Test name
Test status
Simulation time 193428775 ps
CPU time 0.91 seconds
Started Jul 25 07:04:15 PM PDT 24
Finished Jul 25 07:04:16 PM PDT 24
Peak memory 207192 kb
Host smart-6ecd2f60-9127-4a4e-bf8d-f83b1d0665f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92574
4970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.925744970
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.3475573350
Short name T1691
Test name
Test status
Simulation time 1156484020 ps
CPU time 2.98 seconds
Started Jul 25 07:04:19 PM PDT 24
Finished Jul 25 07:04:23 PM PDT 24
Peak memory 207272 kb
Host smart-f4e34058-99f6-4be0-a6e7-121013c9f045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34755
73350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.3475573350
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.2789914548
Short name T2377
Test name
Test status
Simulation time 3717465546 ps
CPU time 27.59 seconds
Started Jul 25 07:04:12 PM PDT 24
Finished Jul 25 07:04:41 PM PDT 24
Peak memory 217064 kb
Host smart-57e4e5b9-2f5b-4aa8-9a21-a45cc0b4f643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27899
14548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.2789914548
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_timeout_missing_host_handshake.2939848
Short name T923
Test name
Test status
Simulation time 163688784 ps
CPU time 0.82 seconds
Started Jul 25 07:04:09 PM PDT 24
Finished Jul 25 07:04:10 PM PDT 24
Peak memory 207124 kb
Host smart-1e8af8b7-47c2-4377-8614-361e12dc5aa2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_timeout_missing_host_h
andshake.2939848
Directory /workspace/18.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.2073328726
Short name T2682
Test name
Test status
Simulation time 52128171 ps
CPU time 0.76 seconds
Started Jul 25 07:04:28 PM PDT 24
Finished Jul 25 07:04:29 PM PDT 24
Peak memory 207168 kb
Host smart-58e6ef2e-8d59-4840-a383-37117b80582d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2073328726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.2073328726
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.851296098
Short name T2648
Test name
Test status
Simulation time 4175716461 ps
CPU time 5.91 seconds
Started Jul 25 07:04:15 PM PDT 24
Finished Jul 25 07:04:21 PM PDT 24
Peak memory 207376 kb
Host smart-3191c3b2-1cd1-4a64-8e6b-48636794f926
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851296098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_ao
n_wake_disconnect.851296098
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.626658462
Short name T820
Test name
Test status
Simulation time 23369973748 ps
CPU time 28.63 seconds
Started Jul 25 07:04:16 PM PDT 24
Finished Jul 25 07:04:45 PM PDT 24
Peak memory 207412 kb
Host smart-9159c4d5-085c-421f-8305-aba72c777950
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626658462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_ao
n_wake_resume.626658462
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.2686361672
Short name T1923
Test name
Test status
Simulation time 277898404 ps
CPU time 1.08 seconds
Started Jul 25 07:04:16 PM PDT 24
Finished Jul 25 07:04:17 PM PDT 24
Peak memory 207184 kb
Host smart-a2f2172f-ba58-4907-8c73-623d1a9adb43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26863
61672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.2686361672
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.1224859880
Short name T1351
Test name
Test status
Simulation time 153510382 ps
CPU time 0.94 seconds
Started Jul 25 07:04:15 PM PDT 24
Finished Jul 25 07:04:16 PM PDT 24
Peak memory 207076 kb
Host smart-f709503e-7c63-4d6f-9801-007ce2d9afa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12248
59880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.1224859880
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.4032357011
Short name T985
Test name
Test status
Simulation time 211927848 ps
CPU time 1.02 seconds
Started Jul 25 07:04:15 PM PDT 24
Finished Jul 25 07:04:16 PM PDT 24
Peak memory 207144 kb
Host smart-02bd942f-c9b6-4e18-889a-7fa637a993e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40323
57011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.4032357011
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.1073537008
Short name T331
Test name
Test status
Simulation time 561989017 ps
CPU time 1.58 seconds
Started Jul 25 07:04:13 PM PDT 24
Finished Jul 25 07:04:15 PM PDT 24
Peak memory 207124 kb
Host smart-fd01eb96-0376-4436-a96a-ac537a56907a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1073537008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.1073537008
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.2849238607
Short name T177
Test name
Test status
Simulation time 11929622609 ps
CPU time 26.07 seconds
Started Jul 25 07:04:14 PM PDT 24
Finished Jul 25 07:04:40 PM PDT 24
Peak memory 207340 kb
Host smart-517b2afb-823b-43cd-b3a9-e3fe565943b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28492
38607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.2849238607
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_device_timeout.3494525062
Short name T2085
Test name
Test status
Simulation time 6352811457 ps
CPU time 43.73 seconds
Started Jul 25 07:04:13 PM PDT 24
Finished Jul 25 07:04:57 PM PDT 24
Peak memory 207372 kb
Host smart-109f232e-ffb4-42ff-bfc7-6f2ddf989e72
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494525062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_timeout.3494525062
Directory /workspace/19.usbdev_device_timeout/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.266041182
Short name T2136
Test name
Test status
Simulation time 395734393 ps
CPU time 1.35 seconds
Started Jul 25 07:04:16 PM PDT 24
Finished Jul 25 07:04:18 PM PDT 24
Peak memory 207020 kb
Host smart-d60a64c3-3f2f-4d4c-8aea-5cdb14ec4dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26604
1182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.266041182
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.1828290295
Short name T566
Test name
Test status
Simulation time 152230716 ps
CPU time 0.8 seconds
Started Jul 25 07:04:14 PM PDT 24
Finished Jul 25 07:04:15 PM PDT 24
Peak memory 207124 kb
Host smart-6353d8b7-12d0-43db-8ef6-59864f84ec40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18282
90295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.1828290295
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.1517744969
Short name T759
Test name
Test status
Simulation time 35681741 ps
CPU time 0.72 seconds
Started Jul 25 07:04:14 PM PDT 24
Finished Jul 25 07:04:15 PM PDT 24
Peak memory 207084 kb
Host smart-1d58c62b-21fc-429f-b6f7-c3b30545f7d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15177
44969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.1517744969
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.3780997249
Short name T1471
Test name
Test status
Simulation time 921463088 ps
CPU time 2.76 seconds
Started Jul 25 07:04:18 PM PDT 24
Finished Jul 25 07:04:21 PM PDT 24
Peak memory 207364 kb
Host smart-69fb7204-3ebd-475f-9935-9d539fa62edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37809
97249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.3780997249
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.1038727518
Short name T2040
Test name
Test status
Simulation time 300496335 ps
CPU time 2.71 seconds
Started Jul 25 07:04:17 PM PDT 24
Finished Jul 25 07:04:20 PM PDT 24
Peak memory 207356 kb
Host smart-df10d872-3d12-4164-bb17-9e748ff08f38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10387
27518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.1038727518
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.3415202778
Short name T358
Test name
Test status
Simulation time 190354072 ps
CPU time 1.04 seconds
Started Jul 25 07:04:20 PM PDT 24
Finished Jul 25 07:04:21 PM PDT 24
Peak memory 207336 kb
Host smart-2b6f754e-7098-485b-bac1-117eb0ddc51a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3415202778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.3415202778
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.1494047483
Short name T1459
Test name
Test status
Simulation time 192711136 ps
CPU time 0.88 seconds
Started Jul 25 07:04:16 PM PDT 24
Finished Jul 25 07:04:18 PM PDT 24
Peak memory 207040 kb
Host smart-6258a8fa-2918-446b-8e1e-293cf8d0d2d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14940
47483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.1494047483
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.2263759614
Short name T1395
Test name
Test status
Simulation time 252067228 ps
CPU time 0.99 seconds
Started Jul 25 07:04:17 PM PDT 24
Finished Jul 25 07:04:18 PM PDT 24
Peak memory 207140 kb
Host smart-8403ccc2-2eb4-4ee2-9ffb-19fe6ab51371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22637
59614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.2263759614
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.3567967771
Short name T997
Test name
Test status
Simulation time 6879342158 ps
CPU time 72.63 seconds
Started Jul 25 07:04:16 PM PDT 24
Finished Jul 25 07:05:29 PM PDT 24
Peak memory 217084 kb
Host smart-f1b963bf-7ba1-4dde-9be3-791923f5c1e5
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3567967771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.3567967771
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/19.usbdev_iso_retraction.3874937615
Short name T2790
Test name
Test status
Simulation time 8766833943 ps
CPU time 103.18 seconds
Started Jul 25 07:04:17 PM PDT 24
Finished Jul 25 07:06:01 PM PDT 24
Peak memory 207328 kb
Host smart-96e61029-f736-4ba8-8e84-808ef39de425
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3874937615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.3874937615
Directory /workspace/19.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.1044864700
Short name T355
Test name
Test status
Simulation time 230473373 ps
CPU time 0.98 seconds
Started Jul 25 07:04:17 PM PDT 24
Finished Jul 25 07:04:18 PM PDT 24
Peak memory 207136 kb
Host smart-a5ee3210-7990-4e12-9291-f12ed8d93b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10448
64700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.1044864700
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.3284930345
Short name T1713
Test name
Test status
Simulation time 23312456311 ps
CPU time 27.9 seconds
Started Jul 25 07:04:13 PM PDT 24
Finished Jul 25 07:04:41 PM PDT 24
Peak memory 207372 kb
Host smart-f498d9ca-0392-4d8f-ad4f-25a09683ccc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32849
30345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.3284930345
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.4189702095
Short name T2140
Test name
Test status
Simulation time 3333810202 ps
CPU time 5.11 seconds
Started Jul 25 07:04:14 PM PDT 24
Finished Jul 25 07:04:19 PM PDT 24
Peak memory 207348 kb
Host smart-ac3d030c-b6d6-4245-8f5a-8d51d37effe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41897
02095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.4189702095
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.1399117401
Short name T2322
Test name
Test status
Simulation time 5518353600 ps
CPU time 166.98 seconds
Started Jul 25 07:04:15 PM PDT 24
Finished Jul 25 07:07:02 PM PDT 24
Peak memory 215608 kb
Host smart-f3753e84-f115-45fd-a326-3d39700d5a5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13991
17401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.1399117401
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.1469071467
Short name T1327
Test name
Test status
Simulation time 5138760226 ps
CPU time 148.65 seconds
Started Jul 25 07:04:16 PM PDT 24
Finished Jul 25 07:06:45 PM PDT 24
Peak memory 215524 kb
Host smart-be03a790-5def-4cca-93ad-46405af90ef1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1469071467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.1469071467
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.890125730
Short name T396
Test name
Test status
Simulation time 273590606 ps
CPU time 1.01 seconds
Started Jul 25 07:04:17 PM PDT 24
Finished Jul 25 07:04:18 PM PDT 24
Peak memory 207076 kb
Host smart-99b905d1-d63e-466c-8eec-b71af6898587
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=890125730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.890125730
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.2207830931
Short name T21
Test name
Test status
Simulation time 203611634 ps
CPU time 0.99 seconds
Started Jul 25 07:04:17 PM PDT 24
Finished Jul 25 07:04:18 PM PDT 24
Peak memory 207136 kb
Host smart-16bc925f-12b5-43cf-8149-41ff03063d94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22078
30931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.2207830931
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.388747666
Short name T2576
Test name
Test status
Simulation time 3028423238 ps
CPU time 24.31 seconds
Started Jul 25 07:04:16 PM PDT 24
Finished Jul 25 07:04:41 PM PDT 24
Peak memory 217064 kb
Host smart-5cc9fad9-12a9-4115-ac28-754c821d6af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38874
7666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.388747666
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.934983815
Short name T1128
Test name
Test status
Simulation time 3806835053 ps
CPU time 38.9 seconds
Started Jul 25 07:04:20 PM PDT 24
Finished Jul 25 07:04:59 PM PDT 24
Peak memory 207412 kb
Host smart-b993eb29-794d-4e1d-8139-ef28867550ac
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=934983815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.934983815
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.3230132215
Short name T474
Test name
Test status
Simulation time 168565273 ps
CPU time 0.9 seconds
Started Jul 25 07:04:16 PM PDT 24
Finished Jul 25 07:04:17 PM PDT 24
Peak memory 207236 kb
Host smart-613cb66c-1c3f-4133-8efe-dca58b954cbe
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3230132215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.3230132215
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.3571906588
Short name T1482
Test name
Test status
Simulation time 163817064 ps
CPU time 0.89 seconds
Started Jul 25 07:04:30 PM PDT 24
Finished Jul 25 07:04:31 PM PDT 24
Peak memory 207148 kb
Host smart-ed1ebfc9-ec75-4781-92c1-2593809a8e1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35719
06588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.3571906588
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.2378527556
Short name T1954
Test name
Test status
Simulation time 210791132 ps
CPU time 0.98 seconds
Started Jul 25 07:04:27 PM PDT 24
Finished Jul 25 07:04:28 PM PDT 24
Peak memory 207124 kb
Host smart-6b5ee90a-c1ea-4083-b0db-2e319365a157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23785
27556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.2378527556
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.880373368
Short name T1209
Test name
Test status
Simulation time 182521736 ps
CPU time 0.93 seconds
Started Jul 25 07:04:26 PM PDT 24
Finished Jul 25 07:04:27 PM PDT 24
Peak memory 207232 kb
Host smart-68c7b137-2d06-491f-b7bd-4673ad4413d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88037
3368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.880373368
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.2059235115
Short name T672
Test name
Test status
Simulation time 181223666 ps
CPU time 0.91 seconds
Started Jul 25 07:04:27 PM PDT 24
Finished Jul 25 07:04:29 PM PDT 24
Peak memory 207156 kb
Host smart-77184bf3-95a6-4567-91fa-83eb09e1206a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20592
35115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.2059235115
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.1968139384
Short name T555
Test name
Test status
Simulation time 209195654 ps
CPU time 0.93 seconds
Started Jul 25 07:04:25 PM PDT 24
Finished Jul 25 07:04:26 PM PDT 24
Peak memory 207164 kb
Host smart-3539d1bd-fbf7-4443-9d51-f7a47cd2f4a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19681
39384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.1968139384
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.4182321353
Short name T193
Test name
Test status
Simulation time 160350323 ps
CPU time 0.89 seconds
Started Jul 25 07:04:28 PM PDT 24
Finished Jul 25 07:04:29 PM PDT 24
Peak memory 207128 kb
Host smart-cd9f2d8e-bb04-4ad5-9cc8-9ff8a320c393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41823
21353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.4182321353
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.56687517
Short name T434
Test name
Test status
Simulation time 260542666 ps
CPU time 1.1 seconds
Started Jul 25 07:04:26 PM PDT 24
Finished Jul 25 07:04:27 PM PDT 24
Peak memory 207116 kb
Host smart-9c6795fa-43ad-4106-9a92-82c019ec2336
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=56687517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.56687517
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.497933179
Short name T1907
Test name
Test status
Simulation time 140945747 ps
CPU time 0.81 seconds
Started Jul 25 07:04:25 PM PDT 24
Finished Jul 25 07:04:26 PM PDT 24
Peak memory 207084 kb
Host smart-9dedea57-994d-4a58-b1f7-1faad5feb3ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49793
3179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.497933179
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.517356134
Short name T2304
Test name
Test status
Simulation time 45340140 ps
CPU time 0.72 seconds
Started Jul 25 07:04:23 PM PDT 24
Finished Jul 25 07:04:24 PM PDT 24
Peak memory 207084 kb
Host smart-195304c0-07cd-4ffc-bb99-cb2c2a00022a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51735
6134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.517356134
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.3432166873
Short name T2273
Test name
Test status
Simulation time 15517382692 ps
CPU time 40.57 seconds
Started Jul 25 07:04:25 PM PDT 24
Finished Jul 25 07:05:06 PM PDT 24
Peak memory 215648 kb
Host smart-535a693a-4518-4047-9c7e-c8135942c483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34321
66873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.3432166873
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.669550257
Short name T2145
Test name
Test status
Simulation time 166324476 ps
CPU time 0.89 seconds
Started Jul 25 07:04:30 PM PDT 24
Finished Jul 25 07:04:31 PM PDT 24
Peak memory 207052 kb
Host smart-a3729a15-63fa-4941-ba6d-4ecc568d856d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66955
0257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.669550257
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.88106253
Short name T1161
Test name
Test status
Simulation time 227673581 ps
CPU time 0.99 seconds
Started Jul 25 07:04:28 PM PDT 24
Finished Jul 25 07:04:29 PM PDT 24
Peak memory 207140 kb
Host smart-eed54f1f-9efd-4284-8c46-1fb4c31c1074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88106
253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.88106253
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.511215349
Short name T1197
Test name
Test status
Simulation time 182714144 ps
CPU time 0.91 seconds
Started Jul 25 07:04:27 PM PDT 24
Finished Jul 25 07:04:28 PM PDT 24
Peak memory 207036 kb
Host smart-7ee38d9c-d08a-40da-b0c0-810defc63665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51121
5349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.511215349
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.2322904828
Short name T359
Test name
Test status
Simulation time 216604024 ps
CPU time 0.99 seconds
Started Jul 25 07:04:27 PM PDT 24
Finished Jul 25 07:04:28 PM PDT 24
Peak memory 207060 kb
Host smart-6da5e077-3c0d-4072-8caf-56a083456c6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23229
04828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.2322904828
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.1095396807
Short name T1289
Test name
Test status
Simulation time 145735678 ps
CPU time 0.86 seconds
Started Jul 25 07:04:30 PM PDT 24
Finished Jul 25 07:04:31 PM PDT 24
Peak memory 207036 kb
Host smart-f4c9a6ac-b8df-43c8-9e90-d47e3d35321f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10953
96807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.1095396807
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.217821498
Short name T2334
Test name
Test status
Simulation time 176941265 ps
CPU time 0.89 seconds
Started Jul 25 07:04:28 PM PDT 24
Finished Jul 25 07:04:29 PM PDT 24
Peak memory 207084 kb
Host smart-d3d9c635-f97d-4e2a-a68a-86d9bc8745a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21782
1498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.217821498
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.3508972664
Short name T2499
Test name
Test status
Simulation time 181803135 ps
CPU time 0.9 seconds
Started Jul 25 07:04:25 PM PDT 24
Finished Jul 25 07:04:26 PM PDT 24
Peak memory 207104 kb
Host smart-29518352-f7d6-48db-b4ce-96d7b0ab1dc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35089
72664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.3508972664
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.3553772574
Short name T1840
Test name
Test status
Simulation time 254038808 ps
CPU time 1.03 seconds
Started Jul 25 07:04:23 PM PDT 24
Finished Jul 25 07:04:25 PM PDT 24
Peak memory 207148 kb
Host smart-3b524518-f67e-470f-aacc-259c61ef1f86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35537
72574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.3553772574
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.891490341
Short name T1369
Test name
Test status
Simulation time 4149860411 ps
CPU time 121.02 seconds
Started Jul 25 07:04:26 PM PDT 24
Finished Jul 25 07:06:27 PM PDT 24
Peak memory 215592 kb
Host smart-fcfa2540-ac3a-4c52-aaf4-f0744bc8e75e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=891490341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.891490341
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.2761767137
Short name T986
Test name
Test status
Simulation time 155130524 ps
CPU time 0.83 seconds
Started Jul 25 07:04:25 PM PDT 24
Finished Jul 25 07:04:25 PM PDT 24
Peak memory 207144 kb
Host smart-8e937295-cb43-460d-8515-0eeac2c63d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27617
67137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.2761767137
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.2374084174
Short name T685
Test name
Test status
Simulation time 181350885 ps
CPU time 1.02 seconds
Started Jul 25 07:04:28 PM PDT 24
Finished Jul 25 07:04:29 PM PDT 24
Peak memory 207128 kb
Host smart-75c438c4-72c5-4f58-84b9-163cf096012a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23740
84174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.2374084174
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.44241712
Short name T1690
Test name
Test status
Simulation time 1209049576 ps
CPU time 2.82 seconds
Started Jul 25 07:04:24 PM PDT 24
Finished Jul 25 07:04:27 PM PDT 24
Peak memory 207260 kb
Host smart-3dfd983a-2012-4cd3-8dd7-1b0bc9c3d7a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44241
712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.44241712
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.510138215
Short name T4
Test name
Test status
Simulation time 4639025681 ps
CPU time 37.46 seconds
Started Jul 25 07:04:25 PM PDT 24
Finished Jul 25 07:05:03 PM PDT 24
Peak memory 216996 kb
Host smart-b8c5f38b-e8ba-439f-ba0f-ec53a3aad9a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51013
8215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.510138215
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_timeout_missing_host_handshake.392902301
Short name T2668
Test name
Test status
Simulation time 1129915416 ps
CPU time 25.83 seconds
Started Jul 25 07:04:18 PM PDT 24
Finished Jul 25 07:04:44 PM PDT 24
Peak memory 207288 kb
Host smart-ecc02d3c-b5ce-4da1-b252-3284f6664bb4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392902301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_timeout_missing_host
_handshake.392902301
Directory /workspace/19.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.3010046963
Short name T1779
Test name
Test status
Simulation time 47660369 ps
CPU time 0.66 seconds
Started Jul 25 07:01:01 PM PDT 24
Finished Jul 25 07:01:01 PM PDT 24
Peak memory 207144 kb
Host smart-e2307b71-46ec-4575-b4d8-7fc6927ebb8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3010046963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.3010046963
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.1652766718
Short name T2231
Test name
Test status
Simulation time 4070791649 ps
CPU time 5.71 seconds
Started Jul 25 07:00:47 PM PDT 24
Finished Jul 25 07:00:53 PM PDT 24
Peak memory 207384 kb
Host smart-d66e7498-03da-4f84-8801-61d2a8cc0503
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652766718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ao
n_wake_disconnect.1652766718
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.3783282470
Short name T2344
Test name
Test status
Simulation time 13331411638 ps
CPU time 19.41 seconds
Started Jul 25 07:00:43 PM PDT 24
Finished Jul 25 07:01:02 PM PDT 24
Peak memory 207384 kb
Host smart-4342765a-ba38-4754-b805-dac722810751
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783282470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.3783282470
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.856258332
Short name T2563
Test name
Test status
Simulation time 23507901890 ps
CPU time 34.78 seconds
Started Jul 25 07:00:41 PM PDT 24
Finished Jul 25 07:01:16 PM PDT 24
Peak memory 207396 kb
Host smart-511b231a-52f0-4442-aa17-e90bc589f0b1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856258332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon
_wake_resume.856258332
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.3241916129
Short name T1602
Test name
Test status
Simulation time 150297829 ps
CPU time 0.82 seconds
Started Jul 25 07:00:42 PM PDT 24
Finished Jul 25 07:00:44 PM PDT 24
Peak memory 207164 kb
Host smart-e70b7871-dba4-4d03-88e6-89fdff772982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32419
16129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.3241916129
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.3472711802
Short name T63
Test name
Test status
Simulation time 173890589 ps
CPU time 0.87 seconds
Started Jul 25 07:00:43 PM PDT 24
Finished Jul 25 07:00:44 PM PDT 24
Peak memory 207132 kb
Host smart-1865bb57-c963-4c6a-8303-ec1e460adcbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34727
11802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.3472711802
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.4054997202
Short name T1390
Test name
Test status
Simulation time 157124793 ps
CPU time 0.85 seconds
Started Jul 25 07:00:40 PM PDT 24
Finished Jul 25 07:00:41 PM PDT 24
Peak memory 207160 kb
Host smart-e30ddaf0-8715-4755-815d-0bbbde360003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40549
97202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.4054997202
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.3235616958
Short name T2575
Test name
Test status
Simulation time 212267549 ps
CPU time 0.95 seconds
Started Jul 25 07:00:41 PM PDT 24
Finished Jul 25 07:00:42 PM PDT 24
Peak memory 207104 kb
Host smart-49906c9c-c596-4bba-8991-aebd65bf9f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32356
16958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.3235616958
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.2505951028
Short name T1301
Test name
Test status
Simulation time 990238247 ps
CPU time 2.55 seconds
Started Jul 25 07:00:42 PM PDT 24
Finished Jul 25 07:00:45 PM PDT 24
Peak memory 207376 kb
Host smart-d9e87fdd-6f90-49d1-ba38-77985c13787f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2505951028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.2505951028
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.3735677614
Short name T2453
Test name
Test status
Simulation time 12546542872 ps
CPU time 24.81 seconds
Started Jul 25 07:00:43 PM PDT 24
Finished Jul 25 07:01:08 PM PDT 24
Peak memory 207348 kb
Host smart-83b8ff88-b0c6-4800-acf8-c4dff38cbcc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37356
77614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.3735677614
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_device_timeout.4051431305
Short name T400
Test name
Test status
Simulation time 4299664005 ps
CPU time 35.1 seconds
Started Jul 25 07:00:43 PM PDT 24
Finished Jul 25 07:01:18 PM PDT 24
Peak memory 207348 kb
Host smart-9ec25cb5-fdf3-47a7-b24e-937fe1e43d68
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051431305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_timeout.4051431305
Directory /workspace/2.usbdev_device_timeout/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.3539218543
Short name T1326
Test name
Test status
Simulation time 488245747 ps
CPU time 1.55 seconds
Started Jul 25 07:00:42 PM PDT 24
Finished Jul 25 07:00:44 PM PDT 24
Peak memory 207080 kb
Host smart-9a1a3857-b88d-4c48-84e5-6cd8eb3edaf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35392
18543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.3539218543
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.4180310290
Short name T2738
Test name
Test status
Simulation time 149240046 ps
CPU time 0.82 seconds
Started Jul 25 07:00:40 PM PDT 24
Finished Jul 25 07:00:41 PM PDT 24
Peak memory 207120 kb
Host smart-020b567f-e385-4055-9ffa-c259de5b0aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41803
10290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.4180310290
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.3068871684
Short name T2352
Test name
Test status
Simulation time 32944463 ps
CPU time 0.69 seconds
Started Jul 25 07:00:41 PM PDT 24
Finished Jul 25 07:00:42 PM PDT 24
Peak memory 207096 kb
Host smart-7fa48afe-283c-4a7a-ae83-e5be883d89d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30688
71684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.3068871684
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.1199249510
Short name T2823
Test name
Test status
Simulation time 832890414 ps
CPU time 2.42 seconds
Started Jul 25 07:00:41 PM PDT 24
Finished Jul 25 07:00:44 PM PDT 24
Peak memory 207336 kb
Host smart-60121247-ad2d-4dd2-8e38-96a9059e30d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11992
49510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.1199249510
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.2281570810
Short name T2047
Test name
Test status
Simulation time 164590584 ps
CPU time 1.6 seconds
Started Jul 25 07:00:42 PM PDT 24
Finished Jul 25 07:00:44 PM PDT 24
Peak memory 207344 kb
Host smart-d434b73c-2630-44ca-9dc7-4c46ecd3ba1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22815
70810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.2281570810
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.4087176890
Short name T1078
Test name
Test status
Simulation time 90206316227 ps
CPU time 143.41 seconds
Started Jul 25 07:00:41 PM PDT 24
Finished Jul 25 07:03:05 PM PDT 24
Peak memory 207384 kb
Host smart-6a795921-7357-4dfc-b715-fd006f52d278
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4087176890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.4087176890
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.2761620797
Short name T2800
Test name
Test status
Simulation time 97380523701 ps
CPU time 169.83 seconds
Started Jul 25 07:00:45 PM PDT 24
Finished Jul 25 07:03:35 PM PDT 24
Peak memory 207328 kb
Host smart-a5b5d13f-3764-4873-aa7f-09b42e180043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761620797 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.2761620797
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.2041906752
Short name T345
Test name
Test status
Simulation time 100108345929 ps
CPU time 178.54 seconds
Started Jul 25 07:00:41 PM PDT 24
Finished Jul 25 07:03:40 PM PDT 24
Peak memory 207348 kb
Host smart-1c0ce9eb-1b7c-4fd4-861e-296c9a8390fd
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2041906752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.2041906752
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.74132244
Short name T1596
Test name
Test status
Simulation time 119031909300 ps
CPU time 202.76 seconds
Started Jul 25 07:00:41 PM PDT 24
Finished Jul 25 07:04:05 PM PDT 24
Peak memory 207384 kb
Host smart-fdf6de7f-3638-412c-8cac-b89264d7b181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74132244 -assert nop
ostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.74132244
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.2905277569
Short name T338
Test name
Test status
Simulation time 113117096392 ps
CPU time 180.69 seconds
Started Jul 25 07:00:52 PM PDT 24
Finished Jul 25 07:03:53 PM PDT 24
Peak memory 207356 kb
Host smart-1a872ecc-d84a-47f7-9de0-aa1ef6c412d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29052
77569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.2905277569
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.2325936568
Short name T1826
Test name
Test status
Simulation time 175286564 ps
CPU time 0.98 seconds
Started Jul 25 07:00:53 PM PDT 24
Finished Jul 25 07:00:54 PM PDT 24
Peak memory 207340 kb
Host smart-32d0b61d-602b-4524-8d9a-a6b866c895e8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2325936568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.2325936568
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.1969836022
Short name T2243
Test name
Test status
Simulation time 134253509 ps
CPU time 0.83 seconds
Started Jul 25 07:00:54 PM PDT 24
Finished Jul 25 07:00:55 PM PDT 24
Peak memory 207080 kb
Host smart-a7393192-f8e0-45e4-8e34-3d28cea62313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19698
36022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.1969836022
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.2666606661
Short name T2178
Test name
Test status
Simulation time 197643821 ps
CPU time 0.93 seconds
Started Jul 25 07:00:55 PM PDT 24
Finished Jul 25 07:00:56 PM PDT 24
Peak memory 207128 kb
Host smart-505d6861-4186-47ac-82f7-ac95fb47420f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26666
06661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.2666606661
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.2933784282
Short name T2686
Test name
Test status
Simulation time 8841829603 ps
CPU time 255.27 seconds
Started Jul 25 07:00:54 PM PDT 24
Finished Jul 25 07:05:10 PM PDT 24
Peak memory 215592 kb
Host smart-450506ce-2ede-4b94-a2e8-002c1502c4bf
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2933784282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.2933784282
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_iso_retraction.1111435730
Short name T1124
Test name
Test status
Simulation time 4506166185 ps
CPU time 59.46 seconds
Started Jul 25 07:00:54 PM PDT 24
Finished Jul 25 07:01:53 PM PDT 24
Peak memory 207484 kb
Host smart-bba4757b-aa5b-4b13-b7fb-711defd56a28
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1111435730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_iso_retraction.1111435730
Directory /workspace/2.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.1684506927
Short name T1913
Test name
Test status
Simulation time 223236757 ps
CPU time 0.95 seconds
Started Jul 25 07:00:55 PM PDT 24
Finished Jul 25 07:00:56 PM PDT 24
Peak memory 207124 kb
Host smart-f444609a-6170-4b37-a138-8628f10b192d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16845
06927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.1684506927
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.1032975307
Short name T1107
Test name
Test status
Simulation time 23344311376 ps
CPU time 29.66 seconds
Started Jul 25 07:00:55 PM PDT 24
Finished Jul 25 07:01:25 PM PDT 24
Peak memory 207356 kb
Host smart-bfbdd6e9-7722-4b6d-b894-a66f67f5b81c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10329
75307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.1032975307
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.948271296
Short name T1319
Test name
Test status
Simulation time 3336070326 ps
CPU time 4.85 seconds
Started Jul 25 07:00:52 PM PDT 24
Finished Jul 25 07:00:57 PM PDT 24
Peak memory 207344 kb
Host smart-d09afb3c-ed57-44f6-b027-1430080f355e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94827
1296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.948271296
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.1459740015
Short name T1601
Test name
Test status
Simulation time 8324599602 ps
CPU time 242.37 seconds
Started Jul 25 07:00:53 PM PDT 24
Finished Jul 25 07:04:56 PM PDT 24
Peak memory 215660 kb
Host smart-d5978f89-e55e-4a4e-a9a9-f1dd40365d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14597
40015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.1459740015
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.2679381214
Short name T164
Test name
Test status
Simulation time 4750961061 ps
CPU time 136.4 seconds
Started Jul 25 07:00:54 PM PDT 24
Finished Jul 25 07:03:10 PM PDT 24
Peak memory 215608 kb
Host smart-aab2fdf7-3fa7-4adb-8edc-144e842da8a8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2679381214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.2679381214
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.2044925919
Short name T2051
Test name
Test status
Simulation time 243807848 ps
CPU time 0.98 seconds
Started Jul 25 07:00:53 PM PDT 24
Finished Jul 25 07:00:54 PM PDT 24
Peak memory 207060 kb
Host smart-b9a4f58b-5ce3-4ff1-a43b-862956fdc13d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2044925919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.2044925919
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.59511682
Short name T547
Test name
Test status
Simulation time 232256920 ps
CPU time 0.95 seconds
Started Jul 25 07:00:52 PM PDT 24
Finished Jul 25 07:00:54 PM PDT 24
Peak memory 207072 kb
Host smart-483840ab-06c5-4d61-9ee4-44a31c093a62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59511
682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.59511682
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.1214280154
Short name T2507
Test name
Test status
Simulation time 3281390484 ps
CPU time 23.74 seconds
Started Jul 25 07:00:55 PM PDT 24
Finished Jul 25 07:01:19 PM PDT 24
Peak memory 216804 kb
Host smart-7b7adb6b-e317-4d61-8310-48626a20c28b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12142
80154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.1214280154
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.3780147726
Short name T1643
Test name
Test status
Simulation time 3732512251 ps
CPU time 110.71 seconds
Started Jul 25 07:00:52 PM PDT 24
Finished Jul 25 07:02:43 PM PDT 24
Peak memory 215664 kb
Host smart-65b1f816-0950-4876-8909-adc732990285
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3780147726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.3780147726
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.3439576069
Short name T540
Test name
Test status
Simulation time 164042627 ps
CPU time 0.91 seconds
Started Jul 25 07:00:52 PM PDT 24
Finished Jul 25 07:00:53 PM PDT 24
Peak memory 207084 kb
Host smart-6f015d14-ceab-4cc2-b2b8-b6e265a41340
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3439576069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.3439576069
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.1295658743
Short name T1967
Test name
Test status
Simulation time 142194791 ps
CPU time 0.81 seconds
Started Jul 25 07:00:53 PM PDT 24
Finished Jul 25 07:00:54 PM PDT 24
Peak memory 207120 kb
Host smart-ac8e7600-6d0a-4211-b12a-6a22b9f4bfcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12956
58743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.1295658743
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.3068459374
Short name T154
Test name
Test status
Simulation time 212648799 ps
CPU time 0.99 seconds
Started Jul 25 07:00:51 PM PDT 24
Finished Jul 25 07:00:52 PM PDT 24
Peak memory 207116 kb
Host smart-795f820d-f073-4b26-9a17-f36f61cd360f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30684
59374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.3068459374
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.318583655
Short name T678
Test name
Test status
Simulation time 168963207 ps
CPU time 0.83 seconds
Started Jul 25 07:00:54 PM PDT 24
Finished Jul 25 07:00:55 PM PDT 24
Peak memory 207160 kb
Host smart-e35f5c9f-2211-4786-acb7-ab84f460ba3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31858
3655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.318583655
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.4114761209
Short name T1833
Test name
Test status
Simulation time 230810192 ps
CPU time 0.94 seconds
Started Jul 25 07:00:53 PM PDT 24
Finished Jul 25 07:00:54 PM PDT 24
Peak memory 207112 kb
Host smart-f464b7ba-8441-4399-a1f4-eb6808505b24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41147
61209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.4114761209
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.3259840899
Short name T18
Test name
Test status
Simulation time 188793915 ps
CPU time 0.95 seconds
Started Jul 25 07:00:51 PM PDT 24
Finished Jul 25 07:00:52 PM PDT 24
Peak memory 207188 kb
Host smart-ddb9ce46-becd-460d-ae82-aab369be8529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32598
40899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.3259840899
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.2500314833
Short name T2150
Test name
Test status
Simulation time 218540329 ps
CPU time 1.03 seconds
Started Jul 25 07:00:53 PM PDT 24
Finished Jul 25 07:00:54 PM PDT 24
Peak memory 207184 kb
Host smart-df39399d-6624-43d1-8938-b7c3511b2430
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2500314833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.2500314833
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.1137029768
Short name T220
Test name
Test status
Simulation time 209595380 ps
CPU time 1.03 seconds
Started Jul 25 07:00:54 PM PDT 24
Finished Jul 25 07:00:55 PM PDT 24
Peak memory 207124 kb
Host smart-81a24267-5546-482a-ab48-f99035d87289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11370
29768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.1137029768
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.3471396953
Short name T1617
Test name
Test status
Simulation time 141900434 ps
CPU time 0.79 seconds
Started Jul 25 07:01:17 PM PDT 24
Finished Jul 25 07:01:18 PM PDT 24
Peak memory 207088 kb
Host smart-b40a5f07-8650-42e7-846d-b79cfb2a28a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34713
96953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.3471396953
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.2756396116
Short name T1339
Test name
Test status
Simulation time 30077119 ps
CPU time 0.72 seconds
Started Jul 25 07:00:53 PM PDT 24
Finished Jul 25 07:00:54 PM PDT 24
Peak memory 207100 kb
Host smart-446008ae-0dc9-4b27-892b-f94b2bbd819a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27563
96116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.2756396116
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.1681479714
Short name T2730
Test name
Test status
Simulation time 189861638 ps
CPU time 0.95 seconds
Started Jul 25 07:00:51 PM PDT 24
Finished Jul 25 07:00:52 PM PDT 24
Peak memory 207108 kb
Host smart-9c5e215e-b483-48c7-99bc-e421bf7995fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16814
79714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.1681479714
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.3417969407
Short name T2351
Test name
Test status
Simulation time 206471191 ps
CPU time 0.94 seconds
Started Jul 25 07:00:55 PM PDT 24
Finished Jul 25 07:00:57 PM PDT 24
Peak memory 207112 kb
Host smart-95066b4e-5ce5-40b3-8987-597a67a303b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34179
69407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.3417969407
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.1617821867
Short name T171
Test name
Test status
Simulation time 9765906217 ps
CPU time 177.36 seconds
Started Jul 25 07:00:59 PM PDT 24
Finished Jul 25 07:03:56 PM PDT 24
Peak memory 215560 kb
Host smart-0d4b8487-911f-4b8f-bcc4-7939151de2cd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617821867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.1617821867
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.4043552869
Short name T2692
Test name
Test status
Simulation time 4709112223 ps
CPU time 119.19 seconds
Started Jul 25 07:01:03 PM PDT 24
Finished Jul 25 07:03:02 PM PDT 24
Peak memory 215604 kb
Host smart-8fe4948e-11b7-4c16-b5e6-45ab9e41022a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4043552869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.4043552869
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.4219008877
Short name T1007
Test name
Test status
Simulation time 19438906142 ps
CPU time 148.19 seconds
Started Jul 25 07:01:04 PM PDT 24
Finished Jul 25 07:03:33 PM PDT 24
Peak memory 217236 kb
Host smart-626f56eb-7631-4495-b545-6ca0f366dc12
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219008877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.4219008877
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.3645965239
Short name T528
Test name
Test status
Simulation time 179577139 ps
CPU time 0.9 seconds
Started Jul 25 07:00:52 PM PDT 24
Finished Jul 25 07:00:53 PM PDT 24
Peak memory 207128 kb
Host smart-7e4b696e-75b6-4dce-a619-492589c6af86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36459
65239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.3645965239
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.2262410733
Short name T234
Test name
Test status
Simulation time 154149140 ps
CPU time 0.86 seconds
Started Jul 25 07:00:55 PM PDT 24
Finished Jul 25 07:00:56 PM PDT 24
Peak memory 207116 kb
Host smart-fe004fd1-2c1b-4e8c-847b-105efdcf6e45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22624
10733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.2262410733
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.2064584022
Short name T1642
Test name
Test status
Simulation time 155783111 ps
CPU time 0.85 seconds
Started Jul 25 07:00:58 PM PDT 24
Finished Jul 25 07:00:59 PM PDT 24
Peak memory 207096 kb
Host smart-4faf54fd-e253-4bb1-a6b9-954ec7503e7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20645
84022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.2064584022
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.3670328761
Short name T2015
Test name
Test status
Simulation time 183370287 ps
CPU time 0.89 seconds
Started Jul 25 07:00:59 PM PDT 24
Finished Jul 25 07:01:01 PM PDT 24
Peak memory 207148 kb
Host smart-964bbf33-13ff-4d31-ac09-964e3f9051cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36703
28761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.3670328761
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.832895902
Short name T210
Test name
Test status
Simulation time 431154169 ps
CPU time 1.34 seconds
Started Jul 25 07:01:00 PM PDT 24
Finished Jul 25 07:01:02 PM PDT 24
Peak memory 224028 kb
Host smart-103a9622-f9e2-48a6-9136-5659d7075c4a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=832895902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.832895902
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.3665033852
Short name T2307
Test name
Test status
Simulation time 418410374 ps
CPU time 1.41 seconds
Started Jul 25 07:01:00 PM PDT 24
Finished Jul 25 07:01:01 PM PDT 24
Peak memory 207152 kb
Host smart-7de63310-03f4-4084-b838-24e2dcd2cb91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36650
33852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.3665033852
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.2923704826
Short name T1300
Test name
Test status
Simulation time 205957369 ps
CPU time 0.97 seconds
Started Jul 25 07:01:00 PM PDT 24
Finished Jul 25 07:01:01 PM PDT 24
Peak memory 207124 kb
Host smart-0747a02d-6656-41f4-9186-38bd444cb38f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29237
04826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.2923704826
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.1724304058
Short name T2060
Test name
Test status
Simulation time 155247032 ps
CPU time 0.85 seconds
Started Jul 25 07:01:24 PM PDT 24
Finished Jul 25 07:01:25 PM PDT 24
Peak memory 207156 kb
Host smart-50984681-d0cb-4e01-8ded-0d74e2aacabf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17243
04058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.1724304058
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.1526094780
Short name T744
Test name
Test status
Simulation time 153481636 ps
CPU time 0.84 seconds
Started Jul 25 07:01:21 PM PDT 24
Finished Jul 25 07:01:22 PM PDT 24
Peak memory 207124 kb
Host smart-bfa918c8-5402-43b5-b05e-7cf46f2d0075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15260
94780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.1526094780
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.3612221105
Short name T1781
Test name
Test status
Simulation time 219856417 ps
CPU time 0.99 seconds
Started Jul 25 07:00:58 PM PDT 24
Finished Jul 25 07:00:59 PM PDT 24
Peak memory 207116 kb
Host smart-4ad58748-b737-4bf9-b630-0b2f265abda5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36122
21105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.3612221105
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.723404878
Short name T1381
Test name
Test status
Simulation time 5348318220 ps
CPU time 40.94 seconds
Started Jul 25 07:00:57 PM PDT 24
Finished Jul 25 07:01:38 PM PDT 24
Peak memory 216884 kb
Host smart-a99f360e-ee1b-4396-b371-65138acda9bb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=723404878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.723404878
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.2666404844
Short name T1571
Test name
Test status
Simulation time 156928758 ps
CPU time 0.82 seconds
Started Jul 25 07:00:57 PM PDT 24
Finished Jul 25 07:00:58 PM PDT 24
Peak memory 207116 kb
Host smart-7ba5af37-8d64-446d-9303-5133d5daab2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26664
04844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.2666404844
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.1029219395
Short name T2802
Test name
Test status
Simulation time 181393665 ps
CPU time 0.88 seconds
Started Jul 25 07:01:01 PM PDT 24
Finished Jul 25 07:01:02 PM PDT 24
Peak memory 207136 kb
Host smart-77cef834-a38e-4edb-aae5-1bc6a7d651dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10292
19395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.1029219395
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.2008018188
Short name T2816
Test name
Test status
Simulation time 903617388 ps
CPU time 2.53 seconds
Started Jul 25 07:01:00 PM PDT 24
Finished Jul 25 07:01:03 PM PDT 24
Peak memory 207316 kb
Host smart-4e93e053-3c50-4404-aee8-32dcd2467ca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20080
18188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.2008018188
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.2090344733
Short name T514
Test name
Test status
Simulation time 4785511102 ps
CPU time 142.26 seconds
Started Jul 25 07:00:59 PM PDT 24
Finished Jul 25 07:03:21 PM PDT 24
Peak memory 215616 kb
Host smart-e523de6a-ea3f-4289-8192-9ca35329f036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20903
44733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.2090344733
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_timeout_missing_host_handshake.1866614233
Short name T1978
Test name
Test status
Simulation time 206266465 ps
CPU time 0.98 seconds
Started Jul 25 07:00:38 PM PDT 24
Finished Jul 25 07:00:40 PM PDT 24
Peak memory 207148 kb
Host smart-3c6775a9-a53d-42b5-8bbb-a204c3f515c0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866614233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_timeout_missing_host
_handshake.1866614233
Directory /workspace/2.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.2623636440
Short name T2605
Test name
Test status
Simulation time 40173838 ps
CPU time 0.66 seconds
Started Jul 25 07:04:42 PM PDT 24
Finished Jul 25 07:04:43 PM PDT 24
Peak memory 207168 kb
Host smart-cbd323e9-a14d-41f0-88df-966683853f90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2623636440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.2623636440
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.2384980764
Short name T2071
Test name
Test status
Simulation time 4267226974 ps
CPU time 6.63 seconds
Started Jul 25 07:04:26 PM PDT 24
Finished Jul 25 07:04:33 PM PDT 24
Peak memory 207488 kb
Host smart-5efdc353-9523-44c1-a20e-379f3b1dd6a9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384980764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_a
on_wake_disconnect.2384980764
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.2480234953
Short name T1164
Test name
Test status
Simulation time 13414159819 ps
CPU time 15.27 seconds
Started Jul 25 07:04:22 PM PDT 24
Finished Jul 25 07:04:38 PM PDT 24
Peak memory 207400 kb
Host smart-d061a58e-0f65-486f-baaf-a0b293d9006d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480234953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.2480234953
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.2545391771
Short name T2363
Test name
Test status
Simulation time 23305752657 ps
CPU time 27.59 seconds
Started Jul 25 07:04:29 PM PDT 24
Finished Jul 25 07:04:56 PM PDT 24
Peak memory 207408 kb
Host smart-d337d16e-c2cc-452f-b0f2-1d9bad06f9f9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545391771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_a
on_wake_resume.2545391771
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.3584276371
Short name T2261
Test name
Test status
Simulation time 193929236 ps
CPU time 0.98 seconds
Started Jul 25 07:04:28 PM PDT 24
Finished Jul 25 07:04:29 PM PDT 24
Peak memory 207152 kb
Host smart-a27e262e-217d-4899-80b1-30ae064b88d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35842
76371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.3584276371
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.3017728597
Short name T1370
Test name
Test status
Simulation time 143540862 ps
CPU time 0.85 seconds
Started Jul 25 07:04:26 PM PDT 24
Finished Jul 25 07:04:28 PM PDT 24
Peak memory 207120 kb
Host smart-7e202bed-43aa-4167-9b49-fec00ca12cea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30177
28597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.3017728597
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.1547417015
Short name T2317
Test name
Test status
Simulation time 378744160 ps
CPU time 1.39 seconds
Started Jul 25 07:04:26 PM PDT 24
Finished Jul 25 07:04:28 PM PDT 24
Peak memory 207144 kb
Host smart-40282bb6-25d7-4b14-9fb6-2cdb50e2b758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15474
17015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.1547417015
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_device_address.1719615090
Short name T2235
Test name
Test status
Simulation time 23742038237 ps
CPU time 54.2 seconds
Started Jul 25 07:04:25 PM PDT 24
Finished Jul 25 07:05:19 PM PDT 24
Peak memory 207296 kb
Host smart-d804eb53-eb52-40c5-866c-a5a8018fc29a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17196
15090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.1719615090
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_device_timeout.3323691382
Short name T233
Test name
Test status
Simulation time 1978605218 ps
CPU time 13.12 seconds
Started Jul 25 07:04:25 PM PDT 24
Finished Jul 25 07:04:39 PM PDT 24
Peak memory 207404 kb
Host smart-fafde2ef-f40e-4b2e-87b4-ff13f1d01e91
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323691382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_timeout.3323691382
Directory /workspace/20.usbdev_device_timeout/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.2441385969
Short name T523
Test name
Test status
Simulation time 384162350 ps
CPU time 1.32 seconds
Started Jul 25 07:04:27 PM PDT 24
Finished Jul 25 07:04:28 PM PDT 24
Peak memory 207088 kb
Host smart-0ee7195b-ec53-4ebe-a62a-5dcfe0f30443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24413
85969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.2441385969
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.1155939360
Short name T2721
Test name
Test status
Simulation time 145175762 ps
CPU time 0.86 seconds
Started Jul 25 07:04:29 PM PDT 24
Finished Jul 25 07:04:30 PM PDT 24
Peak memory 207088 kb
Host smart-1ceb669d-7323-4b10-b54e-c9b06045715b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11559
39360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.1155939360
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.1016433573
Short name T2429
Test name
Test status
Simulation time 33535889 ps
CPU time 0.71 seconds
Started Jul 25 07:04:27 PM PDT 24
Finished Jul 25 07:04:28 PM PDT 24
Peak memory 207084 kb
Host smart-bf0c51cb-e4ca-4ac5-9b33-fbe7e6b4fc15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10164
33573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.1016433573
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.361573264
Short name T551
Test name
Test status
Simulation time 923387873 ps
CPU time 2.3 seconds
Started Jul 25 07:04:26 PM PDT 24
Finished Jul 25 07:04:28 PM PDT 24
Peak memory 207360 kb
Host smart-5b2a4fa0-86d0-400c-9d5d-c7b2db3fbd22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36157
3264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.361573264
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.1959494590
Short name T1468
Test name
Test status
Simulation time 364811301 ps
CPU time 2.44 seconds
Started Jul 25 07:04:26 PM PDT 24
Finished Jul 25 07:04:29 PM PDT 24
Peak memory 207312 kb
Host smart-bc023c28-242e-4f50-b8c5-2195178e2a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19594
94590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.1959494590
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.1641281517
Short name T2011
Test name
Test status
Simulation time 252772535 ps
CPU time 1.23 seconds
Started Jul 25 07:04:28 PM PDT 24
Finished Jul 25 07:04:29 PM PDT 24
Peak memory 207340 kb
Host smart-d6a8e1a3-d4b2-4777-aca7-e7c40e690733
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1641281517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.1641281517
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.3936441238
Short name T1270
Test name
Test status
Simulation time 146493701 ps
CPU time 0.84 seconds
Started Jul 25 07:04:24 PM PDT 24
Finished Jul 25 07:04:25 PM PDT 24
Peak memory 207192 kb
Host smart-8be9c327-9464-40d4-9564-4a1ae19f88fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39364
41238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.3936441238
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.3453683289
Short name T1260
Test name
Test status
Simulation time 175067927 ps
CPU time 0.97 seconds
Started Jul 25 07:04:25 PM PDT 24
Finished Jul 25 07:04:26 PM PDT 24
Peak memory 207228 kb
Host smart-196a0820-5d16-41e1-8fa0-c2f966646cd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34536
83289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.3453683289
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_invalid_sync.2210478263
Short name T704
Test name
Test status
Simulation time 6600884913 ps
CPU time 200.83 seconds
Started Jul 25 07:04:24 PM PDT 24
Finished Jul 25 07:07:45 PM PDT 24
Peak memory 215612 kb
Host smart-7a10b187-4645-407c-94a3-86e30968c5ac
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2210478263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.2210478263
Directory /workspace/20.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.3092178125
Short name T995
Test name
Test status
Simulation time 175666305 ps
CPU time 0.93 seconds
Started Jul 25 07:04:24 PM PDT 24
Finished Jul 25 07:04:25 PM PDT 24
Peak memory 207116 kb
Host smart-f89b499c-25c4-443b-b398-4f803d3fb8da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30921
78125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.3092178125
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.339162057
Short name T2280
Test name
Test status
Simulation time 23277307800 ps
CPU time 29.41 seconds
Started Jul 25 07:04:26 PM PDT 24
Finished Jul 25 07:04:56 PM PDT 24
Peak memory 207372 kb
Host smart-a4884ae3-9551-4c0b-b399-7a49a39bfd7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33916
2057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.339162057
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.1130115887
Short name T577
Test name
Test status
Simulation time 3285029342 ps
CPU time 4.95 seconds
Started Jul 25 07:04:25 PM PDT 24
Finished Jul 25 07:04:30 PM PDT 24
Peak memory 207340 kb
Host smart-ecbb576a-e61b-4d0f-8243-e60af47d38fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11301
15887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.1130115887
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.3353410321
Short name T1957
Test name
Test status
Simulation time 5821122945 ps
CPU time 59.14 seconds
Started Jul 25 07:04:28 PM PDT 24
Finished Jul 25 07:05:27 PM PDT 24
Peak memory 223716 kb
Host smart-6ccf6918-e051-4041-9bf8-72146db8b1b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33534
10321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.3353410321
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.4121573119
Short name T228
Test name
Test status
Simulation time 3833145256 ps
CPU time 40.16 seconds
Started Jul 25 07:04:27 PM PDT 24
Finished Jul 25 07:05:07 PM PDT 24
Peak memory 216740 kb
Host smart-00d73f9a-feb9-4734-a1d1-ff8fb2c3f489
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4121573119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.4121573119
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.3298194562
Short name T1545
Test name
Test status
Simulation time 244530414 ps
CPU time 0.98 seconds
Started Jul 25 07:04:26 PM PDT 24
Finished Jul 25 07:04:27 PM PDT 24
Peak memory 207144 kb
Host smart-3ed16ca6-1250-4234-98a1-86ebc4cf951e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3298194562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.3298194562
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.2729348478
Short name T812
Test name
Test status
Simulation time 204988103 ps
CPU time 0.99 seconds
Started Jul 25 07:04:26 PM PDT 24
Finished Jul 25 07:04:27 PM PDT 24
Peak memory 207180 kb
Host smart-782d75e7-30cb-43a7-88de-9c6e0551c77d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27293
48478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.2729348478
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.4198881214
Short name T1305
Test name
Test status
Simulation time 3797765413 ps
CPU time 40.96 seconds
Started Jul 25 07:04:27 PM PDT 24
Finished Jul 25 07:05:08 PM PDT 24
Peak memory 217208 kb
Host smart-be9b7764-013e-4051-8e3c-e32dda2534cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41988
81214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.4198881214
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.2032698713
Short name T311
Test name
Test status
Simulation time 7716305997 ps
CPU time 59.75 seconds
Started Jul 25 07:04:41 PM PDT 24
Finished Jul 25 07:05:41 PM PDT 24
Peak memory 207424 kb
Host smart-7316fe7c-f4ca-494b-a7e5-f46f85aa266c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2032698713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.2032698713
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.3863229179
Short name T854
Test name
Test status
Simulation time 158940137 ps
CPU time 0.94 seconds
Started Jul 25 07:04:43 PM PDT 24
Finished Jul 25 07:04:45 PM PDT 24
Peak memory 207140 kb
Host smart-0c94efe2-d833-4329-8353-5cf312caf24f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3863229179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.3863229179
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.1051632509
Short name T2059
Test name
Test status
Simulation time 141216162 ps
CPU time 0.9 seconds
Started Jul 25 07:04:42 PM PDT 24
Finished Jul 25 07:04:43 PM PDT 24
Peak memory 207072 kb
Host smart-6f8e0d82-ab5c-4558-b64c-ac8a2517da7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10516
32509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.1051632509
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.2539292948
Short name T1404
Test name
Test status
Simulation time 202046352 ps
CPU time 0.91 seconds
Started Jul 25 07:04:40 PM PDT 24
Finished Jul 25 07:04:41 PM PDT 24
Peak memory 207140 kb
Host smart-7035fa92-d3d5-414c-8fdf-1e067d8f6a1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25392
92948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.2539292948
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.544525920
Short name T1508
Test name
Test status
Simulation time 213279041 ps
CPU time 0.92 seconds
Started Jul 25 07:04:42 PM PDT 24
Finished Jul 25 07:04:43 PM PDT 24
Peak memory 207116 kb
Host smart-1283fd73-2923-4629-8da8-0125d514f50e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54452
5920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.544525920
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.3262629097
Short name T1177
Test name
Test status
Simulation time 181249791 ps
CPU time 0.91 seconds
Started Jul 25 07:04:43 PM PDT 24
Finished Jul 25 07:04:44 PM PDT 24
Peak memory 207148 kb
Host smart-9854b9a0-51fa-4a12-bb39-5917c8be546c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32626
29097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.3262629097
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.3400440768
Short name T2038
Test name
Test status
Simulation time 204935893 ps
CPU time 0.97 seconds
Started Jul 25 07:04:44 PM PDT 24
Finished Jul 25 07:04:46 PM PDT 24
Peak memory 207164 kb
Host smart-d61508a6-2b5f-479e-9560-1afe256e9ca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34004
40768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.3400440768
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.3694124471
Short name T195
Test name
Test status
Simulation time 153008233 ps
CPU time 0.89 seconds
Started Jul 25 07:04:43 PM PDT 24
Finished Jul 25 07:04:44 PM PDT 24
Peak memory 207188 kb
Host smart-e57ad94e-6334-45d3-bb2d-316790e5b7c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36941
24471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.3694124471
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.3762140499
Short name T2144
Test name
Test status
Simulation time 250775992 ps
CPU time 0.98 seconds
Started Jul 25 07:04:46 PM PDT 24
Finished Jul 25 07:04:48 PM PDT 24
Peak memory 207168 kb
Host smart-7d8e1e62-fd88-4855-854f-29e0ba5b5f4a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3762140499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.3762140499
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.3005195582
Short name T1917
Test name
Test status
Simulation time 135342858 ps
CPU time 0.8 seconds
Started Jul 25 07:04:43 PM PDT 24
Finished Jul 25 07:04:44 PM PDT 24
Peak memory 207128 kb
Host smart-6eeb5fe1-12cf-45ce-8ebf-00a965e4e199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30051
95582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.3005195582
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.4037179201
Short name T26
Test name
Test status
Simulation time 80471878 ps
CPU time 0.78 seconds
Started Jul 25 07:04:45 PM PDT 24
Finished Jul 25 07:04:46 PM PDT 24
Peak memory 207084 kb
Host smart-53197428-34cb-4fb2-b9b4-a87590001631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40371
79201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.4037179201
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.1562830225
Short name T1904
Test name
Test status
Simulation time 12380394527 ps
CPU time 30.66 seconds
Started Jul 25 07:04:43 PM PDT 24
Finished Jul 25 07:05:14 PM PDT 24
Peak memory 215620 kb
Host smart-febf0368-4d93-460f-ae2f-9f9f16cc35c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15628
30225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.1562830225
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.4141476118
Short name T2094
Test name
Test status
Simulation time 256280583 ps
CPU time 0.98 seconds
Started Jul 25 07:04:42 PM PDT 24
Finished Jul 25 07:04:43 PM PDT 24
Peak memory 207120 kb
Host smart-3e3bb4b8-8474-4565-8747-01aa658e8b54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41414
76118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.4141476118
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.2567564070
Short name T2494
Test name
Test status
Simulation time 210601785 ps
CPU time 0.96 seconds
Started Jul 25 07:04:42 PM PDT 24
Finished Jul 25 07:04:44 PM PDT 24
Peak memory 207080 kb
Host smart-264a8dc7-7a45-4a57-b4d3-bf348a9eecee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25675
64070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.2567564070
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.2340907729
Short name T2704
Test name
Test status
Simulation time 248377998 ps
CPU time 1.12 seconds
Started Jul 25 07:04:47 PM PDT 24
Finished Jul 25 07:04:48 PM PDT 24
Peak memory 207144 kb
Host smart-8fcb2a8a-d469-4398-bfa8-11fd4438e0e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23409
07729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.2340907729
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.3622514541
Short name T1431
Test name
Test status
Simulation time 167071276 ps
CPU time 0.97 seconds
Started Jul 25 07:04:49 PM PDT 24
Finished Jul 25 07:04:51 PM PDT 24
Peak memory 207112 kb
Host smart-5d910b45-1ae4-4e83-9ac6-8ec995cfb1c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36225
14541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.3622514541
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.3094201035
Short name T2433
Test name
Test status
Simulation time 139040043 ps
CPU time 0.85 seconds
Started Jul 25 07:04:43 PM PDT 24
Finished Jul 25 07:04:45 PM PDT 24
Peak memory 207084 kb
Host smart-39fb9539-564c-428d-a6d2-82e8d8a5879f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30942
01035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.3094201035
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.242056518
Short name T1794
Test name
Test status
Simulation time 157797731 ps
CPU time 0.87 seconds
Started Jul 25 07:04:43 PM PDT 24
Finished Jul 25 07:04:44 PM PDT 24
Peak memory 207092 kb
Host smart-4860fc07-2d97-4610-a076-1d07358904be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24205
6518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.242056518
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.325166391
Short name T2027
Test name
Test status
Simulation time 154897620 ps
CPU time 0.9 seconds
Started Jul 25 07:04:41 PM PDT 24
Finished Jul 25 07:04:42 PM PDT 24
Peak memory 207116 kb
Host smart-bc4d9dd7-78d2-4f63-b021-67cc25e24be4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32516
6391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.325166391
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.2962972306
Short name T2598
Test name
Test status
Simulation time 273634800 ps
CPU time 1.11 seconds
Started Jul 25 07:04:43 PM PDT 24
Finished Jul 25 07:04:45 PM PDT 24
Peak memory 207124 kb
Host smart-7a5c807c-87af-4aff-9000-dec3cac75979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29629
72306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.2962972306
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.3616155601
Short name T1076
Test name
Test status
Simulation time 158259990 ps
CPU time 0.9 seconds
Started Jul 25 07:04:43 PM PDT 24
Finished Jul 25 07:04:45 PM PDT 24
Peak memory 207128 kb
Host smart-92595f4e-ac04-43fe-9134-d82cedd18c53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36161
55601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.3616155601
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.2348102869
Short name T383
Test name
Test status
Simulation time 168627735 ps
CPU time 0.94 seconds
Started Jul 25 07:04:40 PM PDT 24
Finished Jul 25 07:04:41 PM PDT 24
Peak memory 207148 kb
Host smart-e2549a01-c70c-443d-9e07-1993d07111b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23481
02869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.2348102869
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.4274731110
Short name T521
Test name
Test status
Simulation time 754374999 ps
CPU time 2.27 seconds
Started Jul 25 07:04:44 PM PDT 24
Finished Jul 25 07:04:46 PM PDT 24
Peak memory 207104 kb
Host smart-0031aa8c-3562-4ead-ba1b-01ddf8cbf026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42747
31110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.4274731110
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.411548943
Short name T2355
Test name
Test status
Simulation time 7019765255 ps
CPU time 212.86 seconds
Started Jul 25 07:04:42 PM PDT 24
Finished Jul 25 07:08:15 PM PDT 24
Peak memory 215632 kb
Host smart-e5c29a64-7590-4a44-93f3-50c6a54edf84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41154
8943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.411548943
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/20.usbdev_timeout_missing_host_handshake.1517107216
Short name T2656
Test name
Test status
Simulation time 519800246 ps
CPU time 8.35 seconds
Started Jul 25 07:04:25 PM PDT 24
Finished Jul 25 07:04:34 PM PDT 24
Peak memory 207312 kb
Host smart-35c0f769-f1bd-470a-b484-3e94c88e5c03
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517107216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_timeout_missing_hos
t_handshake.1517107216
Directory /workspace/20.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.438090845
Short name T1153
Test name
Test status
Simulation time 36006970 ps
CPU time 0.67 seconds
Started Jul 25 07:04:45 PM PDT 24
Finished Jul 25 07:04:46 PM PDT 24
Peak memory 207124 kb
Host smart-fc29d1e5-6e84-4c5e-ad7a-4b0e9ed95250
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=438090845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.438090845
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.3685978310
Short name T485
Test name
Test status
Simulation time 3458006711 ps
CPU time 5.38 seconds
Started Jul 25 07:04:43 PM PDT 24
Finished Jul 25 07:04:48 PM PDT 24
Peak memory 207360 kb
Host smart-70847708-89f3-4675-b094-5ce540f20d23
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685978310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_a
on_wake_disconnect.3685978310
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.1541869557
Short name T221
Test name
Test status
Simulation time 13385862079 ps
CPU time 15.19 seconds
Started Jul 25 07:04:46 PM PDT 24
Finished Jul 25 07:05:01 PM PDT 24
Peak memory 207412 kb
Host smart-de5a2494-cde8-4ef8-8d3a-0b6e43495d19
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541869557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.1541869557
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.2824621465
Short name T517
Test name
Test status
Simulation time 23329443077 ps
CPU time 29.27 seconds
Started Jul 25 07:04:45 PM PDT 24
Finished Jul 25 07:05:15 PM PDT 24
Peak memory 207396 kb
Host smart-79d31050-5e02-4adb-ba79-db4490b49902
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824621465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_a
on_wake_resume.2824621465
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.1796512386
Short name T450
Test name
Test status
Simulation time 151749806 ps
CPU time 0.97 seconds
Started Jul 25 07:04:49 PM PDT 24
Finished Jul 25 07:04:50 PM PDT 24
Peak memory 207124 kb
Host smart-eaae7340-4515-475a-bd1e-f3c6b070b46a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17965
12386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.1796512386
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.2986755527
Short name T1869
Test name
Test status
Simulation time 144389114 ps
CPU time 0.83 seconds
Started Jul 25 07:04:47 PM PDT 24
Finished Jul 25 07:04:48 PM PDT 24
Peak memory 207116 kb
Host smart-2117138f-6e45-43a5-8c4f-83e26a59e358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29867
55527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.2986755527
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.296801027
Short name T2787
Test name
Test status
Simulation time 187366313 ps
CPU time 1.06 seconds
Started Jul 25 07:04:43 PM PDT 24
Finished Jul 25 07:04:45 PM PDT 24
Peak memory 207120 kb
Host smart-e80b0170-2006-45c9-82d7-febc44b6f8e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29680
1027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.296801027
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.1488675685
Short name T1906
Test name
Test status
Simulation time 828980089 ps
CPU time 2.14 seconds
Started Jul 25 07:04:42 PM PDT 24
Finished Jul 25 07:04:45 PM PDT 24
Peak memory 207112 kb
Host smart-85cae41e-4817-46c6-b71d-36f1c4a7bd9f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1488675685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.1488675685
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.2259371091
Short name T1277
Test name
Test status
Simulation time 15019882773 ps
CPU time 33.1 seconds
Started Jul 25 07:04:49 PM PDT 24
Finished Jul 25 07:05:22 PM PDT 24
Peak memory 207336 kb
Host smart-c79ecc12-4a38-4583-a73a-0722cb24e10f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22593
71091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.2259371091
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_device_timeout.1614941436
Short name T2481
Test name
Test status
Simulation time 866261627 ps
CPU time 18.75 seconds
Started Jul 25 07:04:47 PM PDT 24
Finished Jul 25 07:05:06 PM PDT 24
Peak memory 207364 kb
Host smart-c1d671a4-db38-46c2-9067-cfdfafc95893
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614941436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_timeout.1614941436
Directory /workspace/21.usbdev_device_timeout/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.14831514
Short name T1548
Test name
Test status
Simulation time 412691672 ps
CPU time 1.48 seconds
Started Jul 25 07:04:43 PM PDT 24
Finished Jul 25 07:04:45 PM PDT 24
Peak memory 207156 kb
Host smart-3ad64f7b-a696-4590-a729-612744a3a36b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14831
514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.14831514
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.686987585
Short name T2672
Test name
Test status
Simulation time 138953240 ps
CPU time 0.87 seconds
Started Jul 25 07:04:44 PM PDT 24
Finished Jul 25 07:04:45 PM PDT 24
Peak memory 207088 kb
Host smart-42ffcf5f-162e-472d-bdfc-efaaa681c85e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68698
7585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.686987585
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.2345993442
Short name T1505
Test name
Test status
Simulation time 55674958 ps
CPU time 0.72 seconds
Started Jul 25 07:04:46 PM PDT 24
Finished Jul 25 07:04:47 PM PDT 24
Peak memory 207108 kb
Host smart-403a1248-af2f-4f9d-9cd8-94c79fd01993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23459
93442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.2345993442
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.1357932409
Short name T677
Test name
Test status
Simulation time 855689492 ps
CPU time 2.42 seconds
Started Jul 25 07:04:40 PM PDT 24
Finished Jul 25 07:04:43 PM PDT 24
Peak memory 207276 kb
Host smart-de343fda-376f-4104-87c3-12da8e65adbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13579
32409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.1357932409
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.444391874
Short name T2338
Test name
Test status
Simulation time 386370083 ps
CPU time 2.7 seconds
Started Jul 25 07:04:43 PM PDT 24
Finished Jul 25 07:04:46 PM PDT 24
Peak memory 207208 kb
Host smart-093d081d-3380-4337-acd5-b62bf54611dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44439
1874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.444391874
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.3973617350
Short name T1910
Test name
Test status
Simulation time 196848305 ps
CPU time 1.06 seconds
Started Jul 25 07:04:42 PM PDT 24
Finished Jul 25 07:04:44 PM PDT 24
Peak memory 215508 kb
Host smart-d940c168-ca10-4748-9836-b1f39ae5f735
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3973617350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.3973617350
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.338588357
Short name T2223
Test name
Test status
Simulation time 140800063 ps
CPU time 0.84 seconds
Started Jul 25 07:04:43 PM PDT 24
Finished Jul 25 07:04:44 PM PDT 24
Peak memory 207128 kb
Host smart-b04f937b-5b40-40cc-b199-38368c9256bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33858
8357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.338588357
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.20985141
Short name T1787
Test name
Test status
Simulation time 270107518 ps
CPU time 1.06 seconds
Started Jul 25 07:04:43 PM PDT 24
Finished Jul 25 07:04:45 PM PDT 24
Peak memory 207156 kb
Host smart-36ee1ff4-b67a-45d0-ae0c-6fd81276a6dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20985
141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.20985141
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_invalid_sync.576231482
Short name T2842
Test name
Test status
Simulation time 6365331547 ps
CPU time 179.44 seconds
Started Jul 25 07:05:34 PM PDT 24
Finished Jul 25 07:08:34 PM PDT 24
Peak memory 215600 kb
Host smart-fcd31f38-38f5-4a0f-9dbe-6faea751165b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=576231482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.576231482
Directory /workspace/21.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/21.usbdev_iso_retraction.1435287675
Short name T1932
Test name
Test status
Simulation time 9588576212 ps
CPU time 116.75 seconds
Started Jul 25 07:04:43 PM PDT 24
Finished Jul 25 07:06:40 PM PDT 24
Peak memory 207296 kb
Host smart-4e3951c6-e686-450e-b3b2-5e847ed3dacf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1435287675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_iso_retraction.1435287675
Directory /workspace/21.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.3652415871
Short name T2321
Test name
Test status
Simulation time 204736990 ps
CPU time 0.94 seconds
Started Jul 25 07:04:46 PM PDT 24
Finished Jul 25 07:04:47 PM PDT 24
Peak memory 207128 kb
Host smart-c6a819ac-e08e-455c-bad4-20b0f6e4f429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36524
15871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.3652415871
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.2805954172
Short name T1837
Test name
Test status
Simulation time 23296559812 ps
CPU time 28.87 seconds
Started Jul 25 07:04:45 PM PDT 24
Finished Jul 25 07:05:14 PM PDT 24
Peak memory 207364 kb
Host smart-ef8366d7-0fbf-4af3-994e-b11080ce1bda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28059
54172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.2805954172
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.4214586765
Short name T638
Test name
Test status
Simulation time 3303275542 ps
CPU time 5.32 seconds
Started Jul 25 07:04:44 PM PDT 24
Finished Jul 25 07:04:50 PM PDT 24
Peak memory 207372 kb
Host smart-ff1d1d95-cc04-445b-a9e1-1d2f80628409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42145
86765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.4214586765
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.3619152337
Short name T1755
Test name
Test status
Simulation time 8646284985 ps
CPU time 248.07 seconds
Started Jul 25 07:04:44 PM PDT 24
Finished Jul 25 07:08:53 PM PDT 24
Peak memory 215592 kb
Host smart-8217244f-0e51-448e-b024-a3061e00ee2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36191
52337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.3619152337
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.1300503692
Short name T1490
Test name
Test status
Simulation time 4382234628 ps
CPU time 42.6 seconds
Started Jul 25 07:04:44 PM PDT 24
Finished Jul 25 07:05:27 PM PDT 24
Peak memory 216236 kb
Host smart-32470f3d-d378-427b-ac47-787b314d37e6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1300503692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.1300503692
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.2724078203
Short name T1788
Test name
Test status
Simulation time 278298559 ps
CPU time 1.02 seconds
Started Jul 25 07:04:45 PM PDT 24
Finished Jul 25 07:04:47 PM PDT 24
Peak memory 207080 kb
Host smart-ffdc4a38-b4d1-439d-8b9b-cff6b7693cf0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2724078203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.2724078203
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.805653701
Short name T1519
Test name
Test status
Simulation time 238390458 ps
CPU time 1.03 seconds
Started Jul 25 07:04:45 PM PDT 24
Finished Jul 25 07:04:47 PM PDT 24
Peak memory 207112 kb
Host smart-d0ab4877-6b67-4f8e-a16f-12645759d277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80565
3701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.805653701
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.3259476654
Short name T1625
Test name
Test status
Simulation time 3667397203 ps
CPU time 106.75 seconds
Started Jul 25 07:04:48 PM PDT 24
Finished Jul 25 07:06:35 PM PDT 24
Peak memory 215616 kb
Host smart-c463a44b-4f5c-4021-9179-994e90d685bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32594
76654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.3259476654
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.4216561644
Short name T497
Test name
Test status
Simulation time 6727127370 ps
CPU time 200.59 seconds
Started Jul 25 07:04:46 PM PDT 24
Finished Jul 25 07:08:07 PM PDT 24
Peak memory 215644 kb
Host smart-71d59fc0-46a9-4b4d-adb8-94ef24a21d1d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4216561644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.4216561644
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.773694769
Short name T2513
Test name
Test status
Simulation time 183688921 ps
CPU time 0.89 seconds
Started Jul 25 07:04:46 PM PDT 24
Finished Jul 25 07:04:47 PM PDT 24
Peak memory 207128 kb
Host smart-1bcb5775-690d-400a-8afd-114a52cbc9e5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=773694769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.773694769
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.2334497156
Short name T1437
Test name
Test status
Simulation time 204423618 ps
CPU time 0.88 seconds
Started Jul 25 07:04:49 PM PDT 24
Finished Jul 25 07:04:50 PM PDT 24
Peak memory 207192 kb
Host smart-be61a087-13a5-44b8-a08d-0731252466f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23344
97156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.2334497156
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.4232794202
Short name T1577
Test name
Test status
Simulation time 188600242 ps
CPU time 0.95 seconds
Started Jul 25 07:04:46 PM PDT 24
Finished Jul 25 07:04:47 PM PDT 24
Peak memory 207128 kb
Host smart-391ef9ca-f686-484c-83b6-31f2dcdec09c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42327
94202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.4232794202
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.1475269373
Short name T2540
Test name
Test status
Simulation time 177853648 ps
CPU time 0.92 seconds
Started Jul 25 07:04:49 PM PDT 24
Finished Jul 25 07:04:50 PM PDT 24
Peak memory 207180 kb
Host smart-682b56b9-7a88-48d1-b645-aa6a8871c459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14752
69373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.1475269373
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.1136588971
Short name T1483
Test name
Test status
Simulation time 161889448 ps
CPU time 0.93 seconds
Started Jul 25 07:04:49 PM PDT 24
Finished Jul 25 07:04:50 PM PDT 24
Peak memory 207124 kb
Host smart-fe996625-f12d-4a8c-b9a1-24ab490449c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11365
88971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.1136588971
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.2763200279
Short name T1333
Test name
Test status
Simulation time 166173357 ps
CPU time 0.91 seconds
Started Jul 25 07:04:44 PM PDT 24
Finished Jul 25 07:04:45 PM PDT 24
Peak memory 207108 kb
Host smart-80271ce4-195e-4456-a8df-44826484b5ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27632
00279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.2763200279
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.1708735439
Short name T834
Test name
Test status
Simulation time 169054681 ps
CPU time 0.89 seconds
Started Jul 25 07:04:44 PM PDT 24
Finished Jul 25 07:04:45 PM PDT 24
Peak memory 207104 kb
Host smart-48a09aec-69eb-4396-a95f-0309860011c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17087
35439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.1708735439
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.2138359195
Short name T1792
Test name
Test status
Simulation time 208240124 ps
CPU time 0.99 seconds
Started Jul 25 07:04:45 PM PDT 24
Finished Jul 25 07:04:47 PM PDT 24
Peak memory 207096 kb
Host smart-1ad87476-63c2-4ea6-9a4d-5a6a077973b5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2138359195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.2138359195
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.1667499008
Short name T2132
Test name
Test status
Simulation time 153601754 ps
CPU time 0.84 seconds
Started Jul 25 07:04:45 PM PDT 24
Finished Jul 25 07:04:46 PM PDT 24
Peak memory 207088 kb
Host smart-7bcda3c6-e836-4b58-b797-91f25c1be746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16674
99008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.1667499008
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.2196707290
Short name T2212
Test name
Test status
Simulation time 30305113 ps
CPU time 0.68 seconds
Started Jul 25 07:04:49 PM PDT 24
Finished Jul 25 07:04:50 PM PDT 24
Peak memory 207096 kb
Host smart-ed9c2c92-e3c6-4d74-9f5b-636577288637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21967
07290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.2196707290
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.2555673196
Short name T119
Test name
Test status
Simulation time 18844185732 ps
CPU time 55.31 seconds
Started Jul 25 07:04:49 PM PDT 24
Finished Jul 25 07:05:45 PM PDT 24
Peak memory 215604 kb
Host smart-ea196a28-77eb-42d5-a5ae-93c9efa0d089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25556
73196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.2555673196
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.2090190584
Short name T1929
Test name
Test status
Simulation time 254907893 ps
CPU time 0.97 seconds
Started Jul 25 07:04:45 PM PDT 24
Finished Jul 25 07:04:47 PM PDT 24
Peak memory 207072 kb
Host smart-6c13d363-e1ea-4d2d-a6cf-25386d18f011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20901
90584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.2090190584
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.2694227844
Short name T585
Test name
Test status
Simulation time 180546651 ps
CPU time 0.89 seconds
Started Jul 25 07:04:44 PM PDT 24
Finished Jul 25 07:04:46 PM PDT 24
Peak memory 207088 kb
Host smart-15c30938-7e02-4999-96c9-c954ac027b38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26942
27844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.2694227844
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.2750468845
Short name T1515
Test name
Test status
Simulation time 230006954 ps
CPU time 0.94 seconds
Started Jul 25 07:04:47 PM PDT 24
Finished Jul 25 07:04:48 PM PDT 24
Peak memory 207152 kb
Host smart-273c4d4a-5cd4-4395-9c53-a9a5158f5bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27504
68845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.2750468845
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.2788032785
Short name T2310
Test name
Test status
Simulation time 167275942 ps
CPU time 0.87 seconds
Started Jul 25 07:04:49 PM PDT 24
Finished Jul 25 07:04:50 PM PDT 24
Peak memory 207184 kb
Host smart-6178d1e3-ab48-432a-885b-04ccf4c9c9a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27880
32785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.2788032785
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.2649133588
Short name T1297
Test name
Test status
Simulation time 150599520 ps
CPU time 0.83 seconds
Started Jul 25 07:04:47 PM PDT 24
Finished Jul 25 07:04:48 PM PDT 24
Peak memory 207092 kb
Host smart-84adc652-f5b5-4a76-bcff-e468d650606e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26491
33588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.2649133588
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.3305153062
Short name T2448
Test name
Test status
Simulation time 150834162 ps
CPU time 0.82 seconds
Started Jul 25 07:04:43 PM PDT 24
Finished Jul 25 07:04:44 PM PDT 24
Peak memory 207092 kb
Host smart-3075056c-0086-468a-b0cd-7a68864ba0a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33051
53062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.3305153062
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.180157800
Short name T1700
Test name
Test status
Simulation time 144164222 ps
CPU time 0.87 seconds
Started Jul 25 07:04:46 PM PDT 24
Finished Jul 25 07:04:47 PM PDT 24
Peak memory 207140 kb
Host smart-331f3d4c-9980-42d8-b507-1d642dcdbf28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18015
7800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.180157800
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.3698928374
Short name T1081
Test name
Test status
Simulation time 266250935 ps
CPU time 1.09 seconds
Started Jul 25 07:04:44 PM PDT 24
Finished Jul 25 07:04:45 PM PDT 24
Peak memory 207096 kb
Host smart-969eb7ab-ecaf-4afe-a016-e6675023b269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36989
28374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.3698928374
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.4138550532
Short name T2554
Test name
Test status
Simulation time 4847737602 ps
CPU time 145.03 seconds
Started Jul 25 07:04:46 PM PDT 24
Finished Jul 25 07:07:11 PM PDT 24
Peak memory 215608 kb
Host smart-95f92030-deb2-4762-b2f2-9561cb3422a6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4138550532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.4138550532
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.3602439035
Short name T805
Test name
Test status
Simulation time 209365119 ps
CPU time 0.91 seconds
Started Jul 25 07:04:45 PM PDT 24
Finished Jul 25 07:04:46 PM PDT 24
Peak memory 207148 kb
Host smart-bacdf07a-c644-41ff-9327-0106c1135420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36024
39035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.3602439035
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.3334686040
Short name T1354
Test name
Test status
Simulation time 178616189 ps
CPU time 0.86 seconds
Started Jul 25 07:04:47 PM PDT 24
Finished Jul 25 07:04:48 PM PDT 24
Peak memory 207152 kb
Host smart-58d4aa0c-9efb-4d34-a7d4-1ea4674ff540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33346
86040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.3334686040
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.778972251
Short name T1859
Test name
Test status
Simulation time 435762058 ps
CPU time 1.42 seconds
Started Jul 25 07:04:45 PM PDT 24
Finished Jul 25 07:04:47 PM PDT 24
Peak memory 207132 kb
Host smart-37df4d91-3836-40ef-a829-ac51ef803925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77897
2251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.778972251
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.800203844
Short name T617
Test name
Test status
Simulation time 8498643861 ps
CPU time 258.68 seconds
Started Jul 25 07:04:47 PM PDT 24
Finished Jul 25 07:09:05 PM PDT 24
Peak memory 215624 kb
Host smart-3ef81a16-fbce-477a-8771-8f74ef017b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80020
3844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.800203844
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_timeout_missing_host_handshake.1869421405
Short name T673
Test name
Test status
Simulation time 4958570956 ps
CPU time 35.37 seconds
Started Jul 25 07:04:43 PM PDT 24
Finished Jul 25 07:05:19 PM PDT 24
Peak memory 207412 kb
Host smart-8499a0e7-aade-40f0-a5ee-7422c75eba1f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869421405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_timeout_missing_hos
t_handshake.1869421405
Directory /workspace/21.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.2811103736
Short name T1758
Test name
Test status
Simulation time 59488722 ps
CPU time 0.71 seconds
Started Jul 25 07:05:00 PM PDT 24
Finished Jul 25 07:05:01 PM PDT 24
Peak memory 207196 kb
Host smart-401e9843-f1c7-42a8-b00c-bcb7e616fcb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2811103736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.2811103736
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.2873358942
Short name T2555
Test name
Test status
Simulation time 4193883932 ps
CPU time 6.9 seconds
Started Jul 25 07:04:45 PM PDT 24
Finished Jul 25 07:04:52 PM PDT 24
Peak memory 207388 kb
Host smart-a45a4e2b-cd86-43ac-a2ab-1092cee3641e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873358942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_a
on_wake_disconnect.2873358942
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.131458192
Short name T968
Test name
Test status
Simulation time 13320447839 ps
CPU time 16.21 seconds
Started Jul 25 07:04:55 PM PDT 24
Finished Jul 25 07:05:11 PM PDT 24
Peak memory 207396 kb
Host smart-67b1db6b-d2f6-4260-9822-38c5a34b6f76
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=131458192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.131458192
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.866857223
Short name T1457
Test name
Test status
Simulation time 23493497121 ps
CPU time 28.76 seconds
Started Jul 25 07:04:54 PM PDT 24
Finished Jul 25 07:05:23 PM PDT 24
Peak memory 207388 kb
Host smart-3ec6b837-637b-4302-b326-8d979b95b76b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866857223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_ao
n_wake_resume.866857223
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.1675979706
Short name T974
Test name
Test status
Simulation time 165189858 ps
CPU time 0.85 seconds
Started Jul 25 07:04:57 PM PDT 24
Finished Jul 25 07:04:58 PM PDT 24
Peak memory 207188 kb
Host smart-f378b56a-639c-49cb-a3d3-44949d1af3c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16759
79706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.1675979706
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.2867697504
Short name T2572
Test name
Test status
Simulation time 176824346 ps
CPU time 0.85 seconds
Started Jul 25 07:04:54 PM PDT 24
Finished Jul 25 07:04:55 PM PDT 24
Peak memory 207108 kb
Host smart-f5f2cfaa-84ef-4d64-9221-0cbb5d6490cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28676
97504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.2867697504
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.2864211345
Short name T1064
Test name
Test status
Simulation time 381217271 ps
CPU time 1.47 seconds
Started Jul 25 07:04:56 PM PDT 24
Finished Jul 25 07:04:57 PM PDT 24
Peak memory 207152 kb
Host smart-631aceab-b4f8-45f0-9ae3-dcf1681034d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28642
11345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.2864211345
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.34880313
Short name T2237
Test name
Test status
Simulation time 938683080 ps
CPU time 2.51 seconds
Started Jul 25 07:04:56 PM PDT 24
Finished Jul 25 07:04:59 PM PDT 24
Peak memory 207292 kb
Host smart-09fa50b2-aa7b-4e4e-b455-4ac7a61a008b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=34880313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.34880313
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.1205348614
Short name T967
Test name
Test status
Simulation time 19539194966 ps
CPU time 49.33 seconds
Started Jul 25 07:04:56 PM PDT 24
Finished Jul 25 07:05:45 PM PDT 24
Peak memory 207376 kb
Host smart-50ec6771-4405-4e3d-96bc-bc15167cdbf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12053
48614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.1205348614
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_device_timeout.3677816476
Short name T2608
Test name
Test status
Simulation time 813788084 ps
CPU time 15.62 seconds
Started Jul 25 07:04:57 PM PDT 24
Finished Jul 25 07:05:13 PM PDT 24
Peak memory 207348 kb
Host smart-17354d7b-99f0-401f-8a79-fd0bd73a3df2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677816476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_timeout.3677816476
Directory /workspace/22.usbdev_device_timeout/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.4081813723
Short name T1785
Test name
Test status
Simulation time 302867450 ps
CPU time 1.2 seconds
Started Jul 25 07:04:58 PM PDT 24
Finished Jul 25 07:04:59 PM PDT 24
Peak memory 207108 kb
Host smart-4b9cb69d-a3a8-4e9e-8b19-a1c749c7443a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40818
13723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.4081813723
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.2845950599
Short name T1896
Test name
Test status
Simulation time 145923001 ps
CPU time 0.81 seconds
Started Jul 25 07:04:56 PM PDT 24
Finished Jul 25 07:04:57 PM PDT 24
Peak memory 207128 kb
Host smart-778e1fc8-00d5-4b07-aa01-b581d1af2c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28459
50599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.2845950599
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.1443295008
Short name T1399
Test name
Test status
Simulation time 28568043 ps
CPU time 0.73 seconds
Started Jul 25 07:04:59 PM PDT 24
Finished Jul 25 07:05:01 PM PDT 24
Peak memory 207112 kb
Host smart-8ee9e709-5775-46c7-9c45-858be0befc6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14432
95008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.1443295008
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.1138195880
Short name T334
Test name
Test status
Simulation time 885384712 ps
CPU time 2.47 seconds
Started Jul 25 07:04:58 PM PDT 24
Finished Jul 25 07:05:01 PM PDT 24
Peak memory 207380 kb
Host smart-b424db26-8064-4bf6-901f-a653f8d437e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11381
95880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.1138195880
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.860631297
Short name T1538
Test name
Test status
Simulation time 234333617 ps
CPU time 1.67 seconds
Started Jul 25 07:04:53 PM PDT 24
Finished Jul 25 07:04:55 PM PDT 24
Peak memory 207356 kb
Host smart-78f47e06-e85a-4f9d-9a2a-ef165f9cfa1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86063
1297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.860631297
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.4115606204
Short name T1775
Test name
Test status
Simulation time 194834135 ps
CPU time 1.04 seconds
Started Jul 25 07:04:53 PM PDT 24
Finished Jul 25 07:04:54 PM PDT 24
Peak memory 215532 kb
Host smart-13459d54-53d9-44d4-a634-a52070bea779
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4115606204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.4115606204
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.1522826968
Short name T2798
Test name
Test status
Simulation time 199817453 ps
CPU time 0.9 seconds
Started Jul 25 07:04:59 PM PDT 24
Finished Jul 25 07:05:00 PM PDT 24
Peak memory 207200 kb
Host smart-76b81e2b-a8a3-4f4d-ae22-c8878e67f652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15228
26968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.1522826968
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.3802799516
Short name T1463
Test name
Test status
Simulation time 180731187 ps
CPU time 0.95 seconds
Started Jul 25 07:05:00 PM PDT 24
Finished Jul 25 07:05:01 PM PDT 24
Peak memory 207072 kb
Host smart-91020a51-373a-4935-8b47-9cefa524db16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38027
99516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.3802799516
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.1880571687
Short name T975
Test name
Test status
Simulation time 7809623616 ps
CPU time 80.91 seconds
Started Jul 25 07:04:55 PM PDT 24
Finished Jul 25 07:06:16 PM PDT 24
Peak memory 215588 kb
Host smart-60c78ae2-0ae7-424e-96f3-534a65b06087
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1880571687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.1880571687
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_iso_retraction.2695380306
Short name T2470
Test name
Test status
Simulation time 6042869137 ps
CPU time 40.3 seconds
Started Jul 25 07:04:56 PM PDT 24
Finished Jul 25 07:05:37 PM PDT 24
Peak memory 207324 kb
Host smart-666e2643-47da-48c7-a9b9-c03129b6da1a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2695380306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.2695380306
Directory /workspace/22.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.1420916505
Short name T950
Test name
Test status
Simulation time 275364440 ps
CPU time 1.13 seconds
Started Jul 25 07:04:59 PM PDT 24
Finished Jul 25 07:05:00 PM PDT 24
Peak memory 207236 kb
Host smart-01858707-8143-4c9d-bcd7-a6119f00e111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14209
16505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.1420916505
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.3498629246
Short name T2106
Test name
Test status
Simulation time 23315670535 ps
CPU time 27.72 seconds
Started Jul 25 07:04:59 PM PDT 24
Finished Jul 25 07:05:27 PM PDT 24
Peak memory 207388 kb
Host smart-57e7a54b-c466-4faa-a020-69054a58b2f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34986
29246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.3498629246
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.1281871408
Short name T1800
Test name
Test status
Simulation time 3356749833 ps
CPU time 5.1 seconds
Started Jul 25 07:04:59 PM PDT 24
Finished Jul 25 07:05:05 PM PDT 24
Peak memory 207408 kb
Host smart-497e4491-13f2-45d9-9d91-823bafccfe58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12818
71408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.1281871408
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.223053959
Short name T1852
Test name
Test status
Simulation time 10181882642 ps
CPU time 305.12 seconds
Started Jul 25 07:04:55 PM PDT 24
Finished Jul 25 07:10:01 PM PDT 24
Peak memory 215532 kb
Host smart-901102b4-4277-4fb8-adab-b463c74592b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22305
3959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.223053959
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.4204546873
Short name T2006
Test name
Test status
Simulation time 6220117529 ps
CPU time 182.3 seconds
Started Jul 25 07:04:58 PM PDT 24
Finished Jul 25 07:08:01 PM PDT 24
Peak memory 215528 kb
Host smart-8a4a3feb-f9e2-4b16-9325-a4ff13513cc8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4204546873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.4204546873
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.3068258551
Short name T1798
Test name
Test status
Simulation time 233985787 ps
CPU time 0.93 seconds
Started Jul 25 07:04:58 PM PDT 24
Finished Jul 25 07:04:59 PM PDT 24
Peak memory 207144 kb
Host smart-374246c6-4d99-4c5b-92d7-82b31d5be76b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3068258551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.3068258551
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.1691203856
Short name T416
Test name
Test status
Simulation time 190194689 ps
CPU time 0.93 seconds
Started Jul 25 07:04:59 PM PDT 24
Finished Jul 25 07:05:01 PM PDT 24
Peak memory 207156 kb
Host smart-15f1a4b2-0249-4faf-b4b4-5b55971b9c39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16912
03856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.1691203856
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.938905268
Short name T1810
Test name
Test status
Simulation time 5259942669 ps
CPU time 39.46 seconds
Started Jul 25 07:04:56 PM PDT 24
Finished Jul 25 07:05:36 PM PDT 24
Peak memory 215604 kb
Host smart-cc6ba3da-2729-4352-aa03-4e422779b757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93890
5268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.938905268
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.2297638512
Short name T1063
Test name
Test status
Simulation time 4433380305 ps
CPU time 128.55 seconds
Started Jul 25 07:04:55 PM PDT 24
Finished Jul 25 07:07:04 PM PDT 24
Peak memory 215552 kb
Host smart-987d7628-ddc3-49f7-9a1d-57f4cf7ecde3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2297638512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.2297638512
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.909423955
Short name T882
Test name
Test status
Simulation time 212784031 ps
CPU time 0.96 seconds
Started Jul 25 07:05:00 PM PDT 24
Finished Jul 25 07:05:01 PM PDT 24
Peak memory 207076 kb
Host smart-e2a929dc-eee9-4552-9430-d74b49e18026
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=909423955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.909423955
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.4285318080
Short name T1582
Test name
Test status
Simulation time 173139514 ps
CPU time 0.87 seconds
Started Jul 25 07:05:00 PM PDT 24
Finished Jul 25 07:05:01 PM PDT 24
Peak memory 207144 kb
Host smart-c8c835fa-8f73-4ada-8f2b-bb871d62b47d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42853
18080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.4285318080
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.146673592
Short name T2258
Test name
Test status
Simulation time 198375641 ps
CPU time 0.96 seconds
Started Jul 25 07:05:01 PM PDT 24
Finished Jul 25 07:05:02 PM PDT 24
Peak memory 207144 kb
Host smart-a894efb9-3307-4726-9d65-1c85bce6a4d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14667
3592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.146673592
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.3108061877
Short name T2652
Test name
Test status
Simulation time 156644977 ps
CPU time 0.85 seconds
Started Jul 25 07:04:53 PM PDT 24
Finished Jul 25 07:04:54 PM PDT 24
Peak memory 207124 kb
Host smart-6e75d02d-1532-426b-ba2b-be7dd463c441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31080
61877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.3108061877
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.2789367247
Short name T871
Test name
Test status
Simulation time 198173705 ps
CPU time 0.93 seconds
Started Jul 25 07:04:58 PM PDT 24
Finished Jul 25 07:04:59 PM PDT 24
Peak memory 207124 kb
Host smart-2f3fad55-45fc-4312-8495-f25ce54f8b55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27893
67247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.2789367247
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.1362692412
Short name T2457
Test name
Test status
Simulation time 152630520 ps
CPU time 0.85 seconds
Started Jul 25 07:04:56 PM PDT 24
Finished Jul 25 07:04:57 PM PDT 24
Peak memory 207128 kb
Host smart-9a79813d-a397-4fd1-9b6c-65cdad8f5465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13626
92412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.1362692412
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.4218087935
Short name T2165
Test name
Test status
Simulation time 202925310 ps
CPU time 0.99 seconds
Started Jul 25 07:04:56 PM PDT 24
Finished Jul 25 07:04:57 PM PDT 24
Peak memory 207124 kb
Host smart-b77eaa56-a010-41c7-a6e0-a8e849e85cce
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4218087935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.4218087935
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.2121799425
Short name T1232
Test name
Test status
Simulation time 138980311 ps
CPU time 0.86 seconds
Started Jul 25 07:04:55 PM PDT 24
Finished Jul 25 07:04:56 PM PDT 24
Peak memory 207084 kb
Host smart-3089fbb5-4e32-41ec-b1bd-c50b1f83a0e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21217
99425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.2121799425
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.2079151573
Short name T727
Test name
Test status
Simulation time 81533770 ps
CPU time 0.78 seconds
Started Jul 25 07:04:55 PM PDT 24
Finished Jul 25 07:04:56 PM PDT 24
Peak memory 207084 kb
Host smart-7e475454-c027-4908-acb8-0284109e388c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20791
51573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.2079151573
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.3819637545
Short name T313
Test name
Test status
Simulation time 21823542829 ps
CPU time 52.64 seconds
Started Jul 25 07:04:57 PM PDT 24
Finished Jul 25 07:05:50 PM PDT 24
Peak memory 220620 kb
Host smart-9839140c-9d37-42f4-aeb2-50ab06c9b6a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38196
37545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.3819637545
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.197157675
Short name T1295
Test name
Test status
Simulation time 208740722 ps
CPU time 1.02 seconds
Started Jul 25 07:04:57 PM PDT 24
Finished Jul 25 07:04:58 PM PDT 24
Peak memory 207124 kb
Host smart-5a6a94ff-fe5e-46d3-a2ed-80630ae5a510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19715
7675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.197157675
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.994007532
Short name T2050
Test name
Test status
Simulation time 221493380 ps
CPU time 1.01 seconds
Started Jul 25 07:04:56 PM PDT 24
Finished Jul 25 07:04:57 PM PDT 24
Peak memory 207092 kb
Host smart-efa71e63-9026-4e5a-b067-9907d0e876dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99400
7532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.994007532
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.2737301617
Short name T432
Test name
Test status
Simulation time 220216309 ps
CPU time 0.99 seconds
Started Jul 25 07:04:57 PM PDT 24
Finished Jul 25 07:04:58 PM PDT 24
Peak memory 207124 kb
Host smart-ddb0a98a-5436-4c99-894d-0bd7c2861666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27373
01617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.2737301617
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.1457932670
Short name T1628
Test name
Test status
Simulation time 203902091 ps
CPU time 0.92 seconds
Started Jul 25 07:04:55 PM PDT 24
Finished Jul 25 07:04:56 PM PDT 24
Peak memory 207132 kb
Host smart-fc656bd4-14a9-48cf-b033-bf65cef8286c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14579
32670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.1457932670
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.3329753808
Short name T1651
Test name
Test status
Simulation time 151673058 ps
CPU time 0.86 seconds
Started Jul 25 07:05:00 PM PDT 24
Finished Jul 25 07:05:01 PM PDT 24
Peak memory 207044 kb
Host smart-c0f9ce03-7774-4dd1-b20b-0e132eea5d2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33297
53808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.3329753808
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.1421667737
Short name T1827
Test name
Test status
Simulation time 188669717 ps
CPU time 0.96 seconds
Started Jul 25 07:04:59 PM PDT 24
Finished Jul 25 07:05:00 PM PDT 24
Peak memory 207116 kb
Host smart-45a63de0-9636-4b7a-8f78-185d50680442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14216
67737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.1421667737
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.3598426418
Short name T2350
Test name
Test status
Simulation time 236881874 ps
CPU time 1.07 seconds
Started Jul 25 07:04:56 PM PDT 24
Finished Jul 25 07:04:57 PM PDT 24
Peak memory 207104 kb
Host smart-6e99119e-1597-4f0e-8986-fb31ded1c305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35984
26418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.3598426418
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.796329632
Short name T2080
Test name
Test status
Simulation time 4973991404 ps
CPU time 37.52 seconds
Started Jul 25 07:04:58 PM PDT 24
Finished Jul 25 07:05:36 PM PDT 24
Peak memory 217040 kb
Host smart-d4000a53-36d3-4cbe-8b62-34f8c5042a60
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=796329632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.796329632
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.4161453004
Short name T1420
Test name
Test status
Simulation time 154602901 ps
CPU time 0.91 seconds
Started Jul 25 07:04:55 PM PDT 24
Finished Jul 25 07:04:56 PM PDT 24
Peak memory 207096 kb
Host smart-fe4eee44-5038-4913-a81e-082ac33197c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41614
53004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.4161453004
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.2916522474
Short name T1557
Test name
Test status
Simulation time 184159784 ps
CPU time 0.9 seconds
Started Jul 25 07:04:58 PM PDT 24
Finished Jul 25 07:05:00 PM PDT 24
Peak memory 207108 kb
Host smart-abfdeb69-1d10-4c6f-9a37-a1ee2d6a8d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29165
22474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.2916522474
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.2048607260
Short name T2657
Test name
Test status
Simulation time 1351931627 ps
CPU time 3.17 seconds
Started Jul 25 07:04:55 PM PDT 24
Finished Jul 25 07:04:59 PM PDT 24
Peak memory 207296 kb
Host smart-e70d1e5a-48f9-4c9a-8335-453088a2343f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20486
07260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.2048607260
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.3547900095
Short name T2858
Test name
Test status
Simulation time 3681975553 ps
CPU time 32.3 seconds
Started Jul 25 07:04:57 PM PDT 24
Finished Jul 25 07:05:29 PM PDT 24
Peak memory 217092 kb
Host smart-b874a427-b8b6-4520-bae7-310f7c413556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35479
00095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.3547900095
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_timeout_missing_host_handshake.2095091541
Short name T781
Test name
Test status
Simulation time 6169386181 ps
CPU time 44.94 seconds
Started Jul 25 07:04:55 PM PDT 24
Finished Jul 25 07:05:40 PM PDT 24
Peak memory 207336 kb
Host smart-d0e199d6-4eb2-4cf9-aee1-6403de6e108d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095091541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_timeout_missing_hos
t_handshake.2095091541
Directory /workspace/22.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.3186886167
Short name T2064
Test name
Test status
Simulation time 32441071 ps
CPU time 0.67 seconds
Started Jul 25 07:05:03 PM PDT 24
Finished Jul 25 07:05:04 PM PDT 24
Peak memory 207176 kb
Host smart-f436dbe0-0af8-4eff-863b-4aca57a9c9f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3186886167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.3186886167
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.2592306181
Short name T14
Test name
Test status
Simulation time 4425659254 ps
CPU time 7.39 seconds
Started Jul 25 07:04:58 PM PDT 24
Finished Jul 25 07:05:06 PM PDT 24
Peak memory 207356 kb
Host smart-3a37ec3f-7280-44fc-9bc6-a208ecff32cf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592306181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_a
on_wake_disconnect.2592306181
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.1545698961
Short name T2863
Test name
Test status
Simulation time 13434532731 ps
CPU time 17.53 seconds
Started Jul 25 07:04:56 PM PDT 24
Finished Jul 25 07:05:14 PM PDT 24
Peak memory 207448 kb
Host smart-97ea0276-8a5e-4d43-9ffd-de3139eb6551
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545698961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.1545698961
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.2224832525
Short name T671
Test name
Test status
Simulation time 23353607346 ps
CPU time 31.48 seconds
Started Jul 25 07:05:05 PM PDT 24
Finished Jul 25 07:05:36 PM PDT 24
Peak memory 207368 kb
Host smart-ab0039ff-15bd-40b0-ae32-0cba4fc5155f
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224832525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_a
on_wake_resume.2224832525
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.3295293791
Short name T420
Test name
Test status
Simulation time 151416670 ps
CPU time 0.86 seconds
Started Jul 25 07:04:58 PM PDT 24
Finished Jul 25 07:04:59 PM PDT 24
Peak memory 207120 kb
Host smart-271aff0a-ce17-474f-9e9f-8e96d0f0e5d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32952
93791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.3295293791
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.2352810562
Short name T1109
Test name
Test status
Simulation time 146308933 ps
CPU time 0.85 seconds
Started Jul 25 07:04:59 PM PDT 24
Finished Jul 25 07:05:00 PM PDT 24
Peak memory 207076 kb
Host smart-235c5a40-2132-442b-bcfc-732b337ef8fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23528
10562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.2352810562
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.1562002784
Short name T1065
Test name
Test status
Simulation time 234306295 ps
CPU time 1.04 seconds
Started Jul 25 07:04:56 PM PDT 24
Finished Jul 25 07:04:58 PM PDT 24
Peak memory 207048 kb
Host smart-3cb493c4-e3fb-43c0-8887-11ca51e83794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15620
02784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.1562002784
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.2969383968
Short name T2354
Test name
Test status
Simulation time 1285120439 ps
CPU time 3.41 seconds
Started Jul 25 07:04:59 PM PDT 24
Finished Jul 25 07:05:03 PM PDT 24
Peak memory 207424 kb
Host smart-3dd08151-fa92-4129-bdba-81548725cc77
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2969383968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.2969383968
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.655611852
Short name T190
Test name
Test status
Simulation time 15427910931 ps
CPU time 38.69 seconds
Started Jul 25 07:05:00 PM PDT 24
Finished Jul 25 07:05:39 PM PDT 24
Peak memory 207328 kb
Host smart-a34f150a-a6f1-4952-ae15-f27a512db0f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65561
1852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.655611852
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_device_timeout.450373273
Short name T905
Test name
Test status
Simulation time 4303211197 ps
CPU time 30 seconds
Started Jul 25 07:04:53 PM PDT 24
Finished Jul 25 07:05:23 PM PDT 24
Peak memory 207416 kb
Host smart-4e44b723-1dce-48ff-b136-7d53631d1509
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450373273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_timeout.450373273
Directory /workspace/23.usbdev_device_timeout/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.2556050347
Short name T1883
Test name
Test status
Simulation time 488793275 ps
CPU time 1.69 seconds
Started Jul 25 07:05:00 PM PDT 24
Finished Jul 25 07:05:02 PM PDT 24
Peak memory 207116 kb
Host smart-a6fbeffe-ca0e-44f1-8b0d-f34f00b8a28c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25560
50347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.2556050347
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.38890942
Short name T1579
Test name
Test status
Simulation time 137044707 ps
CPU time 0.89 seconds
Started Jul 25 07:04:59 PM PDT 24
Finished Jul 25 07:05:00 PM PDT 24
Peak memory 207040 kb
Host smart-cfe5a531-892d-47eb-bf88-78dbdf29c474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38890
942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.38890942
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.3924131222
Short name T917
Test name
Test status
Simulation time 36530125 ps
CPU time 0.72 seconds
Started Jul 25 07:04:55 PM PDT 24
Finished Jul 25 07:04:56 PM PDT 24
Peak memory 207096 kb
Host smart-cf790fe3-6185-4390-9f85-54f4b9cedc17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39241
31222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.3924131222
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.2460826203
Short name T1971
Test name
Test status
Simulation time 818967775 ps
CPU time 2.45 seconds
Started Jul 25 07:04:59 PM PDT 24
Finished Jul 25 07:05:02 PM PDT 24
Peak memory 207240 kb
Host smart-bc46d6c2-165e-4b8d-9246-441ea5dc4713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24608
26203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.2460826203
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.1521247702
Short name T1783
Test name
Test status
Simulation time 194433574 ps
CPU time 1.92 seconds
Started Jul 25 07:04:58 PM PDT 24
Finished Jul 25 07:05:00 PM PDT 24
Peak memory 207140 kb
Host smart-9a67e163-0a2d-4520-b7a5-f2086bebf626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15212
47702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.1521247702
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.159450705
Short name T2157
Test name
Test status
Simulation time 192399786 ps
CPU time 1.03 seconds
Started Jul 25 07:05:05 PM PDT 24
Finished Jul 25 07:05:06 PM PDT 24
Peak memory 215516 kb
Host smart-348acadd-9d39-43f9-ad73-b0bd4968d998
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=159450705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.159450705
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.3451345243
Short name T811
Test name
Test status
Simulation time 148514811 ps
CPU time 0.83 seconds
Started Jul 25 07:05:05 PM PDT 24
Finished Jul 25 07:05:06 PM PDT 24
Peak memory 207080 kb
Host smart-133c10c6-a351-4f30-9393-5686849e5c90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34513
45243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.3451345243
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.3207670132
Short name T1888
Test name
Test status
Simulation time 296696861 ps
CPU time 1.06 seconds
Started Jul 25 07:04:56 PM PDT 24
Finished Jul 25 07:04:58 PM PDT 24
Peak memory 207216 kb
Host smart-e44401e6-4874-401a-8f9f-50c5d495bc43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32076
70132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.3207670132
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.479402861
Short name T1169
Test name
Test status
Simulation time 7152573806 ps
CPU time 216.04 seconds
Started Jul 25 07:04:59 PM PDT 24
Finished Jul 25 07:08:35 PM PDT 24
Peak memory 215588 kb
Host smart-df024361-9eb3-48dd-aae4-ab121796a803
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=479402861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.479402861
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.2393010310
Short name T707
Test name
Test status
Simulation time 234112531 ps
CPU time 1.04 seconds
Started Jul 25 07:05:00 PM PDT 24
Finished Jul 25 07:05:01 PM PDT 24
Peak memory 207188 kb
Host smart-690de77f-3762-4b0c-abb4-70b03095ebc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23930
10310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.2393010310
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.1904335616
Short name T1175
Test name
Test status
Simulation time 23362376152 ps
CPU time 31.38 seconds
Started Jul 25 07:04:59 PM PDT 24
Finished Jul 25 07:05:31 PM PDT 24
Peak memory 207360 kb
Host smart-67369e4b-0135-4599-a947-4f0d0f8db0df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19043
35616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.1904335616
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.536591432
Short name T494
Test name
Test status
Simulation time 3273337970 ps
CPU time 4.84 seconds
Started Jul 25 07:04:59 PM PDT 24
Finished Jul 25 07:05:04 PM PDT 24
Peak memory 207384 kb
Host smart-9dfbd84a-d880-41ea-a759-0faedd1e2943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53659
1432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.536591432
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.1405795619
Short name T2529
Test name
Test status
Simulation time 4166072164 ps
CPU time 40.79 seconds
Started Jul 25 07:04:58 PM PDT 24
Finished Jul 25 07:05:39 PM PDT 24
Peak memory 207288 kb
Host smart-a1c4c214-2599-4dd6-a7ae-0c447d8405b1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1405795619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.1405795619
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.1186925593
Short name T1994
Test name
Test status
Simulation time 245411979 ps
CPU time 1.01 seconds
Started Jul 25 07:04:57 PM PDT 24
Finished Jul 25 07:04:58 PM PDT 24
Peak memory 207140 kb
Host smart-2286d058-e087-4c07-a2fc-8322d1954208
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1186925593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.1186925593
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.3080405284
Short name T1874
Test name
Test status
Simulation time 187020414 ps
CPU time 0.98 seconds
Started Jul 25 07:04:59 PM PDT 24
Finished Jul 25 07:05:00 PM PDT 24
Peak memory 207132 kb
Host smart-be366fc9-b68a-49a9-80f2-c7a1e0cc0819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30804
05284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.3080405284
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.3405918465
Short name T1680
Test name
Test status
Simulation time 4361680398 ps
CPU time 33.07 seconds
Started Jul 25 07:04:59 PM PDT 24
Finished Jul 25 07:05:33 PM PDT 24
Peak memory 215588 kb
Host smart-65962ec1-2109-4db6-8520-cf721dff4e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34059
18465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.3405918465
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.939294252
Short name T634
Test name
Test status
Simulation time 4517473251 ps
CPU time 36.21 seconds
Started Jul 25 07:05:00 PM PDT 24
Finished Jul 25 07:05:36 PM PDT 24
Peak memory 207424 kb
Host smart-efd3d031-d399-4237-9f7d-9c87e94dde1a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=939294252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.939294252
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.804323892
Short name T1450
Test name
Test status
Simulation time 208120315 ps
CPU time 0.94 seconds
Started Jul 25 07:05:00 PM PDT 24
Finished Jul 25 07:05:01 PM PDT 24
Peak memory 207144 kb
Host smart-e9e8dfdb-02ee-4e87-9e9e-cb2c74b89a54
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=804323892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.804323892
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.364069526
Short name T1149
Test name
Test status
Simulation time 154615088 ps
CPU time 0.91 seconds
Started Jul 25 07:05:02 PM PDT 24
Finished Jul 25 07:05:03 PM PDT 24
Peak memory 207196 kb
Host smart-d633d506-56dc-4500-bde1-800c84431091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36406
9526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.364069526
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.3437178660
Short name T1344
Test name
Test status
Simulation time 225750779 ps
CPU time 0.95 seconds
Started Jul 25 07:04:58 PM PDT 24
Finished Jul 25 07:04:59 PM PDT 24
Peak memory 207124 kb
Host smart-3cc36f28-cd9c-4089-9db7-75316afb3959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34371
78660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.3437178660
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.1253772686
Short name T1449
Test name
Test status
Simulation time 187434987 ps
CPU time 0.99 seconds
Started Jul 25 07:05:00 PM PDT 24
Finished Jul 25 07:05:01 PM PDT 24
Peak memory 207116 kb
Host smart-a0c49d7f-9864-4ad0-845c-d36e101ba566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12537
72686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.1253772686
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.1625414636
Short name T846
Test name
Test status
Simulation time 198248415 ps
CPU time 0.89 seconds
Started Jul 25 07:04:58 PM PDT 24
Finished Jul 25 07:05:00 PM PDT 24
Peak memory 207116 kb
Host smart-c563c7d6-9e10-4b8a-8cb7-0222e4cc554c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16254
14636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.1625414636
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.8558756
Short name T2645
Test name
Test status
Simulation time 182872851 ps
CPU time 0.89 seconds
Started Jul 25 07:04:58 PM PDT 24
Finished Jul 25 07:04:59 PM PDT 24
Peak memory 207128 kb
Host smart-d45052fd-9fef-4e46-ae65-ebf8cd22e693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85587
56 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.8558756
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.1363305652
Short name T2533
Test name
Test status
Simulation time 169605033 ps
CPU time 0.9 seconds
Started Jul 25 07:04:59 PM PDT 24
Finished Jul 25 07:05:01 PM PDT 24
Peak memory 207108 kb
Host smart-3c39e3c7-f112-4815-836b-faadd51c5c18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13633
05652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.1363305652
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.473177864
Short name T471
Test name
Test status
Simulation time 202405286 ps
CPU time 1.03 seconds
Started Jul 25 07:04:59 PM PDT 24
Finished Jul 25 07:05:00 PM PDT 24
Peak memory 207092 kb
Host smart-cfad58eb-55c8-4ae7-8ff0-018383c5f592
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=473177864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.473177864
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.2992005482
Short name T1528
Test name
Test status
Simulation time 143943651 ps
CPU time 0.86 seconds
Started Jul 25 07:05:01 PM PDT 24
Finished Jul 25 07:05:03 PM PDT 24
Peak memory 207164 kb
Host smart-6f656b8e-c4ae-4d16-9c0e-4be52420bfc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29920
05482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.2992005482
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.3699773880
Short name T2640
Test name
Test status
Simulation time 43902567 ps
CPU time 0.71 seconds
Started Jul 25 07:05:02 PM PDT 24
Finished Jul 25 07:05:02 PM PDT 24
Peak memory 207080 kb
Host smart-8dcb326c-aa13-4e00-88e6-340d77fca228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36997
73880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.3699773880
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.3443893789
Short name T1427
Test name
Test status
Simulation time 13209880366 ps
CPU time 34.93 seconds
Started Jul 25 07:05:09 PM PDT 24
Finished Jul 25 07:05:44 PM PDT 24
Peak memory 215592 kb
Host smart-0d09a633-8bee-4de6-8514-5ee217d79b5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34438
93789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.3443893789
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.3856416452
Short name T1443
Test name
Test status
Simulation time 187945868 ps
CPU time 0.88 seconds
Started Jul 25 07:05:06 PM PDT 24
Finished Jul 25 07:05:07 PM PDT 24
Peak memory 207108 kb
Host smart-6da0c338-75b4-4187-847c-2d9189264960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38564
16452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.3856416452
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.2601512854
Short name T742
Test name
Test status
Simulation time 186542610 ps
CPU time 0.91 seconds
Started Jul 25 07:05:14 PM PDT 24
Finished Jul 25 07:05:15 PM PDT 24
Peak memory 207128 kb
Host smart-ea4273ca-b854-44a2-ba8d-ae81e68f83b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26015
12854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.2601512854
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.1562785970
Short name T1434
Test name
Test status
Simulation time 189898874 ps
CPU time 0.89 seconds
Started Jul 25 07:05:07 PM PDT 24
Finished Jul 25 07:05:08 PM PDT 24
Peak memory 207136 kb
Host smart-fe8b79ac-9207-4d9f-9f3f-5c5acd399078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15627
85970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.1562785970
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.1359927389
Short name T1569
Test name
Test status
Simulation time 227316319 ps
CPU time 0.98 seconds
Started Jul 25 07:05:14 PM PDT 24
Finished Jul 25 07:05:15 PM PDT 24
Peak memory 207172 kb
Host smart-5a014ace-b594-482d-a974-e6e7886a50a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13599
27389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.1359927389
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.3290451374
Short name T1304
Test name
Test status
Simulation time 204305273 ps
CPU time 0.89 seconds
Started Jul 25 07:08:50 PM PDT 24
Finished Jul 25 07:08:51 PM PDT 24
Peak memory 207112 kb
Host smart-2b6750d4-8637-4a9c-9f46-5172ef068d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32904
51374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.3290451374
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.2354897142
Short name T1474
Test name
Test status
Simulation time 149047685 ps
CPU time 0.85 seconds
Started Jul 25 07:05:08 PM PDT 24
Finished Jul 25 07:05:09 PM PDT 24
Peak memory 207104 kb
Host smart-a9230b04-d3ba-4438-a096-a28db2149314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23548
97142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.2354897142
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.1453787754
Short name T2401
Test name
Test status
Simulation time 142936516 ps
CPU time 0.88 seconds
Started Jul 25 07:05:07 PM PDT 24
Finished Jul 25 07:05:08 PM PDT 24
Peak memory 207216 kb
Host smart-eb6944a9-c58c-442e-b2eb-282d42b2fbc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14537
87754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.1453787754
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.3223650418
Short name T2647
Test name
Test status
Simulation time 171788022 ps
CPU time 0.94 seconds
Started Jul 25 07:05:04 PM PDT 24
Finished Jul 25 07:05:05 PM PDT 24
Peak memory 207208 kb
Host smart-e1872ff8-7cca-4246-ad57-9446c61361d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32236
50418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.3223650418
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.1157552480
Short name T2834
Test name
Test status
Simulation time 3703714443 ps
CPU time 31.31 seconds
Started Jul 25 07:05:07 PM PDT 24
Finished Jul 25 07:05:39 PM PDT 24
Peak memory 215664 kb
Host smart-ada15850-5731-4990-ac6d-edd4e8250220
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1157552480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.1157552480
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.4124166142
Short name T909
Test name
Test status
Simulation time 198084388 ps
CPU time 0.98 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:05:17 PM PDT 24
Peak memory 207100 kb
Host smart-8f905f9a-5e06-487e-b4ab-f6152bc652ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41241
66142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.4124166142
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.1558396143
Short name T1586
Test name
Test status
Simulation time 169673707 ps
CPU time 0.86 seconds
Started Jul 25 07:05:08 PM PDT 24
Finished Jul 25 07:05:09 PM PDT 24
Peak memory 207136 kb
Host smart-b6eb8d76-0a93-46ea-9ecd-642120d51396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15583
96143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.1558396143
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.1813954512
Short name T1318
Test name
Test status
Simulation time 969582709 ps
CPU time 2.54 seconds
Started Jul 25 07:05:10 PM PDT 24
Finished Jul 25 07:05:12 PM PDT 24
Peak memory 207264 kb
Host smart-2e235e93-5055-4c31-b5fb-803e46b14bf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18139
54512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.1813954512
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.3321233780
Short name T2101
Test name
Test status
Simulation time 5544541214 ps
CPU time 164.52 seconds
Started Jul 25 07:05:59 PM PDT 24
Finished Jul 25 07:08:44 PM PDT 24
Peak memory 215608 kb
Host smart-8c081f53-996d-4fd1-b64f-befdbc4f8ae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33212
33780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.3321233780
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_timeout_missing_host_handshake.1192929793
Short name T1445
Test name
Test status
Simulation time 179922432 ps
CPU time 0.96 seconds
Started Jul 25 07:04:57 PM PDT 24
Finished Jul 25 07:04:58 PM PDT 24
Peak memory 207116 kb
Host smart-c6c77b56-a1ae-4e5a-b662-72e9e8cff2ce
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192929793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_timeout_missing_hos
t_handshake.1192929793
Directory /workspace/23.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.854070388
Short name T1543
Test name
Test status
Simulation time 45603560 ps
CPU time 0.7 seconds
Started Jul 25 07:05:11 PM PDT 24
Finished Jul 25 07:05:12 PM PDT 24
Peak memory 207152 kb
Host smart-0f9d87fd-83b7-4f21-b654-bfd354ac886d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=854070388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.854070388
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.823321776
Short name T736
Test name
Test status
Simulation time 3693245089 ps
CPU time 6.31 seconds
Started Jul 25 07:05:11 PM PDT 24
Finished Jul 25 07:05:18 PM PDT 24
Peak memory 207392 kb
Host smart-fcf837e7-e347-4d58-9636-a2b56702bb5d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823321776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_ao
n_wake_disconnect.823321776
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.2965940615
Short name T601
Test name
Test status
Simulation time 13373383455 ps
CPU time 19.44 seconds
Started Jul 25 07:05:07 PM PDT 24
Finished Jul 25 07:05:26 PM PDT 24
Peak memory 207456 kb
Host smart-60dd62c7-f8cc-496b-a519-fb01984df3dd
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965940615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.2965940615
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.1366818106
Short name T2534
Test name
Test status
Simulation time 23361638834 ps
CPU time 32.17 seconds
Started Jul 25 07:05:09 PM PDT 24
Finished Jul 25 07:05:41 PM PDT 24
Peak memory 207372 kb
Host smart-cf0916db-58cb-40c6-9ea5-9c69e2ea60e9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366818106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_a
on_wake_resume.1366818106
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.4080644466
Short name T740
Test name
Test status
Simulation time 170323469 ps
CPU time 0.86 seconds
Started Jul 25 07:05:12 PM PDT 24
Finished Jul 25 07:05:13 PM PDT 24
Peak memory 207152 kb
Host smart-3cfe8ea3-b9ca-42e2-902a-c00dfacb4296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40806
44466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.4080644466
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.2836690094
Short name T1376
Test name
Test status
Simulation time 157867801 ps
CPU time 0.88 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:05:16 PM PDT 24
Peak memory 207136 kb
Host smart-e0741e7f-4945-4fa0-b5fa-148a1b364848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28366
90094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.2836690094
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.952809935
Short name T2455
Test name
Test status
Simulation time 284554748 ps
CPU time 1.23 seconds
Started Jul 25 07:05:16 PM PDT 24
Finished Jul 25 07:05:17 PM PDT 24
Peak memory 207180 kb
Host smart-95d7777f-cd68-4d43-8fdf-1031f1fc07cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95280
9935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.952809935
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.3766421907
Short name T97
Test name
Test status
Simulation time 935143116 ps
CPU time 2.66 seconds
Started Jul 25 07:05:07 PM PDT 24
Finished Jul 25 07:05:10 PM PDT 24
Peak memory 207320 kb
Host smart-43c02d80-4950-4c21-95e5-878c5a0b9186
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3766421907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.3766421907
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.986842757
Short name T2715
Test name
Test status
Simulation time 14750502002 ps
CPU time 33.18 seconds
Started Jul 25 07:05:12 PM PDT 24
Finished Jul 25 07:05:46 PM PDT 24
Peak memory 207368 kb
Host smart-c5e24ff0-0862-4370-982e-f2f3eee5b9ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98684
2757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.986842757
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_device_timeout.301268312
Short name T949
Test name
Test status
Simulation time 1150912910 ps
CPU time 26.54 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:05:42 PM PDT 24
Peak memory 207348 kb
Host smart-825a833d-69c3-43ab-be33-40359eb6b93a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301268312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_timeout.301268312
Directory /workspace/24.usbdev_device_timeout/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.2090449217
Short name T632
Test name
Test status
Simulation time 481959792 ps
CPU time 1.6 seconds
Started Jul 25 07:05:08 PM PDT 24
Finished Jul 25 07:05:09 PM PDT 24
Peak memory 207104 kb
Host smart-36190237-2d9a-4691-a0af-db0b7e5bb911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20904
49217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.2090449217
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.235960347
Short name T1728
Test name
Test status
Simulation time 134594941 ps
CPU time 0.82 seconds
Started Jul 25 07:05:09 PM PDT 24
Finished Jul 25 07:05:10 PM PDT 24
Peak memory 207100 kb
Host smart-fb5cb0d2-732f-45ee-9d25-8c01aac61132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23596
0347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.235960347
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.1741668988
Short name T2055
Test name
Test status
Simulation time 31810186 ps
CPU time 0.69 seconds
Started Jul 25 07:05:02 PM PDT 24
Finished Jul 25 07:05:03 PM PDT 24
Peak memory 207080 kb
Host smart-577bbbad-c139-4c1e-87ad-3dece52cd4d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17416
68988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.1741668988
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.1611513496
Short name T1254
Test name
Test status
Simulation time 927039125 ps
CPU time 2.63 seconds
Started Jul 25 07:05:03 PM PDT 24
Finished Jul 25 07:05:05 PM PDT 24
Peak memory 207372 kb
Host smart-2b4f0206-5baf-4865-bc22-6dc783b01acc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16115
13496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.1611513496
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.1239793822
Short name T1962
Test name
Test status
Simulation time 305818106 ps
CPU time 1.89 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:05:18 PM PDT 24
Peak memory 207280 kb
Host smart-942516e9-1b2f-4791-b1db-b9c74ac89cea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12397
93822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.1239793822
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.2752132790
Short name T1423
Test name
Test status
Simulation time 230540471 ps
CPU time 1.2 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:05:16 PM PDT 24
Peak memory 215540 kb
Host smart-1ab617f8-eb5f-4918-ab37-346c959ca425
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2752132790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.2752132790
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.3866080143
Short name T1705
Test name
Test status
Simulation time 154747004 ps
CPU time 0.87 seconds
Started Jul 25 07:05:03 PM PDT 24
Finished Jul 25 07:05:04 PM PDT 24
Peak memory 207112 kb
Host smart-19eeab71-0412-41ea-a31b-2c8559bafd53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38660
80143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.3866080143
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.2071839835
Short name T1362
Test name
Test status
Simulation time 217641780 ps
CPU time 0.98 seconds
Started Jul 25 07:05:08 PM PDT 24
Finished Jul 25 07:05:09 PM PDT 24
Peak memory 207132 kb
Host smart-fe618c96-9856-46c5-be6d-7307f75b56bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20718
39835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.2071839835
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.2750050301
Short name T1379
Test name
Test status
Simulation time 7315485304 ps
CPU time 75.06 seconds
Started Jul 25 07:05:14 PM PDT 24
Finished Jul 25 07:06:29 PM PDT 24
Peak memory 215644 kb
Host smart-3f625a0c-87f0-4c56-a130-df64f81d6a33
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2750050301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.2750050301
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_iso_retraction.817246663
Short name T2681
Test name
Test status
Simulation time 4540955192 ps
CPU time 54.24 seconds
Started Jul 25 07:05:17 PM PDT 24
Finished Jul 25 07:06:11 PM PDT 24
Peak memory 207388 kb
Host smart-f70e8a02-cec7-484c-bcd8-1cc486e7794b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=817246663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_iso_retraction.817246663
Directory /workspace/24.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.3347427689
Short name T1514
Test name
Test status
Simulation time 206616291 ps
CPU time 0.97 seconds
Started Jul 25 07:05:10 PM PDT 24
Finished Jul 25 07:05:11 PM PDT 24
Peak memory 207112 kb
Host smart-415abab6-8eab-4e40-8906-d3856411ee5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33474
27689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.3347427689
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.1213652048
Short name T335
Test name
Test status
Simulation time 23307383812 ps
CPU time 32 seconds
Started Jul 25 07:05:04 PM PDT 24
Finished Jul 25 07:05:36 PM PDT 24
Peak memory 207368 kb
Host smart-549031be-94de-46d5-9018-5ea439f7776a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12136
52048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.1213652048
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.2034442154
Short name T2601
Test name
Test status
Simulation time 3319795652 ps
CPU time 5.7 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:05:21 PM PDT 24
Peak memory 207376 kb
Host smart-0088c56c-f651-4a6a-953e-63b71e951876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20344
42154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.2034442154
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.281957316
Short name T2492
Test name
Test status
Simulation time 6237405508 ps
CPU time 61.94 seconds
Started Jul 25 07:05:14 PM PDT 24
Finished Jul 25 07:06:16 PM PDT 24
Peak memory 217616 kb
Host smart-a74b6dfa-e7f0-4180-a1d6-361558d89c2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28195
7316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.281957316
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.938147017
Short name T1930
Test name
Test status
Simulation time 3970258141 ps
CPU time 117.15 seconds
Started Jul 25 07:05:30 PM PDT 24
Finished Jul 25 07:07:27 PM PDT 24
Peak memory 223472 kb
Host smart-9fdad23f-0f7b-425e-8971-d50841664142
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=938147017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.938147017
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.3879767154
Short name T1523
Test name
Test status
Simulation time 262106382 ps
CPU time 1.07 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:05:17 PM PDT 24
Peak memory 207136 kb
Host smart-4276c32d-d115-49d9-8722-37ea01c777d3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3879767154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.3879767154
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.2597174811
Short name T714
Test name
Test status
Simulation time 197850488 ps
CPU time 0.92 seconds
Started Jul 25 07:05:12 PM PDT 24
Finished Jul 25 07:05:13 PM PDT 24
Peak memory 207172 kb
Host smart-31ec5b2a-df9c-4ab5-ac31-f696834b4b28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25971
74811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.2597174811
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.1832070677
Short name T2251
Test name
Test status
Simulation time 3516081534 ps
CPU time 36.05 seconds
Started Jul 25 07:05:07 PM PDT 24
Finished Jul 25 07:05:43 PM PDT 24
Peak memory 217236 kb
Host smart-650fa635-d976-47a7-a1e9-7c08197eb023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18320
70677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.1832070677
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.2369549990
Short name T2342
Test name
Test status
Simulation time 3268149944 ps
CPU time 25.74 seconds
Started Jul 25 07:05:11 PM PDT 24
Finished Jul 25 07:05:37 PM PDT 24
Peak memory 217164 kb
Host smart-bc518324-6e72-434d-b496-907021ecad17
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2369549990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.2369549990
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.2128878872
Short name T1054
Test name
Test status
Simulation time 149911393 ps
CPU time 0.81 seconds
Started Jul 25 07:05:02 PM PDT 24
Finished Jul 25 07:05:03 PM PDT 24
Peak memory 207148 kb
Host smart-c8c2a897-f18c-440f-ae67-e1a8b8d3fcb3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2128878872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.2128878872
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.2551625242
Short name T2211
Test name
Test status
Simulation time 162409381 ps
CPU time 0.89 seconds
Started Jul 25 07:05:04 PM PDT 24
Finished Jul 25 07:05:05 PM PDT 24
Peak memory 207140 kb
Host smart-7c221e83-9e82-43f7-b4f2-44f4484c759c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25516
25242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.2551625242
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.4257645604
Short name T132
Test name
Test status
Simulation time 203622090 ps
CPU time 0.9 seconds
Started Jul 25 07:05:13 PM PDT 24
Finished Jul 25 07:05:14 PM PDT 24
Peak memory 207168 kb
Host smart-53f2dcfa-bfb1-4282-a98e-04872263445c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42576
45604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.4257645604
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.2445982655
Short name T582
Test name
Test status
Simulation time 160107695 ps
CPU time 0.88 seconds
Started Jul 25 07:05:09 PM PDT 24
Finished Jul 25 07:05:10 PM PDT 24
Peak memory 207072 kb
Host smart-21d12d59-d50c-4e70-9d94-2bac0284f0f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24459
82655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.2445982655
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.2429040859
Short name T1989
Test name
Test status
Simulation time 176827846 ps
CPU time 0.88 seconds
Started Jul 25 07:05:10 PM PDT 24
Finished Jul 25 07:05:11 PM PDT 24
Peak memory 207108 kb
Host smart-277f4bca-5d9e-4f92-aaff-4babc128dd61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24290
40859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.2429040859
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.1446704197
Short name T1945
Test name
Test status
Simulation time 182714307 ps
CPU time 0.99 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:05:17 PM PDT 24
Peak memory 207124 kb
Host smart-9c96b41b-af56-4ea5-a73f-7b46407a3992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14467
04197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.1446704197
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.1814736085
Short name T1259
Test name
Test status
Simulation time 160447858 ps
CPU time 0.91 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:05:16 PM PDT 24
Peak memory 207124 kb
Host smart-df547fae-cf4c-4da4-9f93-744e376f5603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18147
36085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.1814736085
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.3321387005
Short name T259
Test name
Test status
Simulation time 263890776 ps
CPU time 1.05 seconds
Started Jul 25 07:05:09 PM PDT 24
Finished Jul 25 07:05:10 PM PDT 24
Peak memory 207092 kb
Host smart-f6af8bbc-04ea-468d-b876-8552c4774792
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3321387005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.3321387005
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.215037374
Short name T784
Test name
Test status
Simulation time 152261612 ps
CPU time 0.88 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:05:17 PM PDT 24
Peak memory 207116 kb
Host smart-f14181bc-319f-4376-b485-c84bc2c5d75e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21503
7374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.215037374
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.935265721
Short name T2227
Test name
Test status
Simulation time 38496051 ps
CPU time 0.71 seconds
Started Jul 25 07:05:14 PM PDT 24
Finished Jul 25 07:05:15 PM PDT 24
Peak memory 207096 kb
Host smart-57cbf8cc-4ba4-400b-8566-f8ddb03ca719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93526
5721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.935265721
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.2484391945
Short name T2551
Test name
Test status
Simulation time 22472445381 ps
CPU time 53.11 seconds
Started Jul 25 07:05:14 PM PDT 24
Finished Jul 25 07:06:08 PM PDT 24
Peak memory 215624 kb
Host smart-e5843c5f-5949-45af-935f-4f20e36659de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24843
91945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.2484391945
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.1673413213
Short name T2103
Test name
Test status
Simulation time 184515519 ps
CPU time 0.95 seconds
Started Jul 25 07:05:03 PM PDT 24
Finished Jul 25 07:05:04 PM PDT 24
Peak memory 207108 kb
Host smart-0a32bdca-aefb-4a7c-9044-6f78e610f2af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16734
13213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.1673413213
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.3931311621
Short name T2259
Test name
Test status
Simulation time 162845881 ps
CPU time 0.9 seconds
Started Jul 25 07:05:04 PM PDT 24
Finished Jul 25 07:05:05 PM PDT 24
Peak memory 207116 kb
Host smart-75aad1b0-ac35-4f4c-a657-7bf4653bde7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39313
11621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.3931311621
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.3476815682
Short name T662
Test name
Test status
Simulation time 163347029 ps
CPU time 0.88 seconds
Started Jul 25 07:05:03 PM PDT 24
Finished Jul 25 07:05:04 PM PDT 24
Peak memory 207140 kb
Host smart-484934d8-70fd-4fc3-8341-61d2f8f217fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34768
15682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.3476815682
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.3387714070
Short name T804
Test name
Test status
Simulation time 174597282 ps
CPU time 0.97 seconds
Started Jul 25 07:05:42 PM PDT 24
Finished Jul 25 07:05:43 PM PDT 24
Peak memory 207168 kb
Host smart-4b279294-9444-473a-9677-95b2e61f61e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33877
14070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.3387714070
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.80060617
Short name T1127
Test name
Test status
Simulation time 156804047 ps
CPU time 0.86 seconds
Started Jul 25 07:05:10 PM PDT 24
Finished Jul 25 07:05:11 PM PDT 24
Peak memory 206964 kb
Host smart-e1292474-af8b-48cd-9acb-3ae8d5afbb11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80060
617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.80060617
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.1224697416
Short name T915
Test name
Test status
Simulation time 154365924 ps
CPU time 0.9 seconds
Started Jul 25 07:05:09 PM PDT 24
Finished Jul 25 07:05:10 PM PDT 24
Peak memory 207080 kb
Host smart-7f25d53a-6efc-463d-92dc-23c975db9f3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12246
97416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.1224697416
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.2174334636
Short name T1740
Test name
Test status
Simulation time 151751029 ps
CPU time 0.85 seconds
Started Jul 25 07:05:08 PM PDT 24
Finished Jul 25 07:05:09 PM PDT 24
Peak memory 207064 kb
Host smart-f594bef2-0be5-4a86-8a3d-058b6a6cf2eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21743
34636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.2174334636
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.3298437044
Short name T1236
Test name
Test status
Simulation time 219680690 ps
CPU time 1.04 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:05:17 PM PDT 24
Peak memory 207088 kb
Host smart-7cb7668c-0e20-442d-aeb5-f48fe19166d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32984
37044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.3298437044
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.702789865
Short name T801
Test name
Test status
Simulation time 3068482319 ps
CPU time 23.7 seconds
Started Jul 25 07:05:12 PM PDT 24
Finished Jul 25 07:05:36 PM PDT 24
Peak memory 217216 kb
Host smart-8bb1924e-38d6-43a8-89a6-dd37b68c6fe5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=702789865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.702789865
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.1959491316
Short name T2199
Test name
Test status
Simulation time 186788269 ps
CPU time 0.9 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:05:16 PM PDT 24
Peak memory 207120 kb
Host smart-dea66664-229d-4f7c-a77b-3bab1d4e6028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19594
91316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.1959491316
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.2201476326
Short name T1908
Test name
Test status
Simulation time 210408596 ps
CPU time 0.88 seconds
Started Jul 25 07:05:14 PM PDT 24
Finished Jul 25 07:05:15 PM PDT 24
Peak memory 207120 kb
Host smart-f09e251a-14de-4c75-bca7-c27bcfc1eab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22014
76326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.2201476326
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.2474965152
Short name T1633
Test name
Test status
Simulation time 650833719 ps
CPU time 1.74 seconds
Started Jul 25 07:05:16 PM PDT 24
Finished Jul 25 07:05:18 PM PDT 24
Peak memory 207120 kb
Host smart-749483f8-f516-4cfe-9b15-aa4570253e24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24749
65152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.2474965152
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.1816068173
Short name T2124
Test name
Test status
Simulation time 5571866614 ps
CPU time 161.67 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:07:57 PM PDT 24
Peak memory 215564 kb
Host smart-5d50f652-2424-4e69-8d67-4d2c3f30ae92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18160
68173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.1816068173
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_timeout_missing_host_handshake.1154409785
Short name T2095
Test name
Test status
Simulation time 2038423046 ps
CPU time 18.13 seconds
Started Jul 25 07:05:12 PM PDT 24
Finished Jul 25 07:05:30 PM PDT 24
Peak memory 207328 kb
Host smart-5c9dfc3f-4930-4a48-bdbc-7e743bf8901b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154409785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_timeout_missing_hos
t_handshake.1154409785
Directory /workspace/24.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.2504184567
Short name T1138
Test name
Test status
Simulation time 34100753 ps
CPU time 0.67 seconds
Started Jul 25 07:05:22 PM PDT 24
Finished Jul 25 07:05:23 PM PDT 24
Peak memory 207196 kb
Host smart-dae11e10-9474-4956-8edc-a2ea752d1e5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2504184567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.2504184567
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.874301334
Short name T1777
Test name
Test status
Simulation time 4355166178 ps
CPU time 6.09 seconds
Started Jul 25 07:05:14 PM PDT 24
Finished Jul 25 07:05:21 PM PDT 24
Peak memory 207360 kb
Host smart-be5172af-afb6-4eed-a119-914f6187e7a9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874301334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_ao
n_wake_disconnect.874301334
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.1050622980
Short name T2696
Test name
Test status
Simulation time 13300977153 ps
CPU time 17.18 seconds
Started Jul 25 07:05:13 PM PDT 24
Finished Jul 25 07:05:30 PM PDT 24
Peak memory 207464 kb
Host smart-d01151f1-7b6a-4160-bb1f-e844cbf4a180
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050622980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.1050622980
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.1334537047
Short name T1592
Test name
Test status
Simulation time 23348525575 ps
CPU time 26.31 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:05:42 PM PDT 24
Peak memory 207344 kb
Host smart-58b6208f-3590-432e-b9b5-9258e3745cbe
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334537047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_a
on_wake_resume.1334537047
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.3843462760
Short name T978
Test name
Test status
Simulation time 170367473 ps
CPU time 0.89 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:05:16 PM PDT 24
Peak memory 207128 kb
Host smart-2f6e6841-3e26-402f-a122-acddc48d136b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38434
62760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.3843462760
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.210589712
Short name T1021
Test name
Test status
Simulation time 145493105 ps
CPU time 0.8 seconds
Started Jul 25 07:05:12 PM PDT 24
Finished Jul 25 07:05:12 PM PDT 24
Peak memory 207092 kb
Host smart-c7525649-1873-468b-b8b5-8d68f5da9771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21058
9712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.210589712
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.1255443317
Short name T522
Test name
Test status
Simulation time 369890681 ps
CPU time 1.42 seconds
Started Jul 25 07:05:13 PM PDT 24
Finished Jul 25 07:05:15 PM PDT 24
Peak memory 207104 kb
Host smart-4ee8a345-c94d-4aba-b270-bf7f08491a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12554
43317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.1255443317
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.3682229643
Short name T1855
Test name
Test status
Simulation time 409840537 ps
CPU time 1.27 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:05:16 PM PDT 24
Peak memory 207124 kb
Host smart-bc0fba22-81a4-421f-8a4c-55bd0ce42198
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3682229643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.3682229643
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.1797952215
Short name T1481
Test name
Test status
Simulation time 6606348274 ps
CPU time 15.65 seconds
Started Jul 25 07:05:16 PM PDT 24
Finished Jul 25 07:05:32 PM PDT 24
Peak memory 207340 kb
Host smart-80dbb9d5-9c24-4bf6-86c1-958f95c1db49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17979
52215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.1797952215
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_device_timeout.2211201735
Short name T483
Test name
Test status
Simulation time 4994835506 ps
CPU time 33.74 seconds
Started Jul 25 07:05:13 PM PDT 24
Finished Jul 25 07:05:46 PM PDT 24
Peak memory 207444 kb
Host smart-5096c870-ce23-48e2-973b-3910b0284599
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211201735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_timeout.2211201735
Directory /workspace/25.usbdev_device_timeout/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.427027840
Short name T303
Test name
Test status
Simulation time 449631860 ps
CPU time 1.5 seconds
Started Jul 25 07:05:17 PM PDT 24
Finished Jul 25 07:05:18 PM PDT 24
Peak memory 207196 kb
Host smart-ddaecf14-b7bc-4b67-8ef4-29ec6de1087e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42702
7840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.427027840
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.4127979946
Short name T2441
Test name
Test status
Simulation time 137079199 ps
CPU time 0.81 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:05:17 PM PDT 24
Peak memory 207020 kb
Host smart-e001e7ae-fee0-4523-936b-d33621708296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41279
79946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.4127979946
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.2130850011
Short name T1912
Test name
Test status
Simulation time 45220793 ps
CPU time 0.72 seconds
Started Jul 25 07:05:14 PM PDT 24
Finished Jul 25 07:05:15 PM PDT 24
Peak memory 207044 kb
Host smart-07c565dc-a92f-477a-8869-9bd72b417f69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21308
50011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.2130850011
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.1338102229
Short name T445
Test name
Test status
Simulation time 814487166 ps
CPU time 2.16 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:05:18 PM PDT 24
Peak memory 207304 kb
Host smart-322958e1-dc91-4b4b-8126-59c21216a9c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13381
02229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.1338102229
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.2375409261
Short name T2323
Test name
Test status
Simulation time 209341098 ps
CPU time 2.75 seconds
Started Jul 25 07:05:16 PM PDT 24
Finished Jul 25 07:05:19 PM PDT 24
Peak memory 207264 kb
Host smart-f0410884-6e7e-43d2-a66c-f01bff16c78d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23754
09261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.2375409261
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.3857811885
Short name T1
Test name
Test status
Simulation time 189786392 ps
CPU time 1.04 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:05:17 PM PDT 24
Peak memory 215624 kb
Host smart-f0245739-2e92-48d4-b33c-c13ceb5cca1a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3857811885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.3857811885
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.4270420584
Short name T2829
Test name
Test status
Simulation time 150897469 ps
CPU time 0.83 seconds
Started Jul 25 07:05:14 PM PDT 24
Finished Jul 25 07:05:16 PM PDT 24
Peak memory 207052 kb
Host smart-deb5a759-b25c-4d05-870f-68992af071a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42704
20584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.4270420584
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.1369963643
Short name T2414
Test name
Test status
Simulation time 168015553 ps
CPU time 0.86 seconds
Started Jul 25 07:05:20 PM PDT 24
Finished Jul 25 07:05:21 PM PDT 24
Peak memory 206964 kb
Host smart-468a2452-4197-4f2c-a2e5-800cfcea71a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13699
63643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.1369963643
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.3202577360
Short name T760
Test name
Test status
Simulation time 5601875610 ps
CPU time 167.66 seconds
Started Jul 25 07:05:17 PM PDT 24
Finished Jul 25 07:08:05 PM PDT 24
Peak memory 215556 kb
Host smart-5d307648-b3f1-43f9-94d5-584642dc0d3e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3202577360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.3202577360
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_iso_retraction.2977544624
Short name T50
Test name
Test status
Simulation time 11036203205 ps
CPU time 76.96 seconds
Started Jul 25 07:05:14 PM PDT 24
Finished Jul 25 07:06:31 PM PDT 24
Peak memory 207364 kb
Host smart-561636c5-e38e-4272-a703-3463303ff31a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2977544624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_iso_retraction.2977544624
Directory /workspace/25.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.1950962849
Short name T1141
Test name
Test status
Simulation time 173519789 ps
CPU time 0.94 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:05:17 PM PDT 24
Peak memory 207116 kb
Host smart-5d3a9167-0b1d-4f01-8750-c7c511014bdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19509
62849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.1950962849
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.2002644953
Short name T872
Test name
Test status
Simulation time 23375593938 ps
CPU time 33.09 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:05:49 PM PDT 24
Peak memory 207336 kb
Host smart-acf54c49-1199-4917-9bbe-3cbf5d179af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20026
44953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.2002644953
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.694901795
Short name T42
Test name
Test status
Simulation time 3311046465 ps
CPU time 5.09 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:05:21 PM PDT 24
Peak memory 207324 kb
Host smart-abf99b98-19cb-4fe2-a5c0-1d35bbd77bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69490
1795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.694901795
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.2377912243
Short name T1207
Test name
Test status
Simulation time 6488671234 ps
CPU time 192.1 seconds
Started Jul 25 07:05:13 PM PDT 24
Finished Jul 25 07:08:25 PM PDT 24
Peak memory 215648 kb
Host smart-d4dc58ba-0532-40d6-884c-5c77b198e325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23779
12243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.2377912243
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.3008843174
Short name T891
Test name
Test status
Simulation time 6134099054 ps
CPU time 63.22 seconds
Started Jul 25 07:05:17 PM PDT 24
Finished Jul 25 07:06:20 PM PDT 24
Peak memory 207388 kb
Host smart-f91750e9-0bbd-4c6b-bcd9-d004e3649fc9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3008843174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.3008843174
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.3797453591
Short name T702
Test name
Test status
Simulation time 256402319 ps
CPU time 1.03 seconds
Started Jul 25 07:05:16 PM PDT 24
Finished Jul 25 07:05:17 PM PDT 24
Peak memory 207152 kb
Host smart-c1c2ddf7-de8d-4cc3-84cc-dcfe32d9400c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3797453591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.3797453591
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.2587180737
Short name T2325
Test name
Test status
Simulation time 188826015 ps
CPU time 1.01 seconds
Started Jul 25 07:05:13 PM PDT 24
Finished Jul 25 07:05:14 PM PDT 24
Peak memory 207144 kb
Host smart-90e8cd3c-701f-4ad1-a79f-d8cbbe58e406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25871
80737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.2587180737
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.1089983156
Short name T2468
Test name
Test status
Simulation time 6804390905 ps
CPU time 70 seconds
Started Jul 25 07:05:17 PM PDT 24
Finished Jul 25 07:06:27 PM PDT 24
Peak memory 217196 kb
Host smart-4d4ab548-0a3f-4b18-ae2e-aea6fe6b2b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10899
83156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.1089983156
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.2403383363
Short name T1228
Test name
Test status
Simulation time 5255101006 ps
CPU time 54.17 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:06:10 PM PDT 24
Peak memory 216852 kb
Host smart-52e55611-742c-4279-8458-e959f89d2466
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2403383363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.2403383363
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.156351931
Short name T1503
Test name
Test status
Simulation time 155856460 ps
CPU time 0.89 seconds
Started Jul 25 07:05:13 PM PDT 24
Finished Jul 25 07:05:14 PM PDT 24
Peak memory 207116 kb
Host smart-c2d84615-07c0-42ec-87c2-6ad818539316
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=156351931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.156351931
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.426862418
Short name T2014
Test name
Test status
Simulation time 215692341 ps
CPU time 1 seconds
Started Jul 25 07:05:17 PM PDT 24
Finished Jul 25 07:05:18 PM PDT 24
Peak memory 207148 kb
Host smart-24610b07-e746-42d6-b2d1-8d30b54c226e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42686
2418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.426862418
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.1036402968
Short name T150
Test name
Test status
Simulation time 185425203 ps
CPU time 0.89 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:05:17 PM PDT 24
Peak memory 207136 kb
Host smart-0b1df18f-22e0-4aa3-b251-fe91f750dbea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10364
02968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.1036402968
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.758902778
Short name T2077
Test name
Test status
Simulation time 228185331 ps
CPU time 1 seconds
Started Jul 25 07:05:14 PM PDT 24
Finished Jul 25 07:05:15 PM PDT 24
Peak memory 207112 kb
Host smart-a66f2504-1662-432f-b359-6f0650eb6408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75890
2778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.758902778
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.1570101156
Short name T1160
Test name
Test status
Simulation time 178473648 ps
CPU time 0.93 seconds
Started Jul 25 07:05:14 PM PDT 24
Finished Jul 25 07:05:15 PM PDT 24
Peak memory 207120 kb
Host smart-4f5310b7-c54b-46fb-965d-f9b971914f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15701
01156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.1570101156
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.646942750
Short name T1966
Test name
Test status
Simulation time 156083291 ps
CPU time 0.84 seconds
Started Jul 25 07:05:21 PM PDT 24
Finished Jul 25 07:05:22 PM PDT 24
Peak memory 206480 kb
Host smart-2bf5aa08-5811-4854-92ee-f6d78d76ee37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64694
2750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.646942750
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.1070024104
Short name T1088
Test name
Test status
Simulation time 161980383 ps
CPU time 0.88 seconds
Started Jul 25 07:05:20 PM PDT 24
Finished Jul 25 07:05:21 PM PDT 24
Peak memory 206964 kb
Host smart-f59d1def-d201-42a7-a20a-e55e4466d2ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10700
24104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.1070024104
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.2517468776
Short name T1645
Test name
Test status
Simulation time 224763328 ps
CPU time 0.99 seconds
Started Jul 25 07:05:16 PM PDT 24
Finished Jul 25 07:05:17 PM PDT 24
Peak memory 207124 kb
Host smart-9c3e085c-61fc-4bce-81b4-3060c723df6f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2517468776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.2517468776
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.1830934409
Short name T1774
Test name
Test status
Simulation time 156248721 ps
CPU time 0.87 seconds
Started Jul 25 07:05:17 PM PDT 24
Finished Jul 25 07:05:18 PM PDT 24
Peak memory 207016 kb
Host smart-ef3b26e5-7cb0-46a3-8f02-4fe795cafc9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18309
34409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.1830934409
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.1306585028
Short name T838
Test name
Test status
Simulation time 41941563 ps
CPU time 0.68 seconds
Started Jul 25 07:05:18 PM PDT 24
Finished Jul 25 07:05:18 PM PDT 24
Peak memory 207088 kb
Host smart-457411a2-62f1-4fed-b265-4f0b1d2e1476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13065
85028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.1306585028
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.718915441
Short name T1047
Test name
Test status
Simulation time 21076443065 ps
CPU time 52.09 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:06:08 PM PDT 24
Peak memory 223760 kb
Host smart-720b9deb-0cf6-4c65-a80d-ce66e6645e8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71891
5441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.718915441
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.1546321462
Short name T2454
Test name
Test status
Simulation time 185381185 ps
CPU time 0.88 seconds
Started Jul 25 07:05:21 PM PDT 24
Finished Jul 25 07:05:22 PM PDT 24
Peak memory 206512 kb
Host smart-536261c0-22e6-4d18-8897-72022cf75fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15463
21462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.1546321462
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.2604786107
Short name T814
Test name
Test status
Simulation time 224971118 ps
CPU time 1.1 seconds
Started Jul 25 07:05:13 PM PDT 24
Finished Jul 25 07:05:14 PM PDT 24
Peak memory 207124 kb
Host smart-c12a65ea-adc0-4ceb-8bba-855797c1a3cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26047
86107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.2604786107
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.2270158798
Short name T1624
Test name
Test status
Simulation time 150043064 ps
CPU time 0.83 seconds
Started Jul 25 07:05:14 PM PDT 24
Finished Jul 25 07:05:15 PM PDT 24
Peak memory 207148 kb
Host smart-03b3a9c2-b974-47ab-81b6-371ac2b672e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22701
58798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.2270158798
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.3575825314
Short name T2820
Test name
Test status
Simulation time 168484834 ps
CPU time 0.89 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:05:16 PM PDT 24
Peak memory 207176 kb
Host smart-04b5f88c-eefc-4662-b51a-fa42e9323154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35758
25314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.3575825314
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.3478437923
Short name T405
Test name
Test status
Simulation time 191610690 ps
CPU time 0.87 seconds
Started Jul 25 07:05:20 PM PDT 24
Finished Jul 25 07:05:21 PM PDT 24
Peak memory 206932 kb
Host smart-f9dfbd13-4c0f-46fd-b752-c6f83b26b23e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34784
37923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.3478437923
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.803661059
Short name T933
Test name
Test status
Simulation time 151986448 ps
CPU time 0.88 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:05:16 PM PDT 24
Peak memory 207116 kb
Host smart-288b1d4e-1a1d-4376-9337-89f4d04b35b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80366
1059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.803661059
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.1198692015
Short name T2449
Test name
Test status
Simulation time 216249084 ps
CPU time 1.04 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:05:17 PM PDT 24
Peak memory 207208 kb
Host smart-30598f49-24bc-49c8-b5ef-75cd4f737f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11986
92015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.1198692015
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.4167283432
Short name T188
Test name
Test status
Simulation time 3964066643 ps
CPU time 113.07 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:07:09 PM PDT 24
Peak memory 215616 kb
Host smart-4747254b-ad4c-42ca-961e-db28112df812
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4167283432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.4167283432
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.1868912738
Short name T524
Test name
Test status
Simulation time 157105905 ps
CPU time 0.94 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:05:16 PM PDT 24
Peak memory 207164 kb
Host smart-03778e94-7012-40b4-9fc5-f0a684dd93b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18689
12738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.1868912738
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.2950907342
Short name T1373
Test name
Test status
Simulation time 198925676 ps
CPU time 0.93 seconds
Started Jul 25 07:05:21 PM PDT 24
Finished Jul 25 07:05:22 PM PDT 24
Peak memory 206964 kb
Host smart-3b65fb3d-f7be-454d-b8c3-2a01ac12c5a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29509
07342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.2950907342
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.2804971683
Short name T2282
Test name
Test status
Simulation time 231678762 ps
CPU time 0.96 seconds
Started Jul 25 07:05:24 PM PDT 24
Finished Jul 25 07:05:25 PM PDT 24
Peak memory 207080 kb
Host smart-bd5dca70-e97e-4680-9622-d9cdfeafdd37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28049
71683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.2804971683
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.1495223226
Short name T1678
Test name
Test status
Simulation time 5863299517 ps
CPU time 59.02 seconds
Started Jul 25 07:05:25 PM PDT 24
Finished Jul 25 07:06:24 PM PDT 24
Peak memory 207404 kb
Host smart-5f125441-f6b0-44c4-9e68-c57afe08800a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14952
23226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.1495223226
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_timeout_missing_host_handshake.4221889246
Short name T1986
Test name
Test status
Simulation time 2917861999 ps
CPU time 18.94 seconds
Started Jul 25 07:05:15 PM PDT 24
Finished Jul 25 07:05:34 PM PDT 24
Peak memory 207372 kb
Host smart-88921caf-30bd-4f6d-aafd-8c2ee2a028c0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221889246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_timeout_missing_hos
t_handshake.4221889246
Directory /workspace/25.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.1204608613
Short name T204
Test name
Test status
Simulation time 80154032 ps
CPU time 0.74 seconds
Started Jul 25 07:05:33 PM PDT 24
Finished Jul 25 07:05:34 PM PDT 24
Peak memory 207104 kb
Host smart-92d0089e-267d-4f59-9a50-a424acc359d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1204608613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.1204608613
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.2164839456
Short name T1234
Test name
Test status
Simulation time 3435411226 ps
CPU time 5.14 seconds
Started Jul 25 07:05:24 PM PDT 24
Finished Jul 25 07:05:29 PM PDT 24
Peak memory 207368 kb
Host smart-598eec4f-b75c-435e-aae7-fb010ce36b3b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164839456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_a
on_wake_disconnect.2164839456
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.2324383970
Short name T1963
Test name
Test status
Simulation time 13370157660 ps
CPU time 15.65 seconds
Started Jul 25 07:05:21 PM PDT 24
Finished Jul 25 07:05:36 PM PDT 24
Peak memory 207324 kb
Host smart-4858613d-a07a-48a1-80ea-8b4eedd82fea
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324383970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.2324383970
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.1764964875
Short name T719
Test name
Test status
Simulation time 23344191706 ps
CPU time 29.15 seconds
Started Jul 25 07:05:24 PM PDT 24
Finished Jul 25 07:05:53 PM PDT 24
Peak memory 207416 kb
Host smart-221beb2f-76c5-4de2-999c-d0651036a97e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764964875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_a
on_wake_resume.1764964875
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.1425240931
Short name T573
Test name
Test status
Simulation time 186989078 ps
CPU time 1.01 seconds
Started Jul 25 07:05:24 PM PDT 24
Finished Jul 25 07:05:26 PM PDT 24
Peak memory 207120 kb
Host smart-7742fa9a-e894-41e6-bb82-d9b7edec73b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14252
40931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.1425240931
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.1375650548
Short name T399
Test name
Test status
Simulation time 148232120 ps
CPU time 0.82 seconds
Started Jul 25 07:05:23 PM PDT 24
Finished Jul 25 07:05:24 PM PDT 24
Peak memory 207088 kb
Host smart-c3705362-ab8e-4c36-be2e-e60c805f9180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13756
50548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.1375650548
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.2276756284
Short name T2419
Test name
Test status
Simulation time 201265996 ps
CPU time 0.94 seconds
Started Jul 25 07:05:22 PM PDT 24
Finished Jul 25 07:05:23 PM PDT 24
Peak memory 207132 kb
Host smart-8549edbd-302e-4851-be1e-4b482b7c5c35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22767
56284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.2276756284
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.2729585552
Short name T1487
Test name
Test status
Simulation time 333037437 ps
CPU time 1.23 seconds
Started Jul 25 07:05:25 PM PDT 24
Finished Jul 25 07:05:26 PM PDT 24
Peak memory 207196 kb
Host smart-454ccb1f-d888-429e-a009-5c3d1410fde0
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2729585552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.2729585552
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.988375965
Short name T1706
Test name
Test status
Simulation time 17673358080 ps
CPU time 35.57 seconds
Started Jul 25 07:05:23 PM PDT 24
Finished Jul 25 07:05:59 PM PDT 24
Peak memory 207392 kb
Host smart-f366fb10-962c-4723-be74-862c04de8c1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98837
5965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.988375965
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_device_timeout.3895499743
Short name T689
Test name
Test status
Simulation time 3890040334 ps
CPU time 33.43 seconds
Started Jul 25 07:05:25 PM PDT 24
Finished Jul 25 07:05:58 PM PDT 24
Peak memory 207364 kb
Host smart-a6cf7533-b672-42b7-86a5-6099965c32fa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895499743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_timeout.3895499743
Directory /workspace/26.usbdev_device_timeout/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.3986246260
Short name T655
Test name
Test status
Simulation time 437576040 ps
CPU time 1.56 seconds
Started Jul 25 07:05:23 PM PDT 24
Finished Jul 25 07:05:25 PM PDT 24
Peak memory 207088 kb
Host smart-c8907cbd-dcfe-4ae2-b0bd-88ee1d74fd4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39862
46260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.3986246260
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.1998705333
Short name T470
Test name
Test status
Simulation time 156065375 ps
CPU time 0.86 seconds
Started Jul 25 07:05:22 PM PDT 24
Finished Jul 25 07:05:23 PM PDT 24
Peak memory 207104 kb
Host smart-8bffccfb-931d-459b-9fc5-39a0dbcfdba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19987
05333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.1998705333
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.1194062815
Short name T243
Test name
Test status
Simulation time 81952373 ps
CPU time 0.8 seconds
Started Jul 25 07:05:25 PM PDT 24
Finished Jul 25 07:05:26 PM PDT 24
Peak memory 207084 kb
Host smart-e7844836-9333-4054-8b11-0f6ef69409ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11940
62815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.1194062815
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.518812778
Short name T855
Test name
Test status
Simulation time 858061598 ps
CPU time 2.27 seconds
Started Jul 25 07:05:23 PM PDT 24
Finished Jul 25 07:05:25 PM PDT 24
Peak memory 207368 kb
Host smart-e150da97-a630-4be1-904c-d3a480f871ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51881
2778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.518812778
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.4034707167
Short name T698
Test name
Test status
Simulation time 157185968 ps
CPU time 1.46 seconds
Started Jul 25 07:05:24 PM PDT 24
Finished Jul 25 07:05:26 PM PDT 24
Peak memory 207380 kb
Host smart-f613edce-2e46-41eb-bc54-aa3b4270f9fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40347
07167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.4034707167
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.337338141
Short name T1497
Test name
Test status
Simulation time 272949936 ps
CPU time 1.2 seconds
Started Jul 25 07:05:26 PM PDT 24
Finished Jul 25 07:05:27 PM PDT 24
Peak memory 215536 kb
Host smart-11942d5d-0431-489a-988e-6d76f0fb071f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=337338141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.337338141
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.4277015440
Short name T1048
Test name
Test status
Simulation time 140171360 ps
CPU time 0.87 seconds
Started Jul 25 07:05:24 PM PDT 24
Finished Jul 25 07:05:25 PM PDT 24
Peak memory 207076 kb
Host smart-d8df7c46-e5d3-4532-b9dd-17741db2103b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42770
15440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.4277015440
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.552298954
Short name T2621
Test name
Test status
Simulation time 242153248 ps
CPU time 1.02 seconds
Started Jul 25 07:05:23 PM PDT 24
Finished Jul 25 07:05:24 PM PDT 24
Peak memory 207120 kb
Host smart-f55caf01-8a30-4437-8967-1e2dc66af725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55229
8954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.552298954
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_invalid_sync.1760855168
Short name T1079
Test name
Test status
Simulation time 7312168939 ps
CPU time 213.43 seconds
Started Jul 25 07:05:23 PM PDT 24
Finished Jul 25 07:08:56 PM PDT 24
Peak memory 215592 kb
Host smart-3d6b98ac-be24-4c89-a425-8e13ae4898e2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1760855168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.1760855168
Directory /workspace/26.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/26.usbdev_iso_retraction.3636224263
Short name T2749
Test name
Test status
Simulation time 8861047539 ps
CPU time 59.01 seconds
Started Jul 25 07:05:24 PM PDT 24
Finished Jul 25 07:06:24 PM PDT 24
Peak memory 207336 kb
Host smart-3b8828b8-1dfc-418b-9dcd-e04b875b4387
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3636224263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_iso_retraction.3636224263
Directory /workspace/26.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.3466222319
Short name T2856
Test name
Test status
Simulation time 233355186 ps
CPU time 0.96 seconds
Started Jul 25 07:05:24 PM PDT 24
Finished Jul 25 07:05:25 PM PDT 24
Peak memory 207124 kb
Host smart-9292ddc0-698c-49fb-a704-9593eda7619f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34662
22319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.3466222319
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.1512479089
Short name T435
Test name
Test status
Simulation time 23337172279 ps
CPU time 26.03 seconds
Started Jul 25 07:05:25 PM PDT 24
Finished Jul 25 07:05:51 PM PDT 24
Peak memory 207412 kb
Host smart-ba2b5660-1b79-44ec-ac72-a5c1b4f11801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15124
79089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.1512479089
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.863820562
Short name T2597
Test name
Test status
Simulation time 3261481413 ps
CPU time 5.53 seconds
Started Jul 25 07:05:23 PM PDT 24
Finished Jul 25 07:05:29 PM PDT 24
Peak memory 207324 kb
Host smart-a84b592f-087a-45b4-8b83-1f8adb606dd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86382
0562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.863820562
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.1551172422
Short name T1282
Test name
Test status
Simulation time 9991694380 ps
CPU time 98.57 seconds
Started Jul 25 07:05:25 PM PDT 24
Finished Jul 25 07:07:03 PM PDT 24
Peak memory 217572 kb
Host smart-9946af00-54fd-4abd-83ca-9cf93d507d41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15511
72422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.1551172422
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.2726874591
Short name T568
Test name
Test status
Simulation time 4566780748 ps
CPU time 135.36 seconds
Started Jul 25 07:05:26 PM PDT 24
Finished Jul 25 07:07:41 PM PDT 24
Peak memory 215616 kb
Host smart-f6509ead-0e95-4890-a553-4bd1ef889224
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2726874591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.2726874591
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.3708001619
Short name T1708
Test name
Test status
Simulation time 249206103 ps
CPU time 1 seconds
Started Jul 25 07:05:25 PM PDT 24
Finished Jul 25 07:05:26 PM PDT 24
Peak memory 207164 kb
Host smart-f1a8b152-40c8-4cc6-a10a-50e8c57efde2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3708001619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.3708001619
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.2068458281
Short name T230
Test name
Test status
Simulation time 194390385 ps
CPU time 1.02 seconds
Started Jul 25 07:05:22 PM PDT 24
Finished Jul 25 07:05:23 PM PDT 24
Peak memory 207136 kb
Host smart-ec1cbcdc-a2aa-4c4b-9e11-c9735bf9ba26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20684
58281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.2068458281
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.3161694521
Short name T379
Test name
Test status
Simulation time 3316002913 ps
CPU time 92.9 seconds
Started Jul 25 07:05:24 PM PDT 24
Finished Jul 25 07:06:57 PM PDT 24
Peak memory 215640 kb
Host smart-cec67a26-dfcc-4948-bd1e-1924b2ad5067
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3161694521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.3161694521
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.3185561749
Short name T442
Test name
Test status
Simulation time 165055808 ps
CPU time 0.87 seconds
Started Jul 25 07:05:29 PM PDT 24
Finished Jul 25 07:05:30 PM PDT 24
Peak memory 207152 kb
Host smart-e3100630-45b0-40f1-851a-95479b5fb546
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3185561749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.3185561749
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.1524347150
Short name T520
Test name
Test status
Simulation time 148860385 ps
CPU time 0.86 seconds
Started Jul 25 07:05:24 PM PDT 24
Finished Jul 25 07:05:25 PM PDT 24
Peak memory 207144 kb
Host smart-e91b78f3-b676-4a1d-9d4b-dc70dc84427c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15243
47150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.1524347150
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.3165885578
Short name T1955
Test name
Test status
Simulation time 166394540 ps
CPU time 0.89 seconds
Started Jul 25 07:05:22 PM PDT 24
Finished Jul 25 07:05:23 PM PDT 24
Peak memory 207184 kb
Host smart-912e9f96-eb1c-4b76-97e5-adc67e6cc43f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31658
85578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.3165885578
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.1910819191
Short name T761
Test name
Test status
Simulation time 173124693 ps
CPU time 0.86 seconds
Started Jul 25 07:05:28 PM PDT 24
Finished Jul 25 07:05:29 PM PDT 24
Peak memory 207128 kb
Host smart-affe9ec2-091c-4fc3-b988-426eac6cc891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19108
19191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.1910819191
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.3742479828
Short name T1641
Test name
Test status
Simulation time 162160153 ps
CPU time 0.87 seconds
Started Jul 25 07:05:22 PM PDT 24
Finished Jul 25 07:05:23 PM PDT 24
Peak memory 207148 kb
Host smart-69468036-8b45-4c4e-b2e8-d150b0ad9482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37424
79828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.3742479828
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.2308669619
Short name T516
Test name
Test status
Simulation time 208852524 ps
CPU time 0.88 seconds
Started Jul 25 07:05:36 PM PDT 24
Finished Jul 25 07:05:37 PM PDT 24
Peak memory 207152 kb
Host smart-c363db35-0f47-4816-bcd4-1aff90164b33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23086
69619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.2308669619
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.2465515312
Short name T1574
Test name
Test status
Simulation time 180656351 ps
CPU time 0.93 seconds
Started Jul 25 07:05:38 PM PDT 24
Finished Jul 25 07:05:39 PM PDT 24
Peak memory 207104 kb
Host smart-621f8cc4-cd48-4bbc-bdb8-e383c5ff1a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24655
15312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.2465515312
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.3817866359
Short name T2628
Test name
Test status
Simulation time 200513028 ps
CPU time 0.97 seconds
Started Jul 25 07:05:37 PM PDT 24
Finished Jul 25 07:05:38 PM PDT 24
Peak memory 207108 kb
Host smart-d04e498f-b969-4f6d-8419-271b1d366fde
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3817866359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.3817866359
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.1261538390
Short name T651
Test name
Test status
Simulation time 147546795 ps
CPU time 0.82 seconds
Started Jul 25 07:05:36 PM PDT 24
Finished Jul 25 07:05:37 PM PDT 24
Peak memory 207112 kb
Host smart-c835c7b1-5d51-4b8a-9d95-9adc8597ff0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12615
38390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.1261538390
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.3556831544
Short name T1915
Test name
Test status
Simulation time 44689378 ps
CPU time 0.71 seconds
Started Jul 25 07:05:32 PM PDT 24
Finished Jul 25 07:05:33 PM PDT 24
Peak memory 207128 kb
Host smart-b88b3941-27ed-4e8d-81de-f1dccfd652d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35568
31544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.3556831544
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.3514299492
Short name T292
Test name
Test status
Simulation time 18094629193 ps
CPU time 48.45 seconds
Started Jul 25 07:05:33 PM PDT 24
Finished Jul 25 07:06:21 PM PDT 24
Peak memory 215580 kb
Host smart-ae75515d-1293-4961-9287-c1d04047c3be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35142
99492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.3514299492
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.372704273
Short name T960
Test name
Test status
Simulation time 237610034 ps
CPU time 1.02 seconds
Started Jul 25 07:05:36 PM PDT 24
Finished Jul 25 07:05:37 PM PDT 24
Peak memory 207104 kb
Host smart-17dd303e-d494-4690-ae0d-035fcf1da2df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37270
4273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.372704273
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.935722242
Short name T330
Test name
Test status
Simulation time 200223890 ps
CPU time 0.91 seconds
Started Jul 25 07:05:30 PM PDT 24
Finished Jul 25 07:05:31 PM PDT 24
Peak memory 207092 kb
Host smart-71414540-e446-4deb-a524-b6eafc655f04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93572
2242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.935722242
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.3447402698
Short name T1565
Test name
Test status
Simulation time 211449465 ps
CPU time 0.94 seconds
Started Jul 25 07:05:35 PM PDT 24
Finished Jul 25 07:05:37 PM PDT 24
Peak memory 207128 kb
Host smart-5a4e0b90-bd70-4618-8562-b78915af6011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34474
02698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.3447402698
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.4032755445
Short name T1838
Test name
Test status
Simulation time 179915289 ps
CPU time 0.87 seconds
Started Jul 25 07:05:31 PM PDT 24
Finished Jul 25 07:05:32 PM PDT 24
Peak memory 207124 kb
Host smart-36085d01-9df6-42cc-89b3-77478244070c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40327
55445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.4032755445
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.3104050129
Short name T2418
Test name
Test status
Simulation time 164895691 ps
CPU time 0.83 seconds
Started Jul 25 07:05:33 PM PDT 24
Finished Jul 25 07:05:34 PM PDT 24
Peak memory 207088 kb
Host smart-659c3d28-26d1-49ff-9f99-c38341923aa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31040
50129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.3104050129
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.44328990
Short name T2610
Test name
Test status
Simulation time 160431867 ps
CPU time 0.88 seconds
Started Jul 25 07:05:37 PM PDT 24
Finished Jul 25 07:05:38 PM PDT 24
Peak memory 207116 kb
Host smart-754a599e-ae36-414c-9153-a99760e4c8af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44328
990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.44328990
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.2573979847
Short name T1439
Test name
Test status
Simulation time 180841114 ps
CPU time 0.85 seconds
Started Jul 25 07:05:38 PM PDT 24
Finished Jul 25 07:05:39 PM PDT 24
Peak memory 207132 kb
Host smart-2d30e2ee-642c-4771-a266-5a6d75bd7d5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25739
79847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.2573979847
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.1963923457
Short name T2385
Test name
Test status
Simulation time 219239674 ps
CPU time 0.98 seconds
Started Jul 25 07:05:33 PM PDT 24
Finished Jul 25 07:05:34 PM PDT 24
Peak memory 207084 kb
Host smart-f9e2c755-4247-4893-8dd7-872480e75378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19639
23457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.1963923457
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.1802703131
Short name T1599
Test name
Test status
Simulation time 5015017074 ps
CPU time 40.36 seconds
Started Jul 25 07:05:32 PM PDT 24
Finished Jul 25 07:06:13 PM PDT 24
Peak memory 217200 kb
Host smart-7f6bee2d-a0d3-4ccc-9476-d0b1e5c47b86
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1802703131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.1802703131
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.3023221641
Short name T307
Test name
Test status
Simulation time 175522475 ps
CPU time 0.89 seconds
Started Jul 25 07:05:33 PM PDT 24
Finished Jul 25 07:05:34 PM PDT 24
Peak memory 207120 kb
Host smart-f6bcff01-3b21-4be9-9b1a-afe9717a8fe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30232
21641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.3023221641
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.198593415
Short name T1001
Test name
Test status
Simulation time 217317647 ps
CPU time 0.99 seconds
Started Jul 25 07:05:34 PM PDT 24
Finished Jul 25 07:05:35 PM PDT 24
Peak memory 207108 kb
Host smart-44a8e634-4e80-4738-9e60-6a7bdd6e16d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19859
3415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.198593415
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.1035961500
Short name T771
Test name
Test status
Simulation time 1118381355 ps
CPU time 2.71 seconds
Started Jul 25 07:05:33 PM PDT 24
Finished Jul 25 07:05:36 PM PDT 24
Peak memory 207276 kb
Host smart-b7267d39-de06-40b2-9ee6-7e11be48fcb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10359
61500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.1035961500
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.86842643
Short name T2750
Test name
Test status
Simulation time 4677418743 ps
CPU time 143.79 seconds
Started Jul 25 07:05:34 PM PDT 24
Finished Jul 25 07:07:58 PM PDT 24
Peak memory 215592 kb
Host smart-a0bdd996-adb5-4b49-99b8-315ce42db64e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86842
643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.86842643
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_timeout_missing_host_handshake.4288503260
Short name T2066
Test name
Test status
Simulation time 616671049 ps
CPU time 5.33 seconds
Started Jul 25 07:05:24 PM PDT 24
Finished Jul 25 07:05:30 PM PDT 24
Peak memory 207416 kb
Host smart-7a9267aa-6d03-43ad-a7c8-30266314030a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288503260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_timeout_missing_hos
t_handshake.4288503260
Directory /workspace/26.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.2052986175
Short name T2574
Test name
Test status
Simulation time 38425483 ps
CPU time 0.67 seconds
Started Jul 25 07:05:55 PM PDT 24
Finished Jul 25 07:05:56 PM PDT 24
Peak memory 207124 kb
Host smart-3dcf5ea9-7db1-41b2-8c35-4c8dbdd8791e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2052986175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.2052986175
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.1021458011
Short name T1340
Test name
Test status
Simulation time 3923250538 ps
CPU time 5.82 seconds
Started Jul 25 07:05:35 PM PDT 24
Finished Jul 25 07:05:41 PM PDT 24
Peak memory 207392 kb
Host smart-f571cfda-288b-4ac9-99bc-b18c1c5cde2c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021458011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_a
on_wake_disconnect.1021458011
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.3838840884
Short name T1049
Test name
Test status
Simulation time 13345800876 ps
CPU time 16.07 seconds
Started Jul 25 07:05:36 PM PDT 24
Finished Jul 25 07:05:53 PM PDT 24
Peak memory 207300 kb
Host smart-7ca7f798-2647-48a4-b0b2-24d57b4e737f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838840884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.3838840884
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.2469383302
Short name T55
Test name
Test status
Simulation time 23488983531 ps
CPU time 27.29 seconds
Started Jul 25 07:05:32 PM PDT 24
Finished Jul 25 07:05:59 PM PDT 24
Peak memory 207380 kb
Host smart-a39f57f3-235b-4bd3-9f7d-ee29a0a4adf9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469383302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_a
on_wake_resume.2469383302
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.1184001399
Short name T1666
Test name
Test status
Simulation time 180171216 ps
CPU time 0.88 seconds
Started Jul 25 07:05:33 PM PDT 24
Finished Jul 25 07:05:34 PM PDT 24
Peak memory 207144 kb
Host smart-73f4587f-1f34-4b08-b6fe-f640de7cece6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11840
01399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.1184001399
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.3973468785
Short name T1583
Test name
Test status
Simulation time 156676576 ps
CPU time 0.88 seconds
Started Jul 25 07:05:36 PM PDT 24
Finished Jul 25 07:05:37 PM PDT 24
Peak memory 207076 kb
Host smart-265702d5-8514-43fc-9ea1-e1c91fbe935a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39734
68785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.3973468785
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.1247378910
Short name T2619
Test name
Test status
Simulation time 170480738 ps
CPU time 0.92 seconds
Started Jul 25 07:05:32 PM PDT 24
Finished Jul 25 07:05:33 PM PDT 24
Peak memory 207144 kb
Host smart-dab8ac06-eda9-412b-9238-69469bfd986a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12473
78910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.1247378910
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.4104246767
Short name T2710
Test name
Test status
Simulation time 965350994 ps
CPU time 2.55 seconds
Started Jul 25 07:05:32 PM PDT 24
Finished Jul 25 07:05:35 PM PDT 24
Peak memory 207372 kb
Host smart-76c89b3a-4416-4c5b-8392-2dc22fa1338b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4104246767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.4104246767
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.2449202224
Short name T2671
Test name
Test status
Simulation time 11445771133 ps
CPU time 25.42 seconds
Started Jul 25 07:05:32 PM PDT 24
Finished Jul 25 07:05:57 PM PDT 24
Peak memory 207392 kb
Host smart-3f722777-428c-4e6e-8ca5-af72dc345eec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24492
02224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.2449202224
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_device_timeout.2267115989
Short name T1717
Test name
Test status
Simulation time 1552797922 ps
CPU time 13.56 seconds
Started Jul 25 07:05:33 PM PDT 24
Finished Jul 25 07:05:46 PM PDT 24
Peak memory 207436 kb
Host smart-9d5a67af-4da0-4194-8df4-b5d2467a59d7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267115989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_timeout.2267115989
Directory /workspace/27.usbdev_device_timeout/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.3218569607
Short name T2735
Test name
Test status
Simulation time 391220674 ps
CPU time 1.27 seconds
Started Jul 25 07:05:38 PM PDT 24
Finished Jul 25 07:05:40 PM PDT 24
Peak memory 207100 kb
Host smart-7526ad99-a6d6-402a-b364-ea47469115d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32185
69607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.3218569607
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.930111944
Short name T675
Test name
Test status
Simulation time 137237249 ps
CPU time 0.8 seconds
Started Jul 25 07:05:38 PM PDT 24
Finished Jul 25 07:05:39 PM PDT 24
Peak memory 207104 kb
Host smart-2a426852-ff01-4a2c-8f12-1f5c33515831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93011
1944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.930111944
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.1713330048
Short name T652
Test name
Test status
Simulation time 37449293 ps
CPU time 0.71 seconds
Started Jul 25 07:05:34 PM PDT 24
Finished Jul 25 07:05:34 PM PDT 24
Peak memory 207080 kb
Host smart-92ee1e8a-57b7-443e-9c88-dff2a429f79d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17133
30048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.1713330048
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.2053144172
Short name T418
Test name
Test status
Simulation time 823261401 ps
CPU time 2.5 seconds
Started Jul 25 07:05:34 PM PDT 24
Finished Jul 25 07:05:37 PM PDT 24
Peak memory 207384 kb
Host smart-cbc4a81c-230c-40c2-acbd-2e4f1ca2b775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20531
44172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.2053144172
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.1355144848
Short name T2822
Test name
Test status
Simulation time 167000531 ps
CPU time 1.7 seconds
Started Jul 25 07:05:34 PM PDT 24
Finished Jul 25 07:05:36 PM PDT 24
Peak memory 207272 kb
Host smart-c0103a51-959e-4382-a97a-0afa19bfb90c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13551
44848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.1355144848
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.3581511491
Short name T629
Test name
Test status
Simulation time 228869959 ps
CPU time 1.25 seconds
Started Jul 25 07:05:35 PM PDT 24
Finished Jul 25 07:05:37 PM PDT 24
Peak memory 215552 kb
Host smart-16627cf5-0ae1-4186-b921-f80563ced6a2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3581511491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.3581511491
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.2242782411
Short name T2697
Test name
Test status
Simulation time 184968449 ps
CPU time 0.89 seconds
Started Jul 25 07:05:31 PM PDT 24
Finished Jul 25 07:05:32 PM PDT 24
Peak memory 207104 kb
Host smart-b966985e-6c8e-4800-ab92-b9d78916cedc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22427
82411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.2242782411
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.2893855875
Short name T2382
Test name
Test status
Simulation time 213245555 ps
CPU time 1.07 seconds
Started Jul 25 07:05:35 PM PDT 24
Finished Jul 25 07:05:36 PM PDT 24
Peak memory 207152 kb
Host smart-e619001d-93b0-4160-8621-b61576b14920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28938
55875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.2893855875
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.911550762
Short name T1387
Test name
Test status
Simulation time 9060882714 ps
CPU time 92.86 seconds
Started Jul 25 07:05:33 PM PDT 24
Finished Jul 25 07:07:06 PM PDT 24
Peak memory 215612 kb
Host smart-96e5c338-39c1-4435-b66d-dcdda68883bd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=911550762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.911550762
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_iso_retraction.3600739533
Short name T2329
Test name
Test status
Simulation time 4325354378 ps
CPU time 28.74 seconds
Started Jul 25 07:05:33 PM PDT 24
Finished Jul 25 07:06:02 PM PDT 24
Peak memory 207384 kb
Host smart-5b25e61a-9bc1-427f-a063-1f43256e7952
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3600739533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.3600739533
Directory /workspace/27.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.2335859678
Short name T2205
Test name
Test status
Simulation time 258376693 ps
CPU time 1.06 seconds
Started Jul 25 07:05:34 PM PDT 24
Finished Jul 25 07:05:35 PM PDT 24
Peak memory 207124 kb
Host smart-444bee39-deeb-4809-96a6-c0009df99a8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23358
59678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.2335859678
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.73082950
Short name T48
Test name
Test status
Simulation time 23318534138 ps
CPU time 26.46 seconds
Started Jul 25 07:05:38 PM PDT 24
Finished Jul 25 07:06:04 PM PDT 24
Peak memory 207372 kb
Host smart-25622d19-d6c1-4a2b-a9e6-1d8820e74ea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73082
950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.73082950
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.2555188768
Short name T595
Test name
Test status
Simulation time 3289218988 ps
CPU time 4.64 seconds
Started Jul 25 07:05:36 PM PDT 24
Finished Jul 25 07:05:41 PM PDT 24
Peak memory 207400 kb
Host smart-eb02cc21-59e2-40a7-b838-2cc3baefc9c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25551
88768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.2555188768
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.4125084944
Short name T419
Test name
Test status
Simulation time 6480677613 ps
CPU time 63.69 seconds
Started Jul 25 07:05:38 PM PDT 24
Finished Jul 25 07:06:42 PM PDT 24
Peak memory 217520 kb
Host smart-da5eebf5-6ac2-489a-911a-bb496ca09d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41250
84944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.4125084944
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.3528994689
Short name T2194
Test name
Test status
Simulation time 3500670465 ps
CPU time 106.31 seconds
Started Jul 25 07:05:31 PM PDT 24
Finished Jul 25 07:07:17 PM PDT 24
Peak memory 215576 kb
Host smart-fb68fa3c-c4e6-4c65-b234-280d769329da
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3528994689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.3528994689
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.2509894200
Short name T1936
Test name
Test status
Simulation time 251664828 ps
CPU time 1.04 seconds
Started Jul 25 07:05:36 PM PDT 24
Finished Jul 25 07:05:37 PM PDT 24
Peak memory 207132 kb
Host smart-a91fc910-d4c6-48a7-9248-9fba6791eec0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2509894200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.2509894200
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.856771790
Short name T658
Test name
Test status
Simulation time 200171476 ps
CPU time 0.98 seconds
Started Jul 25 07:05:38 PM PDT 24
Finished Jul 25 07:05:39 PM PDT 24
Peak memory 207104 kb
Host smart-28a2070e-6bbd-48d3-8f66-48848ded4330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85677
1790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.856771790
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.3645545873
Short name T1046
Test name
Test status
Simulation time 4691794967 ps
CPU time 46.21 seconds
Started Jul 25 07:05:36 PM PDT 24
Finished Jul 25 07:06:23 PM PDT 24
Peak memory 216836 kb
Host smart-2b5ff286-9cc8-4cbe-92c6-d5fef4c8e98a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36455
45873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.3645545873
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.181146446
Short name T1090
Test name
Test status
Simulation time 5588242609 ps
CPU time 163.12 seconds
Started Jul 25 07:05:38 PM PDT 24
Finished Jul 25 07:08:22 PM PDT 24
Peak memory 215528 kb
Host smart-e2b63df8-2b24-4abf-8b2d-4137de6c6a8f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=181146446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.181146446
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.3593183789
Short name T945
Test name
Test status
Simulation time 235955782 ps
CPU time 0.92 seconds
Started Jul 25 07:05:35 PM PDT 24
Finished Jul 25 07:05:36 PM PDT 24
Peak memory 207136 kb
Host smart-8e523a0c-87d2-4851-845f-e16bf66105ca
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3593183789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.3593183789
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.3419346954
Short name T1440
Test name
Test status
Simulation time 149854644 ps
CPU time 0.84 seconds
Started Jul 25 07:05:33 PM PDT 24
Finished Jul 25 07:05:34 PM PDT 24
Peak memory 207132 kb
Host smart-d31ba6d0-0d2a-4210-9bd6-4fd8f5caa4b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34193
46954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.3419346954
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.1589131343
Short name T159
Test name
Test status
Simulation time 311301745 ps
CPU time 1.18 seconds
Started Jul 25 07:05:35 PM PDT 24
Finished Jul 25 07:05:37 PM PDT 24
Peak memory 207096 kb
Host smart-e620d376-0125-4a7d-bcfb-05a7794f0528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15891
31343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.1589131343
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.4147882618
Short name T2801
Test name
Test status
Simulation time 184913725 ps
CPU time 0.98 seconds
Started Jul 25 07:05:34 PM PDT 24
Finished Jul 25 07:05:35 PM PDT 24
Peak memory 207092 kb
Host smart-6153d0fa-ea74-4b62-999f-0b00cbdf3ad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41478
82618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.4147882618
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.628500411
Short name T498
Test name
Test status
Simulation time 170058621 ps
CPU time 0.89 seconds
Started Jul 25 07:05:33 PM PDT 24
Finished Jul 25 07:05:34 PM PDT 24
Peak memory 207128 kb
Host smart-c0b745d4-bb38-4b3b-acde-c31a212f19ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62850
0411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.628500411
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.2233621975
Short name T1693
Test name
Test status
Simulation time 147934376 ps
CPU time 0.84 seconds
Started Jul 25 07:05:34 PM PDT 24
Finished Jul 25 07:05:35 PM PDT 24
Peak memory 207096 kb
Host smart-7c33b88c-4477-48da-ae92-91bcf1332a3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22336
21975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.2233621975
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.2910423482
Short name T1856
Test name
Test status
Simulation time 153776812 ps
CPU time 0.81 seconds
Started Jul 25 07:05:36 PM PDT 24
Finished Jul 25 07:05:37 PM PDT 24
Peak memory 207144 kb
Host smart-6aeb8882-979b-44a0-9329-9ee5b2514b6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29104
23482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.2910423482
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.1484885939
Short name T1824
Test name
Test status
Simulation time 228726004 ps
CPU time 1.07 seconds
Started Jul 25 07:05:33 PM PDT 24
Finished Jul 25 07:05:34 PM PDT 24
Peak memory 207184 kb
Host smart-5dd65bde-b229-4ca6-962a-356467d1e529
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1484885939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.1484885939
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.1629864865
Short name T2579
Test name
Test status
Simulation time 149948513 ps
CPU time 0.88 seconds
Started Jul 25 07:05:35 PM PDT 24
Finished Jul 25 07:05:36 PM PDT 24
Peak memory 207116 kb
Host smart-8288f7e7-fd13-4505-84b6-92199d8d994b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16298
64865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.1629864865
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.830699313
Short name T1488
Test name
Test status
Simulation time 57630397 ps
CPU time 0.72 seconds
Started Jul 25 07:05:36 PM PDT 24
Finished Jul 25 07:05:37 PM PDT 24
Peak memory 207092 kb
Host smart-6610392c-961c-431a-adbe-8fef1ebd5e45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83069
9313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.830699313
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.971095191
Short name T1143
Test name
Test status
Simulation time 7325277089 ps
CPU time 18.54 seconds
Started Jul 25 07:05:51 PM PDT 24
Finished Jul 25 07:06:10 PM PDT 24
Peak memory 215576 kb
Host smart-86b4d302-dcfa-4e07-89e2-1104efa65009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97109
5191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.971095191
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.521130025
Short name T1066
Test name
Test status
Simulation time 177631952 ps
CPU time 0.92 seconds
Started Jul 25 07:05:51 PM PDT 24
Finished Jul 25 07:05:52 PM PDT 24
Peak memory 207188 kb
Host smart-6a05f96e-b16d-451d-88ae-e29a5e4e42bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52113
0025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.521130025
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.3748637156
Short name T1676
Test name
Test status
Simulation time 163838224 ps
CPU time 0.9 seconds
Started Jul 25 07:05:40 PM PDT 24
Finished Jul 25 07:05:41 PM PDT 24
Peak memory 207096 kb
Host smart-dd141c25-2dbc-4945-aac3-33d0e0972215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37486
37156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.3748637156
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.1165472224
Short name T1842
Test name
Test status
Simulation time 229410251 ps
CPU time 0.99 seconds
Started Jul 25 07:05:40 PM PDT 24
Finished Jul 25 07:05:41 PM PDT 24
Peak memory 207120 kb
Host smart-5e00542d-2e9c-4485-b0e4-95f635c1d656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11654
72224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.1165472224
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.2717410187
Short name T2192
Test name
Test status
Simulation time 170954356 ps
CPU time 0.88 seconds
Started Jul 25 07:05:45 PM PDT 24
Finished Jul 25 07:05:46 PM PDT 24
Peak memory 207112 kb
Host smart-7e13b231-a007-49c2-935b-8081bcddbed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27174
10187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.2717410187
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.1000946021
Short name T1589
Test name
Test status
Simulation time 153680813 ps
CPU time 0.84 seconds
Started Jul 25 07:05:47 PM PDT 24
Finished Jul 25 07:05:48 PM PDT 24
Peak memory 207132 kb
Host smart-fce4b18d-71cb-463d-9c32-dc5fc7d3e2a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10009
46021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.1000946021
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.892320695
Short name T841
Test name
Test status
Simulation time 148378967 ps
CPU time 0.89 seconds
Started Jul 25 07:05:51 PM PDT 24
Finished Jul 25 07:05:52 PM PDT 24
Peak memory 207156 kb
Host smart-a2f064ab-f1df-473b-a934-caa8f2f3b737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89232
0695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.892320695
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.1152438092
Short name T2732
Test name
Test status
Simulation time 155004783 ps
CPU time 0.81 seconds
Started Jul 25 07:05:47 PM PDT 24
Finished Jul 25 07:05:47 PM PDT 24
Peak memory 207128 kb
Host smart-bf7d6580-2405-46fa-aaf4-3f3ecfac3f75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11524
38092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.1152438092
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.820648201
Short name T36
Test name
Test status
Simulation time 258403188 ps
CPU time 1.11 seconds
Started Jul 25 07:05:44 PM PDT 24
Finished Jul 25 07:05:45 PM PDT 24
Peak memory 207104 kb
Host smart-4c4dbbbf-a49e-49ef-bc89-9d85bacec38f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82064
8201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.820648201
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.4157444217
Short name T1211
Test name
Test status
Simulation time 3610112927 ps
CPU time 105.72 seconds
Started Jul 25 07:05:48 PM PDT 24
Finished Jul 25 07:07:33 PM PDT 24
Peak memory 215568 kb
Host smart-14164972-ac1c-498b-a3e4-9fa04e98f031
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4157444217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.4157444217
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.590667315
Short name T2482
Test name
Test status
Simulation time 211067993 ps
CPU time 1 seconds
Started Jul 25 07:05:54 PM PDT 24
Finished Jul 25 07:05:55 PM PDT 24
Peak memory 207124 kb
Host smart-a4a8da28-6ed0-4598-86e5-b57969b84dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59066
7315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.590667315
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.2007457636
Short name T1760
Test name
Test status
Simulation time 204141753 ps
CPU time 0.93 seconds
Started Jul 25 07:05:40 PM PDT 24
Finished Jul 25 07:05:41 PM PDT 24
Peak memory 207124 kb
Host smart-e7393f37-40c3-42f2-b8a2-77cd9409a63a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20074
57636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.2007457636
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.3086696764
Short name T22
Test name
Test status
Simulation time 410695735 ps
CPU time 1.4 seconds
Started Jul 25 07:05:43 PM PDT 24
Finished Jul 25 07:05:45 PM PDT 24
Peak memory 207196 kb
Host smart-db820c9c-7eb5-4769-ad00-29bc92b7c4f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30866
96764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.3086696764
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.160145291
Short name T2772
Test name
Test status
Simulation time 6212579481 ps
CPU time 63.74 seconds
Started Jul 25 07:05:43 PM PDT 24
Finished Jul 25 07:06:48 PM PDT 24
Peak memory 207400 kb
Host smart-5111ee1e-c441-4b45-af8e-a6ea3c215d9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16014
5291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.160145291
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_timeout_missing_host_handshake.409268570
Short name T725
Test name
Test status
Simulation time 155669919 ps
CPU time 0.82 seconds
Started Jul 25 07:05:34 PM PDT 24
Finished Jul 25 07:05:35 PM PDT 24
Peak memory 207112 kb
Host smart-9e996d26-41d0-4666-bc81-1f028bde6f5c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409268570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_timeout_missing_host
_handshake.409268570
Directory /workspace/27.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.2410360402
Short name T1845
Test name
Test status
Simulation time 47531222 ps
CPU time 0.68 seconds
Started Jul 25 07:05:58 PM PDT 24
Finished Jul 25 07:05:59 PM PDT 24
Peak memory 207004 kb
Host smart-e27c0cbc-2216-488a-9619-2b9e1081fad6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2410360402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.2410360402
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.1179251153
Short name T1504
Test name
Test status
Simulation time 4227415513 ps
CPU time 6.22 seconds
Started Jul 25 07:05:48 PM PDT 24
Finished Jul 25 07:05:54 PM PDT 24
Peak memory 207364 kb
Host smart-b4209e8d-84ff-443f-81b7-a2d701bbe8df
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179251153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_a
on_wake_disconnect.1179251153
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.532015859
Short name T214
Test name
Test status
Simulation time 13438135923 ps
CPU time 15.74 seconds
Started Jul 25 07:05:46 PM PDT 24
Finished Jul 25 07:06:02 PM PDT 24
Peak memory 207384 kb
Host smart-d1575ed2-5ba4-4934-9677-592348464b6c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=532015859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.532015859
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.3439992731
Short name T808
Test name
Test status
Simulation time 23352575054 ps
CPU time 34.26 seconds
Started Jul 25 07:05:43 PM PDT 24
Finished Jul 25 07:06:17 PM PDT 24
Peak memory 207420 kb
Host smart-e82b8e56-8de8-4fde-b410-845ae61811ce
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439992731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_a
on_wake_resume.3439992731
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.2057024433
Short name T765
Test name
Test status
Simulation time 154865146 ps
CPU time 0.94 seconds
Started Jul 25 07:05:59 PM PDT 24
Finished Jul 25 07:06:00 PM PDT 24
Peak memory 207112 kb
Host smart-ea0235db-16a0-41c4-b973-066ec5fe089c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20570
24433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.2057024433
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.1397687371
Short name T2777
Test name
Test status
Simulation time 164653461 ps
CPU time 0.93 seconds
Started Jul 25 07:05:50 PM PDT 24
Finished Jul 25 07:05:51 PM PDT 24
Peak memory 207092 kb
Host smart-9de1cfb9-eb38-4762-9c57-6e424bce351d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13976
87371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.1397687371
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.1692582441
Short name T2263
Test name
Test status
Simulation time 429514913 ps
CPU time 1.55 seconds
Started Jul 25 07:05:42 PM PDT 24
Finished Jul 25 07:05:44 PM PDT 24
Peak memory 207144 kb
Host smart-40912dee-c59e-4d02-9640-35ea70d0f5a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16925
82441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.1692582441
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.729498680
Short name T1864
Test name
Test status
Simulation time 333375058 ps
CPU time 1.16 seconds
Started Jul 25 07:05:43 PM PDT 24
Finished Jul 25 07:05:44 PM PDT 24
Peak memory 207196 kb
Host smart-50e5125f-1772-4da7-9cc5-41552fd62b4e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=729498680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.729498680
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.3512148816
Short name T2311
Test name
Test status
Simulation time 12152540389 ps
CPU time 26.91 seconds
Started Jul 25 07:05:50 PM PDT 24
Finished Jul 25 07:06:17 PM PDT 24
Peak memory 207392 kb
Host smart-8f9abe3d-b856-4c29-ae41-f66907195a9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35121
48816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.3512148816
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_device_timeout.2418310589
Short name T1745
Test name
Test status
Simulation time 7747490632 ps
CPU time 50.27 seconds
Started Jul 25 07:05:41 PM PDT 24
Finished Jul 25 07:06:32 PM PDT 24
Peak memory 207344 kb
Host smart-29e675a8-3de2-48e6-9deb-1a0af7a21794
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418310589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_timeout.2418310589
Directory /workspace/28.usbdev_device_timeout/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.3222834204
Short name T306
Test name
Test status
Simulation time 351228205 ps
CPU time 1.34 seconds
Started Jul 25 07:05:44 PM PDT 24
Finished Jul 25 07:05:45 PM PDT 24
Peak memory 207016 kb
Host smart-b8ca61c3-7469-4f8d-88d6-600f39f04a26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32228
34204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.3222834204
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.1991513617
Short name T576
Test name
Test status
Simulation time 149155300 ps
CPU time 0.87 seconds
Started Jul 25 07:05:44 PM PDT 24
Finished Jul 25 07:05:45 PM PDT 24
Peak memory 207096 kb
Host smart-709f44d2-76e8-4340-b8ee-cc7e0d1b480e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19915
13617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.1991513617
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.3554218424
Short name T1604
Test name
Test status
Simulation time 39020441 ps
CPU time 0.73 seconds
Started Jul 25 07:05:41 PM PDT 24
Finished Jul 25 07:05:42 PM PDT 24
Peak memory 207068 kb
Host smart-1de5911f-7cfd-4274-9e4b-20556303a541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35542
18424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.3554218424
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.3184719078
Short name T1639
Test name
Test status
Simulation time 902339749 ps
CPU time 2.36 seconds
Started Jul 25 07:05:43 PM PDT 24
Finished Jul 25 07:05:46 PM PDT 24
Peak memory 207292 kb
Host smart-a8d362fe-c89c-4437-91e0-ff4a7a47fd66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31847
19078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.3184719078
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.1657738513
Short name T2324
Test name
Test status
Simulation time 232733046 ps
CPU time 1.52 seconds
Started Jul 25 07:05:46 PM PDT 24
Finished Jul 25 07:05:48 PM PDT 24
Peak memory 207304 kb
Host smart-6ae73837-a1b8-4dbf-abd7-af312715e6f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16577
38513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.1657738513
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.1681734543
Short name T367
Test name
Test status
Simulation time 169004201 ps
CPU time 0.91 seconds
Started Jul 25 07:05:41 PM PDT 24
Finished Jul 25 07:05:42 PM PDT 24
Peak memory 207100 kb
Host smart-914e11a6-42f7-4547-83f8-6b7ca8b16cc4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1681734543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.1681734543
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.3281782859
Short name T659
Test name
Test status
Simulation time 145824325 ps
CPU time 0.81 seconds
Started Jul 25 07:05:41 PM PDT 24
Finished Jul 25 07:05:42 PM PDT 24
Peak memory 207104 kb
Host smart-63c06d80-8d94-484b-a4cf-49c5fb7c70fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32817
82859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.3281782859
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.848534061
Short name T2839
Test name
Test status
Simulation time 244515152 ps
CPU time 1.04 seconds
Started Jul 25 07:05:55 PM PDT 24
Finished Jul 25 07:05:56 PM PDT 24
Peak memory 207120 kb
Host smart-56ef1367-e659-438b-9d2e-473524d1da94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84853
4061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.848534061
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.2533090800
Short name T758
Test name
Test status
Simulation time 7771540828 ps
CPU time 227.44 seconds
Started Jul 25 07:05:49 PM PDT 24
Finished Jul 25 07:09:36 PM PDT 24
Peak memory 215576 kb
Host smart-120c0f04-966d-4ecd-8eb7-45e7c8d16f60
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2533090800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.2533090800
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_iso_retraction.144841181
Short name T713
Test name
Test status
Simulation time 12777634533 ps
CPU time 160.25 seconds
Started Jul 25 07:05:43 PM PDT 24
Finished Jul 25 07:08:24 PM PDT 24
Peak memory 207420 kb
Host smart-ea769ad6-6b36-4715-978f-d2e78fb779d9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=144841181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_iso_retraction.144841181
Directory /workspace/28.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.736307531
Short name T2596
Test name
Test status
Simulation time 207281582 ps
CPU time 0.94 seconds
Started Jul 25 07:05:45 PM PDT 24
Finished Jul 25 07:05:46 PM PDT 24
Peak memory 207148 kb
Host smart-be9df207-3a71-4e24-b501-bd7a196a8be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73630
7531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.736307531
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.3042258455
Short name T1131
Test name
Test status
Simulation time 23380047842 ps
CPU time 27.88 seconds
Started Jul 25 07:05:46 PM PDT 24
Finished Jul 25 07:06:14 PM PDT 24
Peak memory 207484 kb
Host smart-90245730-1a21-4e2f-88c2-ce7d1ac2e268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30422
58455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.3042258455
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.1462464915
Short name T1037
Test name
Test status
Simulation time 3319030291 ps
CPU time 5.73 seconds
Started Jul 25 07:05:40 PM PDT 24
Finished Jul 25 07:05:45 PM PDT 24
Peak memory 207340 kb
Host smart-f7054e7b-6cba-416a-a75a-63fc59584eef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14624
64915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.1462464915
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.2215342291
Short name T2688
Test name
Test status
Simulation time 10487483796 ps
CPU time 302.53 seconds
Started Jul 25 07:05:44 PM PDT 24
Finished Jul 25 07:10:47 PM PDT 24
Peak memory 215604 kb
Host smart-9bc58dec-9e17-42e0-8522-47ebc72bcdbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22153
42291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.2215342291
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.128834518
Short name T594
Test name
Test status
Simulation time 5487730434 ps
CPU time 56.47 seconds
Started Jul 25 07:05:59 PM PDT 24
Finished Jul 25 07:06:55 PM PDT 24
Peak memory 207412 kb
Host smart-d7284365-c235-4238-b312-09014c71b57c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=128834518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.128834518
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.3049234141
Short name T2862
Test name
Test status
Simulation time 246365666 ps
CPU time 1.07 seconds
Started Jul 25 07:05:43 PM PDT 24
Finished Jul 25 07:05:44 PM PDT 24
Peak memory 207124 kb
Host smart-746b2f75-2452-407a-acf9-2e96296d41e4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3049234141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.3049234141
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.1365081605
Short name T1485
Test name
Test status
Simulation time 198561471 ps
CPU time 0.94 seconds
Started Jul 25 07:05:44 PM PDT 24
Finished Jul 25 07:05:45 PM PDT 24
Peak memory 207072 kb
Host smart-dfcfc1f2-c5e7-4ecd-b713-1e74805f68e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13650
81605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.1365081605
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.2205204867
Short name T453
Test name
Test status
Simulation time 3633052484 ps
CPU time 27.71 seconds
Started Jul 25 07:05:45 PM PDT 24
Finished Jul 25 07:06:13 PM PDT 24
Peak memory 217116 kb
Host smart-3bcb1a62-883c-480a-ae1d-620f65a8d2ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22052
04867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.2205204867
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.355136454
Short name T1659
Test name
Test status
Simulation time 6704866717 ps
CPU time 52.2 seconds
Started Jul 25 07:05:45 PM PDT 24
Finished Jul 25 07:06:37 PM PDT 24
Peak memory 207428 kb
Host smart-ccfe9e9e-a050-4c98-b72b-efc25c3de9c3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=355136454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.355136454
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.2837593690
Short name T2649
Test name
Test status
Simulation time 211733795 ps
CPU time 0.94 seconds
Started Jul 25 07:05:49 PM PDT 24
Finished Jul 25 07:05:50 PM PDT 24
Peak memory 207144 kb
Host smart-1958eda7-547a-43b8-bd31-4b69f1f7c872
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2837593690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.2837593690
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.3108199940
Short name T645
Test name
Test status
Simulation time 147900123 ps
CPU time 0.88 seconds
Started Jul 25 07:05:47 PM PDT 24
Finished Jul 25 07:05:48 PM PDT 24
Peak memory 207144 kb
Host smart-2f6ef01c-919a-4860-83a3-c60a923bf266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31081
99940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.3108199940
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.3645290201
Short name T126
Test name
Test status
Simulation time 182131738 ps
CPU time 0.91 seconds
Started Jul 25 07:05:43 PM PDT 24
Finished Jul 25 07:05:44 PM PDT 24
Peak memory 207156 kb
Host smart-66d5cda3-8ee2-4a39-a683-e8bc3a455ecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36452
90201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.3645290201
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.4044516990
Short name T1921
Test name
Test status
Simulation time 186184000 ps
CPU time 0.93 seconds
Started Jul 25 07:05:50 PM PDT 24
Finished Jul 25 07:05:52 PM PDT 24
Peak memory 207148 kb
Host smart-27ca4f01-c136-4822-8811-b9b547c961c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40445
16990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.4044516990
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.3031599865
Short name T2159
Test name
Test status
Simulation time 185065770 ps
CPU time 0.91 seconds
Started Jul 25 07:05:52 PM PDT 24
Finished Jul 25 07:05:53 PM PDT 24
Peak memory 207112 kb
Host smart-a2fc532f-49b6-40b1-8883-f73bca96d198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30315
99865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.3031599865
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.902956977
Short name T185
Test name
Test status
Simulation time 160450985 ps
CPU time 0.87 seconds
Started Jul 25 07:05:47 PM PDT 24
Finished Jul 25 07:05:48 PM PDT 24
Peak memory 207136 kb
Host smart-f566184b-ff35-4a52-abc2-b65968a4ceb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90295
6977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.902956977
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.3403426058
Short name T885
Test name
Test status
Simulation time 209601407 ps
CPU time 0.98 seconds
Started Jul 25 07:05:45 PM PDT 24
Finished Jul 25 07:05:46 PM PDT 24
Peak memory 207172 kb
Host smart-d9495e0a-e253-4e62-8293-4dd51f560fb0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3403426058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.3403426058
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.441816204
Short name T2303
Test name
Test status
Simulation time 176873064 ps
CPU time 0.85 seconds
Started Jul 25 07:05:43 PM PDT 24
Finished Jul 25 07:05:44 PM PDT 24
Peak memory 207080 kb
Host smart-f71dfc9d-d8eb-4d4c-8df8-933133198d4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44181
6204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.441816204
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.2840721109
Short name T1496
Test name
Test status
Simulation time 36622895 ps
CPU time 0.68 seconds
Started Jul 25 07:05:43 PM PDT 24
Finished Jul 25 07:05:44 PM PDT 24
Peak memory 207096 kb
Host smart-8287dc45-47e0-41e9-b257-aac8c7b4be9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28407
21109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.2840721109
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.140695490
Short name T1575
Test name
Test status
Simulation time 14196226110 ps
CPU time 38.46 seconds
Started Jul 25 07:05:43 PM PDT 24
Finished Jul 25 07:06:22 PM PDT 24
Peak memory 220276 kb
Host smart-5300ae5b-7d77-403b-af25-9a6e55f66577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14069
5490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.140695490
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.1601043220
Short name T1612
Test name
Test status
Simulation time 146361340 ps
CPU time 0.85 seconds
Started Jul 25 07:05:43 PM PDT 24
Finished Jul 25 07:05:45 PM PDT 24
Peak memory 207136 kb
Host smart-015b8d7b-addf-4ce8-80f8-6a9a7c4b9440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16010
43220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.1601043220
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.1763349559
Short name T2489
Test name
Test status
Simulation time 191431977 ps
CPU time 0.93 seconds
Started Jul 25 07:05:50 PM PDT 24
Finished Jul 25 07:05:52 PM PDT 24
Peak memory 207056 kb
Host smart-d68af8f0-23bd-4167-818e-3d486d237e65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17633
49559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.1763349559
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.1693665611
Short name T1263
Test name
Test status
Simulation time 189666373 ps
CPU time 0.9 seconds
Started Jul 25 07:05:53 PM PDT 24
Finished Jul 25 07:05:54 PM PDT 24
Peak memory 207076 kb
Host smart-797369d9-2a63-4401-b697-87112d1b4543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16936
65611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.1693665611
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.1656146159
Short name T708
Test name
Test status
Simulation time 223155450 ps
CPU time 0.99 seconds
Started Jul 25 07:05:57 PM PDT 24
Finished Jul 25 07:05:58 PM PDT 24
Peak memory 207120 kb
Host smart-6cc9b6c9-a64b-4ac0-b3f0-8a948c70b5bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16561
46159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.1656146159
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.95935956
Short name T1210
Test name
Test status
Simulation time 174109636 ps
CPU time 0.84 seconds
Started Jul 25 07:06:00 PM PDT 24
Finished Jul 25 07:06:01 PM PDT 24
Peak memory 207148 kb
Host smart-56cb476b-34a5-4a15-8732-e8bcfdd06fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95935
956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.95935956
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.2318008917
Short name T1733
Test name
Test status
Simulation time 223416455 ps
CPU time 0.92 seconds
Started Jul 25 07:05:53 PM PDT 24
Finished Jul 25 07:05:54 PM PDT 24
Peak memory 207088 kb
Host smart-9b48d066-c741-44b3-8f79-a27c83f6accd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23180
08917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.2318008917
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.4274265041
Short name T2139
Test name
Test status
Simulation time 219214876 ps
CPU time 0.95 seconds
Started Jul 25 07:05:49 PM PDT 24
Finished Jul 25 07:05:50 PM PDT 24
Peak memory 207112 kb
Host smart-912174c1-f18a-4043-a702-162c4459d41f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42742
65041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.4274265041
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.3655594189
Short name T690
Test name
Test status
Simulation time 202216915 ps
CPU time 1.07 seconds
Started Jul 25 07:05:48 PM PDT 24
Finished Jul 25 07:05:49 PM PDT 24
Peak memory 207212 kb
Host smart-94adb889-ca7e-4b94-b91c-39d85d74babb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36555
94189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.3655594189
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.3118536316
Short name T1281
Test name
Test status
Simulation time 5803433302 ps
CPU time 170.64 seconds
Started Jul 25 07:05:46 PM PDT 24
Finished Jul 25 07:08:37 PM PDT 24
Peak memory 215688 kb
Host smart-6f136991-0ac5-48f0-8595-c688932ac588
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3118536316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.3118536316
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.2843429632
Short name T1192
Test name
Test status
Simulation time 187634959 ps
CPU time 0.9 seconds
Started Jul 25 07:05:50 PM PDT 24
Finished Jul 25 07:05:51 PM PDT 24
Peak memory 207080 kb
Host smart-0f7e7fa5-3a03-48fc-9639-78afea5e09aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28434
29632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.2843429632
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.2148250104
Short name T732
Test name
Test status
Simulation time 213533590 ps
CPU time 0.93 seconds
Started Jul 25 07:05:42 PM PDT 24
Finished Jul 25 07:05:44 PM PDT 24
Peak memory 207232 kb
Host smart-5c862210-d6fc-44bb-bee4-58a3a52222e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21482
50104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.2148250104
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.3381424198
Short name T1828
Test name
Test status
Simulation time 627062301 ps
CPU time 1.8 seconds
Started Jul 25 07:05:57 PM PDT 24
Finished Jul 25 07:05:59 PM PDT 24
Peak memory 207116 kb
Host smart-e84b1bf6-6193-49e4-8f03-d4cb7b343358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33814
24198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.3381424198
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.2243880358
Short name T680
Test name
Test status
Simulation time 4156054280 ps
CPU time 118.56 seconds
Started Jul 25 07:05:43 PM PDT 24
Finished Jul 25 07:07:42 PM PDT 24
Peak memory 215620 kb
Host smart-66297fb8-ae1c-458f-a0c4-b75fa3973638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22438
80358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.2243880358
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_timeout_missing_host_handshake.135914145
Short name T2502
Test name
Test status
Simulation time 1116751457 ps
CPU time 9.35 seconds
Started Jul 25 07:05:43 PM PDT 24
Finished Jul 25 07:05:53 PM PDT 24
Peak memory 207340 kb
Host smart-e5c2c894-5b21-4505-a1b0-bb3209537bf5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135914145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_timeout_missing_host
_handshake.135914145
Directory /workspace/28.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.3657962974
Short name T1271
Test name
Test status
Simulation time 45373032 ps
CPU time 0.68 seconds
Started Jul 25 07:05:56 PM PDT 24
Finished Jul 25 07:05:57 PM PDT 24
Peak memory 207172 kb
Host smart-3df185d6-5e88-4900-bba6-4360c5cba5de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3657962974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.3657962974
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.892926053
Short name T2248
Test name
Test status
Simulation time 3969973854 ps
CPU time 6.95 seconds
Started Jul 25 07:05:49 PM PDT 24
Finished Jul 25 07:05:56 PM PDT 24
Peak memory 207376 kb
Host smart-d5cb5d74-1f89-4f18-9ebd-266ea96565cf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892926053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_ao
n_wake_disconnect.892926053
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.1385034436
Short name T1714
Test name
Test status
Simulation time 13303039348 ps
CPU time 14.34 seconds
Started Jul 25 07:05:56 PM PDT 24
Finished Jul 25 07:06:11 PM PDT 24
Peak memory 207420 kb
Host smart-33b5ed25-9780-4a65-a91e-8ba4df0a512c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385034436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.1385034436
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.781993550
Short name T1835
Test name
Test status
Simulation time 23372336671 ps
CPU time 28.42 seconds
Started Jul 25 07:05:42 PM PDT 24
Finished Jul 25 07:06:11 PM PDT 24
Peak memory 207396 kb
Host smart-6ca2e20b-8b3d-49b2-abcc-793308e21538
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781993550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_ao
n_wake_resume.781993550
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.3928606119
Short name T385
Test name
Test status
Simulation time 171075062 ps
CPU time 0.89 seconds
Started Jul 25 07:05:43 PM PDT 24
Finished Jul 25 07:05:45 PM PDT 24
Peak memory 207128 kb
Host smart-133f8baf-5715-4fd4-be7f-90eeb29f1d28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39286
06119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.3928606119
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.1335939077
Short name T2757
Test name
Test status
Simulation time 158566384 ps
CPU time 0.9 seconds
Started Jul 25 07:05:43 PM PDT 24
Finished Jul 25 07:05:45 PM PDT 24
Peak memory 207108 kb
Host smart-722b7312-de5d-4c2c-866d-20b2ee21b7db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13359
39077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.1335939077
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.3320189566
Short name T1623
Test name
Test status
Simulation time 599546818 ps
CPU time 1.79 seconds
Started Jul 25 07:05:57 PM PDT 24
Finished Jul 25 07:05:59 PM PDT 24
Peak memory 206968 kb
Host smart-bb73780e-3112-4a94-817e-bc40c35b2e21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33201
89566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.3320189566
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.4123232468
Short name T2484
Test name
Test status
Simulation time 785703722 ps
CPU time 2.2 seconds
Started Jul 25 07:05:49 PM PDT 24
Finished Jul 25 07:05:51 PM PDT 24
Peak memory 207352 kb
Host smart-05ff3e4f-3027-4177-808a-1e2e5be46d55
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4123232468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.4123232468
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.3617262311
Short name T953
Test name
Test status
Simulation time 7854211908 ps
CPU time 18.44 seconds
Started Jul 25 07:05:50 PM PDT 24
Finished Jul 25 07:06:08 PM PDT 24
Peak memory 207344 kb
Host smart-dc2a3d68-15d5-4d36-b0d6-a58ce4859d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36172
62311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.3617262311
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_device_timeout.2674199239
Short name T2811
Test name
Test status
Simulation time 5670613432 ps
CPU time 53.39 seconds
Started Jul 25 07:05:51 PM PDT 24
Finished Jul 25 07:06:44 PM PDT 24
Peak memory 207388 kb
Host smart-acdda978-6e00-4701-ae90-8cbcaefecb21
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674199239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_timeout.2674199239
Directory /workspace/29.usbdev_device_timeout/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.5793345
Short name T2726
Test name
Test status
Simulation time 416587751 ps
CPU time 1.33 seconds
Started Jul 25 07:06:01 PM PDT 24
Finished Jul 25 07:06:02 PM PDT 24
Peak memory 206936 kb
Host smart-16d52998-7533-497c-8a47-6ae6ec5a2990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57933
45 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.5793345
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.465558654
Short name T1594
Test name
Test status
Simulation time 138478679 ps
CPU time 0.8 seconds
Started Jul 25 07:05:49 PM PDT 24
Finished Jul 25 07:05:50 PM PDT 24
Peak memory 207104 kb
Host smart-67da7ca8-1034-44a8-9708-395614f07a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46555
8654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.465558654
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.2771142735
Short name T1675
Test name
Test status
Simulation time 57397489 ps
CPU time 0.73 seconds
Started Jul 25 07:05:54 PM PDT 24
Finished Jul 25 07:05:55 PM PDT 24
Peak memory 207068 kb
Host smart-75c7b655-3696-4ac4-92d1-111f1f5b23c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27711
42735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.2771142735
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.3181424530
Short name T1718
Test name
Test status
Simulation time 906842498 ps
CPU time 2.35 seconds
Started Jul 25 07:05:54 PM PDT 24
Finished Jul 25 07:05:56 PM PDT 24
Peak memory 207236 kb
Host smart-76c5682a-d294-4a2b-b274-b131426e9189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31814
24530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.3181424530
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.3923515151
Short name T827
Test name
Test status
Simulation time 194960102 ps
CPU time 2.33 seconds
Started Jul 25 07:05:56 PM PDT 24
Finished Jul 25 07:05:59 PM PDT 24
Peak memory 207332 kb
Host smart-8e5b92d7-1934-459e-a383-333c7e7eaa5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39235
15151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.3923515151
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.3187715911
Short name T2411
Test name
Test status
Simulation time 247466043 ps
CPU time 1.1 seconds
Started Jul 25 07:06:05 PM PDT 24
Finished Jul 25 07:06:06 PM PDT 24
Peak memory 207336 kb
Host smart-214c69a2-cdca-4fc0-8c6d-5286311734e7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3187715911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.3187715911
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.1099384295
Short name T2752
Test name
Test status
Simulation time 137387337 ps
CPU time 0.82 seconds
Started Jul 25 07:05:53 PM PDT 24
Finished Jul 25 07:05:54 PM PDT 24
Peak memory 207080 kb
Host smart-29d2e664-4b0f-4664-b6ed-ebb87d72ba7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10993
84295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.1099384295
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.3274063385
Short name T2813
Test name
Test status
Simulation time 207479189 ps
CPU time 0.93 seconds
Started Jul 25 07:06:02 PM PDT 24
Finished Jul 25 07:06:03 PM PDT 24
Peak memory 207140 kb
Host smart-6652f11f-ef4c-492a-99d9-6aa8d4bd1c47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32740
63385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.3274063385
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_invalid_sync.1759644988
Short name T766
Test name
Test status
Simulation time 7596403041 ps
CPU time 235.98 seconds
Started Jul 25 07:05:56 PM PDT 24
Finished Jul 25 07:09:52 PM PDT 24
Peak memory 215628 kb
Host smart-21445690-8710-4ec4-ac46-e10dade58837
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1759644988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.1759644988
Directory /workspace/29.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/29.usbdev_iso_retraction.613271836
Short name T830
Test name
Test status
Simulation time 4461107668 ps
CPU time 32.89 seconds
Started Jul 25 07:05:58 PM PDT 24
Finished Jul 25 07:06:31 PM PDT 24
Peak memory 207316 kb
Host smart-b3d14d96-c790-41c1-b414-f32205d7bf33
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=613271836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.613271836
Directory /workspace/29.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.4142755953
Short name T2528
Test name
Test status
Simulation time 201783101 ps
CPU time 0.89 seconds
Started Jul 25 07:05:51 PM PDT 24
Finished Jul 25 07:05:53 PM PDT 24
Peak memory 207144 kb
Host smart-ccd66b51-30dc-4b36-8e43-96c5f0b607c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41427
55953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.4142755953
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.3833446022
Short name T2098
Test name
Test status
Simulation time 23380947386 ps
CPU time 28.38 seconds
Started Jul 25 07:05:59 PM PDT 24
Finished Jul 25 07:06:28 PM PDT 24
Peak memory 207372 kb
Host smart-a0279197-38a7-4cdd-b335-1da07abb83a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38334
46022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.3833446022
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.1172178231
Short name T2163
Test name
Test status
Simulation time 3263224868 ps
CPU time 5.8 seconds
Started Jul 25 07:05:58 PM PDT 24
Finished Jul 25 07:06:04 PM PDT 24
Peak memory 207372 kb
Host smart-3fa2f80d-ef2b-4871-8628-0ad64494390d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11721
78231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.1172178231
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.3294603119
Short name T2224
Test name
Test status
Simulation time 7467226230 ps
CPU time 72.56 seconds
Started Jul 25 07:05:55 PM PDT 24
Finished Jul 25 07:07:08 PM PDT 24
Peak memory 217600 kb
Host smart-605722e5-cb45-4e9f-bfaf-b43ca3c0d273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32946
03119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.3294603119
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.824887539
Short name T354
Test name
Test status
Simulation time 4410516549 ps
CPU time 129.7 seconds
Started Jul 25 07:05:51 PM PDT 24
Finished Jul 25 07:08:01 PM PDT 24
Peak memory 215624 kb
Host smart-c04d46f8-23f7-4e96-a947-785bf542ebf8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=824887539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.824887539
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.1456070752
Short name T415
Test name
Test status
Simulation time 241776394 ps
CPU time 1 seconds
Started Jul 25 07:06:00 PM PDT 24
Finished Jul 25 07:06:01 PM PDT 24
Peak memory 207184 kb
Host smart-6ab108e5-faf2-4b9d-bb67-0ff9cffdded2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1456070752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.1456070752
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.3894582587
Short name T1173
Test name
Test status
Simulation time 237059082 ps
CPU time 1 seconds
Started Jul 25 07:05:59 PM PDT 24
Finished Jul 25 07:06:01 PM PDT 24
Peak memory 207144 kb
Host smart-3e80322f-ee7b-47da-a679-9849e2beacf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38945
82587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.3894582587
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.894292928
Short name T2000
Test name
Test status
Simulation time 4645769211 ps
CPU time 46.55 seconds
Started Jul 25 07:06:01 PM PDT 24
Finished Jul 25 07:06:48 PM PDT 24
Peak memory 215528 kb
Host smart-adfbc927-0bb9-470e-8e2a-0a775cdcceb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89429
2928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.894292928
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.615898334
Short name T821
Test name
Test status
Simulation time 3980642081 ps
CPU time 38.49 seconds
Started Jul 25 07:05:50 PM PDT 24
Finished Jul 25 07:06:28 PM PDT 24
Peak memory 217140 kb
Host smart-ad531eb6-24dd-4603-8284-a6fd6dc7f014
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=615898334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.615898334
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.2731796507
Short name T2170
Test name
Test status
Simulation time 155285930 ps
CPU time 0.87 seconds
Started Jul 25 07:05:59 PM PDT 24
Finished Jul 25 07:06:00 PM PDT 24
Peak memory 207160 kb
Host smart-e9d3716c-e59d-4bab-8b16-0fb7c83ca983
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2731796507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.2731796507
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.3620245224
Short name T1216
Test name
Test status
Simulation time 166519504 ps
CPU time 0.85 seconds
Started Jul 25 07:05:57 PM PDT 24
Finished Jul 25 07:05:58 PM PDT 24
Peak memory 207140 kb
Host smart-4ea12d0d-1a8e-4dc3-9614-6a97a9f424a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36202
45224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.3620245224
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.2006341855
Short name T1627
Test name
Test status
Simulation time 199795249 ps
CPU time 0.91 seconds
Started Jul 25 07:05:52 PM PDT 24
Finished Jul 25 07:05:53 PM PDT 24
Peak memory 207148 kb
Host smart-65c4edfb-f176-40a2-80d8-b05e272a260b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20063
41855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.2006341855
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.1316947548
Short name T2620
Test name
Test status
Simulation time 146511622 ps
CPU time 0.86 seconds
Started Jul 25 07:05:53 PM PDT 24
Finished Jul 25 07:05:54 PM PDT 24
Peak memory 207064 kb
Host smart-fcde0f27-78dd-4f04-b30e-0f0d54c5363b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13169
47548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.1316947548
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.3277009690
Short name T2289
Test name
Test status
Simulation time 184893511 ps
CPU time 0.87 seconds
Started Jul 25 07:05:56 PM PDT 24
Finished Jul 25 07:05:57 PM PDT 24
Peak memory 207116 kb
Host smart-ba226fb6-1c75-452c-a562-5953889640d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32770
09690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.3277009690
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.3244959182
Short name T1438
Test name
Test status
Simulation time 159068851 ps
CPU time 0.84 seconds
Started Jul 25 07:05:59 PM PDT 24
Finished Jul 25 07:06:00 PM PDT 24
Peak memory 207128 kb
Host smart-d433f050-1654-43cd-9b99-fd4afefbc0e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32449
59182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.3244959182
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.1310812764
Short name T196
Test name
Test status
Simulation time 143484758 ps
CPU time 0.84 seconds
Started Jul 25 07:05:55 PM PDT 24
Finished Jul 25 07:05:56 PM PDT 24
Peak memory 207120 kb
Host smart-1cafcf67-971a-472e-b6a8-d5c9a0f03f06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13108
12764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.1310812764
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.3540502086
Short name T2357
Test name
Test status
Simulation time 200941649 ps
CPU time 0.99 seconds
Started Jul 25 07:05:53 PM PDT 24
Finished Jul 25 07:05:54 PM PDT 24
Peak memory 207132 kb
Host smart-fa185f2c-9cab-4432-b5ad-9d55b4eea975
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3540502086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.3540502086
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.3286504682
Short name T1900
Test name
Test status
Simulation time 159916401 ps
CPU time 0.85 seconds
Started Jul 25 07:05:58 PM PDT 24
Finished Jul 25 07:06:00 PM PDT 24
Peak memory 206924 kb
Host smart-6651805e-b9e0-4197-82fb-37f80e17b358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32865
04682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.3286504682
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.873188428
Short name T41
Test name
Test status
Simulation time 67750251 ps
CPU time 0.7 seconds
Started Jul 25 07:05:58 PM PDT 24
Finished Jul 25 07:05:59 PM PDT 24
Peak memory 207092 kb
Host smart-718212b6-668d-4a04-8f14-8d52d7ebb1d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87318
8428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.873188428
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.3589367660
Short name T258
Test name
Test status
Simulation time 9377478809 ps
CPU time 22.95 seconds
Started Jul 25 07:06:01 PM PDT 24
Finished Jul 25 07:06:24 PM PDT 24
Peak memory 215504 kb
Host smart-c2702227-3550-4a20-a573-1d006bbf37d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35893
67660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.3589367660
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.1609790267
Short name T1560
Test name
Test status
Simulation time 187353772 ps
CPU time 0.91 seconds
Started Jul 25 07:05:57 PM PDT 24
Finished Jul 25 07:05:59 PM PDT 24
Peak memory 207044 kb
Host smart-159132fa-09f0-4e5d-8a70-7a768e7e2866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16097
90267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.1609790267
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.394993492
Short name T23
Test name
Test status
Simulation time 224864599 ps
CPU time 0.98 seconds
Started Jul 25 07:05:55 PM PDT 24
Finished Jul 25 07:05:56 PM PDT 24
Peak memory 207104 kb
Host smart-47ba167e-0a33-4607-9105-77dcd7d661a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39499
3492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.394993492
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.4166659438
Short name T1092
Test name
Test status
Simulation time 262486169 ps
CPU time 0.99 seconds
Started Jul 25 07:05:54 PM PDT 24
Finished Jul 25 07:05:56 PM PDT 24
Peak memory 207116 kb
Host smart-b47d17ed-0e56-4d30-a55e-c6333d4e5166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41666
59438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.4166659438
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.1823632628
Short name T2864
Test name
Test status
Simulation time 175562435 ps
CPU time 0.87 seconds
Started Jul 25 07:06:02 PM PDT 24
Finished Jul 25 07:06:03 PM PDT 24
Peak memory 207136 kb
Host smart-f68271c0-00de-48e6-bd96-9539e66fdd9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18236
32628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.1823632628
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.3976550504
Short name T688
Test name
Test status
Simulation time 144205928 ps
CPU time 0.85 seconds
Started Jul 25 07:05:54 PM PDT 24
Finished Jul 25 07:05:56 PM PDT 24
Peak memory 207132 kb
Host smart-0bd5cb57-5faf-467a-95e8-689c29484d3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39765
50504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.3976550504
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.1205444776
Short name T593
Test name
Test status
Simulation time 184829440 ps
CPU time 0.88 seconds
Started Jul 25 07:05:51 PM PDT 24
Finished Jul 25 07:05:52 PM PDT 24
Peak memory 207112 kb
Host smart-7e0398d7-679f-49a0-b809-00d5de552239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12054
44776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.1205444776
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.3108407964
Short name T422
Test name
Test status
Simulation time 152548080 ps
CPU time 0.82 seconds
Started Jul 25 07:05:56 PM PDT 24
Finished Jul 25 07:05:57 PM PDT 24
Peak memory 207140 kb
Host smart-6115b545-9c77-41b3-ba3c-b255455342ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31084
07964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.3108407964
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.3984602747
Short name T1098
Test name
Test status
Simulation time 218244328 ps
CPU time 1.02 seconds
Started Jul 25 07:05:53 PM PDT 24
Finished Jul 25 07:05:54 PM PDT 24
Peak memory 207068 kb
Host smart-8323973a-d3b7-4684-b871-db8f111c58c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39846
02747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.3984602747
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.3166415839
Short name T1502
Test name
Test status
Simulation time 3380969997 ps
CPU time 25.58 seconds
Started Jul 25 07:05:52 PM PDT 24
Finished Jul 25 07:06:17 PM PDT 24
Peak memory 215608 kb
Host smart-32bdcce7-1cd3-425c-9028-559a5c68ff8c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3166415839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.3166415839
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.3718929391
Short name T1581
Test name
Test status
Simulation time 196850775 ps
CPU time 0.89 seconds
Started Jul 25 07:05:59 PM PDT 24
Finished Jul 25 07:06:00 PM PDT 24
Peak memory 207140 kb
Host smart-ac64a6aa-335d-4d0a-8f55-cff842233a07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37189
29391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.3718929391
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.3081265339
Short name T2664
Test name
Test status
Simulation time 157418119 ps
CPU time 0.81 seconds
Started Jul 25 07:06:03 PM PDT 24
Finished Jul 25 07:06:04 PM PDT 24
Peak memory 207124 kb
Host smart-089d1088-a2b8-4cd6-ac3c-d3240b45fe8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30812
65339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.3081265339
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.2088456706
Short name T1190
Test name
Test status
Simulation time 429568681 ps
CPU time 1.32 seconds
Started Jul 25 07:05:50 PM PDT 24
Finished Jul 25 07:05:52 PM PDT 24
Peak memory 207120 kb
Host smart-9f6358d7-ac4c-48b2-9f5a-95d3d6c9a5a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20884
56706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.2088456706
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.1947392218
Short name T178
Test name
Test status
Simulation time 5265164704 ps
CPU time 52.41 seconds
Started Jul 25 07:05:58 PM PDT 24
Finished Jul 25 07:06:51 PM PDT 24
Peak memory 207288 kb
Host smart-604f0089-f15c-4ee5-b7c4-6a7f29b74a4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19473
92218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.1947392218
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_timeout_missing_host_handshake.76721928
Short name T2678
Test name
Test status
Simulation time 301341462 ps
CPU time 4.64 seconds
Started Jul 25 07:05:50 PM PDT 24
Finished Jul 25 07:05:55 PM PDT 24
Peak memory 207284 kb
Host smart-ac295397-b57f-48c0-b4fb-7777ca4d07e3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76721928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_timeout_missing_host_
handshake.76721928
Directory /workspace/29.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.2472725010
Short name T1795
Test name
Test status
Simulation time 53748010 ps
CPU time 0.71 seconds
Started Jul 25 07:01:17 PM PDT 24
Finished Jul 25 07:01:18 PM PDT 24
Peak memory 207164 kb
Host smart-fe681b59-4b08-4768-b21a-15b6bbc4a93d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2472725010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.2472725010
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.164942679
Short name T2383
Test name
Test status
Simulation time 4042588654 ps
CPU time 6.45 seconds
Started Jul 25 07:00:58 PM PDT 24
Finished Jul 25 07:01:04 PM PDT 24
Peak memory 207420 kb
Host smart-77b67d44-2f8d-4e8b-ba06-0f46b1d7d08b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164942679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon
_wake_disconnect.164942679
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.1104100988
Short name T2204
Test name
Test status
Simulation time 13370235153 ps
CPU time 16.48 seconds
Started Jul 25 07:01:07 PM PDT 24
Finished Jul 25 07:01:23 PM PDT 24
Peak memory 207388 kb
Host smart-d2475358-4ba9-4e80-8d6b-fd0b38af298d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104100988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.1104100988
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.903947372
Short name T2580
Test name
Test status
Simulation time 23406563662 ps
CPU time 33.42 seconds
Started Jul 25 07:01:02 PM PDT 24
Finished Jul 25 07:01:35 PM PDT 24
Peak memory 207360 kb
Host smart-47a68230-8a50-4c4f-9a08-92a4e2f1e127
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903947372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon
_wake_resume.903947372
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.1008773431
Short name T1182
Test name
Test status
Simulation time 193648075 ps
CPU time 0.99 seconds
Started Jul 25 07:01:02 PM PDT 24
Finished Jul 25 07:01:03 PM PDT 24
Peak memory 207120 kb
Host smart-a1b06967-26f8-4031-b071-26783ec303f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10087
73431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.1008773431
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.1986911719
Short name T71
Test name
Test status
Simulation time 132360929 ps
CPU time 0.83 seconds
Started Jul 25 07:00:57 PM PDT 24
Finished Jul 25 07:00:58 PM PDT 24
Peak memory 207080 kb
Host smart-6661f380-6996-4d54-b3cb-78058ff5997d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19869
11719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.1986911719
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.1858040669
Short name T1849
Test name
Test status
Simulation time 147308619 ps
CPU time 0.86 seconds
Started Jul 25 07:00:58 PM PDT 24
Finished Jul 25 07:00:59 PM PDT 24
Peak memory 207088 kb
Host smart-2e90b814-e329-4169-b783-c393f6a0e2ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18580
40669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.1858040669
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.2351922371
Short name T106
Test name
Test status
Simulation time 439234166 ps
CPU time 1.52 seconds
Started Jul 25 07:01:01 PM PDT 24
Finished Jul 25 07:01:03 PM PDT 24
Peak memory 207132 kb
Host smart-016df167-564b-40a9-9f8c-d4b0893430dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23519
22371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.2351922371
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.354943182
Short name T2271
Test name
Test status
Simulation time 723046834 ps
CPU time 1.94 seconds
Started Jul 25 07:01:03 PM PDT 24
Finished Jul 25 07:01:05 PM PDT 24
Peak memory 207120 kb
Host smart-d08d24f6-1115-4213-8da5-b88195f6d754
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=354943182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.354943182
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_timeout.3507040989
Short name T993
Test name
Test status
Simulation time 3900472508 ps
CPU time 33.52 seconds
Started Jul 25 07:01:03 PM PDT 24
Finished Jul 25 07:01:37 PM PDT 24
Peak memory 207400 kb
Host smart-02e8f439-803c-4ef0-a81c-d38ff68f66cc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507040989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_timeout.3507040989
Directory /workspace/3.usbdev_device_timeout/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.2012634032
Short name T1158
Test name
Test status
Simulation time 379478270 ps
CPU time 1.36 seconds
Started Jul 25 07:01:02 PM PDT 24
Finished Jul 25 07:01:04 PM PDT 24
Peak memory 207084 kb
Host smart-ba0cc306-e591-4736-a33c-f07c8c32edb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20126
34032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.2012634032
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.1766841468
Short name T2133
Test name
Test status
Simulation time 138851362 ps
CPU time 0.79 seconds
Started Jul 25 07:00:57 PM PDT 24
Finished Jul 25 07:00:58 PM PDT 24
Peak memory 207120 kb
Host smart-36caa6b0-cd23-4084-9601-f74b07ceb5c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17668
41468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.1766841468
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.1203599577
Short name T2154
Test name
Test status
Simulation time 31477857 ps
CPU time 0.69 seconds
Started Jul 25 07:01:01 PM PDT 24
Finished Jul 25 07:01:02 PM PDT 24
Peak memory 207096 kb
Host smart-0bc4dced-c42a-4767-b8f2-424ab222370c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12035
99577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.1203599577
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.3638130447
Short name T1742
Test name
Test status
Simulation time 942619773 ps
CPU time 2.66 seconds
Started Jul 25 07:01:10 PM PDT 24
Finished Jul 25 07:01:13 PM PDT 24
Peak memory 207368 kb
Host smart-4bb7b398-202e-4a6c-be70-c3529da86d72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36381
30447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.3638130447
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.948753467
Short name T201
Test name
Test status
Simulation time 388910664 ps
CPU time 2.7 seconds
Started Jul 25 07:01:10 PM PDT 24
Finished Jul 25 07:01:13 PM PDT 24
Peak memory 207256 kb
Host smart-3e54b367-df0b-452c-9091-234d130e0d99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94875
3467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.948753467
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.1205231503
Short name T1479
Test name
Test status
Simulation time 114192868887 ps
CPU time 189.57 seconds
Started Jul 25 07:01:10 PM PDT 24
Finished Jul 25 07:04:19 PM PDT 24
Peak memory 207404 kb
Host smart-0851e9dc-0fbe-4bba-b79a-30a3da8c1ecd
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1205231503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.1205231503
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.4046002510
Short name T45
Test name
Test status
Simulation time 83189305977 ps
CPU time 144.92 seconds
Started Jul 25 07:01:28 PM PDT 24
Finished Jul 25 07:03:54 PM PDT 24
Peak memory 207392 kb
Host smart-157f4e08-e1a3-4572-9abf-cc2bcc8cc67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046002510 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.4046002510
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.3267048262
Short name T2061
Test name
Test status
Simulation time 120139125356 ps
CPU time 220.94 seconds
Started Jul 25 07:01:09 PM PDT 24
Finished Jul 25 07:04:50 PM PDT 24
Peak memory 207344 kb
Host smart-754b9b74-8b1c-421b-a042-2f097d5e2230
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3267048262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.3267048262
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.702704488
Short name T836
Test name
Test status
Simulation time 90046493231 ps
CPU time 133.78 seconds
Started Jul 25 07:01:08 PM PDT 24
Finished Jul 25 07:03:22 PM PDT 24
Peak memory 207440 kb
Host smart-135c503e-7341-46b9-bd13-6f82997dcb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702704488 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.702704488
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.41940113
Short name T1867
Test name
Test status
Simulation time 119165617525 ps
CPU time 173.79 seconds
Started Jul 25 07:01:09 PM PDT 24
Finished Jul 25 07:04:03 PM PDT 24
Peak memory 207404 kb
Host smart-4dbcbcea-cddd-4545-b712-746195f12ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41940
113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.41940113
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.1941109580
Short name T1748
Test name
Test status
Simulation time 237995478 ps
CPU time 1.23 seconds
Started Jul 25 07:01:09 PM PDT 24
Finished Jul 25 07:01:11 PM PDT 24
Peak memory 215516 kb
Host smart-e4d788b3-b574-4e94-a2a3-cc94a7c709a5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1941109580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.1941109580
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.3464519279
Short name T462
Test name
Test status
Simulation time 149173337 ps
CPU time 0.82 seconds
Started Jul 25 07:01:10 PM PDT 24
Finished Jul 25 07:01:11 PM PDT 24
Peak memory 207088 kb
Host smart-2d91a0e8-7203-4a9f-8749-e397bb45466d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34645
19279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.3464519279
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.2095043723
Short name T696
Test name
Test status
Simulation time 221598359 ps
CPU time 1.04 seconds
Started Jul 25 07:01:13 PM PDT 24
Finished Jul 25 07:01:14 PM PDT 24
Peak memory 207160 kb
Host smart-ce355ecc-8de5-4509-b658-0bc8e89cf8ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20950
43723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.2095043723
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_invalid_sync.1891649214
Short name T2442
Test name
Test status
Simulation time 6787671666 ps
CPU time 52.89 seconds
Started Jul 25 07:01:09 PM PDT 24
Finished Jul 25 07:02:02 PM PDT 24
Peak memory 217140 kb
Host smart-495a6f7d-e91d-4989-98e4-5572dc4e7bb1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1891649214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.1891649214
Directory /workspace/3.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_iso_retraction.3209153722
Short name T531
Test name
Test status
Simulation time 14440719235 ps
CPU time 101.76 seconds
Started Jul 25 07:01:09 PM PDT 24
Finished Jul 25 07:02:51 PM PDT 24
Peak memory 207372 kb
Host smart-edd15774-c0d4-4fd6-83de-a2937e544936
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3209153722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.3209153722
Directory /workspace/3.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.3675896257
Short name T789
Test name
Test status
Simulation time 199890432 ps
CPU time 0.9 seconds
Started Jul 25 07:01:09 PM PDT 24
Finished Jul 25 07:01:10 PM PDT 24
Peak memory 207072 kb
Host smart-3b6f54e7-1694-48d4-9729-70fa4aed8d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36758
96257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.3675896257
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.1942895854
Short name T859
Test name
Test status
Simulation time 23321070043 ps
CPU time 28.96 seconds
Started Jul 25 07:01:10 PM PDT 24
Finished Jul 25 07:01:39 PM PDT 24
Peak memory 207436 kb
Host smart-afef9334-3230-4ba9-bde1-ef83d5488d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19428
95854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.1942895854
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.868246969
Short name T1707
Test name
Test status
Simulation time 3299064577 ps
CPU time 4.86 seconds
Started Jul 25 07:01:09 PM PDT 24
Finished Jul 25 07:01:14 PM PDT 24
Peak memory 207480 kb
Host smart-95a0ffc1-550c-4ed4-8833-62ddc0685708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86824
6969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.868246969
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.2014438711
Short name T373
Test name
Test status
Simulation time 5225446968 ps
CPU time 50.89 seconds
Started Jul 25 07:01:08 PM PDT 24
Finished Jul 25 07:01:59 PM PDT 24
Peak memory 217444 kb
Host smart-2ad396e6-0ab9-4be8-a1b5-758a68fec845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20144
38711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.2014438711
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.521929470
Short name T768
Test name
Test status
Simulation time 5358297357 ps
CPU time 43.32 seconds
Started Jul 25 07:01:07 PM PDT 24
Finished Jul 25 07:01:51 PM PDT 24
Peak memory 207420 kb
Host smart-012e62a9-b0f6-4f1a-ad50-e851d32c27f2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=521929470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.521929470
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.3214551544
Short name T2594
Test name
Test status
Simulation time 247706525 ps
CPU time 0.95 seconds
Started Jul 25 07:01:17 PM PDT 24
Finished Jul 25 07:01:18 PM PDT 24
Peak memory 207136 kb
Host smart-8ddcbe01-22c8-4669-9367-790da317584b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3214551544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.3214551544
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.2018253870
Short name T2225
Test name
Test status
Simulation time 203855608 ps
CPU time 0.98 seconds
Started Jul 25 07:01:12 PM PDT 24
Finished Jul 25 07:01:13 PM PDT 24
Peak memory 207052 kb
Host smart-4f5734b4-d85c-4f54-8b35-7ba3c7cf7403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20182
53870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.2018253870
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.1615104878
Short name T1555
Test name
Test status
Simulation time 4843955855 ps
CPU time 37.16 seconds
Started Jul 25 07:01:11 PM PDT 24
Finished Jul 25 07:01:48 PM PDT 24
Peak memory 215536 kb
Host smart-a0cbb7c5-5457-49de-85df-1e835ef56fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16151
04878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.1615104878
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.1022220614
Short name T2279
Test name
Test status
Simulation time 3317667979 ps
CPU time 99.6 seconds
Started Jul 25 07:01:11 PM PDT 24
Finished Jul 25 07:02:50 PM PDT 24
Peak memory 215572 kb
Host smart-e99ab1cc-f81a-48ac-b3fe-bcb054fa9def
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1022220614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.1022220614
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.2571666472
Short name T263
Test name
Test status
Simulation time 153882772 ps
CPU time 0.86 seconds
Started Jul 25 07:01:09 PM PDT 24
Finished Jul 25 07:01:10 PM PDT 24
Peak memory 207116 kb
Host smart-8caf2a93-319d-4b49-9749-149578e39909
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2571666472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.2571666472
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.1031061751
Short name T356
Test name
Test status
Simulation time 159929477 ps
CPU time 0.85 seconds
Started Jul 25 07:01:12 PM PDT 24
Finished Jul 25 07:01:13 PM PDT 24
Peak memory 207132 kb
Host smart-25d45b5f-135c-4c55-9d06-5fb27818f113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10310
61751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.1031061751
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.4254404947
Short name T2617
Test name
Test status
Simulation time 180182889 ps
CPU time 1.15 seconds
Started Jul 25 07:01:11 PM PDT 24
Finished Jul 25 07:01:13 PM PDT 24
Peak memory 207160 kb
Host smart-8c0e5f45-946a-4a05-9580-a43c6f099ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42544
04947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.4254404947
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.3554111183
Short name T699
Test name
Test status
Simulation time 156935296 ps
CPU time 0.87 seconds
Started Jul 25 07:01:13 PM PDT 24
Finished Jul 25 07:01:14 PM PDT 24
Peak memory 207128 kb
Host smart-120f7910-edd0-4e49-b145-4b3500da962d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35541
11183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.3554111183
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.915965234
Short name T850
Test name
Test status
Simulation time 187825014 ps
CPU time 1.02 seconds
Started Jul 25 07:01:11 PM PDT 24
Finished Jul 25 07:01:13 PM PDT 24
Peak memory 207072 kb
Host smart-0138b943-ae50-4501-a788-f876b6121840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91596
5234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.915965234
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.1419228796
Short name T606
Test name
Test status
Simulation time 152656988 ps
CPU time 0.82 seconds
Started Jul 25 07:01:11 PM PDT 24
Finished Jul 25 07:01:12 PM PDT 24
Peak memory 207108 kb
Host smart-9c51c43e-c818-4b02-8eb7-84bd01f78a92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14192
28796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.1419228796
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.2484652798
Short name T433
Test name
Test status
Simulation time 251194221 ps
CPU time 1.03 seconds
Started Jul 25 07:01:10 PM PDT 24
Finished Jul 25 07:01:12 PM PDT 24
Peak memory 207108 kb
Host smart-3637c47c-ff14-4732-9c2d-dd6865d144f7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2484652798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.2484652798
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.2366141520
Short name T2384
Test name
Test status
Simulation time 305207168 ps
CPU time 1.13 seconds
Started Jul 25 07:01:11 PM PDT 24
Finished Jul 25 07:01:13 PM PDT 24
Peak memory 207172 kb
Host smart-0194c93d-4025-4c36-a2ec-e2bd17e29988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23661
41520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.2366141520
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.3077580342
Short name T873
Test name
Test status
Simulation time 173321891 ps
CPU time 0.87 seconds
Started Jul 25 07:01:11 PM PDT 24
Finished Jul 25 07:01:12 PM PDT 24
Peak memory 207040 kb
Host smart-35696852-5e96-4f94-bc10-1cb956ad68b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30775
80342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.3077580342
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.3748092955
Short name T2527
Test name
Test status
Simulation time 36154266 ps
CPU time 0.69 seconds
Started Jul 25 07:01:13 PM PDT 24
Finished Jul 25 07:01:14 PM PDT 24
Peak memory 207104 kb
Host smart-88045118-853e-431f-949f-f943200d630a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37480
92955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.3748092955
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.1508693220
Short name T1871
Test name
Test status
Simulation time 9907516020 ps
CPU time 24.46 seconds
Started Jul 25 07:01:11 PM PDT 24
Finished Jul 25 07:01:36 PM PDT 24
Peak memory 215536 kb
Host smart-0b6f07d1-eeac-4e00-9b17-494b5fe444b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15086
93220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.1508693220
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.1992458267
Short name T329
Test name
Test status
Simulation time 169989483 ps
CPU time 0.86 seconds
Started Jul 25 07:01:13 PM PDT 24
Finished Jul 25 07:01:15 PM PDT 24
Peak memory 207088 kb
Host smart-f4442f2e-17f1-41d1-ac8d-88da1dbc6d2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19924
58267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.1992458267
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.1582273424
Short name T1041
Test name
Test status
Simulation time 197326600 ps
CPU time 0.95 seconds
Started Jul 25 07:01:11 PM PDT 24
Finished Jul 25 07:01:12 PM PDT 24
Peak memory 207128 kb
Host smart-d410276b-f35f-404c-ae5c-e84c54136ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15822
73424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.1582273424
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.2386554763
Short name T43
Test name
Test status
Simulation time 8266754755 ps
CPU time 128.74 seconds
Started Jul 25 07:01:09 PM PDT 24
Finished Jul 25 07:03:18 PM PDT 24
Peak memory 215604 kb
Host smart-31546517-9fe2-4fbe-ba04-2dd6080020cf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386554763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.2386554763
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.2331583233
Short name T877
Test name
Test status
Simulation time 19564315383 ps
CPU time 114.44 seconds
Started Jul 25 07:01:11 PM PDT 24
Finished Jul 25 07:03:06 PM PDT 24
Peak memory 223716 kb
Host smart-5396f54e-2b5c-4ac5-bcb3-641ec983abd4
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331583233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.2331583233
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.1854508985
Short name T372
Test name
Test status
Simulation time 219399234 ps
CPU time 1.01 seconds
Started Jul 25 07:01:12 PM PDT 24
Finished Jul 25 07:01:13 PM PDT 24
Peak memory 207120 kb
Host smart-fc65d61b-2e73-4fcf-836e-c7e60a5225ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18545
08985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.1854508985
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.2312071776
Short name T2524
Test name
Test status
Simulation time 183265326 ps
CPU time 0.94 seconds
Started Jul 25 07:01:13 PM PDT 24
Finished Jul 25 07:01:15 PM PDT 24
Peak memory 207104 kb
Host smart-7a65622a-6625-4db7-9357-f68e92404e57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23120
71776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.2312071776
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.3890007370
Short name T83
Test name
Test status
Simulation time 142874664 ps
CPU time 0.83 seconds
Started Jul 25 07:01:11 PM PDT 24
Finished Jul 25 07:01:12 PM PDT 24
Peak memory 207088 kb
Host smart-014297b9-6c88-4c03-a162-5904c67e8d65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38900
07370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.3890007370
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.2403250468
Short name T87
Test name
Test status
Simulation time 177283237 ps
CPU time 0.88 seconds
Started Jul 25 07:01:13 PM PDT 24
Finished Jul 25 07:01:14 PM PDT 24
Peak memory 207112 kb
Host smart-40680d0a-7dd9-4ee3-bc05-0bdbb53f11b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24032
50468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.2403250468
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.652393230
Short name T226
Test name
Test status
Simulation time 254216290 ps
CPU time 1.15 seconds
Started Jul 25 07:01:14 PM PDT 24
Finished Jul 25 07:01:16 PM PDT 24
Peak memory 223028 kb
Host smart-aaba198f-23fb-4093-a57e-68652193fa60
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=652393230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.652393230
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.1329357790
Short name T2835
Test name
Test status
Simulation time 471986137 ps
CPU time 1.48 seconds
Started Jul 25 07:01:12 PM PDT 24
Finished Jul 25 07:01:14 PM PDT 24
Peak memory 207212 kb
Host smart-01402c8d-8ff3-4131-a3d1-95e4c67124c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13293
57790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.1329357790
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.3574166026
Short name T2104
Test name
Test status
Simulation time 169672360 ps
CPU time 0.99 seconds
Started Jul 25 07:01:12 PM PDT 24
Finished Jul 25 07:01:13 PM PDT 24
Peak memory 207056 kb
Host smart-44e02cc9-3b51-4e17-9eb4-5a01ec93a58f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35741
66026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.3574166026
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.53932111
Short name T2349
Test name
Test status
Simulation time 152713402 ps
CPU time 0.85 seconds
Started Jul 25 07:01:12 PM PDT 24
Finished Jul 25 07:01:13 PM PDT 24
Peak memory 207072 kb
Host smart-41195034-69d6-4715-861e-8e6c7cbfa3be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53932
111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.53932111
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.260642490
Short name T876
Test name
Test status
Simulation time 199818486 ps
CPU time 0.95 seconds
Started Jul 25 07:01:12 PM PDT 24
Finished Jul 25 07:01:14 PM PDT 24
Peak memory 207124 kb
Host smart-87bb434e-f66d-4650-97f0-df0801fa75c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26064
2490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.260642490
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.4274957274
Short name T361
Test name
Test status
Simulation time 208261759 ps
CPU time 0.94 seconds
Started Jul 25 07:01:11 PM PDT 24
Finished Jul 25 07:01:12 PM PDT 24
Peak memory 207132 kb
Host smart-216f6c7f-cac1-4eff-84ac-dd8dd9fae12c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42749
57274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.4274957274
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.403384112
Short name T1105
Test name
Test status
Simulation time 3825258299 ps
CPU time 32.65 seconds
Started Jul 25 07:01:12 PM PDT 24
Finished Jul 25 07:01:45 PM PDT 24
Peak memory 215592 kb
Host smart-868156f0-0f9b-450e-80be-db3701e73359
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=403384112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.403384112
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.2401066027
Short name T1219
Test name
Test status
Simulation time 216856464 ps
CPU time 0.96 seconds
Started Jul 25 07:01:12 PM PDT 24
Finished Jul 25 07:01:14 PM PDT 24
Peak memory 207220 kb
Host smart-3ef060e8-5114-4fad-b1a0-f7e3b5fcb78e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24010
66027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.2401066027
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.3702737478
Short name T809
Test name
Test status
Simulation time 169209798 ps
CPU time 0.86 seconds
Started Jul 25 07:01:12 PM PDT 24
Finished Jul 25 07:01:14 PM PDT 24
Peak memory 207132 kb
Host smart-82e0a817-2b16-472a-b432-bb04f940d88e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37027
37478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.3702737478
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.1389959718
Short name T397
Test name
Test status
Simulation time 197618919 ps
CPU time 0.99 seconds
Started Jul 25 07:01:12 PM PDT 24
Finished Jul 25 07:01:13 PM PDT 24
Peak memory 207076 kb
Host smart-2f1e1293-7421-426d-a628-17e59c3232cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13899
59718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.1389959718
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.2886973249
Short name T2694
Test name
Test status
Simulation time 4594097052 ps
CPU time 47.01 seconds
Started Jul 25 07:01:12 PM PDT 24
Finished Jul 25 07:01:59 PM PDT 24
Peak memory 207396 kb
Host smart-6288b871-b056-4c2f-a2d5-9d7576a797ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28869
73249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.2886973249
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.2833255022
Short name T95
Test name
Test status
Simulation time 12686533696 ps
CPU time 90.11 seconds
Started Jul 25 07:01:12 PM PDT 24
Finished Jul 25 07:02:43 PM PDT 24
Peak memory 215600 kb
Host smart-e4a5156a-b4d9-4c32-9a52-123feff012cb
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833255022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.2833255022
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_timeout_missing_host_handshake.2820582666
Short name T477
Test name
Test status
Simulation time 1553889885 ps
CPU time 13.07 seconds
Started Jul 25 07:01:01 PM PDT 24
Finished Jul 25 07:01:14 PM PDT 24
Peak memory 207380 kb
Host smart-6717d07b-dba0-4b9c-8b6e-9274c7b3a436
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820582666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_timeout_missing_host
_handshake.2820582666
Directory /workspace/3.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.1819726371
Short name T636
Test name
Test status
Simulation time 66654691 ps
CPU time 0.71 seconds
Started Jul 25 07:06:06 PM PDT 24
Finished Jul 25 07:06:07 PM PDT 24
Peak memory 207136 kb
Host smart-9302dcee-e457-4bce-ab95-9cfc20bb2cbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1819726371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.1819726371
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.1386746500
Short name T2007
Test name
Test status
Simulation time 4270922652 ps
CPU time 6.22 seconds
Started Jul 25 07:05:54 PM PDT 24
Finished Jul 25 07:06:01 PM PDT 24
Peak memory 207368 kb
Host smart-8eb0987d-02a8-4058-ab31-0a5a77e7065e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386746500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_a
on_wake_disconnect.1386746500
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.2092254322
Short name T1476
Test name
Test status
Simulation time 13312308404 ps
CPU time 16.17 seconds
Started Jul 25 07:05:57 PM PDT 24
Finished Jul 25 07:06:14 PM PDT 24
Peak memory 207316 kb
Host smart-cdce457b-643e-45bb-b5f0-8f954ae06a1b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092254322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.2092254322
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.3472947196
Short name T206
Test name
Test status
Simulation time 23368979744 ps
CPU time 28.66 seconds
Started Jul 25 07:05:57 PM PDT 24
Finished Jul 25 07:06:26 PM PDT 24
Peak memory 207332 kb
Host smart-2576a8cf-a1a7-47c2-839d-fc5cecc1a5c2
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472947196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_a
on_wake_resume.3472947196
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.2411200670
Short name T587
Test name
Test status
Simulation time 212280759 ps
CPU time 0.95 seconds
Started Jul 25 07:05:50 PM PDT 24
Finished Jul 25 07:05:51 PM PDT 24
Peak memory 207160 kb
Host smart-afc8c1dc-b9b0-40d6-923b-76a03d0495fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24112
00670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.2411200670
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.2885722331
Short name T1584
Test name
Test status
Simulation time 148024347 ps
CPU time 0.85 seconds
Started Jul 25 07:06:05 PM PDT 24
Finished Jul 25 07:06:05 PM PDT 24
Peak memory 207092 kb
Host smart-634ea7f2-aed7-4dc2-8b7f-bef872d27e1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28857
22331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.2885722331
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.1296110688
Short name T609
Test name
Test status
Simulation time 305291341 ps
CPU time 1.27 seconds
Started Jul 25 07:05:55 PM PDT 24
Finished Jul 25 07:05:56 PM PDT 24
Peak memory 207196 kb
Host smart-3a0c1b70-5a23-4a82-8c59-8a6e8b7be9cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12961
10688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.1296110688
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.2696499600
Short name T2695
Test name
Test status
Simulation time 333442324 ps
CPU time 1.19 seconds
Started Jul 25 07:05:58 PM PDT 24
Finished Jul 25 07:05:59 PM PDT 24
Peak memory 207076 kb
Host smart-3dc29dad-b1f5-4fcf-a33f-7eeb7e985cb4
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2696499600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.2696499600
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_timeout.3411145682
Short name T2010
Test name
Test status
Simulation time 376760165 ps
CPU time 4.67 seconds
Started Jul 25 07:06:02 PM PDT 24
Finished Jul 25 07:06:07 PM PDT 24
Peak memory 207360 kb
Host smart-2d707967-3330-4beb-bd50-697d53c8cd8e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411145682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_timeout.3411145682
Directory /workspace/30.usbdev_device_timeout/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.3328370515
Short name T2409
Test name
Test status
Simulation time 337720499 ps
CPU time 1.29 seconds
Started Jul 25 07:06:01 PM PDT 24
Finished Jul 25 07:06:02 PM PDT 24
Peak memory 207100 kb
Host smart-086ab0e9-9382-480a-8ed2-1223c0ffd507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33283
70515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.3328370515
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.4259795892
Short name T956
Test name
Test status
Simulation time 169941697 ps
CPU time 0.88 seconds
Started Jul 25 07:06:03 PM PDT 24
Finished Jul 25 07:06:04 PM PDT 24
Peak memory 207088 kb
Host smart-acbb46fb-95dd-42d5-a31c-e3f6a651f78a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42597
95892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.4259795892
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.3976173497
Short name T2736
Test name
Test status
Simulation time 96415994 ps
CPU time 0.77 seconds
Started Jul 25 07:06:04 PM PDT 24
Finished Jul 25 07:06:05 PM PDT 24
Peak memory 207080 kb
Host smart-21aa70ba-9c2e-42bc-893b-caa620245889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39761
73497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.3976173497
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.1696173118
Short name T718
Test name
Test status
Simulation time 839472853 ps
CPU time 2.23 seconds
Started Jul 25 07:06:03 PM PDT 24
Finished Jul 25 07:06:05 PM PDT 24
Peak memory 207264 kb
Host smart-ab83da88-33c1-4788-ae74-decf96051a8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16961
73118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.1696173118
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.585173092
Short name T1215
Test name
Test status
Simulation time 330155853 ps
CPU time 2.31 seconds
Started Jul 25 07:06:01 PM PDT 24
Finished Jul 25 07:06:04 PM PDT 24
Peak memory 207424 kb
Host smart-9395b73f-e7a7-4b83-b3cc-4a82fb764433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58517
3092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.585173092
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.503660156
Short name T1702
Test name
Test status
Simulation time 171548653 ps
CPU time 0.91 seconds
Started Jul 25 07:06:10 PM PDT 24
Finished Jul 25 07:06:11 PM PDT 24
Peak memory 207132 kb
Host smart-d2025581-a59c-43b4-b6d1-f451f5049072
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=503660156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.503660156
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.3526229603
Short name T826
Test name
Test status
Simulation time 157689307 ps
CPU time 0.83 seconds
Started Jul 25 07:06:06 PM PDT 24
Finished Jul 25 07:06:07 PM PDT 24
Peak memory 207080 kb
Host smart-0fcd4f7b-2f21-4cb6-b7fd-3c82cf9ab373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35262
29603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.3526229603
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.674686704
Short name T1374
Test name
Test status
Simulation time 178406389 ps
CPU time 0.89 seconds
Started Jul 25 07:06:03 PM PDT 24
Finished Jul 25 07:06:04 PM PDT 24
Peak memory 207160 kb
Host smart-a046f615-1376-4f15-84ee-f6a46e3aed96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67468
6704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.674686704
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_invalid_sync.3909433624
Short name T2274
Test name
Test status
Simulation time 6548408482 ps
CPU time 68.32 seconds
Started Jul 25 07:06:04 PM PDT 24
Finished Jul 25 07:07:12 PM PDT 24
Peak memory 207404 kb
Host smart-2e9fbf4b-907a-4287-8f83-b5c76f28493d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3909433624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.3909433624
Directory /workspace/30.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/30.usbdev_iso_retraction.2725174269
Short name T1656
Test name
Test status
Simulation time 15441421947 ps
CPU time 118.53 seconds
Started Jul 25 07:06:04 PM PDT 24
Finished Jul 25 07:08:03 PM PDT 24
Peak memory 207296 kb
Host smart-49e7cedf-0b85-4129-92cb-57a5469afc37
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2725174269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_iso_retraction.2725174269
Directory /workspace/30.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.4195403857
Short name T2292
Test name
Test status
Simulation time 197835212 ps
CPU time 0.93 seconds
Started Jul 25 07:06:05 PM PDT 24
Finished Jul 25 07:06:06 PM PDT 24
Peak memory 207152 kb
Host smart-b75642ed-7cd6-44e2-9f4e-fce7d10cf018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41954
03857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.4195403857
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.228825974
Short name T693
Test name
Test status
Simulation time 23286110170 ps
CPU time 26.52 seconds
Started Jul 25 07:06:03 PM PDT 24
Finished Jul 25 07:06:29 PM PDT 24
Peak memory 207404 kb
Host smart-519d0e8c-ff56-4549-8a2e-dec12ff735ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22882
5974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.228825974
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.449096433
Short name T409
Test name
Test status
Simulation time 3427976129 ps
CPU time 5.05 seconds
Started Jul 25 07:06:06 PM PDT 24
Finished Jul 25 07:06:11 PM PDT 24
Peak memory 207408 kb
Host smart-9608c564-e458-4db6-b3c3-54d2a4443b54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44909
6433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.449096433
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.3575973957
Short name T1366
Test name
Test status
Simulation time 5430751331 ps
CPU time 156.94 seconds
Started Jul 25 07:06:05 PM PDT 24
Finished Jul 25 07:08:42 PM PDT 24
Peak memory 215580 kb
Host smart-9e8f382b-6838-4056-83f2-67d7757486bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35759
73957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.3575973957
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.4190380412
Short name T2266
Test name
Test status
Simulation time 3074347602 ps
CPU time 91.78 seconds
Started Jul 25 07:06:10 PM PDT 24
Finished Jul 25 07:07:42 PM PDT 24
Peak memory 215644 kb
Host smart-ef6fa300-101a-40af-ab09-e6ae559f8773
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4190380412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.4190380412
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.3420352700
Short name T864
Test name
Test status
Simulation time 259579354 ps
CPU time 1.05 seconds
Started Jul 25 07:06:02 PM PDT 24
Finished Jul 25 07:06:03 PM PDT 24
Peak memory 207116 kb
Host smart-1b153ba6-07f6-429d-b402-bbc4a639bee6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3420352700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.3420352700
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.3337001885
Short name T1734
Test name
Test status
Simulation time 223815887 ps
CPU time 1.06 seconds
Started Jul 25 07:06:11 PM PDT 24
Finished Jul 25 07:06:12 PM PDT 24
Peak memory 207124 kb
Host smart-c9ccfa36-17d7-4df7-b5b2-46702f7aa05e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33370
01885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.3337001885
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.507114968
Short name T866
Test name
Test status
Simulation time 3065118686 ps
CPU time 89.57 seconds
Started Jul 25 07:06:04 PM PDT 24
Finished Jul 25 07:07:34 PM PDT 24
Peak memory 215676 kb
Host smart-e41af9b6-5428-4eed-b21a-922f0a7053f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50711
4968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.507114968
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.1696060026
Short name T1756
Test name
Test status
Simulation time 4577759872 ps
CPU time 48.97 seconds
Started Jul 25 07:06:04 PM PDT 24
Finished Jul 25 07:06:53 PM PDT 24
Peak memory 207360 kb
Host smart-352ae807-21ba-45b3-a88a-61e2397098a3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1696060026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.1696060026
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.1346571922
Short name T1759
Test name
Test status
Simulation time 150442549 ps
CPU time 0.89 seconds
Started Jul 25 07:06:00 PM PDT 24
Finished Jul 25 07:06:01 PM PDT 24
Peak memory 207168 kb
Host smart-1761c79a-f935-41f4-8217-d9c90c9d71a2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1346571922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.1346571922
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.1576137834
Short name T1715
Test name
Test status
Simulation time 172624433 ps
CPU time 0.88 seconds
Started Jul 25 07:06:02 PM PDT 24
Finished Jul 25 07:06:03 PM PDT 24
Peak memory 207064 kb
Host smart-db59316c-aca0-4cc1-9f1a-371498dc61d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15761
37834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.1576137834
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.3707579382
Short name T148
Test name
Test status
Simulation time 208350791 ps
CPU time 0.98 seconds
Started Jul 25 07:06:00 PM PDT 24
Finished Jul 25 07:06:01 PM PDT 24
Peak memory 207116 kb
Host smart-7fd3c764-2582-47a8-a66c-9bd451bc6abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37075
79382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.3707579382
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.2232542779
Short name T1059
Test name
Test status
Simulation time 160272870 ps
CPU time 0.92 seconds
Started Jul 25 07:06:02 PM PDT 24
Finished Jul 25 07:06:03 PM PDT 24
Peak memory 207072 kb
Host smart-4e7d70e2-81eb-4009-a8f2-e2a42c9a50ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22325
42779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.2232542779
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.2104501195
Short name T901
Test name
Test status
Simulation time 174586862 ps
CPU time 0.87 seconds
Started Jul 25 07:06:05 PM PDT 24
Finished Jul 25 07:06:06 PM PDT 24
Peak memory 207076 kb
Host smart-298f4bb1-e26b-4909-967f-54603bd9765a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21045
01195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.2104501195
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.2355326356
Short name T543
Test name
Test status
Simulation time 150811663 ps
CPU time 0.88 seconds
Started Jul 25 07:06:11 PM PDT 24
Finished Jul 25 07:06:12 PM PDT 24
Peak memory 207148 kb
Host smart-23186339-f883-4556-8613-d7d7e8685875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23553
26356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.2355326356
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.2485733607
Short name T2703
Test name
Test status
Simulation time 149306872 ps
CPU time 0.84 seconds
Started Jul 25 07:06:11 PM PDT 24
Finished Jul 25 07:06:12 PM PDT 24
Peak memory 207124 kb
Host smart-12eb17d9-d614-404f-8999-b16d39b4700e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24857
33607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.2485733607
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.586312644
Short name T1637
Test name
Test status
Simulation time 227869250 ps
CPU time 1.09 seconds
Started Jul 25 07:06:11 PM PDT 24
Finished Jul 25 07:06:12 PM PDT 24
Peak memory 207152 kb
Host smart-906fd776-00a4-49a3-bc7f-960cc86330dd
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=586312644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.586312644
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.768389979
Short name T899
Test name
Test status
Simulation time 138028156 ps
CPU time 0.84 seconds
Started Jul 25 07:06:11 PM PDT 24
Finished Jul 25 07:06:12 PM PDT 24
Peak memory 207092 kb
Host smart-017276c0-a84b-4814-aaf7-400397494bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76838
9979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.768389979
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.3699330122
Short name T39
Test name
Test status
Simulation time 72802320 ps
CPU time 0.76 seconds
Started Jul 25 07:06:05 PM PDT 24
Finished Jul 25 07:06:06 PM PDT 24
Peak memory 207116 kb
Host smart-37457fef-d4a5-430e-b219-8140789b6a02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36993
30122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.3699330122
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.817947710
Short name T743
Test name
Test status
Simulation time 15668232346 ps
CPU time 40.27 seconds
Started Jul 25 07:06:07 PM PDT 24
Finished Jul 25 07:06:48 PM PDT 24
Peak memory 215612 kb
Host smart-011bcc8a-9e6a-4ee9-be9b-623deb086393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81794
7710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.817947710
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.795930337
Short name T619
Test name
Test status
Simulation time 212335592 ps
CPU time 0.99 seconds
Started Jul 25 07:06:14 PM PDT 24
Finished Jul 25 07:06:15 PM PDT 24
Peak memory 207080 kb
Host smart-edc812b0-953c-470e-9b8d-8012fdc95a8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79593
0337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.795930337
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.1995859142
Short name T2203
Test name
Test status
Simulation time 224171151 ps
CPU time 1 seconds
Started Jul 25 07:06:05 PM PDT 24
Finished Jul 25 07:06:07 PM PDT 24
Peak memory 207136 kb
Host smart-6feb1763-2255-4810-adbd-ef053e440b73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19958
59142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.1995859142
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.2864259940
Short name T656
Test name
Test status
Simulation time 208562725 ps
CPU time 0.96 seconds
Started Jul 25 07:06:05 PM PDT 24
Finished Jul 25 07:06:06 PM PDT 24
Peak memory 207052 kb
Host smart-4f85f6a2-aeb8-44b8-9525-fd946831e46c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28642
59940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.2864259940
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.2213841849
Short name T621
Test name
Test status
Simulation time 215588282 ps
CPU time 1.02 seconds
Started Jul 25 07:06:11 PM PDT 24
Finished Jul 25 07:06:12 PM PDT 24
Peak memory 207116 kb
Host smart-e8a19da5-f1a7-41d1-980e-eae9a32c317b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22138
41849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.2213841849
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.2735019026
Short name T1252
Test name
Test status
Simulation time 177363602 ps
CPU time 0.86 seconds
Started Jul 25 07:06:03 PM PDT 24
Finished Jul 25 07:06:04 PM PDT 24
Peak memory 207160 kb
Host smart-ad16c530-4907-4959-be26-beebb4fdc895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27350
19026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.2735019026
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.3055219140
Short name T884
Test name
Test status
Simulation time 155463865 ps
CPU time 0.83 seconds
Started Jul 25 07:06:05 PM PDT 24
Finished Jul 25 07:06:06 PM PDT 24
Peak memory 207088 kb
Host smart-1b40cee5-c394-4602-bc8c-cffc49ce302b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30552
19140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.3055219140
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.1628017633
Short name T496
Test name
Test status
Simulation time 185897374 ps
CPU time 0.88 seconds
Started Jul 25 07:06:05 PM PDT 24
Finished Jul 25 07:06:06 PM PDT 24
Peak memory 207228 kb
Host smart-e8440c66-9ed5-4622-b783-487a76e03b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16280
17633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.1628017633
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.676755196
Short name T553
Test name
Test status
Simulation time 282141707 ps
CPU time 1.12 seconds
Started Jul 25 07:06:06 PM PDT 24
Finished Jul 25 07:06:08 PM PDT 24
Peak memory 207132 kb
Host smart-4754ff2c-3a69-4ee4-b7da-a9bf914d1373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67675
5196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.676755196
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.4111644183
Short name T115
Test name
Test status
Simulation time 4777138300 ps
CPU time 139.51 seconds
Started Jul 25 07:06:05 PM PDT 24
Finished Jul 25 07:08:25 PM PDT 24
Peak memory 215576 kb
Host smart-020cc1c9-314e-4afa-8683-821e3a8587b6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4111644183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.4111644183
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.119351308
Short name T2265
Test name
Test status
Simulation time 146042470 ps
CPU time 0.87 seconds
Started Jul 25 07:06:04 PM PDT 24
Finished Jul 25 07:06:05 PM PDT 24
Peak memory 207128 kb
Host smart-482e1f81-c627-4b6e-afd5-cf59d6f0f11d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11935
1308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.119351308
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.1068146159
Short name T608
Test name
Test status
Simulation time 206448718 ps
CPU time 0.99 seconds
Started Jul 25 07:06:02 PM PDT 24
Finished Jul 25 07:06:03 PM PDT 24
Peak memory 207108 kb
Host smart-5b9f0d7f-dd93-454d-8803-b82daa39b8ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10681
46159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.1068146159
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.1977615379
Short name T2393
Test name
Test status
Simulation time 618868935 ps
CPU time 1.77 seconds
Started Jul 25 07:06:06 PM PDT 24
Finished Jul 25 07:06:08 PM PDT 24
Peak memory 207052 kb
Host smart-7ecb44e3-59a3-428c-a7b0-ad491137ce0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19776
15379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.1977615379
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.1126449929
Short name T700
Test name
Test status
Simulation time 2824191436 ps
CPU time 20.35 seconds
Started Jul 25 07:06:05 PM PDT 24
Finished Jul 25 07:06:26 PM PDT 24
Peak memory 216628 kb
Host smart-feeffe05-9777-47a8-af32-d0540b07481e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11264
49929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.1126449929
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/30.usbdev_timeout_missing_host_handshake.2680798627
Short name T2713
Test name
Test status
Simulation time 298547511 ps
CPU time 4.38 seconds
Started Jul 25 07:06:01 PM PDT 24
Finished Jul 25 07:06:06 PM PDT 24
Peak memory 207296 kb
Host smart-f2b7f624-e4b9-4070-b319-79ca431ae08f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680798627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_timeout_missing_hos
t_handshake.2680798627
Directory /workspace/30.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.3165264695
Short name T49
Test name
Test status
Simulation time 49030750 ps
CPU time 0.65 seconds
Started Jul 25 07:06:11 PM PDT 24
Finished Jul 25 07:06:11 PM PDT 24
Peak memory 207164 kb
Host smart-208de372-5d89-42de-a7b2-46e886729757
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3165264695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.3165264695
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.1856273554
Short name T1262
Test name
Test status
Simulation time 4242097583 ps
CPU time 6.02 seconds
Started Jul 25 07:06:05 PM PDT 24
Finished Jul 25 07:06:11 PM PDT 24
Peak memory 207392 kb
Host smart-414fbf50-5bbe-45a7-b3f4-be11a1a40423
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856273554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_a
on_wake_disconnect.1856273554
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.408981497
Short name T1398
Test name
Test status
Simulation time 13299764326 ps
CPU time 15.9 seconds
Started Jul 25 07:06:03 PM PDT 24
Finished Jul 25 07:06:19 PM PDT 24
Peak memory 207320 kb
Host smart-ac3f8021-1131-41d5-a859-92e0a5d7b1f4
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=408981497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.408981497
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.3057562506
Short name T1118
Test name
Test status
Simulation time 23378896834 ps
CPU time 27.87 seconds
Started Jul 25 07:06:09 PM PDT 24
Finished Jul 25 07:06:37 PM PDT 24
Peak memory 207356 kb
Host smart-af505bdd-31ab-4136-b601-c09a5425c1f1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057562506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_a
on_wake_resume.3057562506
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.1111687800
Short name T1534
Test name
Test status
Simulation time 191574813 ps
CPU time 0.89 seconds
Started Jul 25 07:06:05 PM PDT 24
Finished Jul 25 07:06:07 PM PDT 24
Peak memory 207124 kb
Host smart-54a0a920-502e-43d6-b3b0-1a3e9a9f21e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11116
87800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.1111687800
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.2627496857
Short name T1324
Test name
Test status
Simulation time 153674227 ps
CPU time 0.85 seconds
Started Jul 25 07:06:11 PM PDT 24
Finished Jul 25 07:06:12 PM PDT 24
Peak memory 207092 kb
Host smart-a897af60-dd10-4834-bca9-6f65ab9e36fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26274
96857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.2627496857
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.137587329
Short name T1870
Test name
Test status
Simulation time 326716615 ps
CPU time 1.31 seconds
Started Jul 25 07:06:11 PM PDT 24
Finished Jul 25 07:06:12 PM PDT 24
Peak memory 207124 kb
Host smart-f4cac9bc-6526-4d7c-a434-af260a78c288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13758
7329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.137587329
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.470359187
Short name T1314
Test name
Test status
Simulation time 1435543346 ps
CPU time 3.93 seconds
Started Jul 25 07:06:04 PM PDT 24
Finished Jul 25 07:06:08 PM PDT 24
Peak memory 207308 kb
Host smart-3caa613f-8517-4097-814a-c90ef4e35d4e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=470359187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.470359187
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.1499723431
Short name T2107
Test name
Test status
Simulation time 8251756932 ps
CPU time 20.51 seconds
Started Jul 25 07:06:05 PM PDT 24
Finished Jul 25 07:06:26 PM PDT 24
Peak memory 207332 kb
Host smart-a3bdc32c-7ba4-4caa-8d9d-c5dc91d5f131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14997
23431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.1499723431
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_device_timeout.425578007
Short name T1566
Test name
Test status
Simulation time 442128420 ps
CPU time 7.81 seconds
Started Jul 25 07:06:06 PM PDT 24
Finished Jul 25 07:06:14 PM PDT 24
Peak memory 207352 kb
Host smart-cebaebdb-2074-4cd6-8414-09f8566c2549
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425578007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_timeout.425578007
Directory /workspace/31.usbdev_device_timeout/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.2475144895
Short name T2118
Test name
Test status
Simulation time 353080880 ps
CPU time 1.3 seconds
Started Jul 25 07:06:05 PM PDT 24
Finished Jul 25 07:06:07 PM PDT 24
Peak memory 207088 kb
Host smart-aad23fef-611b-4c40-bb7a-49c4a299c7c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24751
44895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.2475144895
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.701653825
Short name T786
Test name
Test status
Simulation time 144908597 ps
CPU time 0.82 seconds
Started Jul 25 07:06:05 PM PDT 24
Finished Jul 25 07:06:06 PM PDT 24
Peak memory 207116 kb
Host smart-841d46bc-7bc4-4f5e-89f6-6ab7309db8c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70165
3825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.701653825
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.4084990572
Short name T2630
Test name
Test status
Simulation time 39251322 ps
CPU time 0.74 seconds
Started Jul 25 07:06:02 PM PDT 24
Finished Jul 25 07:06:03 PM PDT 24
Peak memory 207196 kb
Host smart-96931197-3562-45b9-a831-5ad9def95e18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40849
90572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.4084990572
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.4210084537
Short name T2262
Test name
Test status
Simulation time 934241231 ps
CPU time 2.5 seconds
Started Jul 25 07:06:07 PM PDT 24
Finished Jul 25 07:06:09 PM PDT 24
Peak memory 207440 kb
Host smart-b8d75056-9c06-4f72-ab76-2e7d1a26acf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42100
84537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.4210084537
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.1809679541
Short name T1204
Test name
Test status
Simulation time 278931267 ps
CPU time 1.72 seconds
Started Jul 25 07:06:04 PM PDT 24
Finished Jul 25 07:06:06 PM PDT 24
Peak memory 207352 kb
Host smart-1b90ed84-3501-438a-9a4f-85608cc95497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18096
79541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.1809679541
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.749152266
Short name T1525
Test name
Test status
Simulation time 225348578 ps
CPU time 1.21 seconds
Started Jul 25 07:06:08 PM PDT 24
Finished Jul 25 07:06:09 PM PDT 24
Peak memory 215520 kb
Host smart-c34f70ad-ccf5-4ad0-b783-2cd8b25b0381
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=749152266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.749152266
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.2507400054
Short name T1108
Test name
Test status
Simulation time 155252863 ps
CPU time 0.81 seconds
Started Jul 25 07:06:02 PM PDT 24
Finished Jul 25 07:06:03 PM PDT 24
Peak memory 207224 kb
Host smart-d3a68edb-456e-428d-b771-e5b2c7f1912d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25074
00054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.2507400054
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.4239952714
Short name T819
Test name
Test status
Simulation time 176474225 ps
CPU time 0.98 seconds
Started Jul 25 07:06:05 PM PDT 24
Finished Jul 25 07:06:06 PM PDT 24
Peak memory 207128 kb
Host smart-b3905b72-fd6a-425d-98ba-4528d12fe6df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42399
52714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.4239952714
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.1676799425
Short name T1535
Test name
Test status
Simulation time 6740236244 ps
CPU time 68.99 seconds
Started Jul 25 07:06:02 PM PDT 24
Finished Jul 25 07:07:11 PM PDT 24
Peak memory 217204 kb
Host smart-2769e81a-8135-4c90-a151-e18d8f7ed2b8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1676799425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.1676799425
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_iso_retraction.3231597268
Short name T508
Test name
Test status
Simulation time 4994145236 ps
CPU time 54.54 seconds
Started Jul 25 07:06:09 PM PDT 24
Finished Jul 25 07:07:04 PM PDT 24
Peak memory 207336 kb
Host smart-03937367-3aea-48e5-b4cf-b3495f5cc2fe
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3231597268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_iso_retraction.3231597268
Directory /workspace/31.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.3359710055
Short name T2084
Test name
Test status
Simulation time 245557369 ps
CPU time 1.08 seconds
Started Jul 25 07:06:19 PM PDT 24
Finished Jul 25 07:06:20 PM PDT 24
Peak memory 207112 kb
Host smart-dd72f761-929a-4135-919b-0035eabf367d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33597
10055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.3359710055
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.3651004492
Short name T1749
Test name
Test status
Simulation time 23395343835 ps
CPU time 31.13 seconds
Started Jul 25 07:06:09 PM PDT 24
Finished Jul 25 07:06:41 PM PDT 24
Peak memory 207300 kb
Host smart-880baf00-7b65-433a-8712-029468dec843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36510
04492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.3651004492
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.2376919915
Short name T1425
Test name
Test status
Simulation time 3347066138 ps
CPU time 5.86 seconds
Started Jul 25 07:06:12 PM PDT 24
Finished Jul 25 07:06:18 PM PDT 24
Peak memory 207344 kb
Host smart-396c2bc7-e898-4570-9726-76d48535f5fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23769
19915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.2376919915
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.1279589618
Short name T1331
Test name
Test status
Simulation time 9950514712 ps
CPU time 73.45 seconds
Started Jul 25 07:06:09 PM PDT 24
Finished Jul 25 07:07:23 PM PDT 24
Peak memory 217664 kb
Host smart-4f16a8d5-b594-436e-a6c6-534ad3204501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12795
89618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.1279589618
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.127730899
Short name T1255
Test name
Test status
Simulation time 6424645286 ps
CPU time 190.42 seconds
Started Jul 25 07:06:08 PM PDT 24
Finished Jul 25 07:09:19 PM PDT 24
Peak memory 215600 kb
Host smart-5f329611-e19f-4f37-8af5-3c4e451b5699
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=127730899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.127730899
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.3416827020
Short name T1017
Test name
Test status
Simulation time 254543571 ps
CPU time 1.02 seconds
Started Jul 25 07:06:08 PM PDT 24
Finished Jul 25 07:06:09 PM PDT 24
Peak memory 207164 kb
Host smart-ad3d32f8-5a1f-4340-bc4a-bdf80d41d835
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3416827020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.3416827020
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.972665943
Short name T2202
Test name
Test status
Simulation time 190443894 ps
CPU time 1 seconds
Started Jul 25 07:06:07 PM PDT 24
Finished Jul 25 07:06:08 PM PDT 24
Peak memory 207192 kb
Host smart-92dc271c-613f-4b49-9b89-67eedc261a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97266
5943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.972665943
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.113698826
Short name T2786
Test name
Test status
Simulation time 6534763855 ps
CPU time 195.15 seconds
Started Jul 25 07:06:11 PM PDT 24
Finished Jul 25 07:09:26 PM PDT 24
Peak memory 215540 kb
Host smart-c4b9946d-0068-4a8b-bd4b-d6014cf84c0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11369
8826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.113698826
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.3094893021
Short name T1462
Test name
Test status
Simulation time 6531978983 ps
CPU time 194.02 seconds
Started Jul 25 07:06:08 PM PDT 24
Finished Jul 25 07:09:22 PM PDT 24
Peak memory 215536 kb
Host smart-dc179496-12c5-4dde-945c-1929979b6168
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3094893021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.3094893021
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.2574346251
Short name T2189
Test name
Test status
Simulation time 149548969 ps
CPU time 0.88 seconds
Started Jul 25 07:06:11 PM PDT 24
Finished Jul 25 07:06:12 PM PDT 24
Peak memory 207156 kb
Host smart-5e7318fa-a04f-4dfe-8f46-ad92af7673e9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2574346251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.2574346251
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.878068946
Short name T384
Test name
Test status
Simulation time 188301912 ps
CPU time 0.89 seconds
Started Jul 25 07:06:10 PM PDT 24
Finished Jul 25 07:06:11 PM PDT 24
Peak memory 207132 kb
Host smart-175ee4cb-8dfd-451e-9646-712c43ed4c73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87806
8946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.878068946
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.2569610191
Short name T144
Test name
Test status
Simulation time 221528627 ps
CPU time 0.97 seconds
Started Jul 25 07:06:11 PM PDT 24
Finished Jul 25 07:06:12 PM PDT 24
Peak memory 207180 kb
Host smart-bf0c1e8b-fc0e-4269-a20d-439e6a5d9ef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25696
10191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.2569610191
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.1441455318
Short name T682
Test name
Test status
Simulation time 166972315 ps
CPU time 0.87 seconds
Started Jul 25 07:06:09 PM PDT 24
Finished Jul 25 07:06:10 PM PDT 24
Peak memory 207120 kb
Host smart-b3e69376-5ef9-4d5d-b8a1-7c2aa949ca4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14414
55318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.1441455318
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.531630633
Short name T388
Test name
Test status
Simulation time 205580103 ps
CPU time 1.05 seconds
Started Jul 25 07:06:16 PM PDT 24
Finished Jul 25 07:06:18 PM PDT 24
Peak memory 207128 kb
Host smart-26dcfa5b-4c1f-4007-a4dd-9933bf74e198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53163
0633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.531630633
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.2397874132
Short name T1549
Test name
Test status
Simulation time 188341837 ps
CPU time 0.91 seconds
Started Jul 25 07:06:10 PM PDT 24
Finished Jul 25 07:06:11 PM PDT 24
Peak memory 207160 kb
Host smart-13e11e23-0820-457c-b260-0668aaf5e909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23978
74132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.2397874132
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.3859008841
Short name T2589
Test name
Test status
Simulation time 200299625 ps
CPU time 0.97 seconds
Started Jul 25 07:06:16 PM PDT 24
Finished Jul 25 07:06:17 PM PDT 24
Peak memory 207168 kb
Host smart-d047c438-3ff6-4cc5-b8d8-e019153688c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38590
08841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.3859008841
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.589268928
Short name T803
Test name
Test status
Simulation time 244489835 ps
CPU time 1.03 seconds
Started Jul 25 07:06:15 PM PDT 24
Finished Jul 25 07:06:16 PM PDT 24
Peak memory 207116 kb
Host smart-c494d8cb-c70b-4e46-b7d3-de8a1c05a352
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=589268928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.589268928
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.3547433842
Short name T511
Test name
Test status
Simulation time 149584332 ps
CPU time 0.85 seconds
Started Jul 25 07:06:17 PM PDT 24
Finished Jul 25 07:06:18 PM PDT 24
Peak memory 207116 kb
Host smart-a370fa9c-0ce7-470e-919c-ccbdbe69ef68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35474
33842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.3547433842
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.1575076188
Short name T472
Test name
Test status
Simulation time 38129944 ps
CPU time 0.68 seconds
Started Jul 25 07:06:10 PM PDT 24
Finished Jul 25 07:06:10 PM PDT 24
Peak memory 207100 kb
Host smart-b1f69c6b-08c5-4641-82da-8066d26b20a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15750
76188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.1575076188
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.2234597487
Short name T667
Test name
Test status
Simulation time 22310324480 ps
CPU time 56.3 seconds
Started Jul 25 07:06:10 PM PDT 24
Finished Jul 25 07:07:06 PM PDT 24
Peak memory 223880 kb
Host smart-249cded4-f203-49c1-8d4b-8f3c8eeb23b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22345
97487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.2234597487
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.2212458246
Short name T1035
Test name
Test status
Simulation time 164311335 ps
CPU time 0.9 seconds
Started Jul 25 07:06:09 PM PDT 24
Finished Jul 25 07:06:10 PM PDT 24
Peak memory 207108 kb
Host smart-0aace120-227f-4b1a-96f7-79219826256e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22124
58246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.2212458246
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.291481501
Short name T2550
Test name
Test status
Simulation time 226384342 ps
CPU time 0.93 seconds
Started Jul 25 07:06:16 PM PDT 24
Finished Jul 25 07:06:17 PM PDT 24
Peak memory 207124 kb
Host smart-0c47ecc6-5482-4715-a3df-46e5f7483c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29148
1501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.291481501
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.1271232657
Short name T1097
Test name
Test status
Simulation time 200816690 ps
CPU time 0.93 seconds
Started Jul 25 07:06:11 PM PDT 24
Finished Jul 25 07:06:12 PM PDT 24
Peak memory 207216 kb
Host smart-254beeb4-c75c-4678-848b-d4c35ba7a45c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12712
32657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.1271232657
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.3135787312
Short name T2844
Test name
Test status
Simulation time 165889115 ps
CPU time 0.88 seconds
Started Jul 25 07:06:15 PM PDT 24
Finished Jul 25 07:06:16 PM PDT 24
Peak memory 207168 kb
Host smart-349489fb-b51c-4dcd-baa0-73db3931054d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31357
87312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.3135787312
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.3108585839
Short name T239
Test name
Test status
Simulation time 145623632 ps
CPU time 0.8 seconds
Started Jul 25 07:06:11 PM PDT 24
Finished Jul 25 07:06:12 PM PDT 24
Peak memory 207128 kb
Host smart-f99917fd-bfd6-4257-ad92-846e3adeb769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31085
85839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.3108585839
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.797377496
Short name T1747
Test name
Test status
Simulation time 158043849 ps
CPU time 0.87 seconds
Started Jul 25 07:06:11 PM PDT 24
Finished Jul 25 07:06:12 PM PDT 24
Peak memory 207108 kb
Host smart-b012e202-6b41-4ef1-841e-bce1183c98d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79737
7496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.797377496
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.4108846892
Short name T752
Test name
Test status
Simulation time 162435424 ps
CPU time 0.92 seconds
Started Jul 25 07:06:08 PM PDT 24
Finished Jul 25 07:06:09 PM PDT 24
Peak memory 207088 kb
Host smart-d773d9f8-da74-4173-85ac-f714f1e7c44f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41088
46892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.4108846892
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.2729670384
Short name T2746
Test name
Test status
Simulation time 269968957 ps
CPU time 1.13 seconds
Started Jul 25 07:06:11 PM PDT 24
Finished Jul 25 07:06:13 PM PDT 24
Peak memory 207188 kb
Host smart-63f222b3-496e-409c-9e74-4c4cb31ee701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27296
70384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.2729670384
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.4035261511
Short name T2716
Test name
Test status
Simulation time 5547992012 ps
CPU time 58.88 seconds
Started Jul 25 07:06:10 PM PDT 24
Finished Jul 25 07:07:09 PM PDT 24
Peak memory 217148 kb
Host smart-40917440-aeb7-4e90-9382-86eebbbabdd0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4035261511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.4035261511
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.3121049958
Short name T2013
Test name
Test status
Simulation time 186872677 ps
CPU time 0.91 seconds
Started Jul 25 07:06:08 PM PDT 24
Finished Jul 25 07:06:09 PM PDT 24
Peak memory 207180 kb
Host smart-3730db29-bc61-4739-aa92-810f31775726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31210
49958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.3121049958
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.4175837799
Short name T369
Test name
Test status
Simulation time 227709863 ps
CPU time 0.96 seconds
Started Jul 25 07:06:11 PM PDT 24
Finished Jul 25 07:06:12 PM PDT 24
Peak memory 207128 kb
Host smart-653200b1-473b-4c2a-af0d-db87d3a74b0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41758
37799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.4175837799
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.2598546963
Short name T1159
Test name
Test status
Simulation time 875171420 ps
CPU time 2.25 seconds
Started Jul 25 07:06:10 PM PDT 24
Finished Jul 25 07:06:13 PM PDT 24
Peak memory 207276 kb
Host smart-060000ff-e3a7-488e-a5e6-5da071c67ab0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25985
46963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.2598546963
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.3639484506
Short name T1116
Test name
Test status
Simulation time 4634804944 ps
CPU time 134.16 seconds
Started Jul 25 07:06:17 PM PDT 24
Finished Jul 25 07:08:31 PM PDT 24
Peak memory 215624 kb
Host smart-8a02fd64-3e68-4a3a-a78e-3fcc1fadf6ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36394
84506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.3639484506
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_timeout_missing_host_handshake.2380743186
Short name T429
Test name
Test status
Simulation time 4963942182 ps
CPU time 32.75 seconds
Started Jul 25 07:06:04 PM PDT 24
Finished Jul 25 07:06:37 PM PDT 24
Peak memory 207452 kb
Host smart-424db6af-21a9-45b4-a037-ad847e09cfca
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380743186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_timeout_missing_hos
t_handshake.2380743186
Directory /workspace/31.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.885342057
Short name T2714
Test name
Test status
Simulation time 90438891 ps
CPU time 0.72 seconds
Started Jul 25 07:06:22 PM PDT 24
Finished Jul 25 07:06:23 PM PDT 24
Peak memory 206884 kb
Host smart-f409cea9-c3bf-47b3-9c12-cf6af65fcbc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=885342057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.885342057
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.2813853714
Short name T2294
Test name
Test status
Simulation time 4388535132 ps
CPU time 7.26 seconds
Started Jul 25 07:06:19 PM PDT 24
Finished Jul 25 07:06:26 PM PDT 24
Peak memory 207324 kb
Host smart-205aa8ab-f77a-466e-9514-8b7ec3475c64
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813853714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_disconnect.2813853714
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.3773480666
Short name T600
Test name
Test status
Simulation time 13346991197 ps
CPU time 18.91 seconds
Started Jul 25 07:06:09 PM PDT 24
Finished Jul 25 07:06:28 PM PDT 24
Peak memory 207504 kb
Host smart-03041052-26e8-4b3e-bd97-a33e9947c7e7
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773480666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.3773480666
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.1567223053
Short name T1198
Test name
Test status
Simulation time 23546877468 ps
CPU time 28.13 seconds
Started Jul 25 07:06:13 PM PDT 24
Finished Jul 25 07:06:41 PM PDT 24
Peak memory 207220 kb
Host smart-4352f1a4-ede7-47bc-ae57-607962ed838d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567223053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_resume.1567223053
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.3688838147
Short name T1721
Test name
Test status
Simulation time 208300538 ps
CPU time 0.89 seconds
Started Jul 25 07:06:16 PM PDT 24
Finished Jul 25 07:06:17 PM PDT 24
Peak memory 207124 kb
Host smart-140ffbff-6ef1-46d5-a7cd-107243caf39b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36888
38147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.3688838147
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.154041435
Short name T1320
Test name
Test status
Simulation time 227667451 ps
CPU time 0.94 seconds
Started Jul 25 07:06:19 PM PDT 24
Finished Jul 25 07:06:20 PM PDT 24
Peak memory 207076 kb
Host smart-12c29949-2294-4b98-81a5-493ffd1b3268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15404
1435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.154041435
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.1496886615
Short name T788
Test name
Test status
Simulation time 475409225 ps
CPU time 1.55 seconds
Started Jul 25 07:06:09 PM PDT 24
Finished Jul 25 07:06:11 PM PDT 24
Peak memory 207140 kb
Host smart-27ca0ece-68b7-4c94-81d8-9c025ca5676c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14968
86615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.1496886615
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.3036650381
Short name T17
Test name
Test status
Simulation time 818112936 ps
CPU time 2.19 seconds
Started Jul 25 07:06:12 PM PDT 24
Finished Jul 25 07:06:14 PM PDT 24
Peak memory 207292 kb
Host smart-374e2ede-bc64-4684-8ba5-e099668bc321
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3036650381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.3036650381
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_timeout.4062944944
Short name T569
Test name
Test status
Simulation time 2883181310 ps
CPU time 26.71 seconds
Started Jul 25 07:06:16 PM PDT 24
Finished Jul 25 07:06:43 PM PDT 24
Peak memory 207452 kb
Host smart-02d554a1-f051-4e4c-8a5e-ef01c88d2feb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062944944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_timeout.4062944944
Directory /workspace/32.usbdev_device_timeout/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.3629025553
Short name T2390
Test name
Test status
Simulation time 343817618 ps
CPU time 1.28 seconds
Started Jul 25 07:06:10 PM PDT 24
Finished Jul 25 07:06:11 PM PDT 24
Peak memory 207088 kb
Host smart-7ab1085d-3ce2-491f-ace1-abf90cd8cd20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36290
25553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.3629025553
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.3248455389
Short name T2658
Test name
Test status
Simulation time 154762914 ps
CPU time 0.83 seconds
Started Jul 25 07:06:17 PM PDT 24
Finished Jul 25 07:06:18 PM PDT 24
Peak memory 207076 kb
Host smart-2e4f86eb-973f-4962-af20-0af4009a91d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32484
55389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.3248455389
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.3637947659
Short name T2808
Test name
Test status
Simulation time 37113909 ps
CPU time 0.71 seconds
Started Jul 25 07:06:17 PM PDT 24
Finished Jul 25 07:06:17 PM PDT 24
Peak memory 207092 kb
Host smart-f0c87cbe-9123-453d-875a-8c1e2c54b048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36379
47659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.3637947659
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.2708930298
Short name T2471
Test name
Test status
Simulation time 897840334 ps
CPU time 2.41 seconds
Started Jul 25 07:06:09 PM PDT 24
Finished Jul 25 07:06:12 PM PDT 24
Peak memory 207296 kb
Host smart-55f4c5c5-3051-46e9-8244-448a85d63991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27089
30298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.2708930298
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.3593428035
Short name T2164
Test name
Test status
Simulation time 329919690 ps
CPU time 2.39 seconds
Started Jul 25 07:06:12 PM PDT 24
Finished Jul 25 07:06:14 PM PDT 24
Peak memory 207336 kb
Host smart-4387a284-ef3d-4511-a3a1-e84f2b0b784a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35934
28035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.3593428035
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.512673291
Short name T1790
Test name
Test status
Simulation time 163619009 ps
CPU time 0.91 seconds
Started Jul 25 07:06:14 PM PDT 24
Finished Jul 25 07:06:15 PM PDT 24
Peak memory 207172 kb
Host smart-24d79539-efb4-44db-b867-892618787d3c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=512673291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.512673291
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.15592351
Short name T604
Test name
Test status
Simulation time 144307967 ps
CPU time 0.81 seconds
Started Jul 25 07:06:19 PM PDT 24
Finished Jul 25 07:06:20 PM PDT 24
Peak memory 207040 kb
Host smart-a72c53a4-0448-4290-b2a1-fef8d95d9d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15592
351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.15592351
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.3494093002
Short name T548
Test name
Test status
Simulation time 203019492 ps
CPU time 0.95 seconds
Started Jul 25 07:06:14 PM PDT 24
Finished Jul 25 07:06:15 PM PDT 24
Peak memory 207144 kb
Host smart-26289f27-cb46-4fb7-acd5-ec9422b1da9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34940
93002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.3494093002
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_invalid_sync.1586977568
Short name T635
Test name
Test status
Simulation time 6156616211 ps
CPU time 52.65 seconds
Started Jul 25 07:06:09 PM PDT 24
Finished Jul 25 07:07:02 PM PDT 24
Peak memory 216912 kb
Host smart-fd91970a-5844-4019-a578-8eccd7d68fcd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1586977568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.1586977568
Directory /workspace/32.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/32.usbdev_iso_retraction.2889165134
Short name T2371
Test name
Test status
Simulation time 6278195688 ps
CPU time 40.21 seconds
Started Jul 25 07:06:25 PM PDT 24
Finished Jul 25 07:07:05 PM PDT 24
Peak memory 207372 kb
Host smart-976a64d1-20e8-4573-adc2-c6946092d509
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2889165134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.2889165134
Directory /workspace/32.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.1367116370
Short name T2320
Test name
Test status
Simulation time 285912705 ps
CPU time 0.99 seconds
Started Jul 25 07:06:22 PM PDT 24
Finished Jul 25 07:06:23 PM PDT 24
Peak memory 207076 kb
Host smart-78ea74f2-3d28-43d1-b7c7-06047395206e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13671
16370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.1367116370
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.2526655920
Short name T2044
Test name
Test status
Simulation time 23319707045 ps
CPU time 32.32 seconds
Started Jul 25 07:06:22 PM PDT 24
Finished Jul 25 07:06:55 PM PDT 24
Peak memory 207404 kb
Host smart-096a02f7-a501-4777-99dd-ceb076721fcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25266
55920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.2526655920
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.2825984813
Short name T1877
Test name
Test status
Simulation time 3269689034 ps
CPU time 5.01 seconds
Started Jul 25 07:06:22 PM PDT 24
Finished Jul 25 07:06:27 PM PDT 24
Peak memory 207384 kb
Host smart-fe5df48e-4488-4176-9f26-c5f7e0dc21df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28259
84813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.2825984813
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.3008123853
Short name T892
Test name
Test status
Simulation time 8288996888 ps
CPU time 235.36 seconds
Started Jul 25 07:06:22 PM PDT 24
Finished Jul 25 07:10:17 PM PDT 24
Peak memory 215540 kb
Host smart-8cc8739c-a5f3-4156-be12-f9dc785d13f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30081
23853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.3008123853
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.3599354062
Short name T2343
Test name
Test status
Simulation time 4839304827 ps
CPU time 143.15 seconds
Started Jul 25 07:06:21 PM PDT 24
Finished Jul 25 07:08:44 PM PDT 24
Peak memory 215548 kb
Host smart-04254ba0-8bba-4ec0-89d5-4115b2353bfb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3599354062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.3599354062
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.754335223
Short name T2602
Test name
Test status
Simulation time 241074487 ps
CPU time 0.95 seconds
Started Jul 25 07:06:18 PM PDT 24
Finished Jul 25 07:06:19 PM PDT 24
Peak memory 207148 kb
Host smart-5c28d34e-e933-456b-a563-27a0946c2f52
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=754335223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.754335223
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.1000086476
Short name T1622
Test name
Test status
Simulation time 212668858 ps
CPU time 0.98 seconds
Started Jul 25 07:06:19 PM PDT 24
Finished Jul 25 07:06:20 PM PDT 24
Peak memory 207144 kb
Host smart-b8184e26-bff9-4739-83da-013ae0c9c7cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10000
86476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.1000086476
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.516156173
Short name T1142
Test name
Test status
Simulation time 4246390779 ps
CPU time 120.27 seconds
Started Jul 25 07:06:21 PM PDT 24
Finished Jul 25 07:08:22 PM PDT 24
Peak memory 215520 kb
Host smart-cc0c5e94-14e8-4ebf-bc1d-85d0b2a69041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51615
6173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.516156173
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.481693208
Short name T1187
Test name
Test status
Simulation time 3056356048 ps
CPU time 31.99 seconds
Started Jul 25 07:06:20 PM PDT 24
Finished Jul 25 07:06:53 PM PDT 24
Peak memory 216872 kb
Host smart-12afefd1-98e6-4041-ad83-8159ba236d4a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=481693208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.481693208
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.3679556195
Short name T1737
Test name
Test status
Simulation time 185201135 ps
CPU time 0.96 seconds
Started Jul 25 07:06:20 PM PDT 24
Finished Jul 25 07:06:21 PM PDT 24
Peak memory 207148 kb
Host smart-688e2a55-cb19-4db5-88bb-2f071229662b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3679556195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.3679556195
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.306259745
Short name T2180
Test name
Test status
Simulation time 146982761 ps
CPU time 0.83 seconds
Started Jul 25 07:06:19 PM PDT 24
Finished Jul 25 07:06:25 PM PDT 24
Peak memory 207104 kb
Host smart-8b1f0fef-0523-456c-a4ae-4a1375077912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30625
9745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.306259745
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.686425654
Short name T2186
Test name
Test status
Simulation time 163396476 ps
CPU time 0.9 seconds
Started Jul 25 07:06:19 PM PDT 24
Finished Jul 25 07:06:20 PM PDT 24
Peak memory 207160 kb
Host smart-287ffe17-e675-46ce-869c-f6eafd48e2e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68642
5654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.686425654
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.657742031
Short name T2847
Test name
Test status
Simulation time 180391384 ps
CPU time 0.95 seconds
Started Jul 25 07:06:22 PM PDT 24
Finished Jul 25 07:06:23 PM PDT 24
Peak memory 207116 kb
Host smart-53703a9d-7b97-428e-8144-e19d75407c29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65774
2031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.657742031
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.223222513
Short name T1699
Test name
Test status
Simulation time 159533062 ps
CPU time 0.86 seconds
Started Jul 25 07:06:22 PM PDT 24
Finished Jul 25 07:06:23 PM PDT 24
Peak memory 207128 kb
Host smart-69f6295b-32b3-4b75-bc15-9e32d1530159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22322
2513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.223222513
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.4059491013
Short name T779
Test name
Test status
Simulation time 158694186 ps
CPU time 0.9 seconds
Started Jul 25 07:06:21 PM PDT 24
Finished Jul 25 07:06:22 PM PDT 24
Peak memory 207124 kb
Host smart-ca5724fa-fbb5-4f9c-a09d-e763eef38512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40594
91013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.4059491013
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.139750872
Short name T1031
Test name
Test status
Simulation time 143754906 ps
CPU time 0.84 seconds
Started Jul 25 07:06:22 PM PDT 24
Finished Jul 25 07:06:23 PM PDT 24
Peak memory 207116 kb
Host smart-06ee8328-8629-4ffc-a31c-d3d967820f1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13975
0872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.139750872
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.210244316
Short name T1813
Test name
Test status
Simulation time 236567117 ps
CPU time 1.1 seconds
Started Jul 25 07:06:22 PM PDT 24
Finished Jul 25 07:06:23 PM PDT 24
Peak memory 207132 kb
Host smart-a95eed56-3f96-432a-ab49-0d8109dbe9c6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=210244316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.210244316
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.2870116813
Short name T340
Test name
Test status
Simulation time 148026446 ps
CPU time 0.85 seconds
Started Jul 25 07:06:21 PM PDT 24
Finished Jul 25 07:06:22 PM PDT 24
Peak memory 207096 kb
Host smart-5dac3fca-1ffc-47ec-9d0a-a7d2a688e828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28701
16813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.2870116813
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.1814154748
Short name T1058
Test name
Test status
Simulation time 41175120 ps
CPU time 0.72 seconds
Started Jul 25 07:06:19 PM PDT 24
Finished Jul 25 07:06:19 PM PDT 24
Peak memory 207096 kb
Host smart-8d44d83c-b566-4394-ac82-664fdd8d8dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18141
54748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.1814154748
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.1879255220
Short name T1751
Test name
Test status
Simulation time 183386268 ps
CPU time 0.87 seconds
Started Jul 25 07:06:24 PM PDT 24
Finished Jul 25 07:06:25 PM PDT 24
Peak memory 207128 kb
Host smart-deb9050d-81b9-4b3b-960d-d3475c037da8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18792
55220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.1879255220
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.885480908
Short name T554
Test name
Test status
Simulation time 229690788 ps
CPU time 0.93 seconds
Started Jul 25 07:06:21 PM PDT 24
Finished Jul 25 07:06:23 PM PDT 24
Peak memory 207108 kb
Host smart-3f26e891-f795-4828-a204-a8fec56be802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88548
0908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.885480908
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.2854505628
Short name T2195
Test name
Test status
Simulation time 210980771 ps
CPU time 0.94 seconds
Started Jul 25 07:06:21 PM PDT 24
Finished Jul 25 07:06:22 PM PDT 24
Peak memory 207108 kb
Host smart-51a72992-ced0-47d6-a4f3-43b42ad8a284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28545
05628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.2854505628
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.1564320933
Short name T1804
Test name
Test status
Simulation time 188686818 ps
CPU time 0.93 seconds
Started Jul 25 07:06:20 PM PDT 24
Finished Jul 25 07:06:22 PM PDT 24
Peak memory 207112 kb
Host smart-817e521e-6129-4aec-9c16-6f43526efbf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15643
20933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.1564320933
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.1518410351
Short name T893
Test name
Test status
Simulation time 151478452 ps
CPU time 0.87 seconds
Started Jul 25 07:06:18 PM PDT 24
Finished Jul 25 07:06:19 PM PDT 24
Peak memory 207076 kb
Host smart-b146b401-6359-4c62-be29-20b08d63ac07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15184
10351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.1518410351
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.3035440007
Short name T2252
Test name
Test status
Simulation time 157942933 ps
CPU time 0.82 seconds
Started Jul 25 07:06:21 PM PDT 24
Finished Jul 25 07:06:22 PM PDT 24
Peak memory 207128 kb
Host smart-d9c03f78-9e2f-4d4d-b0cc-a46975df0a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30354
40007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.3035440007
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.3409073000
Short name T2313
Test name
Test status
Simulation time 170337042 ps
CPU time 0.87 seconds
Started Jul 25 07:06:25 PM PDT 24
Finished Jul 25 07:06:26 PM PDT 24
Peak memory 207140 kb
Host smart-721e565d-5866-4718-955b-226cb184e03c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34090
73000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.3409073000
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.3316615655
Short name T2048
Test name
Test status
Simulation time 203886413 ps
CPU time 0.99 seconds
Started Jul 25 07:06:22 PM PDT 24
Finished Jul 25 07:06:24 PM PDT 24
Peak memory 207072 kb
Host smart-69a16c9d-445d-4c65-84bf-1d8899c1531b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33166
15655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.3316615655
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.587022009
Short name T2426
Test name
Test status
Simulation time 5853117118 ps
CPU time 167.75 seconds
Started Jul 25 07:09:22 PM PDT 24
Finished Jul 25 07:12:10 PM PDT 24
Peak memory 215568 kb
Host smart-3a15e529-b2b4-4784-bb11-854b8edabc29
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=587022009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.587022009
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.1459273865
Short name T2629
Test name
Test status
Simulation time 170976534 ps
CPU time 0.87 seconds
Started Jul 25 07:06:20 PM PDT 24
Finished Jul 25 07:06:22 PM PDT 24
Peak memory 207144 kb
Host smart-4da30641-c7c9-429c-99c6-bc4c941a3f5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14592
73865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.1459273865
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.175223472
Short name T730
Test name
Test status
Simulation time 172328997 ps
CPU time 0.88 seconds
Started Jul 25 07:06:20 PM PDT 24
Finished Jul 25 07:06:21 PM PDT 24
Peak memory 207116 kb
Host smart-0ff4b40d-b141-4025-9885-348457ef96e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17522
3472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.175223472
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.503599286
Short name T2659
Test name
Test status
Simulation time 224357136 ps
CPU time 0.95 seconds
Started Jul 25 07:06:22 PM PDT 24
Finished Jul 25 07:06:23 PM PDT 24
Peak memory 207104 kb
Host smart-1cb4de4d-5456-48b6-8c92-805e398870f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50359
9286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.503599286
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.3831992152
Short name T2731
Test name
Test status
Simulation time 5137288964 ps
CPU time 50.59 seconds
Started Jul 25 07:06:22 PM PDT 24
Finished Jul 25 07:07:12 PM PDT 24
Peak memory 207336 kb
Host smart-ac03d69d-60c2-4b99-a190-a721f558893b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38319
92152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.3831992152
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_timeout_missing_host_handshake.3416550882
Short name T2214
Test name
Test status
Simulation time 1295102049 ps
CPU time 29.43 seconds
Started Jul 25 07:06:09 PM PDT 24
Finished Jul 25 07:06:38 PM PDT 24
Peak memory 207260 kb
Host smart-bf78e774-ecba-4110-b342-4723bc13c48e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416550882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_timeout_missing_hos
t_handshake.3416550882
Directory /workspace/32.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.2504122898
Short name T2493
Test name
Test status
Simulation time 52723839 ps
CPU time 0.73 seconds
Started Jul 25 07:06:46 PM PDT 24
Finished Jul 25 07:06:46 PM PDT 24
Peak memory 207240 kb
Host smart-96adc1da-4625-4c76-937d-522f5304b6ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2504122898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.2504122898
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.2656530780
Short name T9
Test name
Test status
Simulation time 4135382408 ps
CPU time 6.03 seconds
Started Jul 25 07:06:23 PM PDT 24
Finished Jul 25 07:06:29 PM PDT 24
Peak memory 207384 kb
Host smart-a5ea72eb-1849-4973-97a8-050f9676f53e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656530780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_a
on_wake_disconnect.2656530780
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.1420090502
Short name T1071
Test name
Test status
Simulation time 13422636283 ps
CPU time 15.91 seconds
Started Jul 25 07:06:21 PM PDT 24
Finished Jul 25 07:06:37 PM PDT 24
Peak memory 207400 kb
Host smart-b72d46f5-0011-4184-9049-42a65d1b5ee9
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420090502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.1420090502
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.4231826036
Short name T2336
Test name
Test status
Simulation time 23397920621 ps
CPU time 31.46 seconds
Started Jul 25 07:06:22 PM PDT 24
Finished Jul 25 07:06:54 PM PDT 24
Peak memory 207344 kb
Host smart-e47bca4e-1235-4296-8aae-b5ad910451b9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231826036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_a
on_wake_resume.4231826036
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.29496414
Short name T818
Test name
Test status
Simulation time 164388029 ps
CPU time 0.83 seconds
Started Jul 25 07:06:21 PM PDT 24
Finished Jul 25 07:06:22 PM PDT 24
Peak memory 207056 kb
Host smart-5f9879fa-eca4-4b5a-b9f6-4b9a0afc66d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29496
414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.29496414
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.3947267048
Short name T448
Test name
Test status
Simulation time 182767308 ps
CPU time 0.95 seconds
Started Jul 25 07:06:20 PM PDT 24
Finished Jul 25 07:06:22 PM PDT 24
Peak memory 207084 kb
Host smart-8d40a392-59ad-423c-9ff8-4e9185d2ad4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39472
67048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.3947267048
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.537273269
Short name T2358
Test name
Test status
Simulation time 539887298 ps
CPU time 1.7 seconds
Started Jul 25 07:06:20 PM PDT 24
Finished Jul 25 07:06:21 PM PDT 24
Peak memory 207132 kb
Host smart-2d9a575d-4f41-4303-8e53-793aecf14a39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53727
3269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.537273269
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.2548103990
Short name T640
Test name
Test status
Simulation time 408250433 ps
CPU time 1.34 seconds
Started Jul 25 07:06:25 PM PDT 24
Finished Jul 25 07:06:27 PM PDT 24
Peak memory 207148 kb
Host smart-e6a73853-a525-4ccb-9758-ddc185d0d307
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2548103990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.2548103990
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.747289244
Short name T308
Test name
Test status
Simulation time 13111385489 ps
CPU time 26.8 seconds
Started Jul 25 07:06:21 PM PDT 24
Finished Jul 25 07:06:48 PM PDT 24
Peak memory 207380 kb
Host smart-f75b196e-1fb9-4a3a-8aea-8c0e7e3a09ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74728
9244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.747289244
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_device_timeout.3555449033
Short name T1030
Test name
Test status
Simulation time 3108008730 ps
CPU time 21.88 seconds
Started Jul 25 07:06:22 PM PDT 24
Finished Jul 25 07:06:44 PM PDT 24
Peak memory 207132 kb
Host smart-0ca11174-bc25-41c5-b2a1-3d0cce038a33
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555449033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_timeout.3555449033
Directory /workspace/33.usbdev_device_timeout/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.3603094817
Short name T1025
Test name
Test status
Simulation time 472014139 ps
CPU time 1.52 seconds
Started Jul 25 07:06:22 PM PDT 24
Finished Jul 25 07:06:23 PM PDT 24
Peak memory 207160 kb
Host smart-fff78b3e-79c8-4b5d-b532-ccc238bf3201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36030
94817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.3603094817
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.1067480138
Short name T1878
Test name
Test status
Simulation time 233391183 ps
CPU time 0.99 seconds
Started Jul 25 07:06:21 PM PDT 24
Finished Jul 25 07:06:22 PM PDT 24
Peak memory 207076 kb
Host smart-8ed2ee6d-702c-47c8-ac90-b38d57856c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10674
80138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.1067480138
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.3179420588
Short name T2424
Test name
Test status
Simulation time 56779758 ps
CPU time 0.72 seconds
Started Jul 25 07:06:23 PM PDT 24
Finished Jul 25 07:06:29 PM PDT 24
Peak memory 207092 kb
Host smart-8597c2d7-b2ef-4c2d-81c9-a36e184764bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31794
20588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.3179420588
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.485139283
Short name T336
Test name
Test status
Simulation time 1076550100 ps
CPU time 3.04 seconds
Started Jul 25 07:06:22 PM PDT 24
Finished Jul 25 07:06:25 PM PDT 24
Peak memory 207356 kb
Host smart-3cb4f5f9-8c97-4b0b-a562-5c00e18113be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48513
9283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.485139283
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.1213265365
Short name T2741
Test name
Test status
Simulation time 314195596 ps
CPU time 2.12 seconds
Started Jul 25 07:06:21 PM PDT 24
Finished Jul 25 07:06:23 PM PDT 24
Peak memory 207324 kb
Host smart-88e39745-24fc-45a5-98ba-bf866358d2ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12132
65365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.1213265365
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.2904914265
Short name T2296
Test name
Test status
Simulation time 226282268 ps
CPU time 1.2 seconds
Started Jul 25 07:06:21 PM PDT 24
Finished Jul 25 07:06:23 PM PDT 24
Peak memory 207308 kb
Host smart-991b5047-1159-434e-8c3e-62e1456573df
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2904914265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.2904914265
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.1623825070
Short name T977
Test name
Test status
Simulation time 147633200 ps
CPU time 0.85 seconds
Started Jul 25 07:06:21 PM PDT 24
Finished Jul 25 07:06:22 PM PDT 24
Peak memory 207120 kb
Host smart-0d953469-ae67-4e51-adb8-1985a566c5fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16238
25070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.1623825070
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.191667736
Short name T1165
Test name
Test status
Simulation time 204553176 ps
CPU time 0.92 seconds
Started Jul 25 07:06:21 PM PDT 24
Finished Jul 25 07:06:22 PM PDT 24
Peak memory 207088 kb
Host smart-bfcbc973-da70-4ae2-998b-7d87df22820e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19166
7736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.191667736
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_invalid_sync.3407714975
Short name T894
Test name
Test status
Simulation time 4765641902 ps
CPU time 141.28 seconds
Started Jul 25 07:06:19 PM PDT 24
Finished Jul 25 07:08:40 PM PDT 24
Peak memory 215620 kb
Host smart-e7027840-ed91-4a10-bfb0-3cf51d68af2f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3407714975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.3407714975
Directory /workspace/33.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/33.usbdev_iso_retraction.2963899314
Short name T439
Test name
Test status
Simulation time 8936598115 ps
CPU time 120.48 seconds
Started Jul 25 07:06:22 PM PDT 24
Finished Jul 25 07:08:23 PM PDT 24
Peak memory 207368 kb
Host smart-68e60a32-40fb-4abc-bcd2-be0f79d7e959
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2963899314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.2963899314
Directory /workspace/33.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.591351927
Short name T1696
Test name
Test status
Simulation time 187322056 ps
CPU time 0.87 seconds
Started Jul 25 07:06:20 PM PDT 24
Finished Jul 25 07:06:21 PM PDT 24
Peak memory 207092 kb
Host smart-2073afbf-4f06-42be-a56a-5b7370d1ee1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59135
1927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.591351927
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.652895102
Short name T2560
Test name
Test status
Simulation time 23334651833 ps
CPU time 29.53 seconds
Started Jul 25 07:06:21 PM PDT 24
Finished Jul 25 07:06:51 PM PDT 24
Peak memory 207356 kb
Host smart-93299012-62d1-4eb5-904b-bc7bc3add713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65289
5102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.652895102
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.794296498
Short name T1353
Test name
Test status
Simulation time 3302298894 ps
CPU time 5.75 seconds
Started Jul 25 07:06:21 PM PDT 24
Finished Jul 25 07:06:27 PM PDT 24
Peak memory 207312 kb
Host smart-9f8ee739-4060-4d19-b042-1c258b00f6ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79429
6498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.794296498
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.3678216351
Short name T1452
Test name
Test status
Simulation time 4872987204 ps
CPU time 50.66 seconds
Started Jul 25 07:06:21 PM PDT 24
Finished Jul 25 07:07:12 PM PDT 24
Peak memory 217496 kb
Host smart-f445127a-b7b4-4e5f-b355-1a87c761872e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36782
16351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.3678216351
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.788447942
Short name T2233
Test name
Test status
Simulation time 3890374085 ps
CPU time 114.68 seconds
Started Jul 25 07:06:21 PM PDT 24
Finished Jul 25 07:08:16 PM PDT 24
Peak memory 215636 kb
Host smart-e44f9a6f-0a08-497c-8bc0-d9aa1988a17f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=788447942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.788447942
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.958556655
Short name T466
Test name
Test status
Simulation time 263136720 ps
CPU time 0.98 seconds
Started Jul 25 07:06:22 PM PDT 24
Finished Jul 25 07:06:24 PM PDT 24
Peak memory 207120 kb
Host smart-e0fd2278-0376-455f-be9c-c7f8d80264a6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=958556655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.958556655
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.2639331255
Short name T944
Test name
Test status
Simulation time 195922467 ps
CPU time 0.96 seconds
Started Jul 25 07:06:23 PM PDT 24
Finished Jul 25 07:06:24 PM PDT 24
Peak memory 207144 kb
Host smart-b4e7f182-9302-4d3c-bef5-7e0b8a5d0d4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26393
31255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.2639331255
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.3580266990
Short name T918
Test name
Test status
Simulation time 4835377295 ps
CPU time 135.54 seconds
Started Jul 25 07:06:29 PM PDT 24
Finished Jul 25 07:08:45 PM PDT 24
Peak memory 215532 kb
Host smart-a8255328-b623-4c48-ab36-331da393c730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35802
66990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.3580266990
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.1996646362
Short name T746
Test name
Test status
Simulation time 4922577108 ps
CPU time 51.98 seconds
Started Jul 25 07:06:30 PM PDT 24
Finished Jul 25 07:07:22 PM PDT 24
Peak memory 216744 kb
Host smart-32af3327-346f-4d95-aa38-ef0cde152672
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1996646362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.1996646362
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.1356366809
Short name T626
Test name
Test status
Simulation time 170695797 ps
CPU time 0.83 seconds
Started Jul 25 07:06:31 PM PDT 24
Finished Jul 25 07:06:32 PM PDT 24
Peak memory 207164 kb
Host smart-669e47e9-e4c0-4760-b539-da4c0af0f044
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1356366809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.1356366809
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.2809022981
Short name T1038
Test name
Test status
Simulation time 163266896 ps
CPU time 0.86 seconds
Started Jul 25 07:06:30 PM PDT 24
Finished Jul 25 07:06:31 PM PDT 24
Peak memory 207140 kb
Host smart-c9c9a762-5ee5-4ec9-83f4-fd740783b4cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28090
22981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.2809022981
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.1325998061
Short name T133
Test name
Test status
Simulation time 243329302 ps
CPU time 1 seconds
Started Jul 25 07:06:32 PM PDT 24
Finished Jul 25 07:06:33 PM PDT 24
Peak memory 207120 kb
Host smart-aa75a949-5248-4bd9-9ae2-ee95033045ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13259
98061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.1325998061
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.3576683206
Short name T2058
Test name
Test status
Simulation time 168050963 ps
CPU time 0.89 seconds
Started Jul 25 07:06:31 PM PDT 24
Finished Jul 25 07:06:33 PM PDT 24
Peak memory 207224 kb
Host smart-34a7d3fe-fd9b-496d-a31d-0b0689953ae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35766
83206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.3576683206
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.3102906860
Short name T1942
Test name
Test status
Simulation time 186342190 ps
CPU time 0.95 seconds
Started Jul 25 07:06:39 PM PDT 24
Finished Jul 25 07:06:41 PM PDT 24
Peak memory 207120 kb
Host smart-63085ec6-b0cb-43c9-8edf-dd6e77ac817b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31029
06860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.3102906860
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.176556435
Short name T2240
Test name
Test status
Simulation time 165786664 ps
CPU time 0.86 seconds
Started Jul 25 07:06:33 PM PDT 24
Finished Jul 25 07:06:34 PM PDT 24
Peak memory 207140 kb
Host smart-61c1667b-ff1d-4087-b389-df7a7f3b8cd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17655
6435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.176556435
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.3702859202
Short name T1983
Test name
Test status
Simulation time 213232582 ps
CPU time 0.94 seconds
Started Jul 25 07:06:32 PM PDT 24
Finished Jul 25 07:06:33 PM PDT 24
Peak memory 207076 kb
Host smart-948a953d-e3e1-41e4-bbb8-90092eac72a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37028
59202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.3702859202
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.4140297924
Short name T599
Test name
Test status
Simulation time 216992986 ps
CPU time 1.01 seconds
Started Jul 25 07:06:31 PM PDT 24
Finished Jul 25 07:06:32 PM PDT 24
Peak memory 207132 kb
Host smart-abf17867-ffed-4c34-9305-46f04e6a239f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4140297924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.4140297924
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.3270991280
Short name T603
Test name
Test status
Simulation time 145435344 ps
CPU time 0.84 seconds
Started Jul 25 07:06:30 PM PDT 24
Finished Jul 25 07:06:31 PM PDT 24
Peak memory 207120 kb
Host smart-b207e003-b638-4231-a341-d86090bce028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32709
91280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.3270991280
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.66996702
Short name T792
Test name
Test status
Simulation time 74301748 ps
CPU time 0.72 seconds
Started Jul 25 07:06:30 PM PDT 24
Finished Jul 25 07:06:31 PM PDT 24
Peak memory 207196 kb
Host smart-e090de09-7f27-4af4-b6bb-c1fbf7a709db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66996
702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.66996702
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.526751136
Short name T2467
Test name
Test status
Simulation time 6595800723 ps
CPU time 16.76 seconds
Started Jul 25 07:06:30 PM PDT 24
Finished Jul 25 07:06:47 PM PDT 24
Peak memory 215480 kb
Host smart-81fc3b3a-2b77-4f37-a272-d4d35186acbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52675
1136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.526751136
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.1691334581
Short name T1363
Test name
Test status
Simulation time 196918900 ps
CPU time 0.97 seconds
Started Jul 25 07:06:47 PM PDT 24
Finished Jul 25 07:06:48 PM PDT 24
Peak memory 207112 kb
Host smart-65bb6c30-2e55-45d1-bd58-c6f6e19aa135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16913
34581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.1691334581
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.2866845192
Short name T2230
Test name
Test status
Simulation time 191136311 ps
CPU time 0.88 seconds
Started Jul 25 07:06:31 PM PDT 24
Finished Jul 25 07:06:32 PM PDT 24
Peak memory 207076 kb
Host smart-bb5dcf0d-879c-4d37-b876-f96be806025c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28668
45192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.2866845192
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.439247761
Short name T1746
Test name
Test status
Simulation time 232213798 ps
CPU time 0.98 seconds
Started Jul 25 07:06:37 PM PDT 24
Finished Jul 25 07:06:38 PM PDT 24
Peak memory 207068 kb
Host smart-bdb908fd-b8aa-4b3e-99ba-5807917fe9c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43924
7761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.439247761
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.3711954099
Short name T1154
Test name
Test status
Simulation time 187284650 ps
CPU time 0.91 seconds
Started Jul 25 07:06:35 PM PDT 24
Finished Jul 25 07:06:36 PM PDT 24
Peak memory 207072 kb
Host smart-e8083d03-fa76-46c8-88a2-82a5684eabc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37119
54099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.3711954099
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.1856161834
Short name T437
Test name
Test status
Simulation time 145499434 ps
CPU time 0.89 seconds
Started Jul 25 07:06:29 PM PDT 24
Finished Jul 25 07:06:30 PM PDT 24
Peak memory 207112 kb
Host smart-eed4cf07-9cd1-469e-a174-1ac38fffe4fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18561
61834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.1856161834
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.2659028160
Short name T102
Test name
Test status
Simulation time 169802121 ps
CPU time 0.92 seconds
Started Jul 25 07:06:34 PM PDT 24
Finished Jul 25 07:06:35 PM PDT 24
Peak memory 207092 kb
Host smart-3cc882f8-f17d-47b7-a754-f0d79b60c72e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26590
28160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.2659028160
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.613615801
Short name T2805
Test name
Test status
Simulation time 172214812 ps
CPU time 0.83 seconds
Started Jul 25 07:06:29 PM PDT 24
Finished Jul 25 07:06:30 PM PDT 24
Peak memory 207124 kb
Host smart-86aefb6a-f583-4beb-90a7-4ed6f484f3ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61361
5801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.613615801
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.2124513298
Short name T2169
Test name
Test status
Simulation time 216235625 ps
CPU time 1.06 seconds
Started Jul 25 07:06:45 PM PDT 24
Finished Jul 25 07:06:46 PM PDT 24
Peak memory 207124 kb
Host smart-40d915a3-9eb8-4f46-9bda-a70417b3974e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21245
13298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.2124513298
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.3854994861
Short name T1015
Test name
Test status
Simulation time 5333645294 ps
CPU time 39.78 seconds
Started Jul 25 07:06:33 PM PDT 24
Finished Jul 25 07:07:13 PM PDT 24
Peak memory 215620 kb
Host smart-48f0d7ee-7914-49d4-b057-af1dc1142dc5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3854994861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.3854994861
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.931478292
Short name T802
Test name
Test status
Simulation time 176879129 ps
CPU time 0.91 seconds
Started Jul 25 07:06:30 PM PDT 24
Finished Jul 25 07:06:31 PM PDT 24
Peak memory 207152 kb
Host smart-75c32b8f-cc96-4127-b876-a4022411d248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93147
8292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.931478292
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.1671041993
Short name T1412
Test name
Test status
Simulation time 151402407 ps
CPU time 0.84 seconds
Started Jul 25 07:06:32 PM PDT 24
Finished Jul 25 07:06:33 PM PDT 24
Peak memory 207076 kb
Host smart-87b4d346-5910-4c5c-8a99-e31dd0e5c6c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16710
41993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.1671041993
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.1665166704
Short name T2184
Test name
Test status
Simulation time 827495808 ps
CPU time 2.24 seconds
Started Jul 25 07:06:33 PM PDT 24
Finished Jul 25 07:06:35 PM PDT 24
Peak memory 207320 kb
Host smart-725277df-bcb5-40f4-bca5-87b8dde2ac95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16651
66704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.1665166704
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.3895425663
Short name T1735
Test name
Test status
Simulation time 4677036403 ps
CPU time 48.64 seconds
Started Jul 25 07:06:31 PM PDT 24
Finished Jul 25 07:07:20 PM PDT 24
Peak memory 216880 kb
Host smart-f5d6cc77-3bad-472f-ab03-5d170b01b65e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38954
25663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.3895425663
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_timeout_missing_host_handshake.2449862968
Short name T916
Test name
Test status
Simulation time 5042739142 ps
CPU time 32.33 seconds
Started Jul 25 07:06:19 PM PDT 24
Finished Jul 25 07:06:56 PM PDT 24
Peak memory 207356 kb
Host smart-f4f0d807-b91f-4c5e-a625-c3a4df18af2d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449862968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_timeout_missing_hos
t_handshake.2449862968
Directory /workspace/33.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.1575157410
Short name T2685
Test name
Test status
Simulation time 52280702 ps
CPU time 0.72 seconds
Started Jul 25 07:06:49 PM PDT 24
Finished Jul 25 07:06:50 PM PDT 24
Peak memory 207160 kb
Host smart-0912eb07-eee8-48f9-bb27-fb3940334f23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1575157410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.1575157410
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.3560759355
Short name T2229
Test name
Test status
Simulation time 3843422776 ps
CPU time 5.52 seconds
Started Jul 25 07:06:34 PM PDT 24
Finished Jul 25 07:06:39 PM PDT 24
Peak memory 207384 kb
Host smart-812db165-2ae2-487d-a37d-259214611aa9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560759355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_a
on_wake_disconnect.3560759355
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.3949766369
Short name T1512
Test name
Test status
Simulation time 13374093255 ps
CPU time 15.07 seconds
Started Jul 25 07:06:29 PM PDT 24
Finished Jul 25 07:06:44 PM PDT 24
Peak memory 207400 kb
Host smart-fcc4080b-f6bc-42b8-8393-58b130cf82f2
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949766369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.3949766369
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.1442659387
Short name T1446
Test name
Test status
Simulation time 23400696702 ps
CPU time 28.1 seconds
Started Jul 25 07:06:33 PM PDT 24
Finished Jul 25 07:07:01 PM PDT 24
Peak memory 207368 kb
Host smart-46f0a89e-6174-4b26-8935-c60f29437a02
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442659387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_a
on_wake_resume.1442659387
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.3762327046
Short name T835
Test name
Test status
Simulation time 157997744 ps
CPU time 0.94 seconds
Started Jul 25 07:06:29 PM PDT 24
Finished Jul 25 07:06:30 PM PDT 24
Peak memory 207168 kb
Host smart-9bc6e819-2ab9-4902-9936-7f4354515715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37623
27046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.3762327046
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.2420416688
Short name T82
Test name
Test status
Simulation time 156387099 ps
CPU time 0.85 seconds
Started Jul 25 07:06:30 PM PDT 24
Finished Jul 25 07:06:31 PM PDT 24
Peak memory 207080 kb
Host smart-980083a9-24cc-4ad3-9167-dad7ae35b23a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24204
16688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.2420416688
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.523547953
Short name T2241
Test name
Test status
Simulation time 292231326 ps
CPU time 1.18 seconds
Started Jul 25 07:06:31 PM PDT 24
Finished Jul 25 07:06:32 PM PDT 24
Peak memory 207120 kb
Host smart-c977abb8-1fbb-4615-8ef5-9c4ca7e239c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52354
7953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.523547953
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.1655929956
Short name T670
Test name
Test status
Simulation time 337471003 ps
CPU time 1.11 seconds
Started Jul 25 07:06:38 PM PDT 24
Finished Jul 25 07:06:39 PM PDT 24
Peak memory 207124 kb
Host smart-8fb89cc5-3026-4cb2-ab17-f1006768555f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1655929956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.1655929956
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.1418997503
Short name T2679
Test name
Test status
Simulation time 13108887890 ps
CPU time 30.31 seconds
Started Jul 25 07:06:35 PM PDT 24
Finished Jul 25 07:07:05 PM PDT 24
Peak memory 207340 kb
Host smart-7db70ffc-87f8-4e32-8160-74c50148ece5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14189
97503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.1418997503
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_device_timeout.1612690341
Short name T824
Test name
Test status
Simulation time 2488668433 ps
CPU time 21.44 seconds
Started Jul 25 07:06:31 PM PDT 24
Finished Jul 25 07:06:53 PM PDT 24
Peak memory 207332 kb
Host smart-3d4e2247-f83b-40b0-9b27-326c5df05294
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612690341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_timeout.1612690341
Directory /workspace/34.usbdev_device_timeout/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.2427973203
Short name T301
Test name
Test status
Simulation time 494119246 ps
CPU time 1.58 seconds
Started Jul 25 07:06:34 PM PDT 24
Finished Jul 25 07:06:35 PM PDT 24
Peak memory 207092 kb
Host smart-9c3877ca-c7c5-477d-b049-285012f82577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24279
73203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.2427973203
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.3215650565
Short name T2591
Test name
Test status
Simulation time 171336227 ps
CPU time 0.79 seconds
Started Jul 25 07:06:30 PM PDT 24
Finished Jul 25 07:06:31 PM PDT 24
Peak memory 206932 kb
Host smart-fa32e767-e0ff-48c2-b356-e188dd6ac2de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32156
50565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.3215650565
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.1458813450
Short name T1460
Test name
Test status
Simulation time 60321875 ps
CPU time 0.74 seconds
Started Jul 25 07:06:36 PM PDT 24
Finished Jul 25 07:06:37 PM PDT 24
Peak memory 207072 kb
Host smart-8426856b-6494-46fe-a097-d6b0a7ca1a73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14588
13450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.1458813450
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.4194081273
Short name T1600
Test name
Test status
Simulation time 712977877 ps
CPU time 2.12 seconds
Started Jul 25 07:06:32 PM PDT 24
Finished Jul 25 07:06:34 PM PDT 24
Peak memory 207328 kb
Host smart-af3b87fc-6d69-48e0-b0df-9a54f5ad0f61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41940
81273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.4194081273
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.969447332
Short name T764
Test name
Test status
Simulation time 253835421 ps
CPU time 1.37 seconds
Started Jul 25 07:06:31 PM PDT 24
Finished Jul 25 07:06:32 PM PDT 24
Peak memory 207320 kb
Host smart-e65ea8df-6cea-442e-b0e3-a10bbc18c43b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96944
7332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.969447332
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.18080604
Short name T1711
Test name
Test status
Simulation time 157131076 ps
CPU time 0.91 seconds
Started Jul 25 07:06:32 PM PDT 24
Finished Jul 25 07:06:33 PM PDT 24
Peak memory 207128 kb
Host smart-afb5bd43-8dac-42da-8db5-c5af8c1a4d32
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=18080604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.18080604
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.299346917
Short name T1562
Test name
Test status
Simulation time 146831500 ps
CPU time 0.8 seconds
Started Jul 25 07:06:39 PM PDT 24
Finished Jul 25 07:06:40 PM PDT 24
Peak memory 207080 kb
Host smart-12f89eb2-370e-436d-ae7b-467526563f0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29934
6917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.299346917
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.166981754
Short name T2250
Test name
Test status
Simulation time 179250422 ps
CPU time 0.88 seconds
Started Jul 25 07:06:52 PM PDT 24
Finished Jul 25 07:06:53 PM PDT 24
Peak memory 207164 kb
Host smart-1751a56d-156d-4cd8-b5a5-27acd25408e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16698
1754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.166981754
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.3938823630
Short name T723
Test name
Test status
Simulation time 9548463301 ps
CPU time 70.39 seconds
Started Jul 25 07:06:32 PM PDT 24
Finished Jul 25 07:07:43 PM PDT 24
Peak memory 207332 kb
Host smart-d0965be8-4b30-4fda-accf-9d7d88bb05c8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3938823630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.3938823630
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.917787918
Short name T586
Test name
Test status
Simulation time 245194081 ps
CPU time 0.98 seconds
Started Jul 25 07:06:32 PM PDT 24
Finished Jul 25 07:06:33 PM PDT 24
Peak memory 207044 kb
Host smart-4e06d08d-a488-4956-887b-12622551e873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91778
7918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.917787918
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.371772746
Short name T2654
Test name
Test status
Simulation time 23295393619 ps
CPU time 29.75 seconds
Started Jul 25 07:06:45 PM PDT 24
Finished Jul 25 07:07:15 PM PDT 24
Peak memory 207368 kb
Host smart-0a8eeb5c-536f-47cb-b1f4-fee55b50c55d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37177
2746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.371772746
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.3399169530
Short name T806
Test name
Test status
Simulation time 3307262800 ps
CPU time 5.1 seconds
Started Jul 25 07:06:31 PM PDT 24
Finished Jul 25 07:06:36 PM PDT 24
Peak memory 207364 kb
Host smart-be66afdc-3ede-4723-ad23-21f90e7741ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33991
69530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.3399169530
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.3475460954
Short name T959
Test name
Test status
Simulation time 7101279789 ps
CPU time 73.09 seconds
Started Jul 25 07:06:31 PM PDT 24
Finished Jul 25 07:07:45 PM PDT 24
Peak memory 217684 kb
Host smart-12fe42a4-2bda-47b8-bbe3-37c045228ade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34754
60954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.3475460954
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.1670455
Short name T1598
Test name
Test status
Simulation time 3801148587 ps
CPU time 37.92 seconds
Started Jul 25 07:06:33 PM PDT 24
Finished Jul 25 07:07:11 PM PDT 24
Peak memory 216852 kb
Host smart-c8031c0c-44f7-41f1-ae96-5b6d4b75dddf
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1670455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.1670455
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.2297616701
Short name T2319
Test name
Test status
Simulation time 273825455 ps
CPU time 1.09 seconds
Started Jul 25 07:06:32 PM PDT 24
Finished Jul 25 07:06:33 PM PDT 24
Peak memory 207148 kb
Host smart-ec17c336-aee0-4f7b-b438-b497fff8028b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2297616701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.2297616701
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.1552655834
Short name T1841
Test name
Test status
Simulation time 223600682 ps
CPU time 0.95 seconds
Started Jul 25 07:06:35 PM PDT 24
Finished Jul 25 07:06:36 PM PDT 24
Peak memory 207064 kb
Host smart-e92e7374-a7ad-41bd-9a61-036b9a9586ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15526
55834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.1552655834
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.3901849716
Short name T168
Test name
Test status
Simulation time 4621564681 ps
CPU time 46.73 seconds
Started Jul 25 07:06:28 PM PDT 24
Finished Jul 25 07:07:14 PM PDT 24
Peak memory 215568 kb
Host smart-a6958024-4a68-413d-b28d-8a14cb8a844d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39018
49716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.3901849716
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.2765123399
Short name T2108
Test name
Test status
Simulation time 4470067008 ps
CPU time 45.25 seconds
Started Jul 25 07:06:32 PM PDT 24
Finished Jul 25 07:07:17 PM PDT 24
Peak memory 207336 kb
Host smart-f0c6bfe7-62a1-4cfd-bcc9-f8d6199d85c6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2765123399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.2765123399
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.425126309
Short name T1591
Test name
Test status
Simulation time 194906357 ps
CPU time 0.87 seconds
Started Jul 25 07:06:33 PM PDT 24
Finished Jul 25 07:06:34 PM PDT 24
Peak memory 207116 kb
Host smart-a0de1713-f823-424e-b481-4595290c7614
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=425126309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.425126309
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.428872258
Short name T2807
Test name
Test status
Simulation time 157235732 ps
CPU time 0.86 seconds
Started Jul 25 07:06:31 PM PDT 24
Finished Jul 25 07:06:33 PM PDT 24
Peak memory 207228 kb
Host smart-06c38394-02f1-4e3d-b11f-8296309e7cbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42887
2258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.428872258
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.2830837976
Short name T712
Test name
Test status
Simulation time 154867982 ps
CPU time 0.85 seconds
Started Jul 25 07:06:45 PM PDT 24
Finished Jul 25 07:06:46 PM PDT 24
Peak memory 207120 kb
Host smart-c1c04cc8-eaf3-4786-bd89-552a9b6733bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28308
37976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.2830837976
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.323839974
Short name T2764
Test name
Test status
Simulation time 171268140 ps
CPU time 0.86 seconds
Started Jul 25 07:06:48 PM PDT 24
Finished Jul 25 07:06:49 PM PDT 24
Peak memory 207120 kb
Host smart-51a28b5b-f73f-418a-92e2-a5f2b2291560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32383
9974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.323839974
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.2018686420
Short name T1832
Test name
Test status
Simulation time 240591725 ps
CPU time 1 seconds
Started Jul 25 07:06:52 PM PDT 24
Finished Jul 25 07:06:53 PM PDT 24
Peak memory 207160 kb
Host smart-9314ae76-8dd2-409f-90fa-f04800611830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20186
86420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.2018686420
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.1996637920
Short name T1532
Test name
Test status
Simulation time 150508652 ps
CPU time 0.88 seconds
Started Jul 25 07:06:49 PM PDT 24
Finished Jul 25 07:06:50 PM PDT 24
Peak memory 207116 kb
Host smart-ad0a182b-6b9f-4c3a-a203-2657a88cf0ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19966
37920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.1996637920
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.1992030083
Short name T996
Test name
Test status
Simulation time 250320144 ps
CPU time 1.11 seconds
Started Jul 25 07:06:55 PM PDT 24
Finished Jul 25 07:06:56 PM PDT 24
Peak memory 207076 kb
Host smart-1e56923c-892d-4397-a9f4-81bb469f4a17
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1992030083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.1992030083
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.2627737785
Short name T1836
Test name
Test status
Simulation time 150177491 ps
CPU time 0.86 seconds
Started Jul 25 07:06:44 PM PDT 24
Finished Jul 25 07:06:45 PM PDT 24
Peak memory 207088 kb
Host smart-fa9ae389-e817-422c-a644-0d35ace154c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26277
37785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.2627737785
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.2124005545
Short name T1593
Test name
Test status
Simulation time 12671253549 ps
CPU time 35.27 seconds
Started Jul 25 07:06:49 PM PDT 24
Finished Jul 25 07:07:25 PM PDT 24
Peak memory 223732 kb
Host smart-0cf13d51-9261-4b00-8f5c-968187df4f5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21240
05545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.2124005545
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.850643483
Short name T328
Test name
Test status
Simulation time 189094135 ps
CPU time 0.92 seconds
Started Jul 25 07:06:51 PM PDT 24
Finished Jul 25 07:06:52 PM PDT 24
Peak memory 207120 kb
Host smart-b9242456-bb89-4791-afe0-8d208e1c2a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85064
3483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.850643483
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.2579555657
Short name T2210
Test name
Test status
Simulation time 208280533 ps
CPU time 0.99 seconds
Started Jul 25 07:06:50 PM PDT 24
Finished Jul 25 07:06:51 PM PDT 24
Peak memory 207104 kb
Host smart-a0760ce7-593f-4fa3-832b-1f1fd26dc38b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25795
55657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.2579555657
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.3863965327
Short name T2068
Test name
Test status
Simulation time 178020189 ps
CPU time 0.94 seconds
Started Jul 25 07:06:46 PM PDT 24
Finished Jul 25 07:06:48 PM PDT 24
Peak memory 207144 kb
Host smart-98c8f759-a753-4782-8d17-bd02ccede47b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38639
65327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.3863965327
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.1656135535
Short name T2826
Test name
Test status
Simulation time 193521395 ps
CPU time 0.92 seconds
Started Jul 25 07:06:44 PM PDT 24
Finished Jul 25 07:06:45 PM PDT 24
Peak memory 207140 kb
Host smart-afccb21d-4a4f-4681-b93d-df2832904945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16561
35535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.1656135535
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.3780765451
Short name T863
Test name
Test status
Simulation time 136335200 ps
CPU time 0.8 seconds
Started Jul 25 07:06:52 PM PDT 24
Finished Jul 25 07:06:53 PM PDT 24
Peak memory 207084 kb
Host smart-bc4dc2b4-a111-43bc-9b16-3c155643253e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37807
65451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.3780765451
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.454746506
Short name T739
Test name
Test status
Simulation time 160116441 ps
CPU time 0.86 seconds
Started Jul 25 07:06:47 PM PDT 24
Finished Jul 25 07:06:48 PM PDT 24
Peak memory 207108 kb
Host smart-4c931103-b8ba-4800-9131-ba62a84a168e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45474
6506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.454746506
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.1123331497
Short name T726
Test name
Test status
Simulation time 160771702 ps
CPU time 0.89 seconds
Started Jul 25 07:06:51 PM PDT 24
Finished Jul 25 07:06:52 PM PDT 24
Peak memory 207132 kb
Host smart-12b2e9dc-a61a-4a36-84bb-97ce3fd69a06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11233
31497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.1123331497
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.3021176662
Short name T2651
Test name
Test status
Simulation time 261924375 ps
CPU time 1.09 seconds
Started Jul 25 07:06:50 PM PDT 24
Finished Jul 25 07:06:51 PM PDT 24
Peak memory 207068 kb
Host smart-68557f7d-d4a4-47b2-882f-d7b184de3b8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30211
76662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.3021176662
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.2881927154
Short name T965
Test name
Test status
Simulation time 4933521179 ps
CPU time 50 seconds
Started Jul 25 07:06:55 PM PDT 24
Finished Jul 25 07:07:45 PM PDT 24
Peak memory 215544 kb
Host smart-cda9cba9-04cc-47f7-b3b7-ef701e11b420
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2881927154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.2881927154
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.1651532440
Short name T874
Test name
Test status
Simulation time 176019903 ps
CPU time 0.84 seconds
Started Jul 25 07:06:47 PM PDT 24
Finished Jul 25 07:06:48 PM PDT 24
Peak memory 207176 kb
Host smart-f6cc907d-e752-4068-99d8-25dc3e8960c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16515
32440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.1651532440
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.1849175843
Short name T2146
Test name
Test status
Simulation time 159497493 ps
CPU time 0.86 seconds
Started Jul 25 07:06:53 PM PDT 24
Finished Jul 25 07:06:54 PM PDT 24
Peak memory 207112 kb
Host smart-f4b9146a-026d-48e6-96d1-1ab697adf8fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18491
75843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.1849175843
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.638916246
Short name T1956
Test name
Test status
Simulation time 1130491965 ps
CPU time 2.64 seconds
Started Jul 25 07:06:46 PM PDT 24
Finished Jul 25 07:06:49 PM PDT 24
Peak memory 207300 kb
Host smart-5e9fb6e4-16e3-41bd-b1af-9a26252d6ccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63891
6246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.638916246
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.3096921601
Short name T661
Test name
Test status
Simulation time 5858634716 ps
CPU time 165.95 seconds
Started Jul 25 07:06:46 PM PDT 24
Finished Jul 25 07:09:32 PM PDT 24
Peak memory 215596 kb
Host smart-bf253544-ec59-488a-b87b-acb9b546f5c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30969
21601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.3096921601
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_timeout_missing_host_handshake.35486812
Short name T2846
Test name
Test status
Simulation time 5641786001 ps
CPU time 38.79 seconds
Started Jul 25 07:06:33 PM PDT 24
Finished Jul 25 07:07:12 PM PDT 24
Peak memory 207432 kb
Host smart-35fd36fa-e4ef-40b4-9bf2-1be764e4374b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35486812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_timeout_missing_host_
handshake.35486812
Directory /workspace/34.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.1924507629
Short name T2174
Test name
Test status
Simulation time 44027163 ps
CPU time 0.69 seconds
Started Jul 25 07:07:03 PM PDT 24
Finished Jul 25 07:07:03 PM PDT 24
Peak memory 207156 kb
Host smart-79bc2305-a965-4888-a438-6c945051127d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1924507629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.1924507629
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.2893067468
Short name T2086
Test name
Test status
Simulation time 3867850878 ps
CPU time 5.71 seconds
Started Jul 25 07:06:54 PM PDT 24
Finished Jul 25 07:07:00 PM PDT 24
Peak memory 207320 kb
Host smart-05c3c983-8180-40aa-9ca0-c2a68f44d62e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893067468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_a
on_wake_disconnect.2893067468
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.3227994497
Short name T2438
Test name
Test status
Simulation time 23508119191 ps
CPU time 28.14 seconds
Started Jul 25 07:06:48 PM PDT 24
Finished Jul 25 07:07:16 PM PDT 24
Peak memory 207400 kb
Host smart-00b2f25d-2e6c-4e8c-8c4a-34e230bd46c5
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227994497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_a
on_wake_resume.3227994497
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.1571551905
Short name T2581
Test name
Test status
Simulation time 164221654 ps
CPU time 0.87 seconds
Started Jul 25 07:06:49 PM PDT 24
Finished Jul 25 07:06:50 PM PDT 24
Peak memory 207108 kb
Host smart-b5bc2767-c306-40c6-92a5-341850d4a7d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15715
51905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.1571551905
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.959156416
Short name T572
Test name
Test status
Simulation time 139969582 ps
CPU time 0.86 seconds
Started Jul 25 07:06:46 PM PDT 24
Finished Jul 25 07:06:47 PM PDT 24
Peak memory 206912 kb
Host smart-c36a5dd6-cee0-4969-93e5-e0c6054c48fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95915
6416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.959156416
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.3909174296
Short name T1887
Test name
Test status
Simulation time 497260138 ps
CPU time 1.78 seconds
Started Jul 25 07:06:43 PM PDT 24
Finished Jul 25 07:06:45 PM PDT 24
Peak memory 207136 kb
Host smart-15e0de66-f7a7-4d31-ac8a-7ffccf5ab4c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39091
74296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.3909174296
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.962128796
Short name T605
Test name
Test status
Simulation time 333511777 ps
CPU time 1.12 seconds
Started Jul 25 07:06:46 PM PDT 24
Finished Jul 25 07:06:48 PM PDT 24
Peak memory 207072 kb
Host smart-4b454d81-92df-4dff-97a9-67e5ae6dae95
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=962128796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.962128796
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.3653557693
Short name T2758
Test name
Test status
Simulation time 18032794012 ps
CPU time 36.84 seconds
Started Jul 25 07:06:50 PM PDT 24
Finished Jul 25 07:07:27 PM PDT 24
Peak memory 207292 kb
Host smart-6433f44d-36a0-4030-b461-2d2031180fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36535
57693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.3653557693
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_device_timeout.3210668196
Short name T1099
Test name
Test status
Simulation time 1585671887 ps
CPU time 14.09 seconds
Started Jul 25 07:06:46 PM PDT 24
Finished Jul 25 07:07:00 PM PDT 24
Peak memory 207084 kb
Host smart-8bc990d3-5b1f-49cb-a66e-e7e902dd7ce7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210668196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_timeout.3210668196
Directory /workspace/35.usbdev_device_timeout/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.2934846462
Short name T1650
Test name
Test status
Simulation time 438110949 ps
CPU time 1.42 seconds
Started Jul 25 07:06:51 PM PDT 24
Finished Jul 25 07:06:53 PM PDT 24
Peak memory 207044 kb
Host smart-28f1d291-290c-40df-a04a-109efdf44872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29348
46462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.2934846462
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.3018304577
Short name T1660
Test name
Test status
Simulation time 167927168 ps
CPU time 0.88 seconds
Started Jul 25 07:06:47 PM PDT 24
Finished Jul 25 07:06:48 PM PDT 24
Peak memory 207044 kb
Host smart-a52a94e1-2766-4b5e-a21c-3389fd305ed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30183
04577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.3018304577
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.1660274287
Short name T1014
Test name
Test status
Simulation time 64884827 ps
CPU time 0.73 seconds
Started Jul 25 07:06:47 PM PDT 24
Finished Jul 25 07:06:48 PM PDT 24
Peak memory 207152 kb
Host smart-6da86e26-2320-4e86-bd59-f908756bb6ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16602
74287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.1660274287
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.2676246110
Short name T782
Test name
Test status
Simulation time 955604826 ps
CPU time 2.29 seconds
Started Jul 25 07:06:47 PM PDT 24
Finished Jul 25 07:06:50 PM PDT 24
Peak memory 207392 kb
Host smart-5b95d895-a25c-47f6-a717-f4d5ede9e9cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26762
46110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.2676246110
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.3317490375
Short name T2587
Test name
Test status
Simulation time 377181766 ps
CPU time 2.7 seconds
Started Jul 25 07:06:47 PM PDT 24
Finished Jul 25 07:06:50 PM PDT 24
Peak memory 207284 kb
Host smart-7949317a-27fc-4fb1-ae18-f747d1163a15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33174
90375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.3317490375
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.2639557056
Short name T486
Test name
Test status
Simulation time 211118881 ps
CPU time 1.12 seconds
Started Jul 25 07:06:44 PM PDT 24
Finished Jul 25 07:06:45 PM PDT 24
Peak memory 207368 kb
Host smart-214f9689-489c-4f14-857c-3a06e9abccb8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2639557056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.2639557056
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.2129768526
Short name T1273
Test name
Test status
Simulation time 196229630 ps
CPU time 0.9 seconds
Started Jul 25 07:06:49 PM PDT 24
Finished Jul 25 07:06:51 PM PDT 24
Peak memory 207112 kb
Host smart-8d06632f-cd39-4bcc-b285-0ae07e5645ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21297
68526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.2129768526
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.1296351360
Short name T1084
Test name
Test status
Simulation time 196843795 ps
CPU time 0.99 seconds
Started Jul 25 07:06:54 PM PDT 24
Finished Jul 25 07:06:55 PM PDT 24
Peak memory 207084 kb
Host smart-e1198bf0-d987-4cc8-9a50-69b66a006279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12963
51360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.1296351360
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.2107586934
Short name T2855
Test name
Test status
Simulation time 7119026178 ps
CPU time 71.98 seconds
Started Jul 25 07:06:51 PM PDT 24
Finished Jul 25 07:08:04 PM PDT 24
Peak memory 216844 kb
Host smart-72846bf0-e126-4f54-873c-bf1b20c16c0a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2107586934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.2107586934
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/35.usbdev_iso_retraction.1478260118
Short name T1492
Test name
Test status
Simulation time 12144547555 ps
CPU time 152.38 seconds
Started Jul 25 07:06:47 PM PDT 24
Finished Jul 25 07:09:19 PM PDT 24
Peak memory 207312 kb
Host smart-0a51cca9-6604-43aa-8b31-067d6c9822d6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1478260118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.1478260118
Directory /workspace/35.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.3883584338
Short name T998
Test name
Test status
Simulation time 196578522 ps
CPU time 0.96 seconds
Started Jul 25 07:06:44 PM PDT 24
Finished Jul 25 07:06:45 PM PDT 24
Peak memory 207124 kb
Host smart-09369eb2-60a9-444e-ba85-0558ab940a3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38835
84338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.3883584338
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.622905703
Short name T2
Test name
Test status
Simulation time 23347247441 ps
CPU time 27.83 seconds
Started Jul 25 07:06:49 PM PDT 24
Finished Jul 25 07:07:17 PM PDT 24
Peak memory 207120 kb
Host smart-a07a5afb-fb95-4027-82b2-2ea6c2124230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62290
5703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.622905703
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.1718822224
Short name T1191
Test name
Test status
Simulation time 3335902316 ps
CPU time 6.01 seconds
Started Jul 25 07:06:48 PM PDT 24
Finished Jul 25 07:06:54 PM PDT 24
Peak memory 207176 kb
Host smart-ad266664-7a9b-4bcc-a944-45f97ae37072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17188
22224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.1718822224
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.3636884226
Short name T1391
Test name
Test status
Simulation time 5108045121 ps
CPU time 38.12 seconds
Started Jul 25 07:06:43 PM PDT 24
Finished Jul 25 07:07:21 PM PDT 24
Peak memory 223740 kb
Host smart-4b355f3c-04a6-4a93-a67c-3269ee8d651a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36368
84226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.3636884226
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.2625251869
Short name T1935
Test name
Test status
Simulation time 5076357857 ps
CPU time 51.36 seconds
Started Jul 25 07:06:46 PM PDT 24
Finished Jul 25 07:07:38 PM PDT 24
Peak memory 207392 kb
Host smart-fa9351d6-0ace-4dea-81c3-91bdde481029
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2625251869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.2625251869
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.1549294729
Short name T446
Test name
Test status
Simulation time 245510412 ps
CPU time 1.04 seconds
Started Jul 25 07:06:54 PM PDT 24
Finished Jul 25 07:06:56 PM PDT 24
Peak memory 207196 kb
Host smart-a9d83d72-1258-4fb3-9e6b-0aa7e6070819
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1549294729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.1549294729
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.2919052691
Short name T2631
Test name
Test status
Simulation time 184938354 ps
CPU time 0.97 seconds
Started Jul 25 07:06:50 PM PDT 24
Finished Jul 25 07:06:51 PM PDT 24
Peak memory 207068 kb
Host smart-cf9aafeb-cadd-4486-a674-1012a3b6b769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29190
52691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.2919052691
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.1382345194
Short name T1005
Test name
Test status
Simulation time 4774929513 ps
CPU time 50.23 seconds
Started Jul 25 07:06:51 PM PDT 24
Finished Jul 25 07:07:41 PM PDT 24
Peak memory 215552 kb
Host smart-aab72ad4-63f3-4f03-b7c0-2fe29ff33a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13823
45194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.1382345194
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.1195658803
Short name T1461
Test name
Test status
Simulation time 5276882289 ps
CPU time 52.49 seconds
Started Jul 25 07:06:47 PM PDT 24
Finished Jul 25 07:07:40 PM PDT 24
Peak memory 217112 kb
Host smart-a6ff7ee0-d110-4636-8e4c-bb2c39c25e35
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1195658803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.1195658803
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.694470368
Short name T637
Test name
Test status
Simulation time 156820935 ps
CPU time 0.84 seconds
Started Jul 25 07:06:49 PM PDT 24
Finished Jul 25 07:06:50 PM PDT 24
Peak memory 206968 kb
Host smart-bc79ea91-cee2-44ad-baa3-22400254d900
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=694470368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.694470368
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.220239823
Short name T939
Test name
Test status
Simulation time 182761279 ps
CPU time 0.89 seconds
Started Jul 25 07:06:47 PM PDT 24
Finished Jul 25 07:06:49 PM PDT 24
Peak memory 207136 kb
Host smart-38c25784-1724-426f-b250-c5fb82509a4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22023
9823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.220239823
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.557219790
Short name T138
Test name
Test status
Simulation time 253964151 ps
CPU time 1.01 seconds
Started Jul 25 07:06:52 PM PDT 24
Finished Jul 25 07:06:53 PM PDT 24
Peak memory 207124 kb
Host smart-63a433f0-d38d-461e-a664-b5a3a364ecf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55721
9790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.557219790
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.2719859946
Short name T1345
Test name
Test status
Simulation time 158822322 ps
CPU time 0.89 seconds
Started Jul 25 07:06:50 PM PDT 24
Finished Jul 25 07:06:51 PM PDT 24
Peak memory 207120 kb
Host smart-61a51e0a-74c2-4c0c-901f-a390d0c48791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27198
59946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.2719859946
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.1340893586
Short name T1953
Test name
Test status
Simulation time 153795905 ps
CPU time 0.85 seconds
Started Jul 25 07:06:45 PM PDT 24
Finished Jul 25 07:06:46 PM PDT 24
Peak memory 207164 kb
Host smart-f0e3ac68-5fb9-425b-81e2-9596a008cd5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13408
93586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.1340893586
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.1506597207
Short name T623
Test name
Test status
Simulation time 183061735 ps
CPU time 0.92 seconds
Started Jul 25 07:06:49 PM PDT 24
Finished Jul 25 07:06:51 PM PDT 24
Peak memory 207120 kb
Host smart-f4398743-6052-495a-8f27-6092d0134bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15065
97207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.1506597207
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.2120814445
Short name T197
Test name
Test status
Simulation time 173291190 ps
CPU time 0.88 seconds
Started Jul 25 07:06:50 PM PDT 24
Finished Jul 25 07:06:51 PM PDT 24
Peak memory 207052 kb
Host smart-4a652652-de2c-43f6-9260-62ad838c6dd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21208
14445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.2120814445
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.2573819526
Short name T1831
Test name
Test status
Simulation time 203572959 ps
CPU time 1.07 seconds
Started Jul 25 07:06:47 PM PDT 24
Finished Jul 25 07:06:48 PM PDT 24
Peak memory 207168 kb
Host smart-4208b436-dcc6-481d-aa86-3a5585f733b7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2573819526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.2573819526
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.3030742339
Short name T1322
Test name
Test status
Simulation time 146345456 ps
CPU time 0.84 seconds
Started Jul 25 07:06:44 PM PDT 24
Finished Jul 25 07:06:45 PM PDT 24
Peak memory 207196 kb
Host smart-1190ef38-ec20-4967-8c48-1988f0174f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30307
42339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.3030742339
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.49298600
Short name T955
Test name
Test status
Simulation time 36571793 ps
CPU time 0.7 seconds
Started Jul 25 07:06:43 PM PDT 24
Finished Jul 25 07:06:44 PM PDT 24
Peak memory 207188 kb
Host smart-96531860-d974-4e19-a33b-0e6a56e10f6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49298
600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.49298600
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.3052956733
Short name T293
Test name
Test status
Simulation time 7725578745 ps
CPU time 20.74 seconds
Started Jul 25 07:06:46 PM PDT 24
Finished Jul 25 07:07:07 PM PDT 24
Peak memory 215616 kb
Host smart-c73a2182-1519-4df8-9ce3-756b8087e097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30529
56733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.3052956733
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.37505511
Short name T2270
Test name
Test status
Simulation time 226903665 ps
CPU time 0.95 seconds
Started Jul 25 07:06:48 PM PDT 24
Finished Jul 25 07:06:49 PM PDT 24
Peak memory 206988 kb
Host smart-1fefa39d-cd83-47d7-81a9-1201be1ff326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37505
511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.37505511
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.4212014566
Short name T1486
Test name
Test status
Simulation time 256660616 ps
CPU time 0.99 seconds
Started Jul 25 07:06:42 PM PDT 24
Finished Jul 25 07:06:44 PM PDT 24
Peak memory 207136 kb
Host smart-1d839321-5aaf-418b-8b49-5b79e5f0d22a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42120
14566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.4212014566
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.442293173
Short name T1086
Test name
Test status
Simulation time 229732349 ps
CPU time 0.97 seconds
Started Jul 25 07:06:49 PM PDT 24
Finished Jul 25 07:06:50 PM PDT 24
Peak memory 207128 kb
Host smart-ef02415f-d5df-4aea-b071-2180192ac64d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44229
3173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.442293173
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.30149565
Short name T2148
Test name
Test status
Simulation time 245885755 ps
CPU time 1.04 seconds
Started Jul 25 07:06:52 PM PDT 24
Finished Jul 25 07:06:53 PM PDT 24
Peak memory 207144 kb
Host smart-a9c0a0ca-4dc8-46c2-8bad-85563b5cb221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30149
565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.30149565
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.3107257166
Short name T1866
Test name
Test status
Simulation time 161849143 ps
CPU time 0.84 seconds
Started Jul 25 07:06:50 PM PDT 24
Finished Jul 25 07:06:51 PM PDT 24
Peak memory 207100 kb
Host smart-ee7888aa-c5cf-49f3-addc-9a996f479089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31072
57166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.3107257166
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.1623045251
Short name T2392
Test name
Test status
Simulation time 193731149 ps
CPU time 0.87 seconds
Started Jul 25 07:06:51 PM PDT 24
Finished Jul 25 07:06:52 PM PDT 24
Peak memory 207092 kb
Host smart-115486cb-4358-44f4-a126-e51a9a37df53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16230
45251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.1623045251
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.2069389722
Short name T2226
Test name
Test status
Simulation time 218113674 ps
CPU time 1 seconds
Started Jul 25 07:06:54 PM PDT 24
Finished Jul 25 07:06:56 PM PDT 24
Peak memory 207128 kb
Host smart-ad949f91-849d-431b-901a-2a9acd866120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20693
89722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.2069389722
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.1517061858
Short name T2113
Test name
Test status
Simulation time 283660599 ps
CPU time 1.1 seconds
Started Jul 25 07:07:04 PM PDT 24
Finished Jul 25 07:07:05 PM PDT 24
Peak memory 207116 kb
Host smart-ea0730f0-f612-4c18-8207-19966a1295a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15170
61858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.1517061858
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.2576480981
Short name T2819
Test name
Test status
Simulation time 5418458282 ps
CPU time 55.59 seconds
Started Jul 25 07:06:54 PM PDT 24
Finished Jul 25 07:07:50 PM PDT 24
Peak memory 216680 kb
Host smart-c2b3e5f9-c1a4-4e82-8847-be061c150bf8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2576480981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.2576480981
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.3704039490
Short name T2065
Test name
Test status
Simulation time 165471718 ps
CPU time 0.9 seconds
Started Jul 25 07:06:55 PM PDT 24
Finished Jul 25 07:06:56 PM PDT 24
Peak memory 207108 kb
Host smart-7cf84594-9ca8-4ee5-9715-f5b0dc179e6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37040
39490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.3704039490
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.3744325007
Short name T364
Test name
Test status
Simulation time 161737359 ps
CPU time 0.91 seconds
Started Jul 25 07:07:02 PM PDT 24
Finished Jul 25 07:07:03 PM PDT 24
Peak memory 207124 kb
Host smart-8f76ce81-fa33-45bf-a176-e6def23e7f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37443
25007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.3744325007
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.432908297
Short name T2099
Test name
Test status
Simulation time 822777495 ps
CPU time 2.21 seconds
Started Jul 25 07:06:54 PM PDT 24
Finished Jul 25 07:06:56 PM PDT 24
Peak memory 207372 kb
Host smart-edbe474d-c278-4d57-8b43-81c79dad0db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43290
8297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.432908297
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.1744714087
Short name T1225
Test name
Test status
Simulation time 4673910171 ps
CPU time 37.19 seconds
Started Jul 25 07:06:57 PM PDT 24
Finished Jul 25 07:07:35 PM PDT 24
Peak memory 207420 kb
Host smart-bc2dcecc-64b3-4bd9-8ea4-36e1d484ffd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17447
14087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.1744714087
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_timeout_missing_host_handshake.2265519973
Short name T581
Test name
Test status
Simulation time 2448929476 ps
CPU time 22.31 seconds
Started Jul 25 07:06:47 PM PDT 24
Finished Jul 25 07:07:09 PM PDT 24
Peak memory 207372 kb
Host smart-87a1c250-523a-4c70-a685-acdef027b3ea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265519973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_timeout_missing_hos
t_handshake.2265519973
Directory /workspace/35.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.1613709324
Short name T536
Test name
Test status
Simulation time 73669570 ps
CPU time 0.81 seconds
Started Jul 25 07:07:01 PM PDT 24
Finished Jul 25 07:07:02 PM PDT 24
Peak memory 207176 kb
Host smart-f4f4bd88-30c3-4f0d-9c7a-06e6a8f08e90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1613709324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.1613709324
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.2925935043
Short name T1336
Test name
Test status
Simulation time 3834948626 ps
CPU time 5.59 seconds
Started Jul 25 07:06:53 PM PDT 24
Finished Jul 25 07:06:59 PM PDT 24
Peak memory 207368 kb
Host smart-97f60a87-c441-4e9e-82ff-6d04ea509601
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925935043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_a
on_wake_disconnect.2925935043
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.4228259240
Short name T2843
Test name
Test status
Simulation time 13340337690 ps
CPU time 15.7 seconds
Started Jul 25 07:07:01 PM PDT 24
Finished Jul 25 07:07:17 PM PDT 24
Peak memory 207392 kb
Host smart-b2e1da54-8553-4933-a4d9-a087396263d8
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228259240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.4228259240
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.1507954043
Short name T1946
Test name
Test status
Simulation time 23370313474 ps
CPU time 33.42 seconds
Started Jul 25 07:06:59 PM PDT 24
Finished Jul 25 07:07:33 PM PDT 24
Peak memory 207316 kb
Host smart-1cfa77c5-e529-420c-b325-691b7e3171e5
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507954043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_a
on_wake_resume.1507954043
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.1243792031
Short name T2465
Test name
Test status
Simulation time 204827149 ps
CPU time 1.08 seconds
Started Jul 25 07:07:01 PM PDT 24
Finished Jul 25 07:07:02 PM PDT 24
Peak memory 207108 kb
Host smart-e6d22a13-f143-4e3c-92f6-cac9d4bff0a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12437
92031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.1243792031
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.1970702673
Short name T198
Test name
Test status
Simulation time 182231222 ps
CPU time 0.92 seconds
Started Jul 25 07:06:59 PM PDT 24
Finished Jul 25 07:07:01 PM PDT 24
Peak memory 207084 kb
Host smart-4ecf22de-fce1-4b0f-94fa-20f02feead37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19707
02673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.1970702673
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.3595667136
Short name T1045
Test name
Test status
Simulation time 509910961 ps
CPU time 1.82 seconds
Started Jul 25 07:06:58 PM PDT 24
Finished Jul 25 07:07:00 PM PDT 24
Peak memory 207144 kb
Host smart-918dff81-5954-4304-9ef2-bef29c8ce1b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35956
67136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.3595667136
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.1577951526
Short name T1397
Test name
Test status
Simulation time 935996357 ps
CPU time 2.36 seconds
Started Jul 25 07:06:56 PM PDT 24
Finished Jul 25 07:06:59 PM PDT 24
Peak memory 207364 kb
Host smart-33e19e46-fc60-451f-a828-f18e0a98f3c4
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1577951526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.1577951526
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.234449645
Short name T181
Test name
Test status
Simulation time 21113810296 ps
CPU time 49.88 seconds
Started Jul 25 07:06:53 PM PDT 24
Finished Jul 25 07:07:43 PM PDT 24
Peak memory 207372 kb
Host smart-4cf320b2-e352-401e-90c9-f4d69885862b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23444
9645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.234449645
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_device_timeout.3992431862
Short name T1135
Test name
Test status
Simulation time 5718126248 ps
CPU time 39.19 seconds
Started Jul 25 07:06:58 PM PDT 24
Finished Jul 25 07:07:38 PM PDT 24
Peak memory 207396 kb
Host smart-7f2aacd7-74a1-4131-8fe5-12734798ff4f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992431862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_timeout.3992431862
Directory /workspace/36.usbdev_device_timeout/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.810571945
Short name T2473
Test name
Test status
Simulation time 456013292 ps
CPU time 1.63 seconds
Started Jul 25 07:06:56 PM PDT 24
Finished Jul 25 07:06:58 PM PDT 24
Peak memory 207032 kb
Host smart-22e3eb63-ab68-4b8d-9458-de1fe6fdc839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81057
1945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.810571945
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.2965340821
Short name T2120
Test name
Test status
Simulation time 154603598 ps
CPU time 0.83 seconds
Started Jul 25 07:06:53 PM PDT 24
Finished Jul 25 07:06:54 PM PDT 24
Peak memory 207088 kb
Host smart-3e5c3977-0a3d-4697-8bcf-6deacbe600e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29653
40821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.2965340821
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.1666402211
Short name T1736
Test name
Test status
Simulation time 54082715 ps
CPU time 0.7 seconds
Started Jul 25 07:06:55 PM PDT 24
Finished Jul 25 07:06:56 PM PDT 24
Peak memory 207088 kb
Host smart-4d449dac-0fc8-4836-99e5-137c6d689586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16664
02211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.1666402211
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.487158896
Short name T1341
Test name
Test status
Simulation time 867578762 ps
CPU time 2.38 seconds
Started Jul 25 07:07:02 PM PDT 24
Finished Jul 25 07:07:05 PM PDT 24
Peak memory 207268 kb
Host smart-c9ce3b0e-72ea-457f-9d35-aaa61495b7dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48715
8896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.487158896
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.1442361891
Short name T1809
Test name
Test status
Simulation time 250743898 ps
CPU time 1.84 seconds
Started Jul 25 07:07:00 PM PDT 24
Finished Jul 25 07:07:02 PM PDT 24
Peak memory 207228 kb
Host smart-5745e67c-c7eb-4203-9279-5e4088474706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14423
61891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.1442361891
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.2724096053
Short name T447
Test name
Test status
Simulation time 222876293 ps
CPU time 1.19 seconds
Started Jul 25 07:06:59 PM PDT 24
Finished Jul 25 07:07:01 PM PDT 24
Peak memory 215468 kb
Host smart-f201e97e-71d7-4078-b1a6-67eede5de0c7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2724096053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.2724096053
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.686265546
Short name T1673
Test name
Test status
Simulation time 146610941 ps
CPU time 0.86 seconds
Started Jul 25 07:06:57 PM PDT 24
Finished Jul 25 07:06:59 PM PDT 24
Peak memory 207092 kb
Host smart-098e64f0-9034-4c0a-9bbd-d68ddc299900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68626
5546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.686265546
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.1473615010
Short name T1765
Test name
Test status
Simulation time 210142636 ps
CPU time 0.95 seconds
Started Jul 25 07:06:59 PM PDT 24
Finished Jul 25 07:07:00 PM PDT 24
Peak memory 207140 kb
Host smart-e5210a65-a1aa-4661-932d-6ff936cf455a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14736
15010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.1473615010
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_invalid_sync.4234005266
Short name T121
Test name
Test status
Simulation time 9799888139 ps
CPU time 78 seconds
Started Jul 25 07:06:54 PM PDT 24
Finished Jul 25 07:08:13 PM PDT 24
Peak memory 217064 kb
Host smart-fbe29d15-2540-41ef-a1f2-c5dbf45b94b2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4234005266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.4234005266
Directory /workspace/36.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/36.usbdev_iso_retraction.504024284
Short name T2053
Test name
Test status
Simulation time 8517143051 ps
CPU time 100.58 seconds
Started Jul 25 07:07:00 PM PDT 24
Finished Jul 25 07:08:40 PM PDT 24
Peak memory 207332 kb
Host smart-f653e5fc-0458-4ddf-b459-0fe63051210b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=504024284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_iso_retraction.504024284
Directory /workspace/36.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.1720839858
Short name T2373
Test name
Test status
Simulation time 198947192 ps
CPU time 0.97 seconds
Started Jul 25 07:07:01 PM PDT 24
Finished Jul 25 07:07:02 PM PDT 24
Peak memory 207120 kb
Host smart-b43a73b3-b9d7-40a9-8041-3051bf2a7d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17208
39858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.1720839858
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.3021536389
Short name T887
Test name
Test status
Simulation time 23354271911 ps
CPU time 29.56 seconds
Started Jul 25 07:07:03 PM PDT 24
Finished Jul 25 07:07:32 PM PDT 24
Peak memory 207364 kb
Host smart-b0fd26bd-92e9-4e4b-acdc-92b0254edc63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30215
36389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.3021536389
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.2588075209
Short name T799
Test name
Test status
Simulation time 3308311140 ps
CPU time 4.81 seconds
Started Jul 25 07:07:01 PM PDT 24
Finished Jul 25 07:07:06 PM PDT 24
Peak memory 207372 kb
Host smart-d5235053-ec41-4c68-b75e-e4d1be02cb64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25880
75209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.2588075209
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.3289704739
Short name T1570
Test name
Test status
Simulation time 8795120090 ps
CPU time 87.8 seconds
Started Jul 25 07:07:01 PM PDT 24
Finished Jul 25 07:08:29 PM PDT 24
Peak memory 217628 kb
Host smart-a44b113f-df2e-4e09-8247-311281ce90da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32897
04739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.3289704739
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.254440757
Short name T807
Test name
Test status
Simulation time 5003069963 ps
CPU time 144.2 seconds
Started Jul 25 07:06:55 PM PDT 24
Finished Jul 25 07:09:19 PM PDT 24
Peak memory 215604 kb
Host smart-58f9cf07-4243-4775-9541-f114fb29cf48
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=254440757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.254440757
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.1384189643
Short name T1475
Test name
Test status
Simulation time 251138314 ps
CPU time 0.99 seconds
Started Jul 25 07:06:58 PM PDT 24
Finished Jul 25 07:07:00 PM PDT 24
Peak memory 207144 kb
Host smart-386f3b22-eba9-41f6-a2dd-666525e99781
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1384189643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.1384189643
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.2311159454
Short name T1770
Test name
Test status
Simulation time 235773656 ps
CPU time 1.02 seconds
Started Jul 25 07:06:59 PM PDT 24
Finished Jul 25 07:07:00 PM PDT 24
Peak memory 207168 kb
Host smart-d15c11be-60ff-4bb7-8952-a71b9ec33b53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23111
59454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.2311159454
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.3556943789
Short name T1472
Test name
Test status
Simulation time 3986211953 ps
CPU time 29.32 seconds
Started Jul 25 07:06:57 PM PDT 24
Finished Jul 25 07:07:27 PM PDT 24
Peak memory 215504 kb
Host smart-32c91d13-40a0-4b7a-941f-2e0c72259893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35569
43789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.3556943789
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.536478627
Short name T2109
Test name
Test status
Simulation time 5486522343 ps
CPU time 154.64 seconds
Started Jul 25 07:06:59 PM PDT 24
Finished Jul 25 07:09:34 PM PDT 24
Peak memory 215612 kb
Host smart-e20dfa1f-51eb-49ea-80f0-801754012732
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=536478627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.536478627
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.3938753697
Short name T1741
Test name
Test status
Simulation time 150028806 ps
CPU time 0.84 seconds
Started Jul 25 07:07:00 PM PDT 24
Finished Jul 25 07:07:01 PM PDT 24
Peak memory 207168 kb
Host smart-79c948ac-7440-48c8-95f0-e6067f26194e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3938753697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.3938753697
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.2164508032
Short name T921
Test name
Test status
Simulation time 176575078 ps
CPU time 0.87 seconds
Started Jul 25 07:06:57 PM PDT 24
Finished Jul 25 07:06:58 PM PDT 24
Peak memory 207104 kb
Host smart-86b8d220-0afa-4cd2-b381-3c8dad72a3b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21645
08032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.2164508032
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.2817434790
Short name T2582
Test name
Test status
Simulation time 189106152 ps
CPU time 0.93 seconds
Started Jul 25 07:06:58 PM PDT 24
Finished Jul 25 07:06:59 PM PDT 24
Peak memory 207104 kb
Host smart-8734c0b3-8685-4f8d-b0a3-3e126ee64618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28174
34790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.2817434790
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.1087418848
Short name T2638
Test name
Test status
Simulation time 163972877 ps
CPU time 0.91 seconds
Started Jul 25 07:06:55 PM PDT 24
Finished Jul 25 07:06:56 PM PDT 24
Peak memory 207188 kb
Host smart-a706745f-0ebb-4329-997e-7ce8f434ed90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10874
18848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.1087418848
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.2043946090
Short name T1677
Test name
Test status
Simulation time 190147037 ps
CPU time 0.95 seconds
Started Jul 25 07:06:59 PM PDT 24
Finished Jul 25 07:07:00 PM PDT 24
Peak memory 207128 kb
Host smart-7da904d5-f355-4ad9-875b-99b6c93f9762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20439
46090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.2043946090
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.409591878
Short name T1285
Test name
Test status
Simulation time 206610032 ps
CPU time 0.95 seconds
Started Jul 25 07:06:54 PM PDT 24
Finished Jul 25 07:06:55 PM PDT 24
Peak memory 207132 kb
Host smart-02442942-efcc-4338-8cee-83af7d46bc8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40959
1878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.409591878
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.3317134075
Short name T2123
Test name
Test status
Simulation time 163533703 ps
CPU time 0.86 seconds
Started Jul 25 07:07:28 PM PDT 24
Finished Jul 25 07:07:29 PM PDT 24
Peak memory 207156 kb
Host smart-642e2a09-df42-4053-98d7-d72746d910fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33171
34075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.3317134075
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.1701552157
Short name T756
Test name
Test status
Simulation time 198074613 ps
CPU time 0.93 seconds
Started Jul 25 07:07:00 PM PDT 24
Finished Jul 25 07:07:01 PM PDT 24
Peak memory 207132 kb
Host smart-ce8c9cfc-9ec0-4412-a45c-f008b66b4288
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1701552157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.1701552157
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.443940385
Short name T649
Test name
Test status
Simulation time 154892844 ps
CPU time 0.84 seconds
Started Jul 25 07:07:00 PM PDT 24
Finished Jul 25 07:07:01 PM PDT 24
Peak memory 207108 kb
Host smart-4f09b3f0-402e-4b52-bb02-c00c3c141a3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44394
0385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.443940385
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.2755548259
Short name T2796
Test name
Test status
Simulation time 35082745 ps
CPU time 0.7 seconds
Started Jul 25 07:06:56 PM PDT 24
Finished Jul 25 07:06:57 PM PDT 24
Peak memory 207116 kb
Host smart-70a98086-7b95-4f8d-8636-f758f6db164c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27555
48259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.2755548259
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.422920516
Short name T1429
Test name
Test status
Simulation time 13121094646 ps
CPU time 31.05 seconds
Started Jul 25 07:09:51 PM PDT 24
Finished Jul 25 07:10:23 PM PDT 24
Peak memory 215644 kb
Host smart-97445fea-b859-4ce3-9940-9d37ebf071c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42292
0516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.422920516
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.2046154312
Short name T1368
Test name
Test status
Simulation time 181802800 ps
CPU time 0.89 seconds
Started Jul 25 07:07:02 PM PDT 24
Finished Jul 25 07:07:03 PM PDT 24
Peak memory 207124 kb
Host smart-5fcbf7a4-8a43-4249-a589-bc78440f7147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20461
54312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.2046154312
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.85849957
Short name T1793
Test name
Test status
Simulation time 228012245 ps
CPU time 0.95 seconds
Started Jul 25 07:06:58 PM PDT 24
Finished Jul 25 07:07:00 PM PDT 24
Peak memory 207088 kb
Host smart-98a056ff-e4da-4868-9725-c26b7b599383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85849
957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.85849957
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.4115170843
Short name T1110
Test name
Test status
Simulation time 205659616 ps
CPU time 0.94 seconds
Started Jul 25 07:07:00 PM PDT 24
Finished Jul 25 07:07:01 PM PDT 24
Peak memory 207084 kb
Host smart-73b7f8de-8801-48f4-9c59-5bb0a00fefd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41151
70843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.4115170843
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.3278834710
Short name T2114
Test name
Test status
Simulation time 185211385 ps
CPU time 0.99 seconds
Started Jul 25 07:06:57 PM PDT 24
Finished Jul 25 07:06:58 PM PDT 24
Peak memory 207152 kb
Host smart-9651f5d0-cde2-46c3-aee5-df28e9659e12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32788
34710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.3278834710
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.871597055
Short name T2861
Test name
Test status
Simulation time 190592892 ps
CPU time 0.98 seconds
Started Jul 25 07:06:56 PM PDT 24
Finished Jul 25 07:06:58 PM PDT 24
Peak memory 207176 kb
Host smart-26feb086-75da-4c3f-86dc-91b6f31a5ac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87159
7055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.871597055
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.2127661591
Short name T377
Test name
Test status
Simulation time 150394457 ps
CPU time 0.8 seconds
Started Jul 25 07:06:55 PM PDT 24
Finished Jul 25 07:06:56 PM PDT 24
Peak memory 207092 kb
Host smart-91740665-c981-4e47-bb89-f95f744b392c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21276
61591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.2127661591
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.1167021633
Short name T392
Test name
Test status
Simulation time 229378788 ps
CPU time 1 seconds
Started Jul 25 07:06:56 PM PDT 24
Finished Jul 25 07:06:57 PM PDT 24
Peak memory 207132 kb
Host smart-3376fcc4-5f6e-46f0-bd40-5a2a781b345e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11670
21633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.1167021633
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.4226374569
Short name T1493
Test name
Test status
Simulation time 237859528 ps
CPU time 1.06 seconds
Started Jul 25 07:06:56 PM PDT 24
Finished Jul 25 07:06:58 PM PDT 24
Peak memory 207160 kb
Host smart-4013b60e-ba6f-4b20-9111-644285a4ee00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42263
74569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.4226374569
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.3170733900
Short name T1454
Test name
Test status
Simulation time 5446647356 ps
CPU time 44.45 seconds
Started Jul 25 07:06:59 PM PDT 24
Finished Jul 25 07:07:44 PM PDT 24
Peak memory 217032 kb
Host smart-034da1da-c404-4cd3-8068-0c7c7224ae3c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3170733900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.3170733900
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.4122203729
Short name T1181
Test name
Test status
Simulation time 150223045 ps
CPU time 0.86 seconds
Started Jul 25 07:07:00 PM PDT 24
Finished Jul 25 07:07:01 PM PDT 24
Peak memory 207200 kb
Host smart-abdcb2da-68d1-4634-a407-18c07e7638c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41222
03729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.4122203729
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.1245482726
Short name T665
Test name
Test status
Simulation time 179081667 ps
CPU time 0.95 seconds
Started Jul 25 07:07:06 PM PDT 24
Finished Jul 25 07:07:07 PM PDT 24
Peak memory 207128 kb
Host smart-cbc627fe-abad-45db-8f3f-9720d3ed5b24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12454
82726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.1245482726
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.1851467928
Short name T1309
Test name
Test status
Simulation time 338616225 ps
CPU time 1.25 seconds
Started Jul 25 07:06:56 PM PDT 24
Finished Jul 25 07:06:58 PM PDT 24
Peak memory 207160 kb
Host smart-9e9574f7-ff58-4adf-8502-de2afd7456e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18514
67928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.1851467928
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.1362548658
Short name T1039
Test name
Test status
Simulation time 7431684061 ps
CPU time 59.8 seconds
Started Jul 25 07:07:04 PM PDT 24
Finished Jul 25 07:08:04 PM PDT 24
Peak memory 207372 kb
Host smart-6bdcba78-8bab-4e44-a44d-06d9f04e1d8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13625
48658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.1362548658
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_timeout_missing_host_handshake.566134502
Short name T1147
Test name
Test status
Simulation time 3603931227 ps
CPU time 23.59 seconds
Started Jul 25 07:06:59 PM PDT 24
Finished Jul 25 07:07:23 PM PDT 24
Peak memory 207388 kb
Host smart-227192b4-94d4-4c5c-b9c1-9bb368a10c4a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566134502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_timeout_missing_host
_handshake.566134502
Directory /workspace/36.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.2674040347
Short name T2175
Test name
Test status
Simulation time 72909636 ps
CPU time 0.67 seconds
Started Jul 25 07:07:09 PM PDT 24
Finished Jul 25 07:07:10 PM PDT 24
Peak memory 207184 kb
Host smart-03c799ac-2726-47ec-9aa7-b8a662e62e90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2674040347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.2674040347
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.3233865038
Short name T1384
Test name
Test status
Simulation time 3505460676 ps
CPU time 5.76 seconds
Started Jul 25 07:06:55 PM PDT 24
Finished Jul 25 07:07:01 PM PDT 24
Peak memory 207484 kb
Host smart-ee270cc9-f9c3-49ae-9ecb-5ed659564a1b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233865038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_a
on_wake_disconnect.3233865038
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.1648059481
Short name T2234
Test name
Test status
Simulation time 13337493234 ps
CPU time 15.23 seconds
Started Jul 25 07:07:03 PM PDT 24
Finished Jul 25 07:07:19 PM PDT 24
Peak memory 207436 kb
Host smart-260810d0-b44f-4a9f-9be7-bc3cb18c880e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648059481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.1648059481
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.1245478426
Short name T1166
Test name
Test status
Simulation time 23405863206 ps
CPU time 28.85 seconds
Started Jul 25 07:06:57 PM PDT 24
Finished Jul 25 07:07:26 PM PDT 24
Peak memory 207408 kb
Host smart-ea53f137-7721-4ed4-8eb6-cc32da77b8f7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245478426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_a
on_wake_resume.1245478426
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.2969733673
Short name T1521
Test name
Test status
Simulation time 160234204 ps
CPU time 0.9 seconds
Started Jul 25 07:07:03 PM PDT 24
Finished Jul 25 07:07:05 PM PDT 24
Peak memory 207168 kb
Host smart-020f44f1-a668-413a-b4b0-a41010f3718b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29697
33673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.2969733673
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.1909627117
Short name T2526
Test name
Test status
Simulation time 146609236 ps
CPU time 0.9 seconds
Started Jul 25 07:07:03 PM PDT 24
Finished Jul 25 07:07:05 PM PDT 24
Peak memory 207136 kb
Host smart-ed31fc05-0d1e-479d-af6b-0bf3a3043e2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19096
27117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.1909627117
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.2062872619
Short name T2566
Test name
Test status
Simulation time 423898840 ps
CPU time 1.48 seconds
Started Jul 25 07:07:07 PM PDT 24
Finished Jul 25 07:07:09 PM PDT 24
Peak memory 207144 kb
Host smart-7da6d260-d971-44e6-a8df-b3b4b3f69fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20628
72619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.2062872619
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.2210532535
Short name T2718
Test name
Test status
Simulation time 487103882 ps
CPU time 1.58 seconds
Started Jul 25 07:06:59 PM PDT 24
Finished Jul 25 07:07:01 PM PDT 24
Peak memory 207128 kb
Host smart-1fb764e8-b7ec-4796-81a0-cae9b86023b9
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2210532535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.2210532535
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.3016759646
Short name T1070
Test name
Test status
Simulation time 20493527433 ps
CPU time 44.05 seconds
Started Jul 25 07:07:04 PM PDT 24
Finished Jul 25 07:07:49 PM PDT 24
Peak memory 207404 kb
Host smart-7c9eeb8d-9468-4d5f-8990-cd145206bbb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30167
59646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.3016759646
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_device_timeout.2145760982
Short name T1672
Test name
Test status
Simulation time 2907077793 ps
CPU time 18.62 seconds
Started Jul 25 07:06:57 PM PDT 24
Finished Jul 25 07:07:16 PM PDT 24
Peak memory 207428 kb
Host smart-23642a19-ebf4-4a27-a3b6-68f6c2c1d034
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145760982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_timeout.2145760982
Directory /workspace/37.usbdev_device_timeout/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.993967428
Short name T304
Test name
Test status
Simulation time 380856731 ps
CPU time 1.4 seconds
Started Jul 25 07:07:04 PM PDT 24
Finished Jul 25 07:07:06 PM PDT 24
Peak memory 207096 kb
Host smart-0f7bc776-10ff-4548-8a72-4a28883c50fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99396
7428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.993967428
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.2613116654
Short name T1811
Test name
Test status
Simulation time 137953574 ps
CPU time 0.77 seconds
Started Jul 25 07:07:04 PM PDT 24
Finished Jul 25 07:07:05 PM PDT 24
Peak memory 207096 kb
Host smart-14e03774-9302-4354-a9f4-1064b3ff4128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26131
16654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.2613116654
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.3981719159
Short name T1526
Test name
Test status
Simulation time 53787712 ps
CPU time 0.76 seconds
Started Jul 25 07:07:05 PM PDT 24
Finished Jul 25 07:07:06 PM PDT 24
Peak memory 207088 kb
Host smart-d07825b7-3f32-4b21-a6e1-59735d183d41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39817
19159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.3981719159
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.3559702115
Short name T60
Test name
Test status
Simulation time 876662070 ps
CPU time 2.52 seconds
Started Jul 25 07:07:03 PM PDT 24
Finished Jul 25 07:07:06 PM PDT 24
Peak memory 207388 kb
Host smart-f0306c34-6d0b-4c84-898c-06242c454635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35597
02115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.3559702115
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.3110913810
Short name T1778
Test name
Test status
Simulation time 284950421 ps
CPU time 1.97 seconds
Started Jul 25 07:06:57 PM PDT 24
Finished Jul 25 07:06:59 PM PDT 24
Peak memory 207440 kb
Host smart-9383124a-91ad-4c3c-ba71-ce029395d58e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31109
13810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.3110913810
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.162269741
Short name T695
Test name
Test status
Simulation time 178346802 ps
CPU time 1.06 seconds
Started Jul 25 07:07:00 PM PDT 24
Finished Jul 25 07:07:02 PM PDT 24
Peak memory 207312 kb
Host smart-1f6392e8-bd62-4379-9564-ba981593f660
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=162269741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.162269741
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.982375528
Short name T2794
Test name
Test status
Simulation time 142825124 ps
CPU time 0.8 seconds
Started Jul 25 07:07:20 PM PDT 24
Finished Jul 25 07:07:21 PM PDT 24
Peak memory 206836 kb
Host smart-3a0bcf03-7e80-4c04-94c7-a522a7c0e2b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98237
5528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.982375528
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.3661544439
Short name T2851
Test name
Test status
Simulation time 194747316 ps
CPU time 0.95 seconds
Started Jul 25 07:07:03 PM PDT 24
Finished Jul 25 07:07:04 PM PDT 24
Peak memory 207152 kb
Host smart-3262501d-96c7-4ac0-8606-eb4031ff0cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36615
44439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.3661544439
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.3898746151
Short name T1732
Test name
Test status
Simulation time 4781189456 ps
CPU time 35.9 seconds
Started Jul 25 07:06:57 PM PDT 24
Finished Jul 25 07:07:33 PM PDT 24
Peak memory 216956 kb
Host smart-1f57981a-bd0b-4094-9351-0f1a17eb209a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3898746151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.3898746151
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_iso_retraction.163847518
Short name T1020
Test name
Test status
Simulation time 7721718324 ps
CPU time 102.61 seconds
Started Jul 25 07:07:03 PM PDT 24
Finished Jul 25 07:08:46 PM PDT 24
Peak memory 207336 kb
Host smart-ce0ff297-8911-482d-ba14-e4373e0e7282
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=163847518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_iso_retraction.163847518
Directory /workspace/37.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.3081563393
Short name T1820
Test name
Test status
Simulation time 188383489 ps
CPU time 0.9 seconds
Started Jul 25 07:07:05 PM PDT 24
Finished Jul 25 07:07:07 PM PDT 24
Peak memory 207108 kb
Host smart-76557250-5987-461f-ac5e-594ab1917a9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30815
63393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.3081563393
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.1676059225
Short name T1879
Test name
Test status
Simulation time 23349099146 ps
CPU time 28.65 seconds
Started Jul 25 07:07:02 PM PDT 24
Finished Jul 25 07:07:31 PM PDT 24
Peak memory 207340 kb
Host smart-bbe2f986-38c8-438d-97a2-03e22fa92cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16760
59225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.1676059225
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.3585286860
Short name T539
Test name
Test status
Simulation time 3311518189 ps
CPU time 5.12 seconds
Started Jul 25 07:07:05 PM PDT 24
Finished Jul 25 07:07:10 PM PDT 24
Peak memory 207372 kb
Host smart-6202722d-0eb3-4167-ad69-7e40f5965a11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35852
86860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.3585286860
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.416914396
Short name T546
Test name
Test status
Simulation time 5400139594 ps
CPU time 55.28 seconds
Started Jul 25 07:07:05 PM PDT 24
Finished Jul 25 07:08:00 PM PDT 24
Peak memory 217428 kb
Host smart-b65e8e75-0f45-430d-90d8-1238bc09e793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41691
4396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.416914396
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.3153414750
Short name T1979
Test name
Test status
Simulation time 6312918963 ps
CPU time 48.33 seconds
Started Jul 25 07:07:07 PM PDT 24
Finished Jul 25 07:07:55 PM PDT 24
Peak memory 207376 kb
Host smart-44a39981-7cf4-46bd-b0b6-2a0b48b385dd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3153414750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.3153414750
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.838551402
Short name T347
Test name
Test status
Simulation time 277894704 ps
CPU time 1.05 seconds
Started Jul 25 07:07:03 PM PDT 24
Finished Jul 25 07:07:05 PM PDT 24
Peak memory 207136 kb
Host smart-2412eefd-1dc2-4e75-a4f7-6443fce08f51
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=838551402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.838551402
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.3845549181
Short name T2815
Test name
Test status
Simulation time 219726897 ps
CPU time 1 seconds
Started Jul 25 07:07:04 PM PDT 24
Finished Jul 25 07:07:05 PM PDT 24
Peak memory 207144 kb
Host smart-193ff123-a123-4cfd-a132-0eadf42a8760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38455
49181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.3845549181
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.3947540804
Short name T952
Test name
Test status
Simulation time 5561123712 ps
CPU time 54.79 seconds
Started Jul 25 07:07:03 PM PDT 24
Finished Jul 25 07:07:58 PM PDT 24
Peak memory 217288 kb
Host smart-643023ca-9ce0-4643-96bc-1a9eff97c8b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39475
40804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.3947540804
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.1065590330
Short name T2422
Test name
Test status
Simulation time 5420645556 ps
CPU time 56.39 seconds
Started Jul 25 07:07:44 PM PDT 24
Finished Jul 25 07:08:40 PM PDT 24
Peak memory 207448 kb
Host smart-ccd5cc02-e662-4f18-b44e-7b68d5738d9e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1065590330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.1065590330
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.587521644
Short name T991
Test name
Test status
Simulation time 218961245 ps
CPU time 0.94 seconds
Started Jul 25 07:07:05 PM PDT 24
Finished Jul 25 07:07:06 PM PDT 24
Peak memory 207120 kb
Host smart-1880fbba-f383-4d94-8d4d-8965551f04ff
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=587521644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.587521644
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.1450623105
Short name T1231
Test name
Test status
Simulation time 148055641 ps
CPU time 0.88 seconds
Started Jul 25 07:07:04 PM PDT 24
Finished Jul 25 07:07:05 PM PDT 24
Peak memory 207096 kb
Host smart-93e64926-0143-4123-9679-e2472f322558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14506
23105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.1450623105
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.124178693
Short name T157
Test name
Test status
Simulation time 196528382 ps
CPU time 0.92 seconds
Started Jul 25 07:07:09 PM PDT 24
Finished Jul 25 07:07:10 PM PDT 24
Peak memory 207144 kb
Host smart-76198f05-f08b-4b88-8af5-3719ff2c1a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12417
8693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.124178693
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.2975933554
Short name T1752
Test name
Test status
Simulation time 208800556 ps
CPU time 0.94 seconds
Started Jul 25 07:07:08 PM PDT 24
Finished Jul 25 07:07:09 PM PDT 24
Peak memory 207148 kb
Host smart-2b452bc2-720e-423a-be5c-d5dc4840b7e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29759
33554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.2975933554
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.2098877177
Short name T1222
Test name
Test status
Simulation time 181054015 ps
CPU time 0.92 seconds
Started Jul 25 07:07:07 PM PDT 24
Finished Jul 25 07:07:08 PM PDT 24
Peak memory 207092 kb
Host smart-492459b5-76d3-4e4a-9394-99ea01a9f776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20988
77177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.2098877177
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.2281580153
Short name T1730
Test name
Test status
Simulation time 163770540 ps
CPU time 0.91 seconds
Started Jul 25 07:07:05 PM PDT 24
Finished Jul 25 07:07:06 PM PDT 24
Peak memory 207232 kb
Host smart-5a58f1e4-dd94-406b-bcac-72ca35e36450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22815
80153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.2281580153
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.1776128906
Short name T709
Test name
Test status
Simulation time 151507001 ps
CPU time 0.86 seconds
Started Jul 25 07:07:08 PM PDT 24
Finished Jul 25 07:07:09 PM PDT 24
Peak memory 207136 kb
Host smart-129622a5-6749-45eb-9366-73603a2316ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17761
28906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.1776128906
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.569320959
Short name T2571
Test name
Test status
Simulation time 218344878 ps
CPU time 1.13 seconds
Started Jul 25 07:07:05 PM PDT 24
Finished Jul 25 07:07:07 PM PDT 24
Peak memory 207132 kb
Host smart-1f5d53bf-1b48-4d8a-a279-974c3070af41
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=569320959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.569320959
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.1837690507
Short name T2039
Test name
Test status
Simulation time 174597189 ps
CPU time 0.87 seconds
Started Jul 25 07:07:03 PM PDT 24
Finished Jul 25 07:07:05 PM PDT 24
Peak memory 207112 kb
Host smart-6090d05e-2eb1-45f2-a515-4e7f986b88e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18376
90507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.1837690507
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.2811570924
Short name T2537
Test name
Test status
Simulation time 78192909 ps
CPU time 0.71 seconds
Started Jul 25 07:07:05 PM PDT 24
Finished Jul 25 07:07:06 PM PDT 24
Peak memory 207084 kb
Host smart-58dbf93f-1200-43ba-b9fe-498caed1fa3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28115
70924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.2811570924
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.2133847188
Short name T2183
Test name
Test status
Simulation time 20106180115 ps
CPU time 51.1 seconds
Started Jul 25 07:07:03 PM PDT 24
Finished Jul 25 07:07:55 PM PDT 24
Peak memory 215532 kb
Host smart-f9a670bf-e8e9-431c-a428-121d02d71daf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21338
47188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.2133847188
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.2564614534
Short name T1687
Test name
Test status
Simulation time 176208251 ps
CPU time 0.89 seconds
Started Jul 25 07:07:08 PM PDT 24
Finished Jul 25 07:07:09 PM PDT 24
Peak memory 207148 kb
Host smart-3cc5e98f-7476-4a1f-aad8-42ee357102ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25646
14534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.2564614534
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.3536724556
Short name T2632
Test name
Test status
Simulation time 199694195 ps
CPU time 0.94 seconds
Started Jul 25 07:07:08 PM PDT 24
Finished Jul 25 07:07:09 PM PDT 24
Peak memory 207108 kb
Host smart-5ae73b5b-972f-4019-870e-3f964bcb71aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35367
24556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.3536724556
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.2502340719
Short name T904
Test name
Test status
Simulation time 283962210 ps
CPU time 0.98 seconds
Started Jul 25 07:07:09 PM PDT 24
Finished Jul 25 07:07:10 PM PDT 24
Peak memory 207136 kb
Host smart-e226d2c7-f8e9-4a13-b3d3-94f113376872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25023
40719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.2502340719
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.3932535274
Short name T2585
Test name
Test status
Simulation time 187088585 ps
CPU time 0.99 seconds
Started Jul 25 07:07:03 PM PDT 24
Finished Jul 25 07:07:04 PM PDT 24
Peak memory 207108 kb
Host smart-ec0e09ad-525d-4509-b602-64a729684fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39325
35274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.3932535274
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.3190482372
Short name T2389
Test name
Test status
Simulation time 144091253 ps
CPU time 0.82 seconds
Started Jul 25 07:07:20 PM PDT 24
Finished Jul 25 07:07:21 PM PDT 24
Peak memory 206960 kb
Host smart-45a080d1-de9d-41d1-8e74-915a9a9f9639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31904
82372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.3190482372
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.1651658020
Short name T2751
Test name
Test status
Simulation time 154491831 ps
CPU time 0.87 seconds
Started Jul 25 07:07:03 PM PDT 24
Finished Jul 25 07:07:04 PM PDT 24
Peak memory 207120 kb
Host smart-2763052c-ddb8-40ec-baf1-5e741b06ba0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16516
58020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.1651658020
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.3304517389
Short name T716
Test name
Test status
Simulation time 156632411 ps
CPU time 0.85 seconds
Started Jul 25 07:07:03 PM PDT 24
Finished Jul 25 07:07:05 PM PDT 24
Peak memory 207100 kb
Host smart-c10568f4-d8a5-40a5-b428-5e4232c2fa7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33045
17389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.3304517389
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.3966251857
Short name T2509
Test name
Test status
Simulation time 265226439 ps
CPU time 1.04 seconds
Started Jul 25 07:07:07 PM PDT 24
Finished Jul 25 07:07:08 PM PDT 24
Peak memory 207208 kb
Host smart-7a252a34-58b5-473e-9123-61b53dc54dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39662
51857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.3966251857
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.3474662453
Short name T1985
Test name
Test status
Simulation time 3335017482 ps
CPU time 100.11 seconds
Started Jul 25 07:07:04 PM PDT 24
Finished Jul 25 07:08:44 PM PDT 24
Peak memory 215520 kb
Host smart-b23705d7-97c1-4a88-bb96-f7682710c72a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3474662453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.3474662453
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.654755690
Short name T1909
Test name
Test status
Simulation time 157423877 ps
CPU time 0.88 seconds
Started Jul 25 07:07:05 PM PDT 24
Finished Jul 25 07:07:06 PM PDT 24
Peak memory 207128 kb
Host smart-e1c3eeb8-12cd-4783-a023-f1b84f6a93d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65475
5690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.654755690
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.1416798724
Short name T1218
Test name
Test status
Simulation time 216629437 ps
CPU time 0.98 seconds
Started Jul 25 07:07:04 PM PDT 24
Finished Jul 25 07:07:05 PM PDT 24
Peak memory 207124 kb
Host smart-2618be08-d10a-49a8-804c-7ed71ff81488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14167
98724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.1416798724
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.3393008468
Short name T2848
Test name
Test status
Simulation time 672177734 ps
CPU time 1.84 seconds
Started Jul 25 07:07:03 PM PDT 24
Finished Jul 25 07:07:05 PM PDT 24
Peak memory 207088 kb
Host smart-5a1feb01-2643-4ec1-95d8-13a2d2c20a1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33930
08468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.3393008468
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.1469368516
Short name T1889
Test name
Test status
Simulation time 4898794173 ps
CPU time 46.79 seconds
Started Jul 25 07:07:20 PM PDT 24
Finished Jul 25 07:08:07 PM PDT 24
Peak memory 207264 kb
Host smart-de76ed77-45ff-4f9d-a48c-606e9ac8be00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14693
68516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.1469368516
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_timeout_missing_host_handshake.754443955
Short name T800
Test name
Test status
Simulation time 5670190362 ps
CPU time 37.15 seconds
Started Jul 25 07:06:59 PM PDT 24
Finished Jul 25 07:07:36 PM PDT 24
Peak memory 207316 kb
Host smart-1774fdbf-61f2-4764-be67-9616a72948c4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754443955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_timeout_missing_host
_handshake.754443955
Directory /workspace/37.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.697866960
Short name T1610
Test name
Test status
Simulation time 55167763 ps
CPU time 0.7 seconds
Started Jul 25 07:07:16 PM PDT 24
Finished Jul 25 07:07:17 PM PDT 24
Peak memory 207180 kb
Host smart-ae887e5c-4328-4ab4-acc1-6e946b218157
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=697866960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.697866960
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.4137780673
Short name T2771
Test name
Test status
Simulation time 3859492879 ps
CPU time 5.51 seconds
Started Jul 25 07:07:06 PM PDT 24
Finished Jul 25 07:07:12 PM PDT 24
Peak memory 207384 kb
Host smart-ec95ff70-b711-4ef0-95a5-bdd14af37c53
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137780673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_a
on_wake_disconnect.4137780673
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.2162301349
Short name T1872
Test name
Test status
Simulation time 13456070320 ps
CPU time 14.99 seconds
Started Jul 25 07:07:07 PM PDT 24
Finished Jul 25 07:07:22 PM PDT 24
Peak memory 207400 kb
Host smart-ab4cbafe-63de-436d-b490-6a62f1a67025
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162301349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.2162301349
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.1863490617
Short name T1371
Test name
Test status
Simulation time 23366733482 ps
CPU time 26.46 seconds
Started Jul 25 07:07:06 PM PDT 24
Finished Jul 25 07:07:33 PM PDT 24
Peak memory 207388 kb
Host smart-15de2d11-c0b7-4294-9e59-4e31e41efbde
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863490617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_a
on_wake_resume.1863490617
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.317355952
Short name T813
Test name
Test status
Simulation time 182689307 ps
CPU time 0.97 seconds
Started Jul 25 07:07:07 PM PDT 24
Finished Jul 25 07:07:08 PM PDT 24
Peak memory 207132 kb
Host smart-328e0d3c-a3d2-438c-8d36-d9fa5f563ea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31735
5952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.317355952
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.2998785330
Short name T1839
Test name
Test status
Simulation time 175885812 ps
CPU time 0.85 seconds
Started Jul 25 07:07:02 PM PDT 24
Finished Jul 25 07:07:03 PM PDT 24
Peak memory 207080 kb
Host smart-5b7ecd1d-fa01-4925-bc29-0c0f8a2d57fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29987
85330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.2998785330
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.1012238046
Short name T596
Test name
Test status
Simulation time 509423895 ps
CPU time 1.55 seconds
Started Jul 25 07:07:09 PM PDT 24
Finished Jul 25 07:07:10 PM PDT 24
Peak memory 207152 kb
Host smart-8442db9d-6c49-4b6a-bbc2-b8ab854e10cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10122
38046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.1012238046
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.808080897
Short name T843
Test name
Test status
Simulation time 1438948733 ps
CPU time 3.61 seconds
Started Jul 25 07:07:07 PM PDT 24
Finished Jul 25 07:07:11 PM PDT 24
Peak memory 207324 kb
Host smart-f8508c9a-1c2f-4244-b8f9-463f841b3c27
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=808080897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.808080897
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.1860335780
Short name T2440
Test name
Test status
Simulation time 11518769686 ps
CPU time 24.09 seconds
Started Jul 25 07:07:10 PM PDT 24
Finished Jul 25 07:07:34 PM PDT 24
Peak memory 207432 kb
Host smart-04a92102-4edd-48fe-a27c-3e203c2703ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18603
35780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.1860335780
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_device_timeout.3564644854
Short name T2082
Test name
Test status
Simulation time 4347392076 ps
CPU time 29.55 seconds
Started Jul 25 07:07:05 PM PDT 24
Finished Jul 25 07:07:35 PM PDT 24
Peak memory 207400 kb
Host smart-58aeb0d3-1cd2-48f0-8903-7e477834d7bf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564644854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_timeout.3564644854
Directory /workspace/38.usbdev_device_timeout/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.2323137822
Short name T2427
Test name
Test status
Simulation time 392353093 ps
CPU time 1.35 seconds
Started Jul 25 07:07:05 PM PDT 24
Finished Jul 25 07:07:07 PM PDT 24
Peak memory 207096 kb
Host smart-6b99f52e-5060-4d7c-8264-1414f6c398ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23231
37822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.2323137822
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.879771691
Short name T2452
Test name
Test status
Simulation time 154759394 ps
CPU time 0.9 seconds
Started Jul 25 07:07:06 PM PDT 24
Finished Jul 25 07:07:07 PM PDT 24
Peak memory 207084 kb
Host smart-a7ebacf7-ea1e-4997-a91d-d2e99808c08e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87977
1691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.879771691
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.2257914192
Short name T440
Test name
Test status
Simulation time 38762040 ps
CPU time 0.68 seconds
Started Jul 25 07:07:07 PM PDT 24
Finished Jul 25 07:07:08 PM PDT 24
Peak memory 207072 kb
Host smart-b9792d08-67bf-44bb-9e32-ce66326f0ebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22579
14192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.2257914192
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.2501644168
Short name T650
Test name
Test status
Simulation time 789590511 ps
CPU time 2.37 seconds
Started Jul 25 07:07:04 PM PDT 24
Finished Jul 25 07:07:06 PM PDT 24
Peak memory 207344 kb
Host smart-de705084-4abf-4499-9822-d4d9157d8fc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25016
44168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.2501644168
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.3718794988
Short name T1426
Test name
Test status
Simulation time 293524179 ps
CPU time 2.38 seconds
Started Jul 25 07:07:08 PM PDT 24
Finished Jul 25 07:07:11 PM PDT 24
Peak memory 207264 kb
Host smart-4923d891-a7b6-4529-994c-d2f69388463d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37187
94988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.3718794988
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.2032628630
Short name T1853
Test name
Test status
Simulation time 181658518 ps
CPU time 0.93 seconds
Started Jul 25 07:07:12 PM PDT 24
Finished Jul 25 07:07:13 PM PDT 24
Peak memory 207148 kb
Host smart-4ff70a62-f194-4b67-994c-b30dbb5b4b16
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2032628630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.2032628630
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.772360456
Short name T1771
Test name
Test status
Simulation time 137438449 ps
CPU time 0.83 seconds
Started Jul 25 07:07:38 PM PDT 24
Finished Jul 25 07:07:39 PM PDT 24
Peak memory 207092 kb
Host smart-b58dae61-77b7-4f31-934b-b2fae9078743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77236
0456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.772360456
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.3669236000
Short name T533
Test name
Test status
Simulation time 245073606 ps
CPU time 1.09 seconds
Started Jul 25 07:07:09 PM PDT 24
Finished Jul 25 07:07:11 PM PDT 24
Peak memory 207140 kb
Host smart-ffe007d3-e076-4b70-895f-e8c7b6e61e6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36692
36000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.3669236000
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.315531024
Short name T1805
Test name
Test status
Simulation time 8244064970 ps
CPU time 63.86 seconds
Started Jul 25 07:07:04 PM PDT 24
Finished Jul 25 07:08:08 PM PDT 24
Peak memory 215488 kb
Host smart-5655ab7e-92b6-40bc-976e-abaefa0b244e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=315531024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.315531024
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_iso_retraction.3270175551
Short name T2809
Test name
Test status
Simulation time 11407307357 ps
CPU time 144.52 seconds
Started Jul 25 07:07:09 PM PDT 24
Finished Jul 25 07:09:34 PM PDT 24
Peak memory 207348 kb
Host smart-cca04f1d-57a2-4403-af50-5802427a94a3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3270175551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_iso_retraction.3270175551
Directory /workspace/38.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.928168298
Short name T530
Test name
Test status
Simulation time 233121235 ps
CPU time 1.02 seconds
Started Jul 25 07:07:32 PM PDT 24
Finished Jul 25 07:07:33 PM PDT 24
Peak memory 207120 kb
Host smart-744cc923-d277-4e2b-9b94-de3074838ad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92816
8298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.928168298
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.2270112516
Short name T2286
Test name
Test status
Simulation time 23336440019 ps
CPU time 30.67 seconds
Started Jul 25 07:07:09 PM PDT 24
Finished Jul 25 07:07:40 PM PDT 24
Peak memory 207380 kb
Host smart-f2ef1544-74f8-4310-8577-c30eda4e5b2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22701
12516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.2270112516
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.3504445184
Short name T567
Test name
Test status
Simulation time 3287999836 ps
CPU time 4.89 seconds
Started Jul 25 07:07:04 PM PDT 24
Finished Jul 25 07:07:09 PM PDT 24
Peak memory 207380 kb
Host smart-671234d9-5e39-4c8d-807a-bba1268ae127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35044
45184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.3504445184
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.509516095
Short name T484
Test name
Test status
Simulation time 5462157271 ps
CPU time 55.33 seconds
Started Jul 25 07:07:22 PM PDT 24
Finished Jul 25 07:08:22 PM PDT 24
Peak memory 217456 kb
Host smart-8f2a69c6-1656-4fc6-be7e-5fbd81ef5628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50951
6095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.509516095
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.3650634959
Short name T1513
Test name
Test status
Simulation time 4622828539 ps
CPU time 134.68 seconds
Started Jul 25 07:07:20 PM PDT 24
Finished Jul 25 07:09:35 PM PDT 24
Peak memory 215368 kb
Host smart-ae424676-3205-4cae-9c40-bf3a0188ca7b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3650634959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.3650634959
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.2475975830
Short name T2167
Test name
Test status
Simulation time 244811685 ps
CPU time 1.02 seconds
Started Jul 25 07:07:10 PM PDT 24
Finished Jul 25 07:07:11 PM PDT 24
Peak memory 207148 kb
Host smart-f5194368-d89e-45f2-8684-15b9c91b6cbd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2475975830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.2475975830
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.3189804081
Short name T1511
Test name
Test status
Simulation time 190199209 ps
CPU time 0.95 seconds
Started Jul 25 07:07:06 PM PDT 24
Finished Jul 25 07:07:07 PM PDT 24
Peak memory 207104 kb
Host smart-51829aa1-5c2a-4c64-a771-6869feb56499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31898
04081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.3189804081
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.4260436943
Short name T925
Test name
Test status
Simulation time 3765015588 ps
CPU time 106.11 seconds
Started Jul 25 07:07:05 PM PDT 24
Finished Jul 25 07:08:52 PM PDT 24
Peak memory 215608 kb
Host smart-3d8763fa-fcfc-4549-9ab5-910be68f1cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42604
36943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.4260436943
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.103779897
Short name T1294
Test name
Test status
Simulation time 3101331475 ps
CPU time 88.53 seconds
Started Jul 25 07:07:20 PM PDT 24
Finished Jul 25 07:08:49 PM PDT 24
Peak memory 215444 kb
Host smart-2b580e26-ff4b-40d8-a414-8c70fd9d25b2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=103779897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.103779897
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.1527786536
Short name T2541
Test name
Test status
Simulation time 157750286 ps
CPU time 0.9 seconds
Started Jul 25 07:07:05 PM PDT 24
Finished Jul 25 07:07:06 PM PDT 24
Peak memory 207152 kb
Host smart-cd8a4753-76ce-4f1f-8bc1-68ba53f1199b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1527786536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.1527786536
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.606459746
Short name T2253
Test name
Test status
Simulation time 148963718 ps
CPU time 0.83 seconds
Started Jul 25 07:07:12 PM PDT 24
Finished Jul 25 07:07:13 PM PDT 24
Peak memory 207120 kb
Host smart-cee3d6f8-544d-4e57-935c-bb95491b2924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60645
9746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.606459746
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.1248345450
Short name T149
Test name
Test status
Simulation time 237584979 ps
CPU time 0.99 seconds
Started Jul 25 07:07:06 PM PDT 24
Finished Jul 25 07:07:07 PM PDT 24
Peak memory 207108 kb
Host smart-b5e49170-0472-411a-bf9e-89ecf530559f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12483
45450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.1248345450
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.2612352944
Short name T889
Test name
Test status
Simulation time 153056233 ps
CPU time 0.83 seconds
Started Jul 25 07:07:20 PM PDT 24
Finished Jul 25 07:07:21 PM PDT 24
Peak memory 206784 kb
Host smart-a7aff50e-439e-4609-b273-4cb970b2fa25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26123
52944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.2612352944
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.1975180588
Short name T1095
Test name
Test status
Simulation time 197335856 ps
CPU time 0.95 seconds
Started Jul 25 07:07:10 PM PDT 24
Finished Jul 25 07:07:11 PM PDT 24
Peak memory 207160 kb
Host smart-66d48e16-0d36-4380-8b6e-d0db38bfd920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19751
80588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.1975180588
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.348067356
Short name T1689
Test name
Test status
Simulation time 196506060 ps
CPU time 0.92 seconds
Started Jul 25 07:07:08 PM PDT 24
Finished Jul 25 07:07:09 PM PDT 24
Peak memory 207148 kb
Host smart-9e63287c-2f2f-4f50-bd2d-cadf68f5a233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34806
7356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.348067356
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.4041928592
Short name T183
Test name
Test status
Simulation time 153765963 ps
CPU time 0.86 seconds
Started Jul 25 07:07:09 PM PDT 24
Finished Jul 25 07:07:10 PM PDT 24
Peak memory 207128 kb
Host smart-0ac35785-d955-4175-a432-3aced0f3ba6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40419
28592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.4041928592
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.234143783
Short name T421
Test name
Test status
Simulation time 216702051 ps
CPU time 0.99 seconds
Started Jul 25 07:07:07 PM PDT 24
Finished Jul 25 07:07:08 PM PDT 24
Peak memory 207120 kb
Host smart-1fdb5866-e1cc-42e2-819f-0eb5aa34bd25
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=234143783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.234143783
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.690307497
Short name T1726
Test name
Test status
Simulation time 147308207 ps
CPU time 0.8 seconds
Started Jul 25 07:07:05 PM PDT 24
Finished Jul 25 07:07:06 PM PDT 24
Peak memory 207096 kb
Host smart-53156ebd-c3bc-4c68-863b-3fb5d9a59abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69030
7497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.690307497
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.456774002
Short name T558
Test name
Test status
Simulation time 56220101 ps
CPU time 0.73 seconds
Started Jul 25 07:07:06 PM PDT 24
Finished Jul 25 07:07:07 PM PDT 24
Peak memory 207060 kb
Host smart-7b55b853-568a-4f0b-aab8-d099dfafcfd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45677
4002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.456774002
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.4121001149
Short name T269
Test name
Test status
Simulation time 6961277625 ps
CPU time 17.79 seconds
Started Jul 25 07:07:06 PM PDT 24
Finished Jul 25 07:07:24 PM PDT 24
Peak memory 215640 kb
Host smart-3cc2de70-b93e-463e-88d1-bd0a919ff8b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41210
01149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.4121001149
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.3529407214
Short name T1518
Test name
Test status
Simulation time 162712488 ps
CPU time 0.91 seconds
Started Jul 25 07:07:08 PM PDT 24
Finished Jul 25 07:07:09 PM PDT 24
Peak memory 207120 kb
Host smart-c054d31d-47d1-4b00-a702-230e9e23498e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35294
07214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.3529407214
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.3457310277
Short name T1544
Test name
Test status
Simulation time 196339876 ps
CPU time 0.94 seconds
Started Jul 25 07:07:08 PM PDT 24
Finished Jul 25 07:07:09 PM PDT 24
Peak memory 207044 kb
Host smart-b525c6d2-2940-46a7-87cb-fb6f9e94255c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34573
10277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.3457310277
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.3458413091
Short name T426
Test name
Test status
Simulation time 178115646 ps
CPU time 0.88 seconds
Started Jul 25 07:07:11 PM PDT 24
Finished Jul 25 07:07:12 PM PDT 24
Peak memory 207152 kb
Host smart-4378ecd8-f829-4f99-b340-8b4ee3cfc4d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34584
13091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.3458413091
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.3464270479
Short name T728
Test name
Test status
Simulation time 184736705 ps
CPU time 0.97 seconds
Started Jul 25 07:07:09 PM PDT 24
Finished Jul 25 07:07:10 PM PDT 24
Peak memory 207152 kb
Host smart-0297d149-7295-445c-886e-6c477ca70b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34642
70479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.3464270479
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.3075805533
Short name T2516
Test name
Test status
Simulation time 164398805 ps
CPU time 0.82 seconds
Started Jul 25 07:07:05 PM PDT 24
Finished Jul 25 07:07:06 PM PDT 24
Peak memory 207064 kb
Host smart-e17c5d28-23cd-474e-b984-720bef5d4373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30758
05533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.3075805533
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.3161003589
Short name T1356
Test name
Test status
Simulation time 198939233 ps
CPU time 0.89 seconds
Started Jul 25 07:07:06 PM PDT 24
Finished Jul 25 07:07:07 PM PDT 24
Peak memory 207064 kb
Host smart-2c7b66c5-2131-4e47-9cb7-bc3a25ffaebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31610
03589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.3161003589
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.1244295945
Short name T2369
Test name
Test status
Simulation time 151702077 ps
CPU time 0.89 seconds
Started Jul 25 07:07:09 PM PDT 24
Finished Jul 25 07:07:10 PM PDT 24
Peak memory 207132 kb
Host smart-6cbbb3c3-fc5b-4012-9dfe-ada9e5ac3f26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12442
95945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.1244295945
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.685837106
Short name T970
Test name
Test status
Simulation time 216895494 ps
CPU time 1.01 seconds
Started Jul 25 07:07:11 PM PDT 24
Finished Jul 25 07:07:12 PM PDT 24
Peak memory 207092 kb
Host smart-64596dc9-33f5-4412-8616-f8689499c5e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68583
7106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.685837106
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.2131925154
Short name T402
Test name
Test status
Simulation time 3699994603 ps
CPU time 106.3 seconds
Started Jul 25 07:07:20 PM PDT 24
Finished Jul 25 07:09:07 PM PDT 24
Peak memory 215444 kb
Host smart-91982251-ea7e-4adf-ab7a-6cd44b31f2d1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2131925154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.2131925154
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.1674060233
Short name T1731
Test name
Test status
Simulation time 201517074 ps
CPU time 0.94 seconds
Started Jul 25 07:07:12 PM PDT 24
Finished Jul 25 07:07:13 PM PDT 24
Peak memory 207156 kb
Host smart-5e1b77b6-14f0-4cfe-a6b6-d938632fda8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16740
60233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.1674060233
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.58306912
Short name T2302
Test name
Test status
Simulation time 215927400 ps
CPU time 0.88 seconds
Started Jul 25 07:07:27 PM PDT 24
Finished Jul 25 07:07:28 PM PDT 24
Peak memory 207152 kb
Host smart-f4db8105-8f0f-4c4c-ae38-68407a9f18f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58306
912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.58306912
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.477853076
Short name T374
Test name
Test status
Simulation time 1119244975 ps
CPU time 2.64 seconds
Started Jul 25 07:07:21 PM PDT 24
Finished Jul 25 07:07:24 PM PDT 24
Peak memory 207344 kb
Host smart-2219ecd4-b5bb-4094-b879-638a2d1a66cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47785
3076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.477853076
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.4291351075
Short name T976
Test name
Test status
Simulation time 3234073059 ps
CPU time 31.14 seconds
Started Jul 25 07:07:12 PM PDT 24
Finished Jul 25 07:07:43 PM PDT 24
Peak memory 215480 kb
Host smart-e5474a2e-9930-41f7-a2c9-2cbc6648fc2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42913
51075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.4291351075
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_timeout_missing_host_handshake.1694825527
Short name T694
Test name
Test status
Simulation time 697815899 ps
CPU time 14.97 seconds
Started Jul 25 07:07:04 PM PDT 24
Finished Jul 25 07:07:19 PM PDT 24
Peak memory 207404 kb
Host smart-12e87421-9c1b-42c8-bcd3-12fe8e7a12b9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694825527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_timeout_missing_hos
t_handshake.1694825527
Directory /workspace/38.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.1671776686
Short name T777
Test name
Test status
Simulation time 130771344 ps
CPU time 0.74 seconds
Started Jul 25 07:07:20 PM PDT 24
Finished Jul 25 07:07:21 PM PDT 24
Peak memory 207172 kb
Host smart-287a6831-d883-4851-88af-234241870202
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1671776686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.1671776686
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.1147905555
Short name T15
Test name
Test status
Simulation time 4264159858 ps
CPU time 6.34 seconds
Started Jul 25 07:07:21 PM PDT 24
Finished Jul 25 07:07:28 PM PDT 24
Peak memory 207404 kb
Host smart-66517b9e-c771-4752-aec9-133887665b03
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147905555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_a
on_wake_disconnect.1147905555
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.809119254
Short name T896
Test name
Test status
Simulation time 13463054660 ps
CPU time 16.29 seconds
Started Jul 25 07:07:13 PM PDT 24
Finished Jul 25 07:07:30 PM PDT 24
Peak memory 207376 kb
Host smart-b268ec3b-4fdb-4e31-bc73-4be2ed292872
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=809119254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.809119254
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.3650366575
Short name T2670
Test name
Test status
Simulation time 23359846635 ps
CPU time 27.87 seconds
Started Jul 25 07:07:08 PM PDT 24
Finished Jul 25 07:07:37 PM PDT 24
Peak memory 207388 kb
Host smart-5afce345-1c1f-4a05-b95a-12b72c1790ef
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650366575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_a
on_wake_resume.3650366575
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.3789035178
Short name T2290
Test name
Test status
Simulation time 150330427 ps
CPU time 0.84 seconds
Started Jul 25 07:07:15 PM PDT 24
Finished Jul 25 07:07:16 PM PDT 24
Peak memory 207112 kb
Host smart-85ea8ef5-49d7-4c3d-b927-a0fea2571d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37890
35178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.3789035178
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.3101796054
Short name T2430
Test name
Test status
Simulation time 162774786 ps
CPU time 0.87 seconds
Started Jul 25 07:07:12 PM PDT 24
Finished Jul 25 07:07:13 PM PDT 24
Peak memory 207088 kb
Host smart-f5b1b34a-c0a2-4c28-863a-6dd5f96a95c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31017
96054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.3101796054
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.4160167215
Short name T2069
Test name
Test status
Simulation time 482777432 ps
CPU time 1.6 seconds
Started Jul 25 07:07:13 PM PDT 24
Finished Jul 25 07:07:15 PM PDT 24
Peak memory 207220 kb
Host smart-7b2e4f47-5886-439c-8d60-d042924f2ead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41601
67215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.4160167215
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.3825181671
Short name T1873
Test name
Test status
Simulation time 1092433776 ps
CPU time 2.7 seconds
Started Jul 25 07:07:11 PM PDT 24
Finished Jul 25 07:07:14 PM PDT 24
Peak memory 207312 kb
Host smart-8f5200c4-596f-4028-b206-3693f8e1fb37
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3825181671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.3825181671
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.2281021652
Short name T1951
Test name
Test status
Simulation time 10555229630 ps
CPU time 22.81 seconds
Started Jul 25 07:07:14 PM PDT 24
Finished Jul 25 07:07:37 PM PDT 24
Peak memory 207380 kb
Host smart-68052444-cfb6-4d67-8e81-e210ea2620cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22810
21652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.2281021652
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_device_timeout.3019730332
Short name T2254
Test name
Test status
Simulation time 2919859751 ps
CPU time 25.61 seconds
Started Jul 25 07:07:30 PM PDT 24
Finished Jul 25 07:07:56 PM PDT 24
Peak memory 207428 kb
Host smart-8ded4561-9828-4f36-828b-958ffb50d80a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019730332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_timeout.3019730332
Directory /workspace/39.usbdev_device_timeout/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.1652011301
Short name T1652
Test name
Test status
Simulation time 431833093 ps
CPU time 1.61 seconds
Started Jul 25 07:07:10 PM PDT 24
Finished Jul 25 07:07:12 PM PDT 24
Peak memory 207056 kb
Host smart-6d00f74a-a7cf-4b8e-befc-d3cd9258a176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16520
11301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.1652011301
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.2439762177
Short name T943
Test name
Test status
Simulation time 141470405 ps
CPU time 0.85 seconds
Started Jul 25 07:07:33 PM PDT 24
Finished Jul 25 07:07:34 PM PDT 24
Peak memory 207120 kb
Host smart-a38a96dc-b8b9-4359-9616-22055f49826d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24397
62177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.2439762177
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.2593630036
Short name T816
Test name
Test status
Simulation time 58371338 ps
CPU time 0.7 seconds
Started Jul 25 07:07:14 PM PDT 24
Finished Jul 25 07:07:20 PM PDT 24
Peak memory 207088 kb
Host smart-1e6a6ccd-f7b8-44f2-928d-801ff1c3d60a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25936
30036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.2593630036
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.2939839066
Short name T973
Test name
Test status
Simulation time 693558544 ps
CPU time 2.17 seconds
Started Jul 25 07:07:27 PM PDT 24
Finished Jul 25 07:07:29 PM PDT 24
Peak memory 207364 kb
Host smart-3e335e69-d462-40ed-b2b0-dec5d7c9aa79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29398
39066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.2939839066
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.3007245873
Short name T2865
Test name
Test status
Simulation time 192413709 ps
CPU time 2.18 seconds
Started Jul 25 07:07:16 PM PDT 24
Finished Jul 25 07:07:18 PM PDT 24
Peak memory 207304 kb
Host smart-05df458b-f176-4e41-9906-3957ddb109dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30072
45873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.3007245873
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.3103855223
Short name T1729
Test name
Test status
Simulation time 225351151 ps
CPU time 1.18 seconds
Started Jul 25 07:07:14 PM PDT 24
Finished Jul 25 07:07:16 PM PDT 24
Peak memory 215508 kb
Host smart-80db3d6b-4f6a-4b85-92c1-9200ee6d2bfb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3103855223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.3103855223
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.1397449336
Short name T929
Test name
Test status
Simulation time 137450073 ps
CPU time 0.82 seconds
Started Jul 25 07:07:13 PM PDT 24
Finished Jul 25 07:07:14 PM PDT 24
Peak memory 207092 kb
Host smart-ac61b141-2353-485c-b492-96c66989faf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13974
49336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.1397449336
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.523252746
Short name T2056
Test name
Test status
Simulation time 275606741 ps
CPU time 0.97 seconds
Started Jul 25 07:07:10 PM PDT 24
Finished Jul 25 07:07:11 PM PDT 24
Peak memory 207140 kb
Host smart-51802840-6ca9-454d-a601-c95cb9ee70d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52325
2746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.523252746
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_invalid_sync.2204039165
Short name T2300
Test name
Test status
Simulation time 4776592000 ps
CPU time 49.94 seconds
Started Jul 25 07:07:10 PM PDT 24
Finished Jul 25 07:08:00 PM PDT 24
Peak memory 217180 kb
Host smart-4e78d126-ed14-43c4-ad4b-9c8f450097a0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2204039165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.2204039165
Directory /workspace/39.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/39.usbdev_iso_retraction.1543271070
Short name T920
Test name
Test status
Simulation time 4886260464 ps
CPU time 34.18 seconds
Started Jul 25 07:07:14 PM PDT 24
Finished Jul 25 07:07:49 PM PDT 24
Peak memory 207336 kb
Host smart-7d78fad4-aeb6-4812-8d66-dba4f10ec0ac
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1543271070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_iso_retraction.1543271070
Directory /workspace/39.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.2411512896
Short name T1040
Test name
Test status
Simulation time 277605145 ps
CPU time 1.07 seconds
Started Jul 25 07:07:12 PM PDT 24
Finished Jul 25 07:07:13 PM PDT 24
Peak memory 207156 kb
Host smart-81f3cfa7-1537-4c69-8a98-75d27aa9422c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24115
12896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.2411512896
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.1756331151
Short name T2267
Test name
Test status
Simulation time 23345169943 ps
CPU time 28.73 seconds
Started Jul 25 07:07:11 PM PDT 24
Finished Jul 25 07:07:40 PM PDT 24
Peak memory 207388 kb
Host smart-32983533-46c8-48cf-8fc9-333eb6f93870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17563
31151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.1756331151
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.218572451
Short name T476
Test name
Test status
Simulation time 3383002212 ps
CPU time 5.04 seconds
Started Jul 25 07:07:20 PM PDT 24
Finished Jul 25 07:07:26 PM PDT 24
Peak memory 207180 kb
Host smart-20280262-1638-40bb-8c58-5120be330d30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21857
2451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.218572451
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.4025392933
Short name T1074
Test name
Test status
Simulation time 8936088621 ps
CPU time 246.97 seconds
Started Jul 25 07:07:21 PM PDT 24
Finished Jul 25 07:11:28 PM PDT 24
Peak memory 215536 kb
Host smart-cd104490-9447-4fe3-9d42-0758a1cea66a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40253
92933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.4025392933
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.526836198
Short name T1858
Test name
Test status
Simulation time 3763517766 ps
CPU time 37.84 seconds
Started Jul 25 07:07:11 PM PDT 24
Finished Jul 25 07:07:49 PM PDT 24
Peak memory 217048 kb
Host smart-b5a2f502-2c62-457a-84d7-9d6d3e4c522b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=526836198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.526836198
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.3504689134
Short name T615
Test name
Test status
Simulation time 238912421 ps
CPU time 0.99 seconds
Started Jul 25 07:07:09 PM PDT 24
Finished Jul 25 07:07:11 PM PDT 24
Peak memory 207144 kb
Host smart-9b3dd678-1423-4621-a69f-1bfb4bb3b2cd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3504689134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.3504689134
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.1977198392
Short name T2173
Test name
Test status
Simulation time 190122997 ps
CPU time 0.88 seconds
Started Jul 25 07:07:11 PM PDT 24
Finished Jul 25 07:07:13 PM PDT 24
Peak memory 207112 kb
Host smart-1b20205e-3192-44a3-8c14-ea2103b823fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19771
98392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.1977198392
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.2148389313
Short name T2207
Test name
Test status
Simulation time 5696722138 ps
CPU time 60.08 seconds
Started Jul 25 07:07:11 PM PDT 24
Finished Jul 25 07:08:11 PM PDT 24
Peak memory 216728 kb
Host smart-b691e2a7-a8cb-406e-a406-a7d83063b19e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21483
89313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.2148389313
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.3785207626
Short name T1768
Test name
Test status
Simulation time 5644246260 ps
CPU time 55.2 seconds
Started Jul 25 07:07:12 PM PDT 24
Finished Jul 25 07:08:07 PM PDT 24
Peak memory 207512 kb
Host smart-f8ee37e1-ce6f-4609-a9d2-584e8599214f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3785207626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.3785207626
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.2344361940
Short name T1016
Test name
Test status
Simulation time 163229853 ps
CPU time 0.85 seconds
Started Jul 25 07:07:13 PM PDT 24
Finished Jul 25 07:07:14 PM PDT 24
Peak memory 207184 kb
Host smart-9f0d9289-3642-4aa8-ae0e-f54633ff3d85
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2344361940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.2344361940
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.393974998
Short name T2284
Test name
Test status
Simulation time 191512063 ps
CPU time 0.89 seconds
Started Jul 25 07:07:22 PM PDT 24
Finished Jul 25 07:07:23 PM PDT 24
Peak memory 207124 kb
Host smart-d3e46294-c6e2-4874-8c98-07cc7951092c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39397
4998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.393974998
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.1063567101
Short name T161
Test name
Test status
Simulation time 237321548 ps
CPU time 1.01 seconds
Started Jul 25 07:07:13 PM PDT 24
Finished Jul 25 07:07:14 PM PDT 24
Peak memory 207032 kb
Host smart-09db7a70-60d4-4bff-afec-2d7b7bc60f16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10635
67101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.1063567101
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.2340526496
Short name T1383
Test name
Test status
Simulation time 184360598 ps
CPU time 0.89 seconds
Started Jul 25 07:07:10 PM PDT 24
Finished Jul 25 07:07:11 PM PDT 24
Peak memory 207104 kb
Host smart-b5ac5fb9-ca2d-4488-ad0c-9a16faa29fbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23405
26496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.2340526496
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.54780648
Short name T2121
Test name
Test status
Simulation time 161912923 ps
CPU time 0.86 seconds
Started Jul 25 07:07:11 PM PDT 24
Finished Jul 25 07:07:13 PM PDT 24
Peak memory 207116 kb
Host smart-44469d4e-44a9-4831-b27a-e62aea4d9ab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54780
648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.54780648
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.1843064366
Short name T2134
Test name
Test status
Simulation time 199444954 ps
CPU time 0.91 seconds
Started Jul 25 07:07:12 PM PDT 24
Finished Jul 25 07:07:14 PM PDT 24
Peak memory 207196 kb
Host smart-c323e83b-3739-4fb4-bd7c-8ba6c7ec8114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18430
64366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.1843064366
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.966398335
Short name T1121
Test name
Test status
Simulation time 153684050 ps
CPU time 0.89 seconds
Started Jul 25 07:07:13 PM PDT 24
Finished Jul 25 07:07:14 PM PDT 24
Peak memory 207224 kb
Host smart-43faa596-0c0c-400c-87ce-39ed05663718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96639
8335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.966398335
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.2845967060
Short name T1761
Test name
Test status
Simulation time 208577909 ps
CPU time 0.94 seconds
Started Jul 25 07:07:21 PM PDT 24
Finished Jul 25 07:07:22 PM PDT 24
Peak memory 207152 kb
Host smart-958cfcf0-5f4e-4858-9ae3-040a04e74b1d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2845967060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.2845967060
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.1992905492
Short name T969
Test name
Test status
Simulation time 164730724 ps
CPU time 0.83 seconds
Started Jul 25 07:07:26 PM PDT 24
Finished Jul 25 07:07:27 PM PDT 24
Peak memory 207140 kb
Host smart-e5993028-bb02-4e93-8ca0-c0eb8f77467a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19929
05492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.1992905492
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.3626134046
Short name T1306
Test name
Test status
Simulation time 54134612 ps
CPU time 0.72 seconds
Started Jul 25 07:07:12 PM PDT 24
Finished Jul 25 07:07:13 PM PDT 24
Peak memory 207112 kb
Host smart-ca1e83c0-29a0-4d20-b908-1e505c17d2bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36261
34046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.3626134046
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.1636911814
Short name T2523
Test name
Test status
Simulation time 10330564248 ps
CPU time 26.12 seconds
Started Jul 25 07:07:12 PM PDT 24
Finished Jul 25 07:07:39 PM PDT 24
Peak memory 215588 kb
Host smart-f7b08ec3-45a1-4d42-b6b6-79e9db163cc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16369
11814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.1636911814
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.2873361461
Short name T1377
Test name
Test status
Simulation time 156089392 ps
CPU time 0.84 seconds
Started Jul 25 07:07:13 PM PDT 24
Finished Jul 25 07:07:14 PM PDT 24
Peak memory 207016 kb
Host smart-71fbd6fd-ee45-4b4a-ad76-8b8f7643c99a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28733
61461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.2873361461
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.939114921
Short name T1172
Test name
Test status
Simulation time 216711664 ps
CPU time 0.93 seconds
Started Jul 25 07:07:13 PM PDT 24
Finished Jul 25 07:07:14 PM PDT 24
Peak memory 207084 kb
Host smart-939fb912-25e4-4686-8c7a-c606cd0e3e51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93911
4921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.939114921
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.516867315
Short name T972
Test name
Test status
Simulation time 250281894 ps
CPU time 1.03 seconds
Started Jul 25 07:07:12 PM PDT 24
Finished Jul 25 07:07:13 PM PDT 24
Peak memory 207156 kb
Host smart-bcba9fd5-eacd-4585-b89f-7190a7d2b5fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51686
7315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.516867315
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.2809422258
Short name T2247
Test name
Test status
Simulation time 251926514 ps
CPU time 1 seconds
Started Jul 25 07:07:11 PM PDT 24
Finished Jul 25 07:07:13 PM PDT 24
Peak memory 207160 kb
Host smart-20bab46f-0ec4-41b6-ab1e-64e95303300b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28094
22258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.2809422258
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.3130353289
Short name T2857
Test name
Test status
Simulation time 161984283 ps
CPU time 0.87 seconds
Started Jul 25 07:07:30 PM PDT 24
Finished Jul 25 07:07:31 PM PDT 24
Peak memory 207152 kb
Host smart-a98fa995-6a67-47db-afaf-a787247495b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31303
53289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.3130353289
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.3327599644
Short name T349
Test name
Test status
Simulation time 157844745 ps
CPU time 0.94 seconds
Started Jul 25 07:07:15 PM PDT 24
Finished Jul 25 07:07:16 PM PDT 24
Peak memory 207156 kb
Host smart-7769ef74-42b0-4234-b257-46e66341af79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33275
99644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.3327599644
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.3332142147
Short name T265
Test name
Test status
Simulation time 205638228 ps
CPU time 0.9 seconds
Started Jul 25 07:07:22 PM PDT 24
Finished Jul 25 07:07:23 PM PDT 24
Peak memory 206924 kb
Host smart-482ac2cf-ea03-4c42-a1c4-a07e2d4fb6d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33321
42147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.3332142147
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.3791596232
Short name T1536
Test name
Test status
Simulation time 200751248 ps
CPU time 1.06 seconds
Started Jul 25 07:07:22 PM PDT 24
Finished Jul 25 07:07:23 PM PDT 24
Peak memory 206968 kb
Host smart-0007de67-c4a7-4f47-af26-4de770c02c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37915
96232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.3791596232
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.1652619621
Short name T2768
Test name
Test status
Simulation time 3490331549 ps
CPU time 35.65 seconds
Started Jul 25 07:07:15 PM PDT 24
Finished Jul 25 07:07:51 PM PDT 24
Peak memory 215580 kb
Host smart-84c96611-5477-4ae7-bc6b-491a718ee77c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1652619621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.1652619621
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.2139259352
Short name T2115
Test name
Test status
Simulation time 191310348 ps
CPU time 0.91 seconds
Started Jul 25 07:07:21 PM PDT 24
Finished Jul 25 07:07:22 PM PDT 24
Peak memory 207148 kb
Host smart-782881ee-be2d-435c-8701-2a8edd651872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21392
59352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.2139259352
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.3758208060
Short name T2614
Test name
Test status
Simulation time 192764365 ps
CPU time 1.1 seconds
Started Jul 25 07:07:23 PM PDT 24
Finished Jul 25 07:07:25 PM PDT 24
Peak memory 207116 kb
Host smart-1f60621e-f090-453b-bcfd-295ad87f2595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37582
08060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.3758208060
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.1475080161
Short name T602
Test name
Test status
Simulation time 605172780 ps
CPU time 1.7 seconds
Started Jul 25 07:07:19 PM PDT 24
Finished Jul 25 07:07:21 PM PDT 24
Peak memory 207100 kb
Host smart-479c51c6-07ae-4747-bc0c-e83f3ab20739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14750
80161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.1475080161
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.881579479
Short name T2445
Test name
Test status
Simulation time 4499509198 ps
CPU time 134.53 seconds
Started Jul 25 07:07:16 PM PDT 24
Finished Jul 25 07:09:31 PM PDT 24
Peak memory 215576 kb
Host smart-d71f2b5c-449c-4b48-9a40-4585e90cc68c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88157
9479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.881579479
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_timeout_missing_host_handshake.4066743783
Short name T2200
Test name
Test status
Simulation time 2952286019 ps
CPU time 26.11 seconds
Started Jul 25 07:07:10 PM PDT 24
Finished Jul 25 07:07:36 PM PDT 24
Peak memory 207316 kb
Host smart-d40c7020-8e99-4fd9-8450-f45d7fcb223f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066743783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_timeout_missing_hos
t_handshake.4066743783
Directory /workspace/39.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.3759252652
Short name T706
Test name
Test status
Simulation time 45240010 ps
CPU time 0.68 seconds
Started Jul 25 07:01:28 PM PDT 24
Finished Jul 25 07:01:29 PM PDT 24
Peak memory 207188 kb
Host smart-2dcafa65-4a99-44fb-b42a-347026f29da8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3759252652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.3759252652
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.4067397727
Short name T2364
Test name
Test status
Simulation time 3675043388 ps
CPU time 5.99 seconds
Started Jul 25 07:01:11 PM PDT 24
Finished Jul 25 07:01:17 PM PDT 24
Peak memory 207400 kb
Host smart-26409def-3f10-4c03-82f0-1cbd95ffd7c2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067397727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ao
n_wake_disconnect.4067397727
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.1012594692
Short name T957
Test name
Test status
Simulation time 13407088556 ps
CPU time 17.23 seconds
Started Jul 25 07:01:13 PM PDT 24
Finished Jul 25 07:01:30 PM PDT 24
Peak memory 207400 kb
Host smart-86a79310-c7bd-40e0-9d7d-ab017a5918b5
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012594692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.1012594692
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.213001314
Short name T2213
Test name
Test status
Simulation time 23350132368 ps
CPU time 29.41 seconds
Started Jul 25 07:01:14 PM PDT 24
Finished Jul 25 07:01:44 PM PDT 24
Peak memory 207388 kb
Host smart-eb84fa03-0719-4a78-ab84-49636b95135c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213001314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon
_wake_resume.213001314
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.2199598489
Short name T1027
Test name
Test status
Simulation time 157996880 ps
CPU time 0.86 seconds
Started Jul 25 07:01:14 PM PDT 24
Finished Jul 25 07:01:15 PM PDT 24
Peak memory 207144 kb
Host smart-30cd689a-f9e1-4a0c-bf97-acf0bea9ec9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21995
98489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.2199598489
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.2798530320
Short name T2017
Test name
Test status
Simulation time 195305016 ps
CPU time 0.95 seconds
Started Jul 25 07:01:13 PM PDT 24
Finished Jul 25 07:01:14 PM PDT 24
Peak memory 207120 kb
Host smart-ff122cb5-da69-4fd3-bfdb-da9e6f8b2bb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27985
30320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.2798530320
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.2833090032
Short name T116
Test name
Test status
Simulation time 138449809 ps
CPU time 0.81 seconds
Started Jul 25 07:01:13 PM PDT 24
Finished Jul 25 07:01:14 PM PDT 24
Peak memory 207100 kb
Host smart-e8d76819-1ae3-4932-be1b-3e5833a53cd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28330
90032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.2833090032
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.1058179448
Short name T1580
Test name
Test status
Simulation time 142298619 ps
CPU time 0.84 seconds
Started Jul 25 07:01:13 PM PDT 24
Finished Jul 25 07:01:14 PM PDT 24
Peak memory 207092 kb
Host smart-3e3a4877-8283-4da1-bb82-6bb7843e76c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10581
79448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.1058179448
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.1214446697
Short name T1933
Test name
Test status
Simulation time 346350871 ps
CPU time 1.33 seconds
Started Jul 25 07:01:11 PM PDT 24
Finished Jul 25 07:01:12 PM PDT 24
Peak memory 207136 kb
Host smart-41f0df70-d311-4df3-a0be-ae805c2f6b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12144
46697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.1214446697
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.1652473040
Short name T2762
Test name
Test status
Simulation time 795286472 ps
CPU time 2.08 seconds
Started Jul 25 07:01:11 PM PDT 24
Finished Jul 25 07:01:13 PM PDT 24
Peak memory 207152 kb
Host smart-4d1f0ad5-8874-4396-8990-cf3b4ceb4097
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1652473040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.1652473040
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.1369317352
Short name T2049
Test name
Test status
Simulation time 19737763233 ps
CPU time 44.05 seconds
Started Jul 25 07:01:12 PM PDT 24
Finished Jul 25 07:01:56 PM PDT 24
Peak memory 207412 kb
Host smart-1e61dcbf-2573-4679-8bae-03c79a9fc380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13693
17352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.1369317352
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_device_timeout.4193482893
Short name T380
Test name
Test status
Simulation time 1047260356 ps
CPU time 21.04 seconds
Started Jul 25 07:01:13 PM PDT 24
Finished Jul 25 07:01:34 PM PDT 24
Peak memory 207344 kb
Host smart-953e9a46-8d8f-44a8-9f11-916413131f87
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193482893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_timeout.4193482893
Directory /workspace/4.usbdev_device_timeout/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.1878705198
Short name T93
Test name
Test status
Simulation time 323766839 ps
CPU time 1.33 seconds
Started Jul 25 07:01:19 PM PDT 24
Finished Jul 25 07:01:20 PM PDT 24
Peak memory 207128 kb
Host smart-51666fd1-2866-4837-9607-3fa69d7fa8ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18787
05198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.1878705198
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.2534955069
Short name T1484
Test name
Test status
Simulation time 135134302 ps
CPU time 0.87 seconds
Started Jul 25 07:01:18 PM PDT 24
Finished Jul 25 07:01:19 PM PDT 24
Peak memory 207120 kb
Host smart-1397ac0a-c2c8-4847-a3b6-6be90ad97701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25349
55069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.2534955069
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.1714250655
Short name T2666
Test name
Test status
Simulation time 36606428 ps
CPU time 0.73 seconds
Started Jul 25 07:01:20 PM PDT 24
Finished Jul 25 07:01:21 PM PDT 24
Peak memory 207084 kb
Host smart-84072654-507e-4d3d-9cbf-a0048270c187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17142
50655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.1714250655
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.1307635042
Short name T2506
Test name
Test status
Simulation time 845496190 ps
CPU time 2.41 seconds
Started Jul 25 07:01:19 PM PDT 24
Finished Jul 25 07:01:21 PM PDT 24
Peak memory 207356 kb
Host smart-bdb0ed38-5a85-431c-92f6-36aeef8bbbc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13076
35042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.1307635042
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.3705286141
Short name T1554
Test name
Test status
Simulation time 195371741 ps
CPU time 1.75 seconds
Started Jul 25 07:01:21 PM PDT 24
Finished Jul 25 07:01:23 PM PDT 24
Peak memory 207308 kb
Host smart-f86fa7b1-1f39-4e4a-920d-68529415779c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37052
86141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.3705286141
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.2654224558
Short name T344
Test name
Test status
Simulation time 110182441149 ps
CPU time 178.22 seconds
Started Jul 25 07:01:17 PM PDT 24
Finished Jul 25 07:04:16 PM PDT 24
Peak memory 207440 kb
Host smart-7e61556e-9acd-411f-a3ee-e2b4ad7cae76
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2654224558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.2654224558
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.3533135793
Short name T341
Test name
Test status
Simulation time 118431950537 ps
CPU time 229.54 seconds
Started Jul 25 07:01:16 PM PDT 24
Finished Jul 25 07:05:06 PM PDT 24
Peak memory 207392 kb
Host smart-61adbfda-7b94-4650-bd95-ebc914722335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533135793 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.3533135793
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.1910144333
Short name T2564
Test name
Test status
Simulation time 104099996559 ps
CPU time 180.38 seconds
Started Jul 25 07:01:20 PM PDT 24
Finished Jul 25 07:04:20 PM PDT 24
Peak memory 207352 kb
Host smart-b0c2372b-d61d-493e-81cd-60a8461cbe71
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1910144333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.1910144333
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.3309300494
Short name T342
Test name
Test status
Simulation time 97072573157 ps
CPU time 157.39 seconds
Started Jul 25 07:01:18 PM PDT 24
Finished Jul 25 07:03:56 PM PDT 24
Peak memory 207404 kb
Host smart-e30938d0-b6b7-4a9c-8d1b-ed96ce08beb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309300494 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.3309300494
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.3819663201
Short name T961
Test name
Test status
Simulation time 108183174995 ps
CPU time 180.66 seconds
Started Jul 25 07:01:20 PM PDT 24
Finished Jul 25 07:04:21 PM PDT 24
Peak memory 207392 kb
Host smart-1b89d4c5-b58e-46fc-9113-201e18126122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38196
63201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.3819663201
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.759933606
Short name T1739
Test name
Test status
Simulation time 284944763 ps
CPU time 1.24 seconds
Started Jul 25 07:01:18 PM PDT 24
Finished Jul 25 07:01:19 PM PDT 24
Peak memory 215616 kb
Host smart-b8eefe27-b4c0-4f82-b814-6119b391ad5c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=759933606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.759933606
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.3537511146
Short name T2375
Test name
Test status
Simulation time 207674980 ps
CPU time 0.88 seconds
Started Jul 25 07:01:19 PM PDT 24
Finished Jul 25 07:01:20 PM PDT 24
Peak memory 207092 kb
Host smart-ccde670d-b3c3-4f3e-b88a-118c43702026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35375
11146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.3537511146
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.3119649506
Short name T1636
Test name
Test status
Simulation time 245424247 ps
CPU time 1.07 seconds
Started Jul 25 07:01:21 PM PDT 24
Finished Jul 25 07:01:22 PM PDT 24
Peak memory 207068 kb
Host smart-86ac80e4-e03f-4a0c-b909-1811212aa5e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31196
49506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.3119649506
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_invalid_sync.429410639
Short name T1999
Test name
Test status
Simulation time 7183661593 ps
CPU time 68.52 seconds
Started Jul 25 07:01:18 PM PDT 24
Finished Jul 25 07:02:27 PM PDT 24
Peak memory 215560 kb
Host smart-0757fb48-2ddf-44c8-a645-a4a8e72fc3b8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=429410639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.429410639
Directory /workspace/4.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/4.usbdev_iso_retraction.2475046720
Short name T1012
Test name
Test status
Simulation time 5899843433 ps
CPU time 43.17 seconds
Started Jul 25 07:01:21 PM PDT 24
Finished Jul 25 07:02:04 PM PDT 24
Peak memory 207312 kb
Host smart-02fe69cc-68b5-4bc8-82fd-bef3d97bd888
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2475046720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.2475046720
Directory /workspace/4.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.3732160631
Short name T1791
Test name
Test status
Simulation time 240228718 ps
CPU time 1.01 seconds
Started Jul 25 07:01:18 PM PDT 24
Finished Jul 25 07:01:19 PM PDT 24
Peak memory 207128 kb
Host smart-c3501d90-3549-4541-aa3e-d8f5f0b0afb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37321
60631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.3732160631
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.2694457169
Short name T1150
Test name
Test status
Simulation time 23275002252 ps
CPU time 27.25 seconds
Started Jul 25 07:01:18 PM PDT 24
Finished Jul 25 07:01:46 PM PDT 24
Peak memory 207336 kb
Host smart-6225a27f-c7d8-4500-9cbf-43d4b3f460c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26944
57169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.2694457169
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.865920054
Short name T527
Test name
Test status
Simulation time 3284543412 ps
CPU time 5.4 seconds
Started Jul 25 07:01:17 PM PDT 24
Finished Jul 25 07:01:23 PM PDT 24
Peak memory 207336 kb
Host smart-548ac368-f8ab-42d0-98c6-78073c0319db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86592
0054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.865920054
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.2805852619
Short name T2278
Test name
Test status
Simulation time 7387979511 ps
CPU time 51.94 seconds
Started Jul 25 07:01:25 PM PDT 24
Finished Jul 25 07:02:17 PM PDT 24
Peak memory 223740 kb
Host smart-2ce9e805-1d8c-4da1-8e28-6753fd1c4dbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28058
52619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.2805852619
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.2547032792
Short name T2683
Test name
Test status
Simulation time 7061805320 ps
CPU time 57.5 seconds
Started Jul 25 07:01:21 PM PDT 24
Finished Jul 25 07:02:19 PM PDT 24
Peak memory 207412 kb
Host smart-22c945bd-5d35-4212-9a03-aa96ef2382c1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2547032792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.2547032792
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.493399968
Short name T2102
Test name
Test status
Simulation time 268330739 ps
CPU time 1.11 seconds
Started Jul 25 07:01:26 PM PDT 24
Finished Jul 25 07:01:27 PM PDT 24
Peak memory 207128 kb
Host smart-6f703e55-8fc4-428c-bce7-80195e31bccc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=493399968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.493399968
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.1093458333
Short name T880
Test name
Test status
Simulation time 198806310 ps
CPU time 0.94 seconds
Started Jul 25 07:01:26 PM PDT 24
Finished Jul 25 07:01:27 PM PDT 24
Peak memory 207104 kb
Host smart-8a3e6d98-c4c3-44fc-98cd-d214f8135d1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10934
58333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.1093458333
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.1146085755
Short name T2458
Test name
Test status
Simulation time 4488204262 ps
CPU time 130.09 seconds
Started Jul 25 07:01:21 PM PDT 24
Finished Jul 25 07:03:31 PM PDT 24
Peak memory 215528 kb
Host smart-7ca249fd-45a4-4cbd-82b1-f96de4daf42a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11460
85755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.1146085755
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.3815257827
Short name T815
Test name
Test status
Simulation time 3728866224 ps
CPU time 103.73 seconds
Started Jul 25 07:01:18 PM PDT 24
Finished Jul 25 07:03:02 PM PDT 24
Peak memory 215616 kb
Host smart-106d5ddd-1bdc-48ca-8da4-7f73be7badd3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3815257827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.3815257827
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.807614972
Short name T2634
Test name
Test status
Simulation time 156065739 ps
CPU time 0.86 seconds
Started Jul 25 07:01:22 PM PDT 24
Finished Jul 25 07:01:23 PM PDT 24
Peak memory 207180 kb
Host smart-7363f391-d556-403e-9157-11b4bdbb0267
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=807614972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.807614972
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.1803120578
Short name T1082
Test name
Test status
Simulation time 172141360 ps
CPU time 0.86 seconds
Started Jul 25 07:01:19 PM PDT 24
Finished Jul 25 07:01:20 PM PDT 24
Peak memory 207064 kb
Host smart-19d8e3d9-b839-4110-9b90-1d7519678619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18031
20578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.1803120578
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.213655265
Short name T152
Test name
Test status
Simulation time 185689900 ps
CPU time 0.92 seconds
Started Jul 25 07:01:19 PM PDT 24
Finished Jul 25 07:01:20 PM PDT 24
Peak memory 207100 kb
Host smart-d56e9260-8192-4e66-8485-5b8ed9208748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21365
5265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.213655265
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.1871067769
Short name T1695
Test name
Test status
Simulation time 166615911 ps
CPU time 0.85 seconds
Started Jul 25 07:01:19 PM PDT 24
Finished Jul 25 07:01:20 PM PDT 24
Peak memory 207092 kb
Host smart-c652c381-0564-417f-83cb-369016814b3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18710
67769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.1871067769
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.3883858848
Short name T654
Test name
Test status
Simulation time 216392190 ps
CPU time 0.93 seconds
Started Jul 25 07:01:18 PM PDT 24
Finished Jul 25 07:01:19 PM PDT 24
Peak memory 207160 kb
Host smart-7d30e2e7-8a8f-4aee-8505-6f96bcad981f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38838
58848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.3883858848
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.1366943014
Short name T414
Test name
Test status
Simulation time 178249261 ps
CPU time 0.85 seconds
Started Jul 25 07:01:25 PM PDT 24
Finished Jul 25 07:01:26 PM PDT 24
Peak memory 207108 kb
Host smart-c807cd45-ade8-4196-b5d1-94d29bf7cb2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13669
43014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.1366943014
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.2742061571
Short name T1050
Test name
Test status
Simulation time 151612997 ps
CPU time 0.85 seconds
Started Jul 25 07:01:17 PM PDT 24
Finished Jul 25 07:01:18 PM PDT 24
Peak memory 207152 kb
Host smart-076f24db-8626-4b7e-acdb-f9b74774fcc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27420
61571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.2742061571
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.4210151862
Short name T1051
Test name
Test status
Simulation time 248061543 ps
CPU time 1.14 seconds
Started Jul 25 07:01:26 PM PDT 24
Finished Jul 25 07:01:27 PM PDT 24
Peak memory 207132 kb
Host smart-ee3fe8bb-bc01-406e-8b43-8bb9f8151acc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4210151862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.4210151862
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.1766759665
Short name T2105
Test name
Test status
Simulation time 185248573 ps
CPU time 0.91 seconds
Started Jul 25 07:01:22 PM PDT 24
Finished Jul 25 07:01:23 PM PDT 24
Peak memory 207112 kb
Host smart-98ee3a29-65e7-4318-9510-d0a25025480d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17667
59665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.1766759665
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.348319940
Short name T895
Test name
Test status
Simulation time 86574389 ps
CPU time 0.74 seconds
Started Jul 25 07:01:26 PM PDT 24
Finished Jul 25 07:01:27 PM PDT 24
Peak memory 207072 kb
Host smart-7f68020c-0dc1-4dc6-b839-91223bd22558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34831
9940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.348319940
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.4235525308
Short name T270
Test name
Test status
Simulation time 9792948156 ps
CPU time 26.39 seconds
Started Jul 25 07:01:21 PM PDT 24
Finished Jul 25 07:01:47 PM PDT 24
Peak memory 215564 kb
Host smart-97ca6f64-e109-42a0-b2a8-ce8f154e439e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42355
25308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.4235525308
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.3106650775
Short name T1186
Test name
Test status
Simulation time 240188311 ps
CPU time 0.97 seconds
Started Jul 25 07:01:19 PM PDT 24
Finished Jul 25 07:01:20 PM PDT 24
Peak memory 207096 kb
Host smart-8085c4ce-6f13-4947-b156-3cbbef7a3781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31066
50775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.3106650775
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.2947859965
Short name T2035
Test name
Test status
Simulation time 252117636 ps
CPU time 1.02 seconds
Started Jul 25 07:01:22 PM PDT 24
Finished Jul 25 07:01:23 PM PDT 24
Peak memory 207124 kb
Host smart-0a4f975a-5886-4fa6-b8db-6e83e07a4217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29478
59965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.2947859965
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.768679249
Short name T1709
Test name
Test status
Simulation time 10066978235 ps
CPU time 71.39 seconds
Started Jul 25 07:01:26 PM PDT 24
Finished Jul 25 07:02:38 PM PDT 24
Peak memory 217764 kb
Host smart-a52d17f4-a820-4680-b46e-bf807c2d1c1d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=768679249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.768679249
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.2298185471
Short name T2643
Test name
Test status
Simulation time 18808673979 ps
CPU time 445.86 seconds
Started Jul 25 07:01:28 PM PDT 24
Finished Jul 25 07:08:54 PM PDT 24
Peak memory 215628 kb
Host smart-7e639525-9f54-453e-927c-e8cf2a95e02b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298185471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.2298185471
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.1087385860
Short name T762
Test name
Test status
Simulation time 222050936 ps
CPU time 0.95 seconds
Started Jul 25 07:01:22 PM PDT 24
Finished Jul 25 07:01:23 PM PDT 24
Peak memory 207152 kb
Host smart-a0ca5edf-b812-4871-96b8-13cbf56f1c1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10873
85860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.1087385860
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.2397725781
Short name T350
Test name
Test status
Simulation time 193489976 ps
CPU time 0.92 seconds
Started Jul 25 07:01:20 PM PDT 24
Finished Jul 25 07:01:21 PM PDT 24
Peak memory 207116 kb
Host smart-f76b44a1-5fec-4ea7-b5a3-7cd4829eea2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23977
25781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.2397725781
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.1698671338
Short name T2578
Test name
Test status
Simulation time 148647568 ps
CPU time 0.81 seconds
Started Jul 25 07:01:27 PM PDT 24
Finished Jul 25 07:01:28 PM PDT 24
Peak memory 207088 kb
Host smart-2866904b-207d-4c54-98b1-b9d53fd297bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16986
71338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.1698671338
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.404758902
Short name T2367
Test name
Test status
Simulation time 204748371 ps
CPU time 0.89 seconds
Started Jul 25 07:01:29 PM PDT 24
Finished Jul 25 07:01:30 PM PDT 24
Peak memory 207168 kb
Host smart-c38fc30d-f7d8-476d-9f48-9aa2f20c7ca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40475
8902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.404758902
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.2971337013
Short name T227
Test name
Test status
Simulation time 1427062699 ps
CPU time 2.47 seconds
Started Jul 25 07:01:28 PM PDT 24
Finished Jul 25 07:01:30 PM PDT 24
Peak memory 223884 kb
Host smart-1ed8c031-23b3-402d-a311-02a8ef82694e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2971337013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.2971337013
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.315432726
Short name T189
Test name
Test status
Simulation time 331249814 ps
CPU time 1.09 seconds
Started Jul 25 07:01:31 PM PDT 24
Finished Jul 25 07:01:32 PM PDT 24
Peak memory 207128 kb
Host smart-898e37e2-a7d8-43d5-96bd-4ac22b8beb73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31543
2726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.315432726
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.589307898
Short name T1264
Test name
Test status
Simulation time 188389118 ps
CPU time 0.89 seconds
Started Jul 25 07:01:28 PM PDT 24
Finished Jul 25 07:01:29 PM PDT 24
Peak memory 207072 kb
Host smart-1b33fb0d-88f9-485b-ad48-0fa222c0b3f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58930
7898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.589307898
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.2326782275
Short name T2131
Test name
Test status
Simulation time 147808237 ps
CPU time 0.89 seconds
Started Jul 25 07:01:28 PM PDT 24
Finished Jul 25 07:01:29 PM PDT 24
Peak memory 207124 kb
Host smart-702d08df-81cd-4dd4-9ee8-ef1e14d06789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23267
82275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.2326782275
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.708242947
Short name T2073
Test name
Test status
Simulation time 212003695 ps
CPU time 1 seconds
Started Jul 25 07:01:37 PM PDT 24
Finished Jul 25 07:01:38 PM PDT 24
Peak memory 207144 kb
Host smart-9596dd9e-c6f6-4d3d-8ea9-73d0de7a5bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70824
2947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.708242947
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.1828624413
Short name T2045
Test name
Test status
Simulation time 3918641343 ps
CPU time 39.25 seconds
Started Jul 25 07:01:24 PM PDT 24
Finished Jul 25 07:02:04 PM PDT 24
Peak memory 215708 kb
Host smart-68bef743-87fd-4365-a57c-b3ec3624d005
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1828624413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.1828624413
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.77100592
Short name T897
Test name
Test status
Simulation time 141803083 ps
CPU time 0.84 seconds
Started Jul 25 07:01:25 PM PDT 24
Finished Jul 25 07:01:26 PM PDT 24
Peak memory 207112 kb
Host smart-023d0861-e21d-4694-8d41-db357c895416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77100
592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.77100592
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.3161615489
Short name T1863
Test name
Test status
Simulation time 159020100 ps
CPU time 0.84 seconds
Started Jul 25 07:01:27 PM PDT 24
Finished Jul 25 07:01:28 PM PDT 24
Peak memory 207124 kb
Host smart-826d0597-213a-40e7-b119-272cdaf58e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31616
15489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.3161615489
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.712177896
Short name T352
Test name
Test status
Simulation time 818489420 ps
CPU time 2.3 seconds
Started Jul 25 07:01:27 PM PDT 24
Finished Jul 25 07:01:30 PM PDT 24
Peak memory 207284 kb
Host smart-012ccf6b-1e33-4fe9-beff-2de75c8498fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71217
7896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.712177896
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.1563060614
Short name T489
Test name
Test status
Simulation time 5531688335 ps
CPU time 161.3 seconds
Started Jul 25 07:01:36 PM PDT 24
Finished Jul 25 07:04:18 PM PDT 24
Peak memory 215612 kb
Host smart-e4626dc9-0578-4fad-8762-4083d71d89fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15630
60614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.1563060614
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.386635348
Short name T86
Test name
Test status
Simulation time 12526327580 ps
CPU time 95.4 seconds
Started Jul 25 07:01:27 PM PDT 24
Finished Jul 25 07:03:02 PM PDT 24
Peak memory 223800 kb
Host smart-201c1efc-ac66-4b26-ab64-7891a182aba9
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386635348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.386635348
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_timeout_missing_host_handshake.2396049104
Short name T1137
Test name
Test status
Simulation time 2567246051 ps
CPU time 21.18 seconds
Started Jul 25 07:01:12 PM PDT 24
Finished Jul 25 07:01:34 PM PDT 24
Peak memory 207424 kb
Host smart-3dac7d78-db54-41c6-b33b-7de14dc2fbdd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396049104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_timeout_missing_host
_handshake.2396049104
Directory /workspace/4.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.4199068233
Short name T202
Test name
Test status
Simulation time 31564657 ps
CPU time 0.68 seconds
Started Jul 25 07:07:45 PM PDT 24
Finished Jul 25 07:07:46 PM PDT 24
Peak memory 207192 kb
Host smart-17a1b1eb-3d69-4c9a-b836-bba977b2aa16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4199068233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.4199068233
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.2520468569
Short name T2443
Test name
Test status
Simulation time 4493207019 ps
CPU time 6.52 seconds
Started Jul 25 07:07:28 PM PDT 24
Finished Jul 25 07:07:34 PM PDT 24
Peak memory 207316 kb
Host smart-233a8420-848a-4493-a06b-e25f1f32f01a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520468569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_a
on_wake_disconnect.2520468569
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.2842464173
Short name T614
Test name
Test status
Simulation time 13369331390 ps
CPU time 15.74 seconds
Started Jul 25 07:07:16 PM PDT 24
Finished Jul 25 07:07:32 PM PDT 24
Peak memory 207396 kb
Host smart-b66e5678-65e4-4b07-a036-91d31cb2c2b5
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842464173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.2842464173
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.503843149
Short name T1925
Test name
Test status
Simulation time 23392909013 ps
CPU time 26.51 seconds
Started Jul 25 07:07:17 PM PDT 24
Finished Jul 25 07:07:44 PM PDT 24
Peak memory 207344 kb
Host smart-00201eda-4599-4469-b77d-c226ef4a0802
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503843149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_ao
n_wake_resume.503843149
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.3013939208
Short name T1669
Test name
Test status
Simulation time 153959005 ps
CPU time 0.83 seconds
Started Jul 25 07:07:16 PM PDT 24
Finished Jul 25 07:07:17 PM PDT 24
Peak memory 207188 kb
Host smart-c28b74db-9b10-46f9-aa53-1ddb48057304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30139
39208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.3013939208
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.2562952065
Short name T1500
Test name
Test status
Simulation time 146077683 ps
CPU time 0.89 seconds
Started Jul 25 07:07:17 PM PDT 24
Finished Jul 25 07:07:19 PM PDT 24
Peak memory 207044 kb
Host smart-7afb901b-dbb8-4ef1-a174-6dc5122ae18f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25629
52065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.2562952065
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.2074176278
Short name T1195
Test name
Test status
Simulation time 432232311 ps
CPU time 1.6 seconds
Started Jul 25 07:07:18 PM PDT 24
Finished Jul 25 07:07:20 PM PDT 24
Peak memory 207136 kb
Host smart-20496a59-59b5-4e84-9185-755192b8f2d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20741
76278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.2074176278
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.2703745103
Short name T1550
Test name
Test status
Simulation time 535464057 ps
CPU time 1.65 seconds
Started Jul 25 07:07:20 PM PDT 24
Finished Jul 25 07:07:22 PM PDT 24
Peak memory 207112 kb
Host smart-babbeed1-a31f-414d-ac83-3d5c55eed844
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2703745103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.2703745103
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.3953992501
Short name T1380
Test name
Test status
Simulation time 22334407062 ps
CPU time 48.45 seconds
Started Jul 25 07:07:22 PM PDT 24
Finished Jul 25 07:08:11 PM PDT 24
Peak memory 207324 kb
Host smart-819f8eb0-cb12-4091-9092-510822909983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39539
92501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.3953992501
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_device_timeout.3608420970
Short name T2116
Test name
Test status
Simulation time 2435820636 ps
CPU time 21.3 seconds
Started Jul 25 07:07:17 PM PDT 24
Finished Jul 25 07:07:39 PM PDT 24
Peak memory 207536 kb
Host smart-e5640b37-d099-48bc-86f4-27c48bcd541c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608420970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_timeout.3608420970
Directory /workspace/40.usbdev_device_timeout/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.2561547640
Short name T1649
Test name
Test status
Simulation time 345687515 ps
CPU time 1.24 seconds
Started Jul 25 07:07:38 PM PDT 24
Finished Jul 25 07:07:39 PM PDT 24
Peak memory 207092 kb
Host smart-a9292489-de84-467e-9060-3057d04dea9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25615
47640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.2561547640
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.681633892
Short name T2542
Test name
Test status
Simulation time 163291521 ps
CPU time 0.83 seconds
Started Jul 25 07:07:20 PM PDT 24
Finished Jul 25 07:07:21 PM PDT 24
Peak memory 207116 kb
Host smart-5bc344a5-e787-4ad6-b57f-a0a4cdf7d01f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68163
3892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.681633892
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.2973425100
Short name T501
Test name
Test status
Simulation time 41971223 ps
CPU time 0.7 seconds
Started Jul 25 07:07:20 PM PDT 24
Finished Jul 25 07:07:21 PM PDT 24
Peak memory 207040 kb
Host smart-2eadd4c8-5060-49c8-8fdb-1112af376e65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29734
25100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.2973425100
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.2755977003
Short name T110
Test name
Test status
Simulation time 1029783609 ps
CPU time 2.5 seconds
Started Jul 25 07:07:21 PM PDT 24
Finished Jul 25 07:07:24 PM PDT 24
Peak memory 207404 kb
Host smart-dd2caac1-701f-4cfe-ab30-ddadf3ac9df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27559
77003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.2755977003
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.4109547349
Short name T2431
Test name
Test status
Simulation time 408313512 ps
CPU time 3.02 seconds
Started Jul 25 07:07:28 PM PDT 24
Finished Jul 25 07:07:31 PM PDT 24
Peak memory 207260 kb
Host smart-740a9503-bc0b-4573-8b39-b19eaf53ddf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41095
47349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.4109547349
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.1208181409
Short name T1229
Test name
Test status
Simulation time 244850315 ps
CPU time 1.23 seconds
Started Jul 25 07:08:14 PM PDT 24
Finished Jul 25 07:08:16 PM PDT 24
Peak memory 215504 kb
Host smart-45418087-179f-42cf-931c-6f47b2bfe05b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1208181409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.1208181409
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.4048306835
Short name T1469
Test name
Test status
Simulation time 151715728 ps
CPU time 0.8 seconds
Started Jul 25 07:07:18 PM PDT 24
Finished Jul 25 07:07:19 PM PDT 24
Peak memory 207092 kb
Host smart-b44cfd15-0c2b-4746-83b3-d96502ca17d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40483
06835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.4048306835
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.2056759675
Short name T506
Test name
Test status
Simulation time 236551427 ps
CPU time 1.02 seconds
Started Jul 25 07:07:20 PM PDT 24
Finished Jul 25 07:07:22 PM PDT 24
Peak memory 207128 kb
Host smart-c1863a48-275a-429e-aa6b-896b37efe789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20567
59675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.2056759675
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.3037653785
Short name T2469
Test name
Test status
Simulation time 9988988463 ps
CPU time 99.27 seconds
Started Jul 25 07:07:17 PM PDT 24
Finished Jul 25 07:09:06 PM PDT 24
Peak memory 217012 kb
Host smart-baddf648-4ea8-42d6-9f24-aaa57362b4de
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3037653785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.3037653785
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_iso_retraction.1890999168
Short name T268
Test name
Test status
Simulation time 13642056197 ps
CPU time 87.77 seconds
Started Jul 25 07:07:17 PM PDT 24
Finished Jul 25 07:08:45 PM PDT 24
Peak memory 207340 kb
Host smart-6a4f3d3c-f502-44cd-94c1-2d8b63bb83bb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1890999168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.1890999168
Directory /workspace/40.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.662770392
Short name T1766
Test name
Test status
Simulation time 200950756 ps
CPU time 0.93 seconds
Started Jul 25 07:07:20 PM PDT 24
Finished Jul 25 07:07:21 PM PDT 24
Peak memory 207088 kb
Host smart-3220e536-2212-4c7d-be3a-cd2f27d4e121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66277
0392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.662770392
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.2025127069
Short name T2791
Test name
Test status
Simulation time 23347228160 ps
CPU time 30.87 seconds
Started Jul 25 07:07:22 PM PDT 24
Finished Jul 25 07:07:53 PM PDT 24
Peak memory 207408 kb
Host smart-1df5c3fc-bb68-41f1-bace-d5b35fa428eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20251
27069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.2025127069
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.839306581
Short name T1638
Test name
Test status
Simulation time 3333791032 ps
CPU time 5.82 seconds
Started Jul 25 07:07:20 PM PDT 24
Finished Jul 25 07:07:26 PM PDT 24
Peak memory 207288 kb
Host smart-a954e272-49bb-41ab-964c-8bb6e170e763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83930
6581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.839306581
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.1230766818
Short name T557
Test name
Test status
Simulation time 5920495909 ps
CPU time 170.32 seconds
Started Jul 25 07:07:36 PM PDT 24
Finished Jul 25 07:10:26 PM PDT 24
Peak memory 215656 kb
Host smart-72877196-12bd-4241-8ccb-f655c63a68ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12307
66818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.1230766818
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.1061594001
Short name T2845
Test name
Test status
Simulation time 4471733111 ps
CPU time 45.7 seconds
Started Jul 25 07:07:20 PM PDT 24
Finished Jul 25 07:08:06 PM PDT 24
Peak memory 207340 kb
Host smart-29e9cf4e-ea6a-458f-a810-ea4aecb880df
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1061594001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.1061594001
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.2901091369
Short name T1026
Test name
Test status
Simulation time 257967823 ps
CPU time 0.97 seconds
Started Jul 25 07:07:19 PM PDT 24
Finished Jul 25 07:07:20 PM PDT 24
Peak memory 207148 kb
Host smart-c6750f56-a991-49e7-b94e-3211c46e8fa9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2901091369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.2901091369
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.26758109
Short name T598
Test name
Test status
Simulation time 185172397 ps
CPU time 0.95 seconds
Started Jul 25 07:07:35 PM PDT 24
Finished Jul 25 07:07:36 PM PDT 24
Peak memory 207108 kb
Host smart-eeeac902-254b-4c74-ac11-07daadb8302d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26758
109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.26758109
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.2228107727
Short name T1489
Test name
Test status
Simulation time 4046549899 ps
CPU time 30.59 seconds
Started Jul 25 07:07:19 PM PDT 24
Finished Jul 25 07:07:50 PM PDT 24
Peak memory 217184 kb
Host smart-5c9ee893-7fc9-4c41-a007-7ce731ba2d77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22281
07727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.2228107727
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.283107687
Short name T386
Test name
Test status
Simulation time 5978367448 ps
CPU time 184.69 seconds
Started Jul 25 07:07:39 PM PDT 24
Finished Jul 25 07:10:44 PM PDT 24
Peak memory 215560 kb
Host smart-48e34dde-92d7-4e43-92be-563287e57cda
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=283107687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.283107687
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.1999627543
Short name T1329
Test name
Test status
Simulation time 168506226 ps
CPU time 0.9 seconds
Started Jul 25 07:07:45 PM PDT 24
Finished Jul 25 07:07:46 PM PDT 24
Peak memory 207176 kb
Host smart-c44f3c12-1fc6-4a22-86c3-bfd8229517a2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1999627543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.1999627543
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.227987441
Short name T2155
Test name
Test status
Simulation time 160571968 ps
CPU time 0.9 seconds
Started Jul 25 07:07:43 PM PDT 24
Finished Jul 25 07:07:44 PM PDT 24
Peak memory 207128 kb
Host smart-7ac5d73e-2dc8-4e87-a605-f9d7f833d228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22798
7441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.227987441
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.723732053
Short name T153
Test name
Test status
Simulation time 207282997 ps
CPU time 0.93 seconds
Started Jul 25 07:07:35 PM PDT 24
Finished Jul 25 07:07:36 PM PDT 24
Peak memory 207120 kb
Host smart-ba568f12-3906-4d59-93ec-b0db9cde69b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72373
2053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.723732053
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.1333400278
Short name T1272
Test name
Test status
Simulation time 172394003 ps
CPU time 0.89 seconds
Started Jul 25 07:07:32 PM PDT 24
Finished Jul 25 07:07:33 PM PDT 24
Peak memory 207052 kb
Host smart-225e766c-b530-46b2-8314-777f066a7446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13334
00278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.1333400278
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.3497898849
Short name T1876
Test name
Test status
Simulation time 199272147 ps
CPU time 0.97 seconds
Started Jul 25 07:07:31 PM PDT 24
Finished Jul 25 07:07:33 PM PDT 24
Peak memory 207124 kb
Host smart-9503b89a-6e85-4e17-bb11-29509d1cc700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34978
98849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.3497898849
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.2536857873
Short name T628
Test name
Test status
Simulation time 204472829 ps
CPU time 0.93 seconds
Started Jul 25 07:07:31 PM PDT 24
Finished Jul 25 07:07:32 PM PDT 24
Peak memory 207232 kb
Host smart-1f3d4c6f-1ef9-470d-b8a5-1dda5316f2e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25368
57873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.2536857873
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.497436165
Short name T2676
Test name
Test status
Simulation time 178284956 ps
CPU time 0.92 seconds
Started Jul 25 07:07:46 PM PDT 24
Finished Jul 25 07:07:47 PM PDT 24
Peak memory 207184 kb
Host smart-9da0faaa-1f15-48d1-b10b-6fe3ce9e2b0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49743
6165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.497436165
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.249319522
Short name T1551
Test name
Test status
Simulation time 260379372 ps
CPU time 1.12 seconds
Started Jul 25 07:07:39 PM PDT 24
Finished Jul 25 07:07:40 PM PDT 24
Peak memory 207108 kb
Host smart-b75433a5-68f2-41cb-818a-da8c97209d1f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=249319522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.249319522
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.2540751760
Short name T44
Test name
Test status
Simulation time 137943870 ps
CPU time 0.79 seconds
Started Jul 25 07:07:32 PM PDT 24
Finished Jul 25 07:07:33 PM PDT 24
Peak memory 207092 kb
Host smart-4a989f6f-44e0-4c80-ba04-f1077814e90e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25407
51760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.2540751760
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.2267289772
Short name T28
Test name
Test status
Simulation time 50165194 ps
CPU time 0.69 seconds
Started Jul 25 07:07:44 PM PDT 24
Finished Jul 25 07:07:44 PM PDT 24
Peak memory 207084 kb
Host smart-c5b88e3a-d452-4801-8d46-6f6b9fb6fb7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22672
89772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.2267289772
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.1312879216
Short name T1119
Test name
Test status
Simulation time 13721929686 ps
CPU time 35.06 seconds
Started Jul 25 07:07:38 PM PDT 24
Finished Jul 25 07:08:13 PM PDT 24
Peak memory 215656 kb
Host smart-d08ffb86-af8b-42c9-b87a-93676a4b1dd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13128
79216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.1312879216
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.1175231572
Short name T1188
Test name
Test status
Simulation time 170934284 ps
CPU time 1 seconds
Started Jul 25 07:07:46 PM PDT 24
Finished Jul 25 07:07:47 PM PDT 24
Peak memory 207188 kb
Host smart-a16f42a1-3be6-4e56-b5ef-93428e864967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11752
31572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.1175231572
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.3634313097
Short name T721
Test name
Test status
Simulation time 238918421 ps
CPU time 0.98 seconds
Started Jul 25 07:07:44 PM PDT 24
Finished Jul 25 07:07:45 PM PDT 24
Peak memory 207140 kb
Host smart-47bf9cf7-a91c-4722-b02d-bc3a31b7fb04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36343
13097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.3634313097
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.1935159246
Short name T1958
Test name
Test status
Simulation time 176576707 ps
CPU time 0.92 seconds
Started Jul 25 07:07:39 PM PDT 24
Finished Jul 25 07:07:40 PM PDT 24
Peak memory 207112 kb
Host smart-643487cc-a844-4dea-ba0f-ae8be394839f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19351
59246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.1935159246
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.81469237
Short name T1559
Test name
Test status
Simulation time 161174125 ps
CPU time 0.94 seconds
Started Jul 25 07:07:41 PM PDT 24
Finished Jul 25 07:07:42 PM PDT 24
Peak memory 207192 kb
Host smart-fe88d57b-aff3-45c9-84e3-34c4db137167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81469
237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.81469237
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.3278593675
Short name T2501
Test name
Test status
Simulation time 140686457 ps
CPU time 0.83 seconds
Started Jul 25 07:07:45 PM PDT 24
Finished Jul 25 07:07:46 PM PDT 24
Peak memory 206960 kb
Host smart-d93c2995-66df-40a7-bb39-40b9c9f95f5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32785
93675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.3278593675
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.1431956202
Short name T773
Test name
Test status
Simulation time 148275857 ps
CPU time 0.9 seconds
Started Jul 25 07:07:37 PM PDT 24
Finished Jul 25 07:07:38 PM PDT 24
Peak memory 207092 kb
Host smart-d5a7e36c-f941-48d5-b548-9dd37ec8788f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14319
56202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.1431956202
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.1365558921
Short name T2428
Test name
Test status
Simulation time 165163216 ps
CPU time 0.85 seconds
Started Jul 25 07:07:41 PM PDT 24
Finished Jul 25 07:07:42 PM PDT 24
Peak memory 207112 kb
Host smart-dbb284bc-d3c6-491f-99fd-294e4ef90436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13655
58921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.1365558921
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.460224725
Short name T584
Test name
Test status
Simulation time 192334410 ps
CPU time 0.99 seconds
Started Jul 25 07:07:47 PM PDT 24
Finished Jul 25 07:07:48 PM PDT 24
Peak memory 207184 kb
Host smart-2a890d8a-64a3-4fb4-954f-77790f08c6e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46022
4725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.460224725
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.1935297197
Short name T529
Test name
Test status
Simulation time 3960404174 ps
CPU time 116.98 seconds
Started Jul 25 07:07:46 PM PDT 24
Finished Jul 25 07:09:43 PM PDT 24
Peak memory 215684 kb
Host smart-d7167b24-51d0-4e94-a806-1b8d45f356c9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1935297197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.1935297197
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.3796547773
Short name T1829
Test name
Test status
Simulation time 178069862 ps
CPU time 0.92 seconds
Started Jul 25 07:07:45 PM PDT 24
Finished Jul 25 07:07:46 PM PDT 24
Peak memory 207196 kb
Host smart-7f9910fd-047e-46fc-b2af-468891872bba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37965
47773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.3796547773
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.607203847
Short name T1572
Test name
Test status
Simulation time 214218896 ps
CPU time 0.9 seconds
Started Jul 25 07:07:29 PM PDT 24
Finished Jul 25 07:07:30 PM PDT 24
Peak memory 207136 kb
Host smart-582b6c63-8beb-4340-b9eb-eb0dc7199adc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60720
3847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.607203847
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.3517998306
Short name T2486
Test name
Test status
Simulation time 720506752 ps
CPU time 1.98 seconds
Started Jul 25 07:07:32 PM PDT 24
Finished Jul 25 07:07:35 PM PDT 24
Peak memory 207128 kb
Host smart-dec8cb15-fa68-476a-ab0a-6406002d2040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35179
98306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.3517998306
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.3704254455
Short name T532
Test name
Test status
Simulation time 6514002855 ps
CPU time 190.72 seconds
Started Jul 25 07:07:35 PM PDT 24
Finished Jul 25 07:10:46 PM PDT 24
Peak memory 215564 kb
Host smart-19db295f-0d13-4af6-ab0d-277cef81142b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37042
54455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.3704254455
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/40.usbdev_timeout_missing_host_handshake.2148412511
Short name T2552
Test name
Test status
Simulation time 2257036588 ps
CPU time 14.38 seconds
Started Jul 25 07:07:19 PM PDT 24
Finished Jul 25 07:07:34 PM PDT 24
Peak memory 207416 kb
Host smart-171fec77-6d9c-42e0-ae52-db1431d035af
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148412511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_timeout_missing_hos
t_handshake.2148412511
Directory /workspace/40.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.3167010499
Short name T1632
Test name
Test status
Simulation time 38814157 ps
CPU time 0.66 seconds
Started Jul 25 07:07:49 PM PDT 24
Finished Jul 25 07:07:50 PM PDT 24
Peak memory 207176 kb
Host smart-2f7f10aa-414c-4f3e-9d9a-f26642f94283
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3167010499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.3167010499
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.1812865418
Short name T2117
Test name
Test status
Simulation time 4354897896 ps
CPU time 5.96 seconds
Started Jul 25 07:07:39 PM PDT 24
Finished Jul 25 07:07:45 PM PDT 24
Peak memory 207436 kb
Host smart-845101f9-65ef-4d23-ba5b-8ecbc26f0f51
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812865418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_a
on_wake_disconnect.1812865418
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.1790877327
Short name T839
Test name
Test status
Simulation time 13406634318 ps
CPU time 16.27 seconds
Started Jul 25 07:07:30 PM PDT 24
Finished Jul 25 07:07:47 PM PDT 24
Peak memory 207428 kb
Host smart-10da4c90-02dc-492e-b065-897714c81399
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790877327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.1790877327
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.3593144261
Short name T1357
Test name
Test status
Simulation time 23391729712 ps
CPU time 33.1 seconds
Started Jul 25 07:07:45 PM PDT 24
Finished Jul 25 07:08:18 PM PDT 24
Peak memory 207384 kb
Host smart-9575c37a-9835-494e-96fc-87becdf73215
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593144261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_a
on_wake_resume.3593144261
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.3539346530
Short name T1111
Test name
Test status
Simulation time 193237566 ps
CPU time 0.91 seconds
Started Jul 25 07:07:42 PM PDT 24
Finished Jul 25 07:07:43 PM PDT 24
Peak memory 207108 kb
Host smart-28e7e040-78e8-4d82-9a4f-63891af9f55d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35393
46530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.3539346530
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.1354637426
Short name T2333
Test name
Test status
Simulation time 167252520 ps
CPU time 0.87 seconds
Started Jul 25 07:07:31 PM PDT 24
Finished Jul 25 07:07:32 PM PDT 24
Peak memory 207196 kb
Host smart-a1815395-8a2a-4e5e-a15b-311abe7d6c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13546
37426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.1354637426
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.4037223544
Short name T1312
Test name
Test status
Simulation time 338207154 ps
CPU time 1.23 seconds
Started Jul 25 07:07:29 PM PDT 24
Finished Jul 25 07:07:30 PM PDT 24
Peak memory 207136 kb
Host smart-fb8e989c-cef2-40c6-9dc7-5452d3660bfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40372
23544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.4037223544
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.4143683023
Short name T2370
Test name
Test status
Simulation time 555308702 ps
CPU time 1.6 seconds
Started Jul 25 07:07:40 PM PDT 24
Finished Jul 25 07:07:42 PM PDT 24
Peak memory 207112 kb
Host smart-742b373c-88fb-4cd7-9f1d-07308cf50b93
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4143683023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.4143683023
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.142656224
Short name T2268
Test name
Test status
Simulation time 12127187127 ps
CPU time 28.7 seconds
Started Jul 25 07:07:31 PM PDT 24
Finished Jul 25 07:08:00 PM PDT 24
Peak memory 207372 kb
Host smart-867f261b-7bb7-40c0-916e-8ce951d7789e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14265
6224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.142656224
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_device_timeout.221129781
Short name T2698
Test name
Test status
Simulation time 2967031856 ps
CPU time 25.44 seconds
Started Jul 25 07:07:34 PM PDT 24
Finished Jul 25 07:08:00 PM PDT 24
Peak memory 207336 kb
Host smart-09b782cc-fdd0-4479-88e3-cb7af72d7ac3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221129781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_timeout.221129781
Directory /workspace/41.usbdev_device_timeout/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.2767910581
Short name T2028
Test name
Test status
Simulation time 384789093 ps
CPU time 1.33 seconds
Started Jul 25 07:07:42 PM PDT 24
Finished Jul 25 07:07:44 PM PDT 24
Peak memory 207156 kb
Host smart-04c3cd7e-5b63-49ee-a518-2d3e9504e0a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27679
10581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.2767910581
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.816415038
Short name T1506
Test name
Test status
Simulation time 146334302 ps
CPU time 0.82 seconds
Started Jul 25 07:07:40 PM PDT 24
Finished Jul 25 07:07:41 PM PDT 24
Peak memory 207084 kb
Host smart-d4e7181a-8511-44a5-ad74-11653f705570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81641
5038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.816415038
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.2105288355
Short name T1288
Test name
Test status
Simulation time 52933422 ps
CPU time 0.73 seconds
Started Jul 25 07:07:44 PM PDT 24
Finished Jul 25 07:07:45 PM PDT 24
Peak memory 207096 kb
Host smart-33d13a1f-c2c8-4a90-99fa-881a6b0f816f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21052
88355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.2105288355
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.677160719
Short name T1704
Test name
Test status
Simulation time 858341822 ps
CPU time 2.42 seconds
Started Jul 25 07:07:45 PM PDT 24
Finished Jul 25 07:07:47 PM PDT 24
Peak memory 207400 kb
Host smart-be0d9be7-8f70-4c71-aa23-d18698ab80b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67716
0719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.677160719
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.1314099098
Short name T1564
Test name
Test status
Simulation time 204810999 ps
CPU time 1.96 seconds
Started Jul 25 07:07:51 PM PDT 24
Finished Jul 25 07:07:53 PM PDT 24
Peak memory 207376 kb
Host smart-f5eebe1b-0c80-4127-aa6e-4704debdd162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13140
99098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.1314099098
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.3015078104
Short name T1189
Test name
Test status
Simulation time 216968298 ps
CPU time 1.09 seconds
Started Jul 25 07:07:43 PM PDT 24
Finished Jul 25 07:07:44 PM PDT 24
Peak memory 207304 kb
Host smart-ed1d48a7-d328-40da-8d68-29b0fda2db1c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3015078104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.3015078104
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.1449534779
Short name T2421
Test name
Test status
Simulation time 151811167 ps
CPU time 0.8 seconds
Started Jul 25 07:07:49 PM PDT 24
Finished Jul 25 07:07:50 PM PDT 24
Peak memory 207048 kb
Host smart-5d10f328-365b-4eb5-98ad-6ed04c091d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14495
34779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.1449534779
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.878710199
Short name T112
Test name
Test status
Simulation time 210717793 ps
CPU time 0.95 seconds
Started Jul 25 07:07:47 PM PDT 24
Finished Jul 25 07:07:48 PM PDT 24
Peak memory 207072 kb
Host smart-ad758c01-9e00-4ae8-a2b0-769ea636aed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87871
0199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.878710199
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_invalid_sync.1258072257
Short name T1155
Test name
Test status
Simulation time 9378051400 ps
CPU time 281.53 seconds
Started Jul 25 07:07:48 PM PDT 24
Finished Jul 25 07:12:30 PM PDT 24
Peak memory 215496 kb
Host smart-98c56724-a3cd-4f77-9701-99a1fa4443fc
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1258072257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.1258072257
Directory /workspace/41.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/41.usbdev_iso_retraction.3258402891
Short name T2488
Test name
Test status
Simulation time 7356016851 ps
CPU time 88.74 seconds
Started Jul 25 07:07:47 PM PDT 24
Finished Jul 25 07:09:16 PM PDT 24
Peak memory 207348 kb
Host smart-94599f84-5dc2-4a97-9201-da4bb0fc55eb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3258402891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.3258402891
Directory /workspace/41.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.1610574838
Short name T1388
Test name
Test status
Simulation time 190837358 ps
CPU time 0.97 seconds
Started Jul 25 07:07:41 PM PDT 24
Finished Jul 25 07:07:42 PM PDT 24
Peak memory 207192 kb
Host smart-6e06874c-8e12-4585-937c-6fc3217b9e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16105
74838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.1610574838
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.657724849
Short name T505
Test name
Test status
Simulation time 23291496732 ps
CPU time 30.27 seconds
Started Jul 25 07:07:49 PM PDT 24
Finished Jul 25 07:08:19 PM PDT 24
Peak memory 207392 kb
Host smart-b61c1da0-f5b4-4f94-94dd-3d82486fd0f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65772
4849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.657724849
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.2193087492
Short name T984
Test name
Test status
Simulation time 3323312184 ps
CPU time 5.06 seconds
Started Jul 25 07:07:44 PM PDT 24
Finished Jul 25 07:07:49 PM PDT 24
Peak memory 207360 kb
Host smart-3c438825-acfe-4985-b480-20173da560ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21930
87492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.2193087492
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.2384764685
Short name T1019
Test name
Test status
Simulation time 6301613226 ps
CPU time 189.38 seconds
Started Jul 25 07:07:54 PM PDT 24
Finished Jul 25 07:11:04 PM PDT 24
Peak memory 215596 kb
Host smart-d08a3a0f-c6f5-4b50-bebc-54e891dc8ea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23847
64685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.2384764685
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.2459103124
Short name T1647
Test name
Test status
Simulation time 3817912594 ps
CPU time 28.17 seconds
Started Jul 25 07:07:47 PM PDT 24
Finished Jul 25 07:08:15 PM PDT 24
Peak memory 217072 kb
Host smart-faad8f2e-d2a4-4f30-80d7-22e40b3aea37
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2459103124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.2459103124
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.3191235667
Short name T1073
Test name
Test status
Simulation time 235095264 ps
CPU time 0.98 seconds
Started Jul 25 07:07:46 PM PDT 24
Finished Jul 25 07:07:47 PM PDT 24
Peak memory 207148 kb
Host smart-261455a1-5292-43f7-b276-3e5f8aaba6aa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3191235667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.3191235667
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.2391285132
Short name T625
Test name
Test status
Simulation time 194644571 ps
CPU time 0.93 seconds
Started Jul 25 07:07:50 PM PDT 24
Finished Jul 25 07:07:51 PM PDT 24
Peak memory 207072 kb
Host smart-79332b20-1056-40c3-8fac-0e9b4cba3ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23912
85132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.2391285132
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.1474537850
Short name T1068
Test name
Test status
Simulation time 5019937485 ps
CPU time 50.82 seconds
Started Jul 25 07:07:45 PM PDT 24
Finished Jul 25 07:08:36 PM PDT 24
Peak memory 215632 kb
Host smart-ff9f4f63-7950-4354-ba59-5d0213267598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14745
37850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.1474537850
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.2544173846
Short name T715
Test name
Test status
Simulation time 4351445369 ps
CPU time 32.5 seconds
Started Jul 25 07:07:48 PM PDT 24
Finished Jul 25 07:08:21 PM PDT 24
Peak memory 217048 kb
Host smart-9c2c4de9-7c4d-41ea-8f9e-19aa9c44f25a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2544173846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.2544173846
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.82370159
Short name T1093
Test name
Test status
Simulation time 152736010 ps
CPU time 0.89 seconds
Started Jul 25 07:07:45 PM PDT 24
Finished Jul 25 07:07:46 PM PDT 24
Peak memory 207124 kb
Host smart-c3e1195c-5c23-4437-9b03-45b4e15b4074
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=82370159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.82370159
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.4017606052
Short name T109
Test name
Test status
Simulation time 149842291 ps
CPU time 0.86 seconds
Started Jul 25 07:07:39 PM PDT 24
Finished Jul 25 07:07:40 PM PDT 24
Peak memory 207128 kb
Host smart-ac9133e6-b5cd-417c-beed-e90921302086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40176
06052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.4017606052
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.2249474914
Short name T2209
Test name
Test status
Simulation time 204703536 ps
CPU time 0.95 seconds
Started Jul 25 07:07:46 PM PDT 24
Finished Jul 25 07:07:47 PM PDT 24
Peak memory 207176 kb
Host smart-9dac3c09-ee07-41d8-8983-62ba333982ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22494
74914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.2249474914
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.2988003341
Short name T1009
Test name
Test status
Simulation time 204584487 ps
CPU time 1.01 seconds
Started Jul 25 07:07:43 PM PDT 24
Finished Jul 25 07:07:45 PM PDT 24
Peak memory 207156 kb
Host smart-7d234ffd-3d3e-465f-a93b-92cdc580958e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29880
03341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.2988003341
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.3649554546
Short name T1801
Test name
Test status
Simulation time 181328427 ps
CPU time 0.81 seconds
Started Jul 25 07:07:39 PM PDT 24
Finished Jul 25 07:07:40 PM PDT 24
Peak memory 206964 kb
Host smart-ee3bf389-e7ee-4640-819a-d41a0140c055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36495
54546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.3649554546
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.4109119451
Short name T1117
Test name
Test status
Simulation time 151511682 ps
CPU time 0.84 seconds
Started Jul 25 07:07:45 PM PDT 24
Finished Jul 25 07:07:46 PM PDT 24
Peak memory 207160 kb
Host smart-f731aec7-0c4b-4f6d-aba5-ae39d04b8e97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41091
19451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.4109119451
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.2025612352
Short name T2546
Test name
Test status
Simulation time 174803852 ps
CPU time 0.97 seconds
Started Jul 25 07:07:46 PM PDT 24
Finished Jul 25 07:07:47 PM PDT 24
Peak memory 207104 kb
Host smart-4384a085-d9c5-4b48-9047-e56e9c5bdb13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20256
12352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.2025612352
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.3226427930
Short name T2795
Test name
Test status
Simulation time 262907787 ps
CPU time 1.16 seconds
Started Jul 25 07:07:46 PM PDT 24
Finished Jul 25 07:07:47 PM PDT 24
Peak memory 207136 kb
Host smart-48f88cd8-94a7-4594-aed2-db6f92f1fc1b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3226427930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.3226427930
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.2052861004
Short name T2208
Test name
Test status
Simulation time 142054546 ps
CPU time 0.8 seconds
Started Jul 25 07:08:48 PM PDT 24
Finished Jul 25 07:08:49 PM PDT 24
Peak memory 207124 kb
Host smart-a919deb2-2a7e-4bfd-b019-426f82922754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20528
61004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.2052861004
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.3713934753
Short name T2260
Test name
Test status
Simulation time 33929972 ps
CPU time 0.71 seconds
Started Jul 25 07:07:51 PM PDT 24
Finished Jul 25 07:07:52 PM PDT 24
Peak memory 207128 kb
Host smart-7ee4b348-4afa-4344-a7f3-41d5e7117b53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37139
34753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.3713934753
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.3396641324
Short name T1991
Test name
Test status
Simulation time 21467106860 ps
CPU time 51.02 seconds
Started Jul 25 07:07:46 PM PDT 24
Finished Jul 25 07:08:37 PM PDT 24
Peak memory 215568 kb
Host smart-aff3ef44-6dc6-4a1e-bc77-4e4956e4062e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33966
41324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.3396641324
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.24234646
Short name T1023
Test name
Test status
Simulation time 208419950 ps
CPU time 0.96 seconds
Started Jul 25 07:07:46 PM PDT 24
Finished Jul 25 07:07:47 PM PDT 24
Peak memory 207116 kb
Host smart-408bfb19-643a-408c-8df7-1df2cf5e33fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24234
646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.24234646
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.3904669287
Short name T2665
Test name
Test status
Simulation time 207631458 ps
CPU time 1.01 seconds
Started Jul 25 07:07:47 PM PDT 24
Finished Jul 25 07:07:48 PM PDT 24
Peak memory 207160 kb
Host smart-35c6dfd2-09c8-4950-b48c-f28a245aa1f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39046
69287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.3904669287
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.197201850
Short name T1140
Test name
Test status
Simulation time 219349368 ps
CPU time 1.11 seconds
Started Jul 25 07:07:47 PM PDT 24
Finished Jul 25 07:07:49 PM PDT 24
Peak memory 207128 kb
Host smart-2a04a057-e625-46f8-a036-86bebc30165f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19720
1850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.197201850
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.2745901369
Short name T1710
Test name
Test status
Simulation time 194055911 ps
CPU time 0.95 seconds
Started Jul 25 07:07:47 PM PDT 24
Finished Jul 25 07:07:48 PM PDT 24
Peak memory 207072 kb
Host smart-230a18d1-84de-413c-a7aa-8d763b9b5fc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27459
01369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.2745901369
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.1907865769
Short name T1193
Test name
Test status
Simulation time 163422543 ps
CPU time 0.9 seconds
Started Jul 25 07:07:50 PM PDT 24
Finished Jul 25 07:07:51 PM PDT 24
Peak memory 207188 kb
Host smart-d034ae09-a432-446c-b461-c0776170bf73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19078
65769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.1907865769
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.4003349837
Short name T1914
Test name
Test status
Simulation time 183817209 ps
CPU time 0.91 seconds
Started Jul 25 07:07:50 PM PDT 24
Finished Jul 25 07:07:51 PM PDT 24
Peak memory 207092 kb
Host smart-89d70103-a9f5-4f23-82ef-0999efc3784e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40033
49837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.4003349837
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.1601871590
Short name T1396
Test name
Test status
Simulation time 156513572 ps
CPU time 0.89 seconds
Started Jul 25 07:07:47 PM PDT 24
Finished Jul 25 07:07:48 PM PDT 24
Peak memory 207140 kb
Host smart-fe57218d-59fa-4c14-aa52-cda501805555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16018
71590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.1601871590
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.3588245946
Short name T2187
Test name
Test status
Simulation time 243096518 ps
CPU time 1.07 seconds
Started Jul 25 07:07:46 PM PDT 24
Finished Jul 25 07:07:47 PM PDT 24
Peak memory 207124 kb
Host smart-876ee1b1-de22-4ec1-b052-0c5a4d2de368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35882
45946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.3588245946
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.4026732863
Short name T2553
Test name
Test status
Simulation time 3769095986 ps
CPU time 39.03 seconds
Started Jul 25 07:07:50 PM PDT 24
Finished Jul 25 07:08:29 PM PDT 24
Peak memory 215540 kb
Host smart-4391911d-0cac-4cf2-9ef3-869ab7c241af
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4026732863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.4026732863
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.1835987376
Short name T1663
Test name
Test status
Simulation time 231901368 ps
CPU time 0.98 seconds
Started Jul 25 07:07:48 PM PDT 24
Finished Jul 25 07:07:49 PM PDT 24
Peak memory 207180 kb
Host smart-057cb7b0-bfb8-41cb-a80b-c7b6bd8dbfe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18359
87376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.1835987376
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.2193499509
Short name T2075
Test name
Test status
Simulation time 174531287 ps
CPU time 0.94 seconds
Started Jul 25 07:07:47 PM PDT 24
Finished Jul 25 07:07:48 PM PDT 24
Peak memory 207124 kb
Host smart-4adf5372-1e98-4143-a3ad-5ab4a34a2372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21934
99509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.2193499509
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.1446842062
Short name T2583
Test name
Test status
Simulation time 462061541 ps
CPU time 1.33 seconds
Started Jul 25 07:07:49 PM PDT 24
Finished Jul 25 07:07:51 PM PDT 24
Peak memory 207160 kb
Host smart-68451b5b-7e53-4bf8-ac4f-b7c98b523047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14468
42062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.1446842062
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.3065095493
Short name T1926
Test name
Test status
Simulation time 7057587161 ps
CPU time 71.74 seconds
Started Jul 25 07:07:46 PM PDT 24
Finished Jul 25 07:08:58 PM PDT 24
Peak memory 207344 kb
Host smart-5bc56cf9-5a88-4711-a87f-6b38ee94f224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30650
95493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.3065095493
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_timeout_missing_host_handshake.640677515
Short name T1185
Test name
Test status
Simulation time 1119600709 ps
CPU time 26.05 seconds
Started Jul 25 07:07:38 PM PDT 24
Finished Jul 25 07:08:04 PM PDT 24
Peak memory 207364 kb
Host smart-232ce731-cddf-4773-871c-9295e9857c00
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640677515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_timeout_missing_host
_handshake.640677515
Directory /workspace/41.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.1767069122
Short name T203
Test name
Test status
Simulation time 38520617 ps
CPU time 0.69 seconds
Started Jul 25 07:07:48 PM PDT 24
Finished Jul 25 07:07:49 PM PDT 24
Peak memory 207108 kb
Host smart-9f468cb7-43f1-4e96-a809-b71df048b78b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1767069122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.1767069122
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.2051768714
Short name T883
Test name
Test status
Simulation time 4012067793 ps
CPU time 6.25 seconds
Started Jul 25 07:07:44 PM PDT 24
Finished Jul 25 07:07:50 PM PDT 24
Peak memory 207356 kb
Host smart-221963be-b3f5-40e3-9224-701eb0b0c327
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051768714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_a
on_wake_disconnect.2051768714
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.474024909
Short name T588
Test name
Test status
Simulation time 13373032098 ps
CPU time 14.83 seconds
Started Jul 25 07:07:49 PM PDT 24
Finished Jul 25 07:08:04 PM PDT 24
Peak memory 207396 kb
Host smart-3178c4ff-b4da-48c1-93fc-6b09b2f83a9a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=474024909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.474024909
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.4100928361
Short name T1444
Test name
Test status
Simulation time 23311383918 ps
CPU time 29.87 seconds
Started Jul 25 07:07:49 PM PDT 24
Finished Jul 25 07:08:19 PM PDT 24
Peak memory 207404 kb
Host smart-13b4dd24-4414-4d94-8339-bedc1a42df08
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100928361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_a
on_wake_resume.4100928361
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.3942244147
Short name T1683
Test name
Test status
Simulation time 171529871 ps
CPU time 0.91 seconds
Started Jul 25 07:07:47 PM PDT 24
Finished Jul 25 07:07:48 PM PDT 24
Peak memory 207096 kb
Host smart-1380c928-e258-4fdb-a1e8-ef14780cd41f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39422
44147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.3942244147
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.1807534581
Short name T2142
Test name
Test status
Simulation time 147039290 ps
CPU time 0.84 seconds
Started Jul 25 07:07:46 PM PDT 24
Finished Jul 25 07:07:47 PM PDT 24
Peak memory 207040 kb
Host smart-30137efd-629e-49b2-8311-8c0e4d08ec55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18075
34581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.1807534581
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.1065736232
Short name T684
Test name
Test status
Simulation time 505830782 ps
CPU time 1.76 seconds
Started Jul 25 07:07:52 PM PDT 24
Finished Jul 25 07:07:54 PM PDT 24
Peak memory 207136 kb
Host smart-9a907d78-f67f-4dec-9858-1cf5ffc11d50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10657
36232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.1065736232
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.3094066843
Short name T1233
Test name
Test status
Simulation time 296645427 ps
CPU time 1.06 seconds
Started Jul 25 07:07:54 PM PDT 24
Finished Jul 25 07:07:55 PM PDT 24
Peak memory 207112 kb
Host smart-e1dfae1e-3f45-4c9a-bbf3-afa7d21100f9
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3094066843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.3094066843
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.1861296488
Short name T2799
Test name
Test status
Simulation time 15006658180 ps
CPU time 32.4 seconds
Started Jul 25 07:07:52 PM PDT 24
Finished Jul 25 07:08:25 PM PDT 24
Peak memory 207352 kb
Host smart-785c37af-e652-47b3-8341-38ad29942a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18612
96488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.1861296488
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_device_timeout.145166640
Short name T1358
Test name
Test status
Simulation time 743869237 ps
CPU time 15.19 seconds
Started Jul 25 07:07:34 PM PDT 24
Finished Jul 25 07:07:49 PM PDT 24
Peak memory 207260 kb
Host smart-ef30802a-858d-4769-b20f-3f4c4214fbf8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145166640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_timeout.145166640
Directory /workspace/42.usbdev_device_timeout/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.60168030
Short name T302
Test name
Test status
Simulation time 352156226 ps
CPU time 1.36 seconds
Started Jul 25 07:07:48 PM PDT 24
Finished Jul 25 07:07:50 PM PDT 24
Peak memory 207088 kb
Host smart-e337bf02-957f-49a9-8fd7-92dba54f149b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60168
030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.60168030
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.2175926391
Short name T857
Test name
Test status
Simulation time 160643470 ps
CPU time 0.84 seconds
Started Jul 25 07:07:43 PM PDT 24
Finished Jul 25 07:07:44 PM PDT 24
Peak memory 207124 kb
Host smart-37bb83ed-8d01-4a6b-9927-413fdfc634bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21759
26391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.2175926391
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.1297577643
Short name T676
Test name
Test status
Simulation time 54710680 ps
CPU time 0.71 seconds
Started Jul 25 07:07:49 PM PDT 24
Finished Jul 25 07:07:50 PM PDT 24
Peak memory 207036 kb
Host smart-21a176e3-b17b-42f1-a75b-9d2305324e43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12975
77643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.1297577643
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.2405701675
Short name T848
Test name
Test status
Simulation time 890633530 ps
CPU time 2.41 seconds
Started Jul 25 07:07:45 PM PDT 24
Finished Jul 25 07:07:47 PM PDT 24
Peak memory 207292 kb
Host smart-136bbae1-bfa6-4159-8b82-da3001f296bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24057
01675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.2405701675
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.1849737171
Short name T2019
Test name
Test status
Simulation time 196705853 ps
CPU time 2.4 seconds
Started Jul 25 07:07:49 PM PDT 24
Finished Jul 25 07:07:52 PM PDT 24
Peak memory 207324 kb
Host smart-6b5a4838-d318-4906-9efd-736072624201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18497
37171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.1849737171
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.3374303952
Short name T2804
Test name
Test status
Simulation time 231784502 ps
CPU time 1.26 seconds
Started Jul 25 07:07:53 PM PDT 24
Finished Jul 25 07:07:54 PM PDT 24
Peak memory 215552 kb
Host smart-cc57993a-a20f-4b6b-a1f2-8434b62c57b1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3374303952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.3374303952
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.3954049532
Short name T1125
Test name
Test status
Simulation time 149116862 ps
CPU time 0.8 seconds
Started Jul 25 07:07:53 PM PDT 24
Finished Jul 25 07:07:54 PM PDT 24
Peak memory 207084 kb
Host smart-3b223a36-3f18-4456-ba71-9d075accd093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39540
49532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.3954049532
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.1663604999
Short name T2425
Test name
Test status
Simulation time 232300415 ps
CPU time 1 seconds
Started Jul 25 07:07:51 PM PDT 24
Finished Jul 25 07:07:52 PM PDT 24
Peak memory 207108 kb
Host smart-0696e376-5447-4288-81d9-7b5b637706fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16636
04999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.1663604999
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.239596588
Short name T1250
Test name
Test status
Simulation time 7826321701 ps
CPU time 82.41 seconds
Started Jul 25 07:07:56 PM PDT 24
Finished Jul 25 07:09:19 PM PDT 24
Peak memory 216844 kb
Host smart-f2c27ec5-6b7f-47a4-9b1c-d45274f03098
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=239596588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.239596588
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_iso_retraction.3348781846
Short name T2472
Test name
Test status
Simulation time 8645656568 ps
CPU time 52.88 seconds
Started Jul 25 07:07:49 PM PDT 24
Finished Jul 25 07:08:42 PM PDT 24
Peak memory 207364 kb
Host smart-69cdbf10-2721-48bf-858b-ccb82b5a64c0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3348781846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_iso_retraction.3348781846
Directory /workspace/42.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.3456027081
Short name T1806
Test name
Test status
Simulation time 231449155 ps
CPU time 0.98 seconds
Started Jul 25 07:07:45 PM PDT 24
Finished Jul 25 07:07:47 PM PDT 24
Peak memory 207068 kb
Host smart-0feb53a6-10c4-439b-9ae3-c83b2fec56ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34560
27081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.3456027081
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.1304833525
Short name T663
Test name
Test status
Simulation time 23339067743 ps
CPU time 28.14 seconds
Started Jul 25 07:07:53 PM PDT 24
Finished Jul 25 07:08:22 PM PDT 24
Peak memory 207472 kb
Host smart-c98e018f-008e-4d83-b104-c656c4b546a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13048
33525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.1304833525
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.3552906340
Short name T463
Test name
Test status
Simulation time 3328168680 ps
CPU time 5.73 seconds
Started Jul 25 07:07:49 PM PDT 24
Finished Jul 25 07:07:55 PM PDT 24
Peak memory 207376 kb
Host smart-64977213-f214-419d-a775-7578b6e2db47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35529
06340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.3552906340
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.134749289
Short name T2782
Test name
Test status
Simulation time 5006131666 ps
CPU time 147.86 seconds
Started Jul 25 07:07:51 PM PDT 24
Finished Jul 25 07:10:19 PM PDT 24
Peak memory 215572 kb
Host smart-9bb4a9f4-0bfa-4742-ae03-1132daf5621b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13474
9289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.134749289
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.4057338919
Short name T2190
Test name
Test status
Simulation time 5028018195 ps
CPU time 36.28 seconds
Started Jul 25 07:07:50 PM PDT 24
Finished Jul 25 07:08:26 PM PDT 24
Peak memory 207388 kb
Host smart-a1ebdd21-43ee-40f5-a275-c703bf1a2175
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4057338919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.4057338919
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.2327740664
Short name T507
Test name
Test status
Simulation time 237942181 ps
CPU time 0.97 seconds
Started Jul 25 07:07:56 PM PDT 24
Finished Jul 25 07:07:57 PM PDT 24
Peak memory 207144 kb
Host smart-7b76ad45-7297-4a06-9434-07e2b24a1c93
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2327740664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.2327740664
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.313261949
Short name T425
Test name
Test status
Simulation time 194556592 ps
CPU time 0.94 seconds
Started Jul 25 07:07:51 PM PDT 24
Finished Jul 25 07:07:52 PM PDT 24
Peak memory 207188 kb
Host smart-18257c88-2465-4c90-b32a-b345bca2e96f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31326
1949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.313261949
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.2185239249
Short name T2616
Test name
Test status
Simulation time 3806375942 ps
CPU time 108.05 seconds
Started Jul 25 07:07:49 PM PDT 24
Finished Jul 25 07:09:38 PM PDT 24
Peak memory 215524 kb
Host smart-28c98f81-3916-4348-a07c-9b82c2e01b55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21852
39249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.2185239249
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.4040380455
Short name T2729
Test name
Test status
Simulation time 5678725496 ps
CPU time 57.31 seconds
Started Jul 25 07:07:52 PM PDT 24
Finished Jul 25 07:08:49 PM PDT 24
Peak memory 207360 kb
Host smart-6ff053a8-afeb-45dd-a65e-f0a2c7179e1b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4040380455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.4040380455
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.4281871327
Short name T2020
Test name
Test status
Simulation time 167674212 ps
CPU time 0.88 seconds
Started Jul 25 07:07:49 PM PDT 24
Finished Jul 25 07:07:50 PM PDT 24
Peak memory 207144 kb
Host smart-756714d5-b64c-4ef8-a02c-4d39dece52dc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4281871327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.4281871327
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.994434890
Short name T1428
Test name
Test status
Simulation time 150847841 ps
CPU time 0.84 seconds
Started Jul 25 07:07:50 PM PDT 24
Finished Jul 25 07:07:51 PM PDT 24
Peak memory 207156 kb
Host smart-01c80449-ae98-4120-b6f1-b936b4775fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99443
4890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.994434890
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.1056518361
Short name T142
Test name
Test status
Simulation time 194558068 ps
CPU time 0.93 seconds
Started Jul 25 07:07:59 PM PDT 24
Finished Jul 25 07:08:00 PM PDT 24
Peak memory 207156 kb
Host smart-8222d087-b178-4f62-932e-1659146d1cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10565
18361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.1056518361
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.3988377960
Short name T1237
Test name
Test status
Simulation time 161714783 ps
CPU time 0.9 seconds
Started Jul 25 07:07:47 PM PDT 24
Finished Jul 25 07:07:48 PM PDT 24
Peak memory 207088 kb
Host smart-660e90e6-b6b2-4e0f-923a-58c00d795f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39883
77960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.3988377960
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.3182595349
Short name T1541
Test name
Test status
Simulation time 181049268 ps
CPU time 0.93 seconds
Started Jul 25 07:07:55 PM PDT 24
Finished Jul 25 07:07:56 PM PDT 24
Peak memory 207116 kb
Host smart-b32e741c-55ee-4beb-8eaa-b5472f899ff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31825
95349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.3182595349
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.3793880251
Short name T34
Test name
Test status
Simulation time 185170973 ps
CPU time 0.92 seconds
Started Jul 25 07:07:48 PM PDT 24
Finished Jul 25 07:07:49 PM PDT 24
Peak memory 207196 kb
Host smart-8f44dbad-d174-443a-a641-b735ca55dfff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37938
80251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.3793880251
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.498073049
Short name T2125
Test name
Test status
Simulation time 162412306 ps
CPU time 0.89 seconds
Started Jul 25 07:07:51 PM PDT 24
Finished Jul 25 07:07:52 PM PDT 24
Peak memory 207116 kb
Host smart-b8a301bf-cd36-4aa4-90f3-3ef8a5b78811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49807
3049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.498073049
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.2293135580
Short name T2615
Test name
Test status
Simulation time 237253177 ps
CPU time 1.06 seconds
Started Jul 25 07:07:51 PM PDT 24
Finished Jul 25 07:07:52 PM PDT 24
Peak memory 207184 kb
Host smart-009a6c90-919e-48e9-b99d-20445e8096be
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2293135580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.2293135580
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.2053162525
Short name T931
Test name
Test status
Simulation time 141234672 ps
CPU time 0.8 seconds
Started Jul 25 07:07:53 PM PDT 24
Finished Jul 25 07:07:55 PM PDT 24
Peak memory 207100 kb
Host smart-d33dfc56-f14a-4dee-999c-e6b6371a5a52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20531
62525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.2053162525
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.75256535
Short name T1348
Test name
Test status
Simulation time 33227031 ps
CPU time 0.74 seconds
Started Jul 25 07:07:52 PM PDT 24
Finished Jul 25 07:07:53 PM PDT 24
Peak memory 207100 kb
Host smart-fe8d0254-e1e2-41fa-81fa-664f70350975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75256
535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.75256535
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.4035746850
Short name T273
Test name
Test status
Simulation time 10224537866 ps
CPU time 26.08 seconds
Started Jul 25 07:07:46 PM PDT 24
Finished Jul 25 07:08:12 PM PDT 24
Peak memory 215616 kb
Host smart-d93c83b8-9716-4dc5-8f2b-ec192ca9e1e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40357
46850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.4035746850
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.4163668580
Short name T513
Test name
Test status
Simulation time 209138604 ps
CPU time 1 seconds
Started Jul 25 07:07:53 PM PDT 24
Finished Jul 25 07:07:54 PM PDT 24
Peak memory 207084 kb
Host smart-8b9c2440-8849-41f3-8000-0ae921c3fb79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41636
68580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.4163668580
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.2348569340
Short name T1102
Test name
Test status
Simulation time 245349587 ps
CPU time 1 seconds
Started Jul 25 07:07:54 PM PDT 24
Finished Jul 25 07:07:56 PM PDT 24
Peak memory 207124 kb
Host smart-73004e20-1a74-4d93-9c0e-7d88a33e58f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23485
69340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.2348569340
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.2573498505
Short name T1478
Test name
Test status
Simulation time 230262572 ps
CPU time 0.99 seconds
Started Jul 25 07:07:46 PM PDT 24
Finished Jul 25 07:07:47 PM PDT 24
Peak memory 207136 kb
Host smart-ce588073-c4b7-440f-b578-05e2c88658be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25734
98505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.2573498505
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.1797355828
Short name T1053
Test name
Test status
Simulation time 184692853 ps
CPU time 0.91 seconds
Started Jul 25 07:07:51 PM PDT 24
Finished Jul 25 07:07:52 PM PDT 24
Peak memory 207120 kb
Host smart-67f51320-8440-4738-bf0d-7bf728cd9245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17973
55828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.1797355828
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.3083035936
Short name T1129
Test name
Test status
Simulation time 174970553 ps
CPU time 0.88 seconds
Started Jul 25 07:07:48 PM PDT 24
Finished Jul 25 07:07:50 PM PDT 24
Peak memory 207084 kb
Host smart-2e823864-b53e-47b1-a0ec-a6438c23f486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30830
35936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.3083035936
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.3727218106
Short name T2717
Test name
Test status
Simulation time 146832853 ps
CPU time 0.85 seconds
Started Jul 25 07:07:49 PM PDT 24
Finished Jul 25 07:07:50 PM PDT 24
Peak memory 207064 kb
Host smart-3bc78863-2f08-4a42-8854-138c9041f73b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37272
18106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.3727218106
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.2893281206
Short name T124
Test name
Test status
Simulation time 145371269 ps
CPU time 0.88 seconds
Started Jul 25 07:07:49 PM PDT 24
Finished Jul 25 07:07:50 PM PDT 24
Peak memory 207048 kb
Host smart-ab4ff66f-4cbe-4726-b7df-6214ed4ec962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28932
81206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.2893281206
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.209003155
Short name T2152
Test name
Test status
Simulation time 257272030 ps
CPU time 1.08 seconds
Started Jul 25 07:07:54 PM PDT 24
Finished Jul 25 07:07:55 PM PDT 24
Peak memory 207100 kb
Host smart-a169baff-9f09-4699-9ad2-d3f4d538344f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20900
3155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.209003155
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.2355345926
Short name T1036
Test name
Test status
Simulation time 5948486990 ps
CPU time 62.44 seconds
Started Jul 25 07:07:48 PM PDT 24
Finished Jul 25 07:08:50 PM PDT 24
Peak memory 217244 kb
Host smart-d2c621c5-f48f-414e-bef2-baee5cc9c550
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2355345926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.2355345926
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.3923779595
Short name T1517
Test name
Test status
Simulation time 229909004 ps
CPU time 0.92 seconds
Started Jul 25 07:07:48 PM PDT 24
Finished Jul 25 07:07:49 PM PDT 24
Peak memory 207160 kb
Host smart-ca9b241b-df00-44b3-a1b6-a6564cd55ae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39237
79595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.3923779595
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.3178376418
Short name T958
Test name
Test status
Simulation time 164252928 ps
CPU time 0.9 seconds
Started Jul 25 07:07:47 PM PDT 24
Finished Jul 25 07:07:48 PM PDT 24
Peak memory 207108 kb
Host smart-a199a119-8289-4651-97ba-ec40ae4b09ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31783
76418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.3178376418
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.1893500357
Short name T111
Test name
Test status
Simulation time 1054912020 ps
CPU time 2.88 seconds
Started Jul 25 07:07:49 PM PDT 24
Finished Jul 25 07:07:52 PM PDT 24
Peak memory 207340 kb
Host smart-d447be1b-a3d3-42cd-8a55-017f9f963f25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18935
00357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.1893500357
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.1069861480
Short name T2135
Test name
Test status
Simulation time 6527770361 ps
CPU time 196.16 seconds
Started Jul 25 07:07:54 PM PDT 24
Finished Jul 25 07:11:10 PM PDT 24
Peak memory 215576 kb
Host smart-5a0232d0-9209-407e-8eb4-0fd873e11291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10698
61480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.1069861480
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_timeout_missing_host_handshake.31232620
Short name T1085
Test name
Test status
Simulation time 1688068929 ps
CPU time 41.65 seconds
Started Jul 25 07:07:47 PM PDT 24
Finished Jul 25 07:08:29 PM PDT 24
Peak memory 207308 kb
Host smart-1fcd8883-9d49-4451-a6f7-e638c7dcdc45
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31232620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_timeout_missing_host_
handshake.31232620
Directory /workspace/42.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.1575559869
Short name T1224
Test name
Test status
Simulation time 88995875 ps
CPU time 0.67 seconds
Started Jul 25 07:07:53 PM PDT 24
Finished Jul 25 07:07:53 PM PDT 24
Peak memory 207152 kb
Host smart-5b6a2e65-73ac-44ed-9225-6d3532f59fd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1575559869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.1575559869
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.636542182
Short name T954
Test name
Test status
Simulation time 4250129102 ps
CPU time 7.09 seconds
Started Jul 25 07:07:47 PM PDT 24
Finished Jul 25 07:07:55 PM PDT 24
Peak memory 207360 kb
Host smart-136561cb-81ca-444e-86d4-9662ba904938
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636542182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_ao
n_wake_disconnect.636542182
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.2405103123
Short name T2655
Test name
Test status
Simulation time 13423342173 ps
CPU time 15.26 seconds
Started Jul 25 07:07:50 PM PDT 24
Finished Jul 25 07:08:05 PM PDT 24
Peak memory 207408 kb
Host smart-fe55fd20-e796-4b72-b252-fc6c8a639e6d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405103123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.2405103123
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.315360132
Short name T1621
Test name
Test status
Simulation time 23329099527 ps
CPU time 33.83 seconds
Started Jul 25 07:08:10 PM PDT 24
Finished Jul 25 07:08:44 PM PDT 24
Peak memory 207420 kb
Host smart-5dbc4d60-5f53-42f1-9ed5-4dbf31a01a3b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315360132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_ao
n_wake_resume.315360132
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.1295211301
Short name T1310
Test name
Test status
Simulation time 238237401 ps
CPU time 0.97 seconds
Started Jul 25 07:07:49 PM PDT 24
Finished Jul 25 07:07:50 PM PDT 24
Peak memory 207124 kb
Host smart-b6eb3f64-e90a-4050-93af-79b548f26fa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12952
11301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.1295211301
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.1571240052
Short name T2245
Test name
Test status
Simulation time 149104416 ps
CPU time 0.86 seconds
Started Jul 25 07:07:46 PM PDT 24
Finished Jul 25 07:07:47 PM PDT 24
Peak memory 207084 kb
Host smart-89b9bb06-8e21-472f-a2bd-47ca9478a760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15712
40052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.1571240052
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.2835696468
Short name T624
Test name
Test status
Simulation time 413354221 ps
CPU time 1.59 seconds
Started Jul 25 07:07:49 PM PDT 24
Finished Jul 25 07:07:51 PM PDT 24
Peak memory 207196 kb
Host smart-d517f44c-ae32-472b-9626-33bf0e54b2ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28356
96468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.2835696468
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.1336343486
Short name T413
Test name
Test status
Simulation time 606299879 ps
CPU time 1.63 seconds
Started Jul 25 07:07:57 PM PDT 24
Finished Jul 25 07:07:59 PM PDT 24
Peak memory 207080 kb
Host smart-4816707f-3d0f-495c-9445-1d98f63f54c2
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1336343486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.1336343486
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.3370042523
Short name T100
Test name
Test status
Simulation time 8021472558 ps
CPU time 18.71 seconds
Started Jul 25 07:07:55 PM PDT 24
Finished Jul 25 07:08:14 PM PDT 24
Peak memory 207344 kb
Host smart-1c32ea4f-49f2-44da-9d23-238d49bb2d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33700
42523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.3370042523
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_device_timeout.4038253025
Short name T1763
Test name
Test status
Simulation time 160550251 ps
CPU time 0.9 seconds
Started Jul 25 07:07:58 PM PDT 24
Finished Jul 25 07:07:59 PM PDT 24
Peak memory 207116 kb
Host smart-91afb990-5445-43b1-83af-2ee837a7dbae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038253025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_timeout.4038253025
Directory /workspace/43.usbdev_device_timeout/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.835337034
Short name T542
Test name
Test status
Simulation time 386755286 ps
CPU time 1.34 seconds
Started Jul 25 07:07:53 PM PDT 24
Finished Jul 25 07:07:55 PM PDT 24
Peak memory 207088 kb
Host smart-f7a1f6eb-0a90-4238-b1db-81215d97229d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83533
7034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.835337034
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.3991953437
Short name T862
Test name
Test status
Simulation time 161312962 ps
CPU time 0.91 seconds
Started Jul 25 07:07:55 PM PDT 24
Finished Jul 25 07:07:56 PM PDT 24
Peak memory 207036 kb
Host smart-3efa3134-9b89-4c6d-8bde-feeeace90fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39919
53437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.3991953437
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.1970833631
Short name T1424
Test name
Test status
Simulation time 42529863 ps
CPU time 0.74 seconds
Started Jul 25 07:07:56 PM PDT 24
Finished Jul 25 07:07:57 PM PDT 24
Peak memory 207124 kb
Host smart-9eacc859-8bb8-47e7-ac62-58dd47ee2b6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19708
33631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.1970833631
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.2040618795
Short name T427
Test name
Test status
Simulation time 932463973 ps
CPU time 2.54 seconds
Started Jul 25 07:07:53 PM PDT 24
Finished Jul 25 07:07:56 PM PDT 24
Peak memory 207404 kb
Host smart-800c0eb6-b881-4089-ba28-c4b1a62e5f80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20406
18795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.2040618795
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.1306339129
Short name T1670
Test name
Test status
Simulation time 392237461 ps
CPU time 2.72 seconds
Started Jul 25 07:07:54 PM PDT 24
Finished Jul 25 07:07:57 PM PDT 24
Peak memory 207320 kb
Host smart-05871efa-0c3a-436a-b212-5ec2d578647d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13063
39129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.1306339129
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.1529614421
Short name T2544
Test name
Test status
Simulation time 200617622 ps
CPU time 1.08 seconds
Started Jul 25 07:08:01 PM PDT 24
Finished Jul 25 07:08:02 PM PDT 24
Peak memory 215500 kb
Host smart-357125f2-a0a9-4934-a79d-fdfddc7a906c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1529614421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.1529614421
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.822887749
Short name T1796
Test name
Test status
Simulation time 159433938 ps
CPU time 0.83 seconds
Started Jul 25 07:07:50 PM PDT 24
Finished Jul 25 07:07:51 PM PDT 24
Peak memory 207112 kb
Host smart-bdf7820b-c897-4f42-8e09-fe7823b62c8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82288
7749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.822887749
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.1641282299
Short name T1060
Test name
Test status
Simulation time 197556876 ps
CPU time 0.93 seconds
Started Jul 25 07:08:00 PM PDT 24
Finished Jul 25 07:08:01 PM PDT 24
Peak memory 207116 kb
Host smart-190602cc-9eea-4ac3-90aa-3a7ee9c502cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16412
82299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.1641282299
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.1716981108
Short name T2859
Test name
Test status
Simulation time 8198187664 ps
CPU time 80.65 seconds
Started Jul 25 07:08:01 PM PDT 24
Finished Jul 25 07:09:22 PM PDT 24
Peak memory 217108 kb
Host smart-513fe582-75e1-4a16-a5f0-85451dc2c69d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1716981108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.1716981108
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_iso_retraction.1003117817
Short name T118
Test name
Test status
Simulation time 13121338805 ps
CPU time 162.53 seconds
Started Jul 25 07:07:56 PM PDT 24
Finished Jul 25 07:10:39 PM PDT 24
Peak memory 207448 kb
Host smart-bf429928-5bae-4b1a-ac45-14240e173082
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1003117817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_iso_retraction.1003117817
Directory /workspace/43.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.979374905
Short name T1217
Test name
Test status
Simulation time 221357313 ps
CPU time 0.95 seconds
Started Jul 25 07:07:56 PM PDT 24
Finished Jul 25 07:07:57 PM PDT 24
Peak memory 207152 kb
Host smart-0a37657d-abc9-414b-8a4e-e7c7fd859453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97937
4905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.979374905
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.201653758
Short name T2812
Test name
Test status
Simulation time 23347978633 ps
CPU time 30.07 seconds
Started Jul 25 07:08:42 PM PDT 24
Finished Jul 25 07:09:12 PM PDT 24
Peak memory 207364 kb
Host smart-0ba344b6-af5c-4a5d-ba3c-5cc47a7807be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20165
3758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.201653758
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.1629019576
Short name T1928
Test name
Test status
Simulation time 3322858666 ps
CPU time 5.8 seconds
Started Jul 25 07:07:58 PM PDT 24
Finished Jul 25 07:08:04 PM PDT 24
Peak memory 207376 kb
Host smart-9306b3f7-3a01-44f6-9570-afa7487eda49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16290
19576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.1629019576
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.3028855881
Short name T2052
Test name
Test status
Simulation time 7808711811 ps
CPU time 55.73 seconds
Started Jul 25 07:07:52 PM PDT 24
Finished Jul 25 07:08:48 PM PDT 24
Peak memory 217340 kb
Host smart-5cd783d4-8d9a-4b3c-8214-ca736cadb862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30288
55881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.3028855881
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.1905698513
Short name T2091
Test name
Test status
Simulation time 7144150701 ps
CPU time 74.03 seconds
Started Jul 25 07:07:59 PM PDT 24
Finished Jul 25 07:09:13 PM PDT 24
Peak memory 207532 kb
Host smart-4115ff1b-49af-4e2f-8241-a766ababc459
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1905698513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.1905698513
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.2965905698
Short name T32
Test name
Test status
Simulation time 236492295 ps
CPU time 0.99 seconds
Started Jul 25 07:07:56 PM PDT 24
Finished Jul 25 07:07:57 PM PDT 24
Peak memory 207116 kb
Host smart-b7433c7b-5889-4ec4-ad5e-195dcae4ac0e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2965905698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.2965905698
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.171573763
Short name T2378
Test name
Test status
Simulation time 187274638 ps
CPU time 0.91 seconds
Started Jul 25 07:07:54 PM PDT 24
Finished Jul 25 07:07:55 PM PDT 24
Peak memory 207104 kb
Host smart-196ef5f2-3572-4a2a-8081-dfabc63d6c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17157
3763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.171573763
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.577540689
Short name T795
Test name
Test status
Simulation time 4436046035 ps
CPU time 44.41 seconds
Started Jul 25 07:07:59 PM PDT 24
Finished Jul 25 07:08:43 PM PDT 24
Peak memory 215532 kb
Host smart-0b00bad7-ea19-4123-8f56-b0b4c951a045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57754
0689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.577540689
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.750030704
Short name T2510
Test name
Test status
Simulation time 6143936357 ps
CPU time 185.2 seconds
Started Jul 25 07:08:00 PM PDT 24
Finished Jul 25 07:11:05 PM PDT 24
Peak memory 215624 kb
Host smart-9f97f227-5375-4f50-ba5f-512ab34b5c2b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=750030704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.750030704
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.1116131639
Short name T526
Test name
Test status
Simulation time 163938568 ps
CPU time 0.86 seconds
Started Jul 25 07:07:57 PM PDT 24
Finished Jul 25 07:07:58 PM PDT 24
Peak memory 207132 kb
Host smart-6483c9af-5c7f-4f99-a8bd-706a8c565b2d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1116131639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.1116131639
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.2703123982
Short name T1738
Test name
Test status
Simulation time 152432716 ps
CPU time 0.83 seconds
Started Jul 25 07:08:02 PM PDT 24
Finished Jul 25 07:08:03 PM PDT 24
Peak memory 207120 kb
Host smart-f4cbcaf1-7bca-49d5-ac7a-d0350dfcba01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27031
23982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.2703123982
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.3006370696
Short name T2249
Test name
Test status
Simulation time 206173018 ps
CPU time 0.97 seconds
Started Jul 25 07:07:58 PM PDT 24
Finished Jul 25 07:07:59 PM PDT 24
Peak memory 207152 kb
Host smart-b47a3955-0d56-42e8-8d90-99fc7992559e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30063
70696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.3006370696
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.818976332
Short name T823
Test name
Test status
Simulation time 172192499 ps
CPU time 0.92 seconds
Started Jul 25 07:07:56 PM PDT 24
Finished Jul 25 07:07:57 PM PDT 24
Peak memory 207120 kb
Host smart-a9567832-98e8-4753-926f-5381ff838101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81897
6332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.818976332
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.1856974853
Short name T1248
Test name
Test status
Simulation time 163361944 ps
CPU time 0.82 seconds
Started Jul 25 07:07:57 PM PDT 24
Finished Jul 25 07:07:58 PM PDT 24
Peak memory 207088 kb
Host smart-62517278-b08c-430b-9d8c-366f8c4f549f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18569
74853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.1856974853
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.4079270819
Short name T231
Test name
Test status
Simulation time 179373702 ps
CPU time 0.88 seconds
Started Jul 25 07:07:57 PM PDT 24
Finished Jul 25 07:07:58 PM PDT 24
Peak memory 207108 kb
Host smart-01852c3b-ca9a-4422-9462-9a6caf8b13a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40792
70819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.4079270819
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.2183255387
Short name T1789
Test name
Test status
Simulation time 146504846 ps
CPU time 0.85 seconds
Started Jul 25 07:07:55 PM PDT 24
Finished Jul 25 07:07:56 PM PDT 24
Peak memory 207112 kb
Host smart-799ade57-f405-4995-b6f7-f78230fee46d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21832
55387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.2183255387
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.3258823583
Short name T1674
Test name
Test status
Simulation time 211042042 ps
CPU time 1.02 seconds
Started Jul 25 07:07:55 PM PDT 24
Finished Jul 25 07:07:56 PM PDT 24
Peak memory 207192 kb
Host smart-6d32f6a8-11f1-40a9-85ad-8c65d47f61d9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3258823583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.3258823583
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.843293454
Short name T1697
Test name
Test status
Simulation time 165645309 ps
CPU time 0.85 seconds
Started Jul 25 07:07:56 PM PDT 24
Finished Jul 25 07:07:57 PM PDT 24
Peak memory 207108 kb
Host smart-3560f533-03b7-4b8b-9e2e-1b63e69b739d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84329
3454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.843293454
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.1063602128
Short name T924
Test name
Test status
Simulation time 28315959 ps
CPU time 0.69 seconds
Started Jul 25 07:07:58 PM PDT 24
Finished Jul 25 07:07:59 PM PDT 24
Peak memory 207092 kb
Host smart-4111075e-b5bf-4a41-b25b-5d4ed7054edb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10636
02128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.1063602128
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.1539049321
Short name T1279
Test name
Test status
Simulation time 5946001578 ps
CPU time 14.28 seconds
Started Jul 25 07:08:03 PM PDT 24
Finished Jul 25 07:08:17 PM PDT 24
Peak memory 223796 kb
Host smart-0464a0f5-a384-4831-b20a-142dcd23f3bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15390
49321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.1539049321
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.3374906558
Short name T2478
Test name
Test status
Simulation time 259433628 ps
CPU time 1.01 seconds
Started Jul 25 07:07:55 PM PDT 24
Finished Jul 25 07:07:57 PM PDT 24
Peak memory 207136 kb
Host smart-fd77f396-2792-435c-81f1-c4fd68ee7e0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33749
06558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.3374906558
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.1518580518
Short name T390
Test name
Test status
Simulation time 161067497 ps
CPU time 0.91 seconds
Started Jul 25 07:08:02 PM PDT 24
Finished Jul 25 07:08:03 PM PDT 24
Peak memory 207080 kb
Host smart-caabc22f-dd35-4343-a2f1-7bd9fd45286e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15185
80518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.1518580518
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.2961985129
Short name T1585
Test name
Test status
Simulation time 183503052 ps
CPU time 0.94 seconds
Started Jul 25 07:07:56 PM PDT 24
Finished Jul 25 07:07:57 PM PDT 24
Peak memory 207108 kb
Host smart-9d5df901-96c1-46be-b00f-07179383d04f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29619
85129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.2961985129
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.1473858199
Short name T2476
Test name
Test status
Simulation time 184663382 ps
CPU time 0.89 seconds
Started Jul 25 07:07:53 PM PDT 24
Finished Jul 25 07:07:54 PM PDT 24
Peak memory 207084 kb
Host smart-90813cf5-252a-472a-bd37-4fd7843cc120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14738
58199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.1473858199
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.3436443457
Short name T869
Test name
Test status
Simulation time 142790251 ps
CPU time 0.78 seconds
Started Jul 25 07:07:59 PM PDT 24
Finished Jul 25 07:08:00 PM PDT 24
Peak memory 207124 kb
Host smart-8b3fd7e2-cb53-45a7-9c57-e6c021b60d41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34364
43457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.3436443457
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.1389255683
Short name T2299
Test name
Test status
Simulation time 174304388 ps
CPU time 0.86 seconds
Started Jul 25 07:07:57 PM PDT 24
Finished Jul 25 07:07:58 PM PDT 24
Peak memory 207120 kb
Host smart-3dd8d932-04f3-479d-bf97-73e151f98c80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13892
55683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.1389255683
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.2187879162
Short name T1167
Test name
Test status
Simulation time 159991083 ps
CPU time 0.86 seconds
Started Jul 25 07:07:58 PM PDT 24
Finished Jul 25 07:07:59 PM PDT 24
Peak memory 207088 kb
Host smart-9c7bea84-5511-44db-85c0-da4c1b51371d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21878
79162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.2187879162
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.4023502888
Short name T1317
Test name
Test status
Simulation time 189604093 ps
CPU time 0.91 seconds
Started Jul 25 07:07:53 PM PDT 24
Finished Jul 25 07:07:54 PM PDT 24
Peak memory 207212 kb
Host smart-e05f6373-2867-4e32-bcf4-b13152419c1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40235
02888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.4023502888
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.1364990529
Short name T794
Test name
Test status
Simulation time 4949630962 ps
CPU time 147.77 seconds
Started Jul 25 07:07:56 PM PDT 24
Finished Jul 25 07:10:24 PM PDT 24
Peak memory 215664 kb
Host smart-7a54f1ea-f18b-4fe4-ad2e-11c1c421b916
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1364990529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.1364990529
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.4284465483
Short name T229
Test name
Test status
Simulation time 210841193 ps
CPU time 0.93 seconds
Started Jul 25 07:07:58 PM PDT 24
Finished Jul 25 07:07:59 PM PDT 24
Peak memory 207132 kb
Host smart-772172c8-87e4-4c05-91d6-80258faf8750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42844
65483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.4284465483
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.2538235983
Short name T1988
Test name
Test status
Simulation time 193655576 ps
CPU time 0.94 seconds
Started Jul 25 07:07:58 PM PDT 24
Finished Jul 25 07:07:59 PM PDT 24
Peak memory 207112 kb
Host smart-2afdb66a-6bb1-43dc-8ac4-179a0920e677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25382
35983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.2538235983
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.2690010087
Short name T1894
Test name
Test status
Simulation time 462056498 ps
CPU time 1.47 seconds
Started Jul 25 07:07:56 PM PDT 24
Finished Jul 25 07:07:58 PM PDT 24
Peak memory 207112 kb
Host smart-dfbfdbf6-e78f-4a9c-9a6a-c9f26a4b2f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26900
10087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.2690010087
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.1257756374
Short name T1510
Test name
Test status
Simulation time 5510159559 ps
CPU time 44.91 seconds
Started Jul 25 07:08:00 PM PDT 24
Finished Jul 25 07:08:45 PM PDT 24
Peak memory 217076 kb
Host smart-5d9c28f9-26bf-4449-9876-1610f7be84f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12577
56374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.1257756374
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_timeout_missing_host_handshake.568559276
Short name T2374
Test name
Test status
Simulation time 840512766 ps
CPU time 5.31 seconds
Started Jul 25 07:07:58 PM PDT 24
Finished Jul 25 07:08:03 PM PDT 24
Peak memory 207284 kb
Host smart-66418ed7-e075-43d1-8fd1-7dce2ee2610a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568559276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_timeout_missing_host
_handshake.568559276
Directory /workspace/43.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.165552847
Short name T1860
Test name
Test status
Simulation time 33397452 ps
CPU time 0.68 seconds
Started Jul 25 07:08:02 PM PDT 24
Finished Jul 25 07:08:03 PM PDT 24
Peak memory 207172 kb
Host smart-2a39c21f-8f8c-48d1-ad0c-ddb268a2f73b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=165552847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.165552847
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.628828136
Short name T1981
Test name
Test status
Simulation time 3754519225 ps
CPU time 5.58 seconds
Started Jul 25 07:07:55 PM PDT 24
Finished Jul 25 07:08:01 PM PDT 24
Peak memory 207348 kb
Host smart-3f189ae7-0199-43c7-bf8b-b35d297f5d9d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628828136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_ao
n_wake_disconnect.628828136
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.1702862379
Short name T2009
Test name
Test status
Simulation time 13436939580 ps
CPU time 16.55 seconds
Started Jul 25 07:07:57 PM PDT 24
Finished Jul 25 07:08:14 PM PDT 24
Peak memory 207368 kb
Host smart-af82d46b-bc45-43df-953b-19c74f9b87b3
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702862379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.1702862379
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.2833779581
Short name T1442
Test name
Test status
Simulation time 23415660213 ps
CPU time 29.35 seconds
Started Jul 25 07:08:02 PM PDT 24
Finished Jul 25 07:08:32 PM PDT 24
Peak memory 207392 kb
Host smart-8d881593-505e-4bf8-9e67-bb165f90414a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833779581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_a
on_wake_resume.2833779581
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.1239621653
Short name T2376
Test name
Test status
Simulation time 161099237 ps
CPU time 0.83 seconds
Started Jul 25 07:07:54 PM PDT 24
Finished Jul 25 07:07:55 PM PDT 24
Peak memory 207148 kb
Host smart-ad71cfa5-f01f-4dde-ac47-9683f69d6dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12396
21653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.1239621653
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.1338552619
Short name T992
Test name
Test status
Simulation time 143525808 ps
CPU time 0.83 seconds
Started Jul 25 07:07:57 PM PDT 24
Finished Jul 25 07:07:58 PM PDT 24
Peak memory 207076 kb
Host smart-4f817635-41bd-4041-a5db-f77551c01462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13385
52619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.1338552619
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.3107955272
Short name T2841
Test name
Test status
Simulation time 147725256 ps
CPU time 0.82 seconds
Started Jul 25 07:07:54 PM PDT 24
Finished Jul 25 07:07:55 PM PDT 24
Peak memory 207092 kb
Host smart-4309ba32-5d0b-4982-90d0-3fafdd709aca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31079
55272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.3107955272
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.2993024293
Short name T1821
Test name
Test status
Simulation time 961196652 ps
CPU time 2.42 seconds
Started Jul 25 07:07:49 PM PDT 24
Finished Jul 25 07:07:52 PM PDT 24
Peak memory 207380 kb
Host smart-9450f89a-34b4-4f7c-8f1a-b2b3019e14f9
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2993024293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.2993024293
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.2709603047
Short name T332
Test name
Test status
Simulation time 8988869056 ps
CPU time 17.43 seconds
Started Jul 25 07:07:58 PM PDT 24
Finished Jul 25 07:08:16 PM PDT 24
Peak memory 207340 kb
Host smart-bc7127b8-b723-49a5-8d67-5c5847e2ba38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27096
03047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.2709603047
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_device_timeout.1963441860
Short name T2769
Test name
Test status
Simulation time 203135629 ps
CPU time 1.02 seconds
Started Jul 25 07:07:58 PM PDT 24
Finished Jul 25 07:08:00 PM PDT 24
Peak memory 207108 kb
Host smart-e2d297fa-8792-467b-9497-8567daab6927
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963441860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_timeout.1963441860
Directory /workspace/44.usbdev_device_timeout/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.2352958762
Short name T261
Test name
Test status
Simulation time 460746461 ps
CPU time 1.51 seconds
Started Jul 25 07:07:58 PM PDT 24
Finished Jul 25 07:08:00 PM PDT 24
Peak memory 207044 kb
Host smart-a2cbab72-5f5b-432a-b7d1-8524a74ca75a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23529
58762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.2352958762
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.4255333404
Short name T2368
Test name
Test status
Simulation time 154342430 ps
CPU time 0.87 seconds
Started Jul 25 07:07:54 PM PDT 24
Finished Jul 25 07:07:55 PM PDT 24
Peak memory 207100 kb
Host smart-d61b9cef-d0c8-4d12-8bf7-3810ce6a89dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42553
33404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.4255333404
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.3571007984
Short name T2188
Test name
Test status
Simulation time 73112848 ps
CPU time 0.73 seconds
Started Jul 25 07:07:54 PM PDT 24
Finished Jul 25 07:07:55 PM PDT 24
Peak memory 207072 kb
Host smart-d3204514-356e-45e1-bfb2-c8b22805af97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35710
07984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.3571007984
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.2328794619
Short name T30
Test name
Test status
Simulation time 979468217 ps
CPU time 2.68 seconds
Started Jul 25 07:07:57 PM PDT 24
Finished Jul 25 07:08:00 PM PDT 24
Peak memory 207308 kb
Host smart-373ec416-95fc-4099-9e42-c26bc074e098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23287
94619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.2328794619
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.1142768403
Short name T478
Test name
Test status
Simulation time 153169401 ps
CPU time 1.34 seconds
Started Jul 25 07:08:03 PM PDT 24
Finished Jul 25 07:08:04 PM PDT 24
Peak memory 207296 kb
Host smart-56378a5b-6dc0-4264-a1da-8686747d282f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11427
68403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.1142768403
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.994656200
Short name T2810
Test name
Test status
Simulation time 195801771 ps
CPU time 1.04 seconds
Started Jul 25 07:07:59 PM PDT 24
Finished Jul 25 07:08:00 PM PDT 24
Peak memory 215464 kb
Host smart-009d1af2-77ed-40ea-ac46-1b5d3292210e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=994656200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.994656200
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.2662279667
Short name T1359
Test name
Test status
Simulation time 174080982 ps
CPU time 0.83 seconds
Started Jul 25 07:07:55 PM PDT 24
Finished Jul 25 07:07:56 PM PDT 24
Peak memory 207084 kb
Host smart-d2351bdd-70dc-437c-b592-9df65897f417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26622
79667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.2662279667
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.2795727382
Short name T910
Test name
Test status
Simulation time 287824992 ps
CPU time 1.08 seconds
Started Jul 25 07:08:03 PM PDT 24
Finished Jul 25 07:08:04 PM PDT 24
Peak memory 207144 kb
Host smart-3d9c9993-d7da-4fa4-9e49-67d779c0c7c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27957
27382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.2795727382
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.2728611649
Short name T406
Test name
Test status
Simulation time 10004107004 ps
CPU time 106.61 seconds
Started Jul 25 07:07:59 PM PDT 24
Finished Jul 25 07:09:46 PM PDT 24
Peak memory 216896 kb
Host smart-73a102b7-d108-415e-aeb0-7073ddc34d57
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2728611649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.2728611649
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_iso_retraction.1475200367
Short name T2067
Test name
Test status
Simulation time 4539519813 ps
CPU time 29.93 seconds
Started Jul 25 07:07:59 PM PDT 24
Finished Jul 25 07:08:29 PM PDT 24
Peak memory 207344 kb
Host smart-5b12c85a-0ef8-4695-93fc-5f6580edde16
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1475200367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_iso_retraction.1475200367
Directory /workspace/44.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.2169459063
Short name T2590
Test name
Test status
Simulation time 213974635 ps
CPU time 0.94 seconds
Started Jul 25 07:08:05 PM PDT 24
Finished Jul 25 07:08:06 PM PDT 24
Peak memory 207124 kb
Host smart-b1253b1f-dc76-4750-a236-2d3f3b1ab209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21694
59063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.2169459063
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.983291917
Short name T705
Test name
Test status
Simulation time 23350045796 ps
CPU time 28.54 seconds
Started Jul 25 07:07:57 PM PDT 24
Finished Jul 25 07:08:26 PM PDT 24
Peak memory 207364 kb
Host smart-66d21659-6061-4e3d-9f86-62ce16325dab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98329
1917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.983291917
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.2018048948
Short name T1394
Test name
Test status
Simulation time 3350020209 ps
CPU time 5.18 seconds
Started Jul 25 07:07:54 PM PDT 24
Finished Jul 25 07:07:59 PM PDT 24
Peak memory 207364 kb
Host smart-22e0d016-5248-40f6-b1b2-08bf6d45c5cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20180
48948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.2018048948
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.3971855064
Short name T2388
Test name
Test status
Simulation time 6174593199 ps
CPU time 62.02 seconds
Started Jul 25 07:07:55 PM PDT 24
Finished Jul 25 07:08:58 PM PDT 24
Peak memory 223712 kb
Host smart-149df4de-6841-4f7e-bd0e-9990e61ce719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39718
55064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.3971855064
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.4054000320
Short name T2396
Test name
Test status
Simulation time 2939545918 ps
CPU time 87.38 seconds
Started Jul 25 07:07:59 PM PDT 24
Finished Jul 25 07:09:26 PM PDT 24
Peak memory 215680 kb
Host smart-cfbc5584-1e29-43ec-9908-c2b50437ace3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4054000320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.4054000320
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.147562678
Short name T611
Test name
Test status
Simulation time 246766665 ps
CPU time 0.99 seconds
Started Jul 25 07:07:58 PM PDT 24
Finished Jul 25 07:07:59 PM PDT 24
Peak memory 207144 kb
Host smart-77a7f617-b5c6-4baf-abcc-807cb706c34c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=147562678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.147562678
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.2172688222
Short name T2625
Test name
Test status
Simulation time 200113043 ps
CPU time 1.03 seconds
Started Jul 25 07:08:02 PM PDT 24
Finished Jul 25 07:08:03 PM PDT 24
Peak memory 207132 kb
Host smart-91a2d5f2-fe42-4e69-b0c9-ad319234c225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21726
88222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.2172688222
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.1046718143
Short name T2026
Test name
Test status
Simulation time 3397665504 ps
CPU time 98.22 seconds
Started Jul 25 07:07:58 PM PDT 24
Finished Jul 25 07:09:37 PM PDT 24
Peak memory 215620 kb
Host smart-df943446-8448-4f44-a597-b3d8573763e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10467
18143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.1046718143
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.53386918
Short name T847
Test name
Test status
Simulation time 4097709267 ps
CPU time 42.31 seconds
Started Jul 25 07:07:59 PM PDT 24
Finished Jul 25 07:08:42 PM PDT 24
Peak memory 215524 kb
Host smart-8c59e59b-4811-4ae1-a2df-84ce5e855ece
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=53386918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.53386918
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.4270522221
Short name T1905
Test name
Test status
Simulation time 152384787 ps
CPU time 0.87 seconds
Started Jul 25 07:08:01 PM PDT 24
Finished Jul 25 07:08:02 PM PDT 24
Peak memory 207116 kb
Host smart-981feeca-55ed-40ed-8fb3-1959445adb43
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4270522221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.4270522221
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.1282920931
Short name T1342
Test name
Test status
Simulation time 152722605 ps
CPU time 0.85 seconds
Started Jul 25 07:07:58 PM PDT 24
Finished Jul 25 07:07:59 PM PDT 24
Peak memory 207096 kb
Host smart-166c7a2d-b1b8-4d46-be17-0a3012fa3778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12829
20931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.1282920931
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.506649973
Short name T2600
Test name
Test status
Simulation time 200595127 ps
CPU time 0.97 seconds
Started Jul 25 07:08:02 PM PDT 24
Finished Jul 25 07:08:03 PM PDT 24
Peak memory 207120 kb
Host smart-9640895d-6136-4004-8467-d5d2e32bc551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50664
9973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.506649973
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.139016159
Short name T2543
Test name
Test status
Simulation time 201643159 ps
CPU time 0.86 seconds
Started Jul 25 07:07:55 PM PDT 24
Finished Jul 25 07:07:56 PM PDT 24
Peak memory 207112 kb
Host smart-34dded27-c50f-43a2-adbd-87dfd5ccf9a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13901
6159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.139016159
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.2790880541
Short name T2460
Test name
Test status
Simulation time 184832306 ps
CPU time 0.94 seconds
Started Jul 25 07:08:02 PM PDT 24
Finished Jul 25 07:08:03 PM PDT 24
Peak memory 207132 kb
Host smart-74ebee1c-ba40-4ea1-9713-bef59af348d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27908
80541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.2790880541
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.2697889643
Short name T2788
Test name
Test status
Simulation time 184655690 ps
CPU time 0.95 seconds
Started Jul 25 07:07:58 PM PDT 24
Finished Jul 25 07:07:59 PM PDT 24
Peak memory 207128 kb
Host smart-8f4b7560-a39d-4113-a6d1-990503fdbeda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26978
89643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.2697889643
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.3654901608
Short name T552
Test name
Test status
Simulation time 144530995 ps
CPU time 0.89 seconds
Started Jul 25 07:07:57 PM PDT 24
Finished Jul 25 07:07:59 PM PDT 24
Peak memory 207112 kb
Host smart-ed950802-2521-4941-bb26-ddf81279e99a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36549
01608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.3654901608
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.1696680773
Short name T59
Test name
Test status
Simulation time 305447327 ps
CPU time 1.15 seconds
Started Jul 25 07:08:01 PM PDT 24
Finished Jul 25 07:08:02 PM PDT 24
Peak memory 207172 kb
Host smart-1a577f9f-8fc9-49e2-ac99-a63fe57c9440
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1696680773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.1696680773
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.4239709314
Short name T1024
Test name
Test status
Simulation time 143561997 ps
CPU time 0.86 seconds
Started Jul 25 07:07:56 PM PDT 24
Finished Jul 25 07:07:57 PM PDT 24
Peak memory 207100 kb
Host smart-e7b30df2-e3de-4de6-a704-250f4aedd1e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42397
09314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.4239709314
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.3118696353
Short name T2783
Test name
Test status
Simulation time 38185561 ps
CPU time 0.74 seconds
Started Jul 25 07:07:59 PM PDT 24
Finished Jul 25 07:08:00 PM PDT 24
Peak memory 207124 kb
Host smart-de5f8fec-782c-4612-a115-1696929fbd27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31186
96353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.3118696353
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.2440530517
Short name T1203
Test name
Test status
Simulation time 16422068668 ps
CPU time 43.58 seconds
Started Jul 25 07:07:56 PM PDT 24
Finished Jul 25 07:08:39 PM PDT 24
Peak memory 215560 kb
Host smart-a1771cfa-68d6-41a3-9e18-dd1522612fdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24405
30517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.2440530517
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.2521992852
Short name T2606
Test name
Test status
Simulation time 176116039 ps
CPU time 0.91 seconds
Started Jul 25 07:07:59 PM PDT 24
Finished Jul 25 07:08:00 PM PDT 24
Peak memory 207116 kb
Host smart-bd90c242-e5db-4e7b-b638-1a3cbe668b2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25219
92852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.2521992852
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.1854638830
Short name T1703
Test name
Test status
Simulation time 252394314 ps
CPU time 1.01 seconds
Started Jul 25 07:07:57 PM PDT 24
Finished Jul 25 07:07:58 PM PDT 24
Peak memory 207096 kb
Host smart-2a5d40b8-2186-41ca-920a-9885eaa9780d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18546
38830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.1854638830
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.43805052
Short name T919
Test name
Test status
Simulation time 178201747 ps
CPU time 0.85 seconds
Started Jul 25 07:07:57 PM PDT 24
Finished Jul 25 07:07:58 PM PDT 24
Peak memory 207124 kb
Host smart-21f92e66-5d5d-42b4-8fe8-a94479a6d941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43805
052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.43805052
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.40329237
Short name T2264
Test name
Test status
Simulation time 169745948 ps
CPU time 0.86 seconds
Started Jul 25 07:08:00 PM PDT 24
Finished Jul 25 07:08:01 PM PDT 24
Peak memory 207188 kb
Host smart-88e36c0c-2e24-42a7-ba5a-a6b012287152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40329
237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.40329237
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.47043738
Short name T2797
Test name
Test status
Simulation time 197880503 ps
CPU time 0.91 seconds
Started Jul 25 07:08:02 PM PDT 24
Finished Jul 25 07:08:03 PM PDT 24
Peak memory 207160 kb
Host smart-ad19deb8-16e7-4d6e-baef-30b55bb772bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47043
738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.47043738
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.2817365889
Short name T31
Test name
Test status
Simulation time 163834227 ps
CPU time 0.9 seconds
Started Jul 25 07:08:03 PM PDT 24
Finished Jul 25 07:08:04 PM PDT 24
Peak memory 207104 kb
Host smart-2a836952-eccb-411f-ab93-ddb0d273c702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28173
65889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.2817365889
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.3339980558
Short name T454
Test name
Test status
Simulation time 173945506 ps
CPU time 0.86 seconds
Started Jul 25 07:08:00 PM PDT 24
Finished Jul 25 07:08:01 PM PDT 24
Peak memory 207132 kb
Host smart-66bc019e-46dc-41d0-a493-0672bf2e61ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33399
80558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.3339980558
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.4289005256
Short name T487
Test name
Test status
Simulation time 258413029 ps
CPU time 1.04 seconds
Started Jul 25 07:07:57 PM PDT 24
Finished Jul 25 07:07:59 PM PDT 24
Peak memory 207112 kb
Host smart-49929a80-2a3f-4227-ac33-76a24611e024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42890
05256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.4289005256
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.2857017451
Short name T2828
Test name
Test status
Simulation time 4021180039 ps
CPU time 29.73 seconds
Started Jul 25 07:08:11 PM PDT 24
Finished Jul 25 07:08:41 PM PDT 24
Peak memory 215592 kb
Host smart-da04b1b9-897e-4ac9-96e7-90c072b889d9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2857017451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.2857017451
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.685188219
Short name T979
Test name
Test status
Simulation time 202422004 ps
CPU time 0.92 seconds
Started Jul 25 07:08:11 PM PDT 24
Finished Jul 25 07:08:12 PM PDT 24
Peak memory 207104 kb
Host smart-fb0f803a-50dd-49c3-8689-227cde4407f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68518
8219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.685188219
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.3644002769
Short name T1083
Test name
Test status
Simulation time 174959008 ps
CPU time 0.83 seconds
Started Jul 25 07:08:00 PM PDT 24
Finished Jul 25 07:08:01 PM PDT 24
Peak memory 207192 kb
Host smart-13483eba-8dfe-46f0-b372-b2371356a9b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36440
02769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.3644002769
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.1435823845
Short name T1546
Test name
Test status
Simulation time 756522269 ps
CPU time 2.07 seconds
Started Jul 25 07:08:03 PM PDT 24
Finished Jul 25 07:08:05 PM PDT 24
Peak memory 207116 kb
Host smart-fafd39aa-4112-4a7a-8dc9-eec54241e075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14358
23845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.1435823845
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.618417482
Short name T2308
Test name
Test status
Simulation time 4096136677 ps
CPU time 39.75 seconds
Started Jul 25 07:08:00 PM PDT 24
Finished Jul 25 07:08:40 PM PDT 24
Peak memory 207432 kb
Host smart-68e13a03-a78d-4b0f-926a-9c7d77c6bc58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61841
7482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.618417482
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_timeout_missing_host_handshake.3903966769
Short name T1238
Test name
Test status
Simulation time 2053833957 ps
CPU time 17.44 seconds
Started Jul 25 07:08:07 PM PDT 24
Finished Jul 25 07:08:25 PM PDT 24
Peak memory 207360 kb
Host smart-44544b0a-d6fa-4c09-a434-11db49a62c89
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903966769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_timeout_missing_hos
t_handshake.3903966769
Directory /workspace/44.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.1265927450
Short name T1595
Test name
Test status
Simulation time 89492963 ps
CPU time 0.73 seconds
Started Jul 25 07:08:10 PM PDT 24
Finished Jul 25 07:08:10 PM PDT 24
Peak memory 207164 kb
Host smart-f652bb1b-8f79-41fd-8328-a6c42069e33e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1265927450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.1265927450
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.131822835
Short name T2748
Test name
Test status
Simulation time 4491944940 ps
CPU time 6.41 seconds
Started Jul 25 07:08:01 PM PDT 24
Finished Jul 25 07:08:07 PM PDT 24
Peak memory 207372 kb
Host smart-9aa8a888-18a2-4cab-bab9-58b9eb6716a2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131822835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_ao
n_wake_disconnect.131822835
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.1080981660
Short name T2001
Test name
Test status
Simulation time 13308141417 ps
CPU time 14.7 seconds
Started Jul 25 07:08:02 PM PDT 24
Finished Jul 25 07:08:16 PM PDT 24
Peak memory 207504 kb
Host smart-b501dd6b-ed07-4aa2-8536-7db450914e20
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080981660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.1080981660
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.3894313564
Short name T1042
Test name
Test status
Simulation time 23373658854 ps
CPU time 27.89 seconds
Started Jul 25 07:08:12 PM PDT 24
Finished Jul 25 07:08:40 PM PDT 24
Peak memory 207360 kb
Host smart-76fd0b67-979c-4240-ab3c-0c21946d508b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894313564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_a
on_wake_resume.3894313564
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.809786511
Short name T2335
Test name
Test status
Simulation time 144736815 ps
CPU time 0.87 seconds
Started Jul 25 07:08:04 PM PDT 24
Finished Jul 25 07:08:05 PM PDT 24
Peak memory 207140 kb
Host smart-bd1f8356-aaae-4df4-97d6-3eeade58c7ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80978
6511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.809786511
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.4118182776
Short name T2765
Test name
Test status
Simulation time 198138195 ps
CPU time 0.85 seconds
Started Jul 25 07:08:03 PM PDT 24
Finished Jul 25 07:08:04 PM PDT 24
Peak memory 207120 kb
Host smart-5b6c5624-cb01-4977-9179-486b4d0dc168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41181
82776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.4118182776
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.326223215
Short name T2092
Test name
Test status
Simulation time 547577078 ps
CPU time 1.92 seconds
Started Jul 25 07:08:10 PM PDT 24
Finished Jul 25 07:08:12 PM PDT 24
Peak memory 207136 kb
Host smart-7905dad0-4bc3-4c48-a989-734d10b1e4b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32622
3215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.326223215
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.2667572519
Short name T1403
Test name
Test status
Simulation time 422290592 ps
CPU time 1.37 seconds
Started Jul 25 07:08:01 PM PDT 24
Finished Jul 25 07:08:02 PM PDT 24
Peak memory 207128 kb
Host smart-62d7da4f-6c52-406a-af63-21a963dbbe70
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2667572519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.2667572519
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.3480905222
Short name T2611
Test name
Test status
Simulation time 18522400682 ps
CPU time 43.53 seconds
Started Jul 25 07:08:10 PM PDT 24
Finished Jul 25 07:08:54 PM PDT 24
Peak memory 207408 kb
Host smart-59961fff-5f8b-47fd-b69e-c09571e4f2ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34809
05222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.3480905222
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_device_timeout.1213397598
Short name T1069
Test name
Test status
Simulation time 1537266474 ps
CPU time 9.82 seconds
Started Jul 25 07:08:07 PM PDT 24
Finished Jul 25 07:08:17 PM PDT 24
Peak memory 207232 kb
Host smart-25f57073-98da-4970-9a27-11759f16f1ef
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213397598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_timeout.1213397598
Directory /workspace/45.usbdev_device_timeout/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.3176435657
Short name T755
Test name
Test status
Simulation time 395931482 ps
CPU time 1.52 seconds
Started Jul 25 07:08:08 PM PDT 24
Finished Jul 25 07:08:09 PM PDT 24
Peak memory 207052 kb
Host smart-dddf68e3-9953-4e8a-b878-c1031079e3b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31764
35657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.3176435657
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.1402232208
Short name T2728
Test name
Test status
Simulation time 205900677 ps
CPU time 0.91 seconds
Started Jul 25 07:07:59 PM PDT 24
Finished Jul 25 07:08:00 PM PDT 24
Peak memory 207088 kb
Host smart-fb5f0b46-23a4-4b0d-bc9b-4dc848a9ecfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14022
32208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.1402232208
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.1733986777
Short name T1891
Test name
Test status
Simulation time 53972489 ps
CPU time 0.73 seconds
Started Jul 25 07:08:02 PM PDT 24
Finished Jul 25 07:08:03 PM PDT 24
Peak memory 207104 kb
Host smart-7ff2dbfd-487f-41b7-acc1-e90d437a35a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17339
86777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.1733986777
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.4176063028
Short name T1089
Test name
Test status
Simulation time 903403699 ps
CPU time 2.53 seconds
Started Jul 25 07:08:02 PM PDT 24
Finished Jul 25 07:08:05 PM PDT 24
Peak memory 207316 kb
Host smart-dc3243cf-cdaa-4481-a2dc-08d758f39412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41760
63028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.4176063028
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.2118082289
Short name T199
Test name
Test status
Simulation time 216962877 ps
CPU time 1.54 seconds
Started Jul 25 07:07:59 PM PDT 24
Finished Jul 25 07:08:01 PM PDT 24
Peak memory 207292 kb
Host smart-981cc399-b5f5-4af7-b7d6-a5dd0073f5e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21180
82289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.2118082289
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.752489348
Short name T1982
Test name
Test status
Simulation time 217563821 ps
CPU time 1.13 seconds
Started Jul 25 07:08:20 PM PDT 24
Finished Jul 25 07:08:21 PM PDT 24
Peak memory 215360 kb
Host smart-f61e0ebd-be4e-42de-9478-e12f8185ba72
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=752489348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.752489348
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.2300334737
Short name T2837
Test name
Test status
Simulation time 147082943 ps
CPU time 0.86 seconds
Started Jul 25 07:08:02 PM PDT 24
Finished Jul 25 07:08:03 PM PDT 24
Peak memory 207136 kb
Host smart-51d94461-1531-4f42-aaf6-89225d558ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23003
34737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.2300334737
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.278674961
Short name T1385
Test name
Test status
Simulation time 212977896 ps
CPU time 0.95 seconds
Started Jul 25 07:08:01 PM PDT 24
Finished Jul 25 07:08:02 PM PDT 24
Peak memory 207144 kb
Host smart-733133cd-f147-4c87-9bfb-46b529547cb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27867
4961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.278674961
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.3775432689
Short name T2642
Test name
Test status
Simulation time 5976782909 ps
CPU time 50.76 seconds
Started Jul 25 07:07:59 PM PDT 24
Finished Jul 25 07:08:50 PM PDT 24
Peak memory 215636 kb
Host smart-9b7013ca-5e09-4772-ba83-caee11fa04c9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3775432689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.3775432689
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_iso_retraction.3368556825
Short name T412
Test name
Test status
Simulation time 9927404678 ps
CPU time 71.35 seconds
Started Jul 25 07:08:04 PM PDT 24
Finished Jul 25 07:09:16 PM PDT 24
Peak memory 207380 kb
Host smart-c184e887-6cb4-4509-84fa-915da133728e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3368556825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_iso_retraction.3368556825
Directory /workspace/45.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.3765074894
Short name T545
Test name
Test status
Simulation time 232017439 ps
CPU time 1.04 seconds
Started Jul 25 07:08:04 PM PDT 24
Finished Jul 25 07:08:06 PM PDT 24
Peak memory 207136 kb
Host smart-70d99fad-ed18-4365-98b9-33488feb6957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37650
74894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.3765074894
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.1697002443
Short name T828
Test name
Test status
Simulation time 23350046009 ps
CPU time 32.38 seconds
Started Jul 25 07:08:01 PM PDT 24
Finished Jul 25 07:08:33 PM PDT 24
Peak memory 207336 kb
Host smart-244d1204-4e79-4ca2-b12d-5eb4cd62d2e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16970
02443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.1697002443
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.3841825174
Short name T2023
Test name
Test status
Simulation time 3313227753 ps
CPU time 4.86 seconds
Started Jul 25 07:08:07 PM PDT 24
Finished Jul 25 07:08:12 PM PDT 24
Peak memory 207364 kb
Host smart-f884f04a-3880-4d0c-90e2-5cb99592a22b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38418
25174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.3841825174
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.2326214577
Short name T495
Test name
Test status
Simulation time 7314529090 ps
CPU time 71.09 seconds
Started Jul 25 07:08:03 PM PDT 24
Finished Jul 25 07:09:14 PM PDT 24
Peak memory 223768 kb
Host smart-433358f8-ab80-4f65-b060-b684d0f2776b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23262
14577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.2326214577
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.2279785307
Short name T2400
Test name
Test status
Simulation time 4474989577 ps
CPU time 133.12 seconds
Started Jul 25 07:08:02 PM PDT 24
Finished Jul 25 07:10:16 PM PDT 24
Peak memory 215644 kb
Host smart-b704795b-c4cf-4805-b950-f52dbb5c6fd0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2279785307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.2279785307
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.3465778498
Short name T2025
Test name
Test status
Simulation time 294682348 ps
CPU time 1.07 seconds
Started Jul 25 07:08:00 PM PDT 24
Finished Jul 25 07:08:01 PM PDT 24
Peak memory 207232 kb
Host smart-e2cc961f-f3a2-4006-bc61-6ea97e95ed20
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3465778498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.3465778498
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.2572266230
Short name T1201
Test name
Test status
Simulation time 197768019 ps
CPU time 0.93 seconds
Started Jul 25 07:08:01 PM PDT 24
Finished Jul 25 07:08:02 PM PDT 24
Peak memory 207104 kb
Host smart-20edcdba-9208-45f2-a450-6a65a09c1e1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25722
66230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.2572266230
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.3965986312
Short name T165
Test name
Test status
Simulation time 6001896148 ps
CPU time 47.21 seconds
Started Jul 25 07:08:12 PM PDT 24
Finished Jul 25 07:09:00 PM PDT 24
Peak memory 217120 kb
Host smart-dfc48b48-2704-4d6b-ba78-8d175ef9c4f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39659
86312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.3965986312
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.2253518835
Short name T1782
Test name
Test status
Simulation time 6666387082 ps
CPU time 192.84 seconds
Started Jul 25 07:08:06 PM PDT 24
Finished Jul 25 07:11:19 PM PDT 24
Peak memory 215628 kb
Host smart-55b021ce-aeed-4b5c-aee5-a5ec57c6ef45
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2253518835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.2253518835
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.2848421618
Short name T2618
Test name
Test status
Simulation time 155410767 ps
CPU time 0.86 seconds
Started Jul 25 07:07:59 PM PDT 24
Finished Jul 25 07:08:00 PM PDT 24
Peak memory 207172 kb
Host smart-1bfe7d7c-0973-4afd-a7e3-81d8695eedde
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2848421618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.2848421618
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.1925405627
Short name T1061
Test name
Test status
Simulation time 150491010 ps
CPU time 0.9 seconds
Started Jul 25 07:08:02 PM PDT 24
Finished Jul 25 07:08:03 PM PDT 24
Peak memory 207088 kb
Host smart-a32f10a7-e288-4694-9ceb-69b8f76c1a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19254
05627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.1925405627
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.3354573876
Short name T136
Test name
Test status
Simulation time 192991811 ps
CPU time 0.89 seconds
Started Jul 25 07:08:01 PM PDT 24
Finished Jul 25 07:08:02 PM PDT 24
Peak memory 207156 kb
Host smart-6d9af140-c9bc-431a-a163-0237a12d5f7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33545
73876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.3354573876
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.382598180
Short name T1378
Test name
Test status
Simulation time 182427600 ps
CPU time 0.98 seconds
Started Jul 25 07:08:12 PM PDT 24
Finished Jul 25 07:08:13 PM PDT 24
Peak memory 207116 kb
Host smart-3f8759c2-d493-4305-9e4c-5575de3e296c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38259
8180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.382598180
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.1449694646
Short name T825
Test name
Test status
Simulation time 181818128 ps
CPU time 0.84 seconds
Started Jul 25 07:08:00 PM PDT 24
Finished Jul 25 07:08:00 PM PDT 24
Peak memory 207120 kb
Host smart-f4932578-e57d-4439-b1fe-66b4ea3c2d3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14496
94646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.1449694646
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.935524556
Short name T2281
Test name
Test status
Simulation time 229105619 ps
CPU time 0.9 seconds
Started Jul 25 07:08:02 PM PDT 24
Finished Jul 25 07:08:03 PM PDT 24
Peak memory 207244 kb
Host smart-6925da55-11ee-418d-b147-6e47533b8b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93552
4556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.935524556
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.725155124
Short name T1018
Test name
Test status
Simulation time 150536402 ps
CPU time 0.86 seconds
Started Jul 25 07:08:12 PM PDT 24
Finished Jul 25 07:08:13 PM PDT 24
Peak memory 207128 kb
Host smart-999853ec-0b85-465d-bc9b-ea49dd05d4e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72515
5124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.725155124
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.3372871382
Short name T1553
Test name
Test status
Simulation time 242015920 ps
CPU time 1.03 seconds
Started Jul 25 07:08:01 PM PDT 24
Finished Jul 25 07:08:02 PM PDT 24
Peak memory 207148 kb
Host smart-285a839a-3371-44b5-b418-f8fc5810eafd
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3372871382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.3372871382
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.4104583196
Short name T2236
Test name
Test status
Simulation time 141047854 ps
CPU time 0.84 seconds
Started Jul 25 07:08:01 PM PDT 24
Finished Jul 25 07:08:02 PM PDT 24
Peak memory 207064 kb
Host smart-718b3387-b65c-46f6-82cb-9c5635c3569f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41045
83196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.4104583196
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.729361241
Short name T2339
Test name
Test status
Simulation time 65842568 ps
CPU time 0.7 seconds
Started Jul 25 07:08:10 PM PDT 24
Finished Jul 25 07:08:11 PM PDT 24
Peak memory 207108 kb
Host smart-12b410f1-89c6-47ae-a4ea-90e34afd7a81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72936
1241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.729361241
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.801615355
Short name T266
Test name
Test status
Simulation time 10497686129 ps
CPU time 27.25 seconds
Started Jul 25 07:08:05 PM PDT 24
Finished Jul 25 07:08:32 PM PDT 24
Peak memory 223776 kb
Host smart-c459a6ee-a4a5-4fe1-839f-3098f6c3f256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80161
5355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.801615355
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.939505394
Short name T2297
Test name
Test status
Simulation time 219311892 ps
CPU time 0.92 seconds
Started Jul 25 07:08:00 PM PDT 24
Finished Jul 25 07:08:01 PM PDT 24
Peak memory 207076 kb
Host smart-d5dd1339-4c9b-4a5a-a12e-608d2c9dfbba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93950
5394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.939505394
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.2506045104
Short name T2495
Test name
Test status
Simulation time 277835496 ps
CPU time 1.12 seconds
Started Jul 25 07:08:03 PM PDT 24
Finished Jul 25 07:08:04 PM PDT 24
Peak memory 207120 kb
Host smart-57676a4d-4b96-4e09-add2-2fbec43586b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25060
45104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.2506045104
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.3281333962
Short name T1563
Test name
Test status
Simulation time 172872237 ps
CPU time 0.85 seconds
Started Jul 25 07:08:01 PM PDT 24
Finished Jul 25 07:08:02 PM PDT 24
Peak memory 207152 kb
Host smart-c2fd6257-0f2b-4cac-b80b-f4b4e78d9a48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32813
33962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.3281333962
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.421230369
Short name T2315
Test name
Test status
Simulation time 165074180 ps
CPU time 0.87 seconds
Started Jul 25 07:08:10 PM PDT 24
Finished Jul 25 07:08:11 PM PDT 24
Peak memory 207140 kb
Host smart-cb9f8087-4c0f-4adc-92da-893ebe89b644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42123
0369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.421230369
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.4096578041
Short name T1184
Test name
Test status
Simulation time 148669246 ps
CPU time 0.83 seconds
Started Jul 25 07:08:00 PM PDT 24
Finished Jul 25 07:08:01 PM PDT 24
Peak memory 207076 kb
Host smart-1926105b-c06f-41c9-830f-ad7b34f591eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40965
78041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.4096578041
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.113916738
Short name T2399
Test name
Test status
Simulation time 178681074 ps
CPU time 0.86 seconds
Started Jul 25 07:08:07 PM PDT 24
Finished Jul 25 07:08:08 PM PDT 24
Peak memory 207052 kb
Host smart-cd7ff883-0ccd-4459-8d0a-d2ecfb808b8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11391
6738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.113916738
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.3106793016
Short name T851
Test name
Test status
Simulation time 169354717 ps
CPU time 0.87 seconds
Started Jul 25 07:08:03 PM PDT 24
Finished Jul 25 07:08:04 PM PDT 24
Peak memory 207240 kb
Host smart-92b8f43f-9b1c-48f0-abc6-3a51a5e0a496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31067
93016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.3106793016
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.1713184361
Short name T2193
Test name
Test status
Simulation time 244169501 ps
CPU time 1.11 seconds
Started Jul 25 07:08:08 PM PDT 24
Finished Jul 25 07:08:09 PM PDT 24
Peak memory 207084 kb
Host smart-c2f06911-fc7a-44f0-9ab2-5c43c7555017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17131
84361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.1713184361
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.447589962
Short name T459
Test name
Test status
Simulation time 6544309034 ps
CPU time 65.08 seconds
Started Jul 25 07:08:12 PM PDT 24
Finished Jul 25 07:09:17 PM PDT 24
Peak memory 215568 kb
Host smart-b1022824-b5ab-4beb-9d61-bf7cb84aa593
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=447589962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.447589962
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.2702382391
Short name T2423
Test name
Test status
Simulation time 225573028 ps
CPU time 0.94 seconds
Started Jul 25 07:08:10 PM PDT 24
Finished Jul 25 07:08:11 PM PDT 24
Peak memory 207160 kb
Host smart-841dd076-a427-494c-830d-8f8f1394da3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27023
82391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.2702382391
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.3794124026
Short name T1415
Test name
Test status
Simulation time 173532677 ps
CPU time 0.88 seconds
Started Jul 25 07:08:19 PM PDT 24
Finished Jul 25 07:08:20 PM PDT 24
Peak memory 207148 kb
Host smart-26629a34-d63e-4553-ae2a-2a0e6367193d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37941
24026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.3794124026
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.391172024
Short name T417
Test name
Test status
Simulation time 781754672 ps
CPU time 2.17 seconds
Started Jul 25 07:08:24 PM PDT 24
Finished Jul 25 07:08:27 PM PDT 24
Peak memory 207324 kb
Host smart-9d679ec9-2d27-4822-ba00-fefd3f13a016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39117
2024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.391172024
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.3978125347
Short name T633
Test name
Test status
Simulation time 4768908139 ps
CPU time 38.91 seconds
Started Jul 25 07:08:10 PM PDT 24
Finished Jul 25 07:08:49 PM PDT 24
Peak memory 217124 kb
Host smart-30a35e6c-79ad-478b-9f04-450a0a1d2c99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39781
25347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.3978125347
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_timeout_missing_host_handshake.479432980
Short name T1280
Test name
Test status
Simulation time 3666008280 ps
CPU time 23.79 seconds
Started Jul 25 07:08:08 PM PDT 24
Finished Jul 25 07:08:32 PM PDT 24
Peak memory 207376 kb
Host smart-bb14d59e-1355-486c-adeb-76699e63e9e9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479432980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_timeout_missing_host
_handshake.479432980
Directory /workspace/45.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.3163111129
Short name T1786
Test name
Test status
Simulation time 95362144 ps
CPU time 0.73 seconds
Started Jul 25 07:08:33 PM PDT 24
Finished Jul 25 07:08:34 PM PDT 24
Peak memory 207172 kb
Host smart-cf964497-e33e-464e-a386-2e3c88f87fa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3163111129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.3163111129
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.3488928210
Short name T1004
Test name
Test status
Simulation time 3766279129 ps
CPU time 6.7 seconds
Started Jul 25 07:08:17 PM PDT 24
Finished Jul 25 07:08:24 PM PDT 24
Peak memory 207484 kb
Host smart-fe5420ac-bc61-46d7-84a6-a49501a515ef
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488928210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_a
on_wake_disconnect.3488928210
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.1667447314
Short name T2532
Test name
Test status
Simulation time 13414383746 ps
CPU time 15.36 seconds
Started Jul 25 07:08:15 PM PDT 24
Finished Jul 25 07:08:31 PM PDT 24
Peak memory 207396 kb
Host smart-fd9667aa-e31f-4c75-b8db-a574ed33cda4
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667447314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.1667447314
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.3148723642
Short name T1466
Test name
Test status
Simulation time 23438911993 ps
CPU time 27.8 seconds
Started Jul 25 07:08:14 PM PDT 24
Finished Jul 25 07:08:42 PM PDT 24
Peak memory 207364 kb
Host smart-6df927fd-e9dc-467e-a6df-d894327e2299
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148723642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_a
on_wake_resume.3148723642
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.3380303624
Short name T1258
Test name
Test status
Simulation time 171178269 ps
CPU time 0.89 seconds
Started Jul 25 07:08:10 PM PDT 24
Finished Jul 25 07:08:11 PM PDT 24
Peak memory 207148 kb
Host smart-0990a610-8d1d-4661-aaf8-c3fc81d50780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33803
03624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.3380303624
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.2189235840
Short name T2149
Test name
Test status
Simulation time 142502945 ps
CPU time 0.87 seconds
Started Jul 25 07:08:12 PM PDT 24
Finished Jul 25 07:08:13 PM PDT 24
Peak memory 207084 kb
Host smart-470c65c8-dc46-4b4f-9c3f-4ae0c27c0c13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21892
35840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.2189235840
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.800138099
Short name T2386
Test name
Test status
Simulation time 541229627 ps
CPU time 1.77 seconds
Started Jul 25 07:08:10 PM PDT 24
Finished Jul 25 07:08:12 PM PDT 24
Peak memory 207064 kb
Host smart-13b7c66a-f297-4ecc-9c45-46ee19f45908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80013
8099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.800138099
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.293360076
Short name T2613
Test name
Test status
Simulation time 852457004 ps
CPU time 2.18 seconds
Started Jul 25 07:08:10 PM PDT 24
Finished Jul 25 07:08:12 PM PDT 24
Peak memory 207168 kb
Host smart-8d5ef426-0eb3-4a48-8533-c37bffa46637
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=293360076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.293360076
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.516302227
Short name T172
Test name
Test status
Simulation time 14738990292 ps
CPU time 35.07 seconds
Started Jul 25 07:08:12 PM PDT 24
Finished Jul 25 07:08:47 PM PDT 24
Peak memory 207272 kb
Host smart-e73d384b-8665-4efb-9611-60819d963cea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51630
2227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.516302227
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_device_timeout.2034601130
Short name T493
Test name
Test status
Simulation time 1001524712 ps
CPU time 22.74 seconds
Started Jul 25 07:08:17 PM PDT 24
Finished Jul 25 07:08:40 PM PDT 24
Peak memory 207356 kb
Host smart-5a058165-3bf0-4ac3-b83a-b8599b4c6fa4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034601130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_timeout.2034601130
Directory /workspace/46.usbdev_device_timeout/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.401635007
Short name T1605
Test name
Test status
Simulation time 494239727 ps
CPU time 1.44 seconds
Started Jul 25 07:08:09 PM PDT 24
Finished Jul 25 07:08:10 PM PDT 24
Peak memory 207040 kb
Host smart-e844c32e-2666-4bbb-9e02-267d30261b9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40163
5007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.401635007
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.2275233651
Short name T860
Test name
Test status
Simulation time 213930352 ps
CPU time 0.9 seconds
Started Jul 25 07:08:13 PM PDT 24
Finished Jul 25 07:08:14 PM PDT 24
Peak memory 207096 kb
Host smart-bafca847-bedc-4638-8581-1021cd489a6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22752
33651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.2275233651
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.3726214823
Short name T1701
Test name
Test status
Simulation time 38854034 ps
CPU time 0.75 seconds
Started Jul 25 07:08:18 PM PDT 24
Finished Jul 25 07:08:19 PM PDT 24
Peak memory 207072 kb
Host smart-2fe637f6-ab33-415e-a3fa-9dfe626e65f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37262
14823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.3726214823
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.481996577
Short name T2287
Test name
Test status
Simulation time 802809853 ps
CPU time 2.11 seconds
Started Jul 25 07:08:10 PM PDT 24
Finished Jul 25 07:08:12 PM PDT 24
Peak memory 207356 kb
Host smart-0ae0fef0-5592-4aa3-8e28-e406ae3107ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48199
6577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.481996577
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.319388210
Short name T612
Test name
Test status
Simulation time 267070962 ps
CPU time 2.14 seconds
Started Jul 25 07:08:10 PM PDT 24
Finished Jul 25 07:08:12 PM PDT 24
Peak memory 207296 kb
Host smart-5172756d-fe57-4212-8e39-43c1571dce99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31938
8210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.319388210
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.1643741066
Short name T473
Test name
Test status
Simulation time 233546819 ps
CPU time 1.1 seconds
Started Jul 25 07:08:12 PM PDT 24
Finished Jul 25 07:08:13 PM PDT 24
Peak memory 215524 kb
Host smart-b6b83f9c-1613-4cad-a9a8-88ed72b1091c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1643741066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.1643741066
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.3209989876
Short name T104
Test name
Test status
Simulation time 223217724 ps
CPU time 0.86 seconds
Started Jul 25 07:08:09 PM PDT 24
Finished Jul 25 07:08:10 PM PDT 24
Peak memory 207080 kb
Host smart-5adb5128-6dcc-462c-a87d-a3c8b4303317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32099
89876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.3209989876
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.1264624711
Short name T1681
Test name
Test status
Simulation time 173584414 ps
CPU time 0.88 seconds
Started Jul 25 07:08:12 PM PDT 24
Finished Jul 25 07:08:12 PM PDT 24
Peak memory 207160 kb
Host smart-d710a9da-e8c1-40ba-99f1-b56bf6e8546b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12646
24711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.1264624711
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_invalid_sync.1653121450
Short name T2559
Test name
Test status
Simulation time 5279230868 ps
CPU time 39.98 seconds
Started Jul 25 07:08:09 PM PDT 24
Finished Jul 25 07:08:49 PM PDT 24
Peak memory 217164 kb
Host smart-20f3cfaa-a270-4e99-8b05-cdcd56616b94
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1653121450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.1653121450
Directory /workspace/46.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/46.usbdev_iso_retraction.501691162
Short name T1972
Test name
Test status
Simulation time 11595286869 ps
CPU time 134.1 seconds
Started Jul 25 07:08:19 PM PDT 24
Finished Jul 25 07:10:33 PM PDT 24
Peak memory 207372 kb
Host smart-c8bd826e-7ea5-4691-b465-26ca99af9eb4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=501691162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.501691162
Directory /workspace/46.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.1039463901
Short name T2447
Test name
Test status
Simulation time 209522863 ps
CPU time 0.98 seconds
Started Jul 25 07:08:10 PM PDT 24
Finished Jul 25 07:08:11 PM PDT 24
Peak memory 207148 kb
Host smart-5d7262a6-d787-4604-b888-57c71a7f08c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10394
63901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.1039463901
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.173640918
Short name T2222
Test name
Test status
Simulation time 23337785962 ps
CPU time 32.58 seconds
Started Jul 25 07:08:23 PM PDT 24
Finished Jul 25 07:08:56 PM PDT 24
Peak memory 207368 kb
Host smart-e19fbf18-de57-4718-af12-6a67a3193411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17364
0918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.173640918
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.3701485403
Short name T717
Test name
Test status
Simulation time 3294402040 ps
CPU time 5.16 seconds
Started Jul 25 07:08:11 PM PDT 24
Finished Jul 25 07:08:16 PM PDT 24
Peak memory 207384 kb
Host smart-492e82d0-2e95-4f33-a00f-2ef571fa3f1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37014
85403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.3701485403
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.451080733
Short name T2381
Test name
Test status
Simulation time 7855799378 ps
CPU time 231.19 seconds
Started Jul 25 07:08:12 PM PDT 24
Finished Jul 25 07:12:03 PM PDT 24
Peak memory 215476 kb
Host smart-9109d79e-6a4b-4c93-9625-cefba2082030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45108
0733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.451080733
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.1771071030
Short name T1286
Test name
Test status
Simulation time 4650549094 ps
CPU time 35.22 seconds
Started Jul 25 07:08:13 PM PDT 24
Finished Jul 25 07:08:49 PM PDT 24
Peak memory 215660 kb
Host smart-e26dad90-d2fd-4724-a46e-bd81ea459b34
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1771071030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.1771071030
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.2881802573
Short name T1823
Test name
Test status
Simulation time 254588639 ps
CPU time 0.99 seconds
Started Jul 25 07:08:11 PM PDT 24
Finished Jul 25 07:08:12 PM PDT 24
Peak memory 207160 kb
Host smart-0d940528-0a32-4fca-94cf-b4e8d3d7c0bd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2881802573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.2881802573
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.1712370935
Short name T2439
Test name
Test status
Simulation time 266076400 ps
CPU time 1.06 seconds
Started Jul 25 07:08:25 PM PDT 24
Finished Jul 25 07:08:26 PM PDT 24
Peak memory 207116 kb
Host smart-b536d52e-9104-4756-a740-e3f1c595a6c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17123
70935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.1712370935
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.3014475804
Short name T669
Test name
Test status
Simulation time 3627564385 ps
CPU time 107.65 seconds
Started Jul 25 07:08:28 PM PDT 24
Finished Jul 25 07:10:16 PM PDT 24
Peak memory 215584 kb
Host smart-45435328-595e-45a1-b979-0e3f3820d169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30144
75804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.3014475804
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.2666090970
Short name T852
Test name
Test status
Simulation time 3287531507 ps
CPU time 89.16 seconds
Started Jul 25 07:08:26 PM PDT 24
Finished Jul 25 07:09:55 PM PDT 24
Peak memory 223544 kb
Host smart-710ee297-2d44-4e25-89df-3887b83582a0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2666090970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.2666090970
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.197595838
Short name T999
Test name
Test status
Simulation time 153112138 ps
CPU time 0.85 seconds
Started Jul 25 07:08:28 PM PDT 24
Finished Jul 25 07:08:29 PM PDT 24
Peak memory 207144 kb
Host smart-2e2da432-0635-47ed-a3fb-65875adb04f7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=197595838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.197595838
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.1823222549
Short name T1002
Test name
Test status
Simulation time 151633372 ps
CPU time 0.82 seconds
Started Jul 25 07:08:30 PM PDT 24
Finished Jul 25 07:08:31 PM PDT 24
Peak memory 207144 kb
Host smart-526b9252-4d63-447b-be28-0093816a41c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18232
22549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.1823222549
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.1836449449
Short name T25
Test name
Test status
Simulation time 216607515 ps
CPU time 0.99 seconds
Started Jul 25 07:08:29 PM PDT 24
Finished Jul 25 07:08:30 PM PDT 24
Peak memory 207072 kb
Host smart-460388e0-bb44-46e0-9602-d0833fd64350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18364
49449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.1836449449
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.1847664381
Short name T2018
Test name
Test status
Simulation time 196705146 ps
CPU time 0.95 seconds
Started Jul 25 07:08:29 PM PDT 24
Finished Jul 25 07:08:30 PM PDT 24
Peak memory 207128 kb
Host smart-2abaf28b-1c0c-44ea-8ee1-d7af32163fc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18476
64381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.1847664381
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.800321922
Short name T2129
Test name
Test status
Simulation time 184341214 ps
CPU time 0.92 seconds
Started Jul 25 07:08:25 PM PDT 24
Finished Jul 25 07:08:26 PM PDT 24
Peak memory 207096 kb
Host smart-ef17d96b-1e5e-4840-80fa-33626a931e67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80032
1922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.800321922
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.2292923382
Short name T1901
Test name
Test status
Simulation time 150214805 ps
CPU time 0.83 seconds
Started Jul 25 07:08:34 PM PDT 24
Finished Jul 25 07:08:35 PM PDT 24
Peak memory 207124 kb
Host smart-4d60c48c-0dfd-49dd-bc08-0f22113592ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22929
23382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.2292923382
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.1911713697
Short name T1494
Test name
Test status
Simulation time 168273129 ps
CPU time 0.8 seconds
Started Jul 25 07:08:19 PM PDT 24
Finished Jul 25 07:08:21 PM PDT 24
Peak memory 207188 kb
Host smart-45fc74ea-79bd-4099-8297-ec9c575dd995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19117
13697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.1911713697
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.4280940554
Short name T58
Test name
Test status
Simulation time 210655324 ps
CPU time 1.02 seconds
Started Jul 25 07:08:20 PM PDT 24
Finished Jul 25 07:08:21 PM PDT 24
Peak memory 207144 kb
Host smart-84ec6c4e-00b3-4fd0-b53c-dc270dc0b377
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4280940554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.4280940554
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.294372043
Short name T1000
Test name
Test status
Simulation time 142469970 ps
CPU time 0.82 seconds
Started Jul 25 07:08:29 PM PDT 24
Finished Jul 25 07:08:30 PM PDT 24
Peak memory 207056 kb
Host smart-48253212-74b8-4542-8151-4f39f3c69e2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29437
2043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.294372043
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.2343708576
Short name T711
Test name
Test status
Simulation time 28433844 ps
CPU time 0.67 seconds
Started Jul 25 07:08:41 PM PDT 24
Finished Jul 25 07:08:42 PM PDT 24
Peak memory 207112 kb
Host smart-d5ba8f20-c9dc-4fe0-a22e-e945a8872b20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23437
08576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.2343708576
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.2255479495
Short name T1291
Test name
Test status
Simulation time 20658224240 ps
CPU time 56.93 seconds
Started Jul 25 07:08:30 PM PDT 24
Finished Jul 25 07:09:27 PM PDT 24
Peak memory 215564 kb
Host smart-097d1325-d229-429b-9bdf-33a042e0c7f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22554
79495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.2255479495
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.2261929287
Short name T2644
Test name
Test status
Simulation time 153701188 ps
CPU time 0.85 seconds
Started Jul 25 07:08:24 PM PDT 24
Finished Jul 25 07:08:25 PM PDT 24
Peak memory 207092 kb
Host smart-74ae86bc-3564-4207-9645-f6b0b9e20d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22619
29287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.2261929287
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.376005867
Short name T1365
Test name
Test status
Simulation time 254487119 ps
CPU time 1.01 seconds
Started Jul 25 07:08:30 PM PDT 24
Finished Jul 25 07:08:31 PM PDT 24
Peak memory 207160 kb
Host smart-4b26e3c3-7b28-4627-9285-d083666757bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37600
5867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.376005867
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.261137168
Short name T535
Test name
Test status
Simulation time 197446923 ps
CPU time 1.02 seconds
Started Jul 25 07:08:25 PM PDT 24
Finished Jul 25 07:08:26 PM PDT 24
Peak memory 207068 kb
Host smart-afdce78c-b612-4588-a8be-41841902761e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26113
7168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.261137168
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.432631397
Short name T2623
Test name
Test status
Simulation time 153129310 ps
CPU time 0.88 seconds
Started Jul 25 07:08:35 PM PDT 24
Finished Jul 25 07:08:36 PM PDT 24
Peak memory 207156 kb
Host smart-32e70ec9-c780-42c1-89a3-2c8d0c585a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43263
1397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.432631397
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.3043805795
Short name T668
Test name
Test status
Simulation time 155591474 ps
CPU time 0.87 seconds
Started Jul 25 07:08:34 PM PDT 24
Finished Jul 25 07:08:35 PM PDT 24
Peak memory 207132 kb
Host smart-3411d5d3-ffdb-4055-9cd8-90ae50a33dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30438
05795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.3043805795
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.873868397
Short name T376
Test name
Test status
Simulation time 193020774 ps
CPU time 0.87 seconds
Started Jul 25 07:08:23 PM PDT 24
Finished Jul 25 07:08:24 PM PDT 24
Peak memory 207092 kb
Host smart-580b9d29-7d24-4201-9cc3-136561bab5dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87386
8397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.873868397
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.236421100
Short name T1163
Test name
Test status
Simulation time 155199536 ps
CPU time 0.88 seconds
Started Jul 25 07:08:33 PM PDT 24
Finished Jul 25 07:08:34 PM PDT 24
Peak memory 207192 kb
Host smart-011500d6-20d2-4736-880d-593f1178d543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23642
1100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.236421100
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.11678035
Short name T1275
Test name
Test status
Simulation time 242442262 ps
CPU time 1.04 seconds
Started Jul 25 07:08:29 PM PDT 24
Finished Jul 25 07:08:30 PM PDT 24
Peak memory 207116 kb
Host smart-1181e50c-b371-41ac-a7d9-219888f83722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11678
035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.11678035
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.4255779076
Short name T1372
Test name
Test status
Simulation time 4881607284 ps
CPU time 37.27 seconds
Started Jul 25 07:08:25 PM PDT 24
Finished Jul 25 07:09:03 PM PDT 24
Peak memory 217168 kb
Host smart-4c02bec7-c5be-4a4f-a332-cef373adffd8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4255779076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.4255779076
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.965501314
Short name T1246
Test name
Test status
Simulation time 168843664 ps
CPU time 0.89 seconds
Started Jul 25 07:08:25 PM PDT 24
Finished Jul 25 07:08:26 PM PDT 24
Peak memory 207152 kb
Host smart-fcf81190-636a-4468-b85e-b37e961ae5c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96550
1314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.965501314
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.2889404588
Short name T1976
Test name
Test status
Simulation time 189237737 ps
CPU time 0.91 seconds
Started Jul 25 07:08:25 PM PDT 24
Finished Jul 25 07:08:26 PM PDT 24
Peak memory 207136 kb
Host smart-16ca1305-a891-497a-b061-df79060e3fcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28894
04588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.2889404588
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.1978031055
Short name T1386
Test name
Test status
Simulation time 1149652276 ps
CPU time 2.98 seconds
Started Jul 25 07:08:33 PM PDT 24
Finished Jul 25 07:08:36 PM PDT 24
Peak memory 207316 kb
Host smart-1b74ce8a-ca95-479b-8273-57838001a1fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19780
31055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.1978031055
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.226136863
Short name T2215
Test name
Test status
Simulation time 3993480544 ps
CPU time 114.08 seconds
Started Jul 25 07:08:29 PM PDT 24
Finished Jul 25 07:10:23 PM PDT 24
Peak memory 215552 kb
Host smart-57ab6b03-44ac-4b38-a77d-879f6de0fa70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22613
6863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.226136863
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_timeout_missing_host_handshake.2007866266
Short name T29
Test name
Test status
Simulation time 1049250682 ps
CPU time 9.57 seconds
Started Jul 25 07:08:09 PM PDT 24
Finished Jul 25 07:08:19 PM PDT 24
Peak memory 207304 kb
Host smart-6c1015c9-fd7a-4ca4-862d-acc7fe28fdab
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007866266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_timeout_missing_hos
t_handshake.2007866266
Directory /workspace/46.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.2201709330
Short name T2314
Test name
Test status
Simulation time 48148698 ps
CPU time 0.7 seconds
Started Jul 25 07:08:34 PM PDT 24
Finished Jul 25 07:08:35 PM PDT 24
Peak memory 207164 kb
Host smart-9cdae6db-8c7a-40e2-af79-525f583cc4b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2201709330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.2201709330
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.2369577445
Short name T2151
Test name
Test status
Simulation time 3470345059 ps
CPU time 5.41 seconds
Started Jul 25 07:08:32 PM PDT 24
Finished Jul 25 07:08:38 PM PDT 24
Peak memory 207344 kb
Host smart-e4210e63-97e7-4f46-af55-61e1da5973b6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369577445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_a
on_wake_disconnect.2369577445
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.1290513037
Short name T1808
Test name
Test status
Simulation time 13406566646 ps
CPU time 19.45 seconds
Started Jul 25 07:08:31 PM PDT 24
Finished Jul 25 07:08:50 PM PDT 24
Peak memory 207388 kb
Host smart-e071675b-7432-44f3-a1c0-0fba207ee39d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290513037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.1290513037
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.3823400657
Short name T11
Test name
Test status
Simulation time 23486092413 ps
CPU time 35.87 seconds
Started Jul 25 07:08:28 PM PDT 24
Finished Jul 25 07:09:04 PM PDT 24
Peak memory 207384 kb
Host smart-04355998-d3e4-41ec-9cf4-8180733ca916
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823400657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_a
on_wake_resume.3823400657
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.310786238
Short name T1947
Test name
Test status
Simulation time 158927278 ps
CPU time 0.88 seconds
Started Jul 25 07:08:32 PM PDT 24
Finished Jul 25 07:08:34 PM PDT 24
Peak memory 207084 kb
Host smart-4c66d3a8-1338-4f85-a875-e1779ba8491e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31078
6238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.310786238
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.3986101051
Short name T2803
Test name
Test status
Simulation time 144238214 ps
CPU time 0.9 seconds
Started Jul 25 07:08:38 PM PDT 24
Finished Jul 25 07:08:39 PM PDT 24
Peak memory 207044 kb
Host smart-a1dabe21-7d1c-4748-ab7d-d5601fdfb94c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39861
01051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.3986101051
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.4202795123
Short name T1567
Test name
Test status
Simulation time 218194885 ps
CPU time 1.04 seconds
Started Jul 25 07:08:36 PM PDT 24
Finished Jul 25 07:08:38 PM PDT 24
Peak memory 207132 kb
Host smart-051818aa-658c-44ca-ae53-a3371428b457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42027
95123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.4202795123
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.2909624143
Short name T1850
Test name
Test status
Simulation time 853102798 ps
CPU time 2.36 seconds
Started Jul 25 07:08:32 PM PDT 24
Finished Jul 25 07:08:35 PM PDT 24
Peak memory 207128 kb
Host smart-0a161749-c8df-44b2-b1f2-d152498c75ca
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2909624143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.2909624143
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.3985730759
Short name T2404
Test name
Test status
Simulation time 17770844376 ps
CPU time 42.71 seconds
Started Jul 25 07:08:36 PM PDT 24
Finished Jul 25 07:09:19 PM PDT 24
Peak memory 207332 kb
Host smart-fe6c89a9-ebe7-4eef-80d3-bdcb1fe48915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39857
30759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.3985730759
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_device_timeout.570353861
Short name T2776
Test name
Test status
Simulation time 5698185743 ps
CPU time 38.04 seconds
Started Jul 25 07:08:45 PM PDT 24
Finished Jul 25 07:09:23 PM PDT 24
Peak memory 207388 kb
Host smart-fb7eec8f-172c-49e7-88ed-111d39605300
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570353861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_timeout.570353861
Directory /workspace/47.usbdev_device_timeout/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.2559070938
Short name T1685
Test name
Test status
Simulation time 379539855 ps
CPU time 1.38 seconds
Started Jul 25 07:08:26 PM PDT 24
Finished Jul 25 07:08:28 PM PDT 24
Peak memory 207088 kb
Host smart-b7b207c9-fd54-400c-a93f-65dd92460917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25590
70938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.2559070938
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.2961866310
Short name T53
Test name
Test status
Simulation time 184751674 ps
CPU time 0.93 seconds
Started Jul 25 07:08:31 PM PDT 24
Finished Jul 25 07:08:32 PM PDT 24
Peak memory 207088 kb
Host smart-e31b135b-8ba4-43ad-8c14-ac2bbdd695a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29618
66310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.2961866310
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.3614415299
Short name T2853
Test name
Test status
Simulation time 37297161 ps
CPU time 0.68 seconds
Started Jul 25 07:08:30 PM PDT 24
Finished Jul 25 07:08:31 PM PDT 24
Peak memory 207088 kb
Host smart-01f92525-af40-4828-a994-96ebf40d2613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36144
15299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.3614415299
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.2106811813
Short name T461
Test name
Test status
Simulation time 872591233 ps
CPU time 2.62 seconds
Started Jul 25 07:08:31 PM PDT 24
Finished Jul 25 07:08:33 PM PDT 24
Peak memory 207392 kb
Host smart-967d2745-4261-48da-b85b-6abd3a74efbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21068
11813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.2106811813
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.4044023290
Short name T1529
Test name
Test status
Simulation time 278035513 ps
CPU time 2.83 seconds
Started Jul 25 07:08:33 PM PDT 24
Finished Jul 25 07:08:36 PM PDT 24
Peak memory 207276 kb
Host smart-9ddd113c-b04d-4f49-b3b7-25eed534af03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40440
23290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.4044023290
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.1686515159
Short name T1284
Test name
Test status
Simulation time 205542400 ps
CPU time 1.09 seconds
Started Jul 25 07:08:42 PM PDT 24
Finished Jul 25 07:08:43 PM PDT 24
Peak memory 207356 kb
Host smart-2dc8dd13-c69a-4e00-b2f8-7d22662d6c96
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1686515159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.1686515159
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.1454142613
Short name T2318
Test name
Test status
Simulation time 167762023 ps
CPU time 0.81 seconds
Started Jul 25 07:08:35 PM PDT 24
Finished Jul 25 07:08:36 PM PDT 24
Peak memory 207088 kb
Host smart-ccdcd82d-d1f6-4304-a56e-cb5ecce6e075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14541
42613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.1454142613
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.1372240877
Short name T2041
Test name
Test status
Simulation time 220291084 ps
CPU time 1.07 seconds
Started Jul 25 07:08:39 PM PDT 24
Finished Jul 25 07:08:40 PM PDT 24
Peak memory 207072 kb
Host smart-5ba091ac-f941-4d5d-a7a3-c7875145253c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13722
40877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.1372240877
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.3774257812
Short name T1375
Test name
Test status
Simulation time 8210603447 ps
CPU time 82.96 seconds
Started Jul 25 07:08:36 PM PDT 24
Finished Jul 25 07:09:59 PM PDT 24
Peak memory 216924 kb
Host smart-683c73cf-0707-4cce-add0-6b5132f9f365
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3774257812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.3774257812
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_iso_retraction.2048333746
Short name T1857
Test name
Test status
Simulation time 8786325041 ps
CPU time 108.86 seconds
Started Jul 25 07:08:31 PM PDT 24
Finished Jul 25 07:10:20 PM PDT 24
Peak memory 207348 kb
Host smart-1c0071bb-90ca-4745-bd9c-67b99f630ba0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2048333746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.2048333746
Directory /workspace/47.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.1570660476
Short name T2677
Test name
Test status
Simulation time 212278006 ps
CPU time 0.94 seconds
Started Jul 25 07:08:42 PM PDT 24
Finished Jul 25 07:08:43 PM PDT 24
Peak memory 207236 kb
Host smart-8171a9f7-35d9-49b4-839f-0d31f362b266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15706
60476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.1570660476
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.3082056626
Short name T1884
Test name
Test status
Simulation time 23321342899 ps
CPU time 26.95 seconds
Started Jul 25 07:08:36 PM PDT 24
Finished Jul 25 07:09:03 PM PDT 24
Peak memory 207376 kb
Host smart-240122c3-1e30-4dcc-8923-980a5f28c9db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30820
56626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.3082056626
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.3627723299
Short name T1321
Test name
Test status
Simulation time 3322353023 ps
CPU time 5.23 seconds
Started Jul 25 07:08:40 PM PDT 24
Finished Jul 25 07:08:45 PM PDT 24
Peak memory 207348 kb
Host smart-5cd469af-0c14-4d7d-b3b4-208186d2567b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36277
23299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.3627723299
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.2406577766
Short name T1206
Test name
Test status
Simulation time 4536133873 ps
CPU time 130.59 seconds
Started Jul 25 07:08:38 PM PDT 24
Finished Jul 25 07:10:49 PM PDT 24
Peak memory 215548 kb
Host smart-41705886-264f-4d68-b0a8-65bbaedc25b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24065
77766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.2406577766
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.136451362
Short name T1072
Test name
Test status
Simulation time 7015921004 ps
CPU time 54.2 seconds
Started Jul 25 07:08:34 PM PDT 24
Finished Jul 25 07:09:28 PM PDT 24
Peak memory 207468 kb
Host smart-6cbed3ec-5257-4137-8d53-6089fc74130f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=136451362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.136451362
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.1327612994
Short name T1854
Test name
Test status
Simulation time 304082079 ps
CPU time 1.27 seconds
Started Jul 25 07:08:43 PM PDT 24
Finished Jul 25 07:08:44 PM PDT 24
Peak memory 207148 kb
Host smart-ce147203-2808-4644-ab16-a78094188375
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1327612994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.1327612994
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.821922978
Short name T1527
Test name
Test status
Simulation time 204571992 ps
CPU time 1.03 seconds
Started Jul 25 07:08:34 PM PDT 24
Finished Jul 25 07:08:35 PM PDT 24
Peak memory 207156 kb
Host smart-89e17c0b-2212-4049-bc8b-c947e5711d6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82192
2978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.821922978
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.614429983
Short name T1573
Test name
Test status
Simulation time 7004211530 ps
CPU time 71.3 seconds
Started Jul 25 07:08:33 PM PDT 24
Finished Jul 25 07:09:45 PM PDT 24
Peak memory 215532 kb
Host smart-f53f0e56-adb0-47a8-8d08-556930786639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61442
9983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.614429983
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.4193228040
Short name T2410
Test name
Test status
Simulation time 5853761947 ps
CPU time 171.4 seconds
Started Jul 25 07:08:36 PM PDT 24
Finished Jul 25 07:11:28 PM PDT 24
Peak memory 215628 kb
Host smart-b4afba85-80e1-4812-88e0-6dc0b6c1a9f1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4193228040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.4193228040
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.2018987523
Short name T2037
Test name
Test status
Simulation time 168507499 ps
CPU time 0.9 seconds
Started Jul 25 07:08:41 PM PDT 24
Finished Jul 25 07:08:42 PM PDT 24
Peak memory 207060 kb
Host smart-672fa369-efac-4ef6-b9d3-feeeeae9b8a3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2018987523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.2018987523
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.2827401066
Short name T1719
Test name
Test status
Simulation time 152751721 ps
CPU time 0.91 seconds
Started Jul 25 07:08:36 PM PDT 24
Finished Jul 25 07:08:37 PM PDT 24
Peak memory 207148 kb
Host smart-2e459346-57a8-4381-9afd-de96f4ed330d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28274
01066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.2827401066
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.1982210010
Short name T2825
Test name
Test status
Simulation time 235949498 ps
CPU time 0.97 seconds
Started Jul 25 07:08:43 PM PDT 24
Finished Jul 25 07:08:44 PM PDT 24
Peak memory 207096 kb
Host smart-2e9ea6ef-22e7-4a04-840e-cf6c1930be46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19822
10010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.1982210010
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.3418743020
Short name T2756
Test name
Test status
Simulation time 216088689 ps
CPU time 0.93 seconds
Started Jul 25 07:08:48 PM PDT 24
Finished Jul 25 07:08:49 PM PDT 24
Peak memory 207052 kb
Host smart-d4892ee4-cfa2-4286-a24f-b91c25bff352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34187
43020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.3418743020
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.1373304760
Short name T1688
Test name
Test status
Simulation time 168788863 ps
CPU time 0.92 seconds
Started Jul 25 07:08:38 PM PDT 24
Finished Jul 25 07:08:39 PM PDT 24
Peak memory 207072 kb
Host smart-08f6e4a4-1930-458a-b219-328d4d9cd9a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13733
04760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.1373304760
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.3354754957
Short name T510
Test name
Test status
Simulation time 154157396 ps
CPU time 0.85 seconds
Started Jul 25 07:08:44 PM PDT 24
Finished Jul 25 07:08:45 PM PDT 24
Peak memory 207128 kb
Host smart-ef70390c-0c32-4e13-89de-ba7b8cfc8dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33547
54957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.3354754957
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.974824075
Short name T733
Test name
Test status
Simulation time 174480140 ps
CPU time 0.93 seconds
Started Jul 25 07:08:36 PM PDT 24
Finished Jul 25 07:08:37 PM PDT 24
Peak memory 207160 kb
Host smart-f4337fd7-bb3f-4390-9e0b-606267d5166d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97482
4075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.974824075
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.2454365574
Short name T962
Test name
Test status
Simulation time 214722798 ps
CPU time 0.98 seconds
Started Jul 25 07:08:48 PM PDT 24
Finished Jul 25 07:08:49 PM PDT 24
Peak memory 207164 kb
Host smart-235e3f57-bed1-4586-b704-321724009cd9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2454365574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.2454365574
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.1520595291
Short name T2340
Test name
Test status
Simulation time 168459869 ps
CPU time 0.84 seconds
Started Jul 25 07:08:28 PM PDT 24
Finished Jul 25 07:08:29 PM PDT 24
Peak memory 207140 kb
Host smart-02ea7c72-cb2d-41b5-97f0-2b991dbac03d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15205
95291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.1520595291
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.314293198
Short name T1283
Test name
Test status
Simulation time 40052634 ps
CPU time 0.72 seconds
Started Jul 25 07:08:29 PM PDT 24
Finished Jul 25 07:08:30 PM PDT 24
Peak memory 207092 kb
Host smart-6d27fc73-b85b-42a2-865f-b3c9c3ed75fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31429
3198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.314293198
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.2147905090
Short name T1990
Test name
Test status
Simulation time 6923283175 ps
CPU time 17.07 seconds
Started Jul 25 07:08:40 PM PDT 24
Finished Jul 25 07:08:57 PM PDT 24
Peak memory 215568 kb
Host smart-5fde9152-ee36-404c-8d1e-a056b9360634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21479
05090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.2147905090
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.166507720
Short name T1419
Test name
Test status
Simulation time 157895267 ps
CPU time 0.93 seconds
Started Jul 25 07:08:36 PM PDT 24
Finished Jul 25 07:08:37 PM PDT 24
Peak memory 207156 kb
Host smart-2d04d729-c8db-44e7-844f-700ec0f2ec43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16650
7720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.166507720
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.459065871
Short name T2087
Test name
Test status
Simulation time 192796507 ps
CPU time 0.93 seconds
Started Jul 25 07:08:41 PM PDT 24
Finished Jul 25 07:08:42 PM PDT 24
Peak memory 207208 kb
Host smart-fd0d0844-3b5a-4e0e-876a-78762d2678c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45906
5871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.459065871
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.931064455
Short name T357
Test name
Test status
Simulation time 234948599 ps
CPU time 1.04 seconds
Started Jul 25 07:08:37 PM PDT 24
Finished Jul 25 07:08:38 PM PDT 24
Peak memory 207128 kb
Host smart-5ee4db9a-cab2-427e-9365-c46975482695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93106
4455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.931064455
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.1291335921
Short name T2674
Test name
Test status
Simulation time 191771626 ps
CPU time 0.87 seconds
Started Jul 25 07:08:38 PM PDT 24
Finished Jul 25 07:08:39 PM PDT 24
Peak memory 207128 kb
Host smart-8f98bcaa-63c2-4956-9378-115fcecef748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12913
35921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.1291335921
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.1679613236
Short name T2612
Test name
Test status
Simulation time 153717955 ps
CPU time 0.84 seconds
Started Jul 25 07:08:39 PM PDT 24
Finished Jul 25 07:08:40 PM PDT 24
Peak memory 207088 kb
Host smart-2dad6344-ba5a-4bb5-8a1d-eb9c161b52c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16796
13236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.1679613236
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.1450290857
Short name T1970
Test name
Test status
Simulation time 238548021 ps
CPU time 0.96 seconds
Started Jul 25 07:08:38 PM PDT 24
Finished Jul 25 07:08:39 PM PDT 24
Peak memory 207096 kb
Host smart-9840ec24-4338-43e4-9c61-845bec328e2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14502
90857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.1450290857
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.3420804783
Short name T2379
Test name
Test status
Simulation time 150283182 ps
CPU time 0.92 seconds
Started Jul 25 07:08:37 PM PDT 24
Finished Jul 25 07:08:38 PM PDT 24
Peak memory 207128 kb
Host smart-e25c0e8e-9292-4467-85c6-516247993fec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34208
04783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.3420804783
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.2541842226
Short name T2295
Test name
Test status
Simulation time 273427206 ps
CPU time 1.07 seconds
Started Jul 25 07:08:35 PM PDT 24
Finished Jul 25 07:08:37 PM PDT 24
Peak memory 207096 kb
Host smart-2d38d86d-bdfd-4f21-909b-714297424a2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25418
42226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.2541842226
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.955693644
Short name T1044
Test name
Test status
Simulation time 6097648881 ps
CPU time 45.58 seconds
Started Jul 25 07:08:51 PM PDT 24
Finished Jul 25 07:09:36 PM PDT 24
Peak memory 215536 kb
Host smart-d263363d-115d-45a8-8533-9cd8de3c9371
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=955693644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.955693644
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.1279467584
Short name T1178
Test name
Test status
Simulation time 192186900 ps
CPU time 0.97 seconds
Started Jul 25 07:08:36 PM PDT 24
Finished Jul 25 07:08:37 PM PDT 24
Peak memory 207152 kb
Host smart-0d237312-afdd-464a-8c96-efe6edf2d336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12794
67584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.1279467584
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.609295418
Short name T1931
Test name
Test status
Simulation time 166890287 ps
CPU time 0.92 seconds
Started Jul 25 07:08:37 PM PDT 24
Finished Jul 25 07:08:38 PM PDT 24
Peak memory 207124 kb
Host smart-1bc03362-a122-47f3-8486-deade8ab71a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60929
5418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.609295418
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.4123960337
Short name T2627
Test name
Test status
Simulation time 1309277746 ps
CPU time 3.19 seconds
Started Jul 25 07:08:43 PM PDT 24
Finished Jul 25 07:08:46 PM PDT 24
Peak memory 207348 kb
Host smart-f65c3c2a-c59b-48c8-b84b-ba5e9fcd3bd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41239
60337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.4123960337
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.664991489
Short name T2218
Test name
Test status
Simulation time 3385921461 ps
CPU time 96.52 seconds
Started Jul 25 07:08:48 PM PDT 24
Finished Jul 25 07:10:25 PM PDT 24
Peak memory 215620 kb
Host smart-62800f49-b350-4fe2-b9ac-62c155dec2cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66499
1489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.664991489
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_timeout_missing_host_handshake.1281218913
Short name T382
Test name
Test status
Simulation time 185094164 ps
CPU time 0.92 seconds
Started Jul 25 07:08:24 PM PDT 24
Finished Jul 25 07:08:25 PM PDT 24
Peak memory 207136 kb
Host smart-159edcee-c23f-4309-84dc-264fbb4bfd13
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281218913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_timeout_missing_hos
t_handshake.1281218913
Directory /workspace/47.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.900050877
Short name T1530
Test name
Test status
Simulation time 72478520 ps
CPU time 0.74 seconds
Started Jul 25 07:08:46 PM PDT 24
Finished Jul 25 07:08:47 PM PDT 24
Peak memory 207172 kb
Host smart-f69373e9-2f19-4247-9d5e-c23970444f15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=900050877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.900050877
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.1796946372
Short name T8
Test name
Test status
Simulation time 4205300173 ps
CPU time 5.97 seconds
Started Jul 25 07:08:34 PM PDT 24
Finished Jul 25 07:08:40 PM PDT 24
Peak memory 207352 kb
Host smart-b2ca29e3-09b7-43fe-83d4-63f3c91201be
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796946372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_a
on_wake_disconnect.1796946372
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.3444062454
Short name T1091
Test name
Test status
Simulation time 13399297012 ps
CPU time 16.21 seconds
Started Jul 25 07:08:48 PM PDT 24
Finished Jul 25 07:09:05 PM PDT 24
Peak memory 207428 kb
Host smart-3cf7c1de-c85d-4586-82fe-054ead9c0475
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444062454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.3444062454
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.300510763
Short name T2090
Test name
Test status
Simulation time 23357029198 ps
CPU time 28.02 seconds
Started Jul 25 07:08:36 PM PDT 24
Finished Jul 25 07:09:04 PM PDT 24
Peak memory 207368 kb
Host smart-c05dac5f-00fd-4397-b574-65b596348a06
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300510763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_ao
n_wake_resume.300510763
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.885254456
Short name T620
Test name
Test status
Simulation time 187787682 ps
CPU time 0.86 seconds
Started Jul 25 07:08:45 PM PDT 24
Finished Jul 25 07:08:46 PM PDT 24
Peak memory 207228 kb
Host smart-ae5f7624-521f-4a68-99d7-d543a1c3f810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88525
4456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.885254456
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.3295433747
Short name T2711
Test name
Test status
Simulation time 141950853 ps
CPU time 0.94 seconds
Started Jul 25 07:08:37 PM PDT 24
Finished Jul 25 07:08:38 PM PDT 24
Peak memory 207088 kb
Host smart-450049b0-2b1d-4986-b7e1-87560d9d380b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32954
33747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.3295433747
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.1973535885
Short name T1934
Test name
Test status
Simulation time 202759691 ps
CPU time 0.98 seconds
Started Jul 25 07:08:45 PM PDT 24
Finished Jul 25 07:08:46 PM PDT 24
Peak memory 207136 kb
Host smart-cb123b6c-c437-4956-ae7c-db11b8ca8c84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19735
35885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.1973535885
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.4063339858
Short name T393
Test name
Test status
Simulation time 313315398 ps
CPU time 1.12 seconds
Started Jul 25 07:08:41 PM PDT 24
Finished Jul 25 07:08:42 PM PDT 24
Peak memory 207080 kb
Host smart-4634d945-b229-40af-81e8-cbed3e269120
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4063339858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.4063339858
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.2314310554
Short name T908
Test name
Test status
Simulation time 22043556835 ps
CPU time 50.03 seconds
Started Jul 25 07:08:40 PM PDT 24
Finished Jul 25 07:09:30 PM PDT 24
Peak memory 207384 kb
Host smart-1e79023d-0c19-4b0d-9910-d7cefea57173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23143
10554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.2314310554
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_device_timeout.1760491585
Short name T868
Test name
Test status
Simulation time 606507446 ps
CPU time 11.44 seconds
Started Jul 25 07:08:37 PM PDT 24
Finished Jul 25 07:08:48 PM PDT 24
Peak memory 207396 kb
Host smart-321d982a-4dc1-4982-aadc-809ff285917b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760491585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_timeout.1760491585
Directory /workspace/48.usbdev_device_timeout/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.3205358412
Short name T2347
Test name
Test status
Simulation time 446625959 ps
CPU time 1.51 seconds
Started Jul 25 07:08:43 PM PDT 24
Finished Jul 25 07:08:45 PM PDT 24
Peak memory 207124 kb
Host smart-ff4e6069-3c3d-4ec4-9405-768446c7ca2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32053
58412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.3205358412
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.2366421706
Short name T1130
Test name
Test status
Simulation time 148597922 ps
CPU time 0.85 seconds
Started Jul 25 07:08:40 PM PDT 24
Finished Jul 25 07:08:42 PM PDT 24
Peak memory 207096 kb
Host smart-501d4093-529c-4da8-90c9-02f26027ac12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23664
21706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.2366421706
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.1022926550
Short name T2283
Test name
Test status
Simulation time 39919402 ps
CPU time 0.72 seconds
Started Jul 25 07:08:37 PM PDT 24
Finished Jul 25 07:08:38 PM PDT 24
Peak memory 207088 kb
Host smart-9409da9c-34a3-472f-932b-48c09a3be26b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10229
26550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.1022926550
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.241009074
Short name T2360
Test name
Test status
Simulation time 775413751 ps
CPU time 2.04 seconds
Started Jul 25 07:08:37 PM PDT 24
Finished Jul 25 07:08:40 PM PDT 24
Peak memory 207364 kb
Host smart-ba11e07d-289d-4a03-a512-a7bf9edc3708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24100
9074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.241009074
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.3111033052
Short name T2348
Test name
Test status
Simulation time 189210337 ps
CPU time 1.63 seconds
Started Jul 25 07:08:44 PM PDT 24
Finished Jul 25 07:08:46 PM PDT 24
Peak memory 207264 kb
Host smart-a2979cc6-a34f-4d90-8437-127b66839d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31110
33052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.3111033052
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.146912305
Short name T729
Test name
Test status
Simulation time 172154495 ps
CPU time 0.93 seconds
Started Jul 25 07:08:34 PM PDT 24
Finished Jul 25 07:08:35 PM PDT 24
Peak memory 207168 kb
Host smart-9ae05434-327c-4ea6-87d9-7d437b449a80
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=146912305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.146912305
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.2282269371
Short name T2162
Test name
Test status
Simulation time 139917927 ps
CPU time 0.79 seconds
Started Jul 25 07:08:44 PM PDT 24
Finished Jul 25 07:08:45 PM PDT 24
Peak memory 207100 kb
Host smart-ef758c2d-230e-484b-95ef-14f8335fed7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22822
69371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.2282269371
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.4127093179
Short name T2291
Test name
Test status
Simulation time 188639742 ps
CPU time 0.96 seconds
Started Jul 25 07:08:46 PM PDT 24
Finished Jul 25 07:08:48 PM PDT 24
Peak memory 207132 kb
Host smart-d6f7e4ba-d895-4ae1-b610-9da2d294f99a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41270
93179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.4127093179
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.1867324453
Short name T123
Test name
Test status
Simulation time 5789389671 ps
CPU time 166.37 seconds
Started Jul 25 07:08:44 PM PDT 24
Finished Jul 25 07:11:31 PM PDT 24
Peak memory 223552 kb
Host smart-6b8efaee-40cc-4747-8138-436697d24f0c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1867324453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.1867324453
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_iso_retraction.262517914
Short name T348
Test name
Test status
Simulation time 11565228364 ps
CPU time 74.5 seconds
Started Jul 25 07:08:36 PM PDT 24
Finished Jul 25 07:09:50 PM PDT 24
Peak memory 207372 kb
Host smart-d2438806-a41a-411a-b5b9-409e58883d16
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=262517914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_iso_retraction.262517914
Directory /workspace/48.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.3330752664
Short name T2057
Test name
Test status
Simulation time 181338996 ps
CPU time 0.92 seconds
Started Jul 25 07:08:39 PM PDT 24
Finished Jul 25 07:08:40 PM PDT 24
Peak memory 207128 kb
Host smart-407b16d0-3d8e-4c1f-9601-d8402dab6b70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33307
52664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.3330752664
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.3825368886
Short name T1242
Test name
Test status
Simulation time 23348132271 ps
CPU time 27.22 seconds
Started Jul 25 07:08:39 PM PDT 24
Finished Jul 25 07:09:07 PM PDT 24
Peak memory 207368 kb
Host smart-11ff7322-4730-4f95-a168-e4fa2b1db436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38253
68886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.3825368886
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.2322252920
Short name T2008
Test name
Test status
Simulation time 3333509373 ps
CPU time 4.98 seconds
Started Jul 25 07:08:34 PM PDT 24
Finished Jul 25 07:08:39 PM PDT 24
Peak memory 207372 kb
Host smart-b260bf73-6a5d-45ea-b6f3-9828927c4eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23222
52920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.2322252920
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.1708790780
Short name T1170
Test name
Test status
Simulation time 6463774776 ps
CPU time 49.67 seconds
Started Jul 25 07:08:38 PM PDT 24
Finished Jul 25 07:09:28 PM PDT 24
Peak memory 223780 kb
Host smart-eed4bba3-adea-4342-8734-bf59543037b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17087
90780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.1708790780
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.207492943
Short name T2176
Test name
Test status
Simulation time 5666393797 ps
CPU time 55.46 seconds
Started Jul 25 07:08:33 PM PDT 24
Finished Jul 25 07:09:29 PM PDT 24
Peak memory 207408 kb
Host smart-d1c99307-5e53-41ca-ad64-0ee0b60611b2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=207492943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.207492943
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.4008745871
Short name T1897
Test name
Test status
Simulation time 246877444 ps
CPU time 1 seconds
Started Jul 25 07:08:35 PM PDT 24
Finished Jul 25 07:08:37 PM PDT 24
Peak memory 207144 kb
Host smart-9cd4d323-5025-4983-a03e-3824ad706c68
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4008745871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.4008745871
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.3040922104
Short name T1644
Test name
Test status
Simulation time 192917606 ps
CPU time 0.94 seconds
Started Jul 25 07:08:40 PM PDT 24
Finished Jul 25 07:08:41 PM PDT 24
Peak memory 207124 kb
Host smart-ea782457-bcf7-4586-81fa-8213f1ebe89d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30409
22104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.3040922104
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.1894188948
Short name T443
Test name
Test status
Simulation time 5297123563 ps
CPU time 157.15 seconds
Started Jul 25 07:08:40 PM PDT 24
Finished Jul 25 07:11:17 PM PDT 24
Peak memory 215528 kb
Host smart-7278998f-cae9-4872-9618-dbe87ead6fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18941
88948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.1894188948
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.2136727296
Short name T232
Test name
Test status
Simulation time 5262315560 ps
CPU time 156.93 seconds
Started Jul 25 07:08:38 PM PDT 24
Finished Jul 25 07:11:15 PM PDT 24
Peak memory 215612 kb
Host smart-14464d83-492e-4b8f-b9b9-53ae766b512a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2136727296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.2136727296
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.1405815739
Short name T964
Test name
Test status
Simulation time 184448197 ps
CPU time 0.87 seconds
Started Jul 25 07:08:48 PM PDT 24
Finished Jul 25 07:08:49 PM PDT 24
Peak memory 207092 kb
Host smart-973d844a-ed72-4901-9323-6f2e4cb2829b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1405815739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.1405815739
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.1590880998
Short name T692
Test name
Test status
Simulation time 164037611 ps
CPU time 0.87 seconds
Started Jul 25 07:08:39 PM PDT 24
Finished Jul 25 07:08:40 PM PDT 24
Peak memory 207128 kb
Host smart-877e7c84-08b8-4b49-b0c9-5f3d2a24cc16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15908
80998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.1590880998
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.2600800094
Short name T160
Test name
Test status
Simulation time 227420025 ps
CPU time 1.01 seconds
Started Jul 25 07:08:38 PM PDT 24
Finished Jul 25 07:08:39 PM PDT 24
Peak memory 207168 kb
Host smart-5f8dd404-d5a8-4110-85f9-c2572d114f76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26008
00094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.2600800094
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.2547716595
Short name T844
Test name
Test status
Simulation time 183535645 ps
CPU time 0.98 seconds
Started Jul 25 07:08:51 PM PDT 24
Finished Jul 25 07:08:52 PM PDT 24
Peak memory 207080 kb
Host smart-d51f7c43-55a8-45a2-912d-73c7a5a51f77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25477
16595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.2547716595
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.3387981652
Short name T1115
Test name
Test status
Simulation time 197325411 ps
CPU time 0.9 seconds
Started Jul 25 07:08:38 PM PDT 24
Finished Jul 25 07:08:39 PM PDT 24
Peak memory 207132 kb
Host smart-48df9e08-78e8-40a0-b76e-76864282b156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33879
81652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.3387981652
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.2994216498
Short name T398
Test name
Test status
Simulation time 176870787 ps
CPU time 0.87 seconds
Started Jul 25 07:08:40 PM PDT 24
Finished Jul 25 07:08:41 PM PDT 24
Peak memory 207128 kb
Host smart-656d4671-10f8-473e-a0cc-5b8427ddb51d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29942
16498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.2994216498
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.2178623561
Short name T2461
Test name
Test status
Simulation time 151301672 ps
CPU time 0.83 seconds
Started Jul 25 07:08:48 PM PDT 24
Finished Jul 25 07:08:49 PM PDT 24
Peak memory 207084 kb
Host smart-03e62149-2fa3-41a4-bcbd-f8719342b78c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21786
23561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.2178623561
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.257397796
Short name T2497
Test name
Test status
Simulation time 212435605 ps
CPU time 1.05 seconds
Started Jul 25 07:08:51 PM PDT 24
Finished Jul 25 07:08:52 PM PDT 24
Peak memory 207108 kb
Host smart-94d7ce51-da2c-453f-992e-2ef0402a16da
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=257397796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.257397796
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.2258988677
Short name T2398
Test name
Test status
Simulation time 162764078 ps
CPU time 0.88 seconds
Started Jul 25 07:08:50 PM PDT 24
Finished Jul 25 07:08:51 PM PDT 24
Peak memory 207112 kb
Host smart-9118515d-013a-4a41-a3a6-b41bdb22063d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22589
88677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.2258988677
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.143541718
Short name T2558
Test name
Test status
Simulation time 36197613 ps
CPU time 0.72 seconds
Started Jul 25 07:08:55 PM PDT 24
Finished Jul 25 07:08:56 PM PDT 24
Peak memory 207192 kb
Host smart-a0b08c70-b808-46f0-b912-1fe5e4659057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14354
1718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.143541718
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.4099768227
Short name T2128
Test name
Test status
Simulation time 18656986008 ps
CPU time 46.2 seconds
Started Jul 25 07:08:51 PM PDT 24
Finished Jul 25 07:09:37 PM PDT 24
Peak memory 215524 kb
Host smart-0897bb19-32cd-4551-b7a9-537e8af13233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40997
68227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.4099768227
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.1439133524
Short name T2660
Test name
Test status
Simulation time 193189114 ps
CPU time 0.93 seconds
Started Jul 25 07:08:45 PM PDT 24
Finished Jul 25 07:08:46 PM PDT 24
Peak memory 207196 kb
Host smart-9a168169-f05a-4280-b08b-8ac65e4dde27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14391
33524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.1439133524
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.1327562167
Short name T2519
Test name
Test status
Simulation time 200806141 ps
CPU time 0.96 seconds
Started Jul 25 07:08:45 PM PDT 24
Finished Jul 25 07:08:46 PM PDT 24
Peak memory 207120 kb
Host smart-ecc0c327-f300-49c2-9c28-fc8cc778ecc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13275
62167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.1327562167
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.2494628903
Short name T561
Test name
Test status
Simulation time 239922320 ps
CPU time 0.97 seconds
Started Jul 25 07:08:52 PM PDT 24
Finished Jul 25 07:08:54 PM PDT 24
Peak memory 207116 kb
Host smart-08b0bb81-e7cf-471f-a661-1fc262dac4d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24946
28903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.2494628903
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.2141593240
Short name T785
Test name
Test status
Simulation time 195798720 ps
CPU time 0.96 seconds
Started Jul 25 07:08:50 PM PDT 24
Finished Jul 25 07:08:51 PM PDT 24
Peak memory 207136 kb
Host smart-440cebb6-bea6-48bd-9728-7e2c2253c6d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21415
93240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.2141593240
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.19206191
Short name T2650
Test name
Test status
Simulation time 130652090 ps
CPU time 0.83 seconds
Started Jul 25 07:08:55 PM PDT 24
Finished Jul 25 07:08:56 PM PDT 24
Peak memory 207064 kb
Host smart-2cd127e3-9005-4234-ae0d-27ef1d96f36e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19206
191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.19206191
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.889322168
Short name T753
Test name
Test status
Simulation time 145523680 ps
CPU time 0.8 seconds
Started Jul 25 07:08:50 PM PDT 24
Finished Jul 25 07:08:51 PM PDT 24
Peak memory 207088 kb
Host smart-e7ed90b3-0c5c-487b-a796-476455c5c877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88932
2168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.889322168
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.1430267537
Short name T1959
Test name
Test status
Simulation time 199592781 ps
CPU time 0.85 seconds
Started Jul 25 07:08:44 PM PDT 24
Finished Jul 25 07:08:45 PM PDT 24
Peak memory 207064 kb
Host smart-265a0a82-9d08-4d97-9862-9c2b29004a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14302
67537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.1430267537
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.973339388
Short name T1008
Test name
Test status
Simulation time 221313569 ps
CPU time 1 seconds
Started Jul 25 07:08:46 PM PDT 24
Finished Jul 25 07:08:47 PM PDT 24
Peak memory 207132 kb
Host smart-b4f15389-3aa1-401e-b07c-acfb71df0634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97333
9388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.973339388
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.4145664610
Short name T610
Test name
Test status
Simulation time 5742320154 ps
CPU time 165.86 seconds
Started Jul 25 07:08:48 PM PDT 24
Finished Jul 25 07:11:33 PM PDT 24
Peak memory 215624 kb
Host smart-3e14541a-120e-4716-97ec-f87b420b923d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4145664610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.4145664610
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.1146921757
Short name T1846
Test name
Test status
Simulation time 161605758 ps
CPU time 0.85 seconds
Started Jul 25 07:08:44 PM PDT 24
Finished Jul 25 07:08:45 PM PDT 24
Peak memory 207072 kb
Host smart-4e4b7942-76a4-4fda-9390-4dd512c6d8d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11469
21757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.1146921757
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.1688167954
Short name T360
Test name
Test status
Simulation time 234341198 ps
CPU time 0.97 seconds
Started Jul 25 07:08:44 PM PDT 24
Finished Jul 25 07:08:45 PM PDT 24
Peak memory 207236 kb
Host smart-719d1c9a-deb5-4405-b90e-c121d9dfe994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16881
67954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.1688167954
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.1670425134
Short name T370
Test name
Test status
Simulation time 566251287 ps
CPU time 1.69 seconds
Started Jul 25 07:08:51 PM PDT 24
Finished Jul 25 07:08:53 PM PDT 24
Peak memory 207116 kb
Host smart-1128c6d3-6f23-4080-bac9-40a67ce5ec6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16704
25134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.1670425134
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.3690928778
Short name T1432
Test name
Test status
Simulation time 6988264620 ps
CPU time 207.82 seconds
Started Jul 25 07:08:44 PM PDT 24
Finished Jul 25 07:12:12 PM PDT 24
Peak memory 215608 kb
Host smart-b148cb35-49a8-41f9-80e4-67effdf5af69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36909
28778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.3690928778
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_timeout_missing_host_handshake.2392639477
Short name T1075
Test name
Test status
Simulation time 714239235 ps
CPU time 15.58 seconds
Started Jul 25 07:08:35 PM PDT 24
Finished Jul 25 07:08:51 PM PDT 24
Peak memory 207256 kb
Host smart-d4b01626-62c8-4e34-b0e9-8788f0cd7baf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392639477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_timeout_missing_hos
t_handshake.2392639477
Directory /workspace/48.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.2222190538
Short name T890
Test name
Test status
Simulation time 44073757 ps
CPU time 0.65 seconds
Started Jul 25 07:08:54 PM PDT 24
Finished Jul 25 07:08:55 PM PDT 24
Peak memory 207172 kb
Host smart-dc9d3a52-5e51-4822-9fca-1b613d47cdf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2222190538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.2222190538
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.637947200
Short name T2699
Test name
Test status
Simulation time 3470484327 ps
CPU time 5.5 seconds
Started Jul 25 07:08:45 PM PDT 24
Finished Jul 25 07:08:50 PM PDT 24
Peak memory 207388 kb
Host smart-1cbb6917-d219-41b8-ad83-ed4ce9827534
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637947200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_ao
n_wake_disconnect.637947200
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.225546029
Short name T1960
Test name
Test status
Simulation time 13345467220 ps
CPU time 18.19 seconds
Started Jul 25 07:08:50 PM PDT 24
Finished Jul 25 07:09:08 PM PDT 24
Peak memory 207396 kb
Host smart-e5f95796-e4f1-4230-9869-6af9e2ebc7c4
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=225546029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.225546029
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.3436743016
Short name T1606
Test name
Test status
Simulation time 23368323294 ps
CPU time 26.79 seconds
Started Jul 25 07:08:51 PM PDT 24
Finished Jul 25 07:09:18 PM PDT 24
Peak memory 207352 kb
Host smart-5ac3c00b-5e93-4142-8f71-4b86050da007
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436743016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_a
on_wake_resume.3436743016
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.3600780692
Short name T722
Test name
Test status
Simulation time 157650521 ps
CPU time 0.89 seconds
Started Jul 25 07:08:53 PM PDT 24
Finished Jul 25 07:08:54 PM PDT 24
Peak memory 207080 kb
Host smart-95e25f73-84fa-46a2-b2d0-18ccb104d243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36007
80692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.3600780692
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.296699005
Short name T2097
Test name
Test status
Simulation time 135324264 ps
CPU time 0.84 seconds
Started Jul 25 07:08:52 PM PDT 24
Finished Jul 25 07:08:53 PM PDT 24
Peak memory 206732 kb
Host smart-e0cbbc4c-88db-4df7-b9be-bc4f68039d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29669
9005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.296699005
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.4271662403
Short name T1241
Test name
Test status
Simulation time 423416768 ps
CPU time 1.51 seconds
Started Jul 25 07:08:51 PM PDT 24
Finished Jul 25 07:08:53 PM PDT 24
Peak memory 207136 kb
Host smart-d2f04d1b-f2ad-4d36-a291-7381b134f72c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42716
62403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.4271662403
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.2739293836
Short name T1993
Test name
Test status
Simulation time 524885261 ps
CPU time 1.53 seconds
Started Jul 25 07:08:48 PM PDT 24
Finished Jul 25 07:08:50 PM PDT 24
Peak memory 207120 kb
Host smart-8620bc93-2747-4cc5-9bb8-4983b4bb0d7f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2739293836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.2739293836
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_timeout.4219701436
Short name T2609
Test name
Test status
Simulation time 2234288566 ps
CPU time 15.22 seconds
Started Jul 25 07:08:51 PM PDT 24
Finished Jul 25 07:09:06 PM PDT 24
Peak memory 207356 kb
Host smart-f565b3ed-0528-401c-8de9-b818d23be0e4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219701436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_timeout.4219701436
Directory /workspace/49.usbdev_device_timeout/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.2078420192
Short name T1477
Test name
Test status
Simulation time 493938624 ps
CPU time 1.54 seconds
Started Jul 25 07:08:45 PM PDT 24
Finished Jul 25 07:08:46 PM PDT 24
Peak memory 207056 kb
Host smart-e76855e9-f739-433c-849b-572b5b89dc29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20784
20192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.2078420192
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.3499103840
Short name T51
Test name
Test status
Simulation time 146005178 ps
CPU time 0.83 seconds
Started Jul 25 07:08:50 PM PDT 24
Finished Jul 25 07:08:51 PM PDT 24
Peak memory 207104 kb
Host smart-0caab151-b5de-4bea-b909-8041e6fdaa39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34991
03840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.3499103840
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.2622402818
Short name T1522
Test name
Test status
Simulation time 42960038 ps
CPU time 0.66 seconds
Started Jul 25 07:08:46 PM PDT 24
Finished Jul 25 07:08:47 PM PDT 24
Peak memory 207088 kb
Host smart-dd5da6ab-6df6-4605-8c43-8bbf5ecbbd01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26224
02818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.2622402818
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.307667067
Short name T963
Test name
Test status
Simulation time 988859790 ps
CPU time 2.38 seconds
Started Jul 25 07:08:54 PM PDT 24
Finished Jul 25 07:08:57 PM PDT 24
Peak memory 207420 kb
Host smart-a4ae1fa6-709f-432c-8c56-b3af8c9b060f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30766
7067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.307667067
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.1183417833
Short name T898
Test name
Test status
Simulation time 288023404 ps
CPU time 2.45 seconds
Started Jul 25 07:08:44 PM PDT 24
Finished Jul 25 07:08:47 PM PDT 24
Peak memory 207328 kb
Host smart-e9dfd782-e33e-4901-a51b-15d7b2b1e2dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11834
17833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.1183417833
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.1747976432
Short name T1949
Test name
Test status
Simulation time 184221454 ps
CPU time 1.02 seconds
Started Jul 25 07:08:50 PM PDT 24
Finished Jul 25 07:08:51 PM PDT 24
Peak memory 215520 kb
Host smart-eab96ce1-8d0e-4850-b5c2-97a781aebeb0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1747976432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.1747976432
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.3931284643
Short name T103
Test name
Test status
Simulation time 142387182 ps
CPU time 0.86 seconds
Started Jul 25 07:08:50 PM PDT 24
Finished Jul 25 07:08:51 PM PDT 24
Peak memory 206968 kb
Host smart-99126f59-dc1e-41f1-a602-73e69169c87d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39312
84643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.3931284643
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.3250345068
Short name T2725
Test name
Test status
Simulation time 259183610 ps
CPU time 1 seconds
Started Jul 25 07:08:48 PM PDT 24
Finished Jul 25 07:08:49 PM PDT 24
Peak memory 207116 kb
Host smart-c42cae1e-d64b-400b-bccf-a3e5c0806c4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32503
45068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.3250345068
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_invalid_sync.1757402144
Short name T2724
Test name
Test status
Simulation time 9541253611 ps
CPU time 92.44 seconds
Started Jul 25 07:08:47 PM PDT 24
Finished Jul 25 07:10:19 PM PDT 24
Peak memory 215532 kb
Host smart-78e5ed1c-2285-4d16-b7c0-7fa97da95259
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1757402144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.1757402144
Directory /workspace/49.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/49.usbdev_iso_retraction.2744690989
Short name T2330
Test name
Test status
Simulation time 6999662298 ps
CPU time 48.27 seconds
Started Jul 25 07:08:48 PM PDT 24
Finished Jul 25 07:09:37 PM PDT 24
Peak memory 207332 kb
Host smart-be3c47e1-76e4-43af-919d-c140121b411e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2744690989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_iso_retraction.2744690989
Directory /workspace/49.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.565246448
Short name T2272
Test name
Test status
Simulation time 190408454 ps
CPU time 0.92 seconds
Started Jul 25 07:08:44 PM PDT 24
Finished Jul 25 07:08:45 PM PDT 24
Peak memory 207124 kb
Host smart-6f981cf8-6c6a-4218-8c60-a067643eb7bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56524
6448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.565246448
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.525025680
Short name T205
Test name
Test status
Simulation time 23286245046 ps
CPU time 33.62 seconds
Started Jul 25 07:08:45 PM PDT 24
Finished Jul 25 07:09:19 PM PDT 24
Peak memory 207316 kb
Host smart-c04e26e1-690d-4f5b-89fa-e261aeb803ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52502
5680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.525025680
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.3101108487
Short name T710
Test name
Test status
Simulation time 3322841699 ps
CPU time 4.77 seconds
Started Jul 25 07:08:49 PM PDT 24
Finished Jul 25 07:08:54 PM PDT 24
Peak memory 207364 kb
Host smart-06a3a16c-3c6c-4148-9c10-b181ef368456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31011
08487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.3101108487
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.3788066700
Short name T120
Test name
Test status
Simulation time 8186332069 ps
CPU time 81.67 seconds
Started Jul 25 07:08:51 PM PDT 24
Finished Jul 25 07:10:13 PM PDT 24
Peak memory 217504 kb
Host smart-3374603d-7464-4938-8d76-d28b1b23e0f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37880
66700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.3788066700
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.1038059821
Short name T738
Test name
Test status
Simulation time 5039533148 ps
CPU time 42.53 seconds
Started Jul 25 07:08:45 PM PDT 24
Finished Jul 25 07:09:28 PM PDT 24
Peak memory 207460 kb
Host smart-07db063c-2139-4001-b88a-b4aba270417a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1038059821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.1038059821
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.3227993010
Short name T1062
Test name
Test status
Simulation time 241203833 ps
CPU time 0.93 seconds
Started Jul 25 07:08:54 PM PDT 24
Finished Jul 25 07:08:55 PM PDT 24
Peak memory 207152 kb
Host smart-0cfc3db7-962b-453f-b9b4-d34365a315f1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3227993010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.3227993010
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.1726752830
Short name T108
Test name
Test status
Simulation time 202840864 ps
CPU time 0.98 seconds
Started Jul 25 07:08:52 PM PDT 24
Finished Jul 25 07:08:53 PM PDT 24
Peak memory 207172 kb
Host smart-d38208a1-5cf3-4e1b-9d8f-82782071d150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17267
52830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.1726752830
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.2116375782
Short name T2498
Test name
Test status
Simulation time 3664398493 ps
CPU time 35.26 seconds
Started Jul 25 07:08:51 PM PDT 24
Finished Jul 25 07:09:27 PM PDT 24
Peak memory 217264 kb
Host smart-16071960-992e-4ebd-8343-4ba00bde0b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21163
75782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.2116375782
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.914475056
Short name T1618
Test name
Test status
Simulation time 3370464308 ps
CPU time 33.36 seconds
Started Jul 25 07:08:54 PM PDT 24
Finished Jul 25 07:09:28 PM PDT 24
Peak memory 217048 kb
Host smart-02ab82b4-8048-4000-9d62-cd67f05ab13b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=914475056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.914475056
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.341789701
Short name T1100
Test name
Test status
Simulation time 159302679 ps
CPU time 0.85 seconds
Started Jul 25 07:08:45 PM PDT 24
Finished Jul 25 07:08:46 PM PDT 24
Peak memory 207140 kb
Host smart-03e64aad-4166-4c33-a90f-c85fc12b41cb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=341789701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.341789701
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.925132107
Short name T1895
Test name
Test status
Simulation time 149243435 ps
CPU time 0.83 seconds
Started Jul 25 07:08:49 PM PDT 24
Finished Jul 25 07:08:50 PM PDT 24
Peak memory 207132 kb
Host smart-b2d0cf20-62fc-4b2e-a523-e7fe92172496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92513
2107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.925132107
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.2199593371
Short name T147
Test name
Test status
Simulation time 240786015 ps
CPU time 0.94 seconds
Started Jul 25 07:08:49 PM PDT 24
Finished Jul 25 07:08:50 PM PDT 24
Peak memory 207112 kb
Host smart-20368434-6521-4aba-a196-a4a934cf3edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21995
93371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.2199593371
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.217579953
Short name T1712
Test name
Test status
Simulation time 155839346 ps
CPU time 0.91 seconds
Started Jul 25 07:08:54 PM PDT 24
Finished Jul 25 07:08:55 PM PDT 24
Peak memory 207120 kb
Host smart-33590bed-74c5-402f-9d36-6e7690daa0f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21757
9953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.217579953
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.1253287556
Short name T351
Test name
Test status
Simulation time 207338463 ps
CPU time 0.88 seconds
Started Jul 25 07:08:48 PM PDT 24
Finished Jul 25 07:08:49 PM PDT 24
Peak memory 207112 kb
Host smart-39a24d2d-9f36-4dca-ba35-b62711950917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12532
87556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.1253287556
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.1624235422
Short name T378
Test name
Test status
Simulation time 203703023 ps
CPU time 0.97 seconds
Started Jul 25 07:08:42 PM PDT 24
Finished Jul 25 07:08:43 PM PDT 24
Peak memory 207112 kb
Host smart-cc2de438-10ed-484d-8e5e-1f2f15aa6550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16242
35422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.1624235422
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.745678837
Short name T1882
Test name
Test status
Simulation time 148525348 ps
CPU time 0.85 seconds
Started Jul 25 07:08:50 PM PDT 24
Finished Jul 25 07:08:51 PM PDT 24
Peak memory 206920 kb
Host smart-db62e8c8-1bd6-4b55-a40b-f2e77a398846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74567
8837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.745678837
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.3725355835
Short name T1634
Test name
Test status
Simulation time 275251880 ps
CPU time 1.06 seconds
Started Jul 25 07:08:48 PM PDT 24
Finished Jul 25 07:08:50 PM PDT 24
Peak memory 207128 kb
Host smart-d27e125d-755a-4773-bb32-7aa9bc273384
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3725355835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.3725355835
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.3042323792
Short name T1984
Test name
Test status
Simulation time 136249474 ps
CPU time 0.84 seconds
Started Jul 25 07:08:52 PM PDT 24
Finished Jul 25 07:08:54 PM PDT 24
Peak memory 207084 kb
Host smart-e515ad76-a9d7-493e-a330-1ec0da0730fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30423
23792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.3042323792
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.2965924238
Short name T2030
Test name
Test status
Simulation time 30914260 ps
CPU time 0.7 seconds
Started Jul 25 07:08:52 PM PDT 24
Finished Jul 25 07:08:53 PM PDT 24
Peak memory 207060 kb
Host smart-1ed2ff11-0f5a-434c-a55b-7d01c1c46bfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29659
24238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.2965924238
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.812182806
Short name T1249
Test name
Test status
Simulation time 8017112545 ps
CPU time 21.45 seconds
Started Jul 25 07:08:51 PM PDT 24
Finished Jul 25 07:09:13 PM PDT 24
Peak memory 220568 kb
Host smart-40f7cb1e-d0d4-40bb-b362-89c633c7a25e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81218
2806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.812182806
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.4216557605
Short name T2444
Test name
Test status
Simulation time 209451673 ps
CPU time 0.95 seconds
Started Jul 25 07:08:45 PM PDT 24
Finished Jul 25 07:08:46 PM PDT 24
Peak memory 207124 kb
Host smart-1bd9bdbc-c504-4c5c-a36b-4212252ace39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42165
57605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.4216557605
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.4156063681
Short name T683
Test name
Test status
Simulation time 222672777 ps
CPU time 0.95 seconds
Started Jul 25 07:08:44 PM PDT 24
Finished Jul 25 07:08:46 PM PDT 24
Peak memory 207140 kb
Host smart-381cf60d-7bed-4d3b-9dbb-229fb60ebfff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41560
63681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.4156063681
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.197704211
Short name T362
Test name
Test status
Simulation time 255386341 ps
CPU time 1 seconds
Started Jul 25 07:08:48 PM PDT 24
Finished Jul 25 07:08:49 PM PDT 24
Peak memory 207108 kb
Host smart-3422d5ae-d193-483c-9fb0-c60cd9d8f75b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19770
4211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.197704211
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.3239515230
Short name T1619
Test name
Test status
Simulation time 169279583 ps
CPU time 0.94 seconds
Started Jul 25 07:08:55 PM PDT 24
Finished Jul 25 07:08:56 PM PDT 24
Peak memory 207120 kb
Host smart-aa9fa83e-01e1-4a65-b626-5be8ae63d605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32395
15230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.3239515230
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.2703850645
Short name T583
Test name
Test status
Simulation time 160306710 ps
CPU time 0.83 seconds
Started Jul 25 07:08:52 PM PDT 24
Finished Jul 25 07:08:53 PM PDT 24
Peak memory 206684 kb
Host smart-54c71819-d4ef-4bb4-b442-dadf5b5bc645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27038
50645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.2703850645
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.1792121789
Short name T24
Test name
Test status
Simulation time 168336928 ps
CPU time 0.86 seconds
Started Jul 25 07:08:49 PM PDT 24
Finished Jul 25 07:08:50 PM PDT 24
Peak memory 207112 kb
Host smart-3b250139-6b9e-48e1-9d4d-53922e234aeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17921
21789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.1792121789
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.924318862
Short name T1613
Test name
Test status
Simulation time 183251830 ps
CPU time 0.89 seconds
Started Jul 25 07:08:50 PM PDT 24
Finished Jul 25 07:08:51 PM PDT 24
Peak memory 207128 kb
Host smart-4f5e50ba-dcc1-47db-bb76-be33bb39d5cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92431
8862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.924318862
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.1265413610
Short name T1893
Test name
Test status
Simulation time 246230083 ps
CPU time 1.09 seconds
Started Jul 25 07:08:51 PM PDT 24
Finished Jul 25 07:08:53 PM PDT 24
Peak memory 207148 kb
Host smart-c677b120-996d-4eee-b5eb-ca9b78060941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12654
13610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.1265413610
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.4260418962
Short name T1902
Test name
Test status
Simulation time 4454717980 ps
CPU time 127.14 seconds
Started Jul 25 07:08:52 PM PDT 24
Finished Jul 25 07:11:00 PM PDT 24
Peak memory 215628 kb
Host smart-ebc9b83c-47fd-4afb-82bc-3c96cba761dc
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4260418962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.4260418962
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.1697243170
Short name T544
Test name
Test status
Simulation time 175494872 ps
CPU time 0.86 seconds
Started Jul 25 07:09:06 PM PDT 24
Finished Jul 25 07:09:07 PM PDT 24
Peak memory 207092 kb
Host smart-ec94336c-d581-477f-8664-881aff101861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16972
43170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.1697243170
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.211282127
Short name T2547
Test name
Test status
Simulation time 202806454 ps
CPU time 0.87 seconds
Started Jul 25 07:08:56 PM PDT 24
Finished Jul 25 07:08:57 PM PDT 24
Peak memory 207132 kb
Host smart-19928bf7-83cb-4dc3-9188-2cf924ccc286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21128
2127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.211282127
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.1791512673
Short name T2485
Test name
Test status
Simulation time 1342679134 ps
CPU time 3.01 seconds
Started Jul 25 07:08:50 PM PDT 24
Finished Jul 25 07:08:53 PM PDT 24
Peak memory 207324 kb
Host smart-bcea2626-12de-49e7-b623-54da44ca1d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17915
12673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.1791512673
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.389971921
Short name T1266
Test name
Test status
Simulation time 5259044522 ps
CPU time 42.93 seconds
Started Jul 25 07:08:48 PM PDT 24
Finished Jul 25 07:09:31 PM PDT 24
Peak memory 216768 kb
Host smart-60a08ead-9494-48bb-8a5d-9b1bc5666030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38997
1921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.389971921
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_timeout_missing_host_handshake.472481983
Short name T580
Test name
Test status
Simulation time 2454213653 ps
CPU time 22.19 seconds
Started Jul 25 07:08:48 PM PDT 24
Finished Jul 25 07:09:10 PM PDT 24
Peak memory 207440 kb
Host smart-e22057d6-38cc-48ad-a7bd-bfac20399256
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472481983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_timeout_missing_host
_handshake.472481983
Directory /workspace/49.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.231626211
Short name T1830
Test name
Test status
Simulation time 34778166 ps
CPU time 0.7 seconds
Started Jul 25 07:01:36 PM PDT 24
Finished Jul 25 07:01:38 PM PDT 24
Peak memory 207160 kb
Host smart-76ab8177-0bfa-49f9-9919-e4beb3be2fae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=231626211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.231626211
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.4263418245
Short name T987
Test name
Test status
Simulation time 3732775313 ps
CPU time 6.38 seconds
Started Jul 25 07:01:29 PM PDT 24
Finished Jul 25 07:01:36 PM PDT 24
Peak memory 207372 kb
Host smart-272d487c-dd70-451f-8048-3ceea203bc32
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263418245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_disconnect.4263418245
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.3820595552
Short name T1346
Test name
Test status
Simulation time 13414986201 ps
CPU time 16.71 seconds
Started Jul 25 07:01:26 PM PDT 24
Finished Jul 25 07:01:43 PM PDT 24
Peak memory 207436 kb
Host smart-9b974c2a-b07b-475a-a358-d474367d4a41
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820595552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.3820595552
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.1876245148
Short name T1722
Test name
Test status
Simulation time 23392650026 ps
CPU time 27.77 seconds
Started Jul 25 07:01:26 PM PDT 24
Finished Jul 25 07:01:54 PM PDT 24
Peak memory 207404 kb
Host smart-68c4ef0f-605e-4a61-b612-a677997c247e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876245148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_resume.1876245148
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.1662665504
Short name T1087
Test name
Test status
Simulation time 152470369 ps
CPU time 0.86 seconds
Started Jul 25 07:01:36 PM PDT 24
Finished Jul 25 07:01:38 PM PDT 24
Peak memory 207152 kb
Host smart-faa6ed7b-e92c-4441-82f4-8aaa27a944f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16626
65504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.1662665504
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.1468499648
Short name T2072
Test name
Test status
Simulation time 145276907 ps
CPU time 0.86 seconds
Started Jul 25 07:01:29 PM PDT 24
Finished Jul 25 07:01:30 PM PDT 24
Peak memory 207060 kb
Host smart-c28757f0-cf2a-40a4-8410-0dd15d6e075d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14684
99648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.1468499648
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.675451198
Short name T1965
Test name
Test status
Simulation time 270908603 ps
CPU time 1.15 seconds
Started Jul 25 07:01:36 PM PDT 24
Finished Jul 25 07:01:38 PM PDT 24
Peak memory 207152 kb
Host smart-5445f495-c552-4fa2-a3f2-c8184def16ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67545
1198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.675451198
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.4241958957
Short name T589
Test name
Test status
Simulation time 1028733539 ps
CPU time 2.7 seconds
Started Jul 25 07:01:36 PM PDT 24
Finished Jul 25 07:01:39 PM PDT 24
Peak memory 207376 kb
Host smart-2cdb5060-5164-463c-ad76-9d0e3efa74ff
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4241958957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.4241958957
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.1757332292
Short name T1056
Test name
Test status
Simulation time 21925751066 ps
CPU time 44.1 seconds
Started Jul 25 07:01:25 PM PDT 24
Finished Jul 25 07:02:09 PM PDT 24
Peak memory 207400 kb
Host smart-445b872c-2998-4b05-b73f-6cd61498ae5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17573
32292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.1757332292
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_device_timeout.3795528988
Short name T1265
Test name
Test status
Simulation time 4372079459 ps
CPU time 29.8 seconds
Started Jul 25 07:01:29 PM PDT 24
Finished Jul 25 07:01:59 PM PDT 24
Peak memory 207380 kb
Host smart-4e9653d8-9404-4675-8c83-ff3258d53e75
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795528988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_timeout.3795528988
Directory /workspace/5.usbdev_device_timeout/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.3047400252
Short name T1753
Test name
Test status
Simulation time 429142944 ps
CPU time 1.5 seconds
Started Jul 25 07:01:28 PM PDT 24
Finished Jul 25 07:01:29 PM PDT 24
Peak memory 207092 kb
Host smart-8be25cae-4479-422e-8a71-359aa6848639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30474
00252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.3047400252
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.3726327271
Short name T1865
Test name
Test status
Simulation time 139944901 ps
CPU time 0.85 seconds
Started Jul 25 07:01:27 PM PDT 24
Finished Jul 25 07:01:28 PM PDT 24
Peak memory 207160 kb
Host smart-5004a0f9-ba9f-4639-80aa-5b29b61b43b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37263
27271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.3726327271
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.2878231572
Short name T2817
Test name
Test status
Simulation time 95009674 ps
CPU time 0.76 seconds
Started Jul 25 07:01:27 PM PDT 24
Finished Jul 25 07:01:29 PM PDT 24
Peak memory 207088 kb
Host smart-f888e4e3-7e76-4cc0-afe5-ad5c3c5f7be9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28782
31572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.2878231572
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.762450028
Short name T2562
Test name
Test status
Simulation time 918898054 ps
CPU time 2.6 seconds
Started Jul 25 07:01:31 PM PDT 24
Finished Jul 25 07:01:33 PM PDT 24
Peak memory 207352 kb
Host smart-bd87a62e-7696-4e66-8661-06dcdb1b5f9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76245
0028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.762450028
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.3986240743
Short name T2604
Test name
Test status
Simulation time 357137505 ps
CPU time 2.5 seconds
Started Jul 25 07:01:29 PM PDT 24
Finished Jul 25 07:01:31 PM PDT 24
Peak memory 207300 kb
Host smart-32a441b9-c955-40c1-a76f-ac24c7de7875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39862
40743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.3986240743
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.3871218983
Short name T2036
Test name
Test status
Simulation time 162183168 ps
CPU time 0.93 seconds
Started Jul 25 07:01:28 PM PDT 24
Finished Jul 25 07:01:30 PM PDT 24
Peak memory 207132 kb
Host smart-6f4ecd7d-7fa4-4b2f-a9d8-77006ce63096
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3871218983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.3871218983
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.414019182
Short name T464
Test name
Test status
Simulation time 144183674 ps
CPU time 0.86 seconds
Started Jul 25 07:01:26 PM PDT 24
Finished Jul 25 07:01:27 PM PDT 24
Peak memory 207096 kb
Host smart-95fe2d9b-249f-4b4a-b6ad-255f6a5f8af8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41401
9182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.414019182
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.3925107635
Short name T1948
Test name
Test status
Simulation time 227981166 ps
CPU time 1 seconds
Started Jul 25 07:01:27 PM PDT 24
Finished Jul 25 07:01:29 PM PDT 24
Peak memory 207072 kb
Host smart-a08ffd97-8450-48bd-8e1d-8bcf47707f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39251
07635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.3925107635
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.2027581515
Short name T1202
Test name
Test status
Simulation time 7748947444 ps
CPU time 82.65 seconds
Started Jul 25 07:01:29 PM PDT 24
Finished Jul 25 07:02:52 PM PDT 24
Peak memory 215624 kb
Host smart-ec1f370e-fb39-4265-9f77-513d1f926294
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2027581515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.2027581515
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_iso_retraction.1150403877
Short name T2511
Test name
Test status
Simulation time 13410875813 ps
CPU time 96.83 seconds
Started Jul 25 07:01:25 PM PDT 24
Finished Jul 25 07:03:02 PM PDT 24
Peak memory 207368 kb
Host smart-6fcd5e01-27e2-4737-9d34-4b17713597b2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1150403877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.1150403877
Directory /workspace/5.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.2537214705
Short name T833
Test name
Test status
Simulation time 172093865 ps
CPU time 0.9 seconds
Started Jul 25 07:01:37 PM PDT 24
Finished Jul 25 07:01:39 PM PDT 24
Peak memory 207148 kb
Host smart-4075e42f-dd3b-478c-958d-e61cd458b76f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25372
14705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.2537214705
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.182928465
Short name T1400
Test name
Test status
Simulation time 23329193194 ps
CPU time 26.78 seconds
Started Jul 25 07:01:38 PM PDT 24
Finished Jul 25 07:02:05 PM PDT 24
Peak memory 207396 kb
Host smart-5e2d64bf-26d4-4a3e-a70a-1915957abe7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18292
8465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.182928465
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.938856585
Short name T2255
Test name
Test status
Simulation time 3325184387 ps
CPU time 5.01 seconds
Started Jul 25 07:01:28 PM PDT 24
Finished Jul 25 07:01:34 PM PDT 24
Peak memory 207376 kb
Host smart-832827f1-c066-4bca-aa03-b40c6661ee61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93885
6585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.938856585
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.161301302
Short name T1635
Test name
Test status
Simulation time 9334961629 ps
CPU time 269.98 seconds
Started Jul 25 07:01:27 PM PDT 24
Finished Jul 25 07:05:57 PM PDT 24
Peak memory 215536 kb
Host smart-fd578125-ec9b-4984-8810-a169436ec8f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16130
1302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.161301302
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.1093648103
Short name T2436
Test name
Test status
Simulation time 3534410168 ps
CPU time 36.07 seconds
Started Jul 25 07:01:29 PM PDT 24
Finished Jul 25 07:02:05 PM PDT 24
Peak memory 216980 kb
Host smart-70d77c9b-ff0b-4071-b84d-bd27c65e04e0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1093648103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.1093648103
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.2991407754
Short name T592
Test name
Test status
Simulation time 274052262 ps
CPU time 1 seconds
Started Jul 25 07:01:28 PM PDT 24
Finished Jul 25 07:01:30 PM PDT 24
Peak memory 207168 kb
Host smart-8749b5ab-f5a6-44af-88c8-115e35091f2d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2991407754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.2991407754
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.1479346531
Short name T660
Test name
Test status
Simulation time 188603301 ps
CPU time 0.9 seconds
Started Jul 25 07:01:29 PM PDT 24
Finished Jul 25 07:01:30 PM PDT 24
Peak memory 207156 kb
Host smart-6b98dbe0-4c53-45b5-82e7-f6c29bfe5a7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14793
46531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.1479346531
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.1565482601
Short name T2557
Test name
Test status
Simulation time 6656182231 ps
CPU time 54.33 seconds
Started Jul 25 07:01:26 PM PDT 24
Finished Jul 25 07:02:20 PM PDT 24
Peak memory 216908 kb
Host smart-465b9455-908a-455e-8c9f-b6c8d4c4f88a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15654
82601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.1565482601
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.4173821342
Short name T2831
Test name
Test status
Simulation time 6502372841 ps
CPU time 192.7 seconds
Started Jul 25 07:01:28 PM PDT 24
Finished Jul 25 07:04:42 PM PDT 24
Peak memory 215628 kb
Host smart-d4160941-99a8-415b-aa0b-f65675e3678b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4173821342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.4173821342
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.4285072256
Short name T391
Test name
Test status
Simulation time 226411272 ps
CPU time 0.92 seconds
Started Jul 25 07:01:27 PM PDT 24
Finished Jul 25 07:01:28 PM PDT 24
Peak memory 207124 kb
Host smart-016f59d5-bad3-4e80-a1b8-040974bc247f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4285072256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.4285072256
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.1362004793
Short name T1686
Test name
Test status
Simulation time 157315503 ps
CPU time 0.88 seconds
Started Jul 25 07:01:28 PM PDT 24
Finished Jul 25 07:01:30 PM PDT 24
Peak memory 207124 kb
Host smart-9802195c-0111-4a32-9342-c9a4693f7c02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13620
04793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.1362004793
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.3662697937
Short name T155
Test name
Test status
Simulation time 234454518 ps
CPU time 0.99 seconds
Started Jul 25 07:01:40 PM PDT 24
Finished Jul 25 07:01:41 PM PDT 24
Peak memory 207116 kb
Host smart-8a54fa19-54c1-4f91-817d-a01ff5ee5d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36626
97937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.3662697937
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.4138530174
Short name T1716
Test name
Test status
Simulation time 189699812 ps
CPU time 0.94 seconds
Started Jul 25 07:01:35 PM PDT 24
Finished Jul 25 07:01:36 PM PDT 24
Peak memory 207136 kb
Host smart-348d6056-046f-46f3-9330-de11dabe840e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41385
30174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.4138530174
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.3810584354
Short name T2437
Test name
Test status
Simulation time 187344139 ps
CPU time 0.92 seconds
Started Jul 25 07:01:40 PM PDT 24
Finished Jul 25 07:01:41 PM PDT 24
Peak memory 207132 kb
Host smart-e171d305-10cd-43ac-8085-fe488747dabb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38105
84354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.3810584354
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.1654783059
Short name T2328
Test name
Test status
Simulation time 167911712 ps
CPU time 0.95 seconds
Started Jul 25 07:01:41 PM PDT 24
Finished Jul 25 07:01:42 PM PDT 24
Peak memory 207108 kb
Host smart-0081b93e-a82e-406a-a8c2-7e120df969fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16547
83059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.1654783059
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.1592830220
Short name T1750
Test name
Test status
Simulation time 149091208 ps
CPU time 0.83 seconds
Started Jul 25 07:01:40 PM PDT 24
Finished Jul 25 07:01:41 PM PDT 24
Peak memory 207148 kb
Host smart-9860d4d3-e838-4149-9841-00131973dd05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15928
30220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.1592830220
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.83954213
Short name T2238
Test name
Test status
Simulation time 195823048 ps
CPU time 1.03 seconds
Started Jul 25 07:01:36 PM PDT 24
Finished Jul 25 07:01:38 PM PDT 24
Peak memory 207084 kb
Host smart-a0a2e651-ea08-4a1f-80bf-ebf96a4d7ddd
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=83954213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.83954213
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.703243672
Short name T2298
Test name
Test status
Simulation time 173215539 ps
CPU time 0.86 seconds
Started Jul 25 07:01:37 PM PDT 24
Finished Jul 25 07:01:39 PM PDT 24
Peak memory 207068 kb
Host smart-f11b8b44-a0ce-4d07-9191-fdaa537d542d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70324
3672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.703243672
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.3362425393
Short name T37
Test name
Test status
Simulation time 67824046 ps
CPU time 0.79 seconds
Started Jul 25 07:01:36 PM PDT 24
Finished Jul 25 07:01:38 PM PDT 24
Peak memory 207132 kb
Host smart-aecb25a3-304e-44ee-b98f-2dd7a6f68723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33624
25393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.3362425393
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.195908301
Short name T2684
Test name
Test status
Simulation time 17675536073 ps
CPU time 44.34 seconds
Started Jul 25 07:01:36 PM PDT 24
Finished Jul 25 07:02:21 PM PDT 24
Peak memory 215564 kb
Host smart-fcf7da9c-1686-4e8d-bc8f-1f549eed9a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19590
8301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.195908301
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.768538338
Short name T2737
Test name
Test status
Simulation time 166145682 ps
CPU time 0.89 seconds
Started Jul 25 07:01:34 PM PDT 24
Finished Jul 25 07:01:35 PM PDT 24
Peak memory 207156 kb
Host smart-a380fe63-dd8d-47ac-bcb0-ac97fad02b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76853
8338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.768538338
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.2130067443
Short name T796
Test name
Test status
Simulation time 183887572 ps
CPU time 0.88 seconds
Started Jul 25 07:01:36 PM PDT 24
Finished Jul 25 07:01:38 PM PDT 24
Peak memory 207024 kb
Host smart-5dcc2599-2968-4a0b-8bf7-92dc269922d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21300
67443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.2130067443
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.2894397222
Short name T2626
Test name
Test status
Simulation time 3775329663 ps
CPU time 39.43 seconds
Started Jul 25 07:01:43 PM PDT 24
Finished Jul 25 07:02:22 PM PDT 24
Peak memory 223716 kb
Host smart-f26648fc-4239-45e0-907d-3319d73cef55
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894397222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.2894397222
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.1616745234
Short name T2503
Test name
Test status
Simulation time 11334756858 ps
CPU time 86.12 seconds
Started Jul 25 07:01:38 PM PDT 24
Finished Jul 25 07:03:04 PM PDT 24
Peak memory 217740 kb
Host smart-86c35499-c27e-4379-8dc3-86009c404463
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1616745234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.1616745234
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.3004167224
Short name T1980
Test name
Test status
Simulation time 8107026827 ps
CPU time 40.66 seconds
Started Jul 25 07:01:36 PM PDT 24
Finished Jul 25 07:02:17 PM PDT 24
Peak memory 223660 kb
Host smart-3a4fa073-a638-4344-9a07-fd4b7cc32f53
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004167224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.3004167224
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.2453367631
Short name T1470
Test name
Test status
Simulation time 192495144 ps
CPU time 0.89 seconds
Started Jul 25 07:01:36 PM PDT 24
Finished Jul 25 07:01:38 PM PDT 24
Peak memory 207052 kb
Host smart-2a904a73-7bd6-4c9f-8100-b584c67f334b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24533
67631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.2453367631
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.2320807851
Short name T2062
Test name
Test status
Simulation time 155011546 ps
CPU time 0.87 seconds
Started Jul 25 07:01:38 PM PDT 24
Finished Jul 25 07:01:39 PM PDT 24
Peak memory 207128 kb
Host smart-5cd218fe-a7ab-4e6f-8c87-5d68d6b7272e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23208
07851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.2320807851
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.1883736790
Short name T2754
Test name
Test status
Simulation time 197413606 ps
CPU time 0.87 seconds
Started Jul 25 07:01:37 PM PDT 24
Finished Jul 25 07:01:38 PM PDT 24
Peak memory 207056 kb
Host smart-f0382b31-cd8d-40c7-ab1a-e24f421c4fd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18837
36790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.1883736790
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.351362197
Short name T948
Test name
Test status
Simulation time 153989256 ps
CPU time 0.86 seconds
Started Jul 25 07:01:37 PM PDT 24
Finished Jul 25 07:01:39 PM PDT 24
Peak memory 207148 kb
Host smart-3db7d454-800c-4b69-b591-0785aa6f800a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35136
2197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.351362197
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.3831674974
Short name T2624
Test name
Test status
Simulation time 150395262 ps
CPU time 0.84 seconds
Started Jul 25 07:01:34 PM PDT 24
Finished Jul 25 07:01:35 PM PDT 24
Peak memory 207148 kb
Host smart-e9d87f54-e28a-4134-b416-06c50f670074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38316
74974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.3831674974
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.3956350438
Short name T1145
Test name
Test status
Simulation time 196175241 ps
CPU time 0.98 seconds
Started Jul 25 07:01:36 PM PDT 24
Finished Jul 25 07:01:37 PM PDT 24
Peak memory 207136 kb
Host smart-d066542b-c570-450c-b6c1-e68b6a5d103e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39563
50438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.3956350438
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.2437147072
Short name T1389
Test name
Test status
Simulation time 3794301647 ps
CPU time 113.13 seconds
Started Jul 25 07:01:38 PM PDT 24
Finished Jul 25 07:03:32 PM PDT 24
Peak memory 215504 kb
Host smart-def7be15-ca47-448d-a4cd-8573f5c3093c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2437147072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.2437147072
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.651346071
Short name T1875
Test name
Test status
Simulation time 162864474 ps
CPU time 0.91 seconds
Started Jul 25 07:01:37 PM PDT 24
Finished Jul 25 07:01:38 PM PDT 24
Peak memory 207116 kb
Host smart-0ce977b0-5efa-4baa-9b65-08e3df44c915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65134
6071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.651346071
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.4248388605
Short name T394
Test name
Test status
Simulation time 158123081 ps
CPU time 0.91 seconds
Started Jul 25 07:01:40 PM PDT 24
Finished Jul 25 07:01:41 PM PDT 24
Peak memory 207128 kb
Host smart-828bea33-8773-4c4a-a52c-5efc383c8b80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42483
88605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.4248388605
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.3078167726
Short name T1924
Test name
Test status
Simulation time 1097374071 ps
CPU time 2.61 seconds
Started Jul 25 07:01:36 PM PDT 24
Finished Jul 25 07:01:40 PM PDT 24
Peak memory 207292 kb
Host smart-6c02f10e-e4fa-4bed-9b68-b528d15466eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30781
67726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.3078167726
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.1863854184
Short name T1769
Test name
Test status
Simulation time 5918978326 ps
CPU time 175.42 seconds
Started Jul 25 07:01:35 PM PDT 24
Finished Jul 25 07:04:31 PM PDT 24
Peak memory 215592 kb
Host smart-3002f438-91ea-426d-bdfb-7a6a0720be7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18638
54184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.1863854184
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_timeout_missing_host_handshake.2167996688
Short name T2515
Test name
Test status
Simulation time 6376066722 ps
CPU time 41.63 seconds
Started Jul 25 07:01:27 PM PDT 24
Finished Jul 25 07:02:09 PM PDT 24
Peak memory 207364 kb
Host smart-b2008017-528b-4aeb-8b8a-d0212179367c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167996688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_timeout_missing_host
_handshake.2167996688
Directory /workspace/5.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.504735410
Short name T1694
Test name
Test status
Simulation time 36062121 ps
CPU time 0.65 seconds
Started Jul 25 07:01:57 PM PDT 24
Finished Jul 25 07:01:58 PM PDT 24
Peak memory 207108 kb
Host smart-16e23d99-c47e-4462-b49e-5017c0c014ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=504735410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.504735410
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.394603534
Short name T1274
Test name
Test status
Simulation time 3589175674 ps
CPU time 5.4 seconds
Started Jul 25 07:01:39 PM PDT 24
Finished Jul 25 07:01:45 PM PDT 24
Peak memory 207356 kb
Host smart-6d07efba-95ad-4c3f-bac9-abf31e92c8aa
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394603534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon
_wake_disconnect.394603534
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.3344119475
Short name T1720
Test name
Test status
Simulation time 13410407717 ps
CPU time 14.93 seconds
Started Jul 25 07:01:38 PM PDT 24
Finished Jul 25 07:01:53 PM PDT 24
Peak memory 207340 kb
Host smart-627df068-07ec-4180-a408-17f58803dc38
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344119475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.3344119475
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.1610408537
Short name T942
Test name
Test status
Simulation time 23336689101 ps
CPU time 28 seconds
Started Jul 25 07:01:50 PM PDT 24
Finished Jul 25 07:02:18 PM PDT 24
Peak memory 207388 kb
Host smart-c8f17a0d-5b57-4964-834a-0420493d9943
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610408537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_ao
n_wake_resume.1610408537
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.952804694
Short name T613
Test name
Test status
Simulation time 165694126 ps
CPU time 0.87 seconds
Started Jul 25 07:01:43 PM PDT 24
Finished Jul 25 07:01:44 PM PDT 24
Peak memory 207124 kb
Host smart-f1a1e2b0-2c99-4f95-9b2b-3233c25a83c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95280
4694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.952804694
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.2839585085
Short name T1168
Test name
Test status
Simulation time 249592202 ps
CPU time 1.01 seconds
Started Jul 25 07:01:46 PM PDT 24
Finished Jul 25 07:01:47 PM PDT 24
Peak memory 207132 kb
Host smart-79578777-49d6-4e61-935d-466b94ea7be1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28395
85085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.2839585085
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.50009544
Short name T2689
Test name
Test status
Simulation time 466382884 ps
CPU time 1.28 seconds
Started Jul 25 07:01:44 PM PDT 24
Finished Jul 25 07:01:46 PM PDT 24
Peak memory 207196 kb
Host smart-4447e65a-bb53-449a-a683-37ebea9c1523
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=50009544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.50009544
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.2524897049
Short name T2778
Test name
Test status
Simulation time 19078290029 ps
CPU time 40.38 seconds
Started Jul 25 07:01:47 PM PDT 24
Finished Jul 25 07:02:27 PM PDT 24
Peak memory 207372 kb
Host smart-1c42c87f-235a-446a-b9b6-16a35341945a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25248
97049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.2524897049
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_device_timeout.1290181782
Short name T250
Test name
Test status
Simulation time 199396095 ps
CPU time 0.96 seconds
Started Jul 25 07:01:44 PM PDT 24
Finished Jul 25 07:01:45 PM PDT 24
Peak memory 207132 kb
Host smart-0f0fb07d-9082-4ee3-bd43-9cc4326faff5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290181782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_timeout.1290181782
Directory /workspace/6.usbdev_device_timeout/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.3842023192
Short name T1235
Test name
Test status
Simulation time 383668816 ps
CPU time 1.31 seconds
Started Jul 25 07:01:46 PM PDT 24
Finished Jul 25 07:01:47 PM PDT 24
Peak memory 207108 kb
Host smart-b200a196-f518-4f87-92ca-920cdc890234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38420
23192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.3842023192
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.2563944353
Short name T1916
Test name
Test status
Simulation time 157324162 ps
CPU time 0.86 seconds
Started Jul 25 07:01:45 PM PDT 24
Finished Jul 25 07:01:47 PM PDT 24
Peak memory 207084 kb
Host smart-fba7abf9-460b-445e-8a83-bf628abeeaa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25639
44353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.2563944353
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.2931925987
Short name T2709
Test name
Test status
Simulation time 52736965 ps
CPU time 0.7 seconds
Started Jul 25 07:01:44 PM PDT 24
Finished Jul 25 07:01:45 PM PDT 24
Peak memory 207116 kb
Host smart-f290e3f9-730d-45dc-b502-fac1e8382687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29319
25987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.2931925987
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.1918772857
Short name T449
Test name
Test status
Simulation time 902614671 ps
CPU time 2.35 seconds
Started Jul 25 07:01:48 PM PDT 24
Finished Jul 25 07:01:51 PM PDT 24
Peak memory 207256 kb
Host smart-bb462147-4226-490e-a587-cffba6c4c8f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19187
72857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.1918772857
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.1980100911
Short name T1406
Test name
Test status
Simulation time 335423394 ps
CPU time 2.15 seconds
Started Jul 25 07:01:52 PM PDT 24
Finished Jul 25 07:01:54 PM PDT 24
Peak memory 207356 kb
Host smart-44afc8c9-4fcd-44f8-bced-e5a30af8f71a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19801
00911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.1980100911
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.1738431526
Short name T1408
Test name
Test status
Simulation time 199450572 ps
CPU time 1 seconds
Started Jul 25 07:01:45 PM PDT 24
Finished Jul 25 07:01:46 PM PDT 24
Peak memory 207356 kb
Host smart-d5689922-4052-43e1-a5e0-6fdd3657f21a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1738431526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.1738431526
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.1584935600
Short name T2395
Test name
Test status
Simulation time 152853807 ps
CPU time 0.87 seconds
Started Jul 25 07:01:45 PM PDT 24
Finished Jul 25 07:01:46 PM PDT 24
Peak memory 207080 kb
Host smart-58b78317-f99b-43b7-80d6-077e4eb6ba91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15849
35600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.1584935600
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.2803647750
Short name T1244
Test name
Test status
Simulation time 185764262 ps
CPU time 0.95 seconds
Started Jul 25 07:01:46 PM PDT 24
Finished Jul 25 07:01:47 PM PDT 24
Peak memory 207112 kb
Host smart-11b19f25-5762-4f20-9119-d3b4b4c6db86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28036
47750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.2803647750
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.3846972998
Short name T647
Test name
Test status
Simulation time 6881663673 ps
CPU time 206.96 seconds
Started Jul 25 07:01:48 PM PDT 24
Finished Jul 25 07:05:15 PM PDT 24
Peak memory 215616 kb
Host smart-961fd0c1-294e-4b60-8b5c-ecbb7df63c21
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3846972998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.3846972998
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.777643548
Short name T679
Test name
Test status
Simulation time 209774653 ps
CPU time 0.95 seconds
Started Jul 25 07:01:45 PM PDT 24
Finished Jul 25 07:01:46 PM PDT 24
Peak memory 207168 kb
Host smart-b2ffc3f0-2dea-4a41-87b2-494edb1e4766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77764
3548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.777643548
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.3965874492
Short name T2446
Test name
Test status
Simulation time 23301466142 ps
CPU time 33.95 seconds
Started Jul 25 07:01:46 PM PDT 24
Finished Jul 25 07:02:20 PM PDT 24
Peak memory 207332 kb
Host smart-f07bc906-de7c-46f9-8e43-da8059244ee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39658
74492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.3965874492
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.3518804206
Short name T2232
Test name
Test status
Simulation time 3345932198 ps
CPU time 5.71 seconds
Started Jul 25 07:01:46 PM PDT 24
Finished Jul 25 07:01:52 PM PDT 24
Peak memory 207400 kb
Host smart-47a0fad9-c976-4ba5-afaa-d55c0970c9c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35188
04206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.3518804206
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.1832072447
Short name T1456
Test name
Test status
Simulation time 6312812420 ps
CPU time 46.06 seconds
Started Jul 25 07:01:46 PM PDT 24
Finished Jul 25 07:02:32 PM PDT 24
Peak memory 223776 kb
Host smart-5c2440e6-a126-4437-bc3b-eb1ed4e343d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18320
72447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.1832072447
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.3865008695
Short name T1033
Test name
Test status
Simulation time 5474025879 ps
CPU time 161.28 seconds
Started Jul 25 07:01:47 PM PDT 24
Finished Jul 25 07:04:29 PM PDT 24
Peak memory 215544 kb
Host smart-12aaf052-59c5-4fa1-a49b-517d461808dc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3865008695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.3865008695
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.2367653955
Short name T2122
Test name
Test status
Simulation time 275992328 ps
CPU time 1.05 seconds
Started Jul 25 07:01:44 PM PDT 24
Finished Jul 25 07:01:45 PM PDT 24
Peak memory 207148 kb
Host smart-34171152-2593-460e-8b69-c037422ba9cd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2367653955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.2367653955
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.1722019473
Short name T2022
Test name
Test status
Simulation time 210643737 ps
CPU time 0.93 seconds
Started Jul 25 07:01:50 PM PDT 24
Finished Jul 25 07:01:51 PM PDT 24
Peak memory 207064 kb
Host smart-31c299f6-32a8-4e6a-ac69-bd35b6c8d30a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17220
19473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.1722019473
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.3322985228
Short name T2774
Test name
Test status
Simulation time 4665764083 ps
CPU time 34.65 seconds
Started Jul 25 07:01:46 PM PDT 24
Finished Jul 25 07:02:21 PM PDT 24
Peak memory 215576 kb
Host smart-9b0fec4d-631e-46ea-8cc6-27a988022c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33229
85228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.3322985228
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.2942186736
Short name T2088
Test name
Test status
Simulation time 5282100096 ps
CPU time 157.35 seconds
Started Jul 25 07:01:48 PM PDT 24
Finished Jul 25 07:04:26 PM PDT 24
Peak memory 215612 kb
Host smart-9bc4aa11-67ac-429c-9d86-37068887d3dc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2942186736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.2942186736
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.3522833891
Short name T681
Test name
Test status
Simulation time 174526762 ps
CPU time 0.88 seconds
Started Jul 25 07:01:45 PM PDT 24
Finished Jul 25 07:01:46 PM PDT 24
Peak memory 207140 kb
Host smart-649a95d9-d4d1-43f8-831a-e8abb9f2011d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3522833891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.3522833891
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.897997931
Short name T745
Test name
Test status
Simulation time 161473084 ps
CPU time 0.87 seconds
Started Jul 25 07:01:46 PM PDT 24
Finished Jul 25 07:01:47 PM PDT 24
Peak memory 207116 kb
Host smart-463d5601-1b06-483c-8e74-9158ff0d435d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89799
7931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.897997931
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.3619974351
Short name T2491
Test name
Test status
Simulation time 176548554 ps
CPU time 0.95 seconds
Started Jul 25 07:01:46 PM PDT 24
Finished Jul 25 07:01:47 PM PDT 24
Peak memory 207120 kb
Host smart-418bd525-d92d-480b-89d4-02606f8f07f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36199
74351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.3619974351
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.1976791027
Short name T2818
Test name
Test status
Simulation time 156250815 ps
CPU time 0.84 seconds
Started Jul 25 07:01:44 PM PDT 24
Finished Jul 25 07:01:45 PM PDT 24
Peak memory 207188 kb
Host smart-9d10e06a-b8b2-4244-9235-fa552f80918e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19767
91027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.1976791027
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.2105498150
Short name T1542
Test name
Test status
Simulation time 200063944 ps
CPU time 0.9 seconds
Started Jul 25 07:01:46 PM PDT 24
Finished Jul 25 07:01:47 PM PDT 24
Peak memory 207112 kb
Host smart-5e72d688-0429-4e6d-a668-0ea0f81e8a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21054
98150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.2105498150
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.1115083222
Short name T2081
Test name
Test status
Simulation time 157216579 ps
CPU time 0.87 seconds
Started Jul 25 07:01:46 PM PDT 24
Finished Jul 25 07:01:47 PM PDT 24
Peak memory 207072 kb
Host smart-bc83c5c6-9c96-4785-b2d9-4020df6d66dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11150
83222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.1115083222
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.2488256083
Short name T187
Test name
Test status
Simulation time 154144313 ps
CPU time 0.88 seconds
Started Jul 25 07:01:51 PM PDT 24
Finished Jul 25 07:01:52 PM PDT 24
Peak memory 207112 kb
Host smart-5678f7a9-41d3-4f52-844e-c47a7bc46617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24882
56083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.2488256083
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.2417224998
Short name T2158
Test name
Test status
Simulation time 190337593 ps
CPU time 0.91 seconds
Started Jul 25 07:01:45 PM PDT 24
Finished Jul 25 07:01:46 PM PDT 24
Peak memory 207148 kb
Host smart-695af774-d5cd-4f46-9495-f87ecf3fa4ff
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2417224998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.2417224998
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.758601728
Short name T570
Test name
Test status
Simulation time 166343047 ps
CPU time 0.88 seconds
Started Jul 25 07:01:58 PM PDT 24
Finished Jul 25 07:01:59 PM PDT 24
Peak memory 207088 kb
Host smart-11ce2c7c-d001-4525-bfa6-f62bcc7070bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75860
1728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.758601728
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.2448308855
Short name T2327
Test name
Test status
Simulation time 41202211 ps
CPU time 0.68 seconds
Started Jul 25 07:01:55 PM PDT 24
Finished Jul 25 07:01:56 PM PDT 24
Peak memory 207020 kb
Host smart-9b8747fc-7d7c-4bf4-8885-b4e74732aa09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24483
08855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.2448308855
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.1107251447
Short name T2171
Test name
Test status
Simulation time 22592321342 ps
CPU time 58.38 seconds
Started Jul 25 07:01:55 PM PDT 24
Finished Jul 25 07:02:54 PM PDT 24
Peak memory 215664 kb
Host smart-50bac175-3e4d-4a76-8980-8c93b4c64242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11072
51447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.1107251447
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.704348879
Short name T2639
Test name
Test status
Simulation time 170327987 ps
CPU time 0.9 seconds
Started Jul 25 07:01:55 PM PDT 24
Finished Jul 25 07:01:56 PM PDT 24
Peak memory 207128 kb
Host smart-fdd40940-2865-468f-80bf-2c4fcfad30b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70434
8879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.704348879
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.1832795623
Short name T1626
Test name
Test status
Simulation time 207837344 ps
CPU time 0.92 seconds
Started Jul 25 07:01:56 PM PDT 24
Finished Jul 25 07:01:58 PM PDT 24
Peak memory 207124 kb
Host smart-7867d49f-caac-4dd4-862a-045e44c7b651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18327
95623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.1832795623
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.1250968773
Short name T191
Test name
Test status
Simulation time 5594885018 ps
CPU time 40.84 seconds
Started Jul 25 07:01:59 PM PDT 24
Finished Jul 25 07:02:40 PM PDT 24
Peak memory 217316 kb
Host smart-e6828277-10d8-4a4d-9c64-a407442e912b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250968773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.1250968773
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.2949201853
Short name T2220
Test name
Test status
Simulation time 7461299004 ps
CPU time 32.5 seconds
Started Jul 25 07:01:56 PM PDT 24
Finished Jul 25 07:02:29 PM PDT 24
Peak memory 223740 kb
Host smart-c2776bbb-673a-4225-b679-65b12cffe9a9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2949201853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.2949201853
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.848753771
Short name T1698
Test name
Test status
Simulation time 16625336048 ps
CPU time 100.27 seconds
Started Jul 25 07:01:58 PM PDT 24
Finished Jul 25 07:03:39 PM PDT 24
Peak memory 217744 kb
Host smart-ef098175-8e2a-4c43-b979-2381bb36b248
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=848753771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.848753771
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.815740873
Short name T1278
Test name
Test status
Simulation time 197049664 ps
CPU time 0.9 seconds
Started Jul 25 07:01:57 PM PDT 24
Finished Jul 25 07:01:58 PM PDT 24
Peak memory 207148 kb
Host smart-2fd792a8-38cd-4db4-97b8-b4437e1e252c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81574
0873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.815740873
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.179438316
Short name T687
Test name
Test status
Simulation time 155935509 ps
CPU time 0.88 seconds
Started Jul 25 07:01:56 PM PDT 24
Finished Jul 25 07:01:58 PM PDT 24
Peak memory 207120 kb
Host smart-702feeb3-7626-4b54-8862-05113ffb4e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17943
8316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.179438316
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.1615328375
Short name T1848
Test name
Test status
Simulation time 160824373 ps
CPU time 0.83 seconds
Started Jul 25 07:01:57 PM PDT 24
Finished Jul 25 07:01:58 PM PDT 24
Peak memory 207128 kb
Host smart-ce213ae6-45fe-4d83-80f1-c0ef57139163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16153
28375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.1615328375
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.488879011
Short name T2387
Test name
Test status
Simulation time 169617883 ps
CPU time 0.84 seconds
Started Jul 25 07:01:57 PM PDT 24
Finished Jul 25 07:01:58 PM PDT 24
Peak memory 206740 kb
Host smart-25c32262-9259-4c73-b1fc-f4747a03e661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48887
9011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.488879011
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.3312069809
Short name T1987
Test name
Test status
Simulation time 159331185 ps
CPU time 0.87 seconds
Started Jul 25 07:01:56 PM PDT 24
Finished Jul 25 07:01:57 PM PDT 24
Peak memory 207108 kb
Host smart-75ee3398-1ebb-49b7-952d-25550406efd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33120
69809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.3312069809
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.1511130289
Short name T431
Test name
Test status
Simulation time 199541764 ps
CPU time 0.93 seconds
Started Jul 25 07:01:56 PM PDT 24
Finished Jul 25 07:01:57 PM PDT 24
Peak memory 207116 kb
Host smart-b72d5870-053d-4f8a-a983-e361456cedb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15111
30289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.1511130289
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.27148353
Short name T114
Test name
Test status
Simulation time 3230792723 ps
CPU time 24.75 seconds
Started Jul 25 07:01:54 PM PDT 24
Finished Jul 25 07:02:19 PM PDT 24
Peak memory 215528 kb
Host smart-e2e7b63a-cf41-43bd-90ff-85b2f0845db7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=27148353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.27148353
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.4159156116
Short name T2607
Test name
Test status
Simulation time 204606296 ps
CPU time 0.87 seconds
Started Jul 25 07:01:56 PM PDT 24
Finished Jul 25 07:01:58 PM PDT 24
Peak memory 207140 kb
Host smart-9414d5e1-82d7-413c-868d-f78a7684af0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41591
56116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.4159156116
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.3649321970
Short name T2112
Test name
Test status
Simulation time 182887907 ps
CPU time 0.88 seconds
Started Jul 25 07:01:56 PM PDT 24
Finished Jul 25 07:01:57 PM PDT 24
Peak memory 207164 kb
Host smart-1643a178-3c39-4662-8bac-1ea77e421d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36493
21970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.3649321970
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.3213839352
Short name T2083
Test name
Test status
Simulation time 1222906845 ps
CPU time 3.09 seconds
Started Jul 25 07:01:54 PM PDT 24
Finished Jul 25 07:01:58 PM PDT 24
Peak memory 207232 kb
Host smart-b7ad76d8-332b-4133-9e71-f63c12966aaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32138
39352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.3213839352
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.2594426036
Short name T19
Test name
Test status
Simulation time 7457041784 ps
CPU time 56.28 seconds
Started Jul 25 07:02:00 PM PDT 24
Finished Jul 25 07:02:56 PM PDT 24
Peak memory 207352 kb
Host smart-62df877b-ca4d-4e1d-9d53-05d977a64509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25944
26036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.2594426036
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_timeout_missing_host_handshake.373828486
Short name T1815
Test name
Test status
Simulation time 1516003586 ps
CPU time 10.73 seconds
Started Jul 25 07:01:45 PM PDT 24
Finished Jul 25 07:01:56 PM PDT 24
Peak memory 207276 kb
Host smart-e7a9d15a-e3bf-49a5-a15f-8c6feb6c7c4b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373828486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_timeout_missing_host_
handshake.373828486
Directory /workspace/6.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.1677214975
Short name T2849
Test name
Test status
Simulation time 93145106 ps
CPU time 0.73 seconds
Started Jul 25 07:02:05 PM PDT 24
Finished Jul 25 07:02:06 PM PDT 24
Peak memory 207148 kb
Host smart-58426885-b42c-4ba9-afbe-b56d56e9e117
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1677214975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.1677214975
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.2390765138
Short name T1022
Test name
Test status
Simulation time 3562570547 ps
CPU time 5.26 seconds
Started Jul 25 07:01:56 PM PDT 24
Finished Jul 25 07:02:02 PM PDT 24
Peak memory 207368 kb
Host smart-656ad404-a21b-4f4e-8168-acc869150482
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390765138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ao
n_wake_disconnect.2390765138
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.3597968860
Short name T2043
Test name
Test status
Simulation time 13392150487 ps
CPU time 16.31 seconds
Started Jul 25 07:01:56 PM PDT 24
Finished Jul 25 07:02:13 PM PDT 24
Peak memory 207344 kb
Host smart-d0bab9aa-7341-4e39-b235-b910cfe98c30
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597968860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.3597968860
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.3854409309
Short name T2545
Test name
Test status
Simulation time 23379116205 ps
CPU time 30.65 seconds
Started Jul 25 07:02:02 PM PDT 24
Finished Jul 25 07:02:33 PM PDT 24
Peak memory 207312 kb
Host smart-04ea124a-fb76-4a31-ab8f-5a6644e91b68
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854409309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ao
n_wake_resume.3854409309
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.3177277437
Short name T2456
Test name
Test status
Simulation time 158300229 ps
CPU time 0.93 seconds
Started Jul 25 07:01:59 PM PDT 24
Finished Jul 25 07:02:00 PM PDT 24
Peak memory 207136 kb
Host smart-a628b9b7-0fa2-46ba-a238-5943ef54a4a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31772
77437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.3177277437
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.2623454621
Short name T85
Test name
Test status
Simulation time 153643703 ps
CPU time 0.87 seconds
Started Jul 25 07:01:57 PM PDT 24
Finished Jul 25 07:01:59 PM PDT 24
Peak memory 207136 kb
Host smart-0a6de66d-7f27-465f-a8af-18525deb1639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26234
54621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.2623454621
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.337449882
Short name T436
Test name
Test status
Simulation time 305909413 ps
CPU time 1.23 seconds
Started Jul 25 07:01:53 PM PDT 24
Finished Jul 25 07:01:55 PM PDT 24
Peak memory 207084 kb
Host smart-2a90da7f-2cf6-4f2b-879a-c52ed37e4aa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33744
9882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.337449882
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.2471467688
Short name T424
Test name
Test status
Simulation time 1040119915 ps
CPU time 2.55 seconds
Started Jul 25 07:01:54 PM PDT 24
Finished Jul 25 07:01:57 PM PDT 24
Peak memory 207352 kb
Host smart-80e1eba5-336b-4af8-87d6-bdcbc87b8b57
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2471467688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.2471467688
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.534383534
Short name T982
Test name
Test status
Simulation time 13323631917 ps
CPU time 27.84 seconds
Started Jul 25 07:01:57 PM PDT 24
Finished Jul 25 07:02:25 PM PDT 24
Peak memory 207376 kb
Host smart-65fbd2cb-d125-4054-80fc-420a7f9a68bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53438
3534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.534383534
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_device_timeout.2672696556
Short name T509
Test name
Test status
Simulation time 3645316562 ps
CPU time 23.61 seconds
Started Jul 25 07:01:54 PM PDT 24
Finished Jul 25 07:02:18 PM PDT 24
Peak memory 207480 kb
Host smart-e6ec574f-2bfd-4732-8343-b59e78d3a426
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672696556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_timeout.2672696556
Directory /workspace/7.usbdev_device_timeout/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.4242197113
Short name T1247
Test name
Test status
Simulation time 511244995 ps
CPU time 1.77 seconds
Started Jul 25 07:01:56 PM PDT 24
Finished Jul 25 07:01:59 PM PDT 24
Peak memory 207096 kb
Host smart-a13ec6bb-b24d-4a45-9b12-8521a9b3f31e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42421
97113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.4242197113
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.157988016
Short name T1890
Test name
Test status
Simulation time 172748161 ps
CPU time 0.88 seconds
Started Jul 25 07:02:00 PM PDT 24
Finished Jul 25 07:02:01 PM PDT 24
Peak memory 207104 kb
Host smart-935712c3-165d-453a-9a9f-3c093c06fb58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15798
8016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.157988016
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.1114957255
Short name T2667
Test name
Test status
Simulation time 62735839 ps
CPU time 0.71 seconds
Started Jul 25 07:01:57 PM PDT 24
Finished Jul 25 07:01:58 PM PDT 24
Peak memory 207072 kb
Host smart-fabab44f-28d3-4106-88b0-96a1bfda5add
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11149
57255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.1114957255
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.952000279
Short name T597
Test name
Test status
Simulation time 767036765 ps
CPU time 2.18 seconds
Started Jul 25 07:01:57 PM PDT 24
Finished Jul 25 07:01:59 PM PDT 24
Peak memory 207336 kb
Host smart-872e7a6d-a594-4046-84e9-3a68615cd47b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95200
0279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.952000279
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.2776628146
Short name T591
Test name
Test status
Simulation time 202357663 ps
CPU time 2.11 seconds
Started Jul 25 07:01:57 PM PDT 24
Finished Jul 25 07:02:00 PM PDT 24
Peak memory 207296 kb
Host smart-521dbd8b-a072-4130-9c1c-0d5ccbd3fb82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27766
28146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.2776628146
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.1313076142
Short name T911
Test name
Test status
Simulation time 173523994 ps
CPU time 1.01 seconds
Started Jul 25 07:01:55 PM PDT 24
Finished Jul 25 07:01:56 PM PDT 24
Peak memory 207180 kb
Host smart-9f207c81-e124-495c-88bf-07e03b78bdc1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1313076142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.1313076142
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.2150887351
Short name T1028
Test name
Test status
Simulation time 144908703 ps
CPU time 0.83 seconds
Started Jul 25 07:02:00 PM PDT 24
Finished Jul 25 07:02:01 PM PDT 24
Peak memory 207104 kb
Host smart-7b0d7f32-3ad8-4414-81ee-7ba215cbd595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21508
87351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.2150887351
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.3631317511
Short name T1360
Test name
Test status
Simulation time 270205631 ps
CPU time 1.05 seconds
Started Jul 25 07:01:57 PM PDT 24
Finished Jul 25 07:01:58 PM PDT 24
Peak memory 206736 kb
Host smart-9d28bad1-a630-44f4-9cd8-9cc16793da90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36313
17511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.3631317511
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_invalid_sync.1609715874
Short name T2577
Test name
Test status
Simulation time 7948648111 ps
CPU time 59.08 seconds
Started Jul 25 07:01:56 PM PDT 24
Finished Jul 25 07:02:55 PM PDT 24
Peak memory 217036 kb
Host smart-fbbba4d0-e691-4270-808f-10d97a2fc6aa
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1609715874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.1609715874
Directory /workspace/7.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/7.usbdev_iso_retraction.3049223835
Short name T2191
Test name
Test status
Simulation time 10879626791 ps
CPU time 135.22 seconds
Started Jul 25 07:01:56 PM PDT 24
Finished Jul 25 07:04:12 PM PDT 24
Peak memory 207344 kb
Host smart-c2b87d46-da3b-4c33-8335-7f9520698c25
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3049223835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.3049223835
Directory /workspace/7.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.150934344
Short name T456
Test name
Test status
Simulation time 206651699 ps
CPU time 0.95 seconds
Started Jul 25 07:01:58 PM PDT 24
Finished Jul 25 07:01:59 PM PDT 24
Peak memory 207124 kb
Host smart-ebc45404-fdd1-446f-be31-0d32dd646d3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15093
4344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.150934344
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.105794611
Short name T1992
Test name
Test status
Simulation time 23329563565 ps
CPU time 25.8 seconds
Started Jul 25 07:01:55 PM PDT 24
Finished Jul 25 07:02:21 PM PDT 24
Peak memory 207412 kb
Host smart-d4557aa2-d000-4158-b809-38118f08e77b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10579
4611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.105794611
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.1731561926
Short name T1614
Test name
Test status
Simulation time 3342801438 ps
CPU time 5.01 seconds
Started Jul 25 07:01:56 PM PDT 24
Finished Jul 25 07:02:02 PM PDT 24
Peak memory 207368 kb
Host smart-33dfcd4c-26b8-46a3-a7e6-7b508d263a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17315
61926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.1731561926
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.3563633084
Short name T2680
Test name
Test status
Simulation time 6541046146 ps
CPU time 52.8 seconds
Started Jul 25 07:01:55 PM PDT 24
Finished Jul 25 07:02:48 PM PDT 24
Peak memory 216796 kb
Host smart-1013b898-6183-48c1-bda0-b0ba8bb1396d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35636
33084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.3563633084
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.4226737052
Short name T856
Test name
Test status
Simulation time 4903405877 ps
CPU time 141.68 seconds
Started Jul 25 07:01:58 PM PDT 24
Finished Jul 25 07:04:20 PM PDT 24
Peak memory 215620 kb
Host smart-64e7a465-de70-419d-9e88-3b5d08f27aa1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4226737052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.4226737052
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.3550002571
Short name T858
Test name
Test status
Simulation time 260021084 ps
CPU time 1.02 seconds
Started Jul 25 07:01:56 PM PDT 24
Finished Jul 25 07:01:57 PM PDT 24
Peak memory 207100 kb
Host smart-08e852fa-a728-4db8-92c3-2492d525c2b4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3550002571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.3550002571
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.3779064939
Short name T518
Test name
Test status
Simulation time 4331810954 ps
CPU time 130.79 seconds
Started Jul 25 07:01:57 PM PDT 24
Finished Jul 25 07:04:08 PM PDT 24
Peak memory 215488 kb
Host smart-c7c9f608-c169-4cbd-99f3-89e67f27b613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37790
64939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.3779064939
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.3744104519
Short name T1684
Test name
Test status
Simulation time 5074806632 ps
CPU time 51.18 seconds
Started Jul 25 07:01:59 PM PDT 24
Finished Jul 25 07:02:51 PM PDT 24
Peak memory 207448 kb
Host smart-18c5e237-630d-408f-8cf8-e3f1059bb2b9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3744104519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.3744104519
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.2809852761
Short name T1122
Test name
Test status
Simulation time 167558362 ps
CPU time 0.86 seconds
Started Jul 25 07:02:03 PM PDT 24
Finished Jul 25 07:02:04 PM PDT 24
Peak memory 207116 kb
Host smart-04f0b804-7253-4dab-b340-35ca42f5d633
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2809852761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.2809852761
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.2363139449
Short name T2565
Test name
Test status
Simulation time 163748653 ps
CPU time 0.86 seconds
Started Jul 25 07:02:13 PM PDT 24
Finished Jul 25 07:02:14 PM PDT 24
Peak memory 207148 kb
Host smart-39b55798-42c1-4ccf-8369-addc5072719f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23631
39449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.2363139449
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.1603406711
Short name T135
Test name
Test status
Simulation time 243723489 ps
CPU time 0.98 seconds
Started Jul 25 07:02:07 PM PDT 24
Finished Jul 25 07:02:08 PM PDT 24
Peak memory 207132 kb
Host smart-58216869-486e-4ea4-ae50-b31a1bfd74f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16034
06711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.1603406711
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.3536193723
Short name T127
Test name
Test status
Simulation time 234247316 ps
CPU time 1.02 seconds
Started Jul 25 07:02:15 PM PDT 24
Finished Jul 25 07:02:16 PM PDT 24
Peak memory 206884 kb
Host smart-d901f5f4-d024-4bcb-9370-2c6c20396a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35361
93723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.3536193723
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.2745792221
Short name T2137
Test name
Test status
Simulation time 176488081 ps
CPU time 0.86 seconds
Started Jul 25 07:02:04 PM PDT 24
Finished Jul 25 07:02:05 PM PDT 24
Peak memory 207160 kb
Host smart-f6656fbb-7d2d-4a82-8892-b01b2a899b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27457
92221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2745792221
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.2115800236
Short name T504
Test name
Test status
Simulation time 172334976 ps
CPU time 0.88 seconds
Started Jul 25 07:02:05 PM PDT 24
Finished Jul 25 07:02:06 PM PDT 24
Peak memory 207128 kb
Host smart-184dd0fe-498c-46f2-8fb1-41ec8279464b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21158
00236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.2115800236
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.3385702334
Short name T35
Test name
Test status
Simulation time 185678543 ps
CPU time 0.87 seconds
Started Jul 25 07:02:05 PM PDT 24
Finished Jul 25 07:02:06 PM PDT 24
Peak memory 207124 kb
Host smart-8281d888-3adf-43fa-8b15-f445ed9bd8e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33857
02334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.3385702334
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.3013504409
Short name T1402
Test name
Test status
Simulation time 199544199 ps
CPU time 0.96 seconds
Started Jul 25 07:02:05 PM PDT 24
Finished Jul 25 07:02:06 PM PDT 24
Peak memory 207124 kb
Host smart-dce37c26-fb3a-463b-b63b-ac4c29c2b069
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3013504409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.3013504409
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.2299473187
Short name T1773
Test name
Test status
Simulation time 154405071 ps
CPU time 0.84 seconds
Started Jul 25 07:02:07 PM PDT 24
Finished Jul 25 07:02:08 PM PDT 24
Peak memory 207124 kb
Host smart-685e54f1-e7ea-4640-8a8b-cdb74b85ae5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22994
73187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.2299473187
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.2917660018
Short name T2353
Test name
Test status
Simulation time 31848729 ps
CPU time 0.74 seconds
Started Jul 25 07:02:07 PM PDT 24
Finished Jul 25 07:02:08 PM PDT 24
Peak memory 207020 kb
Host smart-567cb1ec-5759-496d-8b48-4b50689e6982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29176
60018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.2917660018
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.3682474448
Short name T914
Test name
Test status
Simulation time 13216585419 ps
CPU time 33.03 seconds
Started Jul 25 07:02:08 PM PDT 24
Finished Jul 25 07:02:41 PM PDT 24
Peak memory 219824 kb
Host smart-24fbcae2-c2a3-4080-b5cf-3b305f092a7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36824
74448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.3682474448
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.1837251568
Short name T1152
Test name
Test status
Simulation time 177957851 ps
CPU time 0.94 seconds
Started Jul 25 07:02:13 PM PDT 24
Finished Jul 25 07:02:14 PM PDT 24
Peak memory 207148 kb
Host smart-50741015-eb74-49d5-92a6-b3b4ac406ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18372
51568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.1837251568
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.3467841738
Short name T525
Test name
Test status
Simulation time 220069824 ps
CPU time 0.93 seconds
Started Jul 25 07:02:14 PM PDT 24
Finished Jul 25 07:02:15 PM PDT 24
Peak memory 207088 kb
Host smart-8c184545-aa44-45a8-92ab-a9532598b45d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34678
41738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.3467841738
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.3405835196
Short name T720
Test name
Test status
Simulation time 12234510624 ps
CPU time 73.09 seconds
Started Jul 25 07:02:09 PM PDT 24
Finished Jul 25 07:03:22 PM PDT 24
Peak memory 223444 kb
Host smart-a956fb85-6eb5-48df-8986-b2205c3c69b0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405835196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.3405835196
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.2638827632
Short name T173
Test name
Test status
Simulation time 17316384500 ps
CPU time 483.53 seconds
Started Jul 25 07:02:07 PM PDT 24
Finished Jul 25 07:10:10 PM PDT 24
Peak memory 215620 kb
Host smart-af7509d3-e7de-47eb-ae14-2689d5366536
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2638827632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.2638827632
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.2447984832
Short name T1950
Test name
Test status
Simulation time 8055382208 ps
CPU time 52.68 seconds
Started Jul 25 07:02:13 PM PDT 24
Finished Jul 25 07:03:05 PM PDT 24
Peak memory 218340 kb
Host smart-d0f9cddf-3582-4ba7-a6b3-549777acc59d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447984832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.2447984832
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.3441610536
Short name T2076
Test name
Test status
Simulation time 200891289 ps
CPU time 0.92 seconds
Started Jul 25 07:02:15 PM PDT 24
Finished Jul 25 07:02:16 PM PDT 24
Peak memory 206896 kb
Host smart-c50eddc1-2e77-4db6-908e-e97a2bd21f44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34416
10536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.3441610536
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.4224935824
Short name T2568
Test name
Test status
Simulation time 190877367 ps
CPU time 0.94 seconds
Started Jul 25 07:02:05 PM PDT 24
Finished Jul 25 07:02:06 PM PDT 24
Peak memory 207124 kb
Host smart-b211eaee-1783-4972-989a-5ce57c0e5ac2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42249
35824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.4224935824
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.1493834233
Short name T2793
Test name
Test status
Simulation time 161520100 ps
CPU time 0.85 seconds
Started Jul 25 07:02:09 PM PDT 24
Finished Jul 25 07:02:10 PM PDT 24
Peak memory 207128 kb
Host smart-5d2fa19e-67bd-47f2-bfb7-81e9d16cf4bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14938
34233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.1493834233
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.157001468
Short name T575
Test name
Test status
Simulation time 161005664 ps
CPU time 0.82 seconds
Started Jul 25 07:02:07 PM PDT 24
Finished Jul 25 07:02:08 PM PDT 24
Peak memory 207228 kb
Host smart-d1c4480a-3294-4fa1-859e-aabd19907e0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15700
1468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.157001468
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.1638086240
Short name T310
Test name
Test status
Simulation time 163151417 ps
CPU time 0.89 seconds
Started Jul 25 07:02:09 PM PDT 24
Finished Jul 25 07:02:10 PM PDT 24
Peak memory 207144 kb
Host smart-da6ce3fb-8b49-4c6b-b227-727a5cd6daef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16380
86240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.1638086240
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.2225550914
Short name T2063
Test name
Test status
Simulation time 231998789 ps
CPU time 0.99 seconds
Started Jul 25 07:02:06 PM PDT 24
Finished Jul 25 07:02:07 PM PDT 24
Peak memory 207120 kb
Host smart-2aa80806-7733-45e2-b755-0db3204e4f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22255
50914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.2225550914
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.911230985
Short name T1433
Test name
Test status
Simulation time 4079830145 ps
CPU time 41.71 seconds
Started Jul 25 07:02:07 PM PDT 24
Finished Jul 25 07:02:49 PM PDT 24
Peak memory 207508 kb
Host smart-cc33c09d-12ad-4847-9450-a132e79361d6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=911230985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.911230985
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.1726507184
Short name T2206
Test name
Test status
Simulation time 175163751 ps
CPU time 0.88 seconds
Started Jul 25 07:02:15 PM PDT 24
Finished Jul 25 07:02:16 PM PDT 24
Peak memory 207124 kb
Host smart-a0c4c0de-9c78-4eae-9972-e597f84579b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17265
07184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.1726507184
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.74701651
Short name T642
Test name
Test status
Simulation time 205203222 ps
CPU time 0.89 seconds
Started Jul 25 07:02:07 PM PDT 24
Finished Jul 25 07:02:08 PM PDT 24
Peak memory 207256 kb
Host smart-49863b29-efbf-4061-9230-2e66312cdd94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74701
651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.74701651
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.867208863
Short name T2316
Test name
Test status
Simulation time 444504694 ps
CPU time 1.55 seconds
Started Jul 25 07:02:16 PM PDT 24
Finished Jul 25 07:02:17 PM PDT 24
Peak memory 207084 kb
Host smart-3647ebe9-bb8b-4ede-8eec-b6dda3266780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86720
8863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.867208863
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.1378809122
Short name T1104
Test name
Test status
Simulation time 7901343187 ps
CPU time 62.1 seconds
Started Jul 25 07:02:14 PM PDT 24
Finished Jul 25 07:03:17 PM PDT 24
Peak memory 207356 kb
Host smart-3ede099b-7703-4f7f-ae99-095bcbd019ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13788
09122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.1378809122
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_timeout_missing_host_handshake.180594073
Short name T20
Test name
Test status
Simulation time 8350632112 ps
CPU time 55.7 seconds
Started Jul 25 07:01:58 PM PDT 24
Finished Jul 25 07:02:54 PM PDT 24
Peak memory 207456 kb
Host smart-d7af59a4-2631-493b-894e-dc1bea47d3a2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180594073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_timeout_missing_host_
handshake.180594073
Directory /workspace/7.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.2108879733
Short name T1126
Test name
Test status
Simulation time 77167460 ps
CPU time 0.69 seconds
Started Jul 25 07:02:14 PM PDT 24
Finished Jul 25 07:02:15 PM PDT 24
Peak memory 207184 kb
Host smart-b913d11f-cadf-4011-a30c-3bb72b9a0450
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2108879733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.2108879733
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.4017490284
Short name T2690
Test name
Test status
Simulation time 4371524374 ps
CPU time 6.52 seconds
Started Jul 25 07:02:07 PM PDT 24
Finished Jul 25 07:02:14 PM PDT 24
Peak memory 207496 kb
Host smart-cac6ea39-9a7f-47bb-b385-6893c1e0a7fc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017490284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ao
n_wake_disconnect.4017490284
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.2724117369
Short name T1269
Test name
Test status
Simulation time 13344191109 ps
CPU time 17.72 seconds
Started Jul 25 07:02:04 PM PDT 24
Finished Jul 25 07:02:22 PM PDT 24
Peak memory 207432 kb
Host smart-0db5fbcf-dff2-4f36-873a-70757cf08578
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724117369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.2724117369
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.3330253206
Short name T481
Test name
Test status
Simulation time 23334335608 ps
CPU time 28.62 seconds
Started Jul 25 07:02:07 PM PDT 24
Finished Jul 25 07:02:36 PM PDT 24
Peak memory 207480 kb
Host smart-9d970a22-2122-4886-b362-57de17a86ecf
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330253206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ao
n_wake_resume.3330253206
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.574615209
Short name T469
Test name
Test status
Simulation time 223587649 ps
CPU time 0.91 seconds
Started Jul 25 07:02:03 PM PDT 24
Finished Jul 25 07:02:04 PM PDT 24
Peak memory 207192 kb
Host smart-17b3850b-ae29-4bd4-ae88-9c53ba5c0baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57461
5209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.574615209
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.696967491
Short name T1352
Test name
Test status
Simulation time 142211055 ps
CPU time 0.89 seconds
Started Jul 25 07:02:13 PM PDT 24
Finished Jul 25 07:02:14 PM PDT 24
Peak memory 207116 kb
Host smart-99ac1cb2-24b1-415a-91dd-c68486913c8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69696
7491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.696967491
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.3440255510
Short name T798
Test name
Test status
Simulation time 562220312 ps
CPU time 1.98 seconds
Started Jul 25 07:02:13 PM PDT 24
Finished Jul 25 07:02:16 PM PDT 24
Peak memory 207116 kb
Host smart-b0cef28d-fe5b-4d4f-95e2-960bd3df5db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34402
55510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.3440255510
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.2456538907
Short name T2520
Test name
Test status
Simulation time 1067080561 ps
CPU time 2.72 seconds
Started Jul 25 07:02:05 PM PDT 24
Finished Jul 25 07:02:08 PM PDT 24
Peak memory 207360 kb
Host smart-b6a37ead-cbf2-41ec-8120-2c3f773270b0
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2456538907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.2456538907
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.2330374147
Short name T309
Test name
Test status
Simulation time 18101695215 ps
CPU time 39.77 seconds
Started Jul 25 07:02:10 PM PDT 24
Finished Jul 25 07:02:49 PM PDT 24
Peak memory 207408 kb
Host smart-089bb82d-27f5-4013-9822-a22aa9feac60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23303
74147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.2330374147
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_device_timeout.695534827
Short name T2110
Test name
Test status
Simulation time 4373696722 ps
CPU time 29.1 seconds
Started Jul 25 07:02:06 PM PDT 24
Finished Jul 25 07:02:35 PM PDT 24
Peak memory 207468 kb
Host smart-a73409f7-65f6-469e-b5ad-96b7f8df0c47
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695534827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_timeout.695534827
Directory /workspace/8.usbdev_device_timeout/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.4013454966
Short name T1646
Test name
Test status
Simulation time 504875575 ps
CPU time 1.54 seconds
Started Jul 25 07:02:14 PM PDT 24
Finished Jul 25 07:02:16 PM PDT 24
Peak memory 207076 kb
Host smart-609c327c-4781-4787-a1cb-addde41caace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40134
54966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.4013454966
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.321761498
Short name T578
Test name
Test status
Simulation time 170160452 ps
CPU time 0.85 seconds
Started Jul 25 07:02:05 PM PDT 24
Finished Jul 25 07:02:06 PM PDT 24
Peak memory 207084 kb
Host smart-9148f6e9-30f8-4aac-bdd8-90f589316e8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32176
1498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.321761498
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.1553075755
Short name T1010
Test name
Test status
Simulation time 37558784 ps
CPU time 0.72 seconds
Started Jul 25 07:02:04 PM PDT 24
Finished Jul 25 07:02:05 PM PDT 24
Peak memory 207092 kb
Host smart-6edb64d5-8fe1-4c74-96d1-29ad15a034c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15530
75755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.1553075755
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.1895185532
Short name T1134
Test name
Test status
Simulation time 698743851 ps
CPU time 2.28 seconds
Started Jul 25 07:02:18 PM PDT 24
Finished Jul 25 07:02:21 PM PDT 24
Peak memory 207292 kb
Host smart-f2e4adbd-3d1e-47e9-b986-27ce54599770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18951
85532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.1895185532
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.3767853874
Short name T697
Test name
Test status
Simulation time 245289442 ps
CPU time 1.92 seconds
Started Jul 25 07:02:13 PM PDT 24
Finished Jul 25 07:02:15 PM PDT 24
Peak memory 207328 kb
Host smart-463d685c-a43d-4c90-875b-8930fbcede5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37678
53874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.3767853874
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.34829681
Short name T1723
Test name
Test status
Simulation time 207695154 ps
CPU time 1.04 seconds
Started Jul 25 07:02:14 PM PDT 24
Finished Jul 25 07:02:15 PM PDT 24
Peak memory 215500 kb
Host smart-9f023326-ecbf-4b4f-bffa-8bce517ae36f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=34829681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.34829681
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.1613031162
Short name T2538
Test name
Test status
Simulation time 172053257 ps
CPU time 0.87 seconds
Started Jul 25 07:02:16 PM PDT 24
Finished Jul 25 07:02:18 PM PDT 24
Peak memory 207112 kb
Host smart-48c91825-f2e7-4116-a892-99959c703ef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16130
31162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.1613031162
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.3087058252
Short name T2147
Test name
Test status
Simulation time 167313613 ps
CPU time 0.96 seconds
Started Jul 25 07:02:16 PM PDT 24
Finished Jul 25 07:02:17 PM PDT 24
Peak memory 207164 kb
Host smart-7dc4e37b-fa6f-4ad1-a585-c0ba06194b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30870
58252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.3087058252
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_invalid_sync.684015511
Short name T1975
Test name
Test status
Simulation time 8335495070 ps
CPU time 254.21 seconds
Started Jul 25 07:02:16 PM PDT 24
Finished Jul 25 07:06:31 PM PDT 24
Peak memory 215624 kb
Host smart-51be75c4-475c-42c2-aa91-1ac52a849708
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=684015511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.684015511
Directory /workspace/8.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/8.usbdev_iso_retraction.481623949
Short name T775
Test name
Test status
Simulation time 13131213153 ps
CPU time 87.28 seconds
Started Jul 25 07:02:19 PM PDT 24
Finished Jul 25 07:03:47 PM PDT 24
Peak memory 207332 kb
Host smart-adbde494-b9ac-41f9-93a4-b78d36f014ef
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=481623949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_iso_retraction.481623949
Directory /workspace/8.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.4003314391
Short name T2569
Test name
Test status
Simulation time 221153347 ps
CPU time 0.97 seconds
Started Jul 25 07:02:13 PM PDT 24
Finished Jul 25 07:02:14 PM PDT 24
Peak memory 207120 kb
Host smart-d6554609-2636-49f8-885f-2a7e060201f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40033
14391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.4003314391
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.2886852128
Short name T2042
Test name
Test status
Simulation time 23363502433 ps
CPU time 29.49 seconds
Started Jul 25 07:02:16 PM PDT 24
Finished Jul 25 07:02:45 PM PDT 24
Peak memory 207364 kb
Host smart-9ed0c53d-5f39-48be-8869-ab651cc9ed81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28868
52128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.2886852128
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.3227070295
Short name T2479
Test name
Test status
Simulation time 3293044652 ps
CPU time 5.49 seconds
Started Jul 25 07:02:15 PM PDT 24
Finished Jul 25 07:02:21 PM PDT 24
Peak memory 207372 kb
Host smart-cf09eab3-9dc9-4e1d-8e8e-b6e77898b83c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32270
70295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.3227070295
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.2866507576
Short name T1590
Test name
Test status
Simulation time 8513695355 ps
CPU time 84.41 seconds
Started Jul 25 07:02:13 PM PDT 24
Finished Jul 25 07:03:38 PM PDT 24
Peak memory 217504 kb
Host smart-3148383a-f8f7-4404-b8a9-6ccb496ff18c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28665
07576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.2866507576
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.790543193
Short name T1447
Test name
Test status
Simulation time 5321650075 ps
CPU time 162.8 seconds
Started Jul 25 07:02:12 PM PDT 24
Finished Jul 25 07:04:55 PM PDT 24
Peak memory 215556 kb
Host smart-aab0871e-1e16-4a74-92a4-dafaa9745e88
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=790543193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.790543193
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.2446603664
Short name T2181
Test name
Test status
Simulation time 270508804 ps
CPU time 1.06 seconds
Started Jul 25 07:02:13 PM PDT 24
Finished Jul 25 07:02:14 PM PDT 24
Peak memory 207164 kb
Host smart-49fa0be5-ee21-4dab-a00a-0495d63c1592
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2446603664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.2446603664
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.959408969
Short name T2785
Test name
Test status
Simulation time 187798744 ps
CPU time 0.94 seconds
Started Jul 25 07:02:15 PM PDT 24
Finished Jul 25 07:02:16 PM PDT 24
Peak memory 207072 kb
Host smart-f480e3fd-06ab-407f-9b30-16fe1e9c0770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95940
8969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.959408969
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.1205855166
Short name T1834
Test name
Test status
Simulation time 6130636227 ps
CPU time 176.07 seconds
Started Jul 25 07:02:13 PM PDT 24
Finished Jul 25 07:05:09 PM PDT 24
Peak memory 215604 kb
Host smart-71502633-ef99-489f-a9d0-5f6b2120ea69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12058
55166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.1205855166
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.3876480090
Short name T1961
Test name
Test status
Simulation time 7256306950 ps
CPU time 209.49 seconds
Started Jul 25 07:02:14 PM PDT 24
Finished Jul 25 07:05:43 PM PDT 24
Peak memory 215576 kb
Host smart-84fb36ba-e87d-4d68-ab5a-77d891621152
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3876480090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.3876480090
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.307751554
Short name T2156
Test name
Test status
Simulation time 208237475 ps
CPU time 0.95 seconds
Started Jul 25 07:02:15 PM PDT 24
Finished Jul 25 07:02:16 PM PDT 24
Peak memory 207084 kb
Host smart-8c8146cb-e01d-4d20-8e10-09aa2bea5927
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=307751554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.307751554
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.4219664279
Short name T947
Test name
Test status
Simulation time 151678717 ps
CPU time 0.84 seconds
Started Jul 25 07:02:16 PM PDT 24
Finished Jul 25 07:02:17 PM PDT 24
Peak memory 207156 kb
Host smart-dde98350-6320-4317-80ae-060fc58fce0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42196
64279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.4219664279
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.1316205294
Short name T2723
Test name
Test status
Simulation time 175514155 ps
CPU time 0.93 seconds
Started Jul 25 07:02:14 PM PDT 24
Finished Jul 25 07:02:15 PM PDT 24
Peak memory 207224 kb
Host smart-6b06b2f0-b7d5-4059-86ac-5181f85635e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13162
05294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.1316205294
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.4172283002
Short name T387
Test name
Test status
Simulation time 177762782 ps
CPU time 0.92 seconds
Started Jul 25 07:02:14 PM PDT 24
Finished Jul 25 07:02:15 PM PDT 24
Peak memory 207108 kb
Host smart-78d10a05-7b45-4709-9aac-92be144ca8ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41722
83002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.4172283002
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.3679701143
Short name T2761
Test name
Test status
Simulation time 150246515 ps
CPU time 0.92 seconds
Started Jul 25 07:02:15 PM PDT 24
Finished Jul 25 07:02:16 PM PDT 24
Peak memory 207160 kb
Host smart-b5fd6bef-0a16-48f5-ade1-7057d5c4ce79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36797
01143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.3679701143
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.521766019
Short name T881
Test name
Test status
Simulation time 169053759 ps
CPU time 0.89 seconds
Started Jul 25 07:02:16 PM PDT 24
Finished Jul 25 07:02:17 PM PDT 24
Peak memory 207116 kb
Host smart-69a34c14-0150-4867-aad4-37afe7913ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52176
6019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.521766019
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.4027887836
Short name T2767
Test name
Test status
Simulation time 200023043 ps
CPU time 1 seconds
Started Jul 25 07:02:14 PM PDT 24
Finished Jul 25 07:02:15 PM PDT 24
Peak memory 207124 kb
Host smart-7992a60c-729a-42e0-b403-965f28724db7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4027887836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.4027887836
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.765015205
Short name T46
Test name
Test status
Simulation time 145431191 ps
CPU time 0.8 seconds
Started Jul 25 07:02:15 PM PDT 24
Finished Jul 25 07:02:16 PM PDT 24
Peak memory 207088 kb
Host smart-c43f6e1f-e3c4-47a3-ac9e-704ac007ecc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76501
5205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.765015205
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.3093244840
Short name T1754
Test name
Test status
Simulation time 38997566 ps
CPU time 0.67 seconds
Started Jul 25 07:02:13 PM PDT 24
Finished Jul 25 07:02:14 PM PDT 24
Peak memory 207040 kb
Host smart-60f2b99a-08ac-4c20-b2f3-fb28411459d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30932
44840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.3093244840
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.1972544701
Short name T260
Test name
Test status
Simulation time 11424301652 ps
CPU time 29.54 seconds
Started Jul 25 07:02:17 PM PDT 24
Finished Jul 25 07:02:46 PM PDT 24
Peak memory 215588 kb
Host smart-0af618f2-47d1-47fe-a3db-da126cb4adef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19725
44701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.1972544701
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.3158208830
Short name T1302
Test name
Test status
Simulation time 179997293 ps
CPU time 0.88 seconds
Started Jul 25 07:04:49 PM PDT 24
Finished Jul 25 07:04:50 PM PDT 24
Peak memory 207120 kb
Host smart-f736e8ba-08c8-4db9-b02d-15c446b3d766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31582
08830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.3158208830
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.1652877067
Short name T574
Test name
Test status
Simulation time 222590553 ps
CPU time 0.97 seconds
Started Jul 25 07:02:16 PM PDT 24
Finished Jul 25 07:02:17 PM PDT 24
Peak memory 207096 kb
Host smart-29065253-d369-4ab3-8315-17da5e4405e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16528
77067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.1652877067
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.251884780
Short name T180
Test name
Test status
Simulation time 7034667633 ps
CPU time 179.74 seconds
Started Jul 25 07:02:12 PM PDT 24
Finished Jul 25 07:05:12 PM PDT 24
Peak memory 215604 kb
Host smart-325d799d-e3ea-441c-8195-e7696b714a36
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=251884780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.251884780
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.3846773037
Short name T1411
Test name
Test status
Simulation time 10584468956 ps
CPU time 59.42 seconds
Started Jul 25 07:02:13 PM PDT 24
Finished Jul 25 07:03:13 PM PDT 24
Peak memory 217808 kb
Host smart-a372e31e-9f94-477b-b9cb-27ab28f61119
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846773037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.3846773037
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.1031442490
Short name T2089
Test name
Test status
Simulation time 182910071 ps
CPU time 0.94 seconds
Started Jul 25 07:02:16 PM PDT 24
Finished Jul 25 07:02:17 PM PDT 24
Peak memory 207124 kb
Host smart-de40c1b5-8192-4a52-a4b1-83b7b1dbabee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10314
42490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.1031442490
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.2174252530
Short name T2033
Test name
Test status
Simulation time 234659685 ps
CPU time 0.97 seconds
Started Jul 25 07:02:14 PM PDT 24
Finished Jul 25 07:02:15 PM PDT 24
Peak memory 207108 kb
Host smart-8aa92444-25f5-45a7-a96b-97bff69b94a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21742
52530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.2174252530
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.432580880
Short name T941
Test name
Test status
Simulation time 184964940 ps
CPU time 0.87 seconds
Started Jul 25 07:02:16 PM PDT 24
Finished Jul 25 07:02:17 PM PDT 24
Peak memory 207120 kb
Host smart-ae769cbe-ca80-4ce9-8851-60074c709bb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43258
0880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.432580880
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.3768721364
Short name T1239
Test name
Test status
Simulation time 167341122 ps
CPU time 0.86 seconds
Started Jul 25 07:02:17 PM PDT 24
Finished Jul 25 07:02:18 PM PDT 24
Peak memory 207096 kb
Host smart-178c080b-c7c2-494c-a00c-f22079d1021b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37687
21364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.3768721364
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.3966639440
Short name T389
Test name
Test status
Simulation time 155461624 ps
CPU time 0.85 seconds
Started Jul 25 07:02:16 PM PDT 24
Finished Jul 25 07:02:17 PM PDT 24
Peak memory 207144 kb
Host smart-ffc4d18d-ef63-42c1-a32d-019f74a87816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39666
39440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.3966639440
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.2130923019
Short name T468
Test name
Test status
Simulation time 226905097 ps
CPU time 1.02 seconds
Started Jul 25 07:02:18 PM PDT 24
Finished Jul 25 07:02:19 PM PDT 24
Peak memory 207116 kb
Host smart-f7fbd151-936d-43e6-9ba7-56b43bdbafaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21309
23019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.2130923019
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.978963985
Short name T2221
Test name
Test status
Simulation time 3724408107 ps
CPU time 39.58 seconds
Started Jul 25 07:02:19 PM PDT 24
Finished Jul 25 07:02:59 PM PDT 24
Peak memory 216960 kb
Host smart-28f3bb0d-412e-4439-8752-cc59376de7ef
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=978963985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.978963985
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.4270773594
Short name T2821
Test name
Test status
Simulation time 182327861 ps
CPU time 0.87 seconds
Started Jul 25 07:02:15 PM PDT 24
Finished Jul 25 07:02:16 PM PDT 24
Peak memory 207164 kb
Host smart-57d22e1e-7f38-452c-b8e0-0399eafceea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42707
73594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.4270773594
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.826355829
Short name T1944
Test name
Test status
Simulation time 156453609 ps
CPU time 0.86 seconds
Started Jul 25 07:02:19 PM PDT 24
Finished Jul 25 07:02:20 PM PDT 24
Peak memory 207128 kb
Host smart-65960fb5-92bf-43d7-b8d3-bca5af03da8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82635
5829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.826355829
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.1197625663
Short name T2196
Test name
Test status
Simulation time 504965592 ps
CPU time 1.55 seconds
Started Jul 25 07:02:14 PM PDT 24
Finished Jul 25 07:02:16 PM PDT 24
Peak memory 207108 kb
Host smart-d5ee402c-0f1a-49b8-b568-e55bbfc26e6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11976
25663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.1197625663
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.1784071929
Short name T631
Test name
Test status
Simulation time 3657997717 ps
CPU time 35.73 seconds
Started Jul 25 07:02:14 PM PDT 24
Finished Jul 25 07:02:50 PM PDT 24
Peak memory 217016 kb
Host smart-f2b340cc-e688-477a-9120-0b5d26708be6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17840
71929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.1784071929
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_timeout_missing_host_handshake.3954547272
Short name T1671
Test name
Test status
Simulation time 1025257450 ps
CPU time 22.48 seconds
Started Jul 25 07:02:15 PM PDT 24
Finished Jul 25 07:02:37 PM PDT 24
Peak memory 207300 kb
Host smart-e74d651d-f4ac-4f9a-834c-455fe5ba195f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954547272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_timeout_missing_host
_handshake.3954547272
Directory /workspace/8.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.600802645
Short name T482
Test name
Test status
Simulation time 45551087 ps
CPU time 0.66 seconds
Started Jul 25 07:02:34 PM PDT 24
Finished Jul 25 07:02:34 PM PDT 24
Peak memory 207160 kb
Host smart-29a23134-9fe0-4845-80ec-88c7001fbf5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=600802645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.600802645
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.1568304494
Short name T966
Test name
Test status
Simulation time 3642145207 ps
CPU time 5.78 seconds
Started Jul 25 07:02:14 PM PDT 24
Finished Jul 25 07:02:20 PM PDT 24
Peak memory 207328 kb
Host smart-a5a31fc6-9c80-4779-bec1-b91a69cf8885
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568304494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_ao
n_wake_disconnect.1568304494
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.3720410780
Short name T2706
Test name
Test status
Simulation time 13370855271 ps
CPU time 15.62 seconds
Started Jul 25 07:02:15 PM PDT 24
Finished Jul 25 07:02:31 PM PDT 24
Peak memory 207396 kb
Host smart-df81c873-e3fe-43ea-8366-aa81e44fd6ae
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720410780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.3720410780
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.1917902708
Short name T2463
Test name
Test status
Simulation time 23315494670 ps
CPU time 28.83 seconds
Started Jul 25 07:02:16 PM PDT 24
Finished Jul 25 07:02:45 PM PDT 24
Peak memory 207348 kb
Host smart-35583720-c5c3-4beb-b1c3-e1abc7b143bc
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917902708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_ao
n_wake_resume.1917902708
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.2540227381
Short name T1537
Test name
Test status
Simulation time 183129168 ps
CPU time 0.88 seconds
Started Jul 25 07:02:28 PM PDT 24
Finished Jul 25 07:02:29 PM PDT 24
Peak memory 207112 kb
Host smart-0a270cce-c981-41ba-ab0d-4e5487fe1225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25402
27381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.2540227381
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.3458727073
Short name T1355
Test name
Test status
Simulation time 150692536 ps
CPU time 0.84 seconds
Started Jul 25 07:02:24 PM PDT 24
Finished Jul 25 07:02:25 PM PDT 24
Peak memory 207116 kb
Host smart-e509797a-eb42-44d1-a421-29079d8076ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34587
27073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.3458727073
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.2157283166
Short name T2866
Test name
Test status
Simulation time 511284682 ps
CPU time 1.54 seconds
Started Jul 25 07:02:24 PM PDT 24
Finished Jul 25 07:02:25 PM PDT 24
Peak memory 207156 kb
Host smart-3bb62df5-d142-466d-ad23-1bab508b03dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21572
83166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.2157283166
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.1645320016
Short name T2185
Test name
Test status
Simulation time 1287897326 ps
CPU time 3.15 seconds
Started Jul 25 07:02:23 PM PDT 24
Finished Jul 25 07:02:26 PM PDT 24
Peak memory 207268 kb
Host smart-00285a4e-547f-4648-a260-2b4b5ed1d9da
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1645320016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.1645320016
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.503897344
Short name T2141
Test name
Test status
Simulation time 10508748481 ps
CPU time 25.09 seconds
Started Jul 25 07:02:26 PM PDT 24
Finished Jul 25 07:02:52 PM PDT 24
Peak memory 207292 kb
Host smart-aeb84cbf-6a3d-44a6-a7fa-bd07c4bd2916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50389
7344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.503897344
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_device_timeout.1397873935
Short name T491
Test name
Test status
Simulation time 2895372521 ps
CPU time 19.75 seconds
Started Jul 25 07:02:24 PM PDT 24
Finished Jul 25 07:02:43 PM PDT 24
Peak memory 207360 kb
Host smart-f6c00370-4019-489d-a82c-3faba961540d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397873935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_timeout.1397873935
Directory /workspace/9.usbdev_device_timeout/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.1813948391
Short name T1927
Test name
Test status
Simulation time 444730014 ps
CPU time 1.34 seconds
Started Jul 25 07:02:25 PM PDT 24
Finished Jul 25 07:02:26 PM PDT 24
Peak memory 207120 kb
Host smart-5f1b2011-0781-4afd-a7ca-d0200b54a845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18139
48391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.1813948391
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.4238717982
Short name T971
Test name
Test status
Simulation time 154667818 ps
CPU time 0.86 seconds
Started Jul 25 07:02:24 PM PDT 24
Finished Jul 25 07:02:25 PM PDT 24
Peak memory 207060 kb
Host smart-c632baaa-776f-4346-995a-9877262bb23e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42387
17982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.4238717982
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.502201979
Short name T410
Test name
Test status
Simulation time 48191322 ps
CPU time 0.7 seconds
Started Jul 25 07:02:26 PM PDT 24
Finished Jul 25 07:02:27 PM PDT 24
Peak memory 207076 kb
Host smart-0cf03438-0678-4b20-af5f-e0412158279b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50220
1979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.502201979
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.132724289
Short name T2216
Test name
Test status
Simulation time 928939848 ps
CPU time 2.3 seconds
Started Jul 25 07:02:23 PM PDT 24
Finished Jul 25 07:02:25 PM PDT 24
Peak memory 207504 kb
Host smart-686bfe52-3250-4503-abf2-f575a079e786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13272
4289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.132724289
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.4058586055
Short name T641
Test name
Test status
Simulation time 251433739 ps
CPU time 2 seconds
Started Jul 25 07:02:27 PM PDT 24
Finished Jul 25 07:02:29 PM PDT 24
Peak memory 207308 kb
Host smart-1deb7ad5-8e42-4960-81b4-41c3cf72d1a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40585
86055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.4058586055
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.1104671448
Short name T2755
Test name
Test status
Simulation time 226271363 ps
CPU time 1.1 seconds
Started Jul 25 07:02:29 PM PDT 24
Finished Jul 25 07:02:30 PM PDT 24
Peak memory 215536 kb
Host smart-7c986ad5-52ab-4be1-9094-435a0dc9dc95
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1104671448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.1104671448
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.2974282047
Short name T1261
Test name
Test status
Simulation time 138616079 ps
CPU time 0.8 seconds
Started Jul 25 07:02:25 PM PDT 24
Finished Jul 25 07:02:26 PM PDT 24
Peak memory 207116 kb
Host smart-5d907cf7-6c34-4e81-90f6-1c870e29b89d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29742
82047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.2974282047
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.1280763601
Short name T2179
Test name
Test status
Simulation time 215583436 ps
CPU time 1 seconds
Started Jul 25 07:02:25 PM PDT 24
Finished Jul 25 07:02:26 PM PDT 24
Peak memory 207112 kb
Host smart-200c9d80-6914-4dc4-869a-1872fc515e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12807
63601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.1280763601
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_invalid_sync.3320921042
Short name T1101
Test name
Test status
Simulation time 5142088851 ps
CPU time 145.7 seconds
Started Jul 25 07:02:27 PM PDT 24
Finished Jul 25 07:04:53 PM PDT 24
Peak memory 215592 kb
Host smart-81dab85c-1088-433e-b1a9-3047fb9efea2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3320921042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.3320921042
Directory /workspace/9.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/9.usbdev_iso_retraction.3052838399
Short name T2435
Test name
Test status
Simulation time 15020882223 ps
CPU time 92.93 seconds
Started Jul 25 07:02:26 PM PDT 24
Finished Jul 25 07:03:59 PM PDT 24
Peak memory 207376 kb
Host smart-7b6720e1-47ad-40a8-bd62-2f0574bb2205
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3052838399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.3052838399
Directory /workspace/9.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.4222205655
Short name T70
Test name
Test status
Simulation time 227230636 ps
CPU time 1.02 seconds
Started Jul 25 07:02:28 PM PDT 24
Finished Jul 25 07:02:29 PM PDT 24
Peak memory 207120 kb
Host smart-1dd5e4f6-020e-477e-9f0d-6ca51e7db32c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42222
05655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.4222205655
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.839114923
Short name T1862
Test name
Test status
Simulation time 23309408005 ps
CPU time 35.46 seconds
Started Jul 25 07:02:26 PM PDT 24
Finished Jul 25 07:03:02 PM PDT 24
Peak memory 207372 kb
Host smart-f46a02f0-2717-47ae-addb-39dea89f6055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83911
4923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.839114923
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.2363636883
Short name T2407
Test name
Test status
Simulation time 3353751240 ps
CPU time 5.1 seconds
Started Jul 25 07:02:25 PM PDT 24
Finished Jul 25 07:02:30 PM PDT 24
Peak memory 207348 kb
Host smart-b950613c-9398-412c-973c-362ec759427d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23636
36883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.2363636883
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.2473011733
Short name T2646
Test name
Test status
Simulation time 7650131817 ps
CPU time 81.6 seconds
Started Jul 25 07:02:24 PM PDT 24
Finished Jul 25 07:03:46 PM PDT 24
Peak memory 217208 kb
Host smart-4cf5237c-3563-49b0-b69f-201fa9926944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24730
11733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.2473011733
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.899910512
Short name T1194
Test name
Test status
Simulation time 4379139060 ps
CPU time 43.06 seconds
Started Jul 25 07:02:26 PM PDT 24
Finished Jul 25 07:03:09 PM PDT 24
Peak memory 217080 kb
Host smart-bb88fa9e-9993-4817-9a06-48a843e016ee
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=899910512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.899910512
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.2230096869
Short name T1578
Test name
Test status
Simulation time 236445908 ps
CPU time 0.95 seconds
Started Jul 25 07:02:26 PM PDT 24
Finished Jul 25 07:02:27 PM PDT 24
Peak memory 207140 kb
Host smart-b7378bc6-aab2-426a-8d03-e9c7881b64fe
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2230096869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.2230096869
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.1345532609
Short name T840
Test name
Test status
Simulation time 250416341 ps
CPU time 1.02 seconds
Started Jul 25 07:02:28 PM PDT 24
Finished Jul 25 07:02:30 PM PDT 24
Peak memory 207124 kb
Host smart-9778f0a4-afd7-47f1-8c84-aade2976b4e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13455
32609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.1345532609
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.532707288
Short name T664
Test name
Test status
Simulation time 5294678169 ps
CPU time 42.15 seconds
Started Jul 25 07:02:24 PM PDT 24
Finished Jul 25 07:03:06 PM PDT 24
Peak memory 217136 kb
Host smart-45766861-5ded-4e8b-bb76-96c1e215e33f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53270
7288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.532707288
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.1408769413
Short name T2474
Test name
Test status
Simulation time 4444263552 ps
CPU time 36.8 seconds
Started Jul 25 07:02:26 PM PDT 24
Finished Jul 25 07:03:03 PM PDT 24
Peak memory 207408 kb
Host smart-5996ff19-638b-4cbc-834c-21dc6b10b2bf
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1408769413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.1408769413
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.1985268204
Short name T1080
Test name
Test status
Simulation time 163499677 ps
CPU time 0.87 seconds
Started Jul 25 07:02:24 PM PDT 24
Finished Jul 25 07:02:25 PM PDT 24
Peak memory 207148 kb
Host smart-851e280e-6664-4b60-8ff1-79883ec96963
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1985268204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.1985268204
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.4150379270
Short name T2662
Test name
Test status
Simulation time 144123086 ps
CPU time 0.82 seconds
Started Jul 25 07:02:20 PM PDT 24
Finished Jul 25 07:02:21 PM PDT 24
Peak memory 207124 kb
Host smart-a60c2635-6c6b-4309-95f2-06614544c585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41503
79270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.4150379270
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.888499279
Short name T2201
Test name
Test status
Simulation time 221283039 ps
CPU time 0.98 seconds
Started Jul 25 07:02:25 PM PDT 24
Finished Jul 25 07:02:26 PM PDT 24
Peak memory 207128 kb
Host smart-19760213-6ec1-4f09-8351-b15c04bd71b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88849
9279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.888499279
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.2529463104
Short name T2707
Test name
Test status
Simulation time 145422707 ps
CPU time 0.85 seconds
Started Jul 25 07:02:25 PM PDT 24
Finished Jul 25 07:02:26 PM PDT 24
Peak memory 207116 kb
Host smart-d28ae20e-d3e5-448b-8c38-81b7f9ef3d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25294
63104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.2529463104
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.2335275847
Short name T2586
Test name
Test status
Simulation time 248086722 ps
CPU time 0.96 seconds
Started Jul 25 07:02:22 PM PDT 24
Finished Jul 25 07:02:23 PM PDT 24
Peak memory 207112 kb
Host smart-8a937952-fa8b-496d-a85c-bffe6f680111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23352
75847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.2335275847
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.3058078137
Short name T2700
Test name
Test status
Simulation time 179143327 ps
CPU time 0.84 seconds
Started Jul 25 07:02:27 PM PDT 24
Finished Jul 25 07:02:28 PM PDT 24
Peak memory 207152 kb
Host smart-5d654d0c-9ef0-4fb8-8364-43a000caea4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30580
78137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.3058078137
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.1900977626
Short name T2277
Test name
Test status
Simulation time 149250382 ps
CPU time 0.87 seconds
Started Jul 25 07:02:24 PM PDT 24
Finished Jul 25 07:02:25 PM PDT 24
Peak memory 207104 kb
Host smart-5ca7b5f7-a17b-4132-8735-74fa859d1eee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19009
77626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.1900977626
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.2638942106
Short name T1299
Test name
Test status
Simulation time 244731466 ps
CPU time 1.03 seconds
Started Jul 25 07:02:25 PM PDT 24
Finished Jul 25 07:02:27 PM PDT 24
Peak memory 207092 kb
Host smart-6fecdd79-151c-4c50-b207-42b0e095f423
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2638942106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.2638942106
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.4218733502
Short name T590
Test name
Test status
Simulation time 150580188 ps
CPU time 0.84 seconds
Started Jul 25 07:02:24 PM PDT 24
Finished Jul 25 07:02:25 PM PDT 24
Peak memory 207156 kb
Host smart-81d16cf2-8ff7-470d-902d-1231f658c398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42187
33502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.4218733502
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.1755165691
Short name T40
Test name
Test status
Simulation time 60879337 ps
CPU time 0.71 seconds
Started Jul 25 07:02:24 PM PDT 24
Finished Jul 25 07:02:25 PM PDT 24
Peak memory 207100 kb
Host smart-f86568c6-1690-40a4-ae50-778ecda7a0d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17551
65691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.1755165691
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.1278788390
Short name T267
Test name
Test status
Simulation time 9233826351 ps
CPU time 23.74 seconds
Started Jul 25 07:02:38 PM PDT 24
Finished Jul 25 07:03:02 PM PDT 24
Peak memory 215560 kb
Host smart-d73d818a-32da-4c14-82aa-260af0415439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12787
88390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.1278788390
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.3425409171
Short name T564
Test name
Test status
Simulation time 155809085 ps
CPU time 0.8 seconds
Started Jul 25 07:02:35 PM PDT 24
Finished Jul 25 07:02:36 PM PDT 24
Peak memory 207068 kb
Host smart-97933edf-6200-454d-b354-068c98b72793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34254
09171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.3425409171
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.2953747164
Short name T2380
Test name
Test status
Simulation time 237778196 ps
CPU time 0.98 seconds
Started Jul 25 07:02:35 PM PDT 24
Finished Jul 25 07:02:36 PM PDT 24
Peak memory 207096 kb
Host smart-867e6424-8098-4efa-a787-16b59ccf6449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29537
47164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.2953747164
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.4043116907
Short name T170
Test name
Test status
Simulation time 17336239073 ps
CPU time 107.43 seconds
Started Jul 25 07:02:35 PM PDT 24
Finished Jul 25 07:04:23 PM PDT 24
Peak memory 217624 kb
Host smart-48ba5340-623b-4f0d-a415-1808dc0abf28
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043116907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.4043116907
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.3668825990
Short name T2637
Test name
Test status
Simulation time 11859227963 ps
CPU time 325.35 seconds
Started Jul 25 07:02:35 PM PDT 24
Finished Jul 25 07:08:01 PM PDT 24
Peak memory 215656 kb
Host smart-71718069-9d0a-432b-92eb-416a605c6c31
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3668825990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.3668825990
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.1128943244
Short name T1556
Test name
Test status
Simulation time 24496498323 ps
CPU time 157.3 seconds
Started Jul 25 07:02:35 PM PDT 24
Finished Jul 25 07:05:12 PM PDT 24
Peak memory 223760 kb
Host smart-eee08c83-416e-45a7-8aaa-30a9537b27d3
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128943244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.1128943244
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.1583084664
Short name T2405
Test name
Test status
Simulation time 269569905 ps
CPU time 1.02 seconds
Started Jul 25 07:02:35 PM PDT 24
Finished Jul 25 07:02:36 PM PDT 24
Peak memory 207076 kb
Host smart-460c84ee-4ce3-47c4-a991-8c3fe1395cc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15830
84664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.1583084664
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.3894952443
Short name T107
Test name
Test status
Simulation time 161406001 ps
CPU time 0.85 seconds
Started Jul 25 07:02:35 PM PDT 24
Finished Jul 25 07:02:36 PM PDT 24
Peak memory 207116 kb
Host smart-76d23e55-4125-41ab-9af9-6dea123eee0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38949
52443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.3894952443
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.3994324401
Short name T57
Test name
Test status
Simulation time 157137947 ps
CPU time 0.83 seconds
Started Jul 25 07:02:36 PM PDT 24
Finished Jul 25 07:02:37 PM PDT 24
Peak memory 207136 kb
Host smart-04461723-ca25-42bd-8e3d-7fa3021d75ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39943
24401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.3994324401
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.2403917920
Short name T444
Test name
Test status
Simulation time 161162091 ps
CPU time 0.84 seconds
Started Jul 25 07:02:37 PM PDT 24
Finished Jul 25 07:02:38 PM PDT 24
Peak memory 207156 kb
Host smart-ed4db455-3933-44e6-a9ea-40bbfd22da78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24039
17920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.2403917920
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.834064184
Short name T2712
Test name
Test status
Simulation time 177639651 ps
CPU time 0.89 seconds
Started Jul 25 07:02:33 PM PDT 24
Finished Jul 25 07:02:34 PM PDT 24
Peak memory 207136 kb
Host smart-47b2f0b3-e483-4940-93da-213b0ddb5121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83406
4184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.834064184
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.2815380711
Short name T2622
Test name
Test status
Simulation time 227308925 ps
CPU time 1.01 seconds
Started Jul 25 07:02:34 PM PDT 24
Finished Jul 25 07:02:35 PM PDT 24
Peak memory 207120 kb
Host smart-d10c7270-6b63-4b24-88e3-de0da9ac86d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28153
80711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.2815380711
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.2000185230
Short name T2054
Test name
Test status
Simulation time 3852638063 ps
CPU time 115.52 seconds
Started Jul 25 07:02:37 PM PDT 24
Finished Jul 25 07:04:33 PM PDT 24
Peak memory 215568 kb
Host smart-07be7f4b-fcdc-497d-a7c5-831feea6cea3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2000185230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.2000185230
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.3828795594
Short name T657
Test name
Test status
Simulation time 150229895 ps
CPU time 0.87 seconds
Started Jul 25 07:02:36 PM PDT 24
Finished Jul 25 07:02:37 PM PDT 24
Peak memory 207148 kb
Host smart-707b0ff2-7ac5-4ebf-bfc6-d15202d59f5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38287
95594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.3828795594
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.3394184024
Short name T829
Test name
Test status
Simulation time 156230528 ps
CPU time 0.85 seconds
Started Jul 25 07:02:35 PM PDT 24
Finished Jul 25 07:02:36 PM PDT 24
Peak memory 207116 kb
Host smart-97b454e9-9627-4e05-8514-b7d860ef5529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33941
84024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.3394184024
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.1193296769
Short name T1658
Test name
Test status
Simulation time 1288118229 ps
CPU time 2.74 seconds
Started Jul 25 07:02:35 PM PDT 24
Finished Jul 25 07:02:38 PM PDT 24
Peak memory 207352 kb
Host smart-050358f7-2a87-4c68-9876-53cb333a6504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11932
96769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.1193296769
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.743114583
Short name T2693
Test name
Test status
Simulation time 4637702153 ps
CPU time 132.78 seconds
Started Jul 25 07:02:36 PM PDT 24
Finished Jul 25 07:04:49 PM PDT 24
Peak memory 223496 kb
Host smart-e5442141-2347-46f2-aae5-169837fe9c7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74311
4583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.743114583
Directory /workspace/9.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_timeout_missing_host_handshake.2489818230
Short name T455
Test name
Test status
Simulation time 164338258 ps
CPU time 0.9 seconds
Started Jul 25 07:02:26 PM PDT 24
Finished Jul 25 07:02:27 PM PDT 24
Peak memory 207104 kb
Host smart-0de06baf-827f-454c-9bb2-5ee09efbba96
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489818230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_timeout_missing_host
_handshake.2489818230
Directory /workspace/9.usbdev_timeout_missing_host_handshake/latest
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