Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	89506	1		T1	2		T3	2		T27	3
all_values[1]	89506	1		T1	2		T3	2		T27	3
all_values[2]	89506	1		T1	2		T3	2		T27	3
all_values[3]	89506	1		T1	2		T3	2		T27	3
all_values[4]	89506	1		T1	2		T3	2		T27	3
all_values[5]	89506	1		T1	2		T3	2		T27	3
all_values[6]	89506	1		T1	2		T3	2		T27	3
all_values[7]	89506	1		T1	2		T3	2		T27	3
all_values[8]	89506	1		T1	2		T3	2		T27	3
all_values[9]	89506	1		T1	2		T3	2		T27	3
all_values[10]	89506	1		T1	2		T3	2		T27	3
all_values[11]	89506	1		T1	2		T3	2		T27	3
all_values[12]	89506	1		T1	2		T3	2		T27	3
all_values[13]	89506	1		T1	2		T3	2		T27	3
all_values[14]	89506	1		T1	2		T3	2		T27	3
all_values[15]	89506	1		T1	2		T3	2		T27	3
all_values[16]	89506	1		T1	2		T3	2		T27	3
all_values[17]	89506	1		T1	2		T3	2		T27	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2857173	1		T1	64		T3	64		T27	96
auto[1]	7019	1		T30	3		T42	2		T6	2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2388215	1		T1	55		T3	61		T27	78
auto[1]	475977	1		T1	9		T3	3		T27	18

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	63337	1		T1	2		T3	2		T28	1062
all_values[0]	auto[0]	auto[1]	25319	1		T27	3		T28	1060		T29	3
all_values[0]	auto[1]	auto[0]	739	1		T21	3		T50	3		T51	3
all_values[0]	auto[1]	auto[1]	111	1		T51	1		T289	1		T290	1
all_values[1]	auto[0]	auto[0]	86207	1		T3	2		T28	2122		T29	2
all_values[1]	auto[0]	auto[1]	1625	1		T1	2		T27	3		T29	1
all_values[1]	auto[1]	auto[0]	661	1		T30	2		T6	1		T7	1
all_values[1]	auto[1]	auto[1]	1013	1		T30	1		T6	1		T7	1
all_values[2]	auto[0]	auto[0]	2980	1		T1	1		T3	1		T27	1
all_values[2]	auto[0]	auto[1]	86266	1		T1	1		T3	1		T27	2
all_values[2]	auto[1]	auto[0]	135	1		T42	1		T43	1		T44	1
all_values[2]	auto[1]	auto[1]	125	1		T42	1		T43	1		T44	1
all_values[3]	auto[0]	auto[0]	87356	1		T1	1		T3	2		T27	3
all_values[3]	auto[0]	auto[1]	560	1		T1	1		T4	1		T5	1
all_values[3]	auto[1]	auto[0]	1523	1		T67	1429		T197	3		T199	5
all_values[3]	auto[1]	auto[1]	67	1		T67	1		T197	2		T198	3
all_values[4]	auto[0]	auto[0]	2922	1		T1	1		T3	1		T27	1
all_values[4]	auto[0]	auto[1]	86405	1		T1	1		T3	1		T27	2
all_values[4]	auto[1]	auto[0]	103	1		T68	1		T197	3		T199	2
all_values[4]	auto[1]	auto[1]	76	1		T68	1		T197	3		T199	1
all_values[5]	auto[0]	auto[0]	88994	1		T1	1		T3	2		T27	3
all_values[5]	auto[0]	auto[1]	348	1		T1	1		T40	1		T6	1
all_values[5]	auto[1]	auto[0]	93	1		T197	1		T199	4		T198	2
all_values[5]	auto[1]	auto[1]	71	1		T197	1		T199	1		T200	3
all_values[6]	auto[0]	auto[0]	89054	1		T1	1		T3	2		T27	3
all_values[6]	auto[0]	auto[1]	280	1		T1	1		T40	1		T6	1
all_values[6]	auto[1]	auto[0]	95	1		T197	1		T199	3		T198	2
all_values[6]	auto[1]	auto[1]	77	1		T199	3		T198	2		T282	1
all_values[7]	auto[0]	auto[0]	34635	1		T1	2		T3	2		T28	2
all_values[7]	auto[0]	auto[1]	54680	1		T27	3		T28	2120		T29	3
all_values[7]	auto[1]	auto[0]	127	1		T53	1		T197	3		T199	2
all_values[7]	auto[1]	auto[1]	64	1		T53	1		T197	1		T199	1
all_values[8]	auto[0]	auto[0]	89273	1		T1	2		T3	2		T27	3
all_values[8]	auto[0]	auto[1]	53	1		T197	1		T199	2		T198	2
all_values[8]	auto[1]	auto[0]	124	1		T55	10		T197	3		T199	1
all_values[8]	auto[1]	auto[1]	56	1		T55	1		T197	3		T198	2
all_values[9]	auto[0]	auto[0]	89248	1		T1	2		T3	2		T27	3
all_values[9]	auto[0]	auto[1]	56	1		T197	2		T198	3		T282	2
all_values[9]	auto[1]	auto[0]	122	1		T64	3		T65	3		T66	3
all_values[9]	auto[1]	auto[1]	80	1		T64	2		T65	2		T66	2
all_values[10]	auto[0]	auto[0]	89021	1		T1	2		T3	2		T27	3
all_values[10]	auto[0]	auto[1]	306	1		T61	1		T62	2		T63	1
all_values[10]	auto[1]	auto[0]	102	1		T197	3		T200	4		T265	3
all_values[10]	auto[1]	auto[1]	77	1		T197	5		T198	1		T282	1
all_values[11]	auto[0]	auto[0]	89117	1		T1	2		T3	2		T27	3
all_values[11]	auto[0]	auto[1]	144	1		T40	1		T72	1		T73	1
all_values[11]	auto[1]	auto[0]	127	1		T49	1		T74	1		T75	1
all_values[11]	auto[1]	auto[1]	118	1		T49	1		T74	1		T75	1
all_values[12]	auto[0]	auto[0]	89255	1		T1	2		T3	2		T27	3
all_values[12]	auto[0]	auto[1]	69	1		T40	1		T76	1		T80	1
all_values[12]	auto[1]	auto[0]	109	1		T77	2		T78	2		T79	2
all_values[12]	auto[1]	auto[1]	73	1		T77	1		T78	1		T79	1
all_values[13]	auto[0]	auto[0]	89163	1		T1	2		T3	2		T27	3
all_values[13]	auto[0]	auto[1]	73	1		T40	1		T76	1		T80	1
all_values[13]	auto[1]	auto[0]	148	1		T72	1		T73	1		T81	1
all_values[13]	auto[1]	auto[1]	122	1		T72	1		T73	1		T81	1
all_values[14]	auto[0]	auto[0]	14554	1		T1	1		T3	2		T27	3
all_values[14]	auto[0]	auto[1]	74791	1		T1	1		T28	2121		T4	1
all_values[14]	auto[1]	auto[0]	89	1		T197	2		T199	3		T198	1
all_values[14]	auto[1]	auto[1]	72	1		T198	1		T265	3		T283	1
all_values[15]	auto[0]	auto[0]	2988	1		T1	1		T3	1		T27	1
all_values[15]	auto[0]	auto[1]	86352	1		T1	1		T3	1		T27	2
all_values[15]	auto[1]	auto[0]	105	1		T197	1		T198	1		T282	1
all_values[15]	auto[1]	auto[1]	61	1		T197	2		T198	4		T265	1
all_values[16]	auto[0]	auto[0]	88883	1		T1	2		T3	2		T27	3
all_values[16]	auto[0]	auto[1]	431	1		T31	1		T40	1		T16	1
all_values[16]	auto[1]	auto[0]	120	1		T69	4		T70	4		T71	4
all_values[16]	auto[1]	auto[1]	72	1		T69	4		T70	4		T71	4
all_values[17]	auto[0]	auto[0]	33509	1		T1	2		T3	2		T4	2
all_values[17]	auto[0]	auto[1]	55835	1		T27	3		T28	2122		T29	3
all_values[17]	auto[1]	auto[0]	113	1		T58	1		T59	1		T60	1
all_values[17]	auto[1]	auto[1]	49	1		T58	1		T59	1		T60	1