Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::address_cg

Group : usbdev_env_pkg::usbdev_env_cov::address_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	14	0	14	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::address_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_address	7	0	7	100.00	100	1	1	0
cp_endp	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_address_X_endp	14	0	14	100.00	100	1	1	0

Summary for Variable cp_address

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_address

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	1711	1		T16	2		T87	5		T110	2
range_16_to_126	189434	1		T1	150		T3	17		T27	2
fifteen	1060	1		T16	6		T87	3		T88	6
range_2_to_14	22988	1		T3	1		T4	355		T146	2
seven	1167	1		T16	3		T87	7		T88	9
one	840	1		T16	4		T87	4		T88	8
zero	715	1		T16	1		T155	1		T87	7

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Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
seven	17386	1		T1	25		T5	33		T40	2
three	13773	1		T1	25		T95	1		T40	23

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Summary for Cross cr_address_X_endp

Samples crossed: cp_address cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	0	14	100.00

Automatically Generated Cross Bins for cr_address_X_endp

Bins

cp_address	cp_endp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	seven	91	1		T87	1		T148	1		T162	2
range_127	three	83	1		T16	1		T88	1		T148	1
range_16_to_126	seven	15725	1		T1	25		T5	33		T40	2
range_16_to_126	three	11644	1		T1	25		T95	1		T40	23
fifteen	seven	210	1		T87	1		T162	1		T298	1
fifteen	three	198	1		T88	1		T162	1		T299	1
range_2_to_14	seven	1275	1		T16	4		T87	6		T88	8
range_2_to_14	three	1783	1		T16	3		T87	4		T88	5
seven	seven	91	1		T88	2		T170	1		T235	63
seven	three	85	1		T300	1		T235	60		T298	1
one	seven	41	1		T88	1		T148	1		T301	2
one	three	45	1		T16	1		T301	2		T169	1
zero	seven	44	1		T162	1		T302	1		T158	1
zero	three	20	1		T162	1		T303	1		T304	1