Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	137035	1		T1	72		T3	17		T27	1
auto[1]	61955	1		T1	72		T27	1		T29	1

---

Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
sixty_four	29976	1		T1	2		T27	2		T28	1060
sixty_three	1217	1		T4	10		T5	3		T100	6
sixty_two	1134	1		T1	2		T4	4		T5	3
sixty_one	1156	1		T1	2		T4	3		T5	1
five	1528	1		T1	2		T4	6		T5	3
four	1584	1		T4	6		T5	6		T40	3
three	1475	1		T4	2		T5	1		T40	1
one	1763	1		T1	4		T4	3		T5	5
zero	11863	1		T4	3		T5	2		T34	2

---

Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
sixty_four	auto[0]	24817	1		T1	1		T27	1		T28	1060
sixty_four	auto[1]	5159	1		T1	1		T27	1		T5	2
sixty_three	auto[0]	767	1		T4	6		T5	2		T100	3
sixty_three	auto[1]	450	1		T4	4		T5	1		T100	3
sixty_two	auto[0]	722	1		T1	1		T4	3		T5	2
sixty_two	auto[1]	412	1		T1	1		T4	1		T5	1
sixty_one	auto[0]	738	1		T1	1		T4	3		T5	1
sixty_one	auto[1]	418	1		T1	1		T40	1		T100	1
five	auto[0]	804	1		T1	1		T4	4		T5	2
five	auto[1]	724	1		T1	1		T4	2		T5	1
four	auto[0]	813	1		T4	4		T5	4		T40	3
four	auto[1]	771	1		T4	2		T5	2		T100	2
three	auto[0]	759	1		T4	1		T5	1		T40	1
three	auto[1]	716	1		T4	1		T20	1		T101	1
one	auto[0]	890	1		T1	2		T4	2		T5	4
one	auto[1]	873	1		T1	2		T4	1		T5	1
zero	auto[0]	932	1		T4	3		T5	1		T34	1
zero	auto[1]	10931	1		T5	1		T34	1		T146	1