Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
42.67	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	6	16	72.73
Crosses	128	80	48	37.50

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	16	4	12	75.00	100	1	1	16
cp_pid	4	2	2	50.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	128	80	48	37.50	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	89220	1		T1	72		T27	1		T28	1060
auto[1]	56920	1		T1	72		T27	1		T30	1

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	16	4	12	75.00

Automatically Generated Bins for cp_endp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[12] - auto[15]]	--	--	4

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	12941	1		T31	1		T4	48		T5	32
auto[1]	11279	1		T30	2		T4	48		T33	9
auto[2]	14222	1		T1	24		T146	2		T6	2
auto[3]	9578	1		T1	24		T95	1		T40	22
auto[4]	10776	1		T16	16		T8	2		T87	30
auto[5]	11064	1		T4	48		T5	32		T40	21
auto[6]	10107	1		T1	24		T29	1		T40	21
auto[7]	13237	1		T1	24		T5	32		T21	3
auto[8]	16355	1		T27	2		T4	48		T40	21
auto[9]	11188	1		T4	48		T5	32		T34	2
auto[10]	14557	1		T1	24		T32	2		T5	32
auto[11]	10836	1		T1	24		T28	1060		T5	32

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	2	2	50.00

User Defined Bins for cp_pid

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
nak	0	1	1
ack	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
data1	68332	1		T1	70		T28	530		T4	119
data0	77780	1		T1	74		T27	2		T28	530

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	80	48	37.50	80

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Element holes

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	NUMBER
[nak , ack]	*	*	--	--	64
[data1 , data0]	*	[auto[12] - auto[15]]	--	--	16

Covered bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
data1	auto[0]	auto[0]	3839	1		T4	9		T5	3		T40	4
data1	auto[0]	auto[1]	2964	1		T4	8		T33	4		T40	1
data1	auto[0]	auto[2]	4022	1		T1	5		T16	9		T20	35
data1	auto[0]	auto[3]	2109	1		T1	6		T40	5		T87	17
data1	auto[0]	auto[4]	2252	1		T16	9		T87	14		T277	6
data1	auto[0]	auto[5]	2601	1		T4	12		T5	8		T40	4
data1	auto[0]	auto[6]	2138	1		T1	4		T40	3		T100	39
data1	auto[0]	auto[7]	3562	1		T1	4		T5	8		T21	1
data1	auto[0]	auto[8]	5130	1		T4	12		T40	6		T16	13
data1	auto[0]	auto[9]	2319	1		T4	8		T5	5		T40	4
data1	auto[0]	auto[10]	4117	1		T1	5		T5	4		T40	3
data1	auto[0]	auto[11]	2534	1		T1	3		T28	530		T5	8
data1	auto[1]	auto[0]	2180	1		T4	14		T5	13		T40	5
data1	auto[1]	auto[1]	2305	1		T4	16		T40	6		T101	15
data1	auto[1]	auto[2]	2676	1		T1	6		T16	6		T20	67
data1	auto[1]	auto[3]	2313	1		T1	6		T40	6		T16	3
data1	auto[1]	auto[4]	2740	1		T148	6		T228	26		T162	8
data1	auto[1]	auto[5]	2513	1		T4	12		T5	8		T40	4
data1	auto[1]	auto[6]	2522	1		T1	8		T40	5		T100	82
data1	auto[1]	auto[7]	2647	1		T1	8		T5	8		T21	1
data1	auto[1]	auto[8]	2696	1		T4	12		T40	4		T87	5
data1	auto[1]	auto[9]	2869	1		T4	16		T5	11		T40	4
data1	auto[1]	auto[10]	2821	1		T1	7		T5	11		T40	5
data1	auto[1]	auto[11]	2463	1		T1	8		T5	8		T88	11
data0	auto[0]	auto[0]	4944	1		T31	1		T4	15		T5	13
data0	auto[0]	auto[1]	4016	1		T30	1		T4	16		T33	5
data0	auto[0]	auto[2]	5310	1		T1	7		T146	1		T6	1
data0	auto[0]	auto[3]	3148	1		T1	6		T95	1		T40	8
data0	auto[0]	auto[4]	3500	1		T16	7		T8	1		T87	16
data0	auto[0]	auto[5]	3748	1		T4	12		T5	8		T40	7
data0	auto[0]	auto[6]	3248	1		T1	8		T29	1		T40	8
data0	auto[0]	auto[7]	4814	1		T1	8		T5	8		T21	1
data0	auto[0]	auto[8]	6267	1		T27	1		T4	12		T40	6
data0	auto[0]	auto[9]	3629	1		T4	16		T5	11		T34	1
data0	auto[0]	auto[10]	5250	1		T1	7		T32	1		T5	12
data0	auto[0]	auto[11]	3731	1		T1	9		T28	530		T5	8
data0	auto[1]	auto[0]	1974	1		T4	10		T5	3		T40	4
data0	auto[1]	auto[1]	1993	1		T30	1		T4	8		T40	3
data0	auto[1]	auto[2]	2213	1		T1	6		T146	1		T6	1
data0	auto[1]	auto[3]	2008	1		T1	6		T40	3		T16	1
data0	auto[1]	auto[4]	2277	1		T8	1		T147	1		T148	2
data0	auto[1]	auto[5]	2199	1		T4	12		T5	8		T40	5
data0	auto[1]	auto[6]	2194	1		T1	4		T40	4		T100	40
data0	auto[1]	auto[7]	2213	1		T1	4		T5	8		T278	1
data0	auto[1]	auto[8]	2261	1		T27	1		T4	12		T40	5
data0	auto[1]	auto[9]	2371	1		T4	8		T5	5		T34	1
data0	auto[1]	auto[10]	2367	1		T1	5		T32	1		T5	5
data0	auto[1]	auto[11]	2105	1		T1	4		T5	8		T88	6