Summary for Variable cp_in_enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_in_enable
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6910 |
1 |
|
T3 |
1 |
|
T16 |
126 |
|
T155 |
5 |
auto[1] |
68507 |
1 |
|
T1 |
78 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_in_iso
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_in_iso
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
70382 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T27 |
1 |
auto[1] |
5035 |
1 |
|
T29 |
1 |
|
T90 |
1 |
|
T18 |
78 |
Summary for Variable cp_in_stall
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_in_stall
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
70471 |
1 |
|
T1 |
78 |
|
T27 |
1 |
|
T29 |
1 |
auto[1] |
4946 |
1 |
|
T3 |
1 |
|
T16 |
59 |
|
T155 |
8 |
Summary for Variable cp_pid
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
1 |
1 |
50.00 |
User Defined Bins for cp_pid
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER |
ignore_pre[PidTypePre] |
0 |
1 |
1 |
Covered bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
pkt_types[PidTypeInToken] |
75417 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T27 |
1 |
Summary for Cross cr_pid_x_epconfig
Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
11 |
5 |
31.25 |
11 |
Automatically Generated Cross Bins for cr_pid_x_epconfig
Element holes
cp_pid | cp_in_enable | cp_in_iso | cp_in_stall | COUNT | AT LEAST | NUMBER |
[ignore_pre[PidTypePre]] |
* |
* |
* |
-- |
-- |
8 |
[pkt_types[PidTypeInToken]] |
[auto[0]] |
[auto[1]] |
* |
-- |
-- |
2 |
Uncovered bins
cp_pid | cp_in_enable | cp_in_iso | cp_in_stall | COUNT | AT LEAST | NUMBER |
[pkt_types[PidTypeInToken]] |
[auto[1]] |
[auto[1]] |
[auto[1]] |
0 |
1 |
1 |
Covered bins
cp_pid | cp_in_enable | cp_in_iso | cp_in_stall | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
pkt_types[PidTypeInToken] |
auto[0] |
auto[0] |
auto[0] |
4368 |
1 |
|
T16 |
80 |
|
T87 |
51 |
|
T271 |
1 |
pkt_types[PidTypeInToken] |
auto[0] |
auto[0] |
auto[1] |
2542 |
1 |
|
T3 |
1 |
|
T16 |
46 |
|
T155 |
5 |
pkt_types[PidTypeInToken] |
auto[1] |
auto[0] |
auto[0] |
61068 |
1 |
|
T1 |
78 |
|
T27 |
1 |
|
T30 |
1 |
pkt_types[PidTypeInToken] |
auto[1] |
auto[0] |
auto[1] |
2404 |
1 |
|
T16 |
13 |
|
T155 |
3 |
|
T87 |
23 |
pkt_types[PidTypeInToken] |
auto[1] |
auto[1] |
auto[0] |
5035 |
1 |
|
T29 |
1 |
|
T90 |
1 |
|
T18 |
78 |