Group : usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
33.85 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv



Summary for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 11 1 10 90.91
Crosses 54 42 12 22.22


Variables for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_avout 3 0 3 100.00 100 1 1 0
cp_avsetup 3 0 3 100.00 100 1 1 0
cp_pid 2 0 2 100.00 100 1 1 0
cp_rx 3 1 2 66.67 100 1 1 0


Crosses for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_fifo_X_pid 54 42 12 22.22 100 1 1 0


Summary for Variable cp_avout

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_avout

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
full 41346 1 T1 72 T4 230 T5 181
solo 93659 1 T3 17 T27 1 T28 1060
empty 1920 1 T16 34 T21 1 T50 1



Summary for Variable cp_avsetup

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_avsetup

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
full 41341 1 T1 72 T4 230 T5 181
solo 49240 1 T3 15 T16 576 T21 1
empty 46398 1 T3 2 T27 1 T28 1060



Summary for Variable cp_pid

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_pid

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
out 109514 1 T1 48 T3 12 T27 1
setup 27473 1 T1 24 T3 5 T4 36



Summary for Variable cp_rx

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 1 2 66.67


User Defined Bins for cp_rx

Uncovered bins
NAMECOUNTAT LEASTNUMBER
full 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
solo 14 1 T54 2 T55 1 T69 1
empty 111653 1 T1 72 T3 17 T27 1



Summary for Cross cr_fifo_X_pid

Samples crossed: cp_avsetup cp_avout cp_rx cp_pid
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 54 42 12 22.22 42


Automatically Generated Cross Bins for cr_fifo_X_pid

Element holes
cp_avsetupcp_avoutcp_rxcp_pidCOUNTAT LEASTNUMBER
[full] [full] [full , solo] * -- -- 4
[full] [solo , empty] * * -- -- 12
[solo] [full] [full , solo] * -- -- 4
[solo] [solo] [full] * -- -- 2
[solo] [empty] [full] * -- -- 2
[empty] [full] * * -- -- 6
[empty] [solo] [full , solo] * -- -- 4
[empty] [empty] [full , solo] * -- -- 4


Uncovered bins
cp_avsetupcp_avoutcp_rxcp_pidCOUNTAT LEASTNUMBER
[solo] [full] [empty] [setup] 0 1 1
[solo] [empty] [solo , empty] [out] -- -- 2
[empty] [solo] [empty] [setup] 0 1 1


Covered bins
cp_avsetupcp_avoutcp_rxcp_pidCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
full full empty out 31571 1 T1 48 T4 194 T5 154
full full empty setup 9770 1 T1 24 T4 36 T5 27
solo full empty out 5 1 T54 1 T56 1 T57 1
solo solo solo out 5 1 T54 1 T56 1 T57 1
solo solo solo setup 5 1 T54 1 T56 1 T57 1
solo solo empty out 17946 1 T3 10 T16 215 T155 9
solo solo empty setup 8960 1 T3 5 T16 123 T155 9
solo empty solo setup 1 1 T55 1 - - - -
solo empty empty setup 313 1 T21 1 T155 2 T87 2
empty solo empty out 42882 1 T3 2 T27 1 T28 1060
empty empty empty out 145 1 T67 142 T69 1 T70 1
empty empty empty setup 50 1 T50 1 T89 1 T276 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%