Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	89506	1		T1	2		T3	2		T27	3
all_pins[1]	89506	1		T1	2		T3	2		T27	3
all_pins[2]	89506	1		T1	2		T3	2		T27	3
all_pins[3]	89506	1		T1	2		T3	2		T27	3
all_pins[4]	89506	1		T1	2		T3	2		T27	3
all_pins[5]	89506	1		T1	2		T3	2		T27	3
all_pins[6]	89506	1		T1	2		T3	2		T27	3
all_pins[7]	89506	1		T1	2		T3	2		T27	3
all_pins[8]	89506	1		T1	2		T3	2		T27	3
all_pins[9]	89506	1		T1	2		T3	2		T27	3
all_pins[10]	89506	1		T1	2		T3	2		T27	3
all_pins[11]	89506	1		T1	2		T3	2		T27	3
all_pins[12]	89506	1		T1	2		T3	2		T27	3
all_pins[13]	89506	1		T1	2		T3	2		T27	3
all_pins[14]	89506	1		T1	2		T3	2		T27	3
all_pins[15]	89506	1		T1	2		T3	2		T27	3
all_pins[16]	89506	1		T1	2		T3	2		T27	3
all_pins[17]	89506	1		T1	2		T3	2		T27	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2861808	1		T1	64		T3	64		T27	96
values[0x1]	2384	1		T30	1		T42	1		T6	1
transitions[0x0=>0x1]	2110	1		T30	1		T42	1		T6	1
transitions[0x1=>0x0]	2110	1		T30	1		T42	1		T6	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	89395	1		T1	2		T3	2		T27	3
all_pins[0]	values[0x1]	111	1		T51	1		T289	1		T290	1
all_pins[0]	transitions[0x0=>0x1]	96	1		T51	1		T289	1		T290	1
all_pins[0]	transitions[0x1=>0x0]	998	1		T30	1		T6	1		T7	1
all_pins[1]	values[0x0]	88493	1		T1	2		T3	2		T27	3
all_pins[1]	values[0x1]	1013	1		T30	1		T6	1		T7	1
all_pins[1]	transitions[0x0=>0x1]	995	1		T30	1		T6	1		T7	1
all_pins[1]	transitions[0x1=>0x0]	107	1		T42	1		T43	1		T44	1
all_pins[2]	values[0x0]	89381	1		T1	2		T3	2		T27	3
all_pins[2]	values[0x1]	125	1		T42	1		T43	1		T44	1
all_pins[2]	transitions[0x0=>0x1]	105	1		T42	1		T43	1		T44	1
all_pins[2]	transitions[0x1=>0x0]	47	1		T67	1		T197	2		T198	3
all_pins[3]	values[0x0]	89439	1		T1	2		T3	2		T27	3
all_pins[3]	values[0x1]	67	1		T67	1		T197	2		T198	3
all_pins[3]	transitions[0x0=>0x1]	53	1		T67	1		T198	2		T200	6
all_pins[3]	transitions[0x1=>0x0]	62	1		T68	1		T197	1		T199	1
all_pins[4]	values[0x0]	89430	1		T1	2		T3	2		T27	3
all_pins[4]	values[0x1]	76	1		T68	1		T197	3		T199	1
all_pins[4]	transitions[0x0=>0x1]	65	1		T68	1		T197	3		T198	3
all_pins[4]	transitions[0x1=>0x0]	60	1		T197	1		T200	3		T265	2
all_pins[5]	values[0x0]	89435	1		T1	2		T3	2		T27	3
all_pins[5]	values[0x1]	71	1		T197	1		T199	1		T200	3
all_pins[5]	transitions[0x0=>0x1]	51	1		T197	1		T200	2		T265	2
all_pins[5]	transitions[0x1=>0x0]	57	1		T199	2		T198	2		T282	1
all_pins[6]	values[0x0]	89429	1		T1	2		T3	2		T27	3
all_pins[6]	values[0x1]	77	1		T199	3		T198	2		T282	1
all_pins[6]	transitions[0x0=>0x1]	56	1		T199	2		T198	2		T282	1
all_pins[6]	transitions[0x1=>0x0]	43	1		T53	1		T197	1		T198	2
all_pins[7]	values[0x0]	89442	1		T1	2		T3	2		T27	3
all_pins[7]	values[0x1]	64	1		T53	1		T197	1		T199	1
all_pins[7]	transitions[0x0=>0x1]	50	1		T53	1		T199	1		T198	1
all_pins[7]	transitions[0x1=>0x0]	42	1		T55	1		T197	2		T198	1
all_pins[8]	values[0x0]	89450	1		T1	2		T3	2		T27	3
all_pins[8]	values[0x1]	56	1		T55	1		T197	3		T198	2
all_pins[8]	transitions[0x0=>0x1]	44	1		T55	1		T197	3		T198	1
all_pins[8]	transitions[0x1=>0x0]	68	1		T64	2		T65	2		T66	2
all_pins[9]	values[0x0]	89426	1		T1	2		T3	2		T27	3
all_pins[9]	values[0x1]	80	1		T64	2		T65	2		T66	2
all_pins[9]	transitions[0x0=>0x1]	60	1		T64	2		T65	2		T66	2
all_pins[9]	transitions[0x1=>0x0]	57	1		T197	4		T198	1		T265	1
all_pins[10]	values[0x0]	89429	1		T1	2		T3	2		T27	3
all_pins[10]	values[0x1]	77	1		T197	5		T198	1		T282	1
all_pins[10]	transitions[0x0=>0x1]	61	1		T197	5		T198	1		T200	1
all_pins[10]	transitions[0x1=>0x0]	102	1		T49	1		T74	1		T75	1
all_pins[11]	values[0x0]	89388	1		T1	2		T3	2		T27	3
all_pins[11]	values[0x1]	118	1		T49	1		T74	1		T75	1
all_pins[11]	transitions[0x0=>0x1]	104	1		T49	1		T74	1		T75	1
all_pins[11]	transitions[0x1=>0x0]	59	1		T77	1		T78	1		T79	1
all_pins[12]	values[0x0]	89433	1		T1	2		T3	2		T27	3
all_pins[12]	values[0x1]	73	1		T77	1		T78	1		T79	1
all_pins[12]	transitions[0x0=>0x1]	53	1		T77	1		T78	1		T79	1
all_pins[12]	transitions[0x1=>0x0]	102	1		T72	1		T73	1		T81	1
all_pins[13]	values[0x0]	89384	1		T1	2		T3	2		T27	3
all_pins[13]	values[0x1]	122	1		T72	1		T73	1		T81	1
all_pins[13]	transitions[0x0=>0x1]	103	1		T72	1		T73	1		T81	1
all_pins[13]	transitions[0x1=>0x0]	53	1		T265	3		T283	1		T284	1
all_pins[14]	values[0x0]	89434	1		T1	2		T3	2		T27	3
all_pins[14]	values[0x1]	72	1		T198	1		T265	3		T283	1
all_pins[14]	transitions[0x0=>0x1]	55	1		T265	2		T283	1		T284	1
all_pins[14]	transitions[0x1=>0x0]	44	1		T197	2		T198	3		T286	2
all_pins[15]	values[0x0]	89445	1		T1	2		T3	2		T27	3
all_pins[15]	values[0x1]	61	1		T197	2		T198	4		T265	1
all_pins[15]	transitions[0x0=>0x1]	47	1		T197	2		T198	1		T265	1
all_pins[15]	transitions[0x1=>0x0]	58	1		T69	4		T70	4		T71	4
all_pins[16]	values[0x0]	89434	1		T1	2		T3	2		T27	3
all_pins[16]	values[0x1]	72	1		T69	4		T70	4		T71	4
all_pins[16]	transitions[0x0=>0x1]	63	1		T69	4		T70	4		T71	4
all_pins[16]	transitions[0x1=>0x0]	40	1		T58	1		T59	1		T60	1
all_pins[17]	values[0x0]	89457	1		T1	2		T3	2		T27	3
all_pins[17]	values[0x1]	49	1		T58	1		T59	1		T60	1
all_pins[17]	transitions[0x0=>0x1]	49	1		T58	1		T59	1		T60	1