Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[12]	5315	1		T4	26		T5	16		T40	2
invalid_ep[13]	5311	1		T4	29		T5	21		T40	3
invalid_ep[14]	5304	1		T4	33		T5	24		T40	4
invalid_ep[15]	5317	1		T4	22		T5	24		T40	1
endpoints[0]	17161	1		T3	7		T31	1		T4	49
endpoints[1]	15423	1		T30	2		T4	49		T33	9
endpoints[2]	18009	1		T1	25		T3	5		T146	2
endpoints[3]	13773	1		T1	25		T95	1		T40	23
endpoints[4]	14698	1		T3	3		T40	5		T16	56
endpoints[5]	15840	1		T4	49		T5	33		T40	22
endpoints[6]	13778	1		T1	25		T3	1		T29	2
endpoints[7]	17386	1		T1	25		T5	33		T40	2
endpoints[8]	20285	1		T3	1		T27	2		T4	49
endpoints[9]	15425	1		T3	1		T4	49		T5	33
endpoints[10]	18713	1		T1	25		T32	2		T5	33
endpoints[11]	15010	1		T1	25		T28	1060		T5	33

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	27473	1		T1	24		T3	5		T4	36
pkt_types[PidTypeOutToken]	109514	1		T1	48		T3	12		T27	1
pkt_types[PidTypeInToken]	79695	1		T1	78		T3	1		T27	1

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[12]	1074	1		T16	13		T87	17		T88	34
pkt_types[PidTypeSetupToken]	invalid_ep[13]	1056	1		T16	12		T87	18		T88	24
pkt_types[PidTypeSetupToken]	invalid_ep[14]	1114	1		T16	13		T87	31		T88	27
pkt_types[PidTypeSetupToken]	invalid_ep[15]	1059	1		T16	20		T87	22		T88	22
pkt_types[PidTypeSetupToken]	endpoints[0]	1724	1		T3	1		T4	10		T5	11
pkt_types[PidTypeSetupToken]	endpoints[1]	1829	1		T4	12		T40	7		T16	15
pkt_types[PidTypeSetupToken]	endpoints[2]	2073	1		T1	4		T3	3		T16	16
pkt_types[PidTypeSetupToken]	endpoints[3]	1773	1		T40	5		T16	16		T155	2
pkt_types[PidTypeSetupToken]	endpoints[4]	2105	1		T3	1		T40	1		T16	16
pkt_types[PidTypeSetupToken]	endpoints[5]	1895	1		T16	12		T87	22		T88	22
pkt_types[PidTypeSetupToken]	endpoints[6]	1795	1		T1	5		T40	1		T100	64
pkt_types[PidTypeSetupToken]	endpoints[7]	1964	1		T1	6		T16	12		T21	1
pkt_types[PidTypeSetupToken]	endpoints[8]	1980	1		T16	16		T87	14		T88	27
pkt_types[PidTypeSetupToken]	endpoints[9]	2154	1		T4	14		T5	8		T16	13
pkt_types[PidTypeSetupToken]	endpoints[10]	1964	1		T1	3		T5	8		T40	4
pkt_types[PidTypeSetupToken]	endpoints[11]	1914	1		T1	6		T16	18		T155	3
pkt_types[PidTypeOutToken]	invalid_ep[12]	3161	1		T4	26		T5	16		T40	2
pkt_types[PidTypeOutToken]	invalid_ep[13]	3178	1		T4	29		T5	21		T40	3
pkt_types[PidTypeOutToken]	invalid_ep[14]	3148	1		T4	33		T5	24		T40	4
pkt_types[PidTypeOutToken]	invalid_ep[15]	3179	1		T4	22		T5	24		T40	1
pkt_types[PidTypeOutToken]	endpoints[0]	9686	1		T3	6		T31	1		T4	14
pkt_types[PidTypeOutToken]	endpoints[1]	7836	1		T30	1		T4	12		T33	9
pkt_types[PidTypeOutToken]	endpoints[2]	9737	1		T1	8		T3	1		T146	1
pkt_types[PidTypeOutToken]	endpoints[3]	5868	1		T1	12		T95	1		T40	8
pkt_types[PidTypeOutToken]	endpoints[4]	6235	1		T3	2		T40	3		T16	24
pkt_types[PidTypeOutToken]	endpoints[5]	7147	1		T4	24		T5	16		T40	12
pkt_types[PidTypeOutToken]	endpoints[6]	6063	1		T1	7		T3	1		T29	1
pkt_types[PidTypeOutToken]	endpoints[7]	8960	1		T1	6		T5	16		T40	1
pkt_types[PidTypeOutToken]	endpoints[8]	11772	1		T3	1		T27	1		T4	24
pkt_types[PidTypeOutToken]	endpoints[9]	6497	1		T3	1		T4	10		T5	8
pkt_types[PidTypeOutToken]	endpoints[10]	10059	1		T1	9		T32	1		T5	8
pkt_types[PidTypeOutToken]	endpoints[11]	6988	1		T1	6		T28	1060		T5	16
pkt_types[PidTypeInToken]	invalid_ep[12]	1080	1		T16	15		T87	19		T88	24
pkt_types[PidTypeInToken]	invalid_ep[13]	1077	1		T16	20		T87	32		T88	31
pkt_types[PidTypeInToken]	invalid_ep[14]	1042	1		T16	12		T87	20		T88	16
pkt_types[PidTypeInToken]	invalid_ep[15]	1079	1		T16	11		T87	14		T88	23
pkt_types[PidTypeInToken]	endpoints[0]	5743	1		T4	25		T5	17		T40	11
pkt_types[PidTypeInToken]	endpoints[1]	5754	1		T30	1		T4	25		T40	10
pkt_types[PidTypeInToken]	endpoints[2]	6195	1		T1	13		T3	1		T146	1
pkt_types[PidTypeInToken]	endpoints[3]	6128	1		T1	13		T40	10		T16	9
pkt_types[PidTypeInToken]	endpoints[4]	6349	1		T16	16		T8	1		T87	20
pkt_types[PidTypeInToken]	endpoints[5]	6791	1		T4	25		T5	17		T40	10
pkt_types[PidTypeInToken]	endpoints[6]	5915	1		T1	13		T29	1		T40	10
pkt_types[PidTypeInToken]	endpoints[7]	6457	1		T1	13		T5	17		T16	14
pkt_types[PidTypeInToken]	endpoints[8]	6529	1		T27	1		T4	25		T40	10
pkt_types[PidTypeInToken]	endpoints[9]	6766	1		T4	25		T5	17		T34	1
pkt_types[PidTypeInToken]	endpoints[10]	6688	1		T1	13		T32	1		T5	17
pkt_types[PidTypeInToken]	endpoints[11]	6102	1		T1	13		T5	17		T90	1