Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	284	1		T197	7		T199	7		T198	7
all_values[1]	284	1		T197	7		T199	7		T198	7
all_values[2]	284	1		T197	7		T199	7		T198	7
all_values[3]	284	1		T197	7		T199	7		T198	7
all_values[4]	284	1		T197	7		T199	7		T198	7
all_values[5]	284	1		T197	7		T199	7		T198	7
all_values[6]	284	1		T197	7		T199	7		T198	7
all_values[7]	284	1		T197	7		T199	7		T198	7
all_values[8]	284	1		T197	7		T199	7		T198	7
all_values[9]	284	1		T197	7		T199	7		T198	7
all_values[10]	284	1		T197	7		T199	7		T198	7
all_values[11]	284	1		T197	7		T199	7		T198	7
all_values[12]	284	1		T197	7		T199	7		T198	7
all_values[13]	284	1		T197	7		T199	7		T198	7
all_values[14]	284	1		T197	7		T199	7		T198	7
all_values[15]	284	1		T197	7		T199	7		T198	7
all_values[16]	284	1		T197	7		T199	7		T198	7
all_values[17]	284	1		T197	7		T199	7		T198	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	6744	1		T197	168		T199	166		T198	161
auto[1]	2344	1		T197	56		T199	58		T198	63

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	6242	1		T197	150		T199	159		T198	155
auto[1]	2846	1		T197	74		T199	65		T198	69

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5356	1		T197	131		T199	135		T198	135
auto[1]	3732	1		T197	93		T199	89		T198	89

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	85	1		T197	3		T199	2		T198	2
all_values[0]	auto[0]	auto[1]	auto[0]	76	1		T197	1		T199	1		T198	4
all_values[0]	auto[1]	auto[0]	auto[1]	64	1		T197	3		T199	1		T198	1
all_values[0]	auto[1]	auto[1]	auto[1]	59	1		T199	3		T282	3		T283	1
all_values[1]	auto[0]	auto[0]	auto[0]	97	1		T197	3		T199	2		T198	4
all_values[1]	auto[0]	auto[1]	auto[0]	77	1		T197	2		T199	3		T198	1
all_values[1]	auto[1]	auto[0]	auto[1]	50	1		T282	2		T265	1		T283	1
all_values[1]	auto[1]	auto[1]	auto[1]	60	1		T197	2		T199	2		T198	2
all_values[2]	auto[0]	auto[0]	auto[0]	54	1		T197	2		T200	4		T283	4
all_values[2]	auto[0]	auto[0]	auto[1]	39	1		T198	1		T282	1		T200	1
all_values[2]	auto[0]	auto[1]	auto[0]	46	1		T197	1		T198	4		T283	2
all_values[2]	auto[0]	auto[1]	auto[1]	24	1		T199	2		T282	1		T266	2
all_values[2]	auto[1]	auto[0]	auto[1]	66	1		T197	2		T199	2		T198	1
all_values[2]	auto[1]	auto[1]	auto[1]	55	1		T197	2		T199	3		T198	1
all_values[3]	auto[0]	auto[0]	auto[0]	56	1		T199	2		T198	2		T282	1
all_values[3]	auto[0]	auto[0]	auto[1]	31	1		T282	1		T283	2		T284	2
all_values[3]	auto[0]	auto[1]	auto[0]	45	1		T199	4		T198	1		T200	1
all_values[3]	auto[0]	auto[1]	auto[1]	28	1		T197	1		T198	1		T200	2
all_values[3]	auto[1]	auto[0]	auto[1]	72	1		T197	3		T199	1		T198	2
all_values[3]	auto[1]	auto[1]	auto[1]	52	1		T197	3		T198	1		T200	4
all_values[4]	auto[0]	auto[0]	auto[0]	52	1		T197	1		T199	2		T198	2
all_values[4]	auto[0]	auto[0]	auto[1]	27	1		T197	1		T199	1		T283	1
all_values[4]	auto[0]	auto[1]	auto[0]	47	1		T199	1		T198	2		T282	1
all_values[4]	auto[0]	auto[1]	auto[1]	34	1		T197	2		T282	1		T285	1
all_values[4]	auto[1]	auto[0]	auto[1]	66	1		T197	1		T199	1		T282	1
all_values[4]	auto[1]	auto[1]	auto[1]	58	1		T197	2		T199	2		T198	3
all_values[5]	auto[0]	auto[0]	auto[0]	69	1		T197	1		T199	3		T198	4
all_values[5]	auto[0]	auto[0]	auto[1]	25	1		T282	1		T286	2		T287	1
all_values[5]	auto[0]	auto[1]	auto[0]	51	1		T199	2		T198	3		T282	1
all_values[5]	auto[0]	auto[1]	auto[1]	33	1		T197	1		T200	1		T265	2
all_values[5]	auto[1]	auto[0]	auto[1]	57	1		T197	3		T282	1		T265	1
all_values[5]	auto[1]	auto[1]	auto[1]	49	1		T197	2		T199	2		T200	2
all_values[6]	auto[0]	auto[0]	auto[0]	61	1		T197	1		T265	2		T283	4
all_values[6]	auto[0]	auto[0]	auto[1]	32	1		T197	3		T198	1		T282	1
all_values[6]	auto[0]	auto[1]	auto[0]	47	1		T199	2		T198	3		T282	2
all_values[6]	auto[0]	auto[1]	auto[1]	34	1		T199	3		T200	1		T284	1
all_values[6]	auto[1]	auto[0]	auto[1]	55	1		T197	2		T199	1		T200	2
all_values[6]	auto[1]	auto[1]	auto[1]	55	1		T197	1		T199	1		T198	3
all_values[7]	auto[0]	auto[0]	auto[0]	84	1		T197	2		T199	3		T198	1
all_values[7]	auto[0]	auto[1]	auto[0]	85	1		T197	3		T199	1		T198	3
all_values[7]	auto[1]	auto[0]	auto[1]	52	1		T198	1		T200	1		T283	1
all_values[7]	auto[1]	auto[1]	auto[1]	63	1		T197	2		T199	3		T198	2
all_values[8]	auto[0]	auto[0]	auto[0]	96	1		T197	2		T199	4		T282	3
all_values[8]	auto[0]	auto[1]	auto[0]	80	1		T197	1		T199	1		T198	3
all_values[8]	auto[1]	auto[0]	auto[1]	58	1		T197	1		T199	2		T198	4
all_values[8]	auto[1]	auto[1]	auto[1]	50	1		T197	3		T200	2		T265	1
all_values[9]	auto[0]	auto[0]	auto[0]	61	1		T197	1		T199	5		T200	2
all_values[9]	auto[0]	auto[0]	auto[1]	20	1		T197	1		T282	2		T287	1
all_values[9]	auto[0]	auto[1]	auto[0]	55	1		T197	1		T200	1		T265	3
all_values[9]	auto[0]	auto[1]	auto[1]	34	1		T197	1		T199	1		T198	1
all_values[9]	auto[1]	auto[0]	auto[1]	60	1		T197	1		T198	5		T282	1
all_values[9]	auto[1]	auto[1]	auto[1]	54	1		T197	2		T199	1		T198	1
all_values[10]	auto[0]	auto[0]	auto[0]	60	1		T199	3		T198	1		T265	1
all_values[10]	auto[0]	auto[0]	auto[1]	26	1		T199	1		T198	3		T282	1
all_values[10]	auto[0]	auto[1]	auto[0]	43	1		T200	4		T265	1		T283	1
all_values[10]	auto[0]	auto[1]	auto[1]	40	1		T197	1		T265	1		T283	1
all_values[10]	auto[1]	auto[0]	auto[1]	59	1		T197	1		T199	3		T198	1
all_values[10]	auto[1]	auto[1]	auto[1]	56	1		T197	5		T198	2		T282	1
all_values[11]	auto[0]	auto[0]	auto[0]	61	1		T197	2		T199	4		T198	1
all_values[11]	auto[0]	auto[0]	auto[1]	35	1		T199	1		T198	1		T282	1
all_values[11]	auto[0]	auto[1]	auto[0]	42	1		T197	5		T198	2		T200	1
all_values[11]	auto[0]	auto[1]	auto[1]	29	1		T198	1		T283	1		T288	1
all_values[11]	auto[1]	auto[0]	auto[1]	66	1		T199	2		T282	2		T200	3
all_values[11]	auto[1]	auto[1]	auto[1]	51	1		T198	2		T282	1		T200	1
all_values[12]	auto[0]	auto[0]	auto[0]	64	1		T197	2		T198	3		T282	1
all_values[12]	auto[0]	auto[0]	auto[1]	29	1		T197	1		T199	1		T200	2
all_values[12]	auto[0]	auto[1]	auto[0]	47	1		T199	2		T198	1		T286	3
all_values[12]	auto[0]	auto[1]	auto[1]	30	1		T197	2		T199	1		T282	1
all_values[12]	auto[1]	auto[0]	auto[1]	70	1		T197	2		T199	1		T198	3
all_values[12]	auto[1]	auto[1]	auto[1]	44	1		T199	2		T282	1		T200	2
all_values[13]	auto[0]	auto[0]	auto[0]	62	1		T197	3		T199	1		T282	1
all_values[13]	auto[0]	auto[0]	auto[1]	28	1		T198	1		T282	1		T200	1
all_values[13]	auto[0]	auto[1]	auto[0]	48	1		T199	1		T200	2		T265	2
all_values[13]	auto[0]	auto[1]	auto[1]	35	1		T197	1		T199	2		T198	2
all_values[13]	auto[1]	auto[0]	auto[1]	67	1		T197	2		T199	1		T198	1
all_values[13]	auto[1]	auto[1]	auto[1]	44	1		T197	1		T199	2		T198	3
all_values[14]	auto[0]	auto[0]	auto[0]	65	1		T197	3		T199	6		T198	1
all_values[14]	auto[0]	auto[0]	auto[1]	30	1		T197	1		T198	1		T283	1
all_values[14]	auto[0]	auto[1]	auto[0]	40	1		T197	1		T199	1		T282	2
all_values[14]	auto[0]	auto[1]	auto[1]	33	1		T198	1		T265	1		T266	1
all_values[14]	auto[1]	auto[0]	auto[1]	69	1		T197	1		T198	4		T282	1
all_values[14]	auto[1]	auto[1]	auto[1]	47	1		T197	1		T265	2		T283	2
all_values[15]	auto[0]	auto[0]	auto[0]	68	1		T197	1		T199	1		T198	2
all_values[15]	auto[0]	auto[0]	auto[1]	24	1		T197	1		T199	3		T285	1
all_values[15]	auto[0]	auto[1]	auto[0]	50	1		T282	1		T200	3		T265	1
all_values[15]	auto[0]	auto[1]	auto[1]	29	1		T197	1		T198	1		T265	1
all_values[15]	auto[1]	auto[0]	auto[1]	69	1		T197	3		T199	3		T198	3
all_values[15]	auto[1]	auto[1]	auto[1]	44	1		T197	1		T198	1		T265	1
all_values[16]	auto[0]	auto[0]	auto[0]	64	1		T197	3		T282	3		T200	1
all_values[16]	auto[0]	auto[0]	auto[1]	35	1		T199	1		T198	3		T200	1
all_values[16]	auto[0]	auto[1]	auto[0]	52	1		T197	2		T198	2		T200	2
all_values[16]	auto[0]	auto[1]	auto[1]	18	1		T199	1		T198	1		T200	2
all_values[16]	auto[1]	auto[0]	auto[1]	59	1		T197	1		T199	2		T200	1
all_values[16]	auto[1]	auto[1]	auto[1]	56	1		T197	1		T199	3		T198	1
all_values[17]	auto[0]	auto[0]	auto[0]	96	1		T197	5		T199	1		T198	2
all_values[17]	auto[0]	auto[1]	auto[0]	80	1		T199	3		T198	3		T282	3
all_values[17]	auto[1]	auto[0]	auto[1]	73	1		T197	1		T199	1		T198	1
all_values[17]	auto[1]	auto[1]	auto[1]	35	1		T197	1		T199	2		T198	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal