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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.51 97.79 93.74 97.44 71.88 96.17 98.17 71.38


Total test records in report: 2975
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T2817 /workspace/coverage/default/10.usbdev_timeout_missing_host_handshake.2573367657 Jul 26 05:08:38 PM PDT 24 Jul 26 05:09:12 PM PDT 24 1347588540 ps
T2818 /workspace/coverage/default/26.usbdev_device_address.2409664866 Jul 26 05:11:50 PM PDT 24 Jul 26 05:12:29 PM PDT 24 19408105966 ps
T2819 /workspace/coverage/default/23.usbdev_out_trans_nak.3945462728 Jul 26 05:11:21 PM PDT 24 Jul 26 05:11:22 PM PDT 24 165643266 ps
T2820 /workspace/coverage/default/45.usbdev_low_speed_traffic.2018273792 Jul 26 05:14:57 PM PDT 24 Jul 26 05:17:27 PM PDT 24 4868669991 ps
T2821 /workspace/coverage/default/0.usbdev_freq_loclk_max.3911154885 Jul 26 05:06:03 PM PDT 24 Jul 26 05:08:39 PM PDT 24 99227381884 ps
T2822 /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.16839852 Jul 26 05:12:20 PM PDT 24 Jul 26 05:12:21 PM PDT 24 190821546 ps
T2823 /workspace/coverage/default/18.usbdev_random_length_in_transaction.3557116107 Jul 26 05:10:28 PM PDT 24 Jul 26 05:10:29 PM PDT 24 169760684 ps
T2824 /workspace/coverage/default/41.usbdev_max_length_out_transaction.1853346365 Jul 26 05:14:21 PM PDT 24 Jul 26 05:14:23 PM PDT 24 194043672 ps
T2825 /workspace/coverage/default/6.usbdev_phy_config_pinflip.4186979416 Jul 26 05:07:45 PM PDT 24 Jul 26 05:07:46 PM PDT 24 259234681 ps
T2826 /workspace/coverage/default/39.usbdev_low_speed_traffic.2676433620 Jul 26 05:14:05 PM PDT 24 Jul 26 05:15:09 PM PDT 24 8997336320 ps
T2827 /workspace/coverage/default/25.usbdev_disconnected.3949249092 Jul 26 05:11:36 PM PDT 24 Jul 26 05:11:37 PM PDT 24 145034329 ps
T2828 /workspace/coverage/default/26.usbdev_min_length_out_transaction.3764842061 Jul 26 05:11:53 PM PDT 24 Jul 26 05:11:55 PM PDT 24 136847237 ps
T2829 /workspace/coverage/default/45.usbdev_stall_priority_over_nak.647801323 Jul 26 05:15:07 PM PDT 24 Jul 26 05:15:08 PM PDT 24 213314005 ps
T2830 /workspace/coverage/default/3.usbdev_min_length_out_transaction.3793820351 Jul 26 05:07:02 PM PDT 24 Jul 26 05:07:03 PM PDT 24 160221331 ps
T2831 /workspace/coverage/default/3.usbdev_device_address.2681373134 Jul 26 05:06:49 PM PDT 24 Jul 26 05:07:33 PM PDT 24 18980084666 ps
T2832 /workspace/coverage/default/44.usbdev_max_length_out_transaction.604403791 Jul 26 05:14:56 PM PDT 24 Jul 26 05:14:57 PM PDT 24 242320673 ps
T2833 /workspace/coverage/default/18.usbdev_timeout_missing_host_handshake.3684555090 Jul 26 05:10:18 PM PDT 24 Jul 26 05:10:37 PM PDT 24 863596170 ps
T2834 /workspace/coverage/default/45.usbdev_pkt_sent.2172165756 Jul 26 05:15:07 PM PDT 24 Jul 26 05:15:08 PM PDT 24 183886559 ps
T2835 /workspace/coverage/default/1.usbdev_device_address.4119566775 Jul 26 05:06:14 PM PDT 24 Jul 26 05:07:01 PM PDT 24 20621850796 ps
T2836 /workspace/coverage/default/4.usbdev_min_length_out_transaction.1908564317 Jul 26 05:07:18 PM PDT 24 Jul 26 05:07:19 PM PDT 24 217685864 ps
T2837 /workspace/coverage/default/25.usbdev_pkt_sent.3071424521 Jul 26 05:11:58 PM PDT 24 Jul 26 05:11:59 PM PDT 24 243823322 ps
T2838 /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.3176052293 Jul 26 05:07:01 PM PDT 24 Jul 26 05:07:54 PM PDT 24 6929336339 ps
T2839 /workspace/coverage/default/46.usbdev_endpoint_access.2752696784 Jul 26 05:15:10 PM PDT 24 Jul 26 05:15:13 PM PDT 24 939015725 ps
T2840 /workspace/coverage/default/46.usbdev_stall_trans.1424859059 Jul 26 05:15:13 PM PDT 24 Jul 26 05:15:15 PM PDT 24 166254757 ps
T2841 /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.4056081627 Jul 26 05:07:45 PM PDT 24 Jul 26 05:07:47 PM PDT 24 149924220 ps
T2842 /workspace/coverage/default/0.usbdev_min_length_out_transaction.218543869 Jul 26 05:06:03 PM PDT 24 Jul 26 05:06:04 PM PDT 24 156492751 ps
T2843 /workspace/coverage/default/16.usbdev_timeout_missing_host_handshake.3687004073 Jul 26 05:10:08 PM PDT 24 Jul 26 05:10:32 PM PDT 24 1052248845 ps
T2844 /workspace/coverage/default/46.usbdev_nak_trans.1893025163 Jul 26 05:15:12 PM PDT 24 Jul 26 05:15:14 PM PDT 24 219679586 ps
T2845 /workspace/coverage/default/1.usbdev_freq_loclk.43485915 Jul 26 05:06:16 PM PDT 24 Jul 26 05:08:31 PM PDT 24 88130119477 ps
T2846 /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.550984382 Jul 26 05:10:42 PM PDT 24 Jul 26 05:11:26 PM PDT 24 5407564812 ps
T2847 /workspace/coverage/default/37.usbdev_link_in_err.3896013775 Jul 26 05:13:41 PM PDT 24 Jul 26 05:13:42 PM PDT 24 196843095 ps
T2848 /workspace/coverage/default/46.usbdev_link_resume.640474785 Jul 26 05:15:12 PM PDT 24 Jul 26 05:15:41 PM PDT 24 23325811643 ps
T2849 /workspace/coverage/default/49.usbdev_streaming_out.2751442019 Jul 26 05:15:38 PM PDT 24 Jul 26 05:16:21 PM PDT 24 5790541750 ps
T2850 /workspace/coverage/default/24.usbdev_data_toggle_clear.618539663 Jul 26 05:11:24 PM PDT 24 Jul 26 05:11:26 PM PDT 24 356450819 ps
T202 /workspace/coverage/default/1.usbdev_sec_cm.4036663106 Jul 26 05:06:32 PM PDT 24 Jul 26 05:06:33 PM PDT 24 313661380 ps
T2851 /workspace/coverage/default/30.usbdev_setup_stage.355934802 Jul 26 05:12:41 PM PDT 24 Jul 26 05:12:42 PM PDT 24 154190897 ps
T2852 /workspace/coverage/default/47.usbdev_invalid_sync.2054469667 Jul 26 05:15:16 PM PDT 24 Jul 26 05:16:10 PM PDT 24 7059412423 ps
T2853 /workspace/coverage/default/38.usbdev_phy_pins_sense.2908425907 Jul 26 05:13:51 PM PDT 24 Jul 26 05:13:52 PM PDT 24 67384076 ps
T2854 /workspace/coverage/default/1.usbdev_aon_wake_disconnect.1107783837 Jul 26 05:06:15 PM PDT 24 Jul 26 05:06:21 PM PDT 24 4073665902 ps
T2855 /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.3176336760 Jul 26 05:13:49 PM PDT 24 Jul 26 05:13:50 PM PDT 24 143135924 ps
T2856 /workspace/coverage/default/20.usbdev_aon_wake_disconnect.2496752555 Jul 26 05:10:44 PM PDT 24 Jul 26 05:10:50 PM PDT 24 3421519632 ps
T2857 /workspace/coverage/default/39.usbdev_device_address.3376211746 Jul 26 05:14:03 PM PDT 24 Jul 26 05:14:53 PM PDT 24 21154318746 ps
T2858 /workspace/coverage/default/21.usbdev_min_length_out_transaction.1678365440 Jul 26 05:10:59 PM PDT 24 Jul 26 05:11:00 PM PDT 24 143267322 ps
T2859 /workspace/coverage/default/36.usbdev_timeout_missing_host_handshake.992657148 Jul 26 05:13:25 PM PDT 24 Jul 26 05:13:27 PM PDT 24 188930040 ps
T2860 /workspace/coverage/default/9.usbdev_low_speed_traffic.990986855 Jul 26 05:08:28 PM PDT 24 Jul 26 05:09:07 PM PDT 24 5082746993 ps
T2861 /workspace/coverage/default/49.usbdev_enable.2757326343 Jul 26 05:15:31 PM PDT 24 Jul 26 05:15:32 PM PDT 24 32100309 ps
T2862 /workspace/coverage/default/11.usbdev_random_length_in_transaction.1753686359 Jul 26 05:09:07 PM PDT 24 Jul 26 05:09:09 PM PDT 24 271386160 ps
T2863 /workspace/coverage/default/24.usbdev_link_suspend.2883605136 Jul 26 05:11:26 PM PDT 24 Jul 26 05:11:31 PM PDT 24 3309782093 ps
T2864 /workspace/coverage/default/41.usbdev_disable_endpoint.4071850566 Jul 26 05:14:18 PM PDT 24 Jul 26 05:14:19 PM PDT 24 382297316 ps
T2865 /workspace/coverage/default/34.usbdev_disable_endpoint.2508823087 Jul 26 05:13:13 PM PDT 24 Jul 26 05:13:15 PM PDT 24 424053834 ps
T188 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.991371102 Jul 26 04:57:07 PM PDT 24 Jul 26 04:57:09 PM PDT 24 89564444 ps
T213 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1568223187 Jul 26 04:57:21 PM PDT 24 Jul 26 04:57:22 PM PDT 24 45865308 ps
T191 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.4015204993 Jul 26 04:57:21 PM PDT 24 Jul 26 04:57:23 PM PDT 24 263639646 ps
T192 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1897987736 Jul 26 04:56:57 PM PDT 24 Jul 26 04:56:58 PM PDT 24 241884739 ps
T214 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1426801731 Jul 26 04:57:16 PM PDT 24 Jul 26 04:57:17 PM PDT 24 85033118 ps
T193 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3041958533 Jul 26 04:57:14 PM PDT 24 Jul 26 04:57:16 PM PDT 24 163831715 ps
T197 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3658234500 Jul 26 04:57:25 PM PDT 24 Jul 26 04:57:26 PM PDT 24 37735134 ps
T189 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1879088066 Jul 26 04:57:31 PM PDT 24 Jul 26 04:57:32 PM PDT 24 88599338 ps
T199 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.3412536736 Jul 26 04:57:07 PM PDT 24 Jul 26 04:57:08 PM PDT 24 36145577 ps
T198 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3762192004 Jul 26 04:56:58 PM PDT 24 Jul 26 04:56:59 PM PDT 24 47965775 ps
T240 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.4002348622 Jul 26 04:56:58 PM PDT 24 Jul 26 04:56:59 PM PDT 24 97675642 ps
T190 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3504500594 Jul 26 04:57:06 PM PDT 24 Jul 26 04:57:07 PM PDT 24 101746317 ps
T210 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.183732053 Jul 26 04:57:05 PM PDT 24 Jul 26 04:57:11 PM PDT 24 1004909292 ps
T254 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3895168935 Jul 26 04:57:23 PM PDT 24 Jul 26 04:57:25 PM PDT 24 251660223 ps
T282 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.52296893 Jul 26 04:57:06 PM PDT 24 Jul 26 04:57:06 PM PDT 24 31073749 ps
T200 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.4167882278 Jul 26 04:57:33 PM PDT 24 Jul 26 04:57:34 PM PDT 24 76528885 ps
T255 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.998752787 Jul 26 04:57:29 PM PDT 24 Jul 26 04:57:30 PM PDT 24 129959969 ps
T265 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1575953128 Jul 26 04:57:14 PM PDT 24 Jul 26 04:57:15 PM PDT 24 54124464 ps
T256 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1794453074 Jul 26 04:57:23 PM PDT 24 Jul 26 04:57:24 PM PDT 24 52474398 ps
T283 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.49267332 Jul 26 04:57:17 PM PDT 24 Jul 26 04:57:18 PM PDT 24 37273745 ps
T241 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2793247742 Jul 26 04:57:36 PM PDT 24 Jul 26 04:57:37 PM PDT 24 47303600 ps
T286 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1018502944 Jul 26 04:57:23 PM PDT 24 Jul 26 04:57:24 PM PDT 24 49087579 ps
T2866 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2591878326 Jul 26 04:56:55 PM PDT 24 Jul 26 04:56:57 PM PDT 24 81992983 ps
T284 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.4158942881 Jul 26 04:57:36 PM PDT 24 Jul 26 04:57:37 PM PDT 24 85643428 ps
T288 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.3755522305 Jul 26 04:57:33 PM PDT 24 Jul 26 04:57:33 PM PDT 24 57267687 ps
T211 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1889985711 Jul 26 04:57:01 PM PDT 24 Jul 26 04:57:06 PM PDT 24 741092958 ps
T212 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.733758748 Jul 26 04:57:23 PM PDT 24 Jul 26 04:57:28 PM PDT 24 806227191 ps
T266 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1822343950 Jul 26 04:57:26 PM PDT 24 Jul 26 04:57:27 PM PDT 24 45510034 ps
T219 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2860752546 Jul 26 04:57:19 PM PDT 24 Jul 26 04:57:21 PM PDT 24 72352661 ps
T220 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2380695321 Jul 26 04:57:11 PM PDT 24 Jul 26 04:57:14 PM PDT 24 192673673 ps
T221 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.4083906560 Jul 26 04:57:25 PM PDT 24 Jul 26 04:57:28 PM PDT 24 347111229 ps
T229 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2260771728 Jul 26 04:56:57 PM PDT 24 Jul 26 04:57:02 PM PDT 24 890092066 ps
T285 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2349300847 Jul 26 04:57:23 PM PDT 24 Jul 26 04:57:24 PM PDT 24 40804509 ps
T230 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3914328936 Jul 26 04:57:16 PM PDT 24 Jul 26 04:57:20 PM PDT 24 505898896 ps
T257 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2672557643 Jul 26 04:57:00 PM PDT 24 Jul 26 04:57:01 PM PDT 24 61230749 ps
T2867 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1042929108 Jul 26 04:57:14 PM PDT 24 Jul 26 04:57:16 PM PDT 24 99505019 ps
T223 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2838131782 Jul 26 04:57:21 PM PDT 24 Jul 26 04:57:23 PM PDT 24 176661903 ps
T222 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3836027955 Jul 26 04:57:23 PM PDT 24 Jul 26 04:57:26 PM PDT 24 256954636 ps
T261 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2731963792 Jul 26 04:57:09 PM PDT 24 Jul 26 04:57:10 PM PDT 24 120777065 ps
T242 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3538169976 Jul 26 04:56:57 PM PDT 24 Jul 26 04:56:58 PM PDT 24 118933224 ps
T243 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.97346424 Jul 26 04:57:11 PM PDT 24 Jul 26 04:57:12 PM PDT 24 100151193 ps
T287 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.213021609 Jul 26 04:57:28 PM PDT 24 Jul 26 04:57:29 PM PDT 24 39835433 ps
T262 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2501152975 Jul 26 04:57:11 PM PDT 24 Jul 26 04:57:12 PM PDT 24 75948735 ps
T2868 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3898145930 Jul 26 04:57:51 PM PDT 24 Jul 26 04:57:51 PM PDT 24 70758093 ps
T2869 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.484680810 Jul 26 04:56:58 PM PDT 24 Jul 26 04:57:01 PM PDT 24 383930130 ps
T231 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.586532441 Jul 26 04:57:18 PM PDT 24 Jul 26 04:57:23 PM PDT 24 1201367027 ps
T2870 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.515492443 Jul 26 04:57:17 PM PDT 24 Jul 26 04:57:17 PM PDT 24 89925286 ps
T2871 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2498173289 Jul 26 04:57:36 PM PDT 24 Jul 26 04:57:37 PM PDT 24 38178293 ps
T297 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.4231355092 Jul 26 04:57:22 PM PDT 24 Jul 26 04:57:27 PM PDT 24 805606737 ps
T244 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1492241248 Jul 26 04:57:26 PM PDT 24 Jul 26 04:57:27 PM PDT 24 63870330 ps
T2872 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2284090113 Jul 26 04:57:08 PM PDT 24 Jul 26 04:57:09 PM PDT 24 82739031 ps
T2873 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1706626803 Jul 26 04:57:20 PM PDT 24 Jul 26 04:57:21 PM PDT 24 54281899 ps
T245 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1900267135 Jul 26 04:56:58 PM PDT 24 Jul 26 04:56:59 PM PDT 24 127305071 ps
T2874 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1851286785 Jul 26 04:57:17 PM PDT 24 Jul 26 04:57:19 PM PDT 24 89123441 ps
T2875 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3972857150 Jul 26 04:57:25 PM PDT 24 Jul 26 04:57:26 PM PDT 24 39407938 ps
T224 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1448574163 Jul 26 04:57:22 PM PDT 24 Jul 26 04:57:25 PM PDT 24 268689519 ps
T2876 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1181649330 Jul 26 04:57:16 PM PDT 24 Jul 26 04:57:17 PM PDT 24 72849197 ps
T246 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2717016419 Jul 26 04:56:58 PM PDT 24 Jul 26 04:56:59 PM PDT 24 63336092 ps
T2877 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.887962398 Jul 26 04:57:10 PM PDT 24 Jul 26 04:57:11 PM PDT 24 136788442 ps
T2878 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2890906367 Jul 26 04:57:30 PM PDT 24 Jul 26 04:57:31 PM PDT 24 124913898 ps
T2879 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2068115531 Jul 26 04:57:27 PM PDT 24 Jul 26 04:57:28 PM PDT 24 71437352 ps
T2880 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3324395302 Jul 26 04:57:16 PM PDT 24 Jul 26 04:57:17 PM PDT 24 103006880 ps
T2881 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.2821113616 Jul 26 04:57:16 PM PDT 24 Jul 26 04:57:17 PM PDT 24 71297758 ps
T2882 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3024712501 Jul 26 04:57:19 PM PDT 24 Jul 26 04:57:21 PM PDT 24 132109667 ps
T2883 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.4284618417 Jul 26 04:57:23 PM PDT 24 Jul 26 04:57:24 PM PDT 24 61081892 ps
T2884 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.4126807618 Jul 26 04:57:00 PM PDT 24 Jul 26 04:57:00 PM PDT 24 81497486 ps
T225 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.481546731 Jul 26 04:57:06 PM PDT 24 Jul 26 04:57:08 PM PDT 24 99566468 ps
T247 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2998384271 Jul 26 04:57:11 PM PDT 24 Jul 26 04:57:12 PM PDT 24 60752943 ps
T2885 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3415773902 Jul 26 04:56:58 PM PDT 24 Jul 26 04:57:00 PM PDT 24 80712091 ps
T226 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2567443639 Jul 26 04:57:18 PM PDT 24 Jul 26 04:57:20 PM PDT 24 201180715 ps
T2886 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2218530264 Jul 26 04:57:16 PM PDT 24 Jul 26 04:57:18 PM PDT 24 113662145 ps
T2887 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.512282500 Jul 26 04:57:09 PM PDT 24 Jul 26 04:57:12 PM PDT 24 208959025 ps
T2888 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3167312614 Jul 26 04:57:09 PM PDT 24 Jul 26 04:57:11 PM PDT 24 146661525 ps
T248 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1872749111 Jul 26 04:57:00 PM PDT 24 Jul 26 04:57:01 PM PDT 24 58718394 ps
T2889 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.645649875 Jul 26 04:57:20 PM PDT 24 Jul 26 04:57:21 PM PDT 24 87340205 ps
T2890 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3200898333 Jul 26 04:57:24 PM PDT 24 Jul 26 04:57:27 PM PDT 24 90989934 ps
T263 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3413363899 Jul 26 04:57:19 PM PDT 24 Jul 26 04:57:22 PM PDT 24 462021674 ps
T2891 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3537178631 Jul 26 04:57:26 PM PDT 24 Jul 26 04:57:27 PM PDT 24 51152048 ps
T2892 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2126058909 Jul 26 04:57:00 PM PDT 24 Jul 26 04:57:01 PM PDT 24 50126403 ps
T2893 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3429024525 Jul 26 04:57:23 PM PDT 24 Jul 26 04:57:25 PM PDT 24 190155847 ps
T2894 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1257292885 Jul 26 04:57:26 PM PDT 24 Jul 26 04:57:28 PM PDT 24 161318482 ps
T253 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.976342199 Jul 26 04:57:11 PM PDT 24 Jul 26 04:57:12 PM PDT 24 76578173 ps
T2895 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3292190010 Jul 26 04:57:16 PM PDT 24 Jul 26 04:57:21 PM PDT 24 171066769 ps
T2896 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2138658362 Jul 26 04:56:59 PM PDT 24 Jul 26 04:57:01 PM PDT 24 62193997 ps
T2897 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.657447802 Jul 26 04:56:59 PM PDT 24 Jul 26 04:57:02 PM PDT 24 256482181 ps
T2898 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.971131695 Jul 26 04:57:26 PM PDT 24 Jul 26 04:57:28 PM PDT 24 242797028 ps
T2899 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3784803956 Jul 26 04:57:41 PM PDT 24 Jul 26 04:57:41 PM PDT 24 45705531 ps
T2900 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.934191822 Jul 26 04:57:20 PM PDT 24 Jul 26 04:57:25 PM PDT 24 639988427 ps
T2901 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1744199015 Jul 26 04:57:17 PM PDT 24 Jul 26 04:57:20 PM PDT 24 117402760 ps
T264 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.4209054490 Jul 26 04:57:20 PM PDT 24 Jul 26 04:57:22 PM PDT 24 396868496 ps
T2902 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.544524448 Jul 26 04:57:31 PM PDT 24 Jul 26 04:57:31 PM PDT 24 53363224 ps
T2903 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.417816705 Jul 26 04:56:56 PM PDT 24 Jul 26 04:56:58 PM PDT 24 125095791 ps
T293 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3667972664 Jul 26 04:57:20 PM PDT 24 Jul 26 04:57:24 PM PDT 24 530980826 ps
T249 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3421711814 Jul 26 04:57:14 PM PDT 24 Jul 26 04:57:15 PM PDT 24 78296398 ps
T2904 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3201864227 Jul 26 04:57:01 PM PDT 24 Jul 26 04:57:03 PM PDT 24 106548247 ps
T267 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2968313860 Jul 26 04:56:59 PM PDT 24 Jul 26 04:57:04 PM PDT 24 873718528 ps
T2905 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3373695954 Jul 26 04:57:23 PM PDT 24 Jul 26 04:57:24 PM PDT 24 49121466 ps
T2906 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.189996110 Jul 26 04:57:23 PM PDT 24 Jul 26 04:57:24 PM PDT 24 103531957 ps
T2907 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.150060506 Jul 26 04:57:08 PM PDT 24 Jul 26 04:57:17 PM PDT 24 2475599356 ps
T2908 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2466863148 Jul 26 04:57:14 PM PDT 24 Jul 26 04:57:15 PM PDT 24 71447803 ps
T2909 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2533168148 Jul 26 04:57:38 PM PDT 24 Jul 26 04:57:39 PM PDT 24 56983270 ps
T2910 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3146747668 Jul 26 04:57:08 PM PDT 24 Jul 26 04:57:09 PM PDT 24 91540249 ps
T2911 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3435544671 Jul 26 04:56:58 PM PDT 24 Jul 26 04:57:00 PM PDT 24 117555227 ps
T2912 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.4252800322 Jul 26 04:56:59 PM PDT 24 Jul 26 04:57:04 PM PDT 24 1025978814 ps
T2913 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.4251019564 Jul 26 04:56:59 PM PDT 24 Jul 26 04:57:00 PM PDT 24 42804158 ps
T250 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2498738062 Jul 26 04:57:09 PM PDT 24 Jul 26 04:57:12 PM PDT 24 194599533 ps
T2914 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2720990433 Jul 26 04:57:16 PM PDT 24 Jul 26 04:57:17 PM PDT 24 100760641 ps
T2915 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1161112520 Jul 26 04:57:05 PM PDT 24 Jul 26 04:57:08 PM PDT 24 94901147 ps
T2916 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.123693370 Jul 26 04:56:57 PM PDT 24 Jul 26 04:57:01 PM PDT 24 487311575 ps
T2917 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2414610753 Jul 26 04:57:16 PM PDT 24 Jul 26 04:57:18 PM PDT 24 104348826 ps
T2918 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2065016458 Jul 26 04:57:15 PM PDT 24 Jul 26 04:57:18 PM PDT 24 256721456 ps
T2919 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1188006293 Jul 26 04:57:20 PM PDT 24 Jul 26 04:57:21 PM PDT 24 93549799 ps
T2920 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1678563592 Jul 26 04:57:04 PM PDT 24 Jul 26 04:57:06 PM PDT 24 184945970 ps
T2921 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2834301257 Jul 26 04:57:08 PM PDT 24 Jul 26 04:57:09 PM PDT 24 58188258 ps
T2922 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3734954827 Jul 26 04:57:11 PM PDT 24 Jul 26 04:57:12 PM PDT 24 177566132 ps
T291 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3474764353 Jul 26 04:57:34 PM PDT 24 Jul 26 04:57:39 PM PDT 24 1082491804 ps
T2923 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1581709082 Jul 26 04:57:33 PM PDT 24 Jul 26 04:57:34 PM PDT 24 99194982 ps
T2924 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3875036157 Jul 26 04:57:04 PM PDT 24 Jul 26 04:57:05 PM PDT 24 47609984 ps
T2925 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.2949957641 Jul 26 04:57:30 PM PDT 24 Jul 26 04:57:31 PM PDT 24 33930435 ps
T2926 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2271736070 Jul 26 04:57:38 PM PDT 24 Jul 26 04:57:39 PM PDT 24 34157668 ps
T292 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3450514046 Jul 26 04:57:01 PM PDT 24 Jul 26 04:57:03 PM PDT 24 352843071 ps
T2927 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.930264640 Jul 26 04:57:20 PM PDT 24 Jul 26 04:57:21 PM PDT 24 89866249 ps
T2928 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2158208261 Jul 26 04:57:24 PM PDT 24 Jul 26 04:57:26 PM PDT 24 102151667 ps
T2929 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.828658232 Jul 26 04:57:21 PM PDT 24 Jul 26 04:57:22 PM PDT 24 49455060 ps
T2930 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.932202359 Jul 26 04:57:16 PM PDT 24 Jul 26 04:57:18 PM PDT 24 175823913 ps
T251 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1386893424 Jul 26 04:57:26 PM PDT 24 Jul 26 04:57:27 PM PDT 24 57168735 ps
T2931 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1564836688 Jul 26 04:57:46 PM PDT 24 Jul 26 04:57:47 PM PDT 24 109827029 ps
T2932 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1715864164 Jul 26 04:57:18 PM PDT 24 Jul 26 04:57:20 PM PDT 24 71105060 ps
T2933 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2816173529 Jul 26 04:57:26 PM PDT 24 Jul 26 04:57:27 PM PDT 24 51123346 ps
T2934 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.4025346934 Jul 26 04:57:12 PM PDT 24 Jul 26 04:57:14 PM PDT 24 94759463 ps
T2935 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.761205709 Jul 26 04:57:11 PM PDT 24 Jul 26 04:57:12 PM PDT 24 35251850 ps
T252 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2731344244 Jul 26 04:57:11 PM PDT 24 Jul 26 04:57:12 PM PDT 24 126873260 ps
T2936 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2217291595 Jul 26 04:56:56 PM PDT 24 Jul 26 04:56:58 PM PDT 24 95251071 ps
T2937 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.3146669176 Jul 26 04:57:34 PM PDT 24 Jul 26 04:57:35 PM PDT 24 41241102 ps
T2938 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2252977122 Jul 26 04:57:29 PM PDT 24 Jul 26 04:57:30 PM PDT 24 36623702 ps
T2939 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2345650691 Jul 26 04:56:58 PM PDT 24 Jul 26 04:57:07 PM PDT 24 2554854776 ps
T295 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.681599191 Jul 26 04:57:00 PM PDT 24 Jul 26 04:57:03 PM PDT 24 525674154 ps
T2940 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1391325455 Jul 26 04:57:10 PM PDT 24 Jul 26 04:57:13 PM PDT 24 192174527 ps
T2941 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1289262438 Jul 26 04:57:38 PM PDT 24 Jul 26 04:57:40 PM PDT 24 101471956 ps
T2942 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.617648384 Jul 26 04:57:21 PM PDT 24 Jul 26 04:57:21 PM PDT 24 49640269 ps
T2943 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3858541720 Jul 26 04:57:27 PM PDT 24 Jul 26 04:57:28 PM PDT 24 33227306 ps
T2944 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.274683753 Jul 26 04:57:24 PM PDT 24 Jul 26 04:57:29 PM PDT 24 1086087932 ps
T2945 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2098229070 Jul 26 04:57:08 PM PDT 24 Jul 26 04:57:10 PM PDT 24 88264950 ps
T296 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1877684224 Jul 26 04:57:11 PM PDT 24 Jul 26 04:57:15 PM PDT 24 907823119 ps
T2946 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3246530040 Jul 26 04:57:06 PM PDT 24 Jul 26 04:57:08 PM PDT 24 69935730 ps
T2947 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1353498511 Jul 26 04:57:14 PM PDT 24 Jul 26 04:57:16 PM PDT 24 86421347 ps
T2948 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1538998412 Jul 26 04:57:11 PM PDT 24 Jul 26 04:57:14 PM PDT 24 139883090 ps
T2949 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1042010665 Jul 26 04:57:17 PM PDT 24 Jul 26 04:57:18 PM PDT 24 35184681 ps
T2950 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.1199088533 Jul 26 04:57:26 PM PDT 24 Jul 26 04:57:27 PM PDT 24 59780243 ps
T2951 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2972783524 Jul 26 04:57:06 PM PDT 24 Jul 26 04:57:07 PM PDT 24 58494677 ps
T2952 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2981175068 Jul 26 04:56:59 PM PDT 24 Jul 26 04:57:02 PM PDT 24 82921882 ps
T2953 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2743328640 Jul 26 04:57:35 PM PDT 24 Jul 26 04:57:37 PM PDT 24 112473851 ps
T2954 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.251923945 Jul 26 04:57:10 PM PDT 24 Jul 26 04:57:11 PM PDT 24 87665832 ps
T2955 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1160470632 Jul 26 04:56:57 PM PDT 24 Jul 26 04:56:58 PM PDT 24 144332322 ps
T2956 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1118955467 Jul 26 04:56:58 PM PDT 24 Jul 26 04:57:05 PM PDT 24 708511741 ps
T2957 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2071043792 Jul 26 04:56:57 PM PDT 24 Jul 26 04:57:00 PM PDT 24 831632880 ps
T2958 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3730925709 Jul 26 04:57:26 PM PDT 24 Jul 26 04:57:27 PM PDT 24 47689563 ps
T2959 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2184148286 Jul 26 04:57:22 PM PDT 24 Jul 26 04:57:23 PM PDT 24 77012402 ps
T2960 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1316930376 Jul 26 04:57:22 PM PDT 24 Jul 26 04:57:24 PM PDT 24 246554524 ps
T2961 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.1301688743 Jul 26 04:57:24 PM PDT 24 Jul 26 04:57:25 PM PDT 24 107942875 ps
T2962 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.4072012734 Jul 26 04:57:27 PM PDT 24 Jul 26 04:57:28 PM PDT 24 51777493 ps
T2963 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.288127705 Jul 26 04:57:08 PM PDT 24 Jul 26 04:57:09 PM PDT 24 64962995 ps
T2964 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.1670011369 Jul 26 04:57:18 PM PDT 24 Jul 26 04:57:21 PM PDT 24 333559152 ps
T2965 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.773777370 Jul 26 04:56:57 PM PDT 24 Jul 26 04:56:59 PM PDT 24 243242827 ps
T2966 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2109432454 Jul 26 04:57:16 PM PDT 24 Jul 26 04:57:18 PM PDT 24 68810551 ps
T2967 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.171284065 Jul 26 04:57:25 PM PDT 24 Jul 26 04:57:26 PM PDT 24 78113128 ps
T2968 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.805546382 Jul 26 04:57:25 PM PDT 24 Jul 26 04:57:26 PM PDT 24 83665186 ps
T294 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3613037130 Jul 26 04:57:17 PM PDT 24 Jul 26 04:57:20 PM PDT 24 388184655 ps
T2969 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.656554589 Jul 26 04:57:26 PM PDT 24 Jul 26 04:57:27 PM PDT 24 32299102 ps
T2970 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3360481238 Jul 26 04:57:18 PM PDT 24 Jul 26 04:57:21 PM PDT 24 332884159 ps
T2971 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1648445203 Jul 26 04:57:07 PM PDT 24 Jul 26 04:57:10 PM PDT 24 97432615 ps
T2972 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2754857356 Jul 26 04:57:10 PM PDT 24 Jul 26 04:57:12 PM PDT 24 116602406 ps
T2973 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.289363564 Jul 26 04:57:06 PM PDT 24 Jul 26 04:57:07 PM PDT 24 59542935 ps
T2974 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.312458122 Jul 26 04:56:59 PM PDT 24 Jul 26 04:57:04 PM PDT 24 926744278 ps
T2975 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.4252101913 Jul 26 04:57:16 PM PDT 24 Jul 26 04:57:18 PM PDT 24 174561166 ps

Test location /workspace/coverage/default/1.usbdev_rand_suspends.3539818821
Short name T1
Test name
Test status
Simulation time 10944804314 ps
CPU time 71.6 seconds
Started Jul 26 05:06:31 PM PDT 24
Finished Jul 26 05:07:43 PM PDT 24
Peak memory 217524 kb
Host smart-33aa8024-a1b6-4890-ba31-8fd233895302
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539818821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.3539818821
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/16.usbdev_device_address.3670158249
Short name T16
Test name
Test status
Simulation time 10158449228 ps
CPU time 22.95 seconds
Started Jul 26 05:09:59 PM PDT 24
Finished Jul 26 05:10:22 PM PDT 24
Peak memory 207392 kb
Host smart-16887630-901f-4eb0-a2a8-e57f0b4ef9a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36701
58249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.3670158249
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3658234500
Short name T197
Test name
Test status
Simulation time 37735134 ps
CPU time 0.73 seconds
Started Jul 26 04:57:25 PM PDT 24
Finished Jul 26 04:57:26 PM PDT 24
Peak memory 205888 kb
Host smart-ba7ae8ca-af6f-4ada-9def-21c7a75b3e0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3658234500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.3658234500
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.537381784
Short name T8
Test name
Test status
Simulation time 3761150141 ps
CPU time 6.09 seconds
Started Jul 26 05:07:36 PM PDT 24
Finished Jul 26 05:07:42 PM PDT 24
Peak memory 207344 kb
Host smart-b80edbfa-3088-48b5-821b-4c975f1c29b5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537381784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon
_wake_disconnect.537381784
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3504500594
Short name T190
Test name
Test status
Simulation time 101746317 ps
CPU time 1.19 seconds
Started Jul 26 04:57:06 PM PDT 24
Finished Jul 26 04:57:07 PM PDT 24
Peak memory 214396 kb
Host smart-411ea98f-abbb-44b6-b58e-ea2a458b4af8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504500594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.3504500594
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.2126527187
Short name T40
Test name
Test status
Simulation time 9327215433 ps
CPU time 285.53 seconds
Started Jul 26 05:06:14 PM PDT 24
Finished Jul 26 05:10:59 PM PDT 24
Peak memory 215396 kb
Host smart-afb8f78f-8df7-462f-acc0-50f0c8b19b5a
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126527187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.2126527187
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.4009004206
Short name T96
Test name
Test status
Simulation time 218406148 ps
CPU time 0.98 seconds
Started Jul 26 05:09:03 PM PDT 24
Finished Jul 26 05:09:04 PM PDT 24
Peak memory 207128 kb
Host smart-0a5b9be1-22e5-495e-a474-4a6a04826e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40090
04206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.4009004206
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.1315989600
Short name T29
Test name
Test status
Simulation time 181258543 ps
CPU time 0.93 seconds
Started Jul 26 05:14:18 PM PDT 24
Finished Jul 26 05:14:20 PM PDT 24
Peak memory 207120 kb
Host smart-bb13995f-b8da-4c25-864b-371214e0af89
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1315989600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.1315989600
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.3163940297
Short name T43
Test name
Test status
Simulation time 147730596 ps
CPU time 0.84 seconds
Started Jul 26 05:10:44 PM PDT 24
Finished Jul 26 05:10:45 PM PDT 24
Peak memory 207028 kb
Host smart-3ccce61d-b93f-47dd-80de-732fcca914c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31639
40297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.3163940297
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.1580832562
Short name T139
Test name
Test status
Simulation time 177451078 ps
CPU time 0.84 seconds
Started Jul 26 05:11:14 PM PDT 24
Finished Jul 26 05:11:15 PM PDT 24
Peak memory 207068 kb
Host smart-4a8b25f1-c490-4f9e-b4c6-f0baef8277f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15808
32562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.1580832562
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.2952987895
Short name T84
Test name
Test status
Simulation time 1646109410 ps
CPU time 3.88 seconds
Started Jul 26 05:37:34 PM PDT 24
Finished Jul 26 05:37:38 PM PDT 24
Peak memory 207340 kb
Host smart-02d5f382-3815-433d-acbf-43cc9f41e485
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2952987895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.2952987895
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.518534391
Short name T26
Test name
Test status
Simulation time 41045938 ps
CPU time 0.72 seconds
Started Jul 26 05:06:07 PM PDT 24
Finished Jul 26 05:06:08 PM PDT 24
Peak memory 207100 kb
Host smart-5805658d-3e99-4d12-bc88-4c5b5aade01b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51853
4391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.518534391
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.49267332
Short name T283
Test name
Test status
Simulation time 37273745 ps
CPU time 0.7 seconds
Started Jul 26 04:57:17 PM PDT 24
Finished Jul 26 04:57:18 PM PDT 24
Peak memory 206056 kb
Host smart-51673654-c342-4c30-a028-96eb73d45d6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=49267332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.49267332
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.183732053
Short name T210
Test name
Test status
Simulation time 1004909292 ps
CPU time 5.05 seconds
Started Jul 26 04:57:05 PM PDT 24
Finished Jul 26 04:57:11 PM PDT 24
Peak memory 206284 kb
Host smart-eb834051-3fb7-45fa-9016-bea56d233c60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=183732053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.183732053
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.4046308941
Short name T45
Test name
Test status
Simulation time 23324793484 ps
CPU time 28.54 seconds
Started Jul 26 05:08:52 PM PDT 24
Finished Jul 26 05:09:21 PM PDT 24
Peak memory 207248 kb
Host smart-746757be-906a-41d4-ac5a-fb8ac4341df3
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046308941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_a
on_wake_resume.4046308941
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.4105917487
Short name T82
Test name
Test status
Simulation time 303531522 ps
CPU time 1.12 seconds
Started Jul 26 05:06:11 PM PDT 24
Finished Jul 26 05:06:13 PM PDT 24
Peak memory 207052 kb
Host smart-1a6eb306-0166-4544-bae7-a6c212305a93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41059
17487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.4105917487
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.2091035607
Short name T187
Test name
Test status
Simulation time 282564057 ps
CPU time 1.12 seconds
Started Jul 26 05:06:14 PM PDT 24
Finished Jul 26 05:06:16 PM PDT 24
Peak memory 222816 kb
Host smart-9f4d2f34-6097-4c0d-a391-5e7cb6ea5215
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2091035607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.2091035607
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.4114640456
Short name T48
Test name
Test status
Simulation time 20154803707 ps
CPU time 23.64 seconds
Started Jul 26 05:06:10 PM PDT 24
Finished Jul 26 05:06:34 PM PDT 24
Peak memory 207232 kb
Host smart-cb3d7897-e4f0-4d87-870e-790c470cde0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41146
40456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.4114640456
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.936707989
Short name T464
Test name
Test status
Simulation time 38210448 ps
CPU time 0.65 seconds
Started Jul 26 05:10:24 PM PDT 24
Finished Jul 26 05:10:25 PM PDT 24
Peak memory 207168 kb
Host smart-f7c917c9-9e42-49a6-88c5-3f1590df2f02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=936707989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.936707989
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.4002348622
Short name T240
Test name
Test status
Simulation time 97675642 ps
CPU time 0.95 seconds
Started Jul 26 04:56:58 PM PDT 24
Finished Jul 26 04:56:59 PM PDT 24
Peak memory 206028 kb
Host smart-07bf6f94-d1c4-4a82-bfc4-481da8fb5be5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4002348622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.4002348622
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/default/49.usbdev_device_address.99462715
Short name T162
Test name
Test status
Simulation time 21637433561 ps
CPU time 41.85 seconds
Started Jul 26 05:15:37 PM PDT 24
Finished Jul 26 05:16:19 PM PDT 24
Peak memory 207312 kb
Host smart-7a0da4b0-cfad-4692-b406-c7d3ea40406d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99462
715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.99462715
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.481546731
Short name T225
Test name
Test status
Simulation time 99566468 ps
CPU time 2.54 seconds
Started Jul 26 04:57:06 PM PDT 24
Finished Jul 26 04:57:08 PM PDT 24
Peak memory 222556 kb
Host smart-153277f6-3c62-4aaf-b09d-354a7caf3877
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=481546731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.481546731
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.213021609
Short name T287
Test name
Test status
Simulation time 39835433 ps
CPU time 0.72 seconds
Started Jul 26 04:57:28 PM PDT 24
Finished Jul 26 04:57:29 PM PDT 24
Peak memory 205944 kb
Host smart-8f4fc7d6-cc1b-4f8d-8b33-e4ad5c446464
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=213021609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.213021609
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.770153738
Short name T51
Test name
Test status
Simulation time 254137911 ps
CPU time 1.01 seconds
Started Jul 26 05:11:57 PM PDT 24
Finished Jul 26 05:11:58 PM PDT 24
Peak memory 207020 kb
Host smart-430481a3-6f5d-4ed3-bf4c-de0cced3692f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77015
3738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.770153738
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.92884203
Short name T74
Test name
Test status
Simulation time 135989914 ps
CPU time 0.77 seconds
Started Jul 26 05:06:04 PM PDT 24
Finished Jul 26 05:06:05 PM PDT 24
Peak memory 207092 kb
Host smart-c4970179-8b9f-400a-9aa9-326bf09430d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92884
203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.92884203
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.2743146113
Short name T73
Test name
Test status
Simulation time 148718572 ps
CPU time 0.84 seconds
Started Jul 26 05:11:28 PM PDT 24
Finished Jul 26 05:11:29 PM PDT 24
Peak memory 207100 kb
Host smart-4ecb511d-af7e-4314-8d96-882c2e546487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27431
46113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.2743146113
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.3358856882
Short name T56
Test name
Test status
Simulation time 448086569 ps
CPU time 1.59 seconds
Started Jul 26 05:06:10 PM PDT 24
Finished Jul 26 05:06:11 PM PDT 24
Peak memory 207204 kb
Host smart-b9dc300c-65e5-43cb-bc61-ea2dc7894264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33588
56882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.3358856882
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/29.usbdev_device_address.1007776328
Short name T275
Test name
Test status
Simulation time 8507077142 ps
CPU time 17.69 seconds
Started Jul 26 05:12:24 PM PDT 24
Finished Jul 26 05:12:42 PM PDT 24
Peak memory 207596 kb
Host smart-9e1ed3a4-8653-4644-9557-84b7bde5c73f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10077
76328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.1007776328
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_invalid_sync.3827922127
Short name T4
Test name
Test status
Simulation time 9338019705 ps
CPU time 263.58 seconds
Started Jul 26 05:15:36 PM PDT 24
Finished Jul 26 05:20:00 PM PDT 24
Peak memory 215524 kb
Host smart-23fb66c3-342c-4711-910e-3fe8267ad6f3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3827922127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.3827922127
Directory /workspace/49.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.3149880535
Short name T71
Test name
Test status
Simulation time 527254597 ps
CPU time 1.6 seconds
Started Jul 26 05:06:03 PM PDT 24
Finished Jul 26 05:06:04 PM PDT 24
Peak memory 207012 kb
Host smart-ebc6832a-768e-4c30-be7a-67a2317638dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31498
80535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.3149880535
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3667972664
Short name T293
Test name
Test status
Simulation time 530980826 ps
CPU time 3.07 seconds
Started Jul 26 04:57:20 PM PDT 24
Finished Jul 26 04:57:24 PM PDT 24
Peak memory 206264 kb
Host smart-ad4e2a2a-2fb8-4c10-9ec2-34ebdd8fa621
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3667972664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.3667972664
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.3136354310
Short name T305
Test name
Test status
Simulation time 121191080206 ps
CPU time 193.83 seconds
Started Jul 26 05:06:02 PM PDT 24
Finished Jul 26 05:09:16 PM PDT 24
Peak memory 207296 kb
Host smart-25f34985-6f0b-4398-9558-021cfdfbfd28
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3136354310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.3136354310
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.318371884
Short name T215
Test name
Test status
Simulation time 13344805081 ps
CPU time 15.09 seconds
Started Jul 26 05:07:09 PM PDT 24
Finished Jul 26 05:07:24 PM PDT 24
Peak memory 207312 kb
Host smart-1aaeb7f1-8867-4529-ada4-1cb8001a8059
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=318371884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.318371884
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.3412536736
Short name T199
Test name
Test status
Simulation time 36145577 ps
CPU time 0.72 seconds
Started Jul 26 04:57:07 PM PDT 24
Finished Jul 26 04:57:08 PM PDT 24
Peak memory 205996 kb
Host smart-813391fe-f887-4fd4-9c2c-90f11cbebd0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3412536736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.3412536736
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/default/37.usbdev_device_address.3090099912
Short name T148
Test name
Test status
Simulation time 17398759484 ps
CPU time 45.96 seconds
Started Jul 26 05:13:37 PM PDT 24
Finished Jul 26 05:14:23 PM PDT 24
Peak memory 207272 kb
Host smart-0948cac1-f132-4f22-8f94-565cf284e7c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30900
99912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.3090099912
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.100854187
Short name T99
Test name
Test status
Simulation time 136992629 ps
CPU time 0.87 seconds
Started Jul 26 05:06:04 PM PDT 24
Finished Jul 26 05:06:05 PM PDT 24
Peak memory 207032 kb
Host smart-964c4140-fac1-4546-8bb3-6b4546133188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10085
4187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.100854187
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.230274190
Short name T173
Test name
Test status
Simulation time 10519543525 ps
CPU time 82.62 seconds
Started Jul 26 05:07:01 PM PDT 24
Finished Jul 26 05:08:23 PM PDT 24
Peak memory 217976 kb
Host smart-67ad769c-2b2c-4b1a-ad56-953f6dd87ce8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=230274190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.230274190
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.3465352623
Short name T55
Test name
Test status
Simulation time 255224321 ps
CPU time 1.08 seconds
Started Jul 26 05:06:09 PM PDT 24
Finished Jul 26 05:06:11 PM PDT 24
Peak memory 207212 kb
Host smart-29f7b273-f8bb-4813-8cbe-3d98425f5f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34653
52623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.3465352623
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.2170448012
Short name T41
Test name
Test status
Simulation time 153709901 ps
CPU time 0.84 seconds
Started Jul 26 05:06:53 PM PDT 24
Finished Jul 26 05:06:54 PM PDT 24
Peak memory 207064 kb
Host smart-44f35645-cfb3-4f10-ab84-b67258f61172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21704
48012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.2170448012
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_device_address.1131339248
Short name T169
Test name
Test status
Simulation time 11782944941 ps
CPU time 24.48 seconds
Started Jul 26 05:12:08 PM PDT 24
Finished Jul 26 05:12:32 PM PDT 24
Peak memory 207252 kb
Host smart-a2c16a77-f59a-4f90-8f08-81d1e546e568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11313
39248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.1131339248
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.4083906560
Short name T221
Test name
Test status
Simulation time 347111229 ps
CPU time 3.63 seconds
Started Jul 26 04:57:25 PM PDT 24
Finished Jul 26 04:57:28 PM PDT 24
Peak memory 214568 kb
Host smart-878e8c3c-2f93-4d44-a5dc-e34249dde046
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4083906560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.4083906560
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3450514046
Short name T292
Test name
Test status
Simulation time 352843071 ps
CPU time 2.5 seconds
Started Jul 26 04:57:01 PM PDT 24
Finished Jul 26 04:57:03 PM PDT 24
Peak memory 206384 kb
Host smart-88224caa-8b0a-4ad7-8b31-83107e479e95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3450514046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3450514046
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3413363899
Short name T263
Test name
Test status
Simulation time 462021674 ps
CPU time 2.98 seconds
Started Jul 26 04:57:19 PM PDT 24
Finished Jul 26 04:57:22 PM PDT 24
Peak memory 206276 kb
Host smart-cf591013-1b26-49a5-acc8-03d6fda61ed0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3413363899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.3413363899
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.681599191
Short name T295
Test name
Test status
Simulation time 525674154 ps
CPU time 3.18 seconds
Started Jul 26 04:57:00 PM PDT 24
Finished Jul 26 04:57:03 PM PDT 24
Peak memory 206292 kb
Host smart-4e53bac4-9ac1-4985-8d6f-2fab4a9b2bae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=681599191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.681599191
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.1715287374
Short name T309
Test name
Test status
Simulation time 5132260583 ps
CPU time 46.84 seconds
Started Jul 26 05:06:06 PM PDT 24
Finished Jul 26 05:06:53 PM PDT 24
Peak memory 207304 kb
Host smart-0b9e16b9-b7bd-48f4-972b-d2226586ab35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17152
87374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.1715287374
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.1477422009
Short name T310
Test name
Test status
Simulation time 103102193573 ps
CPU time 190.8 seconds
Started Jul 26 05:06:07 PM PDT 24
Finished Jul 26 05:09:18 PM PDT 24
Peak memory 207248 kb
Host smart-ddb51334-8137-4ff4-8a2a-3bc3544b185e
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1477422009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.1477422009
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.2967900956
Short name T337
Test name
Test status
Simulation time 162036706 ps
CPU time 0.91 seconds
Started Jul 26 05:06:17 PM PDT 24
Finished Jul 26 05:06:18 PM PDT 24
Peak memory 207024 kb
Host smart-e5564f90-2237-43b7-a4a9-f0629b06fd14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29679
00956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.2967900956
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.4154185407
Short name T983
Test name
Test status
Simulation time 191347896 ps
CPU time 0.94 seconds
Started Jul 26 05:09:16 PM PDT 24
Finished Jul 26 05:09:17 PM PDT 24
Peak memory 207088 kb
Host smart-c725637d-5e0c-4479-ad36-ff4edf70366f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41541
85407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.4154185407
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.4121179307
Short name T182
Test name
Test status
Simulation time 23330370822 ps
CPU time 27.68 seconds
Started Jul 26 05:10:53 PM PDT 24
Finished Jul 26 05:11:21 PM PDT 24
Peak memory 207244 kb
Host smart-cc67aa07-bd59-4aa7-85bb-a267cf4d833f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41211
79307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.4121179307
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.3597260544
Short name T64
Test name
Test status
Simulation time 141757665 ps
CPU time 0.83 seconds
Started Jul 26 05:06:13 PM PDT 24
Finished Jul 26 05:06:14 PM PDT 24
Peak memory 207012 kb
Host smart-20c7dabd-2e15-4516-9317-208b89252658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35972
60544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.3597260544
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.3544095450
Short name T863
Test name
Test status
Simulation time 246233391 ps
CPU time 2.12 seconds
Started Jul 26 05:09:16 PM PDT 24
Finished Jul 26 05:09:18 PM PDT 24
Peak memory 207344 kb
Host smart-190e32d4-d85c-4414-941e-a574bf450e0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35440
95450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.3544095450
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.1655016893
Short name T689
Test name
Test status
Simulation time 36197901 ps
CPU time 0.66 seconds
Started Jul 26 05:09:30 PM PDT 24
Finished Jul 26 05:09:31 PM PDT 24
Peak memory 207088 kb
Host smart-fda08fa9-bb8b-480d-abd5-c7591292dab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16550
16893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.1655016893
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.727354991
Short name T53
Test name
Test status
Simulation time 167587570 ps
CPU time 0.86 seconds
Started Jul 26 05:06:06 PM PDT 24
Finished Jul 26 05:06:07 PM PDT 24
Peak memory 207108 kb
Host smart-8cd3b44f-504a-4126-95b5-dd5411c44cd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72735
4991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.727354991
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.2701902440
Short name T67
Test name
Test status
Simulation time 4174955589 ps
CPU time 10.53 seconds
Started Jul 26 05:06:03 PM PDT 24
Finished Jul 26 05:06:14 PM PDT 24
Peak memory 207368 kb
Host smart-669046a7-30d5-4480-bead-0597dd133c11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27019
02440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.2701902440
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.1583020814
Short name T68
Test name
Test status
Simulation time 167868202 ps
CPU time 0.88 seconds
Started Jul 26 05:06:08 PM PDT 24
Finished Jul 26 05:06:09 PM PDT 24
Peak memory 207100 kb
Host smart-e7eb59ff-257c-439d-9eac-744fe5d14a75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15830
20814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.1583020814
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.1160418386
Short name T77
Test name
Test status
Simulation time 162088346 ps
CPU time 0.86 seconds
Started Jul 26 05:06:10 PM PDT 24
Finished Jul 26 05:06:11 PM PDT 24
Peak memory 207208 kb
Host smart-6527045e-3c63-42eb-b82c-3636c0122dfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11604
18386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.1160418386
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.3083310361
Short name T58
Test name
Test status
Simulation time 168131343 ps
CPU time 0.85 seconds
Started Jul 26 05:06:16 PM PDT 24
Finished Jul 26 05:06:17 PM PDT 24
Peak memory 207104 kb
Host smart-57d350f4-f9f0-4167-acec-66788ded2f1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30833
10361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.3083310361
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.1661205221
Short name T599
Test name
Test status
Simulation time 5858905497 ps
CPU time 45.89 seconds
Started Jul 26 05:11:02 PM PDT 24
Finished Jul 26 05:11:48 PM PDT 24
Peak memory 217676 kb
Host smart-8bc318ff-1f2c-4222-ad20-9579bb5c0781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16612
05221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.1661205221
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.3495773694
Short name T135
Test name
Test status
Simulation time 206454989 ps
CPU time 0.98 seconds
Started Jul 26 05:06:08 PM PDT 24
Finished Jul 26 05:06:10 PM PDT 24
Peak memory 207132 kb
Host smart-94604fd9-8b24-4ee5-be48-b164b0f78e72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34957
73694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.3495773694
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.2626346587
Short name T118
Test name
Test status
Simulation time 192123882 ps
CPU time 0.91 seconds
Started Jul 26 05:06:31 PM PDT 24
Finished Jul 26 05:06:32 PM PDT 24
Peak memory 207084 kb
Host smart-2a44cd0b-8dd0-4999-ae8f-9756d4c14140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26263
46587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.2626346587
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.4289795258
Short name T114
Test name
Test status
Simulation time 229201366 ps
CPU time 1.01 seconds
Started Jul 26 05:08:54 PM PDT 24
Finished Jul 26 05:08:55 PM PDT 24
Peak memory 206976 kb
Host smart-ce8c2f95-ba4b-42e4-a079-36d9b591da91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42897
95258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.4289795258
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.3402980107
Short name T137
Test name
Test status
Simulation time 212979595 ps
CPU time 0.97 seconds
Started Jul 26 05:09:06 PM PDT 24
Finished Jul 26 05:09:08 PM PDT 24
Peak memory 207080 kb
Host smart-3b35cdc3-e862-46f0-b2af-12dbaa240bb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34029
80107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.3402980107
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.1370447947
Short name T119
Test name
Test status
Simulation time 232962230 ps
CPU time 0.9 seconds
Started Jul 26 05:09:16 PM PDT 24
Finished Jul 26 05:09:17 PM PDT 24
Peak memory 207120 kb
Host smart-f8ad17b1-f0f3-49bb-a509-5ec45931e5bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13704
47947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.1370447947
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_iso_retraction.398837613
Short name T489
Test name
Test status
Simulation time 10511139203 ps
CPU time 137.5 seconds
Started Jul 26 05:09:23 PM PDT 24
Finished Jul 26 05:11:40 PM PDT 24
Peak memory 207396 kb
Host smart-200f94a9-777a-42e5-b637-029087915b1a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=398837613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.398837613
Directory /workspace/13.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.2522931552
Short name T2470
Test name
Test status
Simulation time 195395718 ps
CPU time 1.01 seconds
Started Jul 26 05:09:56 PM PDT 24
Finished Jul 26 05:09:57 PM PDT 24
Peak memory 207124 kb
Host smart-1a2805c6-73b2-4974-b6f2-46921fe5185f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25229
31552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.2522931552
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.2122751434
Short name T128
Test name
Test status
Simulation time 213581434 ps
CPU time 0.97 seconds
Started Jul 26 05:10:54 PM PDT 24
Finished Jul 26 05:10:56 PM PDT 24
Peak memory 207024 kb
Host smart-2c0527ff-878c-438b-9bd1-435276d75004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21227
51434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.2122751434
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.1396782958
Short name T144
Test name
Test status
Simulation time 187353227 ps
CPU time 0.96 seconds
Started Jul 26 05:11:38 PM PDT 24
Finished Jul 26 05:11:39 PM PDT 24
Peak memory 207120 kb
Host smart-26b823cd-3a96-4435-9851-9f238b3afa58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13967
82958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.1396782958
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.914489187
Short name T124
Test name
Test status
Simulation time 212911849 ps
CPU time 0.97 seconds
Started Jul 26 05:12:03 PM PDT 24
Finished Jul 26 05:12:04 PM PDT 24
Peak memory 206976 kb
Host smart-186e004d-ba00-4e6c-a95c-7383834aaa92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91448
9187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.914489187
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.1956143110
Short name T122
Test name
Test status
Simulation time 178007401 ps
CPU time 0.96 seconds
Started Jul 26 05:07:02 PM PDT 24
Finished Jul 26 05:07:03 PM PDT 24
Peak memory 206976 kb
Host smart-0a38d30c-48a2-4945-a98f-ae5249431109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19561
43110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.1956143110
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.2749586465
Short name T85
Test name
Test status
Simulation time 12787869915 ps
CPU time 110.7 seconds
Started Jul 26 05:07:11 PM PDT 24
Finished Jul 26 05:09:02 PM PDT 24
Peak memory 215516 kb
Host smart-ad76de22-f14f-48d7-8b8a-e4f0120f63f3
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749586465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.2749586465
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.2833955759
Short name T76
Test name
Test status
Simulation time 14400796203 ps
CPU time 101.1 seconds
Started Jul 26 05:07:26 PM PDT 24
Finished Jul 26 05:09:08 PM PDT 24
Peak memory 217956 kb
Host smart-06e3e9bd-72a5-4f87-afc3-8e1053051a8d
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833955759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.2833955759
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.4234732133
Short name T130
Test name
Test status
Simulation time 221665577 ps
CPU time 1.11 seconds
Started Jul 26 05:14:31 PM PDT 24
Finished Jul 26 05:14:32 PM PDT 24
Peak memory 206924 kb
Host smart-dc679593-73b2-40da-ae46-d27d30ecb722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42347
32133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.4234732133
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1391325455
Short name T2940
Test name
Test status
Simulation time 192174527 ps
CPU time 2.05 seconds
Started Jul 26 04:57:10 PM PDT 24
Finished Jul 26 04:57:13 PM PDT 24
Peak memory 206248 kb
Host smart-af4d60f1-cef5-43ec-9944-bfe85f322813
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1391325455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.1391325455
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2968313860
Short name T267
Test name
Test status
Simulation time 873718528 ps
CPU time 4.77 seconds
Started Jul 26 04:56:59 PM PDT 24
Finished Jul 26 04:57:04 PM PDT 24
Peak memory 206284 kb
Host smart-0964e386-1309-4e23-8ac8-748c6f8ccc0b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2968313860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.2968313860
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1897987736
Short name T192
Test name
Test status
Simulation time 241884739 ps
CPU time 1.01 seconds
Started Jul 26 04:56:57 PM PDT 24
Finished Jul 26 04:56:58 PM PDT 24
Peak memory 206084 kb
Host smart-749f7885-e261-4da2-9f75-c08829261803
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1897987736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1897987736
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1678563592
Short name T2920
Test name
Test status
Simulation time 184945970 ps
CPU time 1.84 seconds
Started Jul 26 04:57:04 PM PDT 24
Finished Jul 26 04:57:06 PM PDT 24
Peak memory 214492 kb
Host smart-103465f0-48ff-46c0-b166-ec56ef7ea5fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678563592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.1678563592
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.4126807618
Short name T2884
Test name
Test status
Simulation time 81497486 ps
CPU time 0.71 seconds
Started Jul 26 04:57:00 PM PDT 24
Finished Jul 26 04:57:00 PM PDT 24
Peak memory 206000 kb
Host smart-0d645a10-2a5f-4b6f-9099-b4ef60e9724a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4126807618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.4126807618
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2498738062
Short name T250
Test name
Test status
Simulation time 194599533 ps
CPU time 2.39 seconds
Started Jul 26 04:57:09 PM PDT 24
Finished Jul 26 04:57:12 PM PDT 24
Peak memory 214440 kb
Host smart-3e2835b3-56ae-4030-819c-0bbc191455d9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2498738062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.2498738062
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.123693370
Short name T2916
Test name
Test status
Simulation time 487311575 ps
CPU time 4.37 seconds
Started Jul 26 04:56:57 PM PDT 24
Finished Jul 26 04:57:01 PM PDT 24
Peak memory 206192 kb
Host smart-dfeaa948-7a8c-44ab-8df8-3d7b55bfa99f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=123693370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.123693370
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3324395302
Short name T2880
Test name
Test status
Simulation time 103006880 ps
CPU time 1.14 seconds
Started Jul 26 04:57:16 PM PDT 24
Finished Jul 26 04:57:17 PM PDT 24
Peak memory 206288 kb
Host smart-24436d08-5cfb-4a57-b00d-9612e95c292c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3324395302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.3324395302
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1161112520
Short name T2915
Test name
Test status
Simulation time 94901147 ps
CPU time 2.37 seconds
Started Jul 26 04:57:05 PM PDT 24
Finished Jul 26 04:57:08 PM PDT 24
Peak memory 206308 kb
Host smart-aeecc416-d768-44ff-8628-5b775fd5829a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1161112520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.1161112520
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.4252800322
Short name T2912
Test name
Test status
Simulation time 1025978814 ps
CPU time 5.12 seconds
Started Jul 26 04:56:59 PM PDT 24
Finished Jul 26 04:57:04 PM PDT 24
Peak memory 206360 kb
Host smart-b2801820-c0f2-4b8e-af83-de5a68dd5031
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4252800322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.4252800322
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.4025346934
Short name T2934
Test name
Test status
Simulation time 94759463 ps
CPU time 1.9 seconds
Started Jul 26 04:57:12 PM PDT 24
Finished Jul 26 04:57:14 PM PDT 24
Peak memory 206280 kb
Host smart-465d0614-c4e1-4bad-8106-4a7a8c876930
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4025346934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.4025346934
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1118955467
Short name T2956
Test name
Test status
Simulation time 708511741 ps
CPU time 7.18 seconds
Started Jul 26 04:56:58 PM PDT 24
Finished Jul 26 04:57:05 PM PDT 24
Peak memory 206436 kb
Host smart-5200b527-9161-45f8-99f3-5f84e00139f0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1118955467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.1118955467
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.773777370
Short name T2965
Test name
Test status
Simulation time 243242827 ps
CPU time 1.03 seconds
Started Jul 26 04:56:57 PM PDT 24
Finished Jul 26 04:56:59 PM PDT 24
Peak memory 206024 kb
Host smart-eb4a9225-9405-497c-85de-fd70b1e1f603
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=773777370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.773777370
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2217291595
Short name T2936
Test name
Test status
Simulation time 95251071 ps
CPU time 2.5 seconds
Started Jul 26 04:56:56 PM PDT 24
Finished Jul 26 04:56:58 PM PDT 24
Peak memory 214528 kb
Host smart-ef36d070-47c3-4b83-bc8f-a986bb8d042d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217291595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.2217291595
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1426801731
Short name T214
Test name
Test status
Simulation time 85033118 ps
CPU time 0.81 seconds
Started Jul 26 04:57:16 PM PDT 24
Finished Jul 26 04:57:17 PM PDT 24
Peak memory 206100 kb
Host smart-cc553ae0-f947-4c90-88f7-25b29a3695cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1426801731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.1426801731
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3875036157
Short name T2924
Test name
Test status
Simulation time 47609984 ps
CPU time 0.72 seconds
Started Jul 26 04:57:04 PM PDT 24
Finished Jul 26 04:57:05 PM PDT 24
Peak memory 205888 kb
Host smart-296ef1d1-ef6a-42a3-9b9b-39bb85cff461
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3875036157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.3875036157
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2098229070
Short name T2945
Test name
Test status
Simulation time 88264950 ps
CPU time 2.03 seconds
Started Jul 26 04:57:08 PM PDT 24
Finished Jul 26 04:57:10 PM PDT 24
Peak memory 214472 kb
Host smart-af4c425d-92c7-4d4e-b498-a303095fb826
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2098229070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2098229070
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3435544671
Short name T2911
Test name
Test status
Simulation time 117555227 ps
CPU time 2.29 seconds
Started Jul 26 04:56:58 PM PDT 24
Finished Jul 26 04:57:00 PM PDT 24
Peak memory 206328 kb
Host smart-f8be13da-2a51-4f0a-9823-dae3da180bad
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3435544671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.3435544671
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3041958533
Short name T193
Test name
Test status
Simulation time 163831715 ps
CPU time 1.43 seconds
Started Jul 26 04:57:14 PM PDT 24
Finished Jul 26 04:57:16 PM PDT 24
Peak memory 205484 kb
Host smart-eeea8067-30ac-48bc-ae2f-50a47bb0a1e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3041958533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.3041958533
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1744199015
Short name T2901
Test name
Test status
Simulation time 117402760 ps
CPU time 2.87 seconds
Started Jul 26 04:57:17 PM PDT 24
Finished Jul 26 04:57:20 PM PDT 24
Peak memory 222536 kb
Host smart-dbe52fdd-e920-4c32-a097-ac01b7352b7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1744199015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1744199015
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2284090113
Short name T2872
Test name
Test status
Simulation time 82739031 ps
CPU time 1.27 seconds
Started Jul 26 04:57:08 PM PDT 24
Finished Jul 26 04:57:09 PM PDT 24
Peak memory 216368 kb
Host smart-623ec98f-8188-459e-adbe-35af4bf5e246
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284090113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.2284090113
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3146747668
Short name T2910
Test name
Test status
Simulation time 91540249 ps
CPU time 0.87 seconds
Started Jul 26 04:57:08 PM PDT 24
Finished Jul 26 04:57:09 PM PDT 24
Peak memory 205964 kb
Host smart-d3a31a34-2fab-417a-b77b-c897969c5558
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3146747668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.3146747668
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2720990433
Short name T2914
Test name
Test status
Simulation time 100760641 ps
CPU time 0.8 seconds
Started Jul 26 04:57:16 PM PDT 24
Finished Jul 26 04:57:17 PM PDT 24
Peak memory 205956 kb
Host smart-15594248-857c-4659-b90e-8ba5c736e10e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2720990433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.2720990433
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3024712501
Short name T2882
Test name
Test status
Simulation time 132109667 ps
CPU time 1.44 seconds
Started Jul 26 04:57:19 PM PDT 24
Finished Jul 26 04:57:21 PM PDT 24
Peak memory 206296 kb
Host smart-26659266-6f7b-4ab4-8ff5-7df1e39d9a28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3024712501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.3024712501
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1648445203
Short name T2971
Test name
Test status
Simulation time 97432615 ps
CPU time 2.43 seconds
Started Jul 26 04:57:07 PM PDT 24
Finished Jul 26 04:57:10 PM PDT 24
Peak memory 222408 kb
Host smart-d950733a-c852-4a6b-834b-98f0e412d961
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1648445203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1648445203
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.4209054490
Short name T264
Test name
Test status
Simulation time 396868496 ps
CPU time 2.46 seconds
Started Jul 26 04:57:20 PM PDT 24
Finished Jul 26 04:57:22 PM PDT 24
Peak memory 206360 kb
Host smart-1712c2ab-6e83-45be-9c3e-a6e2691824dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4209054490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.4209054490
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1353498511
Short name T2947
Test name
Test status
Simulation time 86421347 ps
CPU time 1.25 seconds
Started Jul 26 04:57:14 PM PDT 24
Finished Jul 26 04:57:16 PM PDT 24
Peak memory 214432 kb
Host smart-6e498541-588c-4a92-80bd-39fe3e747e06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353498511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.1353498511
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3421711814
Short name T249
Test name
Test status
Simulation time 78296398 ps
CPU time 0.98 seconds
Started Jul 26 04:57:14 PM PDT 24
Finished Jul 26 04:57:15 PM PDT 24
Peak memory 206056 kb
Host smart-2c39971f-e928-415f-89dc-8fa8149b367f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3421711814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3421711814
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1042010665
Short name T2949
Test name
Test status
Simulation time 35184681 ps
CPU time 0.68 seconds
Started Jul 26 04:57:17 PM PDT 24
Finished Jul 26 04:57:18 PM PDT 24
Peak memory 205888 kb
Host smart-36ae9e55-9097-45e7-91fa-7f23801c13b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1042010665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.1042010665
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.189996110
Short name T2906
Test name
Test status
Simulation time 103531957 ps
CPU time 1.47 seconds
Started Jul 26 04:57:23 PM PDT 24
Finished Jul 26 04:57:24 PM PDT 24
Peak memory 206304 kb
Host smart-c2263244-8682-414b-8881-5c5fbab299e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=189996110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.189996110
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3613037130
Short name T294
Test name
Test status
Simulation time 388184655 ps
CPU time 2.83 seconds
Started Jul 26 04:57:17 PM PDT 24
Finished Jul 26 04:57:20 PM PDT 24
Peak memory 206272 kb
Host smart-63c0f029-ef0c-417d-b6a3-1600d6f71fc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3613037130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.3613037130
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2860752546
Short name T219
Test name
Test status
Simulation time 72352661 ps
CPU time 1.64 seconds
Started Jul 26 04:57:19 PM PDT 24
Finished Jul 26 04:57:21 PM PDT 24
Peak memory 214480 kb
Host smart-d3e35d59-40f6-41f1-a804-56de877ccb01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860752546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.2860752546
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.976342199
Short name T253
Test name
Test status
Simulation time 76578173 ps
CPU time 1 seconds
Started Jul 26 04:57:11 PM PDT 24
Finished Jul 26 04:57:12 PM PDT 24
Peak memory 206096 kb
Host smart-4b1afaf6-9754-47b0-b5dd-c001420f246d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=976342199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.976342199
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2834301257
Short name T2921
Test name
Test status
Simulation time 58188258 ps
CPU time 0.86 seconds
Started Jul 26 04:57:08 PM PDT 24
Finished Jul 26 04:57:09 PM PDT 24
Peak memory 206044 kb
Host smart-cc64bda6-0a3d-4f18-a5ee-a6a910527129
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2834301257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.2834301257
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.1301688743
Short name T2961
Test name
Test status
Simulation time 107942875 ps
CPU time 1.14 seconds
Started Jul 26 04:57:24 PM PDT 24
Finished Jul 26 04:57:25 PM PDT 24
Peak memory 206676 kb
Host smart-b0d11919-844a-46bb-a0c4-7341dc00a679
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1301688743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.1301688743
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3167312614
Short name T2888
Test name
Test status
Simulation time 146661525 ps
CPU time 1.92 seconds
Started Jul 26 04:57:09 PM PDT 24
Finished Jul 26 04:57:11 PM PDT 24
Peak memory 206400 kb
Host smart-0a4596da-23ee-417b-9309-0b9dcfa67120
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3167312614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.3167312614
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.586532441
Short name T231
Test name
Test status
Simulation time 1201367027 ps
CPU time 4.71 seconds
Started Jul 26 04:57:18 PM PDT 24
Finished Jul 26 04:57:23 PM PDT 24
Peak memory 206180 kb
Host smart-4d8ed7e9-7a51-4601-9cd9-025ab4c566a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=586532441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.586532441
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2466863148
Short name T2908
Test name
Test status
Simulation time 71447803 ps
CPU time 1.52 seconds
Started Jul 26 04:57:14 PM PDT 24
Finished Jul 26 04:57:15 PM PDT 24
Peak memory 214644 kb
Host smart-496fd0d3-0a5b-4314-a01e-633837695104
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466863148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.2466863148
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1181649330
Short name T2876
Test name
Test status
Simulation time 72849197 ps
CPU time 1.02 seconds
Started Jul 26 04:57:16 PM PDT 24
Finished Jul 26 04:57:17 PM PDT 24
Peak memory 206164 kb
Host smart-63400647-4f15-43db-b665-befad15d22f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1181649330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.1181649330
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.761205709
Short name T2935
Test name
Test status
Simulation time 35251850 ps
CPU time 0.72 seconds
Started Jul 26 04:57:11 PM PDT 24
Finished Jul 26 04:57:12 PM PDT 24
Peak memory 206016 kb
Host smart-c4a468a2-f0ef-46d1-b836-f327298f69c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=761205709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.761205709
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3734954827
Short name T2922
Test name
Test status
Simulation time 177566132 ps
CPU time 1.2 seconds
Started Jul 26 04:57:11 PM PDT 24
Finished Jul 26 04:57:12 PM PDT 24
Peak memory 206520 kb
Host smart-bcd88e90-57e0-4a6e-9a50-229aea9821bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3734954827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.3734954827
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.1670011369
Short name T2964
Test name
Test status
Simulation time 333559152 ps
CPU time 3.47 seconds
Started Jul 26 04:57:18 PM PDT 24
Finished Jul 26 04:57:21 PM PDT 24
Peak memory 206220 kb
Host smart-892bbb7a-6cac-42ae-954d-b8d066b51611
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1670011369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.1670011369
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.251923945
Short name T2954
Test name
Test status
Simulation time 87665832 ps
CPU time 1.38 seconds
Started Jul 26 04:57:10 PM PDT 24
Finished Jul 26 04:57:11 PM PDT 24
Peak memory 214620 kb
Host smart-2b490903-ef24-49e0-ad8c-95774414ba36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251923945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbde
v_csr_mem_rw_with_rand_reset.251923945
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1706626803
Short name T2873
Test name
Test status
Simulation time 54281899 ps
CPU time 0.82 seconds
Started Jul 26 04:57:20 PM PDT 24
Finished Jul 26 04:57:21 PM PDT 24
Peak memory 206096 kb
Host smart-bbff7827-df55-456b-b15c-56abbe9b2862
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1706626803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.1706626803
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1575953128
Short name T265
Test name
Test status
Simulation time 54124464 ps
CPU time 0.7 seconds
Started Jul 26 04:57:14 PM PDT 24
Finished Jul 26 04:57:15 PM PDT 24
Peak memory 205976 kb
Host smart-fe3621ae-9128-4f38-a02d-f023b95ceb69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1575953128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.1575953128
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2218530264
Short name T2886
Test name
Test status
Simulation time 113662145 ps
CPU time 1.57 seconds
Started Jul 26 04:57:16 PM PDT 24
Finished Jul 26 04:57:18 PM PDT 24
Peak memory 206444 kb
Host smart-f5b4800c-f4ea-425c-a830-d1e439b1d0ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2218530264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.2218530264
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2567443639
Short name T226
Test name
Test status
Simulation time 201180715 ps
CPU time 2.15 seconds
Started Jul 26 04:57:18 PM PDT 24
Finished Jul 26 04:57:20 PM PDT 24
Peak memory 206264 kb
Host smart-a79fdcaa-e0ec-4467-9128-5fa7165eb039
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2567443639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.2567443639
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3360481238
Short name T2970
Test name
Test status
Simulation time 332884159 ps
CPU time 2.6 seconds
Started Jul 26 04:57:18 PM PDT 24
Finished Jul 26 04:57:21 PM PDT 24
Peak memory 206316 kb
Host smart-ab40c1c6-fcb8-4e0d-ab95-4addc85c40bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3360481238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3360481238
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1568223187
Short name T213
Test name
Test status
Simulation time 45865308 ps
CPU time 0.96 seconds
Started Jul 26 04:57:21 PM PDT 24
Finished Jul 26 04:57:22 PM PDT 24
Peak memory 205892 kb
Host smart-d0e0ec7d-4612-4c31-b0a8-3a6949cea29e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1568223187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.1568223187
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.52296893
Short name T282
Test name
Test status
Simulation time 31073749 ps
CPU time 0.65 seconds
Started Jul 26 04:57:06 PM PDT 24
Finished Jul 26 04:57:06 PM PDT 24
Peak memory 206004 kb
Host smart-69a9e0a4-b184-47dc-b6f3-e557c00ebd66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=52296893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.52296893
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.2821113616
Short name T2881
Test name
Test status
Simulation time 71297758 ps
CPU time 1.08 seconds
Started Jul 26 04:57:16 PM PDT 24
Finished Jul 26 04:57:17 PM PDT 24
Peak memory 206072 kb
Host smart-fab6c731-c070-4455-854c-227c375f1cc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2821113616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.2821113616
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2380695321
Short name T220
Test name
Test status
Simulation time 192673673 ps
CPU time 2.16 seconds
Started Jul 26 04:57:11 PM PDT 24
Finished Jul 26 04:57:14 PM PDT 24
Peak memory 206348 kb
Host smart-3013b78c-39c2-4023-868f-badcc46e6dbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2380695321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.2380695321
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1877684224
Short name T296
Test name
Test status
Simulation time 907823119 ps
CPU time 3.49 seconds
Started Jul 26 04:57:11 PM PDT 24
Finished Jul 26 04:57:15 PM PDT 24
Peak memory 206292 kb
Host smart-be797156-2929-4062-b1bf-bcd76a6eeb9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1877684224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.1877684224
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.930264640
Short name T2927
Test name
Test status
Simulation time 89866249 ps
CPU time 1.28 seconds
Started Jul 26 04:57:20 PM PDT 24
Finished Jul 26 04:57:21 PM PDT 24
Peak memory 222676 kb
Host smart-875d6402-7ff9-477f-a9eb-fea1f0befecc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930264640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbde
v_csr_mem_rw_with_rand_reset.930264640
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.617648384
Short name T2942
Test name
Test status
Simulation time 49640269 ps
CPU time 0.82 seconds
Started Jul 26 04:57:21 PM PDT 24
Finished Jul 26 04:57:21 PM PDT 24
Peak memory 206044 kb
Host smart-d954dd6a-2671-464b-99d5-a61d923f998e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=617648384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.617648384
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3429024525
Short name T2893
Test name
Test status
Simulation time 190155847 ps
CPU time 1.64 seconds
Started Jul 26 04:57:23 PM PDT 24
Finished Jul 26 04:57:25 PM PDT 24
Peak memory 206400 kb
Host smart-e3299de9-76d5-4a00-bf12-ee98a7f5d693
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3429024525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.3429024525
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1715864164
Short name T2932
Test name
Test status
Simulation time 71105060 ps
CPU time 2.32 seconds
Started Jul 26 04:57:18 PM PDT 24
Finished Jul 26 04:57:20 PM PDT 24
Peak memory 206304 kb
Host smart-b0ed920b-2536-4ec9-b699-1ece27e5c53f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1715864164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1715864164
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3914328936
Short name T230
Test name
Test status
Simulation time 505898896 ps
CPU time 3.08 seconds
Started Jul 26 04:57:16 PM PDT 24
Finished Jul 26 04:57:20 PM PDT 24
Peak memory 206388 kb
Host smart-eef8d5d2-1fcb-41f0-950a-14708e3b4f3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3914328936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.3914328936
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1879088066
Short name T189
Test name
Test status
Simulation time 88599338 ps
CPU time 1.34 seconds
Started Jul 26 04:57:31 PM PDT 24
Finished Jul 26 04:57:32 PM PDT 24
Peak memory 214492 kb
Host smart-1cb0ae0c-8bb5-434a-aac5-f72d9f2e0262
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879088066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.1879088066
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2184148286
Short name T2959
Test name
Test status
Simulation time 77012402 ps
CPU time 0.82 seconds
Started Jul 26 04:57:22 PM PDT 24
Finished Jul 26 04:57:23 PM PDT 24
Peak memory 206056 kb
Host smart-5754406e-d346-44aa-8735-bba4bb2b234e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2184148286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.2184148286
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.828658232
Short name T2929
Test name
Test status
Simulation time 49455060 ps
CPU time 0.8 seconds
Started Jul 26 04:57:21 PM PDT 24
Finished Jul 26 04:57:22 PM PDT 24
Peak memory 205976 kb
Host smart-ae6cc967-8ab7-4562-a97f-5ea02c9929d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=828658232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.828658232
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.4015204993
Short name T191
Test name
Test status
Simulation time 263639646 ps
CPU time 1.8 seconds
Started Jul 26 04:57:21 PM PDT 24
Finished Jul 26 04:57:23 PM PDT 24
Peak memory 206256 kb
Host smart-505bf004-45d3-441e-873a-949ff59b0f12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4015204993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.4015204993
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1289262438
Short name T2941
Test name
Test status
Simulation time 101471956 ps
CPU time 1.53 seconds
Started Jul 26 04:57:38 PM PDT 24
Finished Jul 26 04:57:40 PM PDT 24
Peak memory 206320 kb
Host smart-984d6d95-c93a-4216-87f5-28472f62e5a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1289262438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.1289262438
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.274683753
Short name T2944
Test name
Test status
Simulation time 1086087932 ps
CPU time 4.76 seconds
Started Jul 26 04:57:24 PM PDT 24
Finished Jul 26 04:57:29 PM PDT 24
Peak memory 206284 kb
Host smart-9864d2c2-4876-4c0c-b6fe-7a80eb64f1d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=274683753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.274683753
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1257292885
Short name T2894
Test name
Test status
Simulation time 161318482 ps
CPU time 2.28 seconds
Started Jul 26 04:57:26 PM PDT 24
Finished Jul 26 04:57:28 PM PDT 24
Peak memory 214528 kb
Host smart-a5ba025a-e34e-4165-a2a8-119a2fa2bb4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257292885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.1257292885
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1386893424
Short name T251
Test name
Test status
Simulation time 57168735 ps
CPU time 0.95 seconds
Started Jul 26 04:57:26 PM PDT 24
Finished Jul 26 04:57:27 PM PDT 24
Peak memory 206032 kb
Host smart-10e6b930-e2b8-4e25-b5ae-5255fbfeec10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1386893424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.1386893424
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3730925709
Short name T2958
Test name
Test status
Simulation time 47689563 ps
CPU time 0.69 seconds
Started Jul 26 04:57:26 PM PDT 24
Finished Jul 26 04:57:27 PM PDT 24
Peak memory 206052 kb
Host smart-611ff6b6-b8da-44a3-9192-df575cfe18b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3730925709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.3730925709
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.998752787
Short name T255
Test name
Test status
Simulation time 129959969 ps
CPU time 1.08 seconds
Started Jul 26 04:57:29 PM PDT 24
Finished Jul 26 04:57:30 PM PDT 24
Peak memory 206296 kb
Host smart-16531ad3-6623-42b0-8ccd-7d4a75e23f53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=998752787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.998752787
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3200898333
Short name T2890
Test name
Test status
Simulation time 90989934 ps
CPU time 2.68 seconds
Started Jul 26 04:57:24 PM PDT 24
Finished Jul 26 04:57:27 PM PDT 24
Peak memory 219088 kb
Host smart-d335891e-fcdb-46a0-9819-a7a3fa2310c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3200898333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3200898333
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3474764353
Short name T291
Test name
Test status
Simulation time 1082491804 ps
CPU time 4.42 seconds
Started Jul 26 04:57:34 PM PDT 24
Finished Jul 26 04:57:39 PM PDT 24
Peak memory 206128 kb
Host smart-bf8797fa-7f1e-4ad0-93b2-fd04a45654e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3474764353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.3474764353
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2743328640
Short name T2953
Test name
Test status
Simulation time 112473851 ps
CPU time 2.04 seconds
Started Jul 26 04:57:35 PM PDT 24
Finished Jul 26 04:57:37 PM PDT 24
Peak memory 214576 kb
Host smart-b7a6bb74-66bc-4d59-9882-d2ec388a2300
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743328640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.2743328640
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2793247742
Short name T241
Test name
Test status
Simulation time 47303600 ps
CPU time 0.99 seconds
Started Jul 26 04:57:36 PM PDT 24
Finished Jul 26 04:57:37 PM PDT 24
Peak memory 206144 kb
Host smart-5c1f6a74-3bce-43c2-95ea-36f7d244bd35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2793247742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.2793247742
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.4167882278
Short name T200
Test name
Test status
Simulation time 76528885 ps
CPU time 0.77 seconds
Started Jul 26 04:57:33 PM PDT 24
Finished Jul 26 04:57:34 PM PDT 24
Peak memory 206052 kb
Host smart-16520c22-f17d-4f92-8e12-4989f3c09ed1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4167882278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.4167882278
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1581709082
Short name T2923
Test name
Test status
Simulation time 99194982 ps
CPU time 1.45 seconds
Started Jul 26 04:57:33 PM PDT 24
Finished Jul 26 04:57:34 PM PDT 24
Peak memory 206312 kb
Host smart-481ae428-41f3-4dcb-bff0-67f1b7a8f4a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1581709082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.1581709082
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3836027955
Short name T222
Test name
Test status
Simulation time 256954636 ps
CPU time 3.07 seconds
Started Jul 26 04:57:23 PM PDT 24
Finished Jul 26 04:57:26 PM PDT 24
Peak memory 221820 kb
Host smart-0efc8bbc-0284-44f9-aa3a-510db93cf537
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3836027955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3836027955
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.733758748
Short name T212
Test name
Test status
Simulation time 806227191 ps
CPU time 4.63 seconds
Started Jul 26 04:57:23 PM PDT 24
Finished Jul 26 04:57:28 PM PDT 24
Peak memory 206316 kb
Host smart-11354dd1-e601-4c82-a3af-c953321e69f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=733758748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.733758748
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2591878326
Short name T2866
Test name
Test status
Simulation time 81992983 ps
CPU time 1.89 seconds
Started Jul 26 04:56:55 PM PDT 24
Finished Jul 26 04:56:57 PM PDT 24
Peak memory 206188 kb
Host smart-b35f967a-afe9-4639-a420-7de90e7bd409
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2591878326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2591878326
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2345650691
Short name T2939
Test name
Test status
Simulation time 2554854776 ps
CPU time 9.04 seconds
Started Jul 26 04:56:58 PM PDT 24
Finished Jul 26 04:57:07 PM PDT 24
Peak memory 206568 kb
Host smart-dfef9288-3eda-473e-a74b-531b73058f50
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2345650691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.2345650691
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2501152975
Short name T262
Test name
Test status
Simulation time 75948735 ps
CPU time 0.83 seconds
Started Jul 26 04:57:11 PM PDT 24
Finished Jul 26 04:57:12 PM PDT 24
Peak memory 206000 kb
Host smart-3201e778-1347-4475-a375-dbd582e3c1ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2501152975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.2501152975
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2838131782
Short name T223
Test name
Test status
Simulation time 176661903 ps
CPU time 1.86 seconds
Started Jul 26 04:57:21 PM PDT 24
Finished Jul 26 04:57:23 PM PDT 24
Peak memory 214548 kb
Host smart-0ecf7b3f-df85-4604-a9c9-158a98a8ab56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838131782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.2838131782
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3246530040
Short name T2946
Test name
Test status
Simulation time 69935730 ps
CPU time 1.07 seconds
Started Jul 26 04:57:06 PM PDT 24
Finished Jul 26 04:57:08 PM PDT 24
Peak memory 206136 kb
Host smart-adc723f8-0898-4bc4-94e7-9e8e5c5d2c4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3246530040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.3246530040
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.289363564
Short name T2973
Test name
Test status
Simulation time 59542935 ps
CPU time 0.76 seconds
Started Jul 26 04:57:06 PM PDT 24
Finished Jul 26 04:57:07 PM PDT 24
Peak memory 206008 kb
Host smart-8b6e2cf6-05c6-49e4-9522-19e71e4635b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=289363564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.289363564
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1900267135
Short name T245
Test name
Test status
Simulation time 127305071 ps
CPU time 1.53 seconds
Started Jul 26 04:56:58 PM PDT 24
Finished Jul 26 04:56:59 PM PDT 24
Peak memory 206180 kb
Host smart-49a5855f-5355-4f62-9cb3-18d1dc9daa5a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1900267135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.1900267135
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.484680810
Short name T2869
Test name
Test status
Simulation time 383930130 ps
CPU time 2.82 seconds
Started Jul 26 04:56:58 PM PDT 24
Finished Jul 26 04:57:01 PM PDT 24
Peak memory 206276 kb
Host smart-c554af07-9d54-4a21-aa56-afda82327cbe
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=484680810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.484680810
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.971131695
Short name T2898
Test name
Test status
Simulation time 242797028 ps
CPU time 1.69 seconds
Started Jul 26 04:57:26 PM PDT 24
Finished Jul 26 04:57:28 PM PDT 24
Peak memory 206320 kb
Host smart-9ea49686-aa21-4c57-bb17-75de614ac903
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=971131695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.971131695
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.417816705
Short name T2903
Test name
Test status
Simulation time 125095791 ps
CPU time 1.47 seconds
Started Jul 26 04:56:56 PM PDT 24
Finished Jul 26 04:56:58 PM PDT 24
Peak memory 206416 kb
Host smart-21d1402c-d87c-4c0f-abd4-040eb195bab8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=417816705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.417816705
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2260771728
Short name T229
Test name
Test status
Simulation time 890092066 ps
CPU time 4.67 seconds
Started Jul 26 04:56:57 PM PDT 24
Finished Jul 26 04:57:02 PM PDT 24
Peak memory 206292 kb
Host smart-bc89e81a-b9c0-4162-8686-e5f4321cfaf5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2260771728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.2260771728
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2349300847
Short name T285
Test name
Test status
Simulation time 40804509 ps
CPU time 0.7 seconds
Started Jul 26 04:57:23 PM PDT 24
Finished Jul 26 04:57:24 PM PDT 24
Peak memory 205968 kb
Host smart-edecd154-eb9a-4735-8872-cb9c3375690a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2349300847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.2349300847
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2271736070
Short name T2926
Test name
Test status
Simulation time 34157668 ps
CPU time 0.71 seconds
Started Jul 26 04:57:38 PM PDT 24
Finished Jul 26 04:57:39 PM PDT 24
Peak memory 205968 kb
Host smart-65db1044-f878-47af-bb05-25437299eb9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2271736070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.2271736070
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.3146669176
Short name T2937
Test name
Test status
Simulation time 41241102 ps
CPU time 0.77 seconds
Started Jul 26 04:57:34 PM PDT 24
Finished Jul 26 04:57:35 PM PDT 24
Peak memory 205996 kb
Host smart-10711382-7011-4a3f-840a-a2d36a1ae852
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3146669176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.3146669176
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3373695954
Short name T2905
Test name
Test status
Simulation time 49121466 ps
CPU time 0.77 seconds
Started Jul 26 04:57:23 PM PDT 24
Finished Jul 26 04:57:24 PM PDT 24
Peak memory 206012 kb
Host smart-e9809e7a-c170-4421-9be3-ce4ea49f326b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3373695954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.3373695954
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1564836688
Short name T2931
Test name
Test status
Simulation time 109827029 ps
CPU time 0.86 seconds
Started Jul 26 04:57:46 PM PDT 24
Finished Jul 26 04:57:47 PM PDT 24
Peak memory 206092 kb
Host smart-14279284-b471-432f-beac-6fa1863aa6c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1564836688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.1564836688
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.4284618417
Short name T2883
Test name
Test status
Simulation time 61081892 ps
CPU time 0.78 seconds
Started Jul 26 04:57:23 PM PDT 24
Finished Jul 26 04:57:24 PM PDT 24
Peak memory 206012 kb
Host smart-a62ddbd9-2cb4-4c79-b829-316a303d4bad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4284618417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.4284618417
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.3755522305
Short name T288
Test name
Test status
Simulation time 57267687 ps
CPU time 0.74 seconds
Started Jul 26 04:57:33 PM PDT 24
Finished Jul 26 04:57:33 PM PDT 24
Peak memory 205896 kb
Host smart-2f5dfa05-d212-47ae-896e-676ad66b9f85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3755522305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.3755522305
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3972857150
Short name T2875
Test name
Test status
Simulation time 39407938 ps
CPU time 0.72 seconds
Started Jul 26 04:57:25 PM PDT 24
Finished Jul 26 04:57:26 PM PDT 24
Peak memory 206044 kb
Host smart-8c7bc5be-9d87-4f66-8bd5-77cceefa989f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3972857150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.3972857150
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.171284065
Short name T2967
Test name
Test status
Simulation time 78113128 ps
CPU time 0.73 seconds
Started Jul 26 04:57:25 PM PDT 24
Finished Jul 26 04:57:26 PM PDT 24
Peak memory 206048 kb
Host smart-11274d9b-df7d-48a1-ace7-461c7c1bb91e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=171284065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.171284065
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1018502944
Short name T286
Test name
Test status
Simulation time 49087579 ps
CPU time 0.7 seconds
Started Jul 26 04:57:23 PM PDT 24
Finished Jul 26 04:57:24 PM PDT 24
Peak memory 206016 kb
Host smart-6d08b907-c228-4b8e-bbcb-f77a223383e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1018502944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.1018502944
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1538998412
Short name T2948
Test name
Test status
Simulation time 139883090 ps
CPU time 2.98 seconds
Started Jul 26 04:57:11 PM PDT 24
Finished Jul 26 04:57:14 PM PDT 24
Peak memory 206328 kb
Host smart-c85eb602-6593-46ce-a835-53cc9eb5f43b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1538998412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.1538998412
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.934191822
Short name T2900
Test name
Test status
Simulation time 639988427 ps
CPU time 4.41 seconds
Started Jul 26 04:57:20 PM PDT 24
Finished Jul 26 04:57:25 PM PDT 24
Peak memory 206388 kb
Host smart-9c7a0b46-f300-471f-b1dd-cee01284cbeb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=934191822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.934191822
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1872749111
Short name T248
Test name
Test status
Simulation time 58718394 ps
CPU time 0.79 seconds
Started Jul 26 04:57:00 PM PDT 24
Finished Jul 26 04:57:01 PM PDT 24
Peak memory 206012 kb
Host smart-3d847825-de73-4979-b111-e38b316dbcfe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1872749111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.1872749111
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2109432454
Short name T2966
Test name
Test status
Simulation time 68810551 ps
CPU time 1.51 seconds
Started Jul 26 04:57:16 PM PDT 24
Finished Jul 26 04:57:18 PM PDT 24
Peak memory 214568 kb
Host smart-f893e73f-4ea6-42ad-a72e-6cd8fc5ccb30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109432454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.2109432454
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2672557643
Short name T257
Test name
Test status
Simulation time 61230749 ps
CPU time 0.79 seconds
Started Jul 26 04:57:00 PM PDT 24
Finished Jul 26 04:57:01 PM PDT 24
Peak memory 205960 kb
Host smart-7c5ffc0f-fb26-4de9-a199-88d7a3209939
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2672557643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2672557643
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.515492443
Short name T2870
Test name
Test status
Simulation time 89925286 ps
CPU time 0.76 seconds
Started Jul 26 04:57:17 PM PDT 24
Finished Jul 26 04:57:17 PM PDT 24
Peak memory 205892 kb
Host smart-f107b0ff-14de-4174-a2d9-464a867ddcd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=515492443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.515492443
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1492241248
Short name T244
Test name
Test status
Simulation time 63870330 ps
CPU time 1.34 seconds
Started Jul 26 04:57:26 PM PDT 24
Finished Jul 26 04:57:27 PM PDT 24
Peak memory 206224 kb
Host smart-36f1ee52-42f7-4392-b7af-82002944f874
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1492241248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1492241248
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3292190010
Short name T2895
Test name
Test status
Simulation time 171066769 ps
CPU time 3.86 seconds
Started Jul 26 04:57:16 PM PDT 24
Finished Jul 26 04:57:21 PM PDT 24
Peak memory 206284 kb
Host smart-5fcf4118-0ff7-4aa2-b4d7-f85bd3dde0dc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3292190010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.3292190010
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1160470632
Short name T2955
Test name
Test status
Simulation time 144332322 ps
CPU time 1.06 seconds
Started Jul 26 04:56:57 PM PDT 24
Finished Jul 26 04:56:58 PM PDT 24
Peak memory 206296 kb
Host smart-90cd7f3a-f13a-41d9-bacc-6a963f788cf1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1160470632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.1160470632
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2138658362
Short name T2896
Test name
Test status
Simulation time 62193997 ps
CPU time 1.32 seconds
Started Jul 26 04:56:59 PM PDT 24
Finished Jul 26 04:57:01 PM PDT 24
Peak memory 206308 kb
Host smart-7043049b-1a99-4d01-b79b-9ffb641c4da1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2138658362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2138658362
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.312458122
Short name T2974
Test name
Test status
Simulation time 926744278 ps
CPU time 4.86 seconds
Started Jul 26 04:56:59 PM PDT 24
Finished Jul 26 04:57:04 PM PDT 24
Peak memory 206336 kb
Host smart-9ba8a980-0032-4b1b-b751-6f5bfc0835bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=312458122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.312458122
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2498173289
Short name T2871
Test name
Test status
Simulation time 38178293 ps
CPU time 0.69 seconds
Started Jul 26 04:57:36 PM PDT 24
Finished Jul 26 04:57:37 PM PDT 24
Peak memory 205948 kb
Host smart-1d5e94a7-0f45-4d16-8459-5825c4625787
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2498173289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.2498173289
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3858541720
Short name T2943
Test name
Test status
Simulation time 33227306 ps
CPU time 0.69 seconds
Started Jul 26 04:57:27 PM PDT 24
Finished Jul 26 04:57:28 PM PDT 24
Peak memory 206224 kb
Host smart-0792049f-7cbf-4d49-a9e8-9102d0b7f795
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3858541720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.3858541720
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.805546382
Short name T2968
Test name
Test status
Simulation time 83665186 ps
CPU time 0.77 seconds
Started Jul 26 04:57:25 PM PDT 24
Finished Jul 26 04:57:26 PM PDT 24
Peak memory 206064 kb
Host smart-ed9b99d8-7175-4036-ac37-e9f79598d4ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=805546382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.805546382
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.4158942881
Short name T284
Test name
Test status
Simulation time 85643428 ps
CPU time 0.83 seconds
Started Jul 26 04:57:36 PM PDT 24
Finished Jul 26 04:57:37 PM PDT 24
Peak memory 206012 kb
Host smart-10222814-1215-409d-8c9c-f79f14f09a3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4158942881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.4158942881
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1822343950
Short name T266
Test name
Test status
Simulation time 45510034 ps
CPU time 0.71 seconds
Started Jul 26 04:57:26 PM PDT 24
Finished Jul 26 04:57:27 PM PDT 24
Peak memory 206224 kb
Host smart-cbb41c47-25c3-42bb-b400-fe51fe0a7cca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1822343950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.1822343950
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2533168148
Short name T2909
Test name
Test status
Simulation time 56983270 ps
CPU time 0.7 seconds
Started Jul 26 04:57:38 PM PDT 24
Finished Jul 26 04:57:39 PM PDT 24
Peak memory 205948 kb
Host smart-ccac280e-ae50-45f8-b07c-ca6b9ca816df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2533168148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.2533168148
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3784803956
Short name T2899
Test name
Test status
Simulation time 45705531 ps
CPU time 0.73 seconds
Started Jul 26 04:57:41 PM PDT 24
Finished Jul 26 04:57:41 PM PDT 24
Peak memory 206004 kb
Host smart-5ca37877-9bd1-47a0-989f-dbb058ec86d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3784803956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.3784803956
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.1199088533
Short name T2950
Test name
Test status
Simulation time 59780243 ps
CPU time 0.71 seconds
Started Jul 26 04:57:26 PM PDT 24
Finished Jul 26 04:57:27 PM PDT 24
Peak memory 206016 kb
Host smart-1c554592-4979-4a2c-b24b-c8681797e966
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1199088533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.1199088533
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.4072012734
Short name T2962
Test name
Test status
Simulation time 51777493 ps
CPU time 0.73 seconds
Started Jul 26 04:57:27 PM PDT 24
Finished Jul 26 04:57:28 PM PDT 24
Peak memory 206028 kb
Host smart-ce230753-5b7a-413e-8288-93e4528a10ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4072012734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.4072012734
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1042929108
Short name T2867
Test name
Test status
Simulation time 99505019 ps
CPU time 1.96 seconds
Started Jul 26 04:57:14 PM PDT 24
Finished Jul 26 04:57:16 PM PDT 24
Peak memory 205380 kb
Host smart-9c4db7aa-7d51-486c-9dc2-18da30b01223
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1042929108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.1042929108
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.150060506
Short name T2907
Test name
Test status
Simulation time 2475599356 ps
CPU time 8.52 seconds
Started Jul 26 04:57:08 PM PDT 24
Finished Jul 26 04:57:17 PM PDT 24
Peak memory 206216 kb
Host smart-50997638-dcbd-4ea6-bc20-cf249125a401
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=150060506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.150060506
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2717016419
Short name T246
Test name
Test status
Simulation time 63336092 ps
CPU time 0.81 seconds
Started Jul 26 04:56:58 PM PDT 24
Finished Jul 26 04:56:59 PM PDT 24
Peak memory 206144 kb
Host smart-c650f48a-252a-4faa-a7de-2353e0cb2d92
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2717016419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.2717016419
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3415773902
Short name T2885
Test name
Test status
Simulation time 80712091 ps
CPU time 1.82 seconds
Started Jul 26 04:56:58 PM PDT 24
Finished Jul 26 04:57:00 PM PDT 24
Peak memory 218716 kb
Host smart-a0abb27d-9ca2-467f-900d-32d71a5a9fd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415773902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.3415773902
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2998384271
Short name T247
Test name
Test status
Simulation time 60752943 ps
CPU time 0.84 seconds
Started Jul 26 04:57:11 PM PDT 24
Finished Jul 26 04:57:12 PM PDT 24
Peak memory 205892 kb
Host smart-3f2464b1-3d7c-4b43-ac49-39ebafd0fa35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2998384271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.2998384271
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.887962398
Short name T2877
Test name
Test status
Simulation time 136788442 ps
CPU time 0.85 seconds
Started Jul 26 04:57:10 PM PDT 24
Finished Jul 26 04:57:11 PM PDT 24
Peak memory 206224 kb
Host smart-e319e435-3623-48a1-8e5a-95e54fe30002
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=887962398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.887962398
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3538169976
Short name T242
Test name
Test status
Simulation time 118933224 ps
CPU time 1.43 seconds
Started Jul 26 04:56:57 PM PDT 24
Finished Jul 26 04:56:58 PM PDT 24
Peak memory 206352 kb
Host smart-4b910291-85d4-4ffd-9d23-400d82eedd6f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3538169976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.3538169976
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2065016458
Short name T2918
Test name
Test status
Simulation time 256721456 ps
CPU time 2.46 seconds
Started Jul 26 04:57:15 PM PDT 24
Finished Jul 26 04:57:18 PM PDT 24
Peak memory 206268 kb
Host smart-5462b36c-3776-4822-b198-20d1a688e437
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2065016458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.2065016458
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1851286785
Short name T2874
Test name
Test status
Simulation time 89123441 ps
CPU time 1.53 seconds
Started Jul 26 04:57:17 PM PDT 24
Finished Jul 26 04:57:19 PM PDT 24
Peak memory 206376 kb
Host smart-be939ad1-0b19-4252-8f0c-de6b4c8cb045
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1851286785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.1851286785
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2414610753
Short name T2917
Test name
Test status
Simulation time 104348826 ps
CPU time 1.45 seconds
Started Jul 26 04:57:16 PM PDT 24
Finished Jul 26 04:57:18 PM PDT 24
Peak memory 206320 kb
Host smart-776669dd-5aff-4abf-b02c-c313330b641a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2414610753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.2414610753
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3898145930
Short name T2868
Test name
Test status
Simulation time 70758093 ps
CPU time 0.77 seconds
Started Jul 26 04:57:51 PM PDT 24
Finished Jul 26 04:57:51 PM PDT 24
Peak memory 206004 kb
Host smart-f6075ea5-61bb-4e77-b44b-b7a4f8b6a6fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3898145930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3898145930
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2252977122
Short name T2938
Test name
Test status
Simulation time 36623702 ps
CPU time 0.67 seconds
Started Jul 26 04:57:29 PM PDT 24
Finished Jul 26 04:57:30 PM PDT 24
Peak memory 205944 kb
Host smart-69c764b6-54bf-4ed9-aaca-7281c5f5355e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2252977122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.2252977122
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.2949957641
Short name T2925
Test name
Test status
Simulation time 33930435 ps
CPU time 0.71 seconds
Started Jul 26 04:57:30 PM PDT 24
Finished Jul 26 04:57:31 PM PDT 24
Peak memory 205996 kb
Host smart-f1ae3e8d-52c2-44de-b512-4b08c4c25aaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2949957641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.2949957641
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.544524448
Short name T2902
Test name
Test status
Simulation time 53363224 ps
CPU time 0.71 seconds
Started Jul 26 04:57:31 PM PDT 24
Finished Jul 26 04:57:31 PM PDT 24
Peak memory 206064 kb
Host smart-90f92a93-d25b-441b-9d66-35bdc5c5a256
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=544524448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.544524448
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2068115531
Short name T2879
Test name
Test status
Simulation time 71437352 ps
CPU time 0.76 seconds
Started Jul 26 04:57:27 PM PDT 24
Finished Jul 26 04:57:28 PM PDT 24
Peak memory 206028 kb
Host smart-d88189b4-3a24-44df-b00e-cd6409229f15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2068115531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2068115531
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2890906367
Short name T2878
Test name
Test status
Simulation time 124913898 ps
CPU time 0.86 seconds
Started Jul 26 04:57:30 PM PDT 24
Finished Jul 26 04:57:31 PM PDT 24
Peak memory 206060 kb
Host smart-b6042462-621d-4f08-9b61-89e05e9d6afa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2890906367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.2890906367
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2816173529
Short name T2933
Test name
Test status
Simulation time 51123346 ps
CPU time 0.75 seconds
Started Jul 26 04:57:26 PM PDT 24
Finished Jul 26 04:57:27 PM PDT 24
Peak memory 206008 kb
Host smart-b098db95-3e55-4d58-b9e4-bba5238757d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2816173529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.2816173529
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.656554589
Short name T2969
Test name
Test status
Simulation time 32299102 ps
CPU time 0.73 seconds
Started Jul 26 04:57:26 PM PDT 24
Finished Jul 26 04:57:27 PM PDT 24
Peak memory 206008 kb
Host smart-cbdfe691-ef7f-430c-865a-2f0483cdbb9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=656554589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.656554589
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3537178631
Short name T2891
Test name
Test status
Simulation time 51152048 ps
CPU time 0.72 seconds
Started Jul 26 04:57:26 PM PDT 24
Finished Jul 26 04:57:27 PM PDT 24
Peak memory 205980 kb
Host smart-8e9fc979-351c-451d-8668-7e32aaa988fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3537178631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.3537178631
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2981175068
Short name T2952
Test name
Test status
Simulation time 82921882 ps
CPU time 2.15 seconds
Started Jul 26 04:56:59 PM PDT 24
Finished Jul 26 04:57:02 PM PDT 24
Peak memory 214560 kb
Host smart-d2ad6e85-d879-4cee-a2bf-77bba3753b14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981175068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.2981175068
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.288127705
Short name T2963
Test name
Test status
Simulation time 64962995 ps
CPU time 0.8 seconds
Started Jul 26 04:57:08 PM PDT 24
Finished Jul 26 04:57:09 PM PDT 24
Peak memory 205960 kb
Host smart-5a247af1-5f45-4520-9e55-d20219d0636c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=288127705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.288127705
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2126058909
Short name T2892
Test name
Test status
Simulation time 50126403 ps
CPU time 0.71 seconds
Started Jul 26 04:57:00 PM PDT 24
Finished Jul 26 04:57:01 PM PDT 24
Peak memory 206032 kb
Host smart-cae52203-896e-44d9-9f10-a082ea8bd7d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2126058909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.2126058909
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2754857356
Short name T2972
Test name
Test status
Simulation time 116602406 ps
CPU time 1.46 seconds
Started Jul 26 04:57:10 PM PDT 24
Finished Jul 26 04:57:12 PM PDT 24
Peak memory 206308 kb
Host smart-4cd9f9d5-419a-4667-a413-867db9dc54b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2754857356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.2754857356
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1448574163
Short name T224
Test name
Test status
Simulation time 268689519 ps
CPU time 3.45 seconds
Started Jul 26 04:57:22 PM PDT 24
Finished Jul 26 04:57:25 PM PDT 24
Peak memory 220404 kb
Host smart-707ca5a6-036e-4751-b4b6-e4e0bc62d7a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1448574163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.1448574163
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2071043792
Short name T2957
Test name
Test status
Simulation time 831632880 ps
CPU time 3.24 seconds
Started Jul 26 04:56:57 PM PDT 24
Finished Jul 26 04:57:00 PM PDT 24
Peak memory 206292 kb
Host smart-7d453b02-9d21-446a-ba89-f960650d30d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2071043792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.2071043792
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.932202359
Short name T2930
Test name
Test status
Simulation time 175823913 ps
CPU time 1.73 seconds
Started Jul 26 04:57:16 PM PDT 24
Finished Jul 26 04:57:18 PM PDT 24
Peak memory 214540 kb
Host smart-6c4141ac-4b20-4bb0-a109-c93e13e065b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932202359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev
_csr_mem_rw_with_rand_reset.932202359
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.97346424
Short name T243
Test name
Test status
Simulation time 100151193 ps
CPU time 0.89 seconds
Started Jul 26 04:57:11 PM PDT 24
Finished Jul 26 04:57:12 PM PDT 24
Peak memory 205984 kb
Host smart-3df0ba89-2488-4a91-bfe7-8c1da86be419
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=97346424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.97346424
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3762192004
Short name T198
Test name
Test status
Simulation time 47965775 ps
CPU time 0.75 seconds
Started Jul 26 04:56:58 PM PDT 24
Finished Jul 26 04:56:59 PM PDT 24
Peak memory 206080 kb
Host smart-f9f8386d-a1bd-4f76-982c-33d054c1137b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3762192004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.3762192004
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3895168935
Short name T254
Test name
Test status
Simulation time 251660223 ps
CPU time 1.74 seconds
Started Jul 26 04:57:23 PM PDT 24
Finished Jul 26 04:57:25 PM PDT 24
Peak memory 206316 kb
Host smart-2ae1e505-c3fa-4aad-8242-69966a95286c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3895168935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.3895168935
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3201864227
Short name T2904
Test name
Test status
Simulation time 106548247 ps
CPU time 1.67 seconds
Started Jul 26 04:57:01 PM PDT 24
Finished Jul 26 04:57:03 PM PDT 24
Peak memory 206400 kb
Host smart-4e050264-5d6a-4182-acee-16a0562d3f08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3201864227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.3201864227
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.4231355092
Short name T297
Test name
Test status
Simulation time 805606737 ps
CPU time 4.72 seconds
Started Jul 26 04:57:22 PM PDT 24
Finished Jul 26 04:57:27 PM PDT 24
Peak memory 206384 kb
Host smart-276bcca6-8ade-4eb1-ad49-3f0930b7b491
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4231355092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.4231355092
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2158208261
Short name T2928
Test name
Test status
Simulation time 102151667 ps
CPU time 2.19 seconds
Started Jul 26 04:57:24 PM PDT 24
Finished Jul 26 04:57:26 PM PDT 24
Peak memory 214520 kb
Host smart-fb334a95-059b-4812-a5ec-0f05aa56ae15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158208261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.2158208261
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1794453074
Short name T256
Test name
Test status
Simulation time 52474398 ps
CPU time 0.83 seconds
Started Jul 26 04:57:23 PM PDT 24
Finished Jul 26 04:57:24 PM PDT 24
Peak memory 206096 kb
Host smart-bbb80575-7305-41c2-922f-ae4d6ae54621
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1794453074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.1794453074
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.4251019564
Short name T2913
Test name
Test status
Simulation time 42804158 ps
CPU time 0.74 seconds
Started Jul 26 04:56:59 PM PDT 24
Finished Jul 26 04:57:00 PM PDT 24
Peak memory 206012 kb
Host smart-1b5068d8-3900-4ce5-aa48-fad5c4f18056
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4251019564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.4251019564
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1316930376
Short name T2960
Test name
Test status
Simulation time 246554524 ps
CPU time 1.64 seconds
Started Jul 26 04:57:22 PM PDT 24
Finished Jul 26 04:57:24 PM PDT 24
Peak memory 206340 kb
Host smart-d0a2f70f-9d36-4eeb-8d51-762f9a3a77b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1316930376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.1316930376
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.657447802
Short name T2897
Test name
Test status
Simulation time 256482181 ps
CPU time 2.84 seconds
Started Jul 26 04:56:59 PM PDT 24
Finished Jul 26 04:57:02 PM PDT 24
Peak memory 222560 kb
Host smart-8fe45ac3-3f6b-469d-a90b-32bf539ef97f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=657447802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.657447802
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1889985711
Short name T211
Test name
Test status
Simulation time 741092958 ps
CPU time 4.9 seconds
Started Jul 26 04:57:01 PM PDT 24
Finished Jul 26 04:57:06 PM PDT 24
Peak memory 206376 kb
Host smart-d96dba28-16d9-4b49-bebc-33ec3aace2f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1889985711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.1889985711
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.4252101913
Short name T2975
Test name
Test status
Simulation time 174561166 ps
CPU time 2.07 seconds
Started Jul 26 04:57:16 PM PDT 24
Finished Jul 26 04:57:18 PM PDT 24
Peak memory 214716 kb
Host smart-7728bc59-a4a4-4255-bae0-b87e9ee741a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252101913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.4252101913
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2731344244
Short name T252
Test name
Test status
Simulation time 126873260 ps
CPU time 1.08 seconds
Started Jul 26 04:57:11 PM PDT 24
Finished Jul 26 04:57:12 PM PDT 24
Peak memory 206216 kb
Host smart-bd602acd-836c-4ee4-bd34-d0190c47f8ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2731344244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2731344244
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2731963792
Short name T261
Test name
Test status
Simulation time 120777065 ps
CPU time 1.16 seconds
Started Jul 26 04:57:09 PM PDT 24
Finished Jul 26 04:57:10 PM PDT 24
Peak memory 206068 kb
Host smart-a597e896-3606-402d-9cef-86be553870b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2731963792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.2731963792
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.991371102
Short name T188
Test name
Test status
Simulation time 89564444 ps
CPU time 2.51 seconds
Started Jul 26 04:57:07 PM PDT 24
Finished Jul 26 04:57:09 PM PDT 24
Peak memory 214508 kb
Host smart-20bea6a4-37d0-4d15-90fa-939d4de20ae1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991371102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev
_csr_mem_rw_with_rand_reset.991371102
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2972783524
Short name T2951
Test name
Test status
Simulation time 58494677 ps
CPU time 0.79 seconds
Started Jul 26 04:57:06 PM PDT 24
Finished Jul 26 04:57:07 PM PDT 24
Peak memory 206120 kb
Host smart-b5393746-b9d6-49e6-bc14-98ff7ef04cdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2972783524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2972783524
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.645649875
Short name T2889
Test name
Test status
Simulation time 87340205 ps
CPU time 0.79 seconds
Started Jul 26 04:57:20 PM PDT 24
Finished Jul 26 04:57:21 PM PDT 24
Peak memory 206008 kb
Host smart-adfacecf-3d99-4f3f-bdcf-f4ea15277cb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=645649875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.645649875
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1188006293
Short name T2919
Test name
Test status
Simulation time 93549799 ps
CPU time 1.15 seconds
Started Jul 26 04:57:20 PM PDT 24
Finished Jul 26 04:57:21 PM PDT 24
Peak memory 206424 kb
Host smart-54110f2b-326f-4944-a790-1ce17afe0aa0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1188006293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.1188006293
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.512282500
Short name T2887
Test name
Test status
Simulation time 208959025 ps
CPU time 2.48 seconds
Started Jul 26 04:57:09 PM PDT 24
Finished Jul 26 04:57:12 PM PDT 24
Peak memory 206332 kb
Host smart-5112dac5-7e1e-4c69-8726-9a684cafbd76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=512282500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.512282500
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.2594600948
Short name T1426
Test name
Test status
Simulation time 44047148 ps
CPU time 0.72 seconds
Started Jul 26 05:06:17 PM PDT 24
Finished Jul 26 05:06:18 PM PDT 24
Peak memory 207140 kb
Host smart-ec4e96f1-5040-4b0a-9549-ebdd9ae2db1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2594600948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.2594600948
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.3061347819
Short name T2375
Test name
Test status
Simulation time 3810328096 ps
CPU time 5.5 seconds
Started Jul 26 05:05:55 PM PDT 24
Finished Jul 26 05:06:00 PM PDT 24
Peak memory 207360 kb
Host smart-bb369d78-025b-4aa0-993f-1c07bf194288
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061347819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_disconnect.3061347819
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.3388531918
Short name T1416
Test name
Test status
Simulation time 13431927762 ps
CPU time 15.61 seconds
Started Jul 26 05:06:06 PM PDT 24
Finished Jul 26 05:06:22 PM PDT 24
Peak memory 207320 kb
Host smart-24a83411-0cc0-4013-a111-2fa89ce4b19d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388531918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.3388531918
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.3453989338
Short name T2084
Test name
Test status
Simulation time 23322098388 ps
CPU time 29.35 seconds
Started Jul 26 05:06:04 PM PDT 24
Finished Jul 26 05:06:34 PM PDT 24
Peak memory 207388 kb
Host smart-55955436-f815-47e7-9d73-1d921acde3f7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453989338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_resume.3453989338
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.1525353326
Short name T1183
Test name
Test status
Simulation time 214528773 ps
CPU time 0.92 seconds
Started Jul 26 05:06:07 PM PDT 24
Finished Jul 26 05:06:08 PM PDT 24
Peak memory 207100 kb
Host smart-fb664851-40e2-4f22-ab35-f85faefef38c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15253
53326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.1525353326
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.1889913367
Short name T2014
Test name
Test status
Simulation time 151382513 ps
CPU time 0.8 seconds
Started Jul 26 05:06:11 PM PDT 24
Finished Jul 26 05:06:12 PM PDT 24
Peak memory 207036 kb
Host smart-695fdac2-48df-4cb4-8859-fa08e8a859ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18899
13367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.1889913367
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.1965940573
Short name T440
Test name
Test status
Simulation time 321564471 ps
CPU time 1.27 seconds
Started Jul 26 05:06:07 PM PDT 24
Finished Jul 26 05:06:08 PM PDT 24
Peak memory 207024 kb
Host smart-3f3992fd-fa14-48be-9579-f03ad0b99022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19659
40573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.1965940573
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.1917554771
Short name T488
Test name
Test status
Simulation time 734841027 ps
CPU time 2.14 seconds
Started Jul 26 05:06:06 PM PDT 24
Finished Jul 26 05:06:09 PM PDT 24
Peak memory 207032 kb
Host smart-7a701eff-6443-453c-9ac3-f6a1900551fe
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1917554771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.1917554771
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.986089310
Short name T2675
Test name
Test status
Simulation time 16737139326 ps
CPU time 39.03 seconds
Started Jul 26 05:06:02 PM PDT 24
Finished Jul 26 05:06:41 PM PDT 24
Peak memory 207300 kb
Host smart-3b8443dc-21cc-41d4-987c-c77987172a8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98608
9310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.986089310
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_device_timeout.41295846
Short name T2607
Test name
Test status
Simulation time 1071297251 ps
CPU time 23.26 seconds
Started Jul 26 05:06:05 PM PDT 24
Finished Jul 26 05:06:28 PM PDT 24
Peak memory 207272 kb
Host smart-b4834d34-f7bf-49c3-b349-cc06e1ea2f44
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41295846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_timeout.41295846
Directory /workspace/0.usbdev_device_timeout/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.3568111683
Short name T540
Test name
Test status
Simulation time 359178642 ps
CPU time 1.27 seconds
Started Jul 26 05:06:03 PM PDT 24
Finished Jul 26 05:06:05 PM PDT 24
Peak memory 206992 kb
Host smart-32defabc-5e05-45b9-954f-b1ad43e9a5e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35681
11683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.3568111683
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.2891762945
Short name T2094
Test name
Test status
Simulation time 134389071 ps
CPU time 0.81 seconds
Started Jul 26 05:06:06 PM PDT 24
Finished Jul 26 05:06:07 PM PDT 24
Peak memory 207080 kb
Host smart-97a451d7-e1da-4459-9872-830aa099b0fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28917
62945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.2891762945
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_enable.2886432125
Short name T1620
Test name
Test status
Simulation time 45755050 ps
CPU time 0.72 seconds
Started Jul 26 05:06:05 PM PDT 24
Finished Jul 26 05:06:06 PM PDT 24
Peak memory 207024 kb
Host smart-6b76630e-304d-44e5-9d9b-1008522a65f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28864
32125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.2886432125
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.1675281633
Short name T915
Test name
Test status
Simulation time 957556482 ps
CPU time 2.53 seconds
Started Jul 26 05:06:02 PM PDT 24
Finished Jul 26 05:06:05 PM PDT 24
Peak memory 207336 kb
Host smart-67776f7f-920f-452d-be1a-852a10d7f8e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16752
81633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.1675281633
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.627958220
Short name T1934
Test name
Test status
Simulation time 185952578 ps
CPU time 2.54 seconds
Started Jul 26 05:06:06 PM PDT 24
Finished Jul 26 05:06:09 PM PDT 24
Peak memory 207344 kb
Host smart-a469a03d-e219-4e15-9368-957e8f0f964f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62795
8220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.627958220
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.2109818532
Short name T308
Test name
Test status
Simulation time 100331888230 ps
CPU time 153.91 seconds
Started Jul 26 05:06:06 PM PDT 24
Finished Jul 26 05:08:40 PM PDT 24
Peak memory 207356 kb
Host smart-851d69dc-9a71-4704-a26d-4ca729299def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109818532 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.2109818532
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.3911154885
Short name T2821
Test name
Test status
Simulation time 99227381884 ps
CPU time 156.08 seconds
Started Jul 26 05:06:03 PM PDT 24
Finished Jul 26 05:08:39 PM PDT 24
Peak memory 207312 kb
Host smart-64747664-1fcc-4578-a7a7-ebb0be418e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911154885 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.3911154885
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.3842887299
Short name T1935
Test name
Test status
Simulation time 98156369300 ps
CPU time 172.2 seconds
Started Jul 26 05:06:03 PM PDT 24
Finished Jul 26 05:08:55 PM PDT 24
Peak memory 207348 kb
Host smart-2a04d5e7-e6a5-4688-bfc9-945515a538e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38428
87299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.3842887299
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.385048548
Short name T1827
Test name
Test status
Simulation time 199170466 ps
CPU time 1.1 seconds
Started Jul 26 05:06:07 PM PDT 24
Finished Jul 26 05:06:08 PM PDT 24
Peak memory 215520 kb
Host smart-fac31e5a-b41b-4290-9639-ab1ee4ebf4be
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=385048548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.385048548
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.2937676154
Short name T1762
Test name
Test status
Simulation time 141321194 ps
CPU time 0.85 seconds
Started Jul 26 05:06:05 PM PDT 24
Finished Jul 26 05:06:06 PM PDT 24
Peak memory 207056 kb
Host smart-63178a27-debd-4a96-a9e8-79ac194432cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29376
76154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.2937676154
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.2044417776
Short name T2264
Test name
Test status
Simulation time 255000637 ps
CPU time 0.99 seconds
Started Jul 26 05:06:11 PM PDT 24
Finished Jul 26 05:06:12 PM PDT 24
Peak memory 207064 kb
Host smart-412855f5-6436-4481-a92c-639d9ed66994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20444
17776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.2044417776
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.3083420587
Short name T947
Test name
Test status
Simulation time 9118482651 ps
CPU time 68.35 seconds
Started Jul 26 05:06:04 PM PDT 24
Finished Jul 26 05:07:13 PM PDT 24
Peak memory 216700 kb
Host smart-20f90a9f-1ef8-4536-8a00-5e0394e1b884
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3083420587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.3083420587
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_iso_retraction.1181631273
Short name T1228
Test name
Test status
Simulation time 4813371373 ps
CPU time 34.02 seconds
Started Jul 26 05:06:06 PM PDT 24
Finished Jul 26 05:06:40 PM PDT 24
Peak memory 207320 kb
Host smart-c34e3f92-fcad-47eb-8826-66dcea83868c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1181631273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.1181631273
Directory /workspace/0.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.4135968231
Short name T1124
Test name
Test status
Simulation time 205131904 ps
CPU time 0.93 seconds
Started Jul 26 05:06:07 PM PDT 24
Finished Jul 26 05:06:08 PM PDT 24
Peak memory 207060 kb
Host smart-3568c4ee-b8b0-4141-b7aa-dd61380c8ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41359
68231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.4135968231
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.1867660509
Short name T70
Test name
Test status
Simulation time 517907745 ps
CPU time 1.68 seconds
Started Jul 26 05:06:04 PM PDT 24
Finished Jul 26 05:06:06 PM PDT 24
Peak memory 207024 kb
Host smart-f6868d30-5fb6-4105-9ac0-de1444d5fa06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18676
60509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.1867660509
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.3198525797
Short name T563
Test name
Test status
Simulation time 23358374895 ps
CPU time 29 seconds
Started Jul 26 05:06:07 PM PDT 24
Finished Jul 26 05:06:36 PM PDT 24
Peak memory 207384 kb
Host smart-0a83399b-5ba5-4335-82e3-cbae6d646a4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31985
25797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.3198525797
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.1556348518
Short name T1249
Test name
Test status
Simulation time 3330397447 ps
CPU time 4.72 seconds
Started Jul 26 05:06:05 PM PDT 24
Finished Jul 26 05:06:10 PM PDT 24
Peak memory 207324 kb
Host smart-5e35a93e-2706-48ed-9972-04a5fca8a068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15563
48518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.1556348518
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.521337011
Short name T1482
Test name
Test status
Simulation time 6131443106 ps
CPU time 68.81 seconds
Started Jul 26 05:06:02 PM PDT 24
Finished Jul 26 05:07:11 PM PDT 24
Peak memory 216864 kb
Host smart-461cb12f-5aea-44c0-84b2-c2f340bf3aa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52133
7011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.521337011
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.2511818296
Short name T1060
Test name
Test status
Simulation time 4250096394 ps
CPU time 123.42 seconds
Started Jul 26 05:06:08 PM PDT 24
Finished Jul 26 05:08:12 PM PDT 24
Peak memory 215568 kb
Host smart-5cb4c7f4-317c-46c0-85d6-36c73bfc6fe7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2511818296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.2511818296
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.3291463972
Short name T2002
Test name
Test status
Simulation time 240435308 ps
CPU time 0.97 seconds
Started Jul 26 05:06:08 PM PDT 24
Finished Jul 26 05:06:09 PM PDT 24
Peak memory 207156 kb
Host smart-0f862888-d636-46da-9e16-bac8842f67f8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3291463972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.3291463972
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.3570377494
Short name T327
Test name
Test status
Simulation time 200436288 ps
CPU time 1.01 seconds
Started Jul 26 05:06:04 PM PDT 24
Finished Jul 26 05:06:05 PM PDT 24
Peak memory 207048 kb
Host smart-480204ac-873b-4473-a35e-a83de35774f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35703
77494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.3570377494
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.2174542085
Short name T2614
Test name
Test status
Simulation time 6595502851 ps
CPU time 201.94 seconds
Started Jul 26 05:06:03 PM PDT 24
Finished Jul 26 05:09:25 PM PDT 24
Peak memory 215496 kb
Host smart-cddda79a-8c19-4c4a-bd52-492774a8c900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21745
42085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.2174542085
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.850147585
Short name T1976
Test name
Test status
Simulation time 5701047435 ps
CPU time 41.54 seconds
Started Jul 26 05:06:08 PM PDT 24
Finished Jul 26 05:06:49 PM PDT 24
Peak memory 207372 kb
Host smart-02c2ab17-c54d-4370-874e-27f02e67d4a6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=850147585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.850147585
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.1624159749
Short name T627
Test name
Test status
Simulation time 160667107 ps
CPU time 0.86 seconds
Started Jul 26 05:06:06 PM PDT 24
Finished Jul 26 05:06:07 PM PDT 24
Peak memory 207108 kb
Host smart-7f37c163-d5e9-42ac-aa49-aff309eccbb4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1624159749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.1624159749
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.218543869
Short name T2842
Test name
Test status
Simulation time 156492751 ps
CPU time 0.88 seconds
Started Jul 26 05:06:03 PM PDT 24
Finished Jul 26 05:06:04 PM PDT 24
Peak memory 207124 kb
Host smart-e3c95866-933a-4572-8f68-e2db0a4bea98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21854
3869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.218543869
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.1462981691
Short name T69
Test name
Test status
Simulation time 449802128 ps
CPU time 1.37 seconds
Started Jul 26 05:06:11 PM PDT 24
Finished Jul 26 05:06:13 PM PDT 24
Peak memory 207084 kb
Host smart-05a11b89-5f4e-49c4-b9b2-1c57b3e3632c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14629
81691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.1462981691
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.2821682773
Short name T1639
Test name
Test status
Simulation time 168153643 ps
CPU time 0.88 seconds
Started Jul 26 05:06:02 PM PDT 24
Finished Jul 26 05:06:03 PM PDT 24
Peak memory 207032 kb
Host smart-c512dd53-cd50-41c0-bd7b-1cd2e5b0407b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28216
82773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.2821682773
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.4096805657
Short name T2036
Test name
Test status
Simulation time 158742059 ps
CPU time 0.88 seconds
Started Jul 26 05:06:04 PM PDT 24
Finished Jul 26 05:06:05 PM PDT 24
Peak memory 207052 kb
Host smart-3f22b868-ea3c-4750-aa08-622e0165f967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40968
05657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.4096805657
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.3572305891
Short name T1776
Test name
Test status
Simulation time 184985399 ps
CPU time 0.9 seconds
Started Jul 26 05:06:02 PM PDT 24
Finished Jul 26 05:06:03 PM PDT 24
Peak memory 207104 kb
Host smart-6729243a-c367-4ae6-bf68-400f4d625a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35723
05891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.3572305891
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.3446807036
Short name T1020
Test name
Test status
Simulation time 152474578 ps
CPU time 0.87 seconds
Started Jul 26 05:06:02 PM PDT 24
Finished Jul 26 05:06:03 PM PDT 24
Peak memory 207120 kb
Host smart-1e8b7891-99be-469e-ac09-f48e4c4e4cf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34468
07036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.3446807036
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.635794243
Short name T881
Test name
Test status
Simulation time 184117862 ps
CPU time 0.88 seconds
Started Jul 26 05:06:04 PM PDT 24
Finished Jul 26 05:06:05 PM PDT 24
Peak memory 207024 kb
Host smart-b6f7f34f-00a0-4c91-ab2e-b91af6336d16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63579
4243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.635794243
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.42376919
Short name T2163
Test name
Test status
Simulation time 204955947 ps
CPU time 1.07 seconds
Started Jul 26 05:06:02 PM PDT 24
Finished Jul 26 05:06:03 PM PDT 24
Peak memory 207008 kb
Host smart-5b12e1e5-4628-48b1-964a-090264813563
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=42376919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.42376919
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.3476037058
Short name T2233
Test name
Test status
Simulation time 230802772 ps
CPU time 1 seconds
Started Jul 26 05:06:04 PM PDT 24
Finished Jul 26 05:06:05 PM PDT 24
Peak memory 207032 kb
Host smart-55bd13c7-0d51-4f44-a345-8a30e694502c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34760
37058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.3476037058
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.1173448189
Short name T1751
Test name
Test status
Simulation time 203480479 ps
CPU time 0.98 seconds
Started Jul 26 05:06:07 PM PDT 24
Finished Jul 26 05:06:08 PM PDT 24
Peak memory 207072 kb
Host smart-bb80ddf9-652d-4d7f-8f33-bdff6c6dec62
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1173448189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.1173448189
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.4007283355
Short name T194
Test name
Test status
Simulation time 217955808 ps
CPU time 1.02 seconds
Started Jul 26 05:06:03 PM PDT 24
Finished Jul 26 05:06:04 PM PDT 24
Peak memory 206976 kb
Host smart-fae63505-ab3e-4c8d-927c-3b027c4ceae8
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4007283355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.4007283355
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.1785535615
Short name T183
Test name
Test status
Simulation time 197173530 ps
CPU time 0.9 seconds
Started Jul 26 05:06:05 PM PDT 24
Finished Jul 26 05:06:06 PM PDT 24
Peak memory 207012 kb
Host smart-394aa030-b969-4622-856f-cbdba9578720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17855
35615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.1785535615
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.3663173432
Short name T233
Test name
Test status
Simulation time 20483306576 ps
CPU time 46.32 seconds
Started Jul 26 05:06:08 PM PDT 24
Finished Jul 26 05:06:54 PM PDT 24
Peak memory 215624 kb
Host smart-5b0c7567-0afe-4b73-bc5d-ba7ff6c1f8ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36631
73432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.3663173432
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.3798652058
Short name T973
Test name
Test status
Simulation time 177967295 ps
CPU time 0.9 seconds
Started Jul 26 05:06:07 PM PDT 24
Finished Jul 26 05:06:08 PM PDT 24
Peak memory 207100 kb
Host smart-58430841-d189-4585-b7f6-0b2457a32739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37986
52058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.3798652058
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.516021430
Short name T2087
Test name
Test status
Simulation time 258621078 ps
CPU time 1.02 seconds
Started Jul 26 05:06:11 PM PDT 24
Finished Jul 26 05:06:13 PM PDT 24
Peak memory 207040 kb
Host smart-bc01203c-98ba-450b-a453-3d345ae708c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51602
1430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.516021430
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.4174291225
Short name T800
Test name
Test status
Simulation time 12457665566 ps
CPU time 94.24 seconds
Started Jul 26 05:06:06 PM PDT 24
Finished Jul 26 05:07:40 PM PDT 24
Peak memory 217216 kb
Host smart-b1532514-1bff-477a-9acd-2325e368169d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174291225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.4174291225
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.1167060291
Short name T425
Test name
Test status
Simulation time 6828757530 ps
CPU time 32.06 seconds
Started Jul 26 05:06:07 PM PDT 24
Finished Jul 26 05:06:39 PM PDT 24
Peak memory 218944 kb
Host smart-e4c0538b-e55e-435d-b9e4-39ed99aeaeca
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167060291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.1167060291
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.3898685144
Short name T311
Test name
Test status
Simulation time 211969105 ps
CPU time 0.92 seconds
Started Jul 26 05:06:07 PM PDT 24
Finished Jul 26 05:06:08 PM PDT 24
Peak memory 207100 kb
Host smart-0a7e90f7-f494-4bab-be54-e482815dd1db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38986
85144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.3898685144
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.3641820438
Short name T1586
Test name
Test status
Simulation time 167291183 ps
CPU time 0.88 seconds
Started Jul 26 05:06:09 PM PDT 24
Finished Jul 26 05:06:10 PM PDT 24
Peak memory 207132 kb
Host smart-5dd7dc86-8eb4-4d96-afc7-85d35b4f2894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36418
20438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.3641820438
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.2565633979
Short name T2424
Test name
Test status
Simulation time 186947336 ps
CPU time 0.94 seconds
Started Jul 26 05:06:14 PM PDT 24
Finished Jul 26 05:06:15 PM PDT 24
Peak memory 206976 kb
Host smart-544bb0a8-e1f4-4d4f-8425-93eab98a8635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25656
33979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.2565633979
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.986408457
Short name T325
Test name
Test status
Simulation time 148445547 ps
CPU time 0.84 seconds
Started Jul 26 05:06:13 PM PDT 24
Finished Jul 26 05:06:14 PM PDT 24
Peak memory 207068 kb
Host smart-736e10ba-4a8d-46ca-8f3e-470c6f5d4072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98640
8457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.986408457
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1739400554
Short name T403
Test name
Test status
Simulation time 234874743 ps
CPU time 1.02 seconds
Started Jul 26 05:06:16 PM PDT 24
Finished Jul 26 05:06:17 PM PDT 24
Peak memory 207028 kb
Host smart-098d6da7-5b2d-4b00-aac8-87c24fbb1f2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17394
00554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1739400554
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.3774873325
Short name T2118
Test name
Test status
Simulation time 7476771224 ps
CPU time 73.22 seconds
Started Jul 26 05:06:13 PM PDT 24
Finished Jul 26 05:07:27 PM PDT 24
Peak memory 207336 kb
Host smart-f362e367-61cb-4445-b309-f44dfba5496f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3774873325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.3774873325
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.3665253886
Short name T2195
Test name
Test status
Simulation time 177444672 ps
CPU time 0.91 seconds
Started Jul 26 05:06:13 PM PDT 24
Finished Jul 26 05:06:14 PM PDT 24
Peak memory 207332 kb
Host smart-3b7fbdea-bf84-4a2e-b01d-17d2a6f37140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36652
53886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.3665253886
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.88756553
Short name T772
Test name
Test status
Simulation time 155041101 ps
CPU time 0.89 seconds
Started Jul 26 05:06:16 PM PDT 24
Finished Jul 26 05:06:17 PM PDT 24
Peak memory 207024 kb
Host smart-03aed16c-4a24-4ffe-8817-a06ccc9af8ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88756
553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.88756553
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.42616756
Short name T858
Test name
Test status
Simulation time 1201066939 ps
CPU time 2.68 seconds
Started Jul 26 05:06:15 PM PDT 24
Finished Jul 26 05:06:18 PM PDT 24
Peak memory 207240 kb
Host smart-bbdbbe28-2b81-46b3-8933-65834e49caa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42616
756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.42616756
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.1257426812
Short name T2130
Test name
Test status
Simulation time 4274814497 ps
CPU time 33.09 seconds
Started Jul 26 05:06:15 PM PDT 24
Finished Jul 26 05:06:48 PM PDT 24
Peak memory 207376 kb
Host smart-37b9a6aa-4e48-4bab-8957-7e2fde53442d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12574
26812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.1257426812
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_timeout_missing_host_handshake.800938795
Short name T2415
Test name
Test status
Simulation time 158723259 ps
CPU time 0.86 seconds
Started Jul 26 05:06:03 PM PDT 24
Finished Jul 26 05:06:04 PM PDT 24
Peak memory 207088 kb
Host smart-d0f95ad5-7733-4fd5-b0d8-4b892fb5229a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800938795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_timeout_missing_host_
handshake.800938795
Directory /workspace/0.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.897883398
Short name T1974
Test name
Test status
Simulation time 42047904 ps
CPU time 0.69 seconds
Started Jul 26 05:06:44 PM PDT 24
Finished Jul 26 05:06:45 PM PDT 24
Peak memory 207120 kb
Host smart-63c228ee-fafa-4179-af0c-bfedadf5baa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=897883398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.897883398
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.1107783837
Short name T2854
Test name
Test status
Simulation time 4073665902 ps
CPU time 5.67 seconds
Started Jul 26 05:06:15 PM PDT 24
Finished Jul 26 05:06:21 PM PDT 24
Peak memory 207360 kb
Host smart-0d046e28-1d40-4294-a41b-8947c06dc958
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107783837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ao
n_wake_disconnect.1107783837
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.590505995
Short name T1880
Test name
Test status
Simulation time 13346383697 ps
CPU time 15.53 seconds
Started Jul 26 05:06:18 PM PDT 24
Finished Jul 26 05:06:33 PM PDT 24
Peak memory 207392 kb
Host smart-e5468f13-ad12-41c4-946d-98c0f4703c15
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=590505995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.590505995
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.1544745701
Short name T1332
Test name
Test status
Simulation time 23400430749 ps
CPU time 30.63 seconds
Started Jul 26 05:06:15 PM PDT 24
Finished Jul 26 05:06:46 PM PDT 24
Peak memory 207336 kb
Host smart-8374404d-99b1-4402-ac33-b8723dd9a29c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544745701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ao
n_wake_resume.1544745701
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.3866515730
Short name T360
Test name
Test status
Simulation time 182972574 ps
CPU time 0.94 seconds
Started Jul 26 05:06:14 PM PDT 24
Finished Jul 26 05:06:15 PM PDT 24
Peak memory 207080 kb
Host smart-b005df76-50f5-4c67-af70-0d3df55dd373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38665
15730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.3866515730
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.2237183144
Short name T1299
Test name
Test status
Simulation time 152276127 ps
CPU time 0.85 seconds
Started Jul 26 05:06:14 PM PDT 24
Finished Jul 26 05:06:15 PM PDT 24
Peak memory 207004 kb
Host smart-5c49c972-0491-4c8b-8260-f44ac017e3aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22371
83144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.2237183144
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.2397961390
Short name T1021
Test name
Test status
Simulation time 263494313 ps
CPU time 1.08 seconds
Started Jul 26 05:06:15 PM PDT 24
Finished Jul 26 05:06:17 PM PDT 24
Peak memory 207040 kb
Host smart-69a681b3-eba1-45ed-9676-706abd8c42e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23979
61390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.2397961390
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.4053149786
Short name T465
Test name
Test status
Simulation time 1001173820 ps
CPU time 2.81 seconds
Started Jul 26 05:06:14 PM PDT 24
Finished Jul 26 05:06:16 PM PDT 24
Peak memory 207212 kb
Host smart-4bff2373-f25d-48aa-b4ad-f9fb18d7ecb4
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4053149786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.4053149786
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.4119566775
Short name T2835
Test name
Test status
Simulation time 20621850796 ps
CPU time 46.08 seconds
Started Jul 26 05:06:14 PM PDT 24
Finished Jul 26 05:07:01 PM PDT 24
Peak memory 207340 kb
Host smart-78af4bed-4718-4822-97f4-7da872613cc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41195
66775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.4119566775
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_device_timeout.744587068
Short name T533
Test name
Test status
Simulation time 587309105 ps
CPU time 12.49 seconds
Started Jul 26 05:06:15 PM PDT 24
Finished Jul 26 05:06:28 PM PDT 24
Peak memory 207204 kb
Host smart-29c8b34a-5e9a-46c0-a813-562e5e813c13
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744587068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_timeout.744587068
Directory /workspace/1.usbdev_device_timeout/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.47891106
Short name T2138
Test name
Test status
Simulation time 435504366 ps
CPU time 1.56 seconds
Started Jul 26 05:06:17 PM PDT 24
Finished Jul 26 05:06:19 PM PDT 24
Peak memory 207092 kb
Host smart-4390d5e8-c415-4cf0-9f25-025660c4df92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47891
106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.47891106
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.2708623661
Short name T1929
Test name
Test status
Simulation time 226534080 ps
CPU time 0.96 seconds
Started Jul 26 05:06:14 PM PDT 24
Finished Jul 26 05:06:15 PM PDT 24
Peak memory 207080 kb
Host smart-97ddeb34-a4e8-4d11-83d6-a0e3c19d74cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27086
23661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.2708623661
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.3393420582
Short name T797
Test name
Test status
Simulation time 45072862 ps
CPU time 0.73 seconds
Started Jul 26 05:06:16 PM PDT 24
Finished Jul 26 05:06:17 PM PDT 24
Peak memory 207092 kb
Host smart-18924399-cb67-433f-bc23-343fabd3ddb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33934
20582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.3393420582
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.1591155567
Short name T2655
Test name
Test status
Simulation time 979011122 ps
CPU time 2.72 seconds
Started Jul 26 05:06:15 PM PDT 24
Finished Jul 26 05:06:18 PM PDT 24
Peak memory 207272 kb
Host smart-cadaa5a7-0a42-45f9-b7c1-f73e2840fd02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15911
55567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.1591155567
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.3689058798
Short name T1915
Test name
Test status
Simulation time 178827614 ps
CPU time 2.19 seconds
Started Jul 26 05:06:17 PM PDT 24
Finished Jul 26 05:06:20 PM PDT 24
Peak memory 207296 kb
Host smart-ac649386-5163-49d0-a811-59f9f48273b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36890
58798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.3689058798
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.344380820
Short name T735
Test name
Test status
Simulation time 96172542500 ps
CPU time 154.58 seconds
Started Jul 26 05:06:14 PM PDT 24
Finished Jul 26 05:08:49 PM PDT 24
Peak memory 207264 kb
Host smart-bc377262-e057-4d62-903c-1116163b65de
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=344380820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.344380820
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.2204144637
Short name T306
Test name
Test status
Simulation time 114235218854 ps
CPU time 193.97 seconds
Started Jul 26 05:06:15 PM PDT 24
Finished Jul 26 05:09:29 PM PDT 24
Peak memory 207288 kb
Host smart-1894f309-e256-48d6-ad9e-b38ea28c25bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204144637 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.2204144637
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.43485915
Short name T2845
Test name
Test status
Simulation time 88130119477 ps
CPU time 134.55 seconds
Started Jul 26 05:06:16 PM PDT 24
Finished Jul 26 05:08:31 PM PDT 24
Peak memory 207240 kb
Host smart-66aff132-0381-48cc-aa60-b789a4359ffb
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=43485915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.43485915
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.2507114215
Short name T2777
Test name
Test status
Simulation time 111213807381 ps
CPU time 177.94 seconds
Started Jul 26 05:06:14 PM PDT 24
Finished Jul 26 05:09:12 PM PDT 24
Peak memory 207284 kb
Host smart-65d52390-8976-49da-b35b-a92c4c3f3d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507114215 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.2507114215
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.294143604
Short name T2247
Test name
Test status
Simulation time 90166069736 ps
CPU time 149.2 seconds
Started Jul 26 05:06:37 PM PDT 24
Finished Jul 26 05:09:07 PM PDT 24
Peak memory 207464 kb
Host smart-01c74d22-67ea-4f32-9e42-516dee02a3b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29414
3604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.294143604
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.3374603628
Short name T2493
Test name
Test status
Simulation time 215189374 ps
CPU time 1.22 seconds
Started Jul 26 05:06:32 PM PDT 24
Finished Jul 26 05:06:34 PM PDT 24
Peak memory 215748 kb
Host smart-943c3c7b-9604-4903-b01a-4220e74653fa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3374603628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.3374603628
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.1788131719
Short name T2478
Test name
Test status
Simulation time 203709042 ps
CPU time 0.94 seconds
Started Jul 26 05:06:30 PM PDT 24
Finished Jul 26 05:06:31 PM PDT 24
Peak memory 207004 kb
Host smart-65503155-bf6c-4380-b0ca-5282a317bae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17881
31719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.1788131719
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.2080029084
Short name T2140
Test name
Test status
Simulation time 235679569 ps
CPU time 1.11 seconds
Started Jul 26 05:06:31 PM PDT 24
Finished Jul 26 05:06:33 PM PDT 24
Peak memory 207156 kb
Host smart-bba6c54d-5f54-47ec-af94-a7bf79dfe0fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20800
29084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.2080029084
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.2039547682
Short name T1875
Test name
Test status
Simulation time 3881610570 ps
CPU time 119.09 seconds
Started Jul 26 05:06:31 PM PDT 24
Finished Jul 26 05:08:31 PM PDT 24
Peak memory 215456 kb
Host smart-6c0975d5-5be9-4c56-9cde-b6758af24eb1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2039547682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.2039547682
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_iso_retraction.3319548268
Short name T2288
Test name
Test status
Simulation time 5099988647 ps
CPU time 64.71 seconds
Started Jul 26 05:06:34 PM PDT 24
Finished Jul 26 05:07:39 PM PDT 24
Peak memory 207376 kb
Host smart-dbce093e-101a-4e78-bf03-c61d82a79e67
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3319548268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.3319548268
Directory /workspace/1.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.1868907669
Short name T1127
Test name
Test status
Simulation time 233365262 ps
CPU time 0.98 seconds
Started Jul 26 05:06:32 PM PDT 24
Finished Jul 26 05:06:34 PM PDT 24
Peak memory 207132 kb
Host smart-c2074241-c6f9-45cb-a901-7eca53d1f9b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18689
07669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.1868907669
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.474910251
Short name T2189
Test name
Test status
Simulation time 23283021201 ps
CPU time 29.35 seconds
Started Jul 26 05:06:33 PM PDT 24
Finished Jul 26 05:07:02 PM PDT 24
Peak memory 207340 kb
Host smart-4854ef9a-3345-40d6-9e51-0e797fb091cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47491
0251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.474910251
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.496728372
Short name T334
Test name
Test status
Simulation time 3315556324 ps
CPU time 5.44 seconds
Started Jul 26 05:06:32 PM PDT 24
Finished Jul 26 05:06:38 PM PDT 24
Peak memory 207580 kb
Host smart-c02d5323-d115-4863-af8d-51bbca08aa6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49672
8372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.496728372
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.2411928756
Short name T743
Test name
Test status
Simulation time 5082439496 ps
CPU time 54.39 seconds
Started Jul 26 05:06:32 PM PDT 24
Finished Jul 26 05:07:26 PM PDT 24
Peak memory 217324 kb
Host smart-3b46a009-83de-4c5f-88bc-29ee70207133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24119
28756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.2411928756
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.107912206
Short name T415
Test name
Test status
Simulation time 4895850099 ps
CPU time 153.02 seconds
Started Jul 26 05:06:31 PM PDT 24
Finished Jul 26 05:09:05 PM PDT 24
Peak memory 215600 kb
Host smart-62f54ed5-c77d-49ca-89af-7f54096d5a90
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=107912206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.107912206
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.1267667462
Short name T1660
Test name
Test status
Simulation time 258786025 ps
CPU time 1.14 seconds
Started Jul 26 05:06:33 PM PDT 24
Finished Jul 26 05:06:35 PM PDT 24
Peak memory 207056 kb
Host smart-1b21ee83-bcd9-42e9-b3a1-a081df9c8e1a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1267667462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.1267667462
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.1490986714
Short name T341
Test name
Test status
Simulation time 186779892 ps
CPU time 0.97 seconds
Started Jul 26 05:06:35 PM PDT 24
Finished Jul 26 05:06:36 PM PDT 24
Peak memory 207128 kb
Host smart-fb74678d-5a26-4267-92bb-a0d5e1880dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14909
86714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.1490986714
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.1186341295
Short name T1113
Test name
Test status
Simulation time 7210223928 ps
CPU time 199.14 seconds
Started Jul 26 05:06:34 PM PDT 24
Finished Jul 26 05:09:53 PM PDT 24
Peak memory 215536 kb
Host smart-05603a23-312c-456a-8897-8745bc84db26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11863
41295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.1186341295
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.2441052854
Short name T2703
Test name
Test status
Simulation time 3538797695 ps
CPU time 107.43 seconds
Started Jul 26 05:06:31 PM PDT 24
Finished Jul 26 05:08:19 PM PDT 24
Peak memory 215516 kb
Host smart-248c57fc-a5d3-46f9-af8b-539d3067c5d1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2441052854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.2441052854
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.556338034
Short name T146
Test name
Test status
Simulation time 151824216 ps
CPU time 0.86 seconds
Started Jul 26 05:06:30 PM PDT 24
Finished Jul 26 05:06:31 PM PDT 24
Peak memory 207036 kb
Host smart-cbd8a907-ac4b-4076-bf75-16c1fa73b4c8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=556338034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.556338034
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.3130471569
Short name T1219
Test name
Test status
Simulation time 148238091 ps
CPU time 0.92 seconds
Started Jul 26 05:06:34 PM PDT 24
Finished Jul 26 05:06:35 PM PDT 24
Peak memory 207044 kb
Host smart-751bd823-9705-4a9c-bf7f-da6e354bdd86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31304
71569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.3130471569
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.2558162718
Short name T751
Test name
Test status
Simulation time 194337011 ps
CPU time 0.91 seconds
Started Jul 26 05:06:31 PM PDT 24
Finished Jul 26 05:06:32 PM PDT 24
Peak memory 206936 kb
Host smart-c1f4f1ac-43ee-4d77-9b77-8b92b3122f91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25581
62718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.2558162718
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.2406398922
Short name T2109
Test name
Test status
Simulation time 204882038 ps
CPU time 0.92 seconds
Started Jul 26 05:06:32 PM PDT 24
Finished Jul 26 05:06:33 PM PDT 24
Peak memory 207124 kb
Host smart-498d0936-d580-42da-befb-e8b11b2358b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24063
98922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.2406398922
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.1505353620
Short name T1335
Test name
Test status
Simulation time 145134024 ps
CPU time 0.86 seconds
Started Jul 26 05:06:33 PM PDT 24
Finished Jul 26 05:06:34 PM PDT 24
Peak memory 207100 kb
Host smart-b309a8d6-8887-4084-bec8-f9a387e52262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15053
53620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.1505353620
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.1128986744
Short name T174
Test name
Test status
Simulation time 149676081 ps
CPU time 0.88 seconds
Started Jul 26 05:06:33 PM PDT 24
Finished Jul 26 05:06:34 PM PDT 24
Peak memory 207136 kb
Host smart-2f368e57-ab7d-43cb-ab75-93e69cd233bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11289
86744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.1128986744
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.955316225
Short name T2630
Test name
Test status
Simulation time 216156667 ps
CPU time 0.96 seconds
Started Jul 26 05:06:32 PM PDT 24
Finished Jul 26 05:06:33 PM PDT 24
Peak memory 207140 kb
Host smart-505ff6fd-b5a7-4c1d-9197-9b3ea15b7176
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=955316225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.955316225
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.354477026
Short name T2081
Test name
Test status
Simulation time 229492493 ps
CPU time 1.11 seconds
Started Jul 26 05:06:34 PM PDT 24
Finished Jul 26 05:06:35 PM PDT 24
Peak memory 207152 kb
Host smart-ee88011a-4007-4eb7-a2e7-350abe7fb176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35447
7026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.354477026
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.1853608825
Short name T2797
Test name
Test status
Simulation time 145946411 ps
CPU time 0.83 seconds
Started Jul 26 05:06:30 PM PDT 24
Finished Jul 26 05:06:31 PM PDT 24
Peak memory 207048 kb
Host smart-8187021d-7454-427c-997c-38fb13403119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18536
08825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.1853608825
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.3963392891
Short name T704
Test name
Test status
Simulation time 38260756 ps
CPU time 0.7 seconds
Started Jul 26 05:06:32 PM PDT 24
Finished Jul 26 05:06:33 PM PDT 24
Peak memory 206988 kb
Host smart-cefc0171-7a7d-4332-a8bb-1e0d415e47a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39633
92891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.3963392891
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.468165575
Short name T2396
Test name
Test status
Simulation time 18672808730 ps
CPU time 47.54 seconds
Started Jul 26 05:06:32 PM PDT 24
Finished Jul 26 05:07:20 PM PDT 24
Peak memory 215464 kb
Host smart-c55e0d47-81a1-4580-89ce-9cca1144ebc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46816
5575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.468165575
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.879001597
Short name T615
Test name
Test status
Simulation time 201320850 ps
CPU time 0.92 seconds
Started Jul 26 05:06:31 PM PDT 24
Finished Jul 26 05:06:32 PM PDT 24
Peak memory 207084 kb
Host smart-b6e7aed6-a19e-4804-97d9-c918da68af41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87900
1597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.879001597
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.4250187552
Short name T1161
Test name
Test status
Simulation time 239747314 ps
CPU time 0.99 seconds
Started Jul 26 05:06:31 PM PDT 24
Finished Jul 26 05:06:32 PM PDT 24
Peak memory 207000 kb
Host smart-8712f33d-67bc-4e00-8f9f-5efe7d45ac97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42501
87552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.4250187552
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.290507102
Short name T629
Test name
Test status
Simulation time 7195698653 ps
CPU time 116.08 seconds
Started Jul 26 05:06:31 PM PDT 24
Finished Jul 26 05:08:28 PM PDT 24
Peak memory 215568 kb
Host smart-b81fc32d-8e70-4cc7-8ff8-9bad13116ffb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=290507102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.290507102
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.44720992
Short name T1889
Test name
Test status
Simulation time 7289372149 ps
CPU time 36.2 seconds
Started Jul 26 05:06:31 PM PDT 24
Finished Jul 26 05:07:08 PM PDT 24
Peak memory 218356 kb
Host smart-50993c4d-98f7-47fb-a3b8-3060601650e3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=44720992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.44720992
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.3400240221
Short name T2026
Test name
Test status
Simulation time 226791873 ps
CPU time 0.96 seconds
Started Jul 26 05:06:31 PM PDT 24
Finished Jul 26 05:06:32 PM PDT 24
Peak memory 207124 kb
Host smart-bbb157ae-9810-447a-9690-db631fb708ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34002
40221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.3400240221
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.802796630
Short name T2361
Test name
Test status
Simulation time 225652724 ps
CPU time 1.02 seconds
Started Jul 26 05:06:32 PM PDT 24
Finished Jul 26 05:06:33 PM PDT 24
Peak memory 207044 kb
Host smart-be239e3d-6307-40c8-b1cc-a5ea038c507b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80279
6630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.802796630
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.250267500
Short name T1155
Test name
Test status
Simulation time 192442453 ps
CPU time 0.91 seconds
Started Jul 26 05:06:29 PM PDT 24
Finished Jul 26 05:06:30 PM PDT 24
Peak memory 207112 kb
Host smart-d02ac94a-e042-416f-9026-97f62b28c4fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25026
7500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.250267500
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.593122381
Short name T78
Test name
Test status
Simulation time 184464037 ps
CPU time 0.91 seconds
Started Jul 26 05:06:30 PM PDT 24
Finished Jul 26 05:06:31 PM PDT 24
Peak memory 207020 kb
Host smart-df94969b-8127-4569-b14e-1a961c4b26ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59312
2381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.593122381
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.4036663106
Short name T202
Test name
Test status
Simulation time 313661380 ps
CPU time 1.15 seconds
Started Jul 26 05:06:32 PM PDT 24
Finished Jul 26 05:06:33 PM PDT 24
Peak memory 222900 kb
Host smart-8b630bb4-e12f-482c-b494-47c414c18ab5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4036663106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.4036663106
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.1580811366
Short name T2342
Test name
Test status
Simulation time 342052689 ps
CPU time 1.3 seconds
Started Jul 26 05:06:32 PM PDT 24
Finished Jul 26 05:06:33 PM PDT 24
Peak memory 207048 kb
Host smart-0220ea11-f243-44b2-86cf-465d67297d13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15808
11366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.1580811366
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.2148583158
Short name T1327
Test name
Test status
Simulation time 248668270 ps
CPU time 1.05 seconds
Started Jul 26 05:06:34 PM PDT 24
Finished Jul 26 05:06:35 PM PDT 24
Peak memory 207100 kb
Host smart-af428023-1cdc-4f55-af2f-99ff3ba320bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21485
83158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.2148583158
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.2818815004
Short name T2520
Test name
Test status
Simulation time 174189073 ps
CPU time 0.89 seconds
Started Jul 26 05:06:34 PM PDT 24
Finished Jul 26 05:06:35 PM PDT 24
Peak memory 207060 kb
Host smart-3ac93cbb-96a4-45e2-b448-c3b9ca235808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28188
15004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.2818815004
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.319857311
Short name T1010
Test name
Test status
Simulation time 210101105 ps
CPU time 0.94 seconds
Started Jul 26 05:06:32 PM PDT 24
Finished Jul 26 05:06:34 PM PDT 24
Peak memory 207040 kb
Host smart-2b7a2cdb-1dd5-4eda-817b-511b699b4fb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31985
7311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.319857311
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.2196196822
Short name T2557
Test name
Test status
Simulation time 213585386 ps
CPU time 0.98 seconds
Started Jul 26 05:06:33 PM PDT 24
Finished Jul 26 05:06:34 PM PDT 24
Peak memory 207008 kb
Host smart-b0fb2d6e-3da3-42fd-9e2e-5ba591648ebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21961
96822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.2196196822
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.2381627100
Short name T1383
Test name
Test status
Simulation time 5857001374 ps
CPU time 46.24 seconds
Started Jul 26 05:06:31 PM PDT 24
Finished Jul 26 05:07:18 PM PDT 24
Peak memory 216916 kb
Host smart-89d17aeb-d340-47db-93ae-9756d910209f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2381627100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.2381627100
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.1921750737
Short name T1192
Test name
Test status
Simulation time 172861140 ps
CPU time 0.83 seconds
Started Jul 26 05:06:31 PM PDT 24
Finished Jul 26 05:06:32 PM PDT 24
Peak memory 206952 kb
Host smart-b8689814-4de6-41ff-8a5e-8c87aceac350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19217
50737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.1921750737
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.254670668
Short name T428
Test name
Test status
Simulation time 162392308 ps
CPU time 0.91 seconds
Started Jul 26 05:06:33 PM PDT 24
Finished Jul 26 05:06:34 PM PDT 24
Peak memory 207124 kb
Host smart-3959bf18-dbfc-4d0a-bbd5-53f46292fbca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25467
0668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.254670668
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.1944478055
Short name T1331
Test name
Test status
Simulation time 654497056 ps
CPU time 2.04 seconds
Started Jul 26 05:06:32 PM PDT 24
Finished Jul 26 05:06:35 PM PDT 24
Peak memory 207096 kb
Host smart-a65bba4d-1c63-4762-8fd1-3c8d114e5d01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19444
78055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.1944478055
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.3369782277
Short name T1016
Test name
Test status
Simulation time 5106434677 ps
CPU time 160.76 seconds
Started Jul 26 05:06:33 PM PDT 24
Finished Jul 26 05:09:14 PM PDT 24
Peak memory 215592 kb
Host smart-c64be204-bfca-4d5b-bf7b-c229d2b569df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33697
82277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.3369782277
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.3962442799
Short name T167
Test name
Test status
Simulation time 11153208738 ps
CPU time 221.37 seconds
Started Jul 26 05:06:32 PM PDT 24
Finished Jul 26 05:10:13 PM PDT 24
Peak memory 215492 kb
Host smart-4d1b776c-0e5b-4247-955a-e4315de8ba32
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962442799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.3962442799
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_timeout_missing_host_handshake.1980055032
Short name T2729
Test name
Test status
Simulation time 4356869421 ps
CPU time 29.25 seconds
Started Jul 26 05:06:17 PM PDT 24
Finished Jul 26 05:06:46 PM PDT 24
Peak memory 207428 kb
Host smart-d9d59a96-012e-4d8b-8a3b-8f7d1ea61cd5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980055032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_timeout_missing_host
_handshake.1980055032
Directory /workspace/1.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.2871222401
Short name T930
Test name
Test status
Simulation time 69578720 ps
CPU time 0.69 seconds
Started Jul 26 05:08:52 PM PDT 24
Finished Jul 26 05:08:53 PM PDT 24
Peak memory 207080 kb
Host smart-38547b82-0bff-4074-9aca-00f7b11d6abc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2871222401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.2871222401
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.3308472419
Short name T478
Test name
Test status
Simulation time 4072142976 ps
CPU time 5.78 seconds
Started Jul 26 05:08:41 PM PDT 24
Finished Jul 26 05:08:47 PM PDT 24
Peak memory 207408 kb
Host smart-dc269983-cbf0-4446-b79d-c06730b587ca
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308472419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_a
on_wake_disconnect.3308472419
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.3602613229
Short name T2796
Test name
Test status
Simulation time 13308478385 ps
CPU time 16.95 seconds
Started Jul 26 05:08:38 PM PDT 24
Finished Jul 26 05:08:55 PM PDT 24
Peak memory 207448 kb
Host smart-61b2c9bf-60a5-4951-a9fa-abaf49226640
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602613229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.3602613229
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.3768152632
Short name T1336
Test name
Test status
Simulation time 23411741148 ps
CPU time 32.3 seconds
Started Jul 26 05:08:41 PM PDT 24
Finished Jul 26 05:09:13 PM PDT 24
Peak memory 207304 kb
Host smart-c8cc8e04-61ce-43f6-ba75-0c03c93fbc4d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768152632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_a
on_wake_resume.3768152632
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.2307160036
Short name T1284
Test name
Test status
Simulation time 190634316 ps
CPU time 0.94 seconds
Started Jul 26 05:08:42 PM PDT 24
Finished Jul 26 05:08:43 PM PDT 24
Peak memory 207036 kb
Host smart-6e1218db-39d7-48b7-bafd-d7a0731cea07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23071
60036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.2307160036
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.918650287
Short name T2022
Test name
Test status
Simulation time 144138144 ps
CPU time 0.85 seconds
Started Jul 26 05:08:41 PM PDT 24
Finished Jul 26 05:08:42 PM PDT 24
Peak memory 206940 kb
Host smart-069072a8-4734-457e-83c9-b12551e4327d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91865
0287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.918650287
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.2328031134
Short name T2098
Test name
Test status
Simulation time 249274085 ps
CPU time 1.1 seconds
Started Jul 26 05:08:43 PM PDT 24
Finished Jul 26 05:08:45 PM PDT 24
Peak memory 207040 kb
Host smart-6a9815fc-f583-450a-9716-3b6f5f740154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23280
31134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.2328031134
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.2537675651
Short name T1434
Test name
Test status
Simulation time 1226446082 ps
CPU time 3.07 seconds
Started Jul 26 05:08:40 PM PDT 24
Finished Jul 26 05:08:43 PM PDT 24
Peak memory 207360 kb
Host smart-89261edc-c2eb-4b14-8f31-f01fa20bf5d7
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2537675651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.2537675651
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.2447365512
Short name T1663
Test name
Test status
Simulation time 19577715168 ps
CPU time 41.5 seconds
Started Jul 26 05:08:42 PM PDT 24
Finished Jul 26 05:09:23 PM PDT 24
Peak memory 207320 kb
Host smart-8674042a-f0a3-4660-92a7-d5b8bca5bc60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24473
65512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.2447365512
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_device_timeout.1831141676
Short name T1821
Test name
Test status
Simulation time 4361671910 ps
CPU time 28.59 seconds
Started Jul 26 05:08:40 PM PDT 24
Finished Jul 26 05:09:08 PM PDT 24
Peak memory 207400 kb
Host smart-94c2f22f-9d13-411b-b60d-0ce9cea13b16
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831141676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_timeout.1831141676
Directory /workspace/10.usbdev_device_timeout/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.752705831
Short name T1111
Test name
Test status
Simulation time 398673094 ps
CPU time 1.59 seconds
Started Jul 26 05:08:38 PM PDT 24
Finished Jul 26 05:08:40 PM PDT 24
Peak memory 207048 kb
Host smart-6e2d1b4b-6fe0-4fb1-abe1-81d7efd3fcd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75270
5831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.752705831
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.2547858356
Short name T2232
Test name
Test status
Simulation time 208116760 ps
CPU time 0.89 seconds
Started Jul 26 05:08:41 PM PDT 24
Finished Jul 26 05:08:42 PM PDT 24
Peak memory 207012 kb
Host smart-c36bb476-d808-482e-a559-4aa97a3dc98a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25478
58356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.2547858356
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.3479228812
Short name T1850
Test name
Test status
Simulation time 60732353 ps
CPU time 0.72 seconds
Started Jul 26 05:08:42 PM PDT 24
Finished Jul 26 05:08:43 PM PDT 24
Peak memory 207060 kb
Host smart-4ce4546a-ec9e-4cbf-88a0-67ce3c74f3eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34792
28812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.3479228812
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.1655361396
Short name T576
Test name
Test status
Simulation time 781490268 ps
CPU time 2.46 seconds
Started Jul 26 05:08:41 PM PDT 24
Finished Jul 26 05:08:44 PM PDT 24
Peak memory 207352 kb
Host smart-b939f708-6e30-4c1a-9dd8-eb7334dc728b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16553
61396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.1655361396
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.2069203221
Short name T2231
Test name
Test status
Simulation time 192958630 ps
CPU time 2.32 seconds
Started Jul 26 05:08:41 PM PDT 24
Finished Jul 26 05:08:44 PM PDT 24
Peak memory 207344 kb
Host smart-a2c5524c-de66-4b70-a411-ccf3b2a38226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20692
03221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.2069203221
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.3841025318
Short name T2269
Test name
Test status
Simulation time 198383681 ps
CPU time 0.95 seconds
Started Jul 26 05:08:39 PM PDT 24
Finished Jul 26 05:08:40 PM PDT 24
Peak memory 207140 kb
Host smart-c4a7fe98-b3e5-4a52-b31a-896c0e1f424d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3841025318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.3841025318
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.4039086745
Short name T1997
Test name
Test status
Simulation time 136924037 ps
CPU time 0.83 seconds
Started Jul 26 05:08:39 PM PDT 24
Finished Jul 26 05:08:40 PM PDT 24
Peak memory 207104 kb
Host smart-d1b28739-30ab-43cd-bb87-2ed137f31150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40390
86745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.4039086745
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.233766504
Short name T332
Test name
Test status
Simulation time 211969374 ps
CPU time 0.95 seconds
Started Jul 26 05:08:42 PM PDT 24
Finished Jul 26 05:08:43 PM PDT 24
Peak memory 207032 kb
Host smart-98e284fc-81b5-4d9a-872b-65d98137d782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23376
6504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.233766504
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_invalid_sync.84741109
Short name T1528
Test name
Test status
Simulation time 8797178423 ps
CPU time 91.94 seconds
Started Jul 26 05:08:42 PM PDT 24
Finished Jul 26 05:10:14 PM PDT 24
Peak memory 215496 kb
Host smart-4fb2040b-ffa7-46ff-b914-8f28f049ac46
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=84741109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.84741109
Directory /workspace/10.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_iso_retraction.3104711888
Short name T2713
Test name
Test status
Simulation time 7606263746 ps
CPU time 51.61 seconds
Started Jul 26 05:08:43 PM PDT 24
Finished Jul 26 05:09:35 PM PDT 24
Peak memory 207236 kb
Host smart-48488f11-c50a-410d-8d62-db9c5a91abac
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3104711888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.3104711888
Directory /workspace/10.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.1550597879
Short name T2785
Test name
Test status
Simulation time 213400114 ps
CPU time 0.97 seconds
Started Jul 26 05:08:44 PM PDT 24
Finished Jul 26 05:08:45 PM PDT 24
Peak memory 207084 kb
Host smart-f8eda3be-8130-42ea-81ce-2c62c6f57c41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15505
97879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.1550597879
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.3474185011
Short name T834
Test name
Test status
Simulation time 23313082137 ps
CPU time 31.13 seconds
Started Jul 26 05:08:39 PM PDT 24
Finished Jul 26 05:09:11 PM PDT 24
Peak memory 207272 kb
Host smart-e505d0e2-9039-4acf-9956-2ddb9642f7e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34741
85011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.3474185011
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.4178973819
Short name T2711
Test name
Test status
Simulation time 3305381182 ps
CPU time 5.01 seconds
Started Jul 26 05:08:43 PM PDT 24
Finished Jul 26 05:08:48 PM PDT 24
Peak memory 207320 kb
Host smart-3f0248a8-a814-4d76-a469-76561699aae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41789
73819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.4178973819
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.519286546
Short name T2261
Test name
Test status
Simulation time 6410063548 ps
CPU time 60.77 seconds
Started Jul 26 05:08:55 PM PDT 24
Finished Jul 26 05:09:56 PM PDT 24
Peak memory 217400 kb
Host smart-d1bde1d0-c522-4450-b66e-3115816403f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51928
6546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.519286546
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.15321653
Short name T2540
Test name
Test status
Simulation time 6205671822 ps
CPU time 188.25 seconds
Started Jul 26 05:08:52 PM PDT 24
Finished Jul 26 05:12:01 PM PDT 24
Peak memory 215600 kb
Host smart-02b0203f-e047-46b4-b22d-d3c100562c0f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=15321653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.15321653
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.1729129673
Short name T355
Test name
Test status
Simulation time 248939773 ps
CPU time 1.01 seconds
Started Jul 26 05:08:53 PM PDT 24
Finished Jul 26 05:08:54 PM PDT 24
Peak memory 207204 kb
Host smart-15cd742d-8bc7-484c-8441-54acfd5ee603
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1729129673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.1729129673
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.3926975596
Short name T660
Test name
Test status
Simulation time 185953044 ps
CPU time 0.98 seconds
Started Jul 26 05:08:54 PM PDT 24
Finished Jul 26 05:08:55 PM PDT 24
Peak memory 207032 kb
Host smart-d28aa0a5-4f82-4e40-824d-cd18585d6964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39269
75596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.3926975596
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.2738114980
Short name T1488
Test name
Test status
Simulation time 5570894715 ps
CPU time 47.16 seconds
Started Jul 26 05:08:54 PM PDT 24
Finished Jul 26 05:09:41 PM PDT 24
Peak memory 217096 kb
Host smart-945fccda-ccaa-4bbd-8f00-4473dac1eee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27381
14980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.2738114980
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.2592010773
Short name T2658
Test name
Test status
Simulation time 4667347095 ps
CPU time 50.91 seconds
Started Jul 26 05:08:53 PM PDT 24
Finished Jul 26 05:09:45 PM PDT 24
Peak memory 207408 kb
Host smart-7c07e00a-7755-4240-be69-bc54aa02f32c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2592010773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.2592010773
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.438240370
Short name T1612
Test name
Test status
Simulation time 179071983 ps
CPU time 0.89 seconds
Started Jul 26 05:08:55 PM PDT 24
Finished Jul 26 05:08:56 PM PDT 24
Peak memory 207072 kb
Host smart-1d4c85e6-5fcd-40ff-a1ea-14b376c1097d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=438240370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.438240370
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.1180966898
Short name T1081
Test name
Test status
Simulation time 188735234 ps
CPU time 0.95 seconds
Started Jul 26 05:08:54 PM PDT 24
Finished Jul 26 05:08:55 PM PDT 24
Peak memory 207056 kb
Host smart-b7a4be85-69bd-4013-97be-83d55fa25aab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11809
66898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.1180966898
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.1875073179
Short name T1351
Test name
Test status
Simulation time 183179477 ps
CPU time 0.9 seconds
Started Jul 26 05:08:56 PM PDT 24
Finished Jul 26 05:08:57 PM PDT 24
Peak memory 206988 kb
Host smart-1cbc8e12-568d-40da-96e8-4010861fa550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18750
73179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.1875073179
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.3029048119
Short name T1147
Test name
Test status
Simulation time 168882619 ps
CPU time 0.87 seconds
Started Jul 26 05:08:54 PM PDT 24
Finished Jul 26 05:08:55 PM PDT 24
Peak memory 207136 kb
Host smart-f07e9b3b-98c8-4a94-b7af-de4392b0fd15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30290
48119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.3029048119
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.774361144
Short name T2621
Test name
Test status
Simulation time 225555049 ps
CPU time 1 seconds
Started Jul 26 05:08:52 PM PDT 24
Finished Jul 26 05:08:53 PM PDT 24
Peak memory 207136 kb
Host smart-5923a272-f647-4ff5-8b7d-ba4149155702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77436
1144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.774361144
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.3898576697
Short name T1531
Test name
Test status
Simulation time 161919170 ps
CPU time 0.86 seconds
Started Jul 26 05:08:51 PM PDT 24
Finished Jul 26 05:08:52 PM PDT 24
Peak memory 207092 kb
Host smart-213900db-579f-4812-8551-3fe538578ba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38985
76697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.3898576697
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.2914983135
Short name T1554
Test name
Test status
Simulation time 242638235 ps
CPU time 1.06 seconds
Started Jul 26 05:08:53 PM PDT 24
Finished Jul 26 05:08:54 PM PDT 24
Peak memory 207128 kb
Host smart-1f880844-15d4-46dd-9bc4-f00a24db663d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2914983135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.2914983135
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.1230117061
Short name T2701
Test name
Test status
Simulation time 134906266 ps
CPU time 0.82 seconds
Started Jul 26 05:08:52 PM PDT 24
Finished Jul 26 05:08:53 PM PDT 24
Peak memory 207096 kb
Host smart-62d2f421-f490-4413-aff2-9d246c848f7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12301
17061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.1230117061
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.3780903417
Short name T1724
Test name
Test status
Simulation time 86317739 ps
CPU time 0.77 seconds
Started Jul 26 05:08:53 PM PDT 24
Finished Jul 26 05:08:54 PM PDT 24
Peak memory 207100 kb
Host smart-6371ba9a-49ee-4e31-b32e-670f14964e80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37809
03417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.3780903417
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.4222201014
Short name T2495
Test name
Test status
Simulation time 12133141226 ps
CPU time 29.95 seconds
Started Jul 26 05:08:53 PM PDT 24
Finished Jul 26 05:09:23 PM PDT 24
Peak memory 215628 kb
Host smart-981817ab-4cbd-4e31-8f8f-a088f5ca0497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42222
01014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.4222201014
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.253093423
Short name T1349
Test name
Test status
Simulation time 192615931 ps
CPU time 1.03 seconds
Started Jul 26 05:08:51 PM PDT 24
Finished Jul 26 05:08:52 PM PDT 24
Peak memory 207100 kb
Host smart-3f8165ae-fbd0-4f77-821a-2646f5a721c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25309
3423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.253093423
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.2958425481
Short name T918
Test name
Test status
Simulation time 199789865 ps
CPU time 0.95 seconds
Started Jul 26 05:08:56 PM PDT 24
Finished Jul 26 05:08:58 PM PDT 24
Peak memory 207052 kb
Host smart-f9536ac3-c0bb-4424-9255-f33f11b9ddb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29584
25481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.2958425481
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.200719630
Short name T32
Test name
Test status
Simulation time 195058759 ps
CPU time 0.94 seconds
Started Jul 26 05:08:53 PM PDT 24
Finished Jul 26 05:08:54 PM PDT 24
Peak memory 207072 kb
Host smart-10cb9af2-1391-4df0-9f58-d134b4e13183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20071
9630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.200719630
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.3274853601
Short name T2327
Test name
Test status
Simulation time 177704520 ps
CPU time 0.92 seconds
Started Jul 26 05:08:56 PM PDT 24
Finished Jul 26 05:08:57 PM PDT 24
Peak memory 206992 kb
Host smart-1efc8ee0-18dd-4093-91ad-b64449253512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32748
53601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.3274853601
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.2162300163
Short name T1493
Test name
Test status
Simulation time 143827702 ps
CPU time 0.87 seconds
Started Jul 26 05:08:53 PM PDT 24
Finished Jul 26 05:08:54 PM PDT 24
Peak memory 207084 kb
Host smart-67838dc6-8090-43be-b4d0-32251c94a602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21623
00163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.2162300163
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.1851051138
Short name T843
Test name
Test status
Simulation time 154758692 ps
CPU time 0.84 seconds
Started Jul 26 05:08:55 PM PDT 24
Finished Jul 26 05:08:55 PM PDT 24
Peak memory 207100 kb
Host smart-b7deadf6-0c74-4ed2-ba05-675ed4389e8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18510
51138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.1851051138
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.3338508414
Short name T204
Test name
Test status
Simulation time 151427813 ps
CPU time 0.88 seconds
Started Jul 26 05:08:52 PM PDT 24
Finished Jul 26 05:08:54 PM PDT 24
Peak memory 207044 kb
Host smart-b20d38e9-363b-45ad-94ea-563fef658835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33385
08414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.3338508414
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.3588911922
Short name T621
Test name
Test status
Simulation time 247457276 ps
CPU time 1.05 seconds
Started Jul 26 05:08:54 PM PDT 24
Finished Jul 26 05:08:55 PM PDT 24
Peak memory 207120 kb
Host smart-e0a2892f-129d-41f8-95ab-fbfefdb626f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35889
11922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.3588911922
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.425054139
Short name T1011
Test name
Test status
Simulation time 6224919813 ps
CPU time 187.69 seconds
Started Jul 26 05:08:54 PM PDT 24
Finished Jul 26 05:12:02 PM PDT 24
Peak memory 215596 kb
Host smart-d2ae4c7e-4e42-4047-9e3e-cbde43277dc9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=425054139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.425054139
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.888480088
Short name T2749
Test name
Test status
Simulation time 231128013 ps
CPU time 1.01 seconds
Started Jul 26 05:08:52 PM PDT 24
Finished Jul 26 05:08:54 PM PDT 24
Peak memory 207120 kb
Host smart-821d6d4a-a408-4497-8b65-a9f4aaba5905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88848
0088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.888480088
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.2377436457
Short name T2500
Test name
Test status
Simulation time 193335979 ps
CPU time 1 seconds
Started Jul 26 05:08:56 PM PDT 24
Finished Jul 26 05:08:57 PM PDT 24
Peak memory 207096 kb
Host smart-f2a5ea97-9b2b-4755-89f4-301aad953f9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23774
36457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.2377436457
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.122934421
Short name T313
Test name
Test status
Simulation time 1335676291 ps
CPU time 3.18 seconds
Started Jul 26 05:08:52 PM PDT 24
Finished Jul 26 05:08:55 PM PDT 24
Peak memory 207280 kb
Host smart-839c2d63-d74d-40cf-aef5-c70c616b20ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12293
4421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.122934421
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.4218071885
Short name T1466
Test name
Test status
Simulation time 4401598888 ps
CPU time 33.72 seconds
Started Jul 26 05:08:53 PM PDT 24
Finished Jul 26 05:09:27 PM PDT 24
Peak memory 216920 kb
Host smart-ceda8f3c-e387-43e8-8da8-9a09ac8e44f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42180
71885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.4218071885
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_timeout_missing_host_handshake.2573367657
Short name T2817
Test name
Test status
Simulation time 1347588540 ps
CPU time 33.94 seconds
Started Jul 26 05:08:38 PM PDT 24
Finished Jul 26 05:09:12 PM PDT 24
Peak memory 207236 kb
Host smart-e903b2b1-af47-43fd-beee-88f94d677bec
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573367657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_timeout_missing_hos
t_handshake.2573367657
Directory /workspace/10.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.983256194
Short name T1588
Test name
Test status
Simulation time 65539837 ps
CPU time 0.7 seconds
Started Jul 26 05:09:12 PM PDT 24
Finished Jul 26 05:09:13 PM PDT 24
Peak memory 207064 kb
Host smart-2c03eccc-7053-4b59-904c-a915c3c0607e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=983256194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.983256194
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.1845694976
Short name T2018
Test name
Test status
Simulation time 4005647192 ps
CPU time 6.39 seconds
Started Jul 26 05:08:53 PM PDT 24
Finished Jul 26 05:08:59 PM PDT 24
Peak memory 207376 kb
Host smart-8fd66274-9a9b-4d57-8d8f-f9340c0464bb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845694976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_a
on_wake_disconnect.1845694976
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.3594116691
Short name T1534
Test name
Test status
Simulation time 13379934165 ps
CPU time 16.33 seconds
Started Jul 26 05:08:55 PM PDT 24
Finished Jul 26 05:09:12 PM PDT 24
Peak memory 207356 kb
Host smart-30f1bae4-8acc-4325-b17a-1950a75f57eb
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594116691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.3594116691
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.945238098
Short name T2793
Test name
Test status
Simulation time 193689434 ps
CPU time 0.97 seconds
Started Jul 26 05:08:52 PM PDT 24
Finished Jul 26 05:08:53 PM PDT 24
Peak memory 207104 kb
Host smart-ed698a23-5246-4285-bc8d-4b93b557e0bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94523
8098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.945238098
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.2963447918
Short name T909
Test name
Test status
Simulation time 140202490 ps
CPU time 0.8 seconds
Started Jul 26 05:08:50 PM PDT 24
Finished Jul 26 05:08:51 PM PDT 24
Peak memory 206956 kb
Host smart-02f55b39-d5a9-4a9f-9258-7d864c2930e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29634
47918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.2963447918
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.1007620137
Short name T1015
Test name
Test status
Simulation time 359157564 ps
CPU time 1.33 seconds
Started Jul 26 05:08:54 PM PDT 24
Finished Jul 26 05:08:56 PM PDT 24
Peak memory 207092 kb
Host smart-1076adcc-2eb8-4d30-a950-a3ff910acbf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10076
20137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.1007620137
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.3726261209
Short name T2255
Test name
Test status
Simulation time 1663642669 ps
CPU time 3.81 seconds
Started Jul 26 05:08:52 PM PDT 24
Finished Jul 26 05:08:56 PM PDT 24
Peak memory 207212 kb
Host smart-f018c80d-df19-42d6-9bbc-0c5b172d631b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3726261209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.3726261209
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.4260766434
Short name T1287
Test name
Test status
Simulation time 18197413888 ps
CPU time 38.79 seconds
Started Jul 26 05:08:53 PM PDT 24
Finished Jul 26 05:09:32 PM PDT 24
Peak memory 207300 kb
Host smart-e4e49175-5ec4-4915-a8aa-35b25863c533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42607
66434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.4260766434
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_device_timeout.963846168
Short name T1631
Test name
Test status
Simulation time 3823867483 ps
CPU time 36.33 seconds
Started Jul 26 05:08:49 PM PDT 24
Finished Jul 26 05:09:25 PM PDT 24
Peak memory 207232 kb
Host smart-298c10fd-70d8-4940-8199-ce310d7f94b6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963846168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_timeout.963846168
Directory /workspace/11.usbdev_device_timeout/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.3101722114
Short name T270
Test name
Test status
Simulation time 357632161 ps
CPU time 1.3 seconds
Started Jul 26 05:08:51 PM PDT 24
Finished Jul 26 05:08:53 PM PDT 24
Peak memory 207012 kb
Host smart-144ebc8b-fa7a-4e6d-86e2-c5f8bdfcaa80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31017
22114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.3101722114
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.510858897
Short name T2124
Test name
Test status
Simulation time 195341965 ps
CPU time 0.93 seconds
Started Jul 26 05:09:02 PM PDT 24
Finished Jul 26 05:09:03 PM PDT 24
Peak memory 206988 kb
Host smart-c5aa2966-8b69-40b0-a9bf-b688fc1a0f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51085
8897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.510858897
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.3080094086
Short name T623
Test name
Test status
Simulation time 71845709 ps
CPU time 0.75 seconds
Started Jul 26 05:09:03 PM PDT 24
Finished Jul 26 05:09:04 PM PDT 24
Peak memory 207064 kb
Host smart-f04b4b91-7469-4daa-8b0d-cc03a4beaec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30800
94086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.3080094086
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.3681671264
Short name T1573
Test name
Test status
Simulation time 833394800 ps
CPU time 2.32 seconds
Started Jul 26 05:09:03 PM PDT 24
Finished Jul 26 05:09:05 PM PDT 24
Peak memory 207480 kb
Host smart-fc37e032-3fb3-443d-9570-015a007aad93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36816
71264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.3681671264
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.3593620513
Short name T1019
Test name
Test status
Simulation time 217719246 ps
CPU time 2.04 seconds
Started Jul 26 05:09:04 PM PDT 24
Finished Jul 26 05:09:06 PM PDT 24
Peak memory 207176 kb
Host smart-6f930a04-e9c5-45eb-bd9e-23a70e395fe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35936
20513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.3593620513
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.242687476
Short name T1067
Test name
Test status
Simulation time 275996823 ps
CPU time 1.25 seconds
Started Jul 26 05:09:03 PM PDT 24
Finished Jul 26 05:09:04 PM PDT 24
Peak memory 207340 kb
Host smart-cf20891c-275e-4168-b897-5c2cfd0565be
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=242687476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.242687476
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.269826554
Short name T2159
Test name
Test status
Simulation time 146201390 ps
CPU time 0.81 seconds
Started Jul 26 05:09:04 PM PDT 24
Finished Jul 26 05:09:05 PM PDT 24
Peak memory 207024 kb
Host smart-7b182110-8fcb-4f94-8ab6-f7e17199ca4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26982
6554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.269826554
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.374216754
Short name T2266
Test name
Test status
Simulation time 182103471 ps
CPU time 0.89 seconds
Started Jul 26 05:09:01 PM PDT 24
Finished Jul 26 05:09:01 PM PDT 24
Peak memory 207020 kb
Host smart-38dc760c-64e6-43f4-9777-02f54522e1d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37421
6754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.374216754
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_invalid_sync.2524487542
Short name T1625
Test name
Test status
Simulation time 6063650909 ps
CPU time 63.4 seconds
Started Jul 26 05:09:05 PM PDT 24
Finished Jul 26 05:10:08 PM PDT 24
Peak memory 215596 kb
Host smart-45d51d73-9432-4383-8013-efd107f025fe
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2524487542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.2524487542
Directory /workspace/11.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/11.usbdev_iso_retraction.2950705250
Short name T2188
Test name
Test status
Simulation time 4636733212 ps
CPU time 55.67 seconds
Started Jul 26 05:09:03 PM PDT 24
Finished Jul 26 05:09:59 PM PDT 24
Peak memory 207300 kb
Host smart-bf36d76f-3a28-45de-9268-6b477d22e425
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2950705250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.2950705250
Directory /workspace/11.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.3698843014
Short name T2332
Test name
Test status
Simulation time 149193654 ps
CPU time 0.85 seconds
Started Jul 26 05:09:07 PM PDT 24
Finished Jul 26 05:09:08 PM PDT 24
Peak memory 206992 kb
Host smart-9f4d45d4-3fff-4524-b49a-97a1b5d0701d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36988
43014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.3698843014
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.1785793409
Short name T1807
Test name
Test status
Simulation time 23297241827 ps
CPU time 30.7 seconds
Started Jul 26 05:09:03 PM PDT 24
Finished Jul 26 05:09:34 PM PDT 24
Peak memory 207372 kb
Host smart-541f9a4b-ae59-4ffa-b53b-8d6467048174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17857
93409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.1785793409
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.2567152943
Short name T1741
Test name
Test status
Simulation time 3331418526 ps
CPU time 5.1 seconds
Started Jul 26 05:09:07 PM PDT 24
Finished Jul 26 05:09:13 PM PDT 24
Peak memory 207240 kb
Host smart-95fb21b2-3ff2-4445-9b47-430135656fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25671
52943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.2567152943
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.2026663080
Short name T1402
Test name
Test status
Simulation time 7237928983 ps
CPU time 55.17 seconds
Started Jul 26 05:09:08 PM PDT 24
Finished Jul 26 05:10:03 PM PDT 24
Peak memory 217208 kb
Host smart-56eae9e8-9711-4e02-a803-07a34ce2b8c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20266
63080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.2026663080
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.481367859
Short name T2605
Test name
Test status
Simulation time 4262297829 ps
CPU time 126.37 seconds
Started Jul 26 05:09:03 PM PDT 24
Finished Jul 26 05:11:09 PM PDT 24
Peak memory 215508 kb
Host smart-78011434-1834-403f-866d-b0c4b84e7874
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=481367859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.481367859
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.2357098962
Short name T27
Test name
Test status
Simulation time 239865180 ps
CPU time 1.01 seconds
Started Jul 26 05:09:08 PM PDT 24
Finished Jul 26 05:09:09 PM PDT 24
Peak memory 207088 kb
Host smart-7df2d34d-49b2-46a4-9d7b-60ccb8c42036
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2357098962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.2357098962
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.2710942266
Short name T407
Test name
Test status
Simulation time 190667352 ps
CPU time 0.96 seconds
Started Jul 26 05:09:04 PM PDT 24
Finished Jul 26 05:09:05 PM PDT 24
Peak memory 207148 kb
Host smart-14742db0-4d58-43a2-a5cb-1316abdb952b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27109
42266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.2710942266
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.4232167275
Short name T1673
Test name
Test status
Simulation time 3510695735 ps
CPU time 34.64 seconds
Started Jul 26 05:09:03 PM PDT 24
Finished Jul 26 05:09:37 PM PDT 24
Peak memory 215540 kb
Host smart-d0e95c05-540c-4355-b9bd-2710141a589f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42321
67275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.4232167275
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.849018349
Short name T2346
Test name
Test status
Simulation time 7333607053 ps
CPU time 76.78 seconds
Started Jul 26 05:09:07 PM PDT 24
Finished Jul 26 05:10:24 PM PDT 24
Peak memory 207372 kb
Host smart-a8df23b9-44da-4b2b-846d-bdc16fd58d5f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=849018349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.849018349
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.83874707
Short name T392
Test name
Test status
Simulation time 153939557 ps
CPU time 0.86 seconds
Started Jul 26 05:09:07 PM PDT 24
Finished Jul 26 05:09:09 PM PDT 24
Peak memory 207108 kb
Host smart-5211d13d-89ca-46bb-a3f0-b1bf04e0d87c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=83874707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.83874707
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.3243959377
Short name T999
Test name
Test status
Simulation time 140986638 ps
CPU time 0.85 seconds
Started Jul 26 05:09:05 PM PDT 24
Finished Jul 26 05:09:06 PM PDT 24
Peak memory 207116 kb
Host smart-a041ac30-0acf-419f-8fa8-d60f6ba49cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32439
59377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.3243959377
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.381351476
Short name T1246
Test name
Test status
Simulation time 186114278 ps
CPU time 0.92 seconds
Started Jul 26 05:09:03 PM PDT 24
Finished Jul 26 05:09:04 PM PDT 24
Peak memory 207132 kb
Host smart-6db86eb2-f404-4b0d-b0ee-8a1eb1945904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38135
1476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.381351476
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.2087999302
Short name T2616
Test name
Test status
Simulation time 205100595 ps
CPU time 0.97 seconds
Started Jul 26 05:09:02 PM PDT 24
Finished Jul 26 05:09:03 PM PDT 24
Peak memory 207016 kb
Host smart-bf5ff383-8f3c-475f-a26a-85b0c96c02c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20879
99302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.2087999302
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.2032173742
Short name T2654
Test name
Test status
Simulation time 148252676 ps
CPU time 0.83 seconds
Started Jul 26 05:09:07 PM PDT 24
Finished Jul 26 05:09:08 PM PDT 24
Peak memory 206988 kb
Host smart-6d990d79-86d2-4f9d-ae61-5f4356aee146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20321
73742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.2032173742
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.554417568
Short name T952
Test name
Test status
Simulation time 204166336 ps
CPU time 1.01 seconds
Started Jul 26 05:09:10 PM PDT 24
Finished Jul 26 05:09:11 PM PDT 24
Peak memory 206976 kb
Host smart-4ec7ca8a-c3d0-4cfd-b03f-d2c5ea9fcc8a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=554417568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.554417568
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.2660034497
Short name T1400
Test name
Test status
Simulation time 145872599 ps
CPU time 0.82 seconds
Started Jul 26 05:09:08 PM PDT 24
Finished Jul 26 05:09:10 PM PDT 24
Peak memory 207044 kb
Host smart-515519ab-b4cd-4895-a1ee-bb216ca67196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26600
34497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.2660034497
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.3710733760
Short name T513
Test name
Test status
Simulation time 34468988 ps
CPU time 0.68 seconds
Started Jul 26 05:09:10 PM PDT 24
Finished Jul 26 05:09:11 PM PDT 24
Peak memory 206932 kb
Host smart-a4330519-cf19-447b-aee3-638a8a60f515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37107
33760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.3710733760
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.1430078440
Short name T1855
Test name
Test status
Simulation time 15829746010 ps
CPU time 40.01 seconds
Started Jul 26 05:09:02 PM PDT 24
Finished Jul 26 05:09:42 PM PDT 24
Peak memory 215532 kb
Host smart-cd523e67-9d3b-43be-9d04-4ef251ec68db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14300
78440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.1430078440
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.1028900366
Short name T856
Test name
Test status
Simulation time 206788069 ps
CPU time 0.94 seconds
Started Jul 26 05:09:05 PM PDT 24
Finished Jul 26 05:09:06 PM PDT 24
Peak memory 207084 kb
Host smart-6e476b0c-e736-433c-a4e4-8172b3bf359f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10289
00366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.1028900366
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.2898333807
Short name T1122
Test name
Test status
Simulation time 215162424 ps
CPU time 0.97 seconds
Started Jul 26 05:09:04 PM PDT 24
Finished Jul 26 05:09:05 PM PDT 24
Peak memory 207048 kb
Host smart-48738a39-2b46-43cb-8008-3644a6529925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28983
33807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.2898333807
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.1753686359
Short name T2862
Test name
Test status
Simulation time 271386160 ps
CPU time 1.06 seconds
Started Jul 26 05:09:07 PM PDT 24
Finished Jul 26 05:09:09 PM PDT 24
Peak memory 207132 kb
Host smart-7c2239aa-043b-4653-921a-b1a6d65432ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17536
86359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.1753686359
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.3918807362
Short name T541
Test name
Test status
Simulation time 174361925 ps
CPU time 0.88 seconds
Started Jul 26 05:09:04 PM PDT 24
Finished Jul 26 05:09:05 PM PDT 24
Peak memory 207128 kb
Host smart-dc650075-e289-44f4-9c24-81e049f01576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39188
07362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.3918807362
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.1234601453
Short name T75
Test name
Test status
Simulation time 163846911 ps
CPU time 0.85 seconds
Started Jul 26 05:09:05 PM PDT 24
Finished Jul 26 05:09:06 PM PDT 24
Peak memory 207108 kb
Host smart-1d810824-9119-4d6e-b298-ad911114dc0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12346
01453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.1234601453
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.967278554
Short name T1258
Test name
Test status
Simulation time 149204303 ps
CPU time 0.87 seconds
Started Jul 26 05:09:07 PM PDT 24
Finished Jul 26 05:09:08 PM PDT 24
Peak memory 207100 kb
Host smart-4def25cd-8ca9-4d97-92a8-e7ce1c87e923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96727
8554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.967278554
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.3087600771
Short name T1792
Test name
Test status
Simulation time 149441159 ps
CPU time 0.82 seconds
Started Jul 26 05:09:04 PM PDT 24
Finished Jul 26 05:09:05 PM PDT 24
Peak memory 206984 kb
Host smart-3597b5ea-b318-473a-aee2-47bc5e4273b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30876
00771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.3087600771
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.3562835177
Short name T2479
Test name
Test status
Simulation time 216585488 ps
CPU time 1.07 seconds
Started Jul 26 05:09:08 PM PDT 24
Finished Jul 26 05:09:09 PM PDT 24
Peak memory 207048 kb
Host smart-8caefb92-bc03-4185-be71-deb1ea9ee329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35628
35177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.3562835177
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.534415361
Short name T1826
Test name
Test status
Simulation time 4644271497 ps
CPU time 47.45 seconds
Started Jul 26 05:09:06 PM PDT 24
Finished Jul 26 05:09:54 PM PDT 24
Peak memory 217048 kb
Host smart-de49d6b0-6d68-401c-957d-a28b8e87b3e3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=534415361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.534415361
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.3113898268
Short name T1668
Test name
Test status
Simulation time 218707034 ps
CPU time 0.97 seconds
Started Jul 26 05:09:04 PM PDT 24
Finished Jul 26 05:09:05 PM PDT 24
Peak memory 206984 kb
Host smart-cf0b137b-0925-459f-9c62-4b469a4b95e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31138
98268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.3113898268
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.4165496892
Short name T302
Test name
Test status
Simulation time 182518390 ps
CPU time 0.94 seconds
Started Jul 26 05:09:07 PM PDT 24
Finished Jul 26 05:09:08 PM PDT 24
Peak memory 207084 kb
Host smart-bbbdc04e-379e-429b-a4ed-5897dbd9d51f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41654
96892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.4165496892
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.2915495089
Short name T509
Test name
Test status
Simulation time 802122909 ps
CPU time 1.93 seconds
Started Jul 26 05:09:10 PM PDT 24
Finished Jul 26 05:09:13 PM PDT 24
Peak memory 207024 kb
Host smart-a4f29af0-d68f-47c5-9f8d-48d3062a152e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29154
95089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.2915495089
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.2268731070
Short name T669
Test name
Test status
Simulation time 4649561902 ps
CPU time 48.81 seconds
Started Jul 26 05:09:07 PM PDT 24
Finished Jul 26 05:09:56 PM PDT 24
Peak memory 207348 kb
Host smart-96fa6b11-3ada-4bc4-b150-c717e390d569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22687
31070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.2268731070
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_timeout_missing_host_handshake.72621900
Short name T63
Test name
Test status
Simulation time 4392880586 ps
CPU time 30.29 seconds
Started Jul 26 05:08:50 PM PDT 24
Finished Jul 26 05:09:21 PM PDT 24
Peak memory 207388 kb
Host smart-dc51f6e0-4a56-4804-a829-38ac4f666272
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72621900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_timeout_missing_host_
handshake.72621900
Directory /workspace/11.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.506156935
Short name T179
Test name
Test status
Simulation time 59016248 ps
CPU time 0.67 seconds
Started Jul 26 05:09:24 PM PDT 24
Finished Jul 26 05:09:25 PM PDT 24
Peak memory 207024 kb
Host smart-0cfdaaed-8090-4b80-8ad5-d7435d6cc4bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=506156935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.506156935
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.306982752
Short name T692
Test name
Test status
Simulation time 4237355971 ps
CPU time 5.93 seconds
Started Jul 26 05:09:14 PM PDT 24
Finished Jul 26 05:09:20 PM PDT 24
Peak memory 207220 kb
Host smart-a360acd6-c1a7-42d6-9967-3032d664f5a4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306982752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_ao
n_wake_disconnect.306982752
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.3917664967
Short name T849
Test name
Test status
Simulation time 13435061535 ps
CPU time 17.28 seconds
Started Jul 26 05:09:12 PM PDT 24
Finished Jul 26 05:09:30 PM PDT 24
Peak memory 207356 kb
Host smart-9f082bb4-97bb-4716-ab4c-41ba0854bfb8
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917664967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.3917664967
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.1555821735
Short name T681
Test name
Test status
Simulation time 23376113853 ps
CPU time 29.99 seconds
Started Jul 26 05:09:12 PM PDT 24
Finished Jul 26 05:09:43 PM PDT 24
Peak memory 207360 kb
Host smart-b1306068-05cb-4378-89af-b34f427c53ac
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555821735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_a
on_wake_resume.1555821735
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.1568800008
Short name T2735
Test name
Test status
Simulation time 202153366 ps
CPU time 0.94 seconds
Started Jul 26 05:09:22 PM PDT 24
Finished Jul 26 05:09:23 PM PDT 24
Peak memory 207008 kb
Host smart-0a5fdf8d-e78b-4cea-80e1-f89b0b958aee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15688
00008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.1568800008
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.4263128730
Short name T2628
Test name
Test status
Simulation time 149321291 ps
CPU time 0.86 seconds
Started Jul 26 05:09:14 PM PDT 24
Finished Jul 26 05:09:15 PM PDT 24
Peak memory 207012 kb
Host smart-7d1a1ff3-6ac6-4957-80ec-3da6d6c058cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42631
28730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.4263128730
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.3793044347
Short name T1300
Test name
Test status
Simulation time 491821961 ps
CPU time 1.62 seconds
Started Jul 26 05:09:13 PM PDT 24
Finished Jul 26 05:09:15 PM PDT 24
Peak memory 207084 kb
Host smart-a29f9d73-99d4-44e5-8b1c-9e06b068c449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37930
44347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.3793044347
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.2505442422
Short name T1384
Test name
Test status
Simulation time 945936294 ps
CPU time 2.36 seconds
Started Jul 26 05:09:12 PM PDT 24
Finished Jul 26 05:09:15 PM PDT 24
Peak memory 207240 kb
Host smart-078be661-b501-43cb-befd-ace23c8c13f5
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2505442422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.2505442422
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.3989886371
Short name T1563
Test name
Test status
Simulation time 7810333780 ps
CPU time 17.89 seconds
Started Jul 26 05:09:21 PM PDT 24
Finished Jul 26 05:09:40 PM PDT 24
Peak memory 207248 kb
Host smart-3619df34-f36b-401b-bda4-dc5ec2612396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39898
86371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.3989886371
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_device_timeout.3367462992
Short name T1007
Test name
Test status
Simulation time 3124292592 ps
CPU time 22.63 seconds
Started Jul 26 05:09:13 PM PDT 24
Finished Jul 26 05:09:36 PM PDT 24
Peak memory 207264 kb
Host smart-6d45272c-e082-4400-8e52-244af89eea13
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367462992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_timeout.3367462992
Directory /workspace/12.usbdev_device_timeout/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.775078861
Short name T1765
Test name
Test status
Simulation time 501167133 ps
CPU time 1.7 seconds
Started Jul 26 05:09:14 PM PDT 24
Finished Jul 26 05:09:16 PM PDT 24
Peak memory 207088 kb
Host smart-5d8912a6-a1f1-475a-a68f-990a8822a12b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77507
8861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.775078861
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.2221776436
Short name T1819
Test name
Test status
Simulation time 173850520 ps
CPU time 0.91 seconds
Started Jul 26 05:09:13 PM PDT 24
Finished Jul 26 05:09:14 PM PDT 24
Peak memory 207068 kb
Host smart-e227352b-7b9a-4b99-81cc-d4a0b9b18ed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22217
76436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.2221776436
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.4227694669
Short name T1334
Test name
Test status
Simulation time 56342327 ps
CPU time 0.73 seconds
Started Jul 26 05:09:16 PM PDT 24
Finished Jul 26 05:09:17 PM PDT 24
Peak memory 207016 kb
Host smart-fe6faa99-581d-407e-8c07-472f67a5e2eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42276
94669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.4227694669
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.98961897
Short name T1803
Test name
Test status
Simulation time 763216942 ps
CPU time 2.24 seconds
Started Jul 26 05:09:16 PM PDT 24
Finished Jul 26 05:09:19 PM PDT 24
Peak memory 207292 kb
Host smart-b4573985-0664-46d6-ba5a-07cd2b0ca58e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98961
897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.98961897
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.1506504749
Short name T2276
Test name
Test status
Simulation time 229393260 ps
CPU time 1.22 seconds
Started Jul 26 05:09:13 PM PDT 24
Finished Jul 26 05:09:15 PM PDT 24
Peak memory 215588 kb
Host smart-b68406bf-8939-49e3-8d57-02e4b701ba5d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1506504749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.1506504749
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.2871897997
Short name T331
Test name
Test status
Simulation time 201633940 ps
CPU time 0.91 seconds
Started Jul 26 05:09:13 PM PDT 24
Finished Jul 26 05:09:14 PM PDT 24
Peak memory 207000 kb
Host smart-13c55698-495a-46dd-a761-a2ad78a4569c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28718
97997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.2871897997
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.2974224875
Short name T1785
Test name
Test status
Simulation time 188456622 ps
CPU time 0.93 seconds
Started Jul 26 05:09:16 PM PDT 24
Finished Jul 26 05:09:17 PM PDT 24
Peak memory 207044 kb
Host smart-b8797be9-ed13-4c01-9d9d-93dbcbcee883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29742
24875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.2974224875
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.3170366767
Short name T389
Test name
Test status
Simulation time 7899035439 ps
CPU time 67.27 seconds
Started Jul 26 05:09:17 PM PDT 24
Finished Jul 26 05:10:24 PM PDT 24
Peak memory 215536 kb
Host smart-dfe10e61-44fd-48b6-967f-ec8dd26e7f57
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3170366767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.3170366767
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/12.usbdev_iso_retraction.2324556939
Short name T1666
Test name
Test status
Simulation time 11181186303 ps
CPU time 78.72 seconds
Started Jul 26 05:09:17 PM PDT 24
Finished Jul 26 05:10:36 PM PDT 24
Peak memory 207344 kb
Host smart-a4f25091-6866-4e88-a428-c0caef52ad55
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2324556939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.2324556939
Directory /workspace/12.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.1817678472
Short name T2251
Test name
Test status
Simulation time 227302835 ps
CPU time 0.97 seconds
Started Jul 26 05:09:13 PM PDT 24
Finished Jul 26 05:09:14 PM PDT 24
Peak memory 207128 kb
Host smart-81965ddb-72ca-44b5-a04e-b683609e8606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18176
78472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.1817678472
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.3094649504
Short name T848
Test name
Test status
Simulation time 23354601740 ps
CPU time 30.16 seconds
Started Jul 26 05:09:12 PM PDT 24
Finished Jul 26 05:09:42 PM PDT 24
Peak memory 207344 kb
Host smart-f4a4dfb6-c81f-4bfb-85a8-1ace297de8de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30946
49504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.3094649504
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.1667904600
Short name T2698
Test name
Test status
Simulation time 3328285298 ps
CPU time 5.23 seconds
Started Jul 26 05:09:12 PM PDT 24
Finished Jul 26 05:09:18 PM PDT 24
Peak memory 207332 kb
Host smart-44b6730a-c2af-4c04-92f1-37e73d67d609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16679
04600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.1667904600
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.3432581065
Short name T975
Test name
Test status
Simulation time 7399520705 ps
CPU time 57.69 seconds
Started Jul 26 05:09:21 PM PDT 24
Finished Jul 26 05:10:19 PM PDT 24
Peak memory 223576 kb
Host smart-0660c9df-1c84-411b-a4b6-e314cfea92ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34325
81065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.3432581065
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.260332869
Short name T1971
Test name
Test status
Simulation time 7043063012 ps
CPU time 76.26 seconds
Started Jul 26 05:09:14 PM PDT 24
Finished Jul 26 05:10:30 PM PDT 24
Peak memory 207256 kb
Host smart-63a7240d-d3d4-4022-ad64-2d63bc86be3e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=260332869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.260332869
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.2001689176
Short name T1304
Test name
Test status
Simulation time 242650347 ps
CPU time 1.01 seconds
Started Jul 26 05:09:16 PM PDT 24
Finished Jul 26 05:09:17 PM PDT 24
Peak memory 207096 kb
Host smart-92affcc4-b8a3-4501-a417-dc3646151cb6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2001689176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.2001689176
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.2560465455
Short name T2525
Test name
Test status
Simulation time 228158219 ps
CPU time 1 seconds
Started Jul 26 05:09:17 PM PDT 24
Finished Jul 26 05:09:18 PM PDT 24
Peak memory 207092 kb
Host smart-f6a97cba-403d-4426-828e-5ad7a08144ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25604
65455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.2560465455
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.2408299990
Short name T1282
Test name
Test status
Simulation time 6149203718 ps
CPU time 53.79 seconds
Started Jul 26 05:09:12 PM PDT 24
Finished Jul 26 05:10:05 PM PDT 24
Peak memory 217132 kb
Host smart-c20d8478-1dc2-4651-991a-ece3acba9a6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24082
99990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.2408299990
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.783105347
Short name T768
Test name
Test status
Simulation time 6825565226 ps
CPU time 68.73 seconds
Started Jul 26 05:09:21 PM PDT 24
Finished Jul 26 05:10:31 PM PDT 24
Peak memory 207176 kb
Host smart-f73b7126-9516-4aa9-87d2-e423c8f7f542
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=783105347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.783105347
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.29255949
Short name T372
Test name
Test status
Simulation time 177686633 ps
CPU time 0.87 seconds
Started Jul 26 05:09:15 PM PDT 24
Finished Jul 26 05:09:17 PM PDT 24
Peak memory 207136 kb
Host smart-a6651d65-6363-47a4-b1e3-247ea94e6084
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=29255949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.29255949
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.1595321015
Short name T2805
Test name
Test status
Simulation time 168807719 ps
CPU time 0.87 seconds
Started Jul 26 05:09:14 PM PDT 24
Finished Jul 26 05:09:16 PM PDT 24
Peak memory 207040 kb
Host smart-3061a5e4-9722-49cc-9c7f-8e7cea19ec8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15953
21015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.1595321015
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.3199461128
Short name T2518
Test name
Test status
Simulation time 213462961 ps
CPU time 1.02 seconds
Started Jul 26 05:09:15 PM PDT 24
Finished Jul 26 05:09:16 PM PDT 24
Peak memory 207080 kb
Host smart-f752cc46-9fba-40e6-8ef0-ff037da9cf20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31994
61128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.3199461128
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.3177459
Short name T1427
Test name
Test status
Simulation time 162760076 ps
CPU time 0.91 seconds
Started Jul 26 05:09:12 PM PDT 24
Finished Jul 26 05:09:14 PM PDT 24
Peak memory 207052 kb
Host smart-ec959b58-9aab-4c0e-99d2-ae3340c52197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31774
59 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.3177459
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.1190569311
Short name T795
Test name
Test status
Simulation time 144929890 ps
CPU time 0.83 seconds
Started Jul 26 05:09:14 PM PDT 24
Finished Jul 26 05:09:15 PM PDT 24
Peak memory 207040 kb
Host smart-c8f9cd6d-a90d-4da3-aa11-391285773804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11905
69311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.1190569311
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.426791434
Short name T2282
Test name
Test status
Simulation time 163930777 ps
CPU time 0.87 seconds
Started Jul 26 05:09:13 PM PDT 24
Finished Jul 26 05:09:14 PM PDT 24
Peak memory 207096 kb
Host smart-21b22e32-60f8-4f00-927e-8a5b4cc8ce2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42679
1434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.426791434
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.2467934071
Short name T52
Test name
Test status
Simulation time 252369705 ps
CPU time 1.04 seconds
Started Jul 26 05:09:13 PM PDT 24
Finished Jul 26 05:09:15 PM PDT 24
Peak memory 207120 kb
Host smart-b163cbfd-969f-40da-b1a8-73639a14b64a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2467934071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.2467934071
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.2201120829
Short name T593
Test name
Test status
Simulation time 150284090 ps
CPU time 0.87 seconds
Started Jul 26 05:09:12 PM PDT 24
Finished Jul 26 05:09:13 PM PDT 24
Peak memory 207092 kb
Host smart-aeaee1d6-61d6-4029-9527-70bade28be06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22011
20829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.2201120829
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.3927666986
Short name T37
Test name
Test status
Simulation time 36510586 ps
CPU time 0.72 seconds
Started Jul 26 05:09:16 PM PDT 24
Finished Jul 26 05:09:17 PM PDT 24
Peak memory 207052 kb
Host smart-2543602f-c859-4a4e-b4d4-c46bc4ef7c26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39276
66986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.3927666986
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.1151419181
Short name T2214
Test name
Test status
Simulation time 12564377155 ps
CPU time 30.01 seconds
Started Jul 26 05:09:17 PM PDT 24
Finished Jul 26 05:09:47 PM PDT 24
Peak memory 215604 kb
Host smart-19fb7b60-92c3-4dfd-b2f1-9236e4daa9c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11514
19181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.1151419181
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.2095757707
Short name T1270
Test name
Test status
Simulation time 169208057 ps
CPU time 0.91 seconds
Started Jul 26 05:09:14 PM PDT 24
Finished Jul 26 05:09:15 PM PDT 24
Peak memory 207080 kb
Host smart-63c5fcd5-616c-4b92-8ae7-157106cbfaba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20957
57707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.2095757707
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.740980403
Short name T945
Test name
Test status
Simulation time 203468846 ps
CPU time 0.97 seconds
Started Jul 26 05:09:16 PM PDT 24
Finished Jul 26 05:09:17 PM PDT 24
Peak memory 207064 kb
Host smart-0ada5970-3cb1-439a-9f54-3de581f4d0cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74098
0403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.740980403
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.4209825152
Short name T1267
Test name
Test status
Simulation time 181891428 ps
CPU time 0.93 seconds
Started Jul 26 05:09:15 PM PDT 24
Finished Jul 26 05:09:16 PM PDT 24
Peak memory 207080 kb
Host smart-3e9aacd0-d420-4b84-8dc3-a73ea24df6f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42098
25152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.4209825152
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.4194948233
Short name T906
Test name
Test status
Simulation time 169651418 ps
CPU time 0.9 seconds
Started Jul 26 05:09:14 PM PDT 24
Finished Jul 26 05:09:15 PM PDT 24
Peak memory 207020 kb
Host smart-e6850b7e-b2b3-4c11-9130-a03f7507b4fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41949
48233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.4194948233
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.3164637151
Short name T827
Test name
Test status
Simulation time 188699143 ps
CPU time 0.89 seconds
Started Jul 26 05:09:14 PM PDT 24
Finished Jul 26 05:09:15 PM PDT 24
Peak memory 207088 kb
Host smart-c9e5d873-e235-4458-b2fc-073ba2f43dd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31646
37151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.3164637151
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.2390475454
Short name T2357
Test name
Test status
Simulation time 164633734 ps
CPU time 0.85 seconds
Started Jul 26 05:09:14 PM PDT 24
Finished Jul 26 05:09:15 PM PDT 24
Peak memory 207032 kb
Host smart-ea144237-c223-43ef-8a38-fb664fe54f80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23904
75454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.2390475454
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.466946759
Short name T1053
Test name
Test status
Simulation time 184627593 ps
CPU time 0.87 seconds
Started Jul 26 05:09:13 PM PDT 24
Finished Jul 26 05:09:14 PM PDT 24
Peak memory 207116 kb
Host smart-d7eff183-13f1-4ed6-99ea-32bcbdca0651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46694
6759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.466946759
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.4237567166
Short name T2020
Test name
Test status
Simulation time 293582215 ps
CPU time 1.18 seconds
Started Jul 26 05:09:14 PM PDT 24
Finished Jul 26 05:09:15 PM PDT 24
Peak memory 207116 kb
Host smart-0607f40c-99d3-4b35-98f2-eb52b07b96ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42375
67166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.4237567166
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.3544865470
Short name T1223
Test name
Test status
Simulation time 5822098443 ps
CPU time 162.73 seconds
Started Jul 26 05:09:14 PM PDT 24
Finished Jul 26 05:11:57 PM PDT 24
Peak memory 215536 kb
Host smart-40f855e0-d11b-461a-8193-aeb3e19b528e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3544865470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.3544865470
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.4284652592
Short name T2043
Test name
Test status
Simulation time 229803336 ps
CPU time 0.99 seconds
Started Jul 26 05:09:15 PM PDT 24
Finished Jul 26 05:09:16 PM PDT 24
Peak memory 207136 kb
Host smart-e2957736-fbef-44bd-a50e-c3b8716e5f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42846
52592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.4284652592
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.3943856172
Short name T481
Test name
Test status
Simulation time 371424921 ps
CPU time 1.3 seconds
Started Jul 26 05:09:17 PM PDT 24
Finished Jul 26 05:09:18 PM PDT 24
Peak memory 207016 kb
Host smart-f3179d9a-87fa-4817-ad31-f39392822dfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39438
56172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.3943856172
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.1521269651
Short name T587
Test name
Test status
Simulation time 5344139640 ps
CPU time 169.99 seconds
Started Jul 26 05:09:13 PM PDT 24
Finished Jul 26 05:12:04 PM PDT 24
Peak memory 215536 kb
Host smart-ff9d5625-7b46-4920-9f46-2252428643c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15212
69651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.1521269651
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_timeout_missing_host_handshake.130056477
Short name T2033
Test name
Test status
Simulation time 2347325668 ps
CPU time 59.16 seconds
Started Jul 26 05:09:35 PM PDT 24
Finished Jul 26 05:10:34 PM PDT 24
Peak memory 207360 kb
Host smart-3f8d75aa-0a57-4474-894a-b7228729c381
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130056477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_timeout_missing_host
_handshake.130056477
Directory /workspace/12.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.1548222021
Short name T1114
Test name
Test status
Simulation time 58427175 ps
CPU time 0.7 seconds
Started Jul 26 05:09:29 PM PDT 24
Finished Jul 26 05:09:29 PM PDT 24
Peak memory 207060 kb
Host smart-c4ae0aa6-b1fc-4ede-a57b-730ea197b1a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1548222021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.1548222021
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.1382756993
Short name T1025
Test name
Test status
Simulation time 3783450675 ps
CPU time 5.68 seconds
Started Jul 26 05:09:20 PM PDT 24
Finished Jul 26 05:09:26 PM PDT 24
Peak memory 207400 kb
Host smart-19970c4e-e9a7-4b04-b4de-5b66ee81a5d0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382756993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_a
on_wake_disconnect.1382756993
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.3075535606
Short name T2178
Test name
Test status
Simulation time 13377006452 ps
CPU time 15.08 seconds
Started Jul 26 05:09:20 PM PDT 24
Finished Jul 26 05:09:35 PM PDT 24
Peak memory 207312 kb
Host smart-e11bc578-6668-45c3-9f70-841441d376d7
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075535606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.3075535606
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.1248638651
Short name T1634
Test name
Test status
Simulation time 23370708849 ps
CPU time 31.62 seconds
Started Jul 26 05:09:23 PM PDT 24
Finished Jul 26 05:09:54 PM PDT 24
Peak memory 207320 kb
Host smart-32c6280b-b4ba-40fd-8b38-77aee74a2cc6
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248638651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_a
on_wake_resume.1248638651
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.2066815046
Short name T600
Test name
Test status
Simulation time 177580452 ps
CPU time 0.95 seconds
Started Jul 26 05:09:23 PM PDT 24
Finished Jul 26 05:09:24 PM PDT 24
Peak memory 207100 kb
Host smart-57b34d03-9d63-4b58-abf8-1ec77ea338fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20668
15046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.2066815046
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.690936382
Short name T1254
Test name
Test status
Simulation time 186722931 ps
CPU time 0.88 seconds
Started Jul 26 05:09:23 PM PDT 24
Finished Jul 26 05:09:24 PM PDT 24
Peak memory 207036 kb
Host smart-eb86a20c-1fe0-4ea9-b798-c225a94d4a93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69093
6382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.690936382
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.2030327184
Short name T1074
Test name
Test status
Simulation time 238830692 ps
CPU time 1.02 seconds
Started Jul 26 05:09:20 PM PDT 24
Finished Jul 26 05:09:21 PM PDT 24
Peak memory 207116 kb
Host smart-2124f1a8-f1e5-4d1d-a96f-37310cde2ef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20303
27184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.2030327184
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.322021169
Short name T796
Test name
Test status
Simulation time 1325987630 ps
CPU time 3.34 seconds
Started Jul 26 05:09:19 PM PDT 24
Finished Jul 26 05:09:23 PM PDT 24
Peak memory 207388 kb
Host smart-d2a7bf98-d500-4425-8724-6757fa1127a0
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=322021169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.322021169
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.2781183007
Short name T2803
Test name
Test status
Simulation time 10608572353 ps
CPU time 24.13 seconds
Started Jul 26 05:09:25 PM PDT 24
Finished Jul 26 05:09:49 PM PDT 24
Peak memory 207336 kb
Host smart-095ab8e3-50af-4233-a559-04e0c4b7adb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27811
83007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.2781183007
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_device_timeout.2580806278
Short name T1355
Test name
Test status
Simulation time 4913354223 ps
CPU time 33.27 seconds
Started Jul 26 05:09:20 PM PDT 24
Finished Jul 26 05:09:54 PM PDT 24
Peak memory 207304 kb
Host smart-bccf9887-6e43-4dbf-b333-ec513934cf04
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580806278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_timeout.2580806278
Directory /workspace/13.usbdev_device_timeout/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.4270150574
Short name T2599
Test name
Test status
Simulation time 381248494 ps
CPU time 1.5 seconds
Started Jul 26 05:09:20 PM PDT 24
Finished Jul 26 05:09:22 PM PDT 24
Peak memory 207100 kb
Host smart-1436c33d-7700-4890-bfda-16ce048eeb5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42701
50574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.4270150574
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.2285170874
Short name T598
Test name
Test status
Simulation time 150021416 ps
CPU time 0.85 seconds
Started Jul 26 05:09:20 PM PDT 24
Finished Jul 26 05:09:21 PM PDT 24
Peak memory 206904 kb
Host smart-4a21325e-506c-4889-940d-cbcd21d8ca4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22851
70874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.2285170874
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.1307373506
Short name T2778
Test name
Test status
Simulation time 32056132 ps
CPU time 0.76 seconds
Started Jul 26 05:09:24 PM PDT 24
Finished Jul 26 05:09:25 PM PDT 24
Peak memory 207068 kb
Host smart-28f76df5-c0b5-4682-a1e4-68926fce51ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13073
73506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.1307373506
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.3629544205
Short name T846
Test name
Test status
Simulation time 1040900541 ps
CPU time 2.73 seconds
Started Jul 26 05:09:22 PM PDT 24
Finished Jul 26 05:09:25 PM PDT 24
Peak memory 207312 kb
Host smart-255ae966-9e50-4c74-9e4d-9fb47921f288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36295
44205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.3629544205
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.1540821943
Short name T727
Test name
Test status
Simulation time 236645500 ps
CPU time 1.93 seconds
Started Jul 26 05:09:21 PM PDT 24
Finished Jul 26 05:09:23 PM PDT 24
Peak memory 207352 kb
Host smart-be5a8c2b-6e5f-4283-9647-971fea45fd02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15408
21943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.1540821943
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.3124342606
Short name T1119
Test name
Test status
Simulation time 191630966 ps
CPU time 0.89 seconds
Started Jul 26 05:09:24 PM PDT 24
Finished Jul 26 05:09:26 PM PDT 24
Peak memory 207040 kb
Host smart-7be3708a-15d1-44f7-8ba3-08b097262f10
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3124342606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.3124342606
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.2067632051
Short name T1842
Test name
Test status
Simulation time 143427052 ps
CPU time 0.86 seconds
Started Jul 26 05:09:25 PM PDT 24
Finished Jul 26 05:09:26 PM PDT 24
Peak memory 207000 kb
Host smart-0dd4de79-a336-447c-af85-d2f6894727a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20676
32051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.2067632051
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.2460995886
Short name T829
Test name
Test status
Simulation time 276518670 ps
CPU time 1.09 seconds
Started Jul 26 05:09:22 PM PDT 24
Finished Jul 26 05:09:24 PM PDT 24
Peak memory 207028 kb
Host smart-08ee6b0e-1e9f-47ff-8d15-d78e09c1970d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24609
95886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.2460995886
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_invalid_sync.3116444021
Short name T1076
Test name
Test status
Simulation time 8862843110 ps
CPU time 88.43 seconds
Started Jul 26 05:09:21 PM PDT 24
Finished Jul 26 05:10:49 PM PDT 24
Peak memory 215604 kb
Host smart-84166885-12fe-40e0-a29c-c9d037b53622
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3116444021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.3116444021
Directory /workspace/13.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.3207302322
Short name T2305
Test name
Test status
Simulation time 170822308 ps
CPU time 0.86 seconds
Started Jul 26 05:09:20 PM PDT 24
Finished Jul 26 05:09:21 PM PDT 24
Peak memory 207096 kb
Host smart-b6f98339-b29c-42a7-a27d-3ac2cb8d384f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32073
02322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.3207302322
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.2499492985
Short name T320
Test name
Test status
Simulation time 23323631736 ps
CPU time 30.28 seconds
Started Jul 26 05:09:22 PM PDT 24
Finished Jul 26 05:09:53 PM PDT 24
Peak memory 207220 kb
Host smart-0688b95c-2721-4899-8c15-a109f544883e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24994
92985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.2499492985
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.3745634407
Short name T2789
Test name
Test status
Simulation time 3331682315 ps
CPU time 5.98 seconds
Started Jul 26 05:09:21 PM PDT 24
Finished Jul 26 05:09:27 PM PDT 24
Peak memory 207268 kb
Host smart-5b6065f3-3748-45a7-993e-20357b240cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37456
34407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.3745634407
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.3450313264
Short name T666
Test name
Test status
Simulation time 10625838328 ps
CPU time 332.65 seconds
Started Jul 26 05:09:24 PM PDT 24
Finished Jul 26 05:14:56 PM PDT 24
Peak memory 215504 kb
Host smart-48f418a5-dae7-4a68-b5ea-5591730c64de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34503
13264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.3450313264
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.2842310681
Short name T667
Test name
Test status
Simulation time 5000189780 ps
CPU time 38.79 seconds
Started Jul 26 05:09:20 PM PDT 24
Finished Jul 26 05:09:59 PM PDT 24
Peak memory 207416 kb
Host smart-7c755f3e-acfa-4ef1-8401-8f13b85859b0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2842310681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.2842310681
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.3295632852
Short name T546
Test name
Test status
Simulation time 276612816 ps
CPU time 0.98 seconds
Started Jul 26 05:09:22 PM PDT 24
Finished Jul 26 05:09:23 PM PDT 24
Peak memory 207044 kb
Host smart-b50fc8e6-deb3-4617-90f0-e584acbe04ca
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3295632852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.3295632852
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.3070185852
Short name T1038
Test name
Test status
Simulation time 211471608 ps
CPU time 0.95 seconds
Started Jul 26 05:09:20 PM PDT 24
Finished Jul 26 05:09:21 PM PDT 24
Peak memory 207124 kb
Host smart-78b2a317-e2d3-4550-87d6-9e2cfb37f481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30701
85852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.3070185852
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.2929301299
Short name T2515
Test name
Test status
Simulation time 5482734501 ps
CPU time 56.03 seconds
Started Jul 26 05:09:20 PM PDT 24
Finished Jul 26 05:10:17 PM PDT 24
Peak memory 215612 kb
Host smart-8baf3d67-283e-40bc-b837-62ce70508909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29293
01299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.2929301299
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.4230737742
Short name T1856
Test name
Test status
Simulation time 5015232183 ps
CPU time 142.54 seconds
Started Jul 26 05:09:21 PM PDT 24
Finished Jul 26 05:11:43 PM PDT 24
Peak memory 215608 kb
Host smart-be39483c-7d32-4244-94b8-955895ad6fef
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4230737742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.4230737742
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.1158252565
Short name T781
Test name
Test status
Simulation time 165924852 ps
CPU time 0.84 seconds
Started Jul 26 05:09:21 PM PDT 24
Finished Jul 26 05:09:22 PM PDT 24
Peak memory 207108 kb
Host smart-a569e540-3f3c-4a0b-8566-6568d19fae1c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1158252565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.1158252565
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.2732309563
Short name T2024
Test name
Test status
Simulation time 152450835 ps
CPU time 0.83 seconds
Started Jul 26 05:09:22 PM PDT 24
Finished Jul 26 05:09:24 PM PDT 24
Peak memory 207156 kb
Host smart-e5bc4f63-4767-43be-868b-0c118ec06568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27323
09563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.2732309563
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.3867817340
Short name T2668
Test name
Test status
Simulation time 233616047 ps
CPU time 0.99 seconds
Started Jul 26 05:09:22 PM PDT 24
Finished Jul 26 05:09:23 PM PDT 24
Peak memory 207068 kb
Host smart-6e327f95-88ed-4bbd-97d4-66c0526708be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38678
17340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.3867817340
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.669064576
Short name T2575
Test name
Test status
Simulation time 254491335 ps
CPU time 1.05 seconds
Started Jul 26 05:09:22 PM PDT 24
Finished Jul 26 05:09:23 PM PDT 24
Peak memory 207060 kb
Host smart-ec446ecd-dc84-47d3-9e40-d5d6f407f19e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66906
4576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.669064576
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.1198132250
Short name T1718
Test name
Test status
Simulation time 205506019 ps
CPU time 0.91 seconds
Started Jul 26 05:09:22 PM PDT 24
Finished Jul 26 05:09:23 PM PDT 24
Peak memory 207076 kb
Host smart-9b61b559-0dae-4e6b-a186-aa2f2e1bd437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11981
32250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.1198132250
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.1954929002
Short name T2679
Test name
Test status
Simulation time 149022642 ps
CPU time 0.8 seconds
Started Jul 26 05:09:22 PM PDT 24
Finished Jul 26 05:09:23 PM PDT 24
Peak memory 207080 kb
Host smart-d49a4ea9-6c79-439a-b66b-947c5a01210d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19549
29002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.1954929002
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.479990586
Short name T872
Test name
Test status
Simulation time 153886923 ps
CPU time 0.83 seconds
Started Jul 26 05:09:21 PM PDT 24
Finished Jul 26 05:09:22 PM PDT 24
Peak memory 207092 kb
Host smart-811b1980-3b94-4242-a64f-6934c3e343ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47999
0586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.479990586
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.388502098
Short name T1421
Test name
Test status
Simulation time 224702281 ps
CPU time 1.03 seconds
Started Jul 26 05:09:21 PM PDT 24
Finished Jul 26 05:09:22 PM PDT 24
Peak memory 207040 kb
Host smart-378e2549-146c-4444-bee2-1fbe3a5f99aa
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=388502098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.388502098
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.4082743797
Short name T1892
Test name
Test status
Simulation time 166921851 ps
CPU time 0.87 seconds
Started Jul 26 05:09:21 PM PDT 24
Finished Jul 26 05:09:22 PM PDT 24
Peak memory 207180 kb
Host smart-c491e1da-7fdf-42a0-86fa-947391de1f79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40827
43797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.4082743797
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.1032122486
Short name T2078
Test name
Test status
Simulation time 11387276560 ps
CPU time 29.86 seconds
Started Jul 26 05:09:30 PM PDT 24
Finished Jul 26 05:10:00 PM PDT 24
Peak memory 215604 kb
Host smart-f4364ac3-1684-4227-bb17-a714066e9d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10321
22486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.1032122486
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.3872406445
Short name T404
Test name
Test status
Simulation time 196587177 ps
CPU time 0.99 seconds
Started Jul 26 05:09:30 PM PDT 24
Finished Jul 26 05:09:32 PM PDT 24
Peak memory 207132 kb
Host smart-36ebbb6c-eecd-4627-a440-a5a5396a587c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38724
06445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.3872406445
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.549198333
Short name T315
Test name
Test status
Simulation time 227889253 ps
CPU time 1.01 seconds
Started Jul 26 05:09:32 PM PDT 24
Finished Jul 26 05:09:33 PM PDT 24
Peak memory 207080 kb
Host smart-136f97e0-d901-42a2-910a-70977de116fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54919
8333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.549198333
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.637799163
Short name T2115
Test name
Test status
Simulation time 238124548 ps
CPU time 0.95 seconds
Started Jul 26 05:09:30 PM PDT 24
Finished Jul 26 05:09:32 PM PDT 24
Peak memory 207100 kb
Host smart-f15b3d15-ec43-4677-ab15-5d391764a83d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63779
9163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.637799163
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.2143433058
Short name T435
Test name
Test status
Simulation time 177295630 ps
CPU time 0.9 seconds
Started Jul 26 05:09:31 PM PDT 24
Finished Jul 26 05:09:33 PM PDT 24
Peak memory 207136 kb
Host smart-f5ec7f1b-1bfd-409d-be18-b0d8167715f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21434
33058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.2143433058
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.386487637
Short name T2110
Test name
Test status
Simulation time 195336532 ps
CPU time 0.92 seconds
Started Jul 26 05:09:30 PM PDT 24
Finished Jul 26 05:09:31 PM PDT 24
Peak memory 207064 kb
Host smart-2bf5f541-eaa0-492a-a723-17b4ab37dbc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38648
7637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.386487637
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.4045831342
Short name T1222
Test name
Test status
Simulation time 189987420 ps
CPU time 0.89 seconds
Started Jul 26 05:09:29 PM PDT 24
Finished Jul 26 05:09:30 PM PDT 24
Peak memory 207064 kb
Host smart-6cc727ec-3fb0-4460-b833-e6c3fd0b85e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40458
31342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.4045831342
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.3747949645
Short name T1906
Test name
Test status
Simulation time 164655463 ps
CPU time 0.86 seconds
Started Jul 26 05:09:30 PM PDT 24
Finished Jul 26 05:09:31 PM PDT 24
Peak memory 207096 kb
Host smart-df2cb84f-2934-48f3-8733-d76a54c24526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37479
49645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.3747949645
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.3175584782
Short name T1928
Test name
Test status
Simulation time 234836811 ps
CPU time 0.97 seconds
Started Jul 26 05:09:31 PM PDT 24
Finished Jul 26 05:09:32 PM PDT 24
Peak memory 207068 kb
Host smart-b45de532-28a8-4a2d-9a90-59b7efba37f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31755
84782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.3175584782
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.4194538031
Short name T1279
Test name
Test status
Simulation time 5430832627 ps
CPU time 154.12 seconds
Started Jul 26 05:09:31 PM PDT 24
Finished Jul 26 05:12:06 PM PDT 24
Peak memory 215480 kb
Host smart-22bd8bc3-d2dc-4993-8f6e-8722e7d25520
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4194538031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.4194538031
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.1372504916
Short name T2013
Test name
Test status
Simulation time 166337006 ps
CPU time 0.87 seconds
Started Jul 26 05:09:31 PM PDT 24
Finished Jul 26 05:09:32 PM PDT 24
Peak memory 207140 kb
Host smart-3a3c894c-2122-4034-a70e-b8ada2e0c6f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13725
04916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.1372504916
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.1478113315
Short name T862
Test name
Test status
Simulation time 259663157 ps
CPU time 0.97 seconds
Started Jul 26 05:09:30 PM PDT 24
Finished Jul 26 05:09:32 PM PDT 24
Peak memory 207128 kb
Host smart-5f89455b-d73f-430c-a0e3-3433124861b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14781
13315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.1478113315
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.3485182016
Short name T653
Test name
Test status
Simulation time 1270227565 ps
CPU time 2.98 seconds
Started Jul 26 05:09:29 PM PDT 24
Finished Jul 26 05:09:32 PM PDT 24
Peak memory 207184 kb
Host smart-84efa08d-7e38-453e-ae6f-a2b44e8f68eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34851
82016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.3485182016
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.911324496
Short name T1706
Test name
Test status
Simulation time 5463884935 ps
CPU time 164.66 seconds
Started Jul 26 05:09:33 PM PDT 24
Finished Jul 26 05:12:18 PM PDT 24
Peak memory 215624 kb
Host smart-b131b46a-9bec-40f0-91de-1a4269c7e3a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91132
4496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.911324496
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_timeout_missing_host_handshake.3877353700
Short name T384
Test name
Test status
Simulation time 1119228703 ps
CPU time 10.5 seconds
Started Jul 26 05:09:21 PM PDT 24
Finished Jul 26 05:09:32 PM PDT 24
Peak memory 207152 kb
Host smart-0835d4d9-2421-42e3-a8bb-412f3b65e57f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877353700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_timeout_missing_hos
t_handshake.3877353700
Directory /workspace/13.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.2764621504
Short name T1922
Test name
Test status
Simulation time 36832252 ps
CPU time 0.68 seconds
Started Jul 26 05:09:53 PM PDT 24
Finished Jul 26 05:09:54 PM PDT 24
Peak memory 207220 kb
Host smart-e85fbb91-bfcf-4259-bc75-ec958019d55a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2764621504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.2764621504
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.1612103798
Short name T217
Test name
Test status
Simulation time 3931860000 ps
CPU time 5.56 seconds
Started Jul 26 05:09:30 PM PDT 24
Finished Jul 26 05:09:36 PM PDT 24
Peak memory 207248 kb
Host smart-37217ebb-92ff-4745-ae40-39ddacbe6db9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612103798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_a
on_wake_disconnect.1612103798
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.1287955318
Short name T1374
Test name
Test status
Simulation time 13338795751 ps
CPU time 16.46 seconds
Started Jul 26 05:09:30 PM PDT 24
Finished Jul 26 05:09:46 PM PDT 24
Peak memory 207200 kb
Host smart-ffbdb115-05c4-4a59-9744-12837c6630e2
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287955318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.1287955318
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.3288767662
Short name T2128
Test name
Test status
Simulation time 23376653844 ps
CPU time 33.81 seconds
Started Jul 26 05:09:32 PM PDT 24
Finished Jul 26 05:10:07 PM PDT 24
Peak memory 207320 kb
Host smart-cab6a778-6f25-4268-b435-a899d6260cbb
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288767662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_a
on_wake_resume.3288767662
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.914684458
Short name T2699
Test name
Test status
Simulation time 181337507 ps
CPU time 0.94 seconds
Started Jul 26 05:09:30 PM PDT 24
Finished Jul 26 05:09:31 PM PDT 24
Peak memory 207020 kb
Host smart-20649d49-4856-4bc5-a0aa-a952032db47b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91468
4458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.914684458
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.3115555785
Short name T792
Test name
Test status
Simulation time 179550835 ps
CPU time 0.9 seconds
Started Jul 26 05:09:42 PM PDT 24
Finished Jul 26 05:09:43 PM PDT 24
Peak memory 206980 kb
Host smart-13330d2f-9092-4f35-907d-66e79e54aae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31155
55785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.3115555785
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.2698359191
Short name T2223
Test name
Test status
Simulation time 460171866 ps
CPU time 1.49 seconds
Started Jul 26 05:09:39 PM PDT 24
Finished Jul 26 05:09:40 PM PDT 24
Peak memory 207100 kb
Host smart-ce5e08c4-2f20-494f-8a4c-7049e4b430f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26983
59191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.2698359191
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.739570978
Short name T86
Test name
Test status
Simulation time 809600135 ps
CPU time 2.17 seconds
Started Jul 26 05:09:41 PM PDT 24
Finished Jul 26 05:09:43 PM PDT 24
Peak memory 207204 kb
Host smart-dd1eb2ae-0065-41b1-8a62-6f0d3de229a7
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=739570978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.739570978
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.3347756591
Short name T87
Test name
Test status
Simulation time 14782770725 ps
CPU time 31.12 seconds
Started Jul 26 05:09:39 PM PDT 24
Finished Jul 26 05:10:10 PM PDT 24
Peak memory 207320 kb
Host smart-811e092f-728a-4e35-aa80-1c7ccbc2f8fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33477
56591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.3347756591
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_device_timeout.2183457608
Short name T2705
Test name
Test status
Simulation time 2523273018 ps
CPU time 22 seconds
Started Jul 26 05:09:38 PM PDT 24
Finished Jul 26 05:10:00 PM PDT 24
Peak memory 207352 kb
Host smart-da6797a6-de54-4a86-bccd-011a7d5ad3c2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183457608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_timeout.2183457608
Directory /workspace/14.usbdev_device_timeout/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.3409823598
Short name T839
Test name
Test status
Simulation time 410387948 ps
CPU time 1.33 seconds
Started Jul 26 05:09:39 PM PDT 24
Finished Jul 26 05:09:41 PM PDT 24
Peak memory 206944 kb
Host smart-2ea88908-0579-4b9b-bb58-c9144081930b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34098
23598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.3409823598
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.3219050784
Short name T740
Test name
Test status
Simulation time 140249229 ps
CPU time 0.8 seconds
Started Jul 26 05:09:39 PM PDT 24
Finished Jul 26 05:09:40 PM PDT 24
Peak memory 207096 kb
Host smart-6f364167-7b10-4c9a-b8f9-3634246a2662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32190
50784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.3219050784
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.2769538534
Short name T935
Test name
Test status
Simulation time 35553629 ps
CPU time 0.7 seconds
Started Jul 26 05:09:39 PM PDT 24
Finished Jul 26 05:09:40 PM PDT 24
Peak memory 206988 kb
Host smart-e8c9510b-d69e-41c1-8d91-6271697c1d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27695
38534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.2769538534
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.2578402736
Short name T1970
Test name
Test status
Simulation time 885262564 ps
CPU time 2.38 seconds
Started Jul 26 05:09:41 PM PDT 24
Finished Jul 26 05:09:43 PM PDT 24
Peak memory 207304 kb
Host smart-1ba4469f-d261-46b0-8cff-bbcc0a56a43a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25784
02736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.2578402736
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.2345088591
Short name T2151
Test name
Test status
Simulation time 278528899 ps
CPU time 2.31 seconds
Started Jul 26 05:09:42 PM PDT 24
Finished Jul 26 05:09:45 PM PDT 24
Peak memory 207364 kb
Host smart-87050a68-6b50-4cda-91d2-70efebd87b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23450
88591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.2345088591
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.2411264938
Short name T2093
Test name
Test status
Simulation time 199795244 ps
CPU time 1.13 seconds
Started Jul 26 05:09:41 PM PDT 24
Finished Jul 26 05:09:42 PM PDT 24
Peak memory 215456 kb
Host smart-e573ed78-7db1-487b-8966-c1a42666bad2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2411264938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.2411264938
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.3609657280
Short name T590
Test name
Test status
Simulation time 173656721 ps
CPU time 0.86 seconds
Started Jul 26 05:09:40 PM PDT 24
Finished Jul 26 05:09:41 PM PDT 24
Peak memory 207032 kb
Host smart-d5bb5327-20d2-4375-a5a2-3f6a810e56ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36096
57280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.3609657280
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.2335709226
Short name T1049
Test name
Test status
Simulation time 218082396 ps
CPU time 0.97 seconds
Started Jul 26 05:09:41 PM PDT 24
Finished Jul 26 05:09:42 PM PDT 24
Peak memory 207132 kb
Host smart-2df812ec-779c-4071-8e07-b272db34b55d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23357
09226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.2335709226
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.182767854
Short name T1046
Test name
Test status
Simulation time 4328489372 ps
CPU time 32.99 seconds
Started Jul 26 05:09:42 PM PDT 24
Finished Jul 26 05:10:16 PM PDT 24
Peak memory 215488 kb
Host smart-b6ba5b2a-6a2a-4ec2-892c-06684f47e7fa
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=182767854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.182767854
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_iso_retraction.3731421256
Short name T1345
Test name
Test status
Simulation time 12131626170 ps
CPU time 152.4 seconds
Started Jul 26 05:09:38 PM PDT 24
Finished Jul 26 05:12:10 PM PDT 24
Peak memory 207344 kb
Host smart-8185d93e-a28f-4318-966f-23001c5e70ed
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3731421256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.3731421256
Directory /workspace/14.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.3414591304
Short name T2640
Test name
Test status
Simulation time 224280676 ps
CPU time 0.96 seconds
Started Jul 26 05:09:40 PM PDT 24
Finished Jul 26 05:09:41 PM PDT 24
Peak memory 207112 kb
Host smart-58d685b0-cda6-4f7a-b98e-3849b7c0ab75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34145
91304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.3414591304
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.1690647208
Short name T352
Test name
Test status
Simulation time 23349052457 ps
CPU time 29.78 seconds
Started Jul 26 05:09:37 PM PDT 24
Finished Jul 26 05:10:07 PM PDT 24
Peak memory 207232 kb
Host smart-5a9abe3e-7840-4dc7-8b4a-aed3ec1831c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16906
47208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.1690647208
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.2820368322
Short name T1358
Test name
Test status
Simulation time 3299517509 ps
CPU time 5.48 seconds
Started Jul 26 05:09:38 PM PDT 24
Finished Jul 26 05:09:43 PM PDT 24
Peak memory 207260 kb
Host smart-f15c147b-f355-4d40-b99b-c46bdb72e0a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28203
68322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.2820368322
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.4236223052
Short name T2402
Test name
Test status
Simulation time 8221642624 ps
CPU time 83.28 seconds
Started Jul 26 05:09:40 PM PDT 24
Finished Jul 26 05:11:03 PM PDT 24
Peak memory 223676 kb
Host smart-c64dfbfa-374b-4bff-be05-b9d8b1fdcf22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42362
23052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.4236223052
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.564949786
Short name T460
Test name
Test status
Simulation time 3344140245 ps
CPU time 35.59 seconds
Started Jul 26 05:09:41 PM PDT 24
Finished Jul 26 05:10:17 PM PDT 24
Peak memory 216920 kb
Host smart-144cbf72-3ba2-4d10-9a52-61352032ae2e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=564949786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.564949786
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.3736583148
Short name T375
Test name
Test status
Simulation time 246389399 ps
CPU time 1.01 seconds
Started Jul 26 05:09:43 PM PDT 24
Finished Jul 26 05:09:44 PM PDT 24
Peak memory 207148 kb
Host smart-a1b382ab-3f42-43db-aed2-e138f19fdca3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3736583148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.3736583148
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.2040978555
Short name T1312
Test name
Test status
Simulation time 201976372 ps
CPU time 1.01 seconds
Started Jul 26 05:09:42 PM PDT 24
Finished Jul 26 05:09:44 PM PDT 24
Peak memory 207212 kb
Host smart-d91d8c8c-cb4c-495e-a09e-d40de7bc8b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20409
78555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.2040978555
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.3178508972
Short name T2611
Test name
Test status
Simulation time 4126468523 ps
CPU time 129.71 seconds
Started Jul 26 05:09:40 PM PDT 24
Finished Jul 26 05:11:50 PM PDT 24
Peak memory 215600 kb
Host smart-d24c8137-4f4e-4a1a-bec7-06c79ffcb0ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31785
08972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.3178508972
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.2379755915
Short name T2184
Test name
Test status
Simulation time 3345101382 ps
CPU time 94.77 seconds
Started Jul 26 05:09:41 PM PDT 24
Finished Jul 26 05:11:15 PM PDT 24
Peak memory 215556 kb
Host smart-961ff12d-64c9-4334-a1a9-9f43ba357069
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2379755915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.2379755915
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.2834485391
Short name T1587
Test name
Test status
Simulation time 159605504 ps
CPU time 0.92 seconds
Started Jul 26 05:09:41 PM PDT 24
Finished Jul 26 05:09:42 PM PDT 24
Peak memory 207140 kb
Host smart-d3d60504-7ecd-4b68-ac4b-526b07f04806
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2834485391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.2834485391
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.850346834
Short name T1362
Test name
Test status
Simulation time 148222582 ps
CPU time 0.82 seconds
Started Jul 26 05:09:41 PM PDT 24
Finished Jul 26 05:09:42 PM PDT 24
Peak memory 207092 kb
Host smart-d8dfc127-0b38-4bdc-90a8-5fb62904da1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85034
6834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.850346834
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.2418710037
Short name T134
Test name
Test status
Simulation time 231336779 ps
CPU time 1.05 seconds
Started Jul 26 05:09:39 PM PDT 24
Finished Jul 26 05:09:40 PM PDT 24
Peak memory 207064 kb
Host smart-61b3fae3-6d92-41d7-a63d-f2aa08162566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24187
10037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.2418710037
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.1210202789
Short name T2201
Test name
Test status
Simulation time 192120277 ps
CPU time 0.93 seconds
Started Jul 26 05:09:40 PM PDT 24
Finished Jul 26 05:09:41 PM PDT 24
Peak memory 207100 kb
Host smart-1c8d96b6-f9c1-469b-8772-de436ec4ae7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12102
02789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.1210202789
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.2492310067
Short name T1697
Test name
Test status
Simulation time 144545215 ps
CPU time 0.85 seconds
Started Jul 26 05:09:39 PM PDT 24
Finished Jul 26 05:09:40 PM PDT 24
Peak memory 207048 kb
Host smart-5b1cce90-2789-4c27-81e3-09a9cd26cee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24923
10067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.2492310067
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.971025278
Short name T2475
Test name
Test status
Simulation time 176612780 ps
CPU time 0.87 seconds
Started Jul 26 05:09:40 PM PDT 24
Finished Jul 26 05:09:41 PM PDT 24
Peak memory 207072 kb
Host smart-1c8f4ec3-5e03-400c-9bc4-8492f9030d00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97102
5278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.971025278
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.1875191144
Short name T2323
Test name
Test status
Simulation time 165105296 ps
CPU time 0.88 seconds
Started Jul 26 05:09:40 PM PDT 24
Finished Jul 26 05:09:41 PM PDT 24
Peak memory 207108 kb
Host smart-f9c8ad82-c236-4543-b07d-c1c9db27ebb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18751
91144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.1875191144
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.2060267492
Short name T824
Test name
Test status
Simulation time 253223758 ps
CPU time 1.05 seconds
Started Jul 26 05:09:40 PM PDT 24
Finished Jul 26 05:09:41 PM PDT 24
Peak memory 207148 kb
Host smart-3978ad1b-e4a7-45db-92bb-c69907188ae9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2060267492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.2060267492
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.3962504181
Short name T1008
Test name
Test status
Simulation time 199640609 ps
CPU time 0.91 seconds
Started Jul 26 05:09:40 PM PDT 24
Finished Jul 26 05:09:41 PM PDT 24
Peak memory 207072 kb
Host smart-440f2dcd-7a2b-44ca-8936-23126d6362ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39625
04181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.3962504181
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.2169310385
Short name T2246
Test name
Test status
Simulation time 32531183 ps
CPU time 0.69 seconds
Started Jul 26 05:09:42 PM PDT 24
Finished Jul 26 05:09:42 PM PDT 24
Peak memory 207000 kb
Host smart-e43b054b-78f9-4d9e-9837-00126c1dc5ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21693
10385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.2169310385
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.4117837105
Short name T239
Test name
Test status
Simulation time 13996116904 ps
CPU time 39.17 seconds
Started Jul 26 05:09:38 PM PDT 24
Finished Jul 26 05:10:17 PM PDT 24
Peak memory 215568 kb
Host smart-62e21fbe-63b7-45c6-963e-8930a27d03bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41178
37105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.4117837105
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.688778453
Short name T2632
Test name
Test status
Simulation time 173220365 ps
CPU time 0.9 seconds
Started Jul 26 05:09:41 PM PDT 24
Finished Jul 26 05:09:42 PM PDT 24
Peak memory 207028 kb
Host smart-e5bd342c-7d14-46ff-bf19-374c1b312e78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68877
8453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.688778453
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.3196958823
Short name T2656
Test name
Test status
Simulation time 186812260 ps
CPU time 0.91 seconds
Started Jul 26 05:09:41 PM PDT 24
Finished Jul 26 05:09:42 PM PDT 24
Peak memory 207036 kb
Host smart-2a7aaf77-7e6e-4254-904e-475bc08af1d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31969
58823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.3196958823
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.3430120303
Short name T1357
Test name
Test status
Simulation time 265672982 ps
CPU time 1.01 seconds
Started Jul 26 05:09:39 PM PDT 24
Finished Jul 26 05:09:40 PM PDT 24
Peak memory 207056 kb
Host smart-edc45898-3bcf-4ca9-ba3e-2fc48861e230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34301
20303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.3430120303
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.2610833614
Short name T2667
Test name
Test status
Simulation time 218431143 ps
CPU time 1 seconds
Started Jul 26 05:09:43 PM PDT 24
Finished Jul 26 05:09:44 PM PDT 24
Peak memory 207084 kb
Host smart-eac30e10-ee7d-4bd6-b5bc-19ebd996c1ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26108
33614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.2610833614
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.2951348240
Short name T1983
Test name
Test status
Simulation time 162839611 ps
CPU time 0.82 seconds
Started Jul 26 05:09:42 PM PDT 24
Finished Jul 26 05:09:43 PM PDT 24
Peak memory 206960 kb
Host smart-d86422a7-cbb3-4f36-bd0c-673bcaf0cc50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29513
48240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.2951348240
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.3863151702
Short name T2401
Test name
Test status
Simulation time 164234488 ps
CPU time 0.84 seconds
Started Jul 26 05:09:39 PM PDT 24
Finished Jul 26 05:09:40 PM PDT 24
Peak memory 206992 kb
Host smart-2354e2bb-5ffe-4763-9d8b-c974c78f7dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38631
51702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.3863151702
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.3964297168
Short name T1476
Test name
Test status
Simulation time 148928247 ps
CPU time 0.88 seconds
Started Jul 26 05:09:50 PM PDT 24
Finished Jul 26 05:09:51 PM PDT 24
Peak memory 207052 kb
Host smart-344c4639-f5b1-4276-8bbb-2801e2ba1bd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39642
97168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.3964297168
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.2007851842
Short name T991
Test name
Test status
Simulation time 299244208 ps
CPU time 1.15 seconds
Started Jul 26 05:09:51 PM PDT 24
Finished Jul 26 05:09:52 PM PDT 24
Peak memory 207128 kb
Host smart-5f9520a2-c22b-4263-aa3a-0fc915ae1493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20078
51842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.2007851842
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.1210952696
Short name T1268
Test name
Test status
Simulation time 3420659869 ps
CPU time 95.21 seconds
Started Jul 26 05:09:50 PM PDT 24
Finished Jul 26 05:11:26 PM PDT 24
Peak memory 215536 kb
Host smart-c151c3cb-cc18-4f82-947b-10ad30e5cb22
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1210952696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.1210952696
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.2285550793
Short name T2259
Test name
Test status
Simulation time 155390316 ps
CPU time 0.87 seconds
Started Jul 26 05:09:56 PM PDT 24
Finished Jul 26 05:09:57 PM PDT 24
Peak memory 207096 kb
Host smart-ce8ace4b-c28b-4cae-9d40-717f8dd5f832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22855
50793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.2285550793
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.3093285590
Short name T1132
Test name
Test status
Simulation time 150790046 ps
CPU time 0.88 seconds
Started Jul 26 05:09:50 PM PDT 24
Finished Jul 26 05:09:51 PM PDT 24
Peak memory 207128 kb
Host smart-82483f43-31c3-4163-8a02-e9f53e2053f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30932
85590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.3093285590
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.1681429894
Short name T638
Test name
Test status
Simulation time 1201584123 ps
CPU time 2.66 seconds
Started Jul 26 05:09:50 PM PDT 24
Finished Jul 26 05:09:52 PM PDT 24
Peak memory 207284 kb
Host smart-89722ab5-5361-4c8f-924c-b4fd1ae877d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16814
29894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.1681429894
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.3481066065
Short name T396
Test name
Test status
Simulation time 3199981771 ps
CPU time 24.79 seconds
Started Jul 26 05:09:49 PM PDT 24
Finished Jul 26 05:10:14 PM PDT 24
Peak memory 215528 kb
Host smart-9087317e-3fd1-4983-868d-f135bde47ccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34810
66065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.3481066065
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_timeout_missing_host_handshake.1949692078
Short name T951
Test name
Test status
Simulation time 645343176 ps
CPU time 4.82 seconds
Started Jul 26 05:09:42 PM PDT 24
Finished Jul 26 05:09:47 PM PDT 24
Peak memory 207212 kb
Host smart-fa2b9f04-8270-453e-a859-6552ce86b067
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949692078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_timeout_missing_hos
t_handshake.1949692078
Directory /workspace/14.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.2588192679
Short name T893
Test name
Test status
Simulation time 49772133 ps
CPU time 0.66 seconds
Started Jul 26 05:10:00 PM PDT 24
Finished Jul 26 05:10:01 PM PDT 24
Peak memory 207064 kb
Host smart-7e4d6a42-4497-48dd-b36b-7ad4751f5a0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2588192679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.2588192679
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.1571154827
Short name T1266
Test name
Test status
Simulation time 3876046865 ps
CPU time 6.49 seconds
Started Jul 26 05:09:58 PM PDT 24
Finished Jul 26 05:10:04 PM PDT 24
Peak memory 207324 kb
Host smart-8aafc6d0-1007-4943-b9be-2d6e8baefd38
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571154827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_disconnect.1571154827
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.4012274076
Short name T2051
Test name
Test status
Simulation time 13357497173 ps
CPU time 17.64 seconds
Started Jul 26 05:09:49 PM PDT 24
Finished Jul 26 05:10:07 PM PDT 24
Peak memory 207388 kb
Host smart-b9c83c2b-290a-47db-8279-0e44395f505d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012274076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.4012274076
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.902573090
Short name T1151
Test name
Test status
Simulation time 23528550210 ps
CPU time 34.65 seconds
Started Jul 26 05:09:49 PM PDT 24
Finished Jul 26 05:10:24 PM PDT 24
Peak memory 207364 kb
Host smart-2ddc66d6-886f-4597-b113-1187e721b2ea
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902573090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_ao
n_wake_resume.902573090
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.1053124042
Short name T314
Test name
Test status
Simulation time 171475523 ps
CPU time 0.9 seconds
Started Jul 26 05:09:50 PM PDT 24
Finished Jul 26 05:09:51 PM PDT 24
Peak memory 207172 kb
Host smart-cfb24e12-59d4-4de3-879f-ad7f7dbc13cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10531
24042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.1053124042
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.1094331458
Short name T1110
Test name
Test status
Simulation time 146222139 ps
CPU time 0.85 seconds
Started Jul 26 05:09:57 PM PDT 24
Finished Jul 26 05:09:58 PM PDT 24
Peak memory 207020 kb
Host smart-d98e05b2-b81b-4b3c-8f44-c25c4bf5850f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10943
31458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.1094331458
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.1840736894
Short name T339
Test name
Test status
Simulation time 375728463 ps
CPU time 1.34 seconds
Started Jul 26 05:09:51 PM PDT 24
Finished Jul 26 05:09:52 PM PDT 24
Peak memory 207040 kb
Host smart-7910b410-0b5b-4680-9a94-d179ca561568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18407
36894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.1840736894
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.2060946723
Short name T539
Test name
Test status
Simulation time 1176884415 ps
CPU time 2.91 seconds
Started Jul 26 05:09:51 PM PDT 24
Finished Jul 26 05:09:54 PM PDT 24
Peak memory 207168 kb
Host smart-2a8e1c27-4477-42a9-8d2c-36a86dd45037
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2060946723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.2060946723
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.3207388555
Short name T2428
Test name
Test status
Simulation time 16616767484 ps
CPU time 37.3 seconds
Started Jul 26 05:09:49 PM PDT 24
Finished Jul 26 05:10:27 PM PDT 24
Peak memory 207288 kb
Host smart-93236d4f-be00-4505-bdbf-7911e801104c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32073
88555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.3207388555
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_device_timeout.2983877725
Short name T61
Test name
Test status
Simulation time 609998291 ps
CPU time 13.35 seconds
Started Jul 26 05:09:49 PM PDT 24
Finished Jul 26 05:10:03 PM PDT 24
Peak memory 207316 kb
Host smart-cc4a7ca0-5b54-4aea-b503-8b66fb1aca01
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983877725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_timeout.2983877725
Directory /workspace/15.usbdev_device_timeout/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.3508819249
Short name T1168
Test name
Test status
Simulation time 377603246 ps
CPU time 1.38 seconds
Started Jul 26 05:09:57 PM PDT 24
Finished Jul 26 05:09:59 PM PDT 24
Peak memory 207016 kb
Host smart-63afae46-2673-44d7-87a7-9c70ae442270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35088
19249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.3508819249
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.2431731472
Short name T2688
Test name
Test status
Simulation time 142132521 ps
CPU time 0.81 seconds
Started Jul 26 05:09:50 PM PDT 24
Finished Jul 26 05:09:51 PM PDT 24
Peak memory 207100 kb
Host smart-1ba7614b-7ab4-46c7-839e-cabca05a3dca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24317
31472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.2431731472
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.1513191024
Short name T2603
Test name
Test status
Simulation time 37830184 ps
CPU time 0.7 seconds
Started Jul 26 05:09:49 PM PDT 24
Finished Jul 26 05:09:50 PM PDT 24
Peak memory 207096 kb
Host smart-bc615a54-af06-4f8f-881c-0fe1a77432e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15131
91024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.1513191024
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.3070400139
Short name T1208
Test name
Test status
Simulation time 930451597 ps
CPU time 2.69 seconds
Started Jul 26 05:09:48 PM PDT 24
Finished Jul 26 05:09:51 PM PDT 24
Peak memory 207312 kb
Host smart-c8949759-47fe-498d-8031-336439b8a2c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30704
00139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.3070400139
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.3343961132
Short name T1608
Test name
Test status
Simulation time 267980551 ps
CPU time 1.78 seconds
Started Jul 26 05:09:50 PM PDT 24
Finished Jul 26 05:09:52 PM PDT 24
Peak memory 207340 kb
Host smart-ba340184-d07e-4f6f-bbc6-fab33d42a78d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33439
61132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.3343961132
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.4068323391
Short name T1519
Test name
Test status
Simulation time 191667531 ps
CPU time 0.95 seconds
Started Jul 26 05:09:50 PM PDT 24
Finished Jul 26 05:09:51 PM PDT 24
Peak memory 207208 kb
Host smart-a2c16ac2-ea01-45b2-b0bb-0f81442d7f8d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4068323391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.4068323391
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.3958017172
Short name T603
Test name
Test status
Simulation time 159510093 ps
CPU time 0.86 seconds
Started Jul 26 05:09:51 PM PDT 24
Finished Jul 26 05:09:52 PM PDT 24
Peak memory 206944 kb
Host smart-eb093cc3-e2a6-41e0-b5c9-c9c0a057d391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39580
17172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.3958017172
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.594206883
Short name T2225
Test name
Test status
Simulation time 178109055 ps
CPU time 0.98 seconds
Started Jul 26 05:09:51 PM PDT 24
Finished Jul 26 05:09:52 PM PDT 24
Peak memory 207132 kb
Host smart-3f41f558-f0d4-4010-98eb-554ee7017937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59420
6883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.594206883
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.609319695
Short name T1611
Test name
Test status
Simulation time 9089168507 ps
CPU time 74.88 seconds
Started Jul 26 05:09:57 PM PDT 24
Finished Jul 26 05:11:12 PM PDT 24
Peak memory 216792 kb
Host smart-4cb02e9c-72b6-4a48-8dd3-673e818d8b55
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=609319695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.609319695
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_iso_retraction.2370343623
Short name T103
Test name
Test status
Simulation time 10102352392 ps
CPU time 128.97 seconds
Started Jul 26 05:09:49 PM PDT 24
Finished Jul 26 05:11:58 PM PDT 24
Peak memory 207240 kb
Host smart-e7e29e94-92b2-4a33-a3b2-963bb27ca137
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2370343623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.2370343623
Directory /workspace/15.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.2325961102
Short name T1293
Test name
Test status
Simulation time 239060712 ps
CPU time 1 seconds
Started Jul 26 05:09:55 PM PDT 24
Finished Jul 26 05:09:56 PM PDT 24
Peak memory 207124 kb
Host smart-8fe77ab8-4547-49b3-bcae-f1f02aece826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23259
61102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.2325961102
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.803061413
Short name T887
Test name
Test status
Simulation time 23289208319 ps
CPU time 31.35 seconds
Started Jul 26 05:09:52 PM PDT 24
Finished Jul 26 05:10:24 PM PDT 24
Peak memory 207460 kb
Host smart-067754ad-5ee6-44b3-9cb2-d263ba8b1372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80306
1413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.803061413
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.2027549404
Short name T317
Test name
Test status
Simulation time 3292487049 ps
CPU time 5.11 seconds
Started Jul 26 05:09:48 PM PDT 24
Finished Jul 26 05:09:54 PM PDT 24
Peak memory 207316 kb
Host smart-90207374-e6dc-49aa-8b23-169000011c17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20275
49404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.2027549404
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.3323920190
Short name T2449
Test name
Test status
Simulation time 5269961240 ps
CPU time 50.43 seconds
Started Jul 26 05:09:54 PM PDT 24
Finished Jul 26 05:10:45 PM PDT 24
Peak memory 217312 kb
Host smart-32557e38-2fb4-49f7-9a39-e72f0aa4a74c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33239
20190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.3323920190
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.2242845070
Short name T1865
Test name
Test status
Simulation time 4405475571 ps
CPU time 127.46 seconds
Started Jul 26 05:09:55 PM PDT 24
Finished Jul 26 05:12:03 PM PDT 24
Peak memory 215532 kb
Host smart-9c73ace8-03a4-40fb-8d81-b29ea38e8a23
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2242845070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.2242845070
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.896634056
Short name T1082
Test name
Test status
Simulation time 266090069 ps
CPU time 1 seconds
Started Jul 26 05:09:52 PM PDT 24
Finished Jul 26 05:09:53 PM PDT 24
Peak memory 207108 kb
Host smart-c17ea61b-bd3d-4f8f-a30e-da3ab850755d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=896634056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.896634056
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.3744213722
Short name T2270
Test name
Test status
Simulation time 195104978 ps
CPU time 0.98 seconds
Started Jul 26 05:09:58 PM PDT 24
Finished Jul 26 05:09:59 PM PDT 24
Peak memory 207048 kb
Host smart-cd7bd691-c9bb-4676-8b6f-2054ad341eeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37442
13722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.3744213722
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.573721340
Short name T1263
Test name
Test status
Simulation time 6543345813 ps
CPU time 51.38 seconds
Started Jul 26 05:09:52 PM PDT 24
Finished Jul 26 05:10:44 PM PDT 24
Peak memory 217004 kb
Host smart-90ec0e19-7c4c-4ecb-9bc1-db485fca0072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57372
1340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.573721340
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.56700295
Short name T156
Test name
Test status
Simulation time 4748704966 ps
CPU time 55.85 seconds
Started Jul 26 05:09:56 PM PDT 24
Finished Jul 26 05:10:52 PM PDT 24
Peak memory 207416 kb
Host smart-cdad5503-8439-4db9-8af5-c40bdac1dc56
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=56700295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.56700295
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.140146996
Short name T1494
Test name
Test status
Simulation time 199097977 ps
CPU time 0.9 seconds
Started Jul 26 05:09:50 PM PDT 24
Finished Jul 26 05:09:51 PM PDT 24
Peak memory 207048 kb
Host smart-1e1e6ee7-5667-4efa-ab94-4a4c53fedbf0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=140146996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.140146996
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.2766880727
Short name T543
Test name
Test status
Simulation time 153770037 ps
CPU time 0.84 seconds
Started Jul 26 05:09:55 PM PDT 24
Finished Jul 26 05:09:56 PM PDT 24
Peak memory 207072 kb
Host smart-385cd91b-4f05-4a69-996b-82b5dad6255b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27668
80727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.2766880727
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.1306669891
Short name T107
Test name
Test status
Simulation time 189865110 ps
CPU time 0.93 seconds
Started Jul 26 05:09:52 PM PDT 24
Finished Jul 26 05:09:53 PM PDT 24
Peak memory 207080 kb
Host smart-d2343279-9de3-40e2-8963-0b2e96ecca25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13066
69891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.1306669891
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.1467936044
Short name T1775
Test name
Test status
Simulation time 182365984 ps
CPU time 0.88 seconds
Started Jul 26 05:09:51 PM PDT 24
Finished Jul 26 05:09:52 PM PDT 24
Peak memory 206976 kb
Host smart-af3bb321-a34f-41a2-bc5e-972bd11ef766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14679
36044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.1467936044
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.1713092736
Short name T208
Test name
Test status
Simulation time 183771256 ps
CPU time 0.89 seconds
Started Jul 26 05:09:49 PM PDT 24
Finished Jul 26 05:09:50 PM PDT 24
Peak memory 207020 kb
Host smart-cd2dea14-081d-4edd-b219-728d4103a6d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17130
92736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.1713092736
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.2643004625
Short name T943
Test name
Test status
Simulation time 172042757 ps
CPU time 0.86 seconds
Started Jul 26 05:09:52 PM PDT 24
Finished Jul 26 05:09:53 PM PDT 24
Peak memory 206988 kb
Host smart-a46b8725-e4f4-4a26-b9d6-7b389304bde0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26430
04625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.2643004625
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.3727127922
Short name T657
Test name
Test status
Simulation time 216479312 ps
CPU time 1.1 seconds
Started Jul 26 05:09:48 PM PDT 24
Finished Jul 26 05:09:49 PM PDT 24
Peak memory 207072 kb
Host smart-d19da821-4351-4e39-83a3-36c9ce6e8787
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3727127922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.3727127922
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.12911994
Short name T2746
Test name
Test status
Simulation time 166583469 ps
CPU time 0.85 seconds
Started Jul 26 05:09:50 PM PDT 24
Finished Jul 26 05:09:51 PM PDT 24
Peak memory 207016 kb
Host smart-df01ac09-437f-4086-b013-56556538a827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12911
994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.12911994
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.553920127
Short name T1514
Test name
Test status
Simulation time 41044435 ps
CPU time 0.69 seconds
Started Jul 26 05:09:52 PM PDT 24
Finished Jul 26 05:09:53 PM PDT 24
Peak memory 206960 kb
Host smart-c46bb695-3336-4bd7-9d92-ec0f20590c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55392
0127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.553920127
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.3624171197
Short name T691
Test name
Test status
Simulation time 13557536669 ps
CPU time 35.98 seconds
Started Jul 26 05:09:56 PM PDT 24
Finished Jul 26 05:10:32 PM PDT 24
Peak memory 219280 kb
Host smart-be911455-ff5e-44ab-9037-cc35663d243c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36241
71197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.3624171197
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.2894256005
Short name T1682
Test name
Test status
Simulation time 204632534 ps
CPU time 1.02 seconds
Started Jul 26 05:09:50 PM PDT 24
Finished Jul 26 05:09:51 PM PDT 24
Peak memory 207152 kb
Host smart-a44c9a26-fb49-4419-95e5-d6a548cf77be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28942
56005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.2894256005
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.3646252101
Short name T1316
Test name
Test status
Simulation time 162382718 ps
CPU time 0.89 seconds
Started Jul 26 05:10:00 PM PDT 24
Finished Jul 26 05:10:01 PM PDT 24
Peak memory 207128 kb
Host smart-bfed887e-0f5c-4e0a-b693-d36c0b712c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36462
52101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.3646252101
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.1638489009
Short name T1452
Test name
Test status
Simulation time 168538667 ps
CPU time 0.92 seconds
Started Jul 26 05:10:03 PM PDT 24
Finished Jul 26 05:10:04 PM PDT 24
Peak memory 207024 kb
Host smart-7a8c283c-cbd8-4f6e-a213-d2985d1534d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16384
89009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.1638489009
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.2558686653
Short name T1659
Test name
Test status
Simulation time 209025691 ps
CPU time 0.96 seconds
Started Jul 26 05:10:04 PM PDT 24
Finished Jul 26 05:10:05 PM PDT 24
Peak memory 207052 kb
Host smart-5a234071-d374-4fea-a6d4-dfade47b15d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25586
86653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.2558686653
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.3820031818
Short name T1645
Test name
Test status
Simulation time 247943734 ps
CPU time 1.06 seconds
Started Jul 26 05:10:09 PM PDT 24
Finished Jul 26 05:10:10 PM PDT 24
Peak memory 207068 kb
Host smart-a2624010-88ab-494c-b547-17abb7069b2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38200
31818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.3820031818
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.3677382765
Short name T1253
Test name
Test status
Simulation time 159021990 ps
CPU time 0.82 seconds
Started Jul 26 05:09:58 PM PDT 24
Finished Jul 26 05:09:59 PM PDT 24
Peak memory 206980 kb
Host smart-251b3340-7c9a-4a8f-b7a9-d3a76e1fee47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36773
82765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.3677382765
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.1302379081
Short name T611
Test name
Test status
Simulation time 184569615 ps
CPU time 0.86 seconds
Started Jul 26 05:09:59 PM PDT 24
Finished Jul 26 05:10:00 PM PDT 24
Peak memory 206992 kb
Host smart-3d5ecbe3-da49-4e72-908d-9822b6db2690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13023
79081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.1302379081
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.3693836018
Short name T2767
Test name
Test status
Simulation time 194454506 ps
CPU time 0.93 seconds
Started Jul 26 05:10:10 PM PDT 24
Finished Jul 26 05:10:12 PM PDT 24
Peak memory 207132 kb
Host smart-0033e257-1749-4cb2-b064-cdfd8728887b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36938
36018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.3693836018
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.1458274099
Short name T1847
Test name
Test status
Simulation time 4699894702 ps
CPU time 50.93 seconds
Started Jul 26 05:10:09 PM PDT 24
Finished Jul 26 05:11:00 PM PDT 24
Peak memory 216900 kb
Host smart-a5d2e0ff-74a5-4d08-8c45-40883ff87fe1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1458274099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.1458274099
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.998272597
Short name T273
Test name
Test status
Simulation time 182138020 ps
CPU time 0.86 seconds
Started Jul 26 05:09:59 PM PDT 24
Finished Jul 26 05:10:00 PM PDT 24
Peak memory 206956 kb
Host smart-0423f97a-4e8f-44ed-ad64-1178f71925b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99827
2597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.998272597
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.611850399
Short name T1859
Test name
Test status
Simulation time 186131445 ps
CPU time 0.88 seconds
Started Jul 26 05:10:02 PM PDT 24
Finished Jul 26 05:10:03 PM PDT 24
Peak memory 207080 kb
Host smart-694c6f06-c15e-41fc-a946-84620195322a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61185
0399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.611850399
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.4032923430
Short name T2765
Test name
Test status
Simulation time 718924658 ps
CPU time 1.9 seconds
Started Jul 26 05:10:00 PM PDT 24
Finished Jul 26 05:10:02 PM PDT 24
Peak memory 207048 kb
Host smart-2712b0ef-fa94-4e58-8e19-c5446e7f5aa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40329
23430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.4032923430
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.3751475553
Short name T1671
Test name
Test status
Simulation time 4413366834 ps
CPU time 47.46 seconds
Started Jul 26 05:10:03 PM PDT 24
Finished Jul 26 05:10:50 PM PDT 24
Peak memory 207344 kb
Host smart-7212d286-89f7-4920-bbd1-4fb4c3887c8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37514
75553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.3751475553
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_timeout_missing_host_handshake.1861564848
Short name T630
Test name
Test status
Simulation time 1054825245 ps
CPU time 22.05 seconds
Started Jul 26 05:09:48 PM PDT 24
Finished Jul 26 05:10:10 PM PDT 24
Peak memory 207236 kb
Host smart-27ee990f-592b-44c8-a45e-f6c549b89468
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861564848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_timeout_missing_hos
t_handshake.1861564848
Directory /workspace/15.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.132371982
Short name T1131
Test name
Test status
Simulation time 57576086 ps
CPU time 0.67 seconds
Started Jul 26 05:10:12 PM PDT 24
Finished Jul 26 05:10:13 PM PDT 24
Peak memory 206736 kb
Host smart-d3d18a0f-3857-4266-8a7f-eaef5e8952e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=132371982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.132371982
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.3149061195
Short name T1036
Test name
Test status
Simulation time 4002581999 ps
CPU time 6.29 seconds
Started Jul 26 05:10:00 PM PDT 24
Finished Jul 26 05:10:06 PM PDT 24
Peak memory 207376 kb
Host smart-090d68bf-b295-4705-8e74-39b7fa40fbe8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149061195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_a
on_wake_disconnect.3149061195
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.1929189662
Short name T1202
Test name
Test status
Simulation time 13392924587 ps
CPU time 18.5 seconds
Started Jul 26 05:09:59 PM PDT 24
Finished Jul 26 05:10:17 PM PDT 24
Peak memory 207264 kb
Host smart-8dc881d5-bb01-4454-a09c-902b60dd05d7
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929189662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.1929189662
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.775051019
Short name T1560
Test name
Test status
Simulation time 23389125976 ps
CPU time 30.26 seconds
Started Jul 26 05:10:05 PM PDT 24
Finished Jul 26 05:10:35 PM PDT 24
Peak memory 207312 kb
Host smart-80e9aafc-9241-4266-b2ef-fd94763b09c1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775051019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_ao
n_wake_resume.775051019
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.3480280156
Short name T1871
Test name
Test status
Simulation time 186101741 ps
CPU time 0.96 seconds
Started Jul 26 05:10:02 PM PDT 24
Finished Jul 26 05:10:03 PM PDT 24
Peak memory 206980 kb
Host smart-0aab4dca-a6bf-4568-8575-9e0a479152e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34802
80156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.3480280156
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.3435129791
Short name T1684
Test name
Test status
Simulation time 171731791 ps
CPU time 0.85 seconds
Started Jul 26 05:10:03 PM PDT 24
Finished Jul 26 05:10:04 PM PDT 24
Peak memory 206960 kb
Host smart-9eecb121-2962-4dda-b581-10e55ac058ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34351
29791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.3435129791
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.2351277626
Short name T2801
Test name
Test status
Simulation time 492215315 ps
CPU time 1.49 seconds
Started Jul 26 05:10:01 PM PDT 24
Finished Jul 26 05:10:02 PM PDT 24
Peak memory 207100 kb
Host smart-236e1a6c-e9a8-4250-99a4-0eaf715019fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23512
77626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.2351277626
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.1799440470
Short name T1882
Test name
Test status
Simulation time 497044786 ps
CPU time 1.72 seconds
Started Jul 26 05:10:00 PM PDT 24
Finished Jul 26 05:10:02 PM PDT 24
Peak memory 207048 kb
Host smart-efbc5cda-3f01-4856-bb95-bb1b925c0ab9
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1799440470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.1799440470
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_timeout.2514197879
Short name T1338
Test name
Test status
Simulation time 1562292838 ps
CPU time 13.47 seconds
Started Jul 26 05:09:59 PM PDT 24
Finished Jul 26 05:10:13 PM PDT 24
Peak memory 207368 kb
Host smart-40672b49-415f-4f9e-8638-eaf1fbcd8533
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514197879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_timeout.2514197879
Directory /workspace/16.usbdev_device_timeout/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.574633699
Short name T1079
Test name
Test status
Simulation time 433031244 ps
CPU time 1.49 seconds
Started Jul 26 05:10:02 PM PDT 24
Finished Jul 26 05:10:04 PM PDT 24
Peak memory 207096 kb
Host smart-ef914ab4-fb4e-461f-9e4d-5630f4abae44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57463
3699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.574633699
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.3343981818
Short name T2717
Test name
Test status
Simulation time 161061490 ps
CPU time 0.9 seconds
Started Jul 26 05:10:01 PM PDT 24
Finished Jul 26 05:10:02 PM PDT 24
Peak memory 207032 kb
Host smart-f2ef12de-b62b-4084-8874-39f07807d48a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33439
81818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.3343981818
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.159096503
Short name T2760
Test name
Test status
Simulation time 44133411 ps
CPU time 0.71 seconds
Started Jul 26 05:10:00 PM PDT 24
Finished Jul 26 05:10:01 PM PDT 24
Peak memory 207064 kb
Host smart-88f33358-85c8-4eec-99c4-b03dfc292b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15909
6503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.159096503
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.3825353362
Short name T2222
Test name
Test status
Simulation time 665296696 ps
CPU time 1.91 seconds
Started Jul 26 05:10:00 PM PDT 24
Finished Jul 26 05:10:02 PM PDT 24
Peak memory 207344 kb
Host smart-a931f5b8-0e8d-41a8-98e5-ac4a17676a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38253
53362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.3825353362
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.3859759003
Short name T2068
Test name
Test status
Simulation time 345854829 ps
CPU time 2.9 seconds
Started Jul 26 05:10:01 PM PDT 24
Finished Jul 26 05:10:04 PM PDT 24
Peak memory 207344 kb
Host smart-ea7636b5-410d-4ba7-996e-be6e30ea9c6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38597
59003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.3859759003
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.3068558811
Short name T995
Test name
Test status
Simulation time 196296623 ps
CPU time 1.02 seconds
Started Jul 26 05:09:59 PM PDT 24
Finished Jul 26 05:10:00 PM PDT 24
Peak memory 215508 kb
Host smart-79db954b-729d-4544-a580-e5e40ff027ec
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3068558811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.3068558811
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.3999990468
Short name T1216
Test name
Test status
Simulation time 158800061 ps
CPU time 0.89 seconds
Started Jul 26 05:09:59 PM PDT 24
Finished Jul 26 05:10:00 PM PDT 24
Peak memory 207068 kb
Host smart-66a72ffa-d8f4-409d-8449-5872a9d51db1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39999
90468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.3999990468
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.760783608
Short name T2336
Test name
Test status
Simulation time 184118115 ps
CPU time 0.92 seconds
Started Jul 26 05:10:01 PM PDT 24
Finished Jul 26 05:10:02 PM PDT 24
Peak memory 206980 kb
Host smart-2f88aba6-1285-4272-b090-b6670057fdd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76078
3608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.760783608
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.2351290604
Short name T2345
Test name
Test status
Simulation time 7444853418 ps
CPU time 57.19 seconds
Started Jul 26 05:10:09 PM PDT 24
Finished Jul 26 05:11:06 PM PDT 24
Peak memory 215608 kb
Host smart-b8bde87d-869f-4413-806b-e64145e69854
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2351290604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.2351290604
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/16.usbdev_iso_retraction.3996035637
Short name T609
Test name
Test status
Simulation time 10413407308 ps
CPU time 125.66 seconds
Started Jul 26 05:10:01 PM PDT 24
Finished Jul 26 05:12:07 PM PDT 24
Peak memory 207368 kb
Host smart-647e5f3b-1259-4e78-abf9-0fa412395080
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3996035637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.3996035637
Directory /workspace/16.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.255747065
Short name T2526
Test name
Test status
Simulation time 215312481 ps
CPU time 0.95 seconds
Started Jul 26 05:09:59 PM PDT 24
Finished Jul 26 05:10:00 PM PDT 24
Peak memory 207092 kb
Host smart-70e1930e-494d-4fba-96e7-da4ad49d8d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25574
7065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.255747065
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.3500163753
Short name T536
Test name
Test status
Simulation time 23402299598 ps
CPU time 25.9 seconds
Started Jul 26 05:10:17 PM PDT 24
Finished Jul 26 05:10:43 PM PDT 24
Peak memory 207344 kb
Host smart-b47a9cb7-e489-448e-a939-207bc306d182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35001
63753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.3500163753
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.2399944887
Short name T2634
Test name
Test status
Simulation time 3273325147 ps
CPU time 5.42 seconds
Started Jul 26 05:10:03 PM PDT 24
Finished Jul 26 05:10:08 PM PDT 24
Peak memory 207252 kb
Host smart-9e86131f-055b-4963-a748-70eccc49f808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23999
44887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.2399944887
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.3757394728
Short name T2491
Test name
Test status
Simulation time 10211850425 ps
CPU time 102.72 seconds
Started Jul 26 05:10:00 PM PDT 24
Finished Jul 26 05:11:43 PM PDT 24
Peak memory 223772 kb
Host smart-94d0d3d9-66f4-4355-a4f5-5620330d1f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37573
94728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.3757394728
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.4054278551
Short name T2536
Test name
Test status
Simulation time 5266174826 ps
CPU time 44.04 seconds
Started Jul 26 05:10:00 PM PDT 24
Finished Jul 26 05:10:44 PM PDT 24
Peak memory 207360 kb
Host smart-cb895b92-e601-4fa0-afc6-3173b87eb52f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4054278551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.4054278551
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.787489652
Short name T2535
Test name
Test status
Simulation time 308577917 ps
CPU time 1.1 seconds
Started Jul 26 05:10:10 PM PDT 24
Finished Jul 26 05:10:11 PM PDT 24
Peak memory 207060 kb
Host smart-f829d7fb-68fe-4408-8a27-93b9d2ba8465
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=787489652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.787489652
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.469521986
Short name T2638
Test name
Test status
Simulation time 185940766 ps
CPU time 1.02 seconds
Started Jul 26 05:10:02 PM PDT 24
Finished Jul 26 05:10:03 PM PDT 24
Peak memory 207068 kb
Host smart-8a448bbd-ff17-4238-8983-12d53f81e872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46952
1986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.469521986
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.2369043242
Short name T1571
Test name
Test status
Simulation time 6427010205 ps
CPU time 188.29 seconds
Started Jul 26 05:10:12 PM PDT 24
Finished Jul 26 05:13:20 PM PDT 24
Peak memory 215516 kb
Host smart-e41489e8-ee58-4ca2-a6bb-637e504b1003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23690
43242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.2369043242
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.2246382910
Short name T1949
Test name
Test status
Simulation time 3445818664 ps
CPU time 37.56 seconds
Started Jul 26 05:10:02 PM PDT 24
Finished Jul 26 05:10:39 PM PDT 24
Peak memory 217020 kb
Host smart-f62786da-0eaf-4373-a5e8-ea713f39bd2b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2246382910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.2246382910
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.2902102042
Short name T1499
Test name
Test status
Simulation time 175728244 ps
CPU time 0.85 seconds
Started Jul 26 05:10:00 PM PDT 24
Finished Jul 26 05:10:01 PM PDT 24
Peak memory 207108 kb
Host smart-9491b0e8-3f98-47f0-8bc6-5736841b6803
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2902102042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.2902102042
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.3548376425
Short name T2412
Test name
Test status
Simulation time 164919176 ps
CPU time 0.86 seconds
Started Jul 26 05:10:00 PM PDT 24
Finished Jul 26 05:10:01 PM PDT 24
Peak memory 207100 kb
Host smart-179e3e75-a2e4-4d34-9437-6846ee48a0cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35483
76425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.3548376425
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.3182519267
Short name T2618
Test name
Test status
Simulation time 241333727 ps
CPU time 0.93 seconds
Started Jul 26 05:10:01 PM PDT 24
Finished Jul 26 05:10:02 PM PDT 24
Peak memory 207072 kb
Host smart-88253b35-1409-464f-9f6d-0bd601e9a974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31825
19267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.3182519267
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.3949866286
Short name T2150
Test name
Test status
Simulation time 206545518 ps
CPU time 0.96 seconds
Started Jul 26 05:10:01 PM PDT 24
Finished Jul 26 05:10:02 PM PDT 24
Peak memory 207040 kb
Host smart-a6c6ff98-3e47-43ad-b001-a9435ca133ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39498
66286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.3949866286
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.1722702939
Short name T595
Test name
Test status
Simulation time 164426914 ps
CPU time 0.91 seconds
Started Jul 26 05:10:01 PM PDT 24
Finished Jul 26 05:10:02 PM PDT 24
Peak memory 207212 kb
Host smart-c768ba04-1bd2-4ccd-92ac-0a45b4bb6de6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17227
02939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.1722702939
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.3616052693
Short name T990
Test name
Test status
Simulation time 195592624 ps
CPU time 0.93 seconds
Started Jul 26 05:10:09 PM PDT 24
Finished Jul 26 05:10:10 PM PDT 24
Peak memory 207048 kb
Host smart-c09f665e-6a60-4dbf-9ec6-1dcff0c6186b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36160
52693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.3616052693
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.525435210
Short name T151
Test name
Test status
Simulation time 146012830 ps
CPU time 0.88 seconds
Started Jul 26 05:10:05 PM PDT 24
Finished Jul 26 05:10:06 PM PDT 24
Peak memory 207024 kb
Host smart-b114a409-4024-4315-b1e2-797168fdc289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52543
5210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.525435210
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.912593299
Short name T699
Test name
Test status
Simulation time 231490882 ps
CPU time 1.11 seconds
Started Jul 26 05:10:02 PM PDT 24
Finished Jul 26 05:10:03 PM PDT 24
Peak memory 206752 kb
Host smart-6043e724-d16a-4fa3-8ce9-664747351209
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=912593299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.912593299
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.2944397794
Short name T2534
Test name
Test status
Simulation time 142673357 ps
CPU time 0.83 seconds
Started Jul 26 05:10:03 PM PDT 24
Finished Jul 26 05:10:04 PM PDT 24
Peak memory 207056 kb
Host smart-948312e8-c329-4fd2-8964-5f390e0f1b0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29443
97794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.2944397794
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.2137121914
Short name T36
Test name
Test status
Simulation time 35333678 ps
CPU time 0.72 seconds
Started Jul 26 05:10:05 PM PDT 24
Finished Jul 26 05:10:06 PM PDT 24
Peak memory 206996 kb
Host smart-95b9ccdf-5807-4ecf-8113-8365add4872f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21371
21914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.2137121914
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.2647656389
Short name T1438
Test name
Test status
Simulation time 15507111258 ps
CPU time 44.23 seconds
Started Jul 26 05:10:02 PM PDT 24
Finished Jul 26 05:10:46 PM PDT 24
Peak memory 215356 kb
Host smart-8aea4ae9-e022-44aa-9ddd-be75a8bca7b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26476
56389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.2647656389
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.1768037058
Short name T1533
Test name
Test status
Simulation time 169369482 ps
CPU time 0.91 seconds
Started Jul 26 05:10:01 PM PDT 24
Finished Jul 26 05:10:02 PM PDT 24
Peak memory 207072 kb
Host smart-0532a75e-1e45-4e58-abe0-2ae1ef46289a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17680
37058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.1768037058
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.2586965861
Short name T2733
Test name
Test status
Simulation time 223880571 ps
CPU time 1.01 seconds
Started Jul 26 05:10:02 PM PDT 24
Finished Jul 26 05:10:03 PM PDT 24
Peak memory 207028 kb
Host smart-6f5911fa-9c1e-449b-8653-d97958dd245a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25869
65861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.2586965861
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.2528582246
Short name T957
Test name
Test status
Simulation time 216249521 ps
CPU time 0.9 seconds
Started Jul 26 05:10:02 PM PDT 24
Finished Jul 26 05:10:03 PM PDT 24
Peak memory 207080 kb
Host smart-85fd06b1-3ca9-46e0-b129-005c32626525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25285
82246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.2528582246
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.1752550623
Short name T1158
Test name
Test status
Simulation time 185944503 ps
CPU time 0.93 seconds
Started Jul 26 05:10:00 PM PDT 24
Finished Jul 26 05:10:01 PM PDT 24
Peak memory 207136 kb
Host smart-e1053cea-c6f2-417a-b33e-2633fb6b2072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17525
50623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.1752550623
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.3400386580
Short name T635
Test name
Test status
Simulation time 142080966 ps
CPU time 0.81 seconds
Started Jul 26 05:10:03 PM PDT 24
Finished Jul 26 05:10:03 PM PDT 24
Peak memory 207048 kb
Host smart-e4c1fd00-35d7-4764-b2c9-58d62d94b16a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34003
86580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.3400386580
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.2969008630
Short name T515
Test name
Test status
Simulation time 153397137 ps
CPU time 0.95 seconds
Started Jul 26 05:10:04 PM PDT 24
Finished Jul 26 05:10:05 PM PDT 24
Peak memory 207024 kb
Host smart-d7382f2d-048c-4e2d-b378-2a580746dbee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29690
08630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.2969008630
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.2055101296
Short name T50
Test name
Test status
Simulation time 154380523 ps
CPU time 0.91 seconds
Started Jul 26 05:10:04 PM PDT 24
Finished Jul 26 05:10:05 PM PDT 24
Peak memory 207148 kb
Host smart-fe6699a8-cf57-4bf8-8d4d-a8b692e448b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20551
01296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.2055101296
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.3757269010
Short name T2606
Test name
Test status
Simulation time 221685751 ps
CPU time 0.97 seconds
Started Jul 26 05:10:10 PM PDT 24
Finished Jul 26 05:10:11 PM PDT 24
Peak memory 207124 kb
Host smart-4a6b691b-7907-4227-b430-717bf3ab6145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37572
69010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.3757269010
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.4184602803
Short name T2348
Test name
Test status
Simulation time 7478468706 ps
CPU time 220.96 seconds
Started Jul 26 05:10:19 PM PDT 24
Finished Jul 26 05:14:00 PM PDT 24
Peak memory 215552 kb
Host smart-df32c484-c716-4931-a8ea-32743711792c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4184602803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.4184602803
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.75737426
Short name T1835
Test name
Test status
Simulation time 153830842 ps
CPU time 0.81 seconds
Started Jul 26 05:10:10 PM PDT 24
Finished Jul 26 05:10:11 PM PDT 24
Peak memory 207144 kb
Host smart-9d5c9857-6270-4cb2-b98d-285548087112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75737
426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.75737426
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.3625796785
Short name T1205
Test name
Test status
Simulation time 224866672 ps
CPU time 0.97 seconds
Started Jul 26 05:10:11 PM PDT 24
Finished Jul 26 05:10:12 PM PDT 24
Peak memory 207024 kb
Host smart-e00e8698-5895-4c2c-ba6d-bb784e468733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36257
96785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.3625796785
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.1051881306
Short name T1824
Test name
Test status
Simulation time 197684164 ps
CPU time 0.96 seconds
Started Jul 26 05:10:09 PM PDT 24
Finished Jul 26 05:10:11 PM PDT 24
Peak memory 207036 kb
Host smart-9ad10c40-a915-4f75-a683-556a6b66f909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10518
81306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.1051881306
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.621964129
Short name T904
Test name
Test status
Simulation time 5519659495 ps
CPU time 178.31 seconds
Started Jul 26 05:10:09 PM PDT 24
Finished Jul 26 05:13:07 PM PDT 24
Peak memory 215412 kb
Host smart-7ba4f765-dee3-45d5-8c83-a78f4badfcf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62196
4129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.621964129
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_timeout_missing_host_handshake.3687004073
Short name T2843
Test name
Test status
Simulation time 1052248845 ps
CPU time 23.63 seconds
Started Jul 26 05:10:08 PM PDT 24
Finished Jul 26 05:10:32 PM PDT 24
Peak memory 207328 kb
Host smart-86dcc560-3409-4e3a-81a9-382ffcd8ad2e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687004073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_timeout_missing_hos
t_handshake.3687004073
Directory /workspace/16.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.1463457847
Short name T2524
Test name
Test status
Simulation time 3845864210 ps
CPU time 5.42 seconds
Started Jul 26 05:10:11 PM PDT 24
Finished Jul 26 05:10:17 PM PDT 24
Peak memory 207264 kb
Host smart-007f3430-5b2e-4e3a-bb46-1e33154ff5e0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463457847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_a
on_wake_disconnect.1463457847
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.641108066
Short name T1761
Test name
Test status
Simulation time 13384530549 ps
CPU time 15.68 seconds
Started Jul 26 05:10:12 PM PDT 24
Finished Jul 26 05:10:28 PM PDT 24
Peak memory 207400 kb
Host smart-227033df-9fa3-4771-a69e-4ca7b22652bb
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=641108066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.641108066
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.3180389732
Short name T922
Test name
Test status
Simulation time 23346456643 ps
CPU time 26.23 seconds
Started Jul 26 05:10:13 PM PDT 24
Finished Jul 26 05:10:39 PM PDT 24
Peak memory 207288 kb
Host smart-903a28c8-536b-4695-a562-7c824b5700fd
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180389732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_a
on_wake_resume.3180389732
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.2205995029
Short name T1689
Test name
Test status
Simulation time 196387553 ps
CPU time 0.95 seconds
Started Jul 26 05:10:11 PM PDT 24
Finished Jul 26 05:10:12 PM PDT 24
Peak memory 207120 kb
Host smart-3b7d6328-077c-487f-b8ea-b264fbefccad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22059
95029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.2205995029
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.3192433779
Short name T1257
Test name
Test status
Simulation time 210673434 ps
CPU time 0.94 seconds
Started Jul 26 05:10:19 PM PDT 24
Finished Jul 26 05:10:20 PM PDT 24
Peak memory 207048 kb
Host smart-af8a10d8-205a-499a-ab8a-141ea8959b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31924
33779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.3192433779
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.2284734066
Short name T2741
Test name
Test status
Simulation time 180044108 ps
CPU time 0.95 seconds
Started Jul 26 05:10:14 PM PDT 24
Finished Jul 26 05:10:16 PM PDT 24
Peak memory 207048 kb
Host smart-5ba89fb5-4926-4dff-9773-f00da1834a36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22847
34066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.2284734066
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.2504724611
Short name T486
Test name
Test status
Simulation time 1050906099 ps
CPU time 2.44 seconds
Started Jul 26 05:10:11 PM PDT 24
Finished Jul 26 05:10:14 PM PDT 24
Peak memory 207316 kb
Host smart-38bf822d-70b1-4a8b-8fb3-55de7eeaeaa8
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2504724611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.2504724611
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.590101154
Short name T88
Test name
Test status
Simulation time 20518977340 ps
CPU time 55.27 seconds
Started Jul 26 05:10:12 PM PDT 24
Finished Jul 26 05:11:07 PM PDT 24
Peak memory 207388 kb
Host smart-5721daec-3005-486d-a6f4-a319a4976a7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59010
1154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.590101154
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_device_timeout.2056127487
Short name T531
Test name
Test status
Simulation time 5738252704 ps
CPU time 38.95 seconds
Started Jul 26 05:10:10 PM PDT 24
Finished Jul 26 05:10:49 PM PDT 24
Peak memory 207280 kb
Host smart-4d8b1ec3-724f-432a-8548-d3b1a7071aec
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056127487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_timeout.2056127487
Directory /workspace/17.usbdev_device_timeout/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.2883095242
Short name T527
Test name
Test status
Simulation time 436407321 ps
CPU time 1.44 seconds
Started Jul 26 05:10:16 PM PDT 24
Finished Jul 26 05:10:18 PM PDT 24
Peak memory 206772 kb
Host smart-6786941e-d1dc-4a2d-a15c-3bbcce186c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28830
95242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.2883095242
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.3109094835
Short name T2626
Test name
Test status
Simulation time 139992526 ps
CPU time 0.84 seconds
Started Jul 26 05:10:09 PM PDT 24
Finished Jul 26 05:10:10 PM PDT 24
Peak memory 207096 kb
Host smart-f653281c-e910-4fdd-89b7-9004ca49d4b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31090
94835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.3109094835
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.2045658344
Short name T2505
Test name
Test status
Simulation time 52064643 ps
CPU time 0.71 seconds
Started Jul 26 05:10:11 PM PDT 24
Finished Jul 26 05:10:12 PM PDT 24
Peak memory 207008 kb
Host smart-283140ef-8767-4b27-ae27-583d05342a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20456
58344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.2045658344
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.2817280700
Short name T1064
Test name
Test status
Simulation time 830227812 ps
CPU time 2.43 seconds
Started Jul 26 05:10:10 PM PDT 24
Finished Jul 26 05:10:13 PM PDT 24
Peak memory 207240 kb
Host smart-909543cf-c662-4d62-904f-6e40f52aa387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28172
80700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.2817280700
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.230199694
Short name T2356
Test name
Test status
Simulation time 196919974 ps
CPU time 1.58 seconds
Started Jul 26 05:10:15 PM PDT 24
Finished Jul 26 05:10:17 PM PDT 24
Peak memory 207344 kb
Host smart-c6777545-25fb-4c40-9aca-4138e3248d33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23019
9694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.230199694
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.2825837012
Short name T1565
Test name
Test status
Simulation time 225985898 ps
CPU time 1.19 seconds
Started Jul 26 05:10:12 PM PDT 24
Finished Jul 26 05:10:13 PM PDT 24
Peak memory 207336 kb
Host smart-acbf5e20-f47a-44c1-a21c-039d632cb50a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2825837012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.2825837012
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.3895281771
Short name T770
Test name
Test status
Simulation time 139099774 ps
CPU time 0.78 seconds
Started Jul 26 05:10:16 PM PDT 24
Finished Jul 26 05:10:17 PM PDT 24
Peak memory 207072 kb
Host smart-7ac0127f-f79c-4849-a546-2f5eb93052f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38952
81771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.3895281771
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.3492276020
Short name T353
Test name
Test status
Simulation time 151899416 ps
CPU time 0.91 seconds
Started Jul 26 05:10:20 PM PDT 24
Finished Jul 26 05:10:21 PM PDT 24
Peak memory 207080 kb
Host smart-1e2d8aaf-5b21-4bdb-b781-439c61a57539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34922
76020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.3492276020
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.354820142
Short name T1635
Test name
Test status
Simulation time 5604696019 ps
CPU time 163.26 seconds
Started Jul 26 05:10:13 PM PDT 24
Finished Jul 26 05:12:56 PM PDT 24
Peak memory 215464 kb
Host smart-f3c07117-7e7e-4c55-adc6-2c8a48d1e238
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=354820142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.354820142
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/17.usbdev_iso_retraction.914605755
Short name T2509
Test name
Test status
Simulation time 7074370338 ps
CPU time 43.44 seconds
Started Jul 26 05:10:12 PM PDT 24
Finished Jul 26 05:10:56 PM PDT 24
Peak memory 206972 kb
Host smart-27b98e7b-532d-405f-82be-035570d25455
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=914605755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.914605755
Directory /workspace/17.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.2790180935
Short name T1629
Test name
Test status
Simulation time 174762282 ps
CPU time 0.87 seconds
Started Jul 26 05:10:21 PM PDT 24
Finished Jul 26 05:10:22 PM PDT 24
Peak memory 207100 kb
Host smart-f2e056b0-957b-4e70-bb80-0f0a783ce0df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27901
80935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.2790180935
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.3735470757
Short name T1857
Test name
Test status
Simulation time 23339038903 ps
CPU time 26.79 seconds
Started Jul 26 05:10:11 PM PDT 24
Finished Jul 26 05:10:38 PM PDT 24
Peak memory 207268 kb
Host smart-09ceedc8-7293-4c6e-a06f-b51307f34a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37354
70757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.3735470757
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.3385568137
Short name T2271
Test name
Test status
Simulation time 3316533523 ps
CPU time 5.11 seconds
Started Jul 26 05:10:10 PM PDT 24
Finished Jul 26 05:10:15 PM PDT 24
Peak memory 207308 kb
Host smart-8de54f53-0e81-44af-8bdf-86868e0e1aab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33855
68137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.3385568137
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.1048162847
Short name T1899
Test name
Test status
Simulation time 4565443192 ps
CPU time 124.92 seconds
Started Jul 26 05:10:19 PM PDT 24
Finished Jul 26 05:12:24 PM PDT 24
Peak memory 223512 kb
Host smart-be65c80e-9ed2-4688-b5c4-f19e7a1795e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10481
62847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.1048162847
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.526677486
Short name T482
Test name
Test status
Simulation time 7779161080 ps
CPU time 81.97 seconds
Started Jul 26 05:10:15 PM PDT 24
Finished Jul 26 05:11:37 PM PDT 24
Peak memory 207364 kb
Host smart-bf097b8e-2bb0-4cb6-86b5-829e799f5313
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=526677486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.526677486
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.829997949
Short name T844
Test name
Test status
Simulation time 256232463 ps
CPU time 1.06 seconds
Started Jul 26 05:10:10 PM PDT 24
Finished Jul 26 05:10:11 PM PDT 24
Peak memory 207112 kb
Host smart-62b08103-bc69-46d5-b8ef-65efbb530317
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=829997949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.829997949
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.3201965393
Short name T2574
Test name
Test status
Simulation time 190878461 ps
CPU time 0.94 seconds
Started Jul 26 05:10:16 PM PDT 24
Finished Jul 26 05:10:17 PM PDT 24
Peak memory 206788 kb
Host smart-93525f42-300c-4250-99c7-19ee54adbc81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32019
65393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.3201965393
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.3706640678
Short name T1324
Test name
Test status
Simulation time 5169508874 ps
CPU time 58.69 seconds
Started Jul 26 05:10:10 PM PDT 24
Finished Jul 26 05:11:09 PM PDT 24
Peak memory 217076 kb
Host smart-ce82e10a-2072-47ef-b80b-fcacb867bdf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37066
40678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.3706640678
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.389999853
Short name T717
Test name
Test status
Simulation time 6585599846 ps
CPU time 69.49 seconds
Started Jul 26 05:10:14 PM PDT 24
Finished Jul 26 05:11:24 PM PDT 24
Peak memory 207376 kb
Host smart-5eda3f4c-49cf-47ae-bb81-4b217629c5fe
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=389999853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.389999853
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.85382146
Short name T2347
Test name
Test status
Simulation time 165723299 ps
CPU time 0.92 seconds
Started Jul 26 05:10:12 PM PDT 24
Finished Jul 26 05:10:13 PM PDT 24
Peak memory 207044 kb
Host smart-929dbc6c-c3be-4ca9-bec5-86b28f38a3cd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=85382146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.85382146
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.524724081
Short name T927
Test name
Test status
Simulation time 163112767 ps
CPU time 0.89 seconds
Started Jul 26 05:10:19 PM PDT 24
Finished Jul 26 05:10:21 PM PDT 24
Peak memory 207076 kb
Host smart-6e5a92a6-8146-4ce8-83f9-706fb76af5c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52472
4081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.524724081
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.4236488182
Short name T121
Test name
Test status
Simulation time 180061492 ps
CPU time 0.94 seconds
Started Jul 26 05:10:14 PM PDT 24
Finished Jul 26 05:10:15 PM PDT 24
Peak memory 207016 kb
Host smart-ddf52282-17d1-4af5-9590-3c0efb484cbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42364
88182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.4236488182
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.2382609463
Short name T2691
Test name
Test status
Simulation time 152371660 ps
CPU time 0.85 seconds
Started Jul 26 05:10:10 PM PDT 24
Finished Jul 26 05:10:11 PM PDT 24
Peak memory 207068 kb
Host smart-bb3726a3-9058-4d06-8fff-bd03eb03d98b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23826
09463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.2382609463
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.2044408829
Short name T1988
Test name
Test status
Simulation time 176809796 ps
CPU time 0.86 seconds
Started Jul 26 05:10:14 PM PDT 24
Finished Jul 26 05:10:15 PM PDT 24
Peak memory 207040 kb
Host smart-04997cf4-8c45-4c56-b4f5-3602694093a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20444
08829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.2044408829
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.358401251
Short name T718
Test name
Test status
Simulation time 183879288 ps
CPU time 0.89 seconds
Started Jul 26 05:10:12 PM PDT 24
Finished Jul 26 05:10:13 PM PDT 24
Peak memory 207076 kb
Host smart-70007339-44b4-400f-8520-d9e672ddf2fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35840
1251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.358401251
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.1519954091
Short name T2050
Test name
Test status
Simulation time 146309840 ps
CPU time 0.82 seconds
Started Jul 26 05:10:14 PM PDT 24
Finished Jul 26 05:10:15 PM PDT 24
Peak memory 207016 kb
Host smart-4bba55f7-e98a-4eac-9a5c-aee372201f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15199
54091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.1519954091
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.3262334364
Short name T2531
Test name
Test status
Simulation time 194038308 ps
CPU time 0.89 seconds
Started Jul 26 05:10:21 PM PDT 24
Finished Jul 26 05:10:22 PM PDT 24
Peak memory 207124 kb
Host smart-bb761fa3-d4c2-4310-8536-78c51cdea9d6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3262334364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.3262334364
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.2764874723
Short name T2391
Test name
Test status
Simulation time 150488401 ps
CPU time 0.81 seconds
Started Jul 26 05:10:10 PM PDT 24
Finished Jul 26 05:10:11 PM PDT 24
Peak memory 207072 kb
Host smart-45d1527c-fabb-4810-abde-c5bb5ef22a57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27648
74723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.2764874723
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.3322808058
Short name T24
Test name
Test status
Simulation time 38357302 ps
CPU time 0.71 seconds
Started Jul 26 05:10:14 PM PDT 24
Finished Jul 26 05:10:15 PM PDT 24
Peak memory 207004 kb
Host smart-881a9061-b8dc-4967-aaba-85c56015583f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33228
08058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.3322808058
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.689089894
Short name T259
Test name
Test status
Simulation time 11982204311 ps
CPU time 31.51 seconds
Started Jul 26 05:10:11 PM PDT 24
Finished Jul 26 05:10:42 PM PDT 24
Peak memory 215512 kb
Host smart-d4f15756-bbf3-4197-a2b9-399eaac3207d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68908
9894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.689089894
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.1631510374
Short name T289
Test name
Test status
Simulation time 202419755 ps
CPU time 0.99 seconds
Started Jul 26 05:10:10 PM PDT 24
Finished Jul 26 05:10:11 PM PDT 24
Peak memory 206936 kb
Host smart-c66f48a7-fa55-47fb-ae7b-0db947c8d162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16315
10374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.1631510374
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.377827619
Short name T2267
Test name
Test status
Simulation time 150323400 ps
CPU time 0.87 seconds
Started Jul 26 05:10:11 PM PDT 24
Finished Jul 26 05:10:12 PM PDT 24
Peak memory 207004 kb
Host smart-eb5f4f70-38ad-4622-a9b6-4807416db0f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37782
7619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.377827619
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.3153136037
Short name T786
Test name
Test status
Simulation time 188289725 ps
CPU time 0.89 seconds
Started Jul 26 05:10:14 PM PDT 24
Finished Jul 26 05:10:15 PM PDT 24
Peak memory 207136 kb
Host smart-0c06f1b1-03f6-4141-aa7d-61e8bdf674be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31531
36037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.3153136037
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.1856111693
Short name T2398
Test name
Test status
Simulation time 233462088 ps
CPU time 0.97 seconds
Started Jul 26 05:10:09 PM PDT 24
Finished Jul 26 05:10:10 PM PDT 24
Peak memory 207012 kb
Host smart-f500f933-cb83-40f9-95ea-98a69f9b9f73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18561
11693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.1856111693
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.4015803187
Short name T1679
Test name
Test status
Simulation time 156647197 ps
CPU time 0.83 seconds
Started Jul 26 05:10:13 PM PDT 24
Finished Jul 26 05:10:14 PM PDT 24
Peak memory 207032 kb
Host smart-55b2fbec-6991-4997-90a9-4b12a1e6ac5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40158
03187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.4015803187
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.3127307485
Short name T494
Test name
Test status
Simulation time 149710584 ps
CPU time 0.9 seconds
Started Jul 26 05:10:09 PM PDT 24
Finished Jul 26 05:10:10 PM PDT 24
Peak memory 207080 kb
Host smart-ce7a0f3a-2f0b-4b73-b787-79d0747ae0c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31273
07485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.3127307485
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.3564252875
Short name T2758
Test name
Test status
Simulation time 183289566 ps
CPU time 0.95 seconds
Started Jul 26 05:10:16 PM PDT 24
Finished Jul 26 05:10:17 PM PDT 24
Peak memory 207032 kb
Host smart-97e07e64-216e-4996-ac0c-9e759a57a550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35642
52875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.3564252875
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.2760214701
Short name T505
Test name
Test status
Simulation time 267008568 ps
CPU time 1.1 seconds
Started Jul 26 05:10:15 PM PDT 24
Finished Jul 26 05:10:16 PM PDT 24
Peak memory 207024 kb
Host smart-368f04e9-fa21-4438-bb33-54aa48fc23c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27602
14701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.2760214701
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.189206784
Short name T988
Test name
Test status
Simulation time 5557328286 ps
CPU time 63.41 seconds
Started Jul 26 05:10:10 PM PDT 24
Finished Jul 26 05:11:14 PM PDT 24
Peak memory 216780 kb
Host smart-6e6f26ac-17c7-475b-b3f5-1e4e7e5f45dd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=189206784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.189206784
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.915706126
Short name T2326
Test name
Test status
Simulation time 176758102 ps
CPU time 0.93 seconds
Started Jul 26 05:10:14 PM PDT 24
Finished Jul 26 05:10:15 PM PDT 24
Peak memory 207036 kb
Host smart-a305e0fa-4d6e-4f78-8bef-b169a39fbdcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91570
6126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.915706126
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.3911722763
Short name T1052
Test name
Test status
Simulation time 174776770 ps
CPU time 0.87 seconds
Started Jul 26 05:10:19 PM PDT 24
Finished Jul 26 05:10:20 PM PDT 24
Peak memory 207024 kb
Host smart-cdff6524-59b4-41f2-b3fb-77866248de8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39117
22763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.3911722763
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.4214396597
Short name T2435
Test name
Test status
Simulation time 1195671230 ps
CPU time 2.84 seconds
Started Jul 26 05:10:20 PM PDT 24
Finished Jul 26 05:10:23 PM PDT 24
Peak memory 207236 kb
Host smart-10cd4675-faa4-4e64-ab6e-557a76d54be6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42143
96597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.4214396597
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.1418963101
Short name T1437
Test name
Test status
Simulation time 6614388736 ps
CPU time 199.63 seconds
Started Jul 26 05:10:21 PM PDT 24
Finished Jul 26 05:13:41 PM PDT 24
Peak memory 215516 kb
Host smart-0a069771-b7c1-48c1-94b2-80fa146a3781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14189
63101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.1418963101
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_timeout_missing_host_handshake.626626402
Short name T720
Test name
Test status
Simulation time 4306069969 ps
CPU time 29.19 seconds
Started Jul 26 05:10:14 PM PDT 24
Finished Jul 26 05:10:43 PM PDT 24
Peak memory 207292 kb
Host smart-05d0a4ef-a865-439a-9d00-6e505c9ba8c5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626626402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_timeout_missing_host
_handshake.626626402
Directory /workspace/17.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.3476618251
Short name T581
Test name
Test status
Simulation time 38547235 ps
CPU time 0.72 seconds
Started Jul 26 05:10:34 PM PDT 24
Finished Jul 26 05:10:35 PM PDT 24
Peak memory 207084 kb
Host smart-6dc092ab-74f8-47ae-8902-27b7d5e396bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3476618251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.3476618251
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.2406448626
Short name T1939
Test name
Test status
Simulation time 3493189819 ps
CPU time 5.79 seconds
Started Jul 26 05:10:24 PM PDT 24
Finished Jul 26 05:10:31 PM PDT 24
Peak memory 207372 kb
Host smart-332e00c2-bbb9-49cb-bbe8-fd655b54b438
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406448626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_a
on_wake_disconnect.2406448626
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.4125749868
Short name T925
Test name
Test status
Simulation time 13370045777 ps
CPU time 15.16 seconds
Started Jul 26 05:10:24 PM PDT 24
Finished Jul 26 05:10:39 PM PDT 24
Peak memory 207352 kb
Host smart-e3a34dc7-7bfe-4de8-b77b-98ee8cf72ff9
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125749868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.4125749868
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.4141352601
Short name T395
Test name
Test status
Simulation time 23390176196 ps
CPU time 29.66 seconds
Started Jul 26 05:10:18 PM PDT 24
Finished Jul 26 05:10:47 PM PDT 24
Peak memory 207228 kb
Host smart-229c56f3-3398-46b2-a18a-960b95f3aef4
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141352601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_a
on_wake_resume.4141352601
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.3543715447
Short name T1227
Test name
Test status
Simulation time 168217391 ps
CPU time 0.88 seconds
Started Jul 26 05:10:24 PM PDT 24
Finished Jul 26 05:10:25 PM PDT 24
Peak memory 207120 kb
Host smart-fc4126cf-4427-4870-bde9-3ca7f87d70f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35437
15447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.3543715447
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.3193105400
Short name T1248
Test name
Test status
Simulation time 144497985 ps
CPU time 0.79 seconds
Started Jul 26 05:10:18 PM PDT 24
Finished Jul 26 05:10:19 PM PDT 24
Peak memory 206960 kb
Host smart-7ae7844f-a09a-4694-93c3-1c0e50bfff0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31931
05400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.3193105400
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.2076845614
Short name T92
Test name
Test status
Simulation time 210782034 ps
CPU time 0.95 seconds
Started Jul 26 05:10:20 PM PDT 24
Finished Jul 26 05:10:21 PM PDT 24
Peak memory 207124 kb
Host smart-80f9352b-b325-4e66-9317-909183edd003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20768
45614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.2076845614
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.1079602076
Short name T1196
Test name
Test status
Simulation time 507643844 ps
CPU time 1.51 seconds
Started Jul 26 05:10:19 PM PDT 24
Finished Jul 26 05:10:21 PM PDT 24
Peak memory 207136 kb
Host smart-13d1356a-6b99-4531-bf84-03c4fe4ba33f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1079602076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.1079602076
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.1282507200
Short name T2101
Test name
Test status
Simulation time 21664362706 ps
CPU time 47.71 seconds
Started Jul 26 05:10:18 PM PDT 24
Finished Jul 26 05:11:06 PM PDT 24
Peak memory 207336 kb
Host smart-8974a1c5-3ad4-4ee1-b8a0-123847977c68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12825
07200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.1282507200
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_device_timeout.4172218645
Short name T2377
Test name
Test status
Simulation time 1342263499 ps
CPU time 9.34 seconds
Started Jul 26 05:10:20 PM PDT 24
Finished Jul 26 05:10:30 PM PDT 24
Peak memory 207304 kb
Host smart-aeedda0a-b081-4806-ae56-0c44c306f9b2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172218645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_timeout.4172218645
Directory /workspace/18.usbdev_device_timeout/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.3559731222
Short name T1547
Test name
Test status
Simulation time 431876770 ps
CPU time 1.55 seconds
Started Jul 26 05:10:20 PM PDT 24
Finished Jul 26 05:10:21 PM PDT 24
Peak memory 207080 kb
Host smart-4313c3f8-20a0-45b0-8601-55c690b311c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35597
31222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.3559731222
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.3458634027
Short name T1512
Test name
Test status
Simulation time 137271511 ps
CPU time 0.85 seconds
Started Jul 26 05:10:20 PM PDT 24
Finished Jul 26 05:10:21 PM PDT 24
Peak memory 207024 kb
Host smart-67635705-d30e-4546-8564-054434917c50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34586
34027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.3458634027
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.3464797397
Short name T1352
Test name
Test status
Simulation time 33689618 ps
CPU time 0.71 seconds
Started Jul 26 05:10:22 PM PDT 24
Finished Jul 26 05:10:23 PM PDT 24
Peak memory 207032 kb
Host smart-6992cd55-77c6-4ca3-a460-7f98bee6117b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34647
97397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.3464797397
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.211625878
Short name T1781
Test name
Test status
Simulation time 965138748 ps
CPU time 2.27 seconds
Started Jul 26 05:10:58 PM PDT 24
Finished Jul 26 05:11:01 PM PDT 24
Peak memory 207376 kb
Host smart-002a8c80-c1c2-4e56-992a-d1b2617075db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21162
5878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.211625878
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.628276184
Short name T1862
Test name
Test status
Simulation time 161382295 ps
CPU time 1.45 seconds
Started Jul 26 05:10:19 PM PDT 24
Finished Jul 26 05:10:20 PM PDT 24
Peak memory 207312 kb
Host smart-67700954-1efa-4ba3-9034-b1fc23f77cf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62827
6184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.628276184
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.376636823
Short name T1234
Test name
Test status
Simulation time 205178830 ps
CPU time 1.11 seconds
Started Jul 26 05:10:26 PM PDT 24
Finished Jul 26 05:10:27 PM PDT 24
Peak memory 215524 kb
Host smart-1f707ee5-08e9-4588-aa18-bea3384fe3be
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=376636823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.376636823
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.1046761106
Short name T369
Test name
Test status
Simulation time 148168601 ps
CPU time 0.88 seconds
Started Jul 26 05:10:23 PM PDT 24
Finished Jul 26 05:10:24 PM PDT 24
Peak memory 207072 kb
Host smart-8d8a5857-6327-45a0-bb37-0a8e1b8f451e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10467
61106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.1046761106
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.386793831
Short name T2745
Test name
Test status
Simulation time 222740577 ps
CPU time 1.02 seconds
Started Jul 26 05:10:24 PM PDT 24
Finished Jul 26 05:10:25 PM PDT 24
Peak memory 207104 kb
Host smart-4c49e6b5-0204-418d-819b-9b08bc92d489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38679
3831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.386793831
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.3254420338
Short name T1186
Test name
Test status
Simulation time 7774464518 ps
CPU time 225.07 seconds
Started Jul 26 05:10:21 PM PDT 24
Finished Jul 26 05:14:06 PM PDT 24
Peak memory 215548 kb
Host smart-871b6462-554f-4380-adca-6b288c0e7217
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3254420338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.3254420338
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_iso_retraction.1814761977
Short name T1445
Test name
Test status
Simulation time 11952713038 ps
CPU time 148.83 seconds
Started Jul 26 05:10:20 PM PDT 24
Finished Jul 26 05:12:49 PM PDT 24
Peak memory 207236 kb
Host smart-bd0961db-e167-4b61-9420-2e64f75bd512
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1814761977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_iso_retraction.1814761977
Directory /workspace/18.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.2688881024
Short name T2172
Test name
Test status
Simulation time 194159710 ps
CPU time 0.97 seconds
Started Jul 26 05:10:27 PM PDT 24
Finished Jul 26 05:10:28 PM PDT 24
Peak memory 207104 kb
Host smart-fc77e22d-ee1d-4ef1-8aed-37d1450c6a38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26888
81024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.2688881024
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.3359753058
Short name T2446
Test name
Test status
Simulation time 23300740579 ps
CPU time 29.2 seconds
Started Jul 26 05:10:20 PM PDT 24
Finished Jul 26 05:10:49 PM PDT 24
Peak memory 207292 kb
Host smart-d4c525d6-52e3-4ae7-9fb6-28102286989f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33597
53058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.3359753058
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.4108972364
Short name T1048
Test name
Test status
Simulation time 3310875104 ps
CPU time 5.95 seconds
Started Jul 26 05:10:29 PM PDT 24
Finished Jul 26 05:10:35 PM PDT 24
Peak memory 207348 kb
Host smart-bd3102cf-606a-4ad9-8474-3a7e119fc26d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41089
72364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.4108972364
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.3058515901
Short name T2256
Test name
Test status
Simulation time 9918751136 ps
CPU time 101.55 seconds
Started Jul 26 05:10:19 PM PDT 24
Finished Jul 26 05:12:00 PM PDT 24
Peak memory 217128 kb
Host smart-c4252276-633b-45bc-be08-6b08dc5935fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30585
15901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.3058515901
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.1454417649
Short name T493
Test name
Test status
Simulation time 4587655494 ps
CPU time 35.47 seconds
Started Jul 26 05:10:29 PM PDT 24
Finished Jul 26 05:11:04 PM PDT 24
Peak memory 215580 kb
Host smart-9e27d290-5c1c-4174-a593-0523ea0b204f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1454417649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.1454417649
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.1061305686
Short name T840
Test name
Test status
Simulation time 234982094 ps
CPU time 0.93 seconds
Started Jul 26 05:10:23 PM PDT 24
Finished Jul 26 05:10:25 PM PDT 24
Peak memory 207108 kb
Host smart-6dba9020-8292-45f1-abfe-10a2f172af65
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1061305686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.1061305686
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.939363322
Short name T1417
Test name
Test status
Simulation time 197232511 ps
CPU time 0.95 seconds
Started Jul 26 05:10:24 PM PDT 24
Finished Jul 26 05:10:25 PM PDT 24
Peak memory 207156 kb
Host smart-d156334d-9450-42d9-80d4-4513c322c0ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93936
3322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.939363322
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.2217676610
Short name T1305
Test name
Test status
Simulation time 4714606891 ps
CPU time 37.58 seconds
Started Jul 26 05:10:20 PM PDT 24
Finished Jul 26 05:10:58 PM PDT 24
Peak memory 215480 kb
Host smart-1bb1d778-c9c3-44f0-9e75-60b941e9f2d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22176
76610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.2217676610
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.3765276560
Short name T912
Test name
Test status
Simulation time 4342846442 ps
CPU time 142.25 seconds
Started Jul 26 05:10:19 PM PDT 24
Finished Jul 26 05:12:42 PM PDT 24
Peak memory 215468 kb
Host smart-1cab45ff-5fbe-4378-aec7-1a72a7fe0b8c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3765276560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.3765276560
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.3260839292
Short name T1877
Test name
Test status
Simulation time 164361585 ps
CPU time 0.88 seconds
Started Jul 26 05:10:18 PM PDT 24
Finished Jul 26 05:10:19 PM PDT 24
Peak memory 207056 kb
Host smart-470dc6b7-a2d9-4ad0-a659-a1382b841d7c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3260839292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.3260839292
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.2850211320
Short name T1162
Test name
Test status
Simulation time 141289522 ps
CPU time 0.82 seconds
Started Jul 26 05:10:20 PM PDT 24
Finished Jul 26 05:10:21 PM PDT 24
Peak memory 207024 kb
Host smart-61cccf6b-aca0-4deb-ad82-bffdfb2d9e63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28502
11320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.2850211320
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.3120924955
Short name T1995
Test name
Test status
Simulation time 230896650 ps
CPU time 1.01 seconds
Started Jul 26 05:10:24 PM PDT 24
Finished Jul 26 05:10:25 PM PDT 24
Peak memory 207136 kb
Host smart-35fc5903-3956-435a-9f7f-d2faec447d0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31209
24955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.3120924955
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.923548384
Short name T108
Test name
Test status
Simulation time 173939270 ps
CPU time 0.9 seconds
Started Jul 26 05:10:19 PM PDT 24
Finished Jul 26 05:10:20 PM PDT 24
Peak memory 207132 kb
Host smart-4639a75f-920f-477c-9a3d-0e861c1d3167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92354
8384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.923548384
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.543395080
Short name T1569
Test name
Test status
Simulation time 207911606 ps
CPU time 0.93 seconds
Started Jul 26 05:10:32 PM PDT 24
Finished Jul 26 05:10:34 PM PDT 24
Peak memory 206984 kb
Host smart-57b07a51-4b53-4e51-ad88-49675d38b6d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54339
5080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.543395080
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.891129562
Short name T461
Test name
Test status
Simulation time 195448614 ps
CPU time 0.87 seconds
Started Jul 26 05:10:31 PM PDT 24
Finished Jul 26 05:10:32 PM PDT 24
Peak memory 207132 kb
Host smart-c60bc0da-3f6c-4a4b-98dc-905d4413d35a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89112
9562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.891129562
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.3427465671
Short name T2681
Test name
Test status
Simulation time 217839570 ps
CPU time 0.96 seconds
Started Jul 26 05:10:30 PM PDT 24
Finished Jul 26 05:10:31 PM PDT 24
Peak memory 207072 kb
Host smart-8e57096b-7ac8-47d6-93a0-836caa4a2d16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34274
65671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.3427465671
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.920660477
Short name T2644
Test name
Test status
Simulation time 185567780 ps
CPU time 0.97 seconds
Started Jul 26 05:10:30 PM PDT 24
Finished Jul 26 05:10:32 PM PDT 24
Peak memory 207152 kb
Host smart-f1689dd6-c75e-4940-9f55-a3ddadbf26f5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=920660477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.920660477
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.2563278190
Short name T736
Test name
Test status
Simulation time 144036713 ps
CPU time 0.86 seconds
Started Jul 26 05:10:32 PM PDT 24
Finished Jul 26 05:10:33 PM PDT 24
Peak memory 206976 kb
Host smart-2124db6c-fb3f-42e7-bd9e-e78ce53a2420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25632
78190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.2563278190
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.2879061594
Short name T2394
Test name
Test status
Simulation time 109962756 ps
CPU time 0.82 seconds
Started Jul 26 05:10:32 PM PDT 24
Finished Jul 26 05:10:33 PM PDT 24
Peak memory 207048 kb
Host smart-c7fb020a-eea6-42f9-a7a7-e0e1d01a7eb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28790
61594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.2879061594
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.1365489863
Short name T2205
Test name
Test status
Simulation time 14574504197 ps
CPU time 38.52 seconds
Started Jul 26 05:10:29 PM PDT 24
Finished Jul 26 05:11:08 PM PDT 24
Peak memory 219348 kb
Host smart-6e8df105-f1ff-4aa5-8b32-a9be6e0a9e5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13654
89863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.1365489863
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.1356412250
Short name T2333
Test name
Test status
Simulation time 164794286 ps
CPU time 0.93 seconds
Started Jul 26 05:10:30 PM PDT 24
Finished Jul 26 05:10:31 PM PDT 24
Peak memory 207152 kb
Host smart-4d66550c-eeb7-4197-94c8-a201e7f8a64b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13564
12250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.1356412250
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.638620137
Short name T2730
Test name
Test status
Simulation time 234701061 ps
CPU time 0.98 seconds
Started Jul 26 05:10:31 PM PDT 24
Finished Jul 26 05:10:32 PM PDT 24
Peak memory 207128 kb
Host smart-e68b5a06-60d8-4ccf-82d6-5ef4b2fb19bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63862
0137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.638620137
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.3557116107
Short name T2823
Test name
Test status
Simulation time 169760684 ps
CPU time 0.84 seconds
Started Jul 26 05:10:28 PM PDT 24
Finished Jul 26 05:10:29 PM PDT 24
Peak memory 207052 kb
Host smart-539ca850-a00e-4105-9120-f52b88c605b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35571
16107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.3557116107
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.1959253871
Short name T1863
Test name
Test status
Simulation time 183976568 ps
CPU time 0.92 seconds
Started Jul 26 05:10:30 PM PDT 24
Finished Jul 26 05:10:31 PM PDT 24
Peak memory 207020 kb
Host smart-e381eea1-0228-4af3-9ed7-ddde73abac75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19592
53871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.1959253871
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.2870132228
Short name T632
Test name
Test status
Simulation time 154224046 ps
CPU time 0.88 seconds
Started Jul 26 05:10:31 PM PDT 24
Finished Jul 26 05:10:32 PM PDT 24
Peak memory 207092 kb
Host smart-0fd40df4-ed5c-4dcb-baa2-c46e8bdd4555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28701
32228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.2870132228
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.2241291363
Short name T2586
Test name
Test status
Simulation time 148697502 ps
CPU time 0.92 seconds
Started Jul 26 05:10:32 PM PDT 24
Finished Jul 26 05:10:33 PM PDT 24
Peak memory 207052 kb
Host smart-d63bc4ab-6a3a-41e8-a79f-2ee9e3a6e043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22412
91363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.2241291363
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.811336224
Short name T520
Test name
Test status
Simulation time 155885073 ps
CPU time 0.88 seconds
Started Jul 26 05:10:32 PM PDT 24
Finished Jul 26 05:10:33 PM PDT 24
Peak memory 207048 kb
Host smart-8f4c50b2-5715-44e0-b198-56ed25f0c666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81133
6224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.811336224
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.2793171005
Short name T2593
Test name
Test status
Simulation time 226541006 ps
CPU time 1.09 seconds
Started Jul 26 05:10:29 PM PDT 24
Finished Jul 26 05:10:30 PM PDT 24
Peak memory 207128 kb
Host smart-d8232e64-331b-4e5e-9938-8c68aa86d558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27931
71005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.2793171005
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.3712868647
Short name T1213
Test name
Test status
Simulation time 4318130328 ps
CPU time 33.42 seconds
Started Jul 26 05:10:34 PM PDT 24
Finished Jul 26 05:11:07 PM PDT 24
Peak memory 216812 kb
Host smart-17c066b8-ae43-4ac9-91b9-55fe2e304e89
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3712868647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.3712868647
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.3491006606
Short name T457
Test name
Test status
Simulation time 162146046 ps
CPU time 0.91 seconds
Started Jul 26 05:10:29 PM PDT 24
Finished Jul 26 05:10:30 PM PDT 24
Peak memory 207016 kb
Host smart-e3843d72-cad3-4142-b6d0-6c1ba7da086d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34910
06606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.3491006606
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.2761165425
Short name T850
Test name
Test status
Simulation time 203667162 ps
CPU time 0.97 seconds
Started Jul 26 05:10:30 PM PDT 24
Finished Jul 26 05:10:31 PM PDT 24
Peak memory 207096 kb
Host smart-6b800f69-9157-4f89-af55-a4f476c783ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27611
65425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.2761165425
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.1921902942
Short name T989
Test name
Test status
Simulation time 901349864 ps
CPU time 2.31 seconds
Started Jul 26 05:10:29 PM PDT 24
Finished Jul 26 05:10:32 PM PDT 24
Peak memory 207212 kb
Host smart-8d67ea18-f9fe-4f6b-b4c6-b7812d37c21a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19219
02942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.1921902942
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.323722354
Short name T2441
Test name
Test status
Simulation time 3311782326 ps
CPU time 37.9 seconds
Started Jul 26 05:10:29 PM PDT 24
Finished Jul 26 05:11:07 PM PDT 24
Peak memory 216700 kb
Host smart-26d9cd29-a6ae-4cb2-b3b2-73f60bf5d5a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32372
2354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.323722354
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_timeout_missing_host_handshake.3684555090
Short name T2833
Test name
Test status
Simulation time 863596170 ps
CPU time 18.89 seconds
Started Jul 26 05:10:18 PM PDT 24
Finished Jul 26 05:10:37 PM PDT 24
Peak memory 207364 kb
Host smart-82abde1a-4269-4cad-ba7a-cac6aa5257f3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684555090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_timeout_missing_hos
t_handshake.3684555090
Directory /workspace/18.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.2646100702
Short name T1661
Test name
Test status
Simulation time 40023965 ps
CPU time 0.66 seconds
Started Jul 26 05:10:43 PM PDT 24
Finished Jul 26 05:10:44 PM PDT 24
Peak memory 207004 kb
Host smart-f6d3e90e-630a-4796-a851-ad89df934f8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2646100702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.2646100702
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.1136641153
Short name T47
Test name
Test status
Simulation time 3428802895 ps
CPU time 5.37 seconds
Started Jul 26 05:10:30 PM PDT 24
Finished Jul 26 05:10:36 PM PDT 24
Peak memory 207328 kb
Host smart-63e366e2-e71b-4102-871d-5e09c8190890
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136641153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_a
on_wake_disconnect.1136641153
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.1186747090
Short name T1178
Test name
Test status
Simulation time 13389341062 ps
CPU time 16.16 seconds
Started Jul 26 05:10:34 PM PDT 24
Finished Jul 26 05:10:50 PM PDT 24
Peak memory 207308 kb
Host smart-92af2238-e30b-4f34-ab3a-38322662b31b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186747090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.1186747090
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.1916694352
Short name T1796
Test name
Test status
Simulation time 23424227456 ps
CPU time 30.46 seconds
Started Jul 26 05:10:31 PM PDT 24
Finished Jul 26 05:11:02 PM PDT 24
Peak memory 207372 kb
Host smart-cb8537af-b01c-4d7c-a545-c2402a8a3ef4
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916694352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_a
on_wake_resume.1916694352
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.1100317268
Short name T1559
Test name
Test status
Simulation time 184992286 ps
CPU time 0.96 seconds
Started Jul 26 05:10:29 PM PDT 24
Finished Jul 26 05:10:30 PM PDT 24
Peak memory 207048 kb
Host smart-bcd0ed35-c569-407d-8365-a84c905e7300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11003
17268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.1100317268
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.584145338
Short name T1126
Test name
Test status
Simulation time 176994105 ps
CPU time 0.91 seconds
Started Jul 26 05:10:30 PM PDT 24
Finished Jul 26 05:10:31 PM PDT 24
Peak memory 206948 kb
Host smart-fd271cf8-d742-4b9f-9818-ec8ae0250d17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58414
5338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.584145338
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.2788292377
Short name T1032
Test name
Test status
Simulation time 231968062 ps
CPU time 1.09 seconds
Started Jul 26 05:10:31 PM PDT 24
Finished Jul 26 05:10:33 PM PDT 24
Peak memory 207140 kb
Host smart-bc171155-7a34-4c25-b6e1-ab660e080d99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27882
92377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.2788292377
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.627021381
Short name T1703
Test name
Test status
Simulation time 1433246795 ps
CPU time 3.47 seconds
Started Jul 26 05:10:30 PM PDT 24
Finished Jul 26 05:10:34 PM PDT 24
Peak memory 207324 kb
Host smart-5c4d339b-2487-4ed9-9c0f-290394bfcb06
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=627021381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.627021381
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.2483869015
Short name T1770
Test name
Test status
Simulation time 9286240721 ps
CPU time 19.28 seconds
Started Jul 26 05:10:31 PM PDT 24
Finished Jul 26 05:10:51 PM PDT 24
Peak memory 207324 kb
Host smart-49f5f6e5-4718-4424-96e7-384fabde3552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24838
69015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.2483869015
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_device_timeout.4198072840
Short name T2485
Test name
Test status
Simulation time 955626433 ps
CPU time 21.49 seconds
Started Jul 26 05:10:29 PM PDT 24
Finished Jul 26 05:10:51 PM PDT 24
Peak memory 207156 kb
Host smart-75f8fa49-4428-417c-90ad-9a55d27fa6d6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198072840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_timeout.4198072840
Directory /workspace/19.usbdev_device_timeout/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.2237153237
Short name T2274
Test name
Test status
Simulation time 502225501 ps
CPU time 1.66 seconds
Started Jul 26 05:10:29 PM PDT 24
Finished Jul 26 05:10:30 PM PDT 24
Peak memory 207012 kb
Host smart-555d6e09-c97c-46d5-938b-2c490f9a4f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22371
53237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.2237153237
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.1205485873
Short name T1743
Test name
Test status
Simulation time 152025668 ps
CPU time 0.85 seconds
Started Jul 26 05:10:30 PM PDT 24
Finished Jul 26 05:10:31 PM PDT 24
Peak memory 207096 kb
Host smart-cc48dcd7-ba43-4b8a-8259-342126ab18bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12054
85873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.1205485873
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.1987633986
Short name T1779
Test name
Test status
Simulation time 56633424 ps
CPU time 0.74 seconds
Started Jul 26 05:10:30 PM PDT 24
Finished Jul 26 05:10:31 PM PDT 24
Peak memory 207096 kb
Host smart-a9b310c4-85b6-4192-9997-029b3928c6eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19876
33986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.1987633986
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.3977823578
Short name T2210
Test name
Test status
Simulation time 932987035 ps
CPU time 2.66 seconds
Started Jul 26 05:10:29 PM PDT 24
Finished Jul 26 05:10:32 PM PDT 24
Peak memory 207172 kb
Host smart-d50139e5-6635-4843-9b52-46f57e781b77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39778
23578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.3977823578
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.565238948
Short name T2190
Test name
Test status
Simulation time 290286711 ps
CPU time 2.46 seconds
Started Jul 26 05:10:32 PM PDT 24
Finished Jul 26 05:10:35 PM PDT 24
Peak memory 207296 kb
Host smart-ff89e630-d031-4a37-b1e9-cf1d17be3acc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56523
8948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.565238948
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.1713734168
Short name T2647
Test name
Test status
Simulation time 208718795 ps
CPU time 1.17 seconds
Started Jul 26 05:10:29 PM PDT 24
Finished Jul 26 05:10:31 PM PDT 24
Peak memory 207304 kb
Host smart-d07b16a8-4698-4504-a500-e0e66424c829
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1713734168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.1713734168
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.2328607435
Short name T758
Test name
Test status
Simulation time 153896858 ps
CPU time 0.87 seconds
Started Jul 26 05:10:31 PM PDT 24
Finished Jul 26 05:10:32 PM PDT 24
Peak memory 207008 kb
Host smart-25b53d8e-e5ef-435a-9acd-add2ef16bceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23286
07435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.2328607435
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.2621561656
Short name T2038
Test name
Test status
Simulation time 249247178 ps
CPU time 1.06 seconds
Started Jul 26 05:10:30 PM PDT 24
Finished Jul 26 05:10:32 PM PDT 24
Peak memory 207128 kb
Host smart-30aa1faf-d75b-47a2-872c-2e06398bc141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26215
61656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.2621561656
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.1565009285
Short name T2465
Test name
Test status
Simulation time 5763499628 ps
CPU time 169.56 seconds
Started Jul 26 05:10:30 PM PDT 24
Finished Jul 26 05:13:20 PM PDT 24
Peak memory 215616 kb
Host smart-3668bb65-d6dd-4688-abad-a3cacbabeffc
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1565009285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.1565009285
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/19.usbdev_iso_retraction.2458113965
Short name T537
Test name
Test status
Simulation time 8731093111 ps
CPU time 55.87 seconds
Started Jul 26 05:10:27 PM PDT 24
Finished Jul 26 05:11:24 PM PDT 24
Peak memory 207320 kb
Host smart-37f625e3-63a8-4d61-aacb-6866d020e738
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2458113965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.2458113965
Directory /workspace/19.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.3199797603
Short name T762
Test name
Test status
Simulation time 231092160 ps
CPU time 1 seconds
Started Jul 26 05:10:44 PM PDT 24
Finished Jul 26 05:10:45 PM PDT 24
Peak memory 207128 kb
Host smart-9c28dcce-9c39-4fa8-a1c7-0e5a2a993722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31997
97603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.3199797603
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.2290252727
Short name T347
Test name
Test status
Simulation time 23360436687 ps
CPU time 30.13 seconds
Started Jul 26 05:10:48 PM PDT 24
Finished Jul 26 05:11:18 PM PDT 24
Peak memory 207332 kb
Host smart-5cf4099b-ade8-4d9f-9f36-657d16dc0c66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22902
52727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.2290252727
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.2824150426
Short name T1630
Test name
Test status
Simulation time 3304947979 ps
CPU time 5.14 seconds
Started Jul 26 05:10:44 PM PDT 24
Finished Jul 26 05:10:50 PM PDT 24
Peak memory 207344 kb
Host smart-5e9954af-fbbd-4ec6-aaa3-68e19063a91f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28241
50426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.2824150426
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.1838192921
Short name T1101
Test name
Test status
Simulation time 7064600010 ps
CPU time 85.93 seconds
Started Jul 26 05:10:44 PM PDT 24
Finished Jul 26 05:12:10 PM PDT 24
Peak memory 215472 kb
Host smart-f94055e4-b0b9-433c-8498-c95b96216768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18381
92921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.1838192921
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.3330663340
Short name T955
Test name
Test status
Simulation time 5142901996 ps
CPU time 40.77 seconds
Started Jul 26 05:10:43 PM PDT 24
Finished Jul 26 05:11:24 PM PDT 24
Peak memory 207340 kb
Host smart-496abc5c-878b-4474-8e48-3233a45c65c5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3330663340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.3330663340
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.2060091317
Short name T1298
Test name
Test status
Simulation time 230809184 ps
CPU time 1.04 seconds
Started Jul 26 05:10:44 PM PDT 24
Finished Jul 26 05:10:45 PM PDT 24
Peak memory 207108 kb
Host smart-f6a52f46-0564-4311-b743-dd382a5d0887
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2060091317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.2060091317
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.219790063
Short name T94
Test name
Test status
Simulation time 258871821 ps
CPU time 0.99 seconds
Started Jul 26 05:10:42 PM PDT 24
Finished Jul 26 05:10:44 PM PDT 24
Peak memory 206996 kb
Host smart-7efe3571-00dc-4a65-94e3-3bb865943966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21979
0063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.219790063
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.4257205266
Short name T2040
Test name
Test status
Simulation time 6101902280 ps
CPU time 49.5 seconds
Started Jul 26 05:10:43 PM PDT 24
Finished Jul 26 05:11:33 PM PDT 24
Peak memory 216544 kb
Host smart-e8852ac0-a443-4688-850f-14cee41c7331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42572
05266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.4257205266
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.550984382
Short name T2846
Test name
Test status
Simulation time 5407564812 ps
CPU time 44.57 seconds
Started Jul 26 05:10:42 PM PDT 24
Finished Jul 26 05:11:26 PM PDT 24
Peak memory 207392 kb
Host smart-1164ab14-7d89-465e-9f95-db340a39feee
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=550984382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.550984382
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.2057252060
Short name T1087
Test name
Test status
Simulation time 153146862 ps
CPU time 0.91 seconds
Started Jul 26 05:10:50 PM PDT 24
Finished Jul 26 05:10:51 PM PDT 24
Peak memory 207108 kb
Host smart-2f7d4aa4-4224-4870-b459-ee7cd6d400fc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2057252060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.2057252060
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.846181911
Short name T715
Test name
Test status
Simulation time 149694150 ps
CPU time 0.85 seconds
Started Jul 26 05:10:45 PM PDT 24
Finished Jul 26 05:10:46 PM PDT 24
Peak memory 207096 kb
Host smart-0fa3aef0-1f33-49f7-a82c-81a34831cf5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84618
1911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.846181911
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.197396638
Short name T2262
Test name
Test status
Simulation time 229102029 ps
CPU time 0.97 seconds
Started Jul 26 05:10:44 PM PDT 24
Finished Jul 26 05:10:45 PM PDT 24
Peak memory 206940 kb
Host smart-4bbb5a8e-db67-4b79-be1f-a55b61632f08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19739
6638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.197396638
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.2131064654
Short name T1864
Test name
Test status
Simulation time 224311870 ps
CPU time 0.97 seconds
Started Jul 26 05:10:47 PM PDT 24
Finished Jul 26 05:10:48 PM PDT 24
Peak memory 207080 kb
Host smart-bb91d471-6605-4cbb-b929-fb6de7dd95c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21310
64654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.2131064654
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.3092900145
Short name T959
Test name
Test status
Simulation time 185192357 ps
CPU time 0.89 seconds
Started Jul 26 05:10:48 PM PDT 24
Finished Jul 26 05:10:49 PM PDT 24
Peak memory 207036 kb
Host smart-278897ef-0c15-4eff-8032-88f3885904a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30929
00145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.3092900145
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.299728574
Short name T1116
Test name
Test status
Simulation time 176798349 ps
CPU time 0.9 seconds
Started Jul 26 05:10:47 PM PDT 24
Finished Jul 26 05:10:48 PM PDT 24
Peak memory 207084 kb
Host smart-2d1ff7ad-4a15-47bb-9ac4-9c84e283b75a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29972
8574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.299728574
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.382394376
Short name T1913
Test name
Test status
Simulation time 158443591 ps
CPU time 0.83 seconds
Started Jul 26 05:10:43 PM PDT 24
Finished Jul 26 05:10:44 PM PDT 24
Peak memory 207028 kb
Host smart-82caa17f-bbe5-4478-a6bf-660b84991392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38239
4376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.382394376
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.4123449426
Short name T1201
Test name
Test status
Simulation time 240675096 ps
CPU time 1.1 seconds
Started Jul 26 05:10:43 PM PDT 24
Finished Jul 26 05:10:44 PM PDT 24
Peak memory 207132 kb
Host smart-eab0835f-a117-4106-adf1-705eaf9df37b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4123449426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.4123449426
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.3697021364
Short name T2338
Test name
Test status
Simulation time 198938680 ps
CPU time 0.9 seconds
Started Jul 26 05:10:45 PM PDT 24
Finished Jul 26 05:10:46 PM PDT 24
Peak memory 207112 kb
Host smart-0606a2d5-a1dd-40fb-b320-c8222c514efb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36970
21364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.3697021364
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.197971482
Short name T1984
Test name
Test status
Simulation time 39420672 ps
CPU time 0.69 seconds
Started Jul 26 05:10:46 PM PDT 24
Finished Jul 26 05:10:47 PM PDT 24
Peak memory 206976 kb
Host smart-2211b4e8-f914-48e8-98a1-92eee43cc497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19797
1482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.197971482
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.3743507607
Short name T1867
Test name
Test status
Simulation time 11735634061 ps
CPU time 34.42 seconds
Started Jul 26 05:10:46 PM PDT 24
Finished Jul 26 05:11:21 PM PDT 24
Peak memory 215572 kb
Host smart-3071f425-73a1-4281-9a91-8e9af5229f31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37435
07607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.3743507607
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.700328664
Short name T631
Test name
Test status
Simulation time 189610714 ps
CPU time 0.97 seconds
Started Jul 26 05:10:43 PM PDT 24
Finished Jul 26 05:10:44 PM PDT 24
Peak memory 207104 kb
Host smart-7faf9df1-d24c-4c37-b8fb-0e989cd20589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70032
8664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.700328664
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.1504586589
Short name T830
Test name
Test status
Simulation time 227325227 ps
CPU time 1.05 seconds
Started Jul 26 05:10:45 PM PDT 24
Finished Jul 26 05:10:46 PM PDT 24
Peak memory 207052 kb
Host smart-a6cc41a0-704a-4f96-b26f-633311dfd5e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15045
86589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.1504586589
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.2530407897
Short name T19
Test name
Test status
Simulation time 212363529 ps
CPU time 0.98 seconds
Started Jul 26 05:10:42 PM PDT 24
Finished Jul 26 05:10:44 PM PDT 24
Peak memory 207000 kb
Host smart-bf862170-c4c6-4592-835a-e10d7e2efa76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25304
07897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.2530407897
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.2474497547
Short name T312
Test name
Test status
Simulation time 193968377 ps
CPU time 0.89 seconds
Started Jul 26 05:10:43 PM PDT 24
Finished Jul 26 05:10:44 PM PDT 24
Peak memory 207028 kb
Host smart-1f00e1b1-a10c-4249-9692-7cc59106c495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24744
97547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.2474497547
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.285181859
Short name T1858
Test name
Test status
Simulation time 210799246 ps
CPU time 0.87 seconds
Started Jul 26 05:10:45 PM PDT 24
Finished Jul 26 05:10:46 PM PDT 24
Peak memory 207116 kb
Host smart-e9574336-b318-4402-9804-feb8fd5378ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28518
1859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.285181859
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.3321351500
Short name T1231
Test name
Test status
Simulation time 145822276 ps
CPU time 0.8 seconds
Started Jul 26 05:10:45 PM PDT 24
Finished Jul 26 05:10:45 PM PDT 24
Peak memory 207120 kb
Host smart-f73f879a-8db1-4618-afdc-4502b0257636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33213
51500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.3321351500
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.2654211861
Short name T2041
Test name
Test status
Simulation time 148750249 ps
CPU time 0.85 seconds
Started Jul 26 05:10:43 PM PDT 24
Finished Jul 26 05:10:44 PM PDT 24
Peak memory 207028 kb
Host smart-b4f4b4e7-7c25-44a5-b800-dea521c9c515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26542
11861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.2654211861
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.1715334446
Short name T484
Test name
Test status
Simulation time 214600313 ps
CPU time 0.94 seconds
Started Jul 26 05:10:47 PM PDT 24
Finished Jul 26 05:10:48 PM PDT 24
Peak memory 207036 kb
Host smart-7737b7e7-f035-44f5-8a61-c8b456cca911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17153
34446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.1715334446
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.2788491046
Short name T1557
Test name
Test status
Simulation time 3493818447 ps
CPU time 104.15 seconds
Started Jul 26 05:10:46 PM PDT 24
Finished Jul 26 05:12:30 PM PDT 24
Peak memory 215552 kb
Host smart-24ec0704-6fce-4dc2-a47d-5d845238547d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2788491046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.2788491046
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.1701190169
Short name T2604
Test name
Test status
Simulation time 164015529 ps
CPU time 0.93 seconds
Started Jul 26 05:10:47 PM PDT 24
Finished Jul 26 05:10:48 PM PDT 24
Peak memory 207052 kb
Host smart-6548f172-7456-4e5a-b43f-a38655ac1749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17011
90169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.1701190169
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.4141056908
Short name T1917
Test name
Test status
Simulation time 177002099 ps
CPU time 0.98 seconds
Started Jul 26 05:10:45 PM PDT 24
Finished Jul 26 05:10:46 PM PDT 24
Peak memory 207124 kb
Host smart-99489826-3248-4eda-a0e9-eb09e4ef8cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41410
56908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.4141056908
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.471438826
Short name T940
Test name
Test status
Simulation time 687391051 ps
CPU time 1.97 seconds
Started Jul 26 05:10:46 PM PDT 24
Finished Jul 26 05:10:49 PM PDT 24
Peak memory 207088 kb
Host smart-0747dd05-854b-4da0-a01e-13fb405fe1c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47143
8826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.471438826
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.2089783209
Short name T1091
Test name
Test status
Simulation time 4622716933 ps
CPU time 48.64 seconds
Started Jul 26 05:10:47 PM PDT 24
Finished Jul 26 05:11:36 PM PDT 24
Peak memory 207336 kb
Host smart-0de1c958-83c4-47ab-83a4-a6e13714a1bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20897
83209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.2089783209
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_timeout_missing_host_handshake.1597050535
Short name T485
Test name
Test status
Simulation time 2008408606 ps
CPU time 17.85 seconds
Started Jul 26 05:10:28 PM PDT 24
Finished Jul 26 05:10:46 PM PDT 24
Peak memory 207248 kb
Host smart-35577256-f11b-4924-a94c-c3c87adc11fd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597050535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_timeout_missing_hos
t_handshake.1597050535
Directory /workspace/19.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.2870519870
Short name T2709
Test name
Test status
Simulation time 34835120 ps
CPU time 0.65 seconds
Started Jul 26 05:06:48 PM PDT 24
Finished Jul 26 05:06:49 PM PDT 24
Peak memory 207052 kb
Host smart-a42c3221-9854-4d7b-9020-759d56f472ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2870519870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.2870519870
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.4047805617
Short name T2099
Test name
Test status
Simulation time 3769473309 ps
CPU time 6.51 seconds
Started Jul 26 05:06:39 PM PDT 24
Finished Jul 26 05:06:46 PM PDT 24
Peak memory 207340 kb
Host smart-91e271a8-5405-46e4-91c3-a434250841c2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047805617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ao
n_wake_disconnect.4047805617
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.63799479
Short name T2580
Test name
Test status
Simulation time 13360504127 ps
CPU time 16.47 seconds
Started Jul 26 05:06:41 PM PDT 24
Finished Jul 26 05:06:57 PM PDT 24
Peak memory 207280 kb
Host smart-80345a84-62e8-4bc1-b51d-07954b427966
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=63799479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.63799479
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.1097279803
Short name T398
Test name
Test status
Simulation time 23393416456 ps
CPU time 27.06 seconds
Started Jul 26 05:06:52 PM PDT 24
Finished Jul 26 05:07:19 PM PDT 24
Peak memory 207304 kb
Host smart-aef070a8-c0ea-4bd1-8e9e-d178d6828dd7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097279803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ao
n_wake_resume.1097279803
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.1225063982
Short name T1798
Test name
Test status
Simulation time 165745622 ps
CPU time 0.92 seconds
Started Jul 26 05:06:52 PM PDT 24
Finished Jul 26 05:06:53 PM PDT 24
Peak memory 207100 kb
Host smart-a8c49eb2-7ed5-4363-a7ff-f61a1cec90ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12250
63982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.1225063982
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.825721172
Short name T59
Test name
Test status
Simulation time 150327842 ps
CPU time 0.82 seconds
Started Jul 26 05:06:52 PM PDT 24
Finished Jul 26 05:06:53 PM PDT 24
Peak memory 207100 kb
Host smart-eb3c2553-5ad8-46ac-9750-1098a593d402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82572
1172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.825721172
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.2250455081
Short name T65
Test name
Test status
Simulation time 175342107 ps
CPU time 0.94 seconds
Started Jul 26 05:06:44 PM PDT 24
Finished Jul 26 05:06:45 PM PDT 24
Peak memory 207056 kb
Host smart-9e12b5e4-22ba-422a-85ab-7a9fee4bdea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22504
55081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.2250455081
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.53137838
Short name T2240
Test name
Test status
Simulation time 175045000 ps
CPU time 0.87 seconds
Started Jul 26 05:06:40 PM PDT 24
Finished Jul 26 05:06:41 PM PDT 24
Peak memory 206988 kb
Host smart-0e0e2b66-ee04-436e-8713-ea721112ab6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53137
838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.53137838
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.1915734910
Short name T2469
Test name
Test status
Simulation time 253755844 ps
CPU time 1.05 seconds
Started Jul 26 05:06:41 PM PDT 24
Finished Jul 26 05:06:42 PM PDT 24
Peak memory 207124 kb
Host smart-a8890a64-38e6-42d0-8311-f93b90e99e8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19157
34910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.1915734910
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.1979222739
Short name T507
Test name
Test status
Simulation time 1291400470 ps
CPU time 3.28 seconds
Started Jul 26 05:06:52 PM PDT 24
Finished Jul 26 05:06:56 PM PDT 24
Peak memory 207324 kb
Host smart-b78ba374-76d0-40d2-ac2d-6fa81b184db2
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1979222739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.1979222739
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.2483190435
Short name T1063
Test name
Test status
Simulation time 12239005744 ps
CPU time 25.84 seconds
Started Jul 26 05:06:48 PM PDT 24
Finished Jul 26 05:07:14 PM PDT 24
Peak memory 207400 kb
Host smart-7501b0de-8d01-46f9-a3b7-55163dd748db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24831
90435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.2483190435
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_device_timeout.499471362
Short name T1809
Test name
Test status
Simulation time 413937851 ps
CPU time 7.6 seconds
Started Jul 26 05:06:47 PM PDT 24
Finished Jul 26 05:06:55 PM PDT 24
Peak memory 207276 kb
Host smart-a4386635-53c2-43c5-9d60-7268c4568319
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499471362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_timeout.499471362
Directory /workspace/2.usbdev_device_timeout/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.4284583049
Short name T2696
Test name
Test status
Simulation time 399144377 ps
CPU time 1.48 seconds
Started Jul 26 05:06:43 PM PDT 24
Finished Jul 26 05:06:44 PM PDT 24
Peak memory 207076 kb
Host smart-457d3592-5faa-4b62-b40a-4400fe90824e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42845
83049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.4284583049
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.2013202859
Short name T767
Test name
Test status
Simulation time 165045200 ps
CPU time 0.88 seconds
Started Jul 26 05:06:52 PM PDT 24
Finished Jul 26 05:06:53 PM PDT 24
Peak memory 207020 kb
Host smart-aaa9ada7-baae-4210-9fad-7d096433dc72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20132
02859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.2013202859
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.3656762625
Short name T1029
Test name
Test status
Simulation time 49641898 ps
CPU time 0.72 seconds
Started Jul 26 05:06:40 PM PDT 24
Finished Jul 26 05:06:41 PM PDT 24
Peak memory 207064 kb
Host smart-adafc9e2-4027-46aa-b128-5ad4dfa8f950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36567
62625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.3656762625
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.2414793437
Short name T1869
Test name
Test status
Simulation time 1038067274 ps
CPU time 2.65 seconds
Started Jul 26 05:06:42 PM PDT 24
Finished Jul 26 05:06:45 PM PDT 24
Peak memory 207336 kb
Host smart-5db69a5b-76fe-47aa-9cbf-1cd55d89c902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24147
93437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.2414793437
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.3333220808
Short name T2229
Test name
Test status
Simulation time 185694529 ps
CPU time 1.57 seconds
Started Jul 26 05:06:43 PM PDT 24
Finished Jul 26 05:06:45 PM PDT 24
Peak memory 207256 kb
Host smart-a8a03800-6ad4-4123-892b-c5bd9cb96b33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33332
20808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.3333220808
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.4166826087
Short name T2389
Test name
Test status
Simulation time 100213064491 ps
CPU time 165.52 seconds
Started Jul 26 05:06:42 PM PDT 24
Finished Jul 26 05:09:28 PM PDT 24
Peak memory 207348 kb
Host smart-8357f367-ec05-428c-b31c-7cfd7711b097
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4166826087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.4166826087
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.1994094855
Short name T28
Test name
Test status
Simulation time 116107541791 ps
CPU time 185.32 seconds
Started Jul 26 05:06:41 PM PDT 24
Finished Jul 26 05:09:46 PM PDT 24
Peak memory 207312 kb
Host smart-791157fd-f466-47c6-9629-241e7a507e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994094855 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.1994094855
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.749625268
Short name T2521
Test name
Test status
Simulation time 90116928550 ps
CPU time 164.5 seconds
Started Jul 26 05:06:47 PM PDT 24
Finished Jul 26 05:09:32 PM PDT 24
Peak memory 207388 kb
Host smart-3cf497e5-3c48-4735-9ca0-0ded13e057a5
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=749625268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.749625268
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.2549161826
Short name T1957
Test name
Test status
Simulation time 117920459690 ps
CPU time 171.27 seconds
Started Jul 26 05:06:39 PM PDT 24
Finished Jul 26 05:09:31 PM PDT 24
Peak memory 207236 kb
Host smart-eecd9f29-81b5-4a40-80af-f3e716cb88b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549161826 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.2549161826
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.75420212
Short name T1767
Test name
Test status
Simulation time 99193878144 ps
CPU time 150.7 seconds
Started Jul 26 05:06:43 PM PDT 24
Finished Jul 26 05:09:14 PM PDT 24
Peak memory 207236 kb
Host smart-68826d67-8208-4e14-985c-b37950103288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75420
212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.75420212
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.2871212279
Short name T1688
Test name
Test status
Simulation time 195365737 ps
CPU time 1.04 seconds
Started Jul 26 05:06:43 PM PDT 24
Finished Jul 26 05:06:44 PM PDT 24
Peak memory 215536 kb
Host smart-7c26aaf5-749a-4968-b6f7-bfdb4962fd10
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2871212279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.2871212279
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.3196876291
Short name T1953
Test name
Test status
Simulation time 221837670 ps
CPU time 0.92 seconds
Started Jul 26 05:06:43 PM PDT 24
Finished Jul 26 05:06:45 PM PDT 24
Peak memory 207288 kb
Host smart-6f462575-82dc-46d4-8323-404f667c7cf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31968
76291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.3196876291
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.3677328601
Short name T1950
Test name
Test status
Simulation time 234592931 ps
CPU time 1.04 seconds
Started Jul 26 05:06:42 PM PDT 24
Finished Jul 26 05:06:43 PM PDT 24
Peak memory 207128 kb
Host smart-551f8451-f681-4fe4-af27-0e6c35eeb9b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36773
28601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.3677328601
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.1629964598
Short name T1522
Test name
Test status
Simulation time 8342529869 ps
CPU time 68.46 seconds
Started Jul 26 05:06:43 PM PDT 24
Finished Jul 26 05:07:52 PM PDT 24
Peak memory 216600 kb
Host smart-cd805f1f-ead2-4d79-9607-2ee3d8304c83
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1629964598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.1629964598
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_iso_retraction.3772015569
Short name T1619
Test name
Test status
Simulation time 9477712605 ps
CPU time 63.22 seconds
Started Jul 26 05:06:47 PM PDT 24
Finished Jul 26 05:07:50 PM PDT 24
Peak memory 207344 kb
Host smart-5ae1da3b-b72a-401d-9eea-7f81e55db0fb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3772015569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_iso_retraction.3772015569
Directory /workspace/2.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.3050988930
Short name T1343
Test name
Test status
Simulation time 177365388 ps
CPU time 0.89 seconds
Started Jul 26 05:06:47 PM PDT 24
Finished Jul 26 05:06:48 PM PDT 24
Peak memory 207096 kb
Host smart-a91ab9b3-78ca-45a0-b0ce-bf36e4f0396e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30509
88930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.3050988930
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.3266584864
Short name T1218
Test name
Test status
Simulation time 23292056131 ps
CPU time 28.44 seconds
Started Jul 26 05:06:44 PM PDT 24
Finished Jul 26 05:07:13 PM PDT 24
Peak memory 207368 kb
Host smart-975ca19e-2bad-482f-a4ff-de1118c9ddde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32665
84864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.3266584864
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.2437525224
Short name T1881
Test name
Test status
Simulation time 3278952444 ps
CPU time 4.84 seconds
Started Jul 26 05:06:43 PM PDT 24
Finished Jul 26 05:06:48 PM PDT 24
Peak memory 207332 kb
Host smart-17e18b80-fd0c-451b-9699-8f7d6b00cec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24375
25224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.2437525224
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.1514026395
Short name T1940
Test name
Test status
Simulation time 6024690946 ps
CPU time 48.92 seconds
Started Jul 26 05:06:43 PM PDT 24
Finished Jul 26 05:07:32 PM PDT 24
Peak memory 217504 kb
Host smart-954a5912-54de-43b5-b4a2-d9911134bcb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15140
26395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.1514026395
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.2644240024
Short name T2383
Test name
Test status
Simulation time 4015477049 ps
CPU time 46.96 seconds
Started Jul 26 05:06:44 PM PDT 24
Finished Jul 26 05:07:31 PM PDT 24
Peak memory 216912 kb
Host smart-cb6e0d9d-04d8-493f-9071-25788d96fe7d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2644240024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.2644240024
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.2094432551
Short name T2451
Test name
Test status
Simulation time 256320488 ps
CPU time 1.07 seconds
Started Jul 26 05:06:42 PM PDT 24
Finished Jul 26 05:06:43 PM PDT 24
Peak memory 207092 kb
Host smart-597851f4-8149-437a-9012-6d353fda7d3d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2094432551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.2094432551
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.3375300270
Short name T1698
Test name
Test status
Simulation time 189121074 ps
CPU time 1.03 seconds
Started Jul 26 05:06:43 PM PDT 24
Finished Jul 26 05:06:44 PM PDT 24
Peak memory 207332 kb
Host smart-4013fe8b-9c4d-4d4e-89f7-5c9bb1c94e61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33753
00270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.3375300270
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.2781244753
Short name T1717
Test name
Test status
Simulation time 5424866792 ps
CPU time 44.4 seconds
Started Jul 26 05:06:48 PM PDT 24
Finished Jul 26 05:07:32 PM PDT 24
Peak memory 217216 kb
Host smart-57b8e044-98fe-4a36-84d5-c4790fa3d377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27812
44753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.2781244753
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.3125115835
Short name T2748
Test name
Test status
Simulation time 3387262812 ps
CPU time 28.15 seconds
Started Jul 26 05:06:53 PM PDT 24
Finished Jul 26 05:07:21 PM PDT 24
Peak memory 215328 kb
Host smart-7833ce94-2d20-4c23-a6fa-8353794df288
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3125115835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.3125115835
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.1313378288
Short name T1968
Test name
Test status
Simulation time 177256480 ps
CPU time 0.87 seconds
Started Jul 26 05:06:44 PM PDT 24
Finished Jul 26 05:06:45 PM PDT 24
Peak memory 207084 kb
Host smart-bdcd8d61-f81a-4a64-80bb-7d07100761a4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1313378288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.1313378288
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.2980899110
Short name T2472
Test name
Test status
Simulation time 149047840 ps
CPU time 0.83 seconds
Started Jul 26 05:06:42 PM PDT 24
Finished Jul 26 05:06:43 PM PDT 24
Peak memory 207088 kb
Host smart-2c0c68aa-ce25-475f-8286-431d868cf5e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29808
99110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.2980899110
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.204122355
Short name T116
Test name
Test status
Simulation time 220269535 ps
CPU time 1.01 seconds
Started Jul 26 05:06:40 PM PDT 24
Finished Jul 26 05:06:42 PM PDT 24
Peak memory 207104 kb
Host smart-ab339e98-7c92-4abc-b075-f195ebb327eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20412
2355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.204122355
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.1148586219
Short name T2666
Test name
Test status
Simulation time 196064863 ps
CPU time 1.01 seconds
Started Jul 26 05:06:41 PM PDT 24
Finished Jul 26 05:06:42 PM PDT 24
Peak memory 206972 kb
Host smart-bb67dffe-582a-4743-86c1-ef57dd479fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11485
86219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.1148586219
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.3252308025
Short name T1624
Test name
Test status
Simulation time 162820642 ps
CPU time 0.85 seconds
Started Jul 26 05:06:52 PM PDT 24
Finished Jul 26 05:06:53 PM PDT 24
Peak memory 207072 kb
Host smart-ca24db5e-50cd-4259-a089-6294901c2505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32523
08025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.3252308025
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.1841355087
Short name T2420
Test name
Test status
Simulation time 192569669 ps
CPU time 0.9 seconds
Started Jul 26 05:06:43 PM PDT 24
Finished Jul 26 05:06:44 PM PDT 24
Peak memory 207068 kb
Host smart-5e60f939-096f-4ecf-a8e3-2d331e852303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18413
55087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.1841355087
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.539544139
Short name T1823
Test name
Test status
Simulation time 182555284 ps
CPU time 0.86 seconds
Started Jul 26 05:06:48 PM PDT 24
Finished Jul 26 05:06:49 PM PDT 24
Peak memory 207072 kb
Host smart-b23cb9ff-67b8-48f2-bd4c-1a05c2de0cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53954
4139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.539544139
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.1388436402
Short name T2218
Test name
Test status
Simulation time 201038438 ps
CPU time 0.97 seconds
Started Jul 26 05:06:53 PM PDT 24
Finished Jul 26 05:06:54 PM PDT 24
Peak memory 207124 kb
Host smart-e7c08ef0-603f-4564-a3f7-6e3bcc91d9f5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1388436402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.1388436402
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.1348971790
Short name T2794
Test name
Test status
Simulation time 266574712 ps
CPU time 1.09 seconds
Started Jul 26 05:06:40 PM PDT 24
Finished Jul 26 05:06:42 PM PDT 24
Peak memory 207152 kb
Host smart-785c6fc8-1f7f-4eb5-857f-56c95073f170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13489
71790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.1348971790
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.1907435255
Short name T1603
Test name
Test status
Simulation time 46121261 ps
CPU time 0.7 seconds
Started Jul 26 05:06:44 PM PDT 24
Finished Jul 26 05:06:45 PM PDT 24
Peak memory 207048 kb
Host smart-1863e55d-a260-42cb-9a52-6257292ebba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19074
35255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.1907435255
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.2047734747
Short name T1106
Test name
Test status
Simulation time 9467689265 ps
CPU time 23.82 seconds
Started Jul 26 05:06:43 PM PDT 24
Finished Jul 26 05:07:07 PM PDT 24
Peak memory 220356 kb
Host smart-4bd3f28f-758e-4231-bf67-b64821800021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20477
34747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.2047734747
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.3596491282
Short name T1347
Test name
Test status
Simulation time 172990800 ps
CPU time 0.92 seconds
Started Jul 26 05:06:40 PM PDT 24
Finished Jul 26 05:06:41 PM PDT 24
Peak memory 207000 kb
Host smart-f7e0765b-df59-402e-ae61-d16ee253469a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35964
91282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.3596491282
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.2425086380
Short name T1948
Test name
Test status
Simulation time 195914940 ps
CPU time 0.9 seconds
Started Jul 26 05:06:52 PM PDT 24
Finished Jul 26 05:06:53 PM PDT 24
Peak memory 207056 kb
Host smart-a2081b28-5ed9-4df1-a33f-a428b3932208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24250
86380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.2425086380
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.1385209390
Short name T406
Test name
Test status
Simulation time 9057754057 ps
CPU time 86.74 seconds
Started Jul 26 05:06:53 PM PDT 24
Finished Jul 26 05:08:20 PM PDT 24
Peak memory 217024 kb
Host smart-7bc741ff-a2cf-40c4-a40d-49cfb90f8080
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385209390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.1385209390
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.437828409
Short name T1553
Test name
Test status
Simulation time 13282513710 ps
CPU time 267.81 seconds
Started Jul 26 05:06:45 PM PDT 24
Finished Jul 26 05:11:13 PM PDT 24
Peak memory 215548 kb
Host smart-60df3989-c0e9-4c85-9897-8cbf1db57ffc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=437828409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.437828409
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.3223311470
Short name T1978
Test name
Test status
Simulation time 8193848841 ps
CPU time 45.69 seconds
Started Jul 26 05:06:45 PM PDT 24
Finished Jul 26 05:07:31 PM PDT 24
Peak memory 219004 kb
Host smart-e3071e2e-12fc-461d-814f-0f4af531ed12
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223311470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.3223311470
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.2219274066
Short name T1252
Test name
Test status
Simulation time 247151625 ps
CPU time 0.95 seconds
Started Jul 26 05:06:53 PM PDT 24
Finished Jul 26 05:06:54 PM PDT 24
Peak memory 207100 kb
Host smart-1d568925-7143-4986-af82-c93d02ba263b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22192
74066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.2219274066
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.730414094
Short name T2795
Test name
Test status
Simulation time 179210044 ps
CPU time 0.9 seconds
Started Jul 26 05:06:43 PM PDT 24
Finished Jul 26 05:06:44 PM PDT 24
Peak memory 207112 kb
Host smart-41f4c1c4-ef3d-40b2-9419-871f1a458593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73041
4094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.730414094
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.49464531
Short name T1420
Test name
Test status
Simulation time 171908597 ps
CPU time 0.89 seconds
Started Jul 26 05:06:47 PM PDT 24
Finished Jul 26 05:06:49 PM PDT 24
Peak memory 207120 kb
Host smart-04217be4-19be-498a-845a-453a4ed50a34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49464
531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.49464531
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.2424911239
Short name T2769
Test name
Test status
Simulation time 163577882 ps
CPU time 0.9 seconds
Started Jul 26 05:06:53 PM PDT 24
Finished Jul 26 05:06:54 PM PDT 24
Peak memory 207120 kb
Host smart-f902f392-5ccc-4eb3-a97f-e883a17e551f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24249
11239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.2424911239
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.1081606778
Short name T186
Test name
Test status
Simulation time 915981507 ps
CPU time 1.71 seconds
Started Jul 26 05:06:50 PM PDT 24
Finished Jul 26 05:06:52 PM PDT 24
Peak memory 223920 kb
Host smart-60c68881-a617-4304-9f19-618483ebec7e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1081606778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.1081606778
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.2540076881
Short name T54
Test name
Test status
Simulation time 464160702 ps
CPU time 1.4 seconds
Started Jul 26 05:06:51 PM PDT 24
Finished Jul 26 05:06:53 PM PDT 24
Peak memory 207100 kb
Host smart-32405251-0fe1-43e8-9668-cbb0ee6eae76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25400
76881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.2540076881
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.3076226756
Short name T1744
Test name
Test status
Simulation time 276629206 ps
CPU time 1.02 seconds
Started Jul 26 05:06:52 PM PDT 24
Finished Jul 26 05:06:53 PM PDT 24
Peak memory 207124 kb
Host smart-b1978845-4dc6-4ce5-8c21-4ccdb136aa3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30762
26756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.3076226756
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.2454318534
Short name T1097
Test name
Test status
Simulation time 146074245 ps
CPU time 0.89 seconds
Started Jul 26 05:06:48 PM PDT 24
Finished Jul 26 05:06:49 PM PDT 24
Peak memory 207040 kb
Host smart-1f06bfba-e851-4cc3-abba-1d78da1ea54b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24543
18534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.2454318534
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.787632825
Short name T496
Test name
Test status
Simulation time 169390032 ps
CPU time 0.87 seconds
Started Jul 26 05:07:10 PM PDT 24
Finished Jul 26 05:07:10 PM PDT 24
Peak memory 207132 kb
Host smart-aff6e07e-8f3f-4947-9fbf-78c44b73c810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78763
2825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.787632825
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.1067048372
Short name T387
Test name
Test status
Simulation time 249057978 ps
CPU time 1.07 seconds
Started Jul 26 05:06:51 PM PDT 24
Finished Jul 26 05:06:53 PM PDT 24
Peak memory 207124 kb
Host smart-6393593b-4782-46a1-9340-bfbbde9ebbf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10670
48372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.1067048372
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.1456861417
Short name T2453
Test name
Test status
Simulation time 5616324415 ps
CPU time 164.58 seconds
Started Jul 26 05:06:49 PM PDT 24
Finished Jul 26 05:09:34 PM PDT 24
Peak memory 215544 kb
Host smart-9d3a8aa5-1364-4140-8bef-dc5da9c3d3e4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1456861417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.1456861417
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.4280652644
Short name T145
Test name
Test status
Simulation time 153955839 ps
CPU time 0.84 seconds
Started Jul 26 05:06:51 PM PDT 24
Finished Jul 26 05:06:52 PM PDT 24
Peak memory 207208 kb
Host smart-05888b64-d68a-40ad-a483-e175c0ba1596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42806
52644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.4280652644
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.1777143476
Short name T2806
Test name
Test status
Simulation time 159700626 ps
CPU time 0.83 seconds
Started Jul 26 05:06:48 PM PDT 24
Finished Jul 26 05:06:49 PM PDT 24
Peak memory 207020 kb
Host smart-a7ecfb4b-d0cc-4a6a-a002-422a86fe0662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17771
43476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.1777143476
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.4086012040
Short name T33
Test name
Test status
Simulation time 719712664 ps
CPU time 1.95 seconds
Started Jul 26 05:06:55 PM PDT 24
Finished Jul 26 05:06:57 PM PDT 24
Peak memory 206800 kb
Host smart-c7d2b349-d2f9-4c1d-9085-4375a1e79aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40860
12040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.4086012040
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.1030082216
Short name T855
Test name
Test status
Simulation time 4943111760 ps
CPU time 138.09 seconds
Started Jul 26 05:06:55 PM PDT 24
Finished Jul 26 05:09:13 PM PDT 24
Peak memory 215264 kb
Host smart-fb8ca454-c818-4282-b6df-503ae799075e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10300
82216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.1030082216
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.3913758810
Short name T80
Test name
Test status
Simulation time 15407741174 ps
CPU time 445.77 seconds
Started Jul 26 05:06:50 PM PDT 24
Finished Jul 26 05:14:16 PM PDT 24
Peak memory 215564 kb
Host smart-dd6dc0d4-34a2-44fe-98b3-de745fcc2de1
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913758810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.3913758810
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_timeout_missing_host_handshake.2468369996
Short name T2454
Test name
Test status
Simulation time 2037859588 ps
CPU time 18.22 seconds
Started Jul 26 05:06:42 PM PDT 24
Finished Jul 26 05:07:01 PM PDT 24
Peak memory 207204 kb
Host smart-5a75d089-b8f3-444c-abae-c02cac37920a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468369996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_timeout_missing_host
_handshake.2468369996
Directory /workspace/2.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.3210372791
Short name T2487
Test name
Test status
Simulation time 44389418 ps
CPU time 0.71 seconds
Started Jul 26 05:11:00 PM PDT 24
Finished Jul 26 05:11:00 PM PDT 24
Peak memory 207048 kb
Host smart-80c36453-2636-4dd9-a613-13f2b1462f1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3210372791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.3210372791
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.2496752555
Short name T2856
Test name
Test status
Simulation time 3421519632 ps
CPU time 5.15 seconds
Started Jul 26 05:10:44 PM PDT 24
Finished Jul 26 05:10:50 PM PDT 24
Peak memory 207376 kb
Host smart-d1af23ca-320e-440a-9706-573226d7f032
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496752555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_a
on_wake_disconnect.2496752555
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.3086356754
Short name T1905
Test name
Test status
Simulation time 13420668281 ps
CPU time 16.6 seconds
Started Jul 26 05:10:44 PM PDT 24
Finished Jul 26 05:11:00 PM PDT 24
Peak memory 207304 kb
Host smart-7374da43-2813-4689-a712-db9be506c506
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086356754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.3086356754
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.1379608054
Short name T2702
Test name
Test status
Simulation time 23353467998 ps
CPU time 31.54 seconds
Started Jul 26 05:10:46 PM PDT 24
Finished Jul 26 05:11:17 PM PDT 24
Peak memory 207324 kb
Host smart-e790647f-b365-4d97-9b16-9c289ab17b2d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379608054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_a
on_wake_resume.1379608054
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.3105298344
Short name T1055
Test name
Test status
Simulation time 149933920 ps
CPU time 0.86 seconds
Started Jul 26 05:10:46 PM PDT 24
Finished Jul 26 05:10:48 PM PDT 24
Peak memory 207028 kb
Host smart-5753d82f-e53d-4e53-97a8-f18bf4510c2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31052
98344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.3105298344
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.286521534
Short name T1752
Test name
Test status
Simulation time 144278532 ps
CPU time 0.82 seconds
Started Jul 26 05:10:46 PM PDT 24
Finished Jul 26 05:10:47 PM PDT 24
Peak memory 207044 kb
Host smart-646f0bcd-6628-4aae-bf47-a5cb59b24303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28652
1534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.286521534
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.2676414013
Short name T1242
Test name
Test status
Simulation time 402630129 ps
CPU time 1.55 seconds
Started Jul 26 05:10:46 PM PDT 24
Finished Jul 26 05:10:48 PM PDT 24
Peak memory 207128 kb
Host smart-f3cabb34-9191-4fd0-880e-bd81a81ce1b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26764
14013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.2676414013
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.1376373641
Short name T2316
Test name
Test status
Simulation time 1061166727 ps
CPU time 2.66 seconds
Started Jul 26 05:10:46 PM PDT 24
Finished Jul 26 05:10:49 PM PDT 24
Peak memory 207368 kb
Host smart-48bf5c1e-d3dd-462c-8a65-04e751af7124
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1376373641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.1376373641
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.271510147
Short name T2532
Test name
Test status
Simulation time 14313598092 ps
CPU time 31.66 seconds
Started Jul 26 05:10:45 PM PDT 24
Finished Jul 26 05:11:16 PM PDT 24
Peak memory 207404 kb
Host smart-a6b7ddf8-e864-454d-b3b2-0095eaec5e4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27151
0147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.271510147
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_device_timeout.1081348045
Short name T209
Test name
Test status
Simulation time 283430736 ps
CPU time 4.59 seconds
Started Jul 26 05:10:42 PM PDT 24
Finished Jul 26 05:10:47 PM PDT 24
Peak memory 207344 kb
Host smart-046dbdc4-bbcb-4965-96b7-ab7528d26879
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081348045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_timeout.1081348045
Directory /workspace/20.usbdev_device_timeout/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.320784688
Short name T1768
Test name
Test status
Simulation time 369001324 ps
CPU time 1.26 seconds
Started Jul 26 05:10:46 PM PDT 24
Finished Jul 26 05:10:48 PM PDT 24
Peak memory 207044 kb
Host smart-4fc8c134-82ed-48d6-86c7-3f5a6e5f9b80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32078
4688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.320784688
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_enable.2754076904
Short name T1068
Test name
Test status
Simulation time 46565687 ps
CPU time 0.74 seconds
Started Jul 26 05:10:48 PM PDT 24
Finished Jul 26 05:10:49 PM PDT 24
Peak memory 207048 kb
Host smart-05743f28-0608-4232-87a9-bb9cf08f2449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27540
76904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.2754076904
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.1902162305
Short name T2016
Test name
Test status
Simulation time 851586542 ps
CPU time 2.26 seconds
Started Jul 26 05:10:46 PM PDT 24
Finished Jul 26 05:10:48 PM PDT 24
Peak memory 207296 kb
Host smart-05c215c2-0002-4427-964f-76df1d38a690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19021
62305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.1902162305
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.1645456408
Short name T900
Test name
Test status
Simulation time 192945328 ps
CPU time 1.3 seconds
Started Jul 26 05:10:46 PM PDT 24
Finished Jul 26 05:10:47 PM PDT 24
Peak memory 207176 kb
Host smart-6f45b312-39c9-4bf4-bc40-c9856a370992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16454
56408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.1645456408
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.852135801
Short name T1009
Test name
Test status
Simulation time 232765950 ps
CPU time 1.27 seconds
Started Jul 26 05:10:50 PM PDT 24
Finished Jul 26 05:10:51 PM PDT 24
Peak memory 215508 kb
Host smart-56e89248-2b47-4fe1-bd41-7dcbfbf25cc9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=852135801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.852135801
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.2515413769
Short name T1388
Test name
Test status
Simulation time 139734294 ps
CPU time 0.83 seconds
Started Jul 26 05:10:58 PM PDT 24
Finished Jul 26 05:10:59 PM PDT 24
Peak memory 207044 kb
Host smart-c957f4bb-d4e5-4469-9578-f07860da68d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25154
13769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.2515413769
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.103728933
Short name T473
Test name
Test status
Simulation time 270611289 ps
CPU time 1.01 seconds
Started Jul 26 05:10:54 PM PDT 24
Finished Jul 26 05:10:55 PM PDT 24
Peak memory 207120 kb
Host smart-049a44d4-f294-41f2-aae1-5def287de3f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10372
8933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.103728933
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_invalid_sync.2460244150
Short name T1537
Test name
Test status
Simulation time 5294234101 ps
CPU time 165.94 seconds
Started Jul 26 05:10:48 PM PDT 24
Finished Jul 26 05:13:34 PM PDT 24
Peak memory 215496 kb
Host smart-4fcf8907-82e3-44ab-b7f8-77ebdd7bdb38
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2460244150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.2460244150
Directory /workspace/20.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/20.usbdev_iso_retraction.2958641164
Short name T1090
Test name
Test status
Simulation time 13527163015 ps
CPU time 148.11 seconds
Started Jul 26 05:11:01 PM PDT 24
Finished Jul 26 05:13:29 PM PDT 24
Peak memory 207280 kb
Host smart-e10c65d5-04cf-4bec-8093-47885b46ad15
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2958641164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.2958641164
Directory /workspace/20.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.3703498320
Short name T1319
Test name
Test status
Simulation time 220073720 ps
CPU time 0.94 seconds
Started Jul 26 05:10:57 PM PDT 24
Finished Jul 26 05:10:58 PM PDT 24
Peak memory 207128 kb
Host smart-a7ff4bf3-14b1-45e9-be8c-39cabcc6f670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37034
98320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.3703498320
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.3449514901
Short name T2660
Test name
Test status
Simulation time 3343628003 ps
CPU time 5.88 seconds
Started Jul 26 05:11:01 PM PDT 24
Finished Jul 26 05:11:07 PM PDT 24
Peak memory 207284 kb
Host smart-11bdc7ce-11ce-4e58-a36c-7b3fd65df392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34495
14901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.3449514901
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.4262151949
Short name T719
Test name
Test status
Simulation time 5718238367 ps
CPU time 43.2 seconds
Started Jul 26 05:10:55 PM PDT 24
Finished Jul 26 05:11:38 PM PDT 24
Peak memory 217436 kb
Host smart-2c675ccc-89ad-4721-b409-be5cdc72fc61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42621
51949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.4262151949
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.4197734156
Short name T875
Test name
Test status
Simulation time 5110789541 ps
CPU time 43.07 seconds
Started Jul 26 05:10:54 PM PDT 24
Finished Jul 26 05:11:37 PM PDT 24
Peak memory 216976 kb
Host smart-7f993035-7d9e-4ec6-984b-3cc289f942a1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4197734156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.4197734156
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.1651771758
Short name T2486
Test name
Test status
Simulation time 244717713 ps
CPU time 1.02 seconds
Started Jul 26 05:11:00 PM PDT 24
Finished Jul 26 05:11:01 PM PDT 24
Peak memory 207072 kb
Host smart-f5c1ec8e-6273-4036-8225-75afc95e718d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1651771758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.1651771758
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.3528076318
Short name T2609
Test name
Test status
Simulation time 191509703 ps
CPU time 0.96 seconds
Started Jul 26 05:10:56 PM PDT 24
Finished Jul 26 05:10:57 PM PDT 24
Peak memory 207040 kb
Host smart-e2abef6b-96f7-4e99-9e5a-e47be88f1d01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35280
76318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.3528076318
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.192028672
Short name T2106
Test name
Test status
Simulation time 3359313423 ps
CPU time 27.43 seconds
Started Jul 26 05:10:55 PM PDT 24
Finished Jul 26 05:11:23 PM PDT 24
Peak memory 215588 kb
Host smart-576be520-aa02-4ddc-8427-4190eaacbd81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19202
8672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.192028672
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.1876447202
Short name T608
Test name
Test status
Simulation time 5606666422 ps
CPU time 156.2 seconds
Started Jul 26 05:10:57 PM PDT 24
Finished Jul 26 05:13:34 PM PDT 24
Peak memory 215612 kb
Host smart-fe03fc12-8a0d-4952-8015-335143e80187
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1876447202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.1876447202
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.732032067
Short name T1280
Test name
Test status
Simulation time 169969319 ps
CPU time 0.88 seconds
Started Jul 26 05:10:54 PM PDT 24
Finished Jul 26 05:10:55 PM PDT 24
Peak memory 207124 kb
Host smart-0781f20c-45ff-4001-91e3-e3197cba8a96
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=732032067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.732032067
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.3412751442
Short name T432
Test name
Test status
Simulation time 150410978 ps
CPU time 0.82 seconds
Started Jul 26 05:10:57 PM PDT 24
Finished Jul 26 05:10:58 PM PDT 24
Peak memory 207072 kb
Host smart-b8f9c6c1-0bfe-424c-8db1-5367c4223fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34127
51442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.3412751442
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.1224016443
Short name T1290
Test name
Test status
Simulation time 203725453 ps
CPU time 0.92 seconds
Started Jul 26 05:10:55 PM PDT 24
Finished Jul 26 05:10:56 PM PDT 24
Peak memory 207060 kb
Host smart-57502ebb-c04b-4424-8172-ebced3686319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12240
16443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.1224016443
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.644998723
Short name T1674
Test name
Test status
Simulation time 178865746 ps
CPU time 0.95 seconds
Started Jul 26 05:10:57 PM PDT 24
Finished Jul 26 05:10:58 PM PDT 24
Peak memory 207104 kb
Host smart-11ea67b3-770a-46f9-af8d-2115ed520811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64499
8723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.644998723
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.2447571153
Short name T385
Test name
Test status
Simulation time 157370349 ps
CPU time 0.87 seconds
Started Jul 26 05:10:57 PM PDT 24
Finished Jul 26 05:10:58 PM PDT 24
Peak memory 207092 kb
Host smart-13370ece-823c-4ec8-a058-0d2076e1c4af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24475
71153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.2447571153
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.3151122899
Short name T1992
Test name
Test status
Simulation time 181306478 ps
CPU time 0.9 seconds
Started Jul 26 05:10:56 PM PDT 24
Finished Jul 26 05:10:57 PM PDT 24
Peak memory 207012 kb
Host smart-566842f6-2504-442a-a338-ba20c46e5377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31511
22899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.3151122899
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.3809659032
Short name T1511
Test name
Test status
Simulation time 265246590 ps
CPU time 1.21 seconds
Started Jul 26 05:10:55 PM PDT 24
Finished Jul 26 05:10:57 PM PDT 24
Peak memory 207124 kb
Host smart-15b5f526-3bb0-4264-91f0-e1f98cce8d17
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3809659032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.3809659032
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.1635961759
Short name T184
Test name
Test status
Simulation time 186538927 ps
CPU time 0.89 seconds
Started Jul 26 05:11:00 PM PDT 24
Finished Jul 26 05:11:01 PM PDT 24
Peak memory 206992 kb
Host smart-d8a2b585-8586-4c6c-aaa3-614701dc76c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16359
61759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.1635961759
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.2923388713
Short name T1040
Test name
Test status
Simulation time 30293805 ps
CPU time 0.65 seconds
Started Jul 26 05:10:55 PM PDT 24
Finished Jul 26 05:10:55 PM PDT 24
Peak memory 207012 kb
Host smart-77b36797-d2ca-4fe8-b4e9-34f57f1f25cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29233
88713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.2923388713
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.4232028664
Short name T260
Test name
Test status
Simulation time 22682180639 ps
CPU time 58.2 seconds
Started Jul 26 05:10:56 PM PDT 24
Finished Jul 26 05:11:55 PM PDT 24
Peak memory 215516 kb
Host smart-f6ae1483-c5ce-4eb2-a36c-7ad1cf91775d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42320
28664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.4232028664
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.2386423650
Short name T2204
Test name
Test status
Simulation time 169024148 ps
CPU time 0.91 seconds
Started Jul 26 05:10:56 PM PDT 24
Finished Jul 26 05:10:57 PM PDT 24
Peak memory 207024 kb
Host smart-b367d551-da96-4d95-bbe2-838dfc92a40d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23864
23650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.2386423650
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.1661788753
Short name T522
Test name
Test status
Simulation time 240656736 ps
CPU time 1.04 seconds
Started Jul 26 05:10:59 PM PDT 24
Finished Jul 26 05:11:00 PM PDT 24
Peak memory 207004 kb
Host smart-dd3e36c7-3eb2-41de-899d-26f898f1f8c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16617
88753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.1661788753
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.4251546628
Short name T2802
Test name
Test status
Simulation time 179903297 ps
CPU time 0.91 seconds
Started Jul 26 05:10:59 PM PDT 24
Finished Jul 26 05:11:00 PM PDT 24
Peak memory 207080 kb
Host smart-7106c388-18ec-40b8-b93e-2ed6140b25df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42515
46628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.4251546628
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.227988400
Short name T1653
Test name
Test status
Simulation time 158328789 ps
CPU time 0.88 seconds
Started Jul 26 05:10:57 PM PDT 24
Finished Jul 26 05:10:58 PM PDT 24
Peak memory 207124 kb
Host smart-ac80fae3-f139-4ac2-9e6e-384112db974b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22798
8400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.227988400
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.3415722046
Short name T1944
Test name
Test status
Simulation time 145767279 ps
CPU time 0.81 seconds
Started Jul 26 05:10:56 PM PDT 24
Finished Jul 26 05:10:57 PM PDT 24
Peak memory 207096 kb
Host smart-a1cb2f01-d785-4342-a0c5-8926fffe4e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34157
22046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.3415722046
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.1711401277
Short name T898
Test name
Test status
Simulation time 172190853 ps
CPU time 0.93 seconds
Started Jul 26 05:11:00 PM PDT 24
Finished Jul 26 05:11:01 PM PDT 24
Peak memory 206996 kb
Host smart-313988ff-7357-4b45-8657-5500a16dcbe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17114
01277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.1711401277
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.992709431
Short name T803
Test name
Test status
Simulation time 172265022 ps
CPU time 0.84 seconds
Started Jul 26 05:10:59 PM PDT 24
Finished Jul 26 05:11:00 PM PDT 24
Peak memory 207136 kb
Host smart-27da3503-9e17-4f78-bd44-5be63463ce7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99270
9431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.992709431
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.839956201
Short name T2468
Test name
Test status
Simulation time 239257371 ps
CPU time 1.07 seconds
Started Jul 26 05:10:58 PM PDT 24
Finished Jul 26 05:10:59 PM PDT 24
Peak memory 207132 kb
Host smart-b5ad1ad5-4b2d-4fd0-81ba-5e8c6da0e65b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83995
6201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.839956201
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.2529158922
Short name T1191
Test name
Test status
Simulation time 4206456964 ps
CPU time 42.88 seconds
Started Jul 26 05:11:00 PM PDT 24
Finished Jul 26 05:11:43 PM PDT 24
Peak memory 215472 kb
Host smart-2783781d-90ab-464f-af9e-f5ecee1dd829
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2529158922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.2529158922
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.338965392
Short name T1489
Test name
Test status
Simulation time 192391572 ps
CPU time 0.95 seconds
Started Jul 26 05:11:01 PM PDT 24
Finished Jul 26 05:11:02 PM PDT 24
Peak memory 207068 kb
Host smart-e2036671-d4be-4c2a-82b6-e5604effc9b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33896
5392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.338965392
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.1807465337
Short name T2139
Test name
Test status
Simulation time 169207093 ps
CPU time 0.83 seconds
Started Jul 26 05:10:56 PM PDT 24
Finished Jul 26 05:10:57 PM PDT 24
Peak memory 207024 kb
Host smart-5c5a79e8-c1bc-46ce-aa1c-e336087cf2d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18074
65337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.1807465337
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.3397587165
Short name T780
Test name
Test status
Simulation time 834962187 ps
CPU time 2.2 seconds
Started Jul 26 05:10:56 PM PDT 24
Finished Jul 26 05:10:58 PM PDT 24
Peak memory 206988 kb
Host smart-1f719693-788a-454b-8dd7-c16ffd246e9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33975
87165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.3397587165
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.35780325
Short name T1788
Test name
Test status
Simulation time 3632396567 ps
CPU time 30.25 seconds
Started Jul 26 05:10:57 PM PDT 24
Finished Jul 26 05:11:28 PM PDT 24
Peak memory 216884 kb
Host smart-dbb5cefd-6b37-47f9-a792-9138299b3315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35780
325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.35780325
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/20.usbdev_timeout_missing_host_handshake.1743396827
Short name T2197
Test name
Test status
Simulation time 4315334197 ps
CPU time 28.14 seconds
Started Jul 26 05:10:44 PM PDT 24
Finished Jul 26 05:11:12 PM PDT 24
Peak memory 207428 kb
Host smart-0e8695f8-170b-4a4a-8c2f-91a9d7930206
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743396827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_timeout_missing_hos
t_handshake.1743396827
Directory /workspace/20.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.2383296389
Short name T1264
Test name
Test status
Simulation time 44629836 ps
CPU time 0.66 seconds
Started Jul 26 05:11:12 PM PDT 24
Finished Jul 26 05:11:12 PM PDT 24
Peak memory 207132 kb
Host smart-09a39a63-16fc-4033-a9aa-5f3eda53c552
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2383296389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.2383296389
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.3204671615
Short name T1143
Test name
Test status
Simulation time 3516350582 ps
CPU time 5.1 seconds
Started Jul 26 05:10:58 PM PDT 24
Finished Jul 26 05:11:03 PM PDT 24
Peak memory 207260 kb
Host smart-b82e0daf-e28a-45a2-a691-8f68ae813015
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204671615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_a
on_wake_disconnect.3204671615
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.10614736
Short name T10
Test name
Test status
Simulation time 13381479270 ps
CPU time 16.58 seconds
Started Jul 26 05:10:57 PM PDT 24
Finished Jul 26 05:11:14 PM PDT 24
Peak memory 207356 kb
Host smart-151c7778-aae1-43d4-bc51-1ad2d8179faf
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=10614736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.10614736
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.1040878319
Short name T1583
Test name
Test status
Simulation time 23324541322 ps
CPU time 30.52 seconds
Started Jul 26 05:10:59 PM PDT 24
Finished Jul 26 05:11:30 PM PDT 24
Peak memory 207312 kb
Host smart-c687bbed-8db2-4ffe-b4b2-5891322668fb
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040878319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_a
on_wake_resume.1040878319
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.2402946677
Short name T2752
Test name
Test status
Simulation time 164595827 ps
CPU time 0.92 seconds
Started Jul 26 05:10:55 PM PDT 24
Finished Jul 26 05:10:56 PM PDT 24
Peak memory 207024 kb
Host smart-2bc660a1-35e7-4402-89db-c3a875d12473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24029
46677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2402946677
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.218251534
Short name T1931
Test name
Test status
Simulation time 141842817 ps
CPU time 0.86 seconds
Started Jul 26 05:11:02 PM PDT 24
Finished Jul 26 05:11:03 PM PDT 24
Peak memory 207180 kb
Host smart-4004d109-2912-485f-99df-b5d93fc3f8cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21825
1534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.218251534
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.2660310875
Short name T605
Test name
Test status
Simulation time 433325815 ps
CPU time 1.53 seconds
Started Jul 26 05:10:58 PM PDT 24
Finished Jul 26 05:11:00 PM PDT 24
Peak memory 207060 kb
Host smart-0471390d-33a3-4bc3-a1b6-2e4b06a7a833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26603
10875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.2660310875
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.3541653133
Short name T1839
Test name
Test status
Simulation time 606136458 ps
CPU time 1.88 seconds
Started Jul 26 05:10:54 PM PDT 24
Finished Jul 26 05:10:56 PM PDT 24
Peak memory 206940 kb
Host smart-6ea0fcee-b5ae-4354-9a9f-7246787bc28b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3541653133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.3541653133
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.3854124083
Short name T1041
Test name
Test status
Simulation time 20839977505 ps
CPU time 48.3 seconds
Started Jul 26 05:10:57 PM PDT 24
Finished Jul 26 05:11:46 PM PDT 24
Peak memory 207308 kb
Host smart-44064719-fbf8-49d0-b6c7-03412bb340c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38541
24083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.3854124083
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_device_timeout.2773025057
Short name T694
Test name
Test status
Simulation time 414455998 ps
CPU time 8.96 seconds
Started Jul 26 05:10:57 PM PDT 24
Finished Jul 26 05:11:06 PM PDT 24
Peak memory 207356 kb
Host smart-be80b4de-1f1e-462a-9fec-09b67d74891f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773025057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_timeout.2773025057
Directory /workspace/21.usbdev_device_timeout/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.774453795
Short name T1378
Test name
Test status
Simulation time 320593002 ps
CPU time 1.24 seconds
Started Jul 26 05:11:00 PM PDT 24
Finished Jul 26 05:11:01 PM PDT 24
Peak memory 207000 kb
Host smart-e19abcae-7bd0-475d-b302-9179cc807ed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77445
3795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.774453795
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.445956126
Short name T2275
Test name
Test status
Simulation time 147676769 ps
CPU time 0.85 seconds
Started Jul 26 05:10:57 PM PDT 24
Finished Jul 26 05:10:58 PM PDT 24
Peak memory 206988 kb
Host smart-26a382ea-4845-4146-b1d8-07fd0c4a394e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44595
6126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.445956126
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.2544801208
Short name T1539
Test name
Test status
Simulation time 78807849 ps
CPU time 0.75 seconds
Started Jul 26 05:10:57 PM PDT 24
Finished Jul 26 05:10:58 PM PDT 24
Peak memory 207004 kb
Host smart-04558741-7a4f-40f4-8701-3572d48d418d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25448
01208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.2544801208
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.4131406541
Short name T1156
Test name
Test status
Simulation time 868366561 ps
CPU time 2.71 seconds
Started Jul 26 05:11:01 PM PDT 24
Finished Jul 26 05:11:03 PM PDT 24
Peak memory 207304 kb
Host smart-8d84fc7c-6613-4fea-a7d4-6eeff9984d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41314
06541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.4131406541
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.2136219227
Short name T2060
Test name
Test status
Simulation time 301740971 ps
CPU time 2 seconds
Started Jul 26 05:10:57 PM PDT 24
Finished Jul 26 05:10:59 PM PDT 24
Peak memory 207348 kb
Host smart-98f6b5d4-a748-4b1b-8b79-b6735a4419b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21362
19227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.2136219227
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.3964612154
Short name T1389
Test name
Test status
Simulation time 243436780 ps
CPU time 1.25 seconds
Started Jul 26 05:11:01 PM PDT 24
Finished Jul 26 05:11:03 PM PDT 24
Peak memory 215464 kb
Host smart-3756e9fd-c58a-4945-969e-70807b5b0473
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3964612154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.3964612154
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.3430500796
Short name T2410
Test name
Test status
Simulation time 159477001 ps
CPU time 0.88 seconds
Started Jul 26 05:11:01 PM PDT 24
Finished Jul 26 05:11:02 PM PDT 24
Peak memory 207016 kb
Host smart-df7c655d-1daa-4927-b679-636b46560b58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34305
00796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.3430500796
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.2778901652
Short name T30
Test name
Test status
Simulation time 208477199 ps
CPU time 0.95 seconds
Started Jul 26 05:10:56 PM PDT 24
Finished Jul 26 05:10:57 PM PDT 24
Peak memory 207100 kb
Host smart-71a73c13-b49c-4d99-a3f4-6ac803911752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27789
01652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.2778901652
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_invalid_sync.3814096697
Short name T2627
Test name
Test status
Simulation time 5678283593 ps
CPU time 44.3 seconds
Started Jul 26 05:11:01 PM PDT 24
Finished Jul 26 05:11:46 PM PDT 24
Peak memory 215472 kb
Host smart-67c5a5fa-f96a-48e8-ab8d-585384bd63ab
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3814096697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.3814096697
Directory /workspace/21.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/21.usbdev_iso_retraction.1491932839
Short name T1738
Test name
Test status
Simulation time 12456599053 ps
CPU time 92.49 seconds
Started Jul 26 05:10:55 PM PDT 24
Finished Jul 26 05:12:28 PM PDT 24
Peak memory 207344 kb
Host smart-e15c0353-b78b-4c07-a6ff-bcd716b5554a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1491932839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_iso_retraction.1491932839
Directory /workspace/21.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.2776048811
Short name T1173
Test name
Test status
Simulation time 207053825 ps
CPU time 0.93 seconds
Started Jul 26 05:10:55 PM PDT 24
Finished Jul 26 05:10:56 PM PDT 24
Peak memory 207136 kb
Host smart-c4f87af5-4edc-4947-b83a-3dda204ce8c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27760
48811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.2776048811
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.1162360664
Short name T2303
Test name
Test status
Simulation time 23293129569 ps
CPU time 29.03 seconds
Started Jul 26 05:11:02 PM PDT 24
Finished Jul 26 05:11:31 PM PDT 24
Peak memory 207436 kb
Host smart-c8c108bf-897b-430c-a364-7994b65a961d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11623
60664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.1162360664
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.1435989959
Short name T336
Test name
Test status
Simulation time 3269767544 ps
CPU time 5.09 seconds
Started Jul 26 05:11:00 PM PDT 24
Finished Jul 26 05:11:05 PM PDT 24
Peak memory 207228 kb
Host smart-f2114049-53bd-4dd1-88d3-d79c43156583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14359
89959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.1435989959
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.89499572
Short name T565
Test name
Test status
Simulation time 5171597872 ps
CPU time 151.33 seconds
Started Jul 26 05:11:00 PM PDT 24
Finished Jul 26 05:13:31 PM PDT 24
Peak memory 215476 kb
Host smart-d2ade44d-a5fa-480d-b7ee-d371faa1b1cd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=89499572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.89499572
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.2770244614
Short name T534
Test name
Test status
Simulation time 316022202 ps
CPU time 1.15 seconds
Started Jul 26 05:11:03 PM PDT 24
Finished Jul 26 05:11:04 PM PDT 24
Peak memory 207204 kb
Host smart-13cb8077-157d-4495-a92c-bc73ecb44f11
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2770244614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.2770244614
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.1867869419
Short name T503
Test name
Test status
Simulation time 198139169 ps
CPU time 0.94 seconds
Started Jul 26 05:10:58 PM PDT 24
Finished Jul 26 05:10:59 PM PDT 24
Peak memory 207100 kb
Host smart-8fcf7c56-6c82-4456-aa31-3235bcc6f4ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18678
69419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.1867869419
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.607656420
Short name T2643
Test name
Test status
Simulation time 5912621968 ps
CPU time 171.46 seconds
Started Jul 26 05:10:58 PM PDT 24
Finished Jul 26 05:13:50 PM PDT 24
Peak memory 215580 kb
Host smart-f52f891e-7b5c-4b5a-983f-d3c4ed042df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60765
6420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.607656420
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.1758887261
Short name T998
Test name
Test status
Simulation time 4399024903 ps
CPU time 36.86 seconds
Started Jul 26 05:10:59 PM PDT 24
Finished Jul 26 05:11:36 PM PDT 24
Peak memory 216876 kb
Host smart-13742e5b-96ff-4aff-9020-78b3c99d732b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1758887261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.1758887261
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.2896740609
Short name T1148
Test name
Test status
Simulation time 194365878 ps
CPU time 0.94 seconds
Started Jul 26 05:10:58 PM PDT 24
Finished Jul 26 05:10:59 PM PDT 24
Peak memory 207128 kb
Host smart-1849ef23-1fd8-4a77-b78a-4520711acf62
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2896740609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.2896740609
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.1678365440
Short name T2858
Test name
Test status
Simulation time 143267322 ps
CPU time 0.82 seconds
Started Jul 26 05:10:59 PM PDT 24
Finished Jul 26 05:11:00 PM PDT 24
Peak memory 207056 kb
Host smart-2ea5466f-305e-4a0d-85b9-dbe5e5a8d920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16783
65440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.1678365440
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.219625622
Short name T136
Test name
Test status
Simulation time 266823805 ps
CPU time 1.07 seconds
Started Jul 26 05:11:03 PM PDT 24
Finished Jul 26 05:11:04 PM PDT 24
Peak memory 207212 kb
Host smart-f4397288-dfcf-4471-97ef-541686131a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21962
5622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.219625622
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.3859788281
Short name T564
Test name
Test status
Simulation time 174718027 ps
CPU time 0.92 seconds
Started Jul 26 05:11:00 PM PDT 24
Finished Jul 26 05:11:01 PM PDT 24
Peak memory 206972 kb
Host smart-80b7f96c-335f-4116-aea8-4d9173c9fc25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38597
88281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.3859788281
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.4215313513
Short name T1592
Test name
Test status
Simulation time 178674056 ps
CPU time 0.88 seconds
Started Jul 26 05:10:59 PM PDT 24
Finished Jul 26 05:11:00 PM PDT 24
Peak memory 207140 kb
Host smart-9f3dc491-efe3-48ac-8bab-e1988226eb14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42153
13513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.4215313513
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.373536419
Short name T1477
Test name
Test status
Simulation time 186161208 ps
CPU time 0.93 seconds
Started Jul 26 05:11:03 PM PDT 24
Finished Jul 26 05:11:04 PM PDT 24
Peak memory 207072 kb
Host smart-414f263b-08b9-473f-8c24-503064777921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37353
6419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.373536419
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.3598948707
Short name T1719
Test name
Test status
Simulation time 219818683 ps
CPU time 0.95 seconds
Started Jul 26 05:11:04 PM PDT 24
Finished Jul 26 05:11:05 PM PDT 24
Peak memory 207048 kb
Host smart-2c7d2497-a687-4499-8ac8-c4547643ebc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35989
48707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.3598948707
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.3265872304
Short name T876
Test name
Test status
Simulation time 239834292 ps
CPU time 1.08 seconds
Started Jul 26 05:11:00 PM PDT 24
Finished Jul 26 05:11:01 PM PDT 24
Peak memory 206980 kb
Host smart-bfe590bc-5fa7-46fa-8465-210fb49633b8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3265872304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.3265872304
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.1512983955
Short name T1390
Test name
Test status
Simulation time 149075537 ps
CPU time 0.87 seconds
Started Jul 26 05:11:04 PM PDT 24
Finished Jul 26 05:11:05 PM PDT 24
Peak memory 207060 kb
Host smart-b848b61a-85f0-4f41-8727-3a5875f8ddf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15129
83955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.1512983955
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.877930543
Short name T2260
Test name
Test status
Simulation time 43456195 ps
CPU time 0.73 seconds
Started Jul 26 05:11:03 PM PDT 24
Finished Jul 26 05:11:05 PM PDT 24
Peak memory 207036 kb
Host smart-ad4495c2-2e50-4992-acf0-b818026932dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87793
0543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.877930543
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.390650184
Short name T2314
Test name
Test status
Simulation time 12013676813 ps
CPU time 30.51 seconds
Started Jul 26 05:11:00 PM PDT 24
Finished Jul 26 05:11:31 PM PDT 24
Peak memory 219616 kb
Host smart-51a49c73-b359-41a6-9f7f-803e06a500cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39065
0184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.390650184
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.2315131462
Short name T2127
Test name
Test status
Simulation time 220617104 ps
CPU time 1.01 seconds
Started Jul 26 05:11:03 PM PDT 24
Finished Jul 26 05:11:04 PM PDT 24
Peak memory 207072 kb
Host smart-4ebd0872-cbd1-474c-96f2-1d76a08840d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23151
31462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.2315131462
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.1296990906
Short name T2659
Test name
Test status
Simulation time 220690759 ps
CPU time 0.98 seconds
Started Jul 26 05:10:59 PM PDT 24
Finished Jul 26 05:11:00 PM PDT 24
Peak memory 207128 kb
Host smart-b2d01a16-08f7-47ee-bbc5-dc57308f1b38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12969
90906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.1296990906
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.43754416
Short name T1561
Test name
Test status
Simulation time 171817334 ps
CPU time 0.94 seconds
Started Jul 26 05:11:03 PM PDT 24
Finished Jul 26 05:11:04 PM PDT 24
Peak memory 207072 kb
Host smart-186abb17-6b86-4627-9836-4148c484d1f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43754
416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.43754416
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.353653579
Short name T1283
Test name
Test status
Simulation time 158827119 ps
CPU time 0.89 seconds
Started Jul 26 05:10:59 PM PDT 24
Finished Jul 26 05:11:00 PM PDT 24
Peak memory 207056 kb
Host smart-4877aa70-0d50-47a6-abe1-ca10c312445d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35365
3579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.353653579
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.3431464720
Short name T2023
Test name
Test status
Simulation time 200561567 ps
CPU time 0.89 seconds
Started Jul 26 05:11:02 PM PDT 24
Finished Jul 26 05:11:03 PM PDT 24
Peak memory 207068 kb
Host smart-361f5cf2-464c-42a8-9792-fd7dd080210e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34314
64720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.3431464720
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.1562524150
Short name T2117
Test name
Test status
Simulation time 156725811 ps
CPU time 0.83 seconds
Started Jul 26 05:11:08 PM PDT 24
Finished Jul 26 05:11:08 PM PDT 24
Peak memory 207180 kb
Host smart-88dd9250-26b4-42d6-8d0e-0719fcd5bc3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15625
24150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.1562524150
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.3297910302
Short name T303
Test name
Test status
Simulation time 159298470 ps
CPU time 0.95 seconds
Started Jul 26 05:11:11 PM PDT 24
Finished Jul 26 05:11:12 PM PDT 24
Peak memory 207060 kb
Host smart-e2dbc9e2-5aed-4555-a9c6-6c399303745a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32979
10302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.3297910302
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.4196368548
Short name T1736
Test name
Test status
Simulation time 251413120 ps
CPU time 1.06 seconds
Started Jul 26 05:11:08 PM PDT 24
Finished Jul 26 05:11:09 PM PDT 24
Peak memory 207128 kb
Host smart-4b8808d2-90a1-4028-9f8d-ca17d2ae71e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41963
68548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.4196368548
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.799301407
Short name T2160
Test name
Test status
Simulation time 5068207078 ps
CPU time 51.61 seconds
Started Jul 26 05:11:06 PM PDT 24
Finished Jul 26 05:11:57 PM PDT 24
Peak memory 217244 kb
Host smart-0b17d64d-5bf8-4d63-a317-a5ec5ead912d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=799301407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.799301407
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.3511993324
Short name T591
Test name
Test status
Simulation time 167530608 ps
CPU time 0.88 seconds
Started Jul 26 05:11:06 PM PDT 24
Finished Jul 26 05:11:07 PM PDT 24
Peak memory 207052 kb
Host smart-70ba995f-b014-4dab-8c74-1393a7191f95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35119
93324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.3511993324
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.1572008424
Short name T953
Test name
Test status
Simulation time 189358715 ps
CPU time 0.87 seconds
Started Jul 26 05:11:07 PM PDT 24
Finished Jul 26 05:11:08 PM PDT 24
Peak memory 207024 kb
Host smart-3be5b753-6835-43f0-816c-21fdd175d762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15720
08424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.1572008424
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.3494407969
Short name T1012
Test name
Test status
Simulation time 1202895748 ps
CPU time 3.16 seconds
Started Jul 26 05:11:06 PM PDT 24
Finished Jul 26 05:11:09 PM PDT 24
Peak memory 207340 kb
Host smart-4d3c282b-5219-4fee-b553-7c936c68e8f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34944
07969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.3494407969
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.1353853706
Short name T683
Test name
Test status
Simulation time 4110920827 ps
CPU time 118.92 seconds
Started Jul 26 05:11:05 PM PDT 24
Finished Jul 26 05:13:04 PM PDT 24
Peak memory 215532 kb
Host smart-f3806701-84e2-48b4-8ce7-9ebe0934d69f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13538
53706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.1353853706
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_timeout_missing_host_handshake.2246092673
Short name T1170
Test name
Test status
Simulation time 171124702 ps
CPU time 0.92 seconds
Started Jul 26 05:10:58 PM PDT 24
Finished Jul 26 05:10:59 PM PDT 24
Peak memory 207128 kb
Host smart-7b1c45d7-61fe-4a1f-9ec4-49bd39ea9aaf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246092673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_timeout_missing_hos
t_handshake.2246092673
Directory /workspace/21.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.2661464194
Short name T449
Test name
Test status
Simulation time 47089485 ps
CPU time 0.64 seconds
Started Jul 26 05:11:17 PM PDT 24
Finished Jul 26 05:11:17 PM PDT 24
Peak memory 207084 kb
Host smart-e46edae7-5bf3-45f2-8773-bd415d288b15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2661464194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.2661464194
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.3322900323
Short name T2006
Test name
Test status
Simulation time 3809563757 ps
CPU time 6.27 seconds
Started Jul 26 05:11:04 PM PDT 24
Finished Jul 26 05:11:10 PM PDT 24
Peak memory 207344 kb
Host smart-0d76f253-2d74-4751-a48b-4b22efe872d1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322900323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_a
on_wake_disconnect.3322900323
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.3099863930
Short name T1107
Test name
Test status
Simulation time 13351869652 ps
CPU time 18.36 seconds
Started Jul 26 05:11:04 PM PDT 24
Finished Jul 26 05:11:23 PM PDT 24
Peak memory 207392 kb
Host smart-60338417-5ec7-434a-8e70-c205edb3c87d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099863930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.3099863930
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.3021563042
Short name T2663
Test name
Test status
Simulation time 23420627084 ps
CPU time 27.98 seconds
Started Jul 26 05:11:10 PM PDT 24
Finished Jul 26 05:11:38 PM PDT 24
Peak memory 207360 kb
Host smart-bcc84120-fe62-46d0-bd7c-ce49f3440d00
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021563042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_a
on_wake_resume.3021563042
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.2580821220
Short name T2369
Test name
Test status
Simulation time 211127324 ps
CPU time 0.9 seconds
Started Jul 26 05:11:16 PM PDT 24
Finished Jul 26 05:11:18 PM PDT 24
Peak memory 207012 kb
Host smart-22926689-3249-4cbc-aef8-93dd577bbf37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25808
21220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.2580821220
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.2644089385
Short name T2119
Test name
Test status
Simulation time 156250050 ps
CPU time 0.85 seconds
Started Jul 26 05:11:10 PM PDT 24
Finished Jul 26 05:11:11 PM PDT 24
Peak memory 207092 kb
Host smart-2aa6eca7-2e66-4234-8e9d-e385e21dafd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26440
89385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.2644089385
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.2273573722
Short name T450
Test name
Test status
Simulation time 342184963 ps
CPU time 1.32 seconds
Started Jul 26 05:11:06 PM PDT 24
Finished Jul 26 05:11:07 PM PDT 24
Peak memory 207040 kb
Host smart-0b5b0f2b-418e-400f-993e-6f536f965c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22735
73722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.2273573722
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.2874953037
Short name T913
Test name
Test status
Simulation time 1012126464 ps
CPU time 2.53 seconds
Started Jul 26 05:11:14 PM PDT 24
Finished Jul 26 05:11:17 PM PDT 24
Peak memory 207344 kb
Host smart-435073e6-d4ad-47ea-9116-5f5f60b27897
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2874953037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.2874953037
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.1974963576
Short name T1083
Test name
Test status
Simulation time 21940998279 ps
CPU time 47.87 seconds
Started Jul 26 05:11:07 PM PDT 24
Finished Jul 26 05:11:55 PM PDT 24
Peak memory 207324 kb
Host smart-6f40817a-e569-4716-80f8-460e39559d26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19749
63576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.1974963576
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_device_timeout.3289691874
Short name T1742
Test name
Test status
Simulation time 1545473000 ps
CPU time 35.49 seconds
Started Jul 26 05:11:05 PM PDT 24
Finished Jul 26 05:11:40 PM PDT 24
Peak memory 207304 kb
Host smart-08b8667d-d5e5-484c-9f69-df9067b96aa8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289691874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_timeout.3289691874
Directory /workspace/22.usbdev_device_timeout/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.382250686
Short name T992
Test name
Test status
Simulation time 327124348 ps
CPU time 1.2 seconds
Started Jul 26 05:11:12 PM PDT 24
Finished Jul 26 05:11:13 PM PDT 24
Peak memory 207064 kb
Host smart-ed09699b-670f-47c4-909b-57939a0e5ced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38225
0686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.382250686
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.3846483485
Short name T1714
Test name
Test status
Simulation time 166232903 ps
CPU time 0.85 seconds
Started Jul 26 05:11:11 PM PDT 24
Finished Jul 26 05:11:12 PM PDT 24
Peak memory 207028 kb
Host smart-938f235f-3ba3-422a-9930-2001c008d981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38464
83485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.3846483485
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.2521683154
Short name T1233
Test name
Test status
Simulation time 58503231 ps
CPU time 0.7 seconds
Started Jul 26 05:11:08 PM PDT 24
Finished Jul 26 05:11:09 PM PDT 24
Peak memory 207060 kb
Host smart-104ff0c4-1126-480a-939a-c7c9ab8a1e6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25216
83154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.2521683154
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.3785021256
Short name T2444
Test name
Test status
Simulation time 883145137 ps
CPU time 2.33 seconds
Started Jul 26 05:11:19 PM PDT 24
Finished Jul 26 05:11:21 PM PDT 24
Peak memory 207236 kb
Host smart-af6778b1-0538-4018-93bf-b02256242e6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37850
21256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.3785021256
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.3724432128
Short name T1873
Test name
Test status
Simulation time 305091201 ps
CPU time 2.01 seconds
Started Jul 26 05:11:05 PM PDT 24
Finished Jul 26 05:11:07 PM PDT 24
Peak memory 207200 kb
Host smart-6f627f63-ebe9-41fc-9ecb-532a0f678d0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37244
32128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.3724432128
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.2360239094
Short name T2045
Test name
Test status
Simulation time 177536938 ps
CPU time 0.97 seconds
Started Jul 26 05:11:10 PM PDT 24
Finished Jul 26 05:11:11 PM PDT 24
Peak memory 207136 kb
Host smart-449000b1-821c-4cca-99dc-2d06300c48c7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2360239094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.2360239094
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.2203743338
Short name T1766
Test name
Test status
Simulation time 151448964 ps
CPU time 0.87 seconds
Started Jul 26 05:11:11 PM PDT 24
Finished Jul 26 05:11:13 PM PDT 24
Peak memory 207012 kb
Host smart-451a30a3-e708-411f-ba63-67e02d2f083c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22037
43338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.2203743338
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.1095650931
Short name T708
Test name
Test status
Simulation time 215437469 ps
CPU time 0.98 seconds
Started Jul 26 05:11:07 PM PDT 24
Finished Jul 26 05:11:08 PM PDT 24
Peak memory 207080 kb
Host smart-0c0ad8b9-bd7c-4661-9bd8-9666b8a0d702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10956
50931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.1095650931
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.736050853
Short name T1102
Test name
Test status
Simulation time 9352669193 ps
CPU time 69.41 seconds
Started Jul 26 05:11:17 PM PDT 24
Finished Jul 26 05:12:27 PM PDT 24
Peak memory 216528 kb
Host smart-52ab1f89-fb7e-4dd3-b45b-6d77a59a5538
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=736050853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.736050853
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_iso_retraction.48875525
Short name T2354
Test name
Test status
Simulation time 4853342181 ps
CPU time 31.88 seconds
Started Jul 26 05:11:06 PM PDT 24
Finished Jul 26 05:11:38 PM PDT 24
Peak memory 207304 kb
Host smart-88337a64-e7cf-47ff-a200-4e25f8beedaa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=48875525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.48875525
Directory /workspace/22.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.2518745029
Short name T2464
Test name
Test status
Simulation time 197356171 ps
CPU time 0.98 seconds
Started Jul 26 05:11:15 PM PDT 24
Finished Jul 26 05:11:17 PM PDT 24
Peak memory 207100 kb
Host smart-15eb0b2d-a06a-483a-8fcf-2a52fb79d861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25187
45029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.2518745029
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.3545353831
Short name T2708
Test name
Test status
Simulation time 23282900942 ps
CPU time 27.65 seconds
Started Jul 26 05:11:17 PM PDT 24
Finished Jul 26 05:11:45 PM PDT 24
Peak memory 207240 kb
Host smart-251fe92d-eaca-4973-b4b1-f123188a5b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35453
53831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.3545353831
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.2340642819
Short name T2723
Test name
Test status
Simulation time 3322296331 ps
CPU time 5.04 seconds
Started Jul 26 05:11:10 PM PDT 24
Finished Jul 26 05:11:15 PM PDT 24
Peak memory 207372 kb
Host smart-b0ee6368-15a0-4f6e-9347-bb71f310136d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23406
42819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.2340642819
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.2916657796
Short name T299
Test name
Test status
Simulation time 6887889639 ps
CPU time 205.98 seconds
Started Jul 26 05:11:08 PM PDT 24
Finished Jul 26 05:14:34 PM PDT 24
Peak memory 215488 kb
Host smart-d9d7e052-840d-4068-93de-9f6336373d41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29166
57796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.2916657796
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.1736933509
Short name T1585
Test name
Test status
Simulation time 4070886418 ps
CPU time 123.17 seconds
Started Jul 26 05:11:05 PM PDT 24
Finished Jul 26 05:13:09 PM PDT 24
Peak memory 215544 kb
Host smart-38921519-c254-4fb8-b784-472af2b29443
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1736933509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.1736933509
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.4053209465
Short name T1330
Test name
Test status
Simulation time 302311455 ps
CPU time 1.09 seconds
Started Jul 26 05:11:14 PM PDT 24
Finished Jul 26 05:11:16 PM PDT 24
Peak memory 207124 kb
Host smart-03f2351d-3314-45e0-b694-b2daf25d5b5e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4053209465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.4053209465
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.4037349330
Short name T698
Test name
Test status
Simulation time 192708580 ps
CPU time 0.96 seconds
Started Jul 26 05:11:10 PM PDT 24
Finished Jul 26 05:11:11 PM PDT 24
Peak memory 207156 kb
Host smart-73fc46d4-5634-44d8-9de5-229cf226acbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40373
49330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.4037349330
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.2808404222
Short name T1391
Test name
Test status
Simulation time 5442213080 ps
CPU time 39.43 seconds
Started Jul 26 05:11:15 PM PDT 24
Finished Jul 26 05:11:54 PM PDT 24
Peak memory 215572 kb
Host smart-96bbbc6c-6ded-4c90-b9c5-467686005f87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28084
04222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.2808404222
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.1153189302
Short name T2721
Test name
Test status
Simulation time 5028133902 ps
CPU time 39.58 seconds
Started Jul 26 05:11:08 PM PDT 24
Finished Jul 26 05:11:47 PM PDT 24
Peak memory 216720 kb
Host smart-f0273825-432c-4cb6-b0b7-d004fbfe7bb8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1153189302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.1153189302
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.152023867
Short name T1885
Test name
Test status
Simulation time 173431185 ps
CPU time 0.87 seconds
Started Jul 26 05:11:08 PM PDT 24
Finished Jul 26 05:11:09 PM PDT 24
Peak memory 207140 kb
Host smart-9ab3f382-8604-4e58-8268-1f6d7ee24889
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=152023867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.152023867
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.744824059
Short name T1262
Test name
Test status
Simulation time 161542214 ps
CPU time 0.87 seconds
Started Jul 26 05:11:06 PM PDT 24
Finished Jul 26 05:11:07 PM PDT 24
Peak memory 207096 kb
Host smart-a0b3a95c-ea59-494d-9935-a44bf61a3bcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74482
4059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.744824059
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.2893136299
Short name T115
Test name
Test status
Simulation time 166893165 ps
CPU time 0.92 seconds
Started Jul 26 05:11:11 PM PDT 24
Finished Jul 26 05:11:12 PM PDT 24
Peak memory 207144 kb
Host smart-457910c7-3221-4ba8-85d0-78ee5162772b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28931
36299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.2893136299
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.3311783155
Short name T1556
Test name
Test status
Simulation time 157930061 ps
CPU time 0.85 seconds
Started Jul 26 05:11:17 PM PDT 24
Finished Jul 26 05:11:19 PM PDT 24
Peak memory 206904 kb
Host smart-b6b9af41-f6f5-403c-9cad-54353f762ad3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33117
83155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.3311783155
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.2949855012
Short name T1599
Test name
Test status
Simulation time 162549648 ps
CPU time 0.87 seconds
Started Jul 26 05:11:09 PM PDT 24
Finished Jul 26 05:11:10 PM PDT 24
Peak memory 207048 kb
Host smart-ab5f3751-beab-4c75-af8b-bec675c0b852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29498
55012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.2949855012
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.3562275538
Short name T1816
Test name
Test status
Simulation time 152356559 ps
CPU time 0.83 seconds
Started Jul 26 05:11:11 PM PDT 24
Finished Jul 26 05:11:12 PM PDT 24
Peak memory 207136 kb
Host smart-032eb127-4e00-400f-b5da-6311bf2fc95e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35622
75538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.3562275538
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.2836508891
Short name T163
Test name
Test status
Simulation time 161733399 ps
CPU time 0.85 seconds
Started Jul 26 05:11:17 PM PDT 24
Finished Jul 26 05:11:18 PM PDT 24
Peak memory 206988 kb
Host smart-4dd4d1ed-3139-404e-808f-965a0d715b19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28365
08891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.2836508891
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.2412222713
Short name T2429
Test name
Test status
Simulation time 246597044 ps
CPU time 1.03 seconds
Started Jul 26 05:11:16 PM PDT 24
Finished Jul 26 05:11:17 PM PDT 24
Peak memory 207100 kb
Host smart-bb11867c-692e-4d98-b063-5e2be82fcef7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2412222713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.2412222713
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.827395155
Short name T1478
Test name
Test status
Simulation time 178628384 ps
CPU time 0.94 seconds
Started Jul 26 05:11:16 PM PDT 24
Finished Jul 26 05:11:17 PM PDT 24
Peak memory 207088 kb
Host smart-6e5d46de-5d75-47de-b024-40283f261628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82739
5155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.827395155
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.85274793
Short name T1722
Test name
Test status
Simulation time 45139111 ps
CPU time 0.74 seconds
Started Jul 26 05:11:11 PM PDT 24
Finished Jul 26 05:11:12 PM PDT 24
Peak memory 206972 kb
Host smart-8b4e8643-3925-48e3-8338-dd7dcbcc44da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85274
793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.85274793
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.2627597816
Short name T258
Test name
Test status
Simulation time 22948112634 ps
CPU time 60.71 seconds
Started Jul 26 05:11:07 PM PDT 24
Finished Jul 26 05:12:08 PM PDT 24
Peak memory 215592 kb
Host smart-1e5d7104-9531-4b71-a1f6-950d9cce9b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26275
97816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.2627597816
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.3741714480
Short name T2135
Test name
Test status
Simulation time 180196078 ps
CPU time 0.96 seconds
Started Jul 26 05:11:05 PM PDT 24
Finished Jul 26 05:11:06 PM PDT 24
Peak memory 207080 kb
Host smart-f91cc672-0d17-4e0f-ac29-1e18f11632ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37417
14480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.3741714480
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.2376296106
Short name T970
Test name
Test status
Simulation time 218288066 ps
CPU time 0.95 seconds
Started Jul 26 05:11:17 PM PDT 24
Finished Jul 26 05:11:18 PM PDT 24
Peak memory 206976 kb
Host smart-fb0602eb-c95d-4706-b3f6-8fd2d2f07d77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23762
96106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.2376296106
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.2626922089
Short name T1392
Test name
Test status
Simulation time 171441432 ps
CPU time 0.9 seconds
Started Jul 26 05:11:17 PM PDT 24
Finished Jul 26 05:11:19 PM PDT 24
Peak memory 206884 kb
Host smart-3f3a8996-0ec4-424c-a983-a7a36d001f57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26269
22089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.2626922089
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.4233788666
Short name T1169
Test name
Test status
Simulation time 173204406 ps
CPU time 0.93 seconds
Started Jul 26 05:11:05 PM PDT 24
Finished Jul 26 05:11:06 PM PDT 24
Peak memory 207136 kb
Host smart-e239d14a-5fca-4b75-9f7c-575ffe272039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42337
88666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.4233788666
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.2681606767
Short name T2278
Test name
Test status
Simulation time 139405379 ps
CPU time 0.82 seconds
Started Jul 26 05:11:06 PM PDT 24
Finished Jul 26 05:11:07 PM PDT 24
Peak memory 207000 kb
Host smart-75db148f-cc32-4962-bdcf-ff8d0cdace17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26816
06767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.2681606767
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.3816367394
Short name T2463
Test name
Test status
Simulation time 151259084 ps
CPU time 0.84 seconds
Started Jul 26 05:11:11 PM PDT 24
Finished Jul 26 05:11:12 PM PDT 24
Peak memory 207092 kb
Host smart-fcd0388b-a9bf-4590-9b65-26b6a336b13d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38163
67394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.3816367394
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.2639084118
Short name T2096
Test name
Test status
Simulation time 145334137 ps
CPU time 0.81 seconds
Started Jul 26 05:11:15 PM PDT 24
Finished Jul 26 05:11:16 PM PDT 24
Peak memory 207104 kb
Host smart-793f5bd3-df85-4371-b277-7b8cb40a1c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26390
84118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.2639084118
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.4192272150
Short name T1339
Test name
Test status
Simulation time 260217573 ps
CPU time 1.17 seconds
Started Jul 26 05:11:06 PM PDT 24
Finished Jul 26 05:11:07 PM PDT 24
Peak memory 207012 kb
Host smart-d45058c8-fd0f-4c70-9dcd-08ac0ea9e320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41922
72150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.4192272150
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.2773287059
Short name T2198
Test name
Test status
Simulation time 3345308385 ps
CPU time 25.99 seconds
Started Jul 26 05:11:03 PM PDT 24
Finished Jul 26 05:11:29 PM PDT 24
Peak memory 215508 kb
Host smart-d1baa484-aa91-4062-9a9a-8f9eb5b75b43
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2773287059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.2773287059
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.992273819
Short name T2367
Test name
Test status
Simulation time 176167409 ps
CPU time 0.91 seconds
Started Jul 26 05:11:12 PM PDT 24
Finished Jul 26 05:11:13 PM PDT 24
Peak memory 207084 kb
Host smart-5958bcc0-c59c-4880-b1f1-13cce82660de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99227
3819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.992273819
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.2505058615
Short name T636
Test name
Test status
Simulation time 177160290 ps
CPU time 0.98 seconds
Started Jul 26 05:11:04 PM PDT 24
Finished Jul 26 05:11:05 PM PDT 24
Peak memory 207000 kb
Host smart-25a3172d-7cce-43cf-8259-dd69d0d7b066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25050
58615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.2505058615
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.2664836203
Short name T1481
Test name
Test status
Simulation time 668594427 ps
CPU time 2.01 seconds
Started Jul 26 05:11:16 PM PDT 24
Finished Jul 26 05:11:18 PM PDT 24
Peak memory 206248 kb
Host smart-70a27369-f1a9-4e5a-a998-4e3a07ce7e1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26648
36203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.2664836203
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.658772457
Short name T1925
Test name
Test status
Simulation time 4771568410 ps
CPU time 38.73 seconds
Started Jul 26 05:11:20 PM PDT 24
Finished Jul 26 05:11:59 PM PDT 24
Peak memory 216996 kb
Host smart-361916de-5c0c-474a-923f-af486dcb91df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65877
2457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.658772457
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_timeout_missing_host_handshake.2974677278
Short name T2307
Test name
Test status
Simulation time 1667962729 ps
CPU time 40.77 seconds
Started Jul 26 05:11:10 PM PDT 24
Finished Jul 26 05:11:51 PM PDT 24
Peak memory 207384 kb
Host smart-63aca35c-d277-439f-860c-7434c3632892
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974677278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_timeout_missing_hos
t_handshake.2974677278
Directory /workspace/22.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.1812847128
Short name T1945
Test name
Test status
Simulation time 39133133 ps
CPU time 0.68 seconds
Started Jul 26 05:11:28 PM PDT 24
Finished Jul 26 05:11:29 PM PDT 24
Peak memory 206924 kb
Host smart-4bcb4c32-d41f-41d5-9866-7209ed67fddf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1812847128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.1812847128
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.3326938889
Short name T1328
Test name
Test status
Simulation time 4243553347 ps
CPU time 6.28 seconds
Started Jul 26 05:11:18 PM PDT 24
Finished Jul 26 05:11:25 PM PDT 24
Peak memory 207264 kb
Host smart-2eba79df-9123-41e6-a9ca-62e3ca8ea5d4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326938889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_a
on_wake_disconnect.3326938889
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.3917899466
Short name T2302
Test name
Test status
Simulation time 13355883520 ps
CPU time 15 seconds
Started Jul 26 05:11:17 PM PDT 24
Finished Jul 26 05:11:33 PM PDT 24
Peak memory 207296 kb
Host smart-51d3f8c5-12e7-477d-bc5f-a295e7cfd4dc
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917899466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.3917899466
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.936062676
Short name T1840
Test name
Test status
Simulation time 23362112442 ps
CPU time 32.48 seconds
Started Jul 26 05:11:18 PM PDT 24
Finished Jul 26 05:11:50 PM PDT 24
Peak memory 207296 kb
Host smart-fbd7742c-fed8-4bd7-8fc6-30972679e0fa
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936062676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_ao
n_wake_resume.936062676
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.2238946161
Short name T2555
Test name
Test status
Simulation time 150218303 ps
CPU time 0.81 seconds
Started Jul 26 05:11:16 PM PDT 24
Finished Jul 26 05:11:17 PM PDT 24
Peak memory 207148 kb
Host smart-31a6ad30-faf4-47fd-a6e1-9fe774eb062f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22389
46161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.2238946161
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.2463517038
Short name T2431
Test name
Test status
Simulation time 172233406 ps
CPU time 0.88 seconds
Started Jul 26 05:11:17 PM PDT 24
Finished Jul 26 05:11:18 PM PDT 24
Peak memory 207100 kb
Host smart-354f510d-6aff-4437-9eaf-d9e3db02f855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24635
17038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.2463517038
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.553770749
Short name T1920
Test name
Test status
Simulation time 250546086 ps
CPU time 1.1 seconds
Started Jul 26 05:11:14 PM PDT 24
Finished Jul 26 05:11:15 PM PDT 24
Peak memory 207320 kb
Host smart-c3f8d636-56cc-4cae-b3a2-524d3a883a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55377
0749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.553770749
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.3143212410
Short name T2154
Test name
Test status
Simulation time 837491762 ps
CPU time 2.61 seconds
Started Jul 26 05:11:18 PM PDT 24
Finished Jul 26 05:11:20 PM PDT 24
Peak memory 207236 kb
Host smart-5b3decd4-8531-4d36-9825-5cb92a30fe9a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3143212410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.3143212410
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.4090783433
Short name T1800
Test name
Test status
Simulation time 5990379601 ps
CPU time 12.77 seconds
Started Jul 26 05:11:16 PM PDT 24
Finished Jul 26 05:11:29 PM PDT 24
Peak memory 207560 kb
Host smart-5ebe638f-26c4-4d08-a644-dcb77c154140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40907
83433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.4090783433
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_device_timeout.2651650668
Short name T1483
Test name
Test status
Simulation time 178497830 ps
CPU time 0.95 seconds
Started Jul 26 05:11:17 PM PDT 24
Finished Jul 26 05:11:18 PM PDT 24
Peak memory 207112 kb
Host smart-5294c658-657f-4999-a78f-82527d13bed8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651650668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_timeout.2651650668
Directory /workspace/23.usbdev_device_timeout/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.3750075733
Short name T2062
Test name
Test status
Simulation time 455518047 ps
CPU time 1.54 seconds
Started Jul 26 05:11:16 PM PDT 24
Finished Jul 26 05:11:18 PM PDT 24
Peak memory 207096 kb
Host smart-7edb9d54-f4df-4e69-977c-5910af43c13e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37500
75733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.3750075733
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.1850550326
Short name T2209
Test name
Test status
Simulation time 146415678 ps
CPU time 0.85 seconds
Started Jul 26 05:11:17 PM PDT 24
Finished Jul 26 05:11:18 PM PDT 24
Peak memory 206944 kb
Host smart-c1a27b38-d72b-45cf-ac1b-3b7355055711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18505
50326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.1850550326
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.2708819098
Short name T939
Test name
Test status
Simulation time 92310946 ps
CPU time 0.75 seconds
Started Jul 26 05:11:16 PM PDT 24
Finished Jul 26 05:11:16 PM PDT 24
Peak memory 207064 kb
Host smart-491f729e-50a1-455b-9b8a-dbd73e7cc546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27088
19098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.2708819098
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.2579088828
Short name T2224
Test name
Test status
Simulation time 855574850 ps
CPU time 2.38 seconds
Started Jul 26 05:11:16 PM PDT 24
Finished Jul 26 05:11:18 PM PDT 24
Peak memory 207352 kb
Host smart-72e10a06-3371-4a10-8400-b53ef82e9fab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25790
88828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.2579088828
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.3705541480
Short name T750
Test name
Test status
Simulation time 255927802 ps
CPU time 2.02 seconds
Started Jul 26 05:11:17 PM PDT 24
Finished Jul 26 05:11:19 PM PDT 24
Peak memory 207280 kb
Host smart-46c5b241-86a0-4210-ade5-8caa3f99ef48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37055
41480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.3705541480
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.2393048827
Short name T2809
Test name
Test status
Simulation time 211362833 ps
CPU time 1.05 seconds
Started Jul 26 05:11:17 PM PDT 24
Finished Jul 26 05:11:19 PM PDT 24
Peak memory 215536 kb
Host smart-700d9fa5-19c9-48ae-99c7-6e8222dfeca8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2393048827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.2393048827
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.2999644391
Short name T2344
Test name
Test status
Simulation time 148006234 ps
CPU time 0.79 seconds
Started Jul 26 05:11:17 PM PDT 24
Finished Jul 26 05:11:19 PM PDT 24
Peak memory 207124 kb
Host smart-ce4f2b78-fa5f-4ba0-983a-4f3eaa6b27aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29996
44391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.2999644391
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.4107851056
Short name T2426
Test name
Test status
Simulation time 208742987 ps
CPU time 0.96 seconds
Started Jul 26 05:11:16 PM PDT 24
Finished Jul 26 05:11:17 PM PDT 24
Peak memory 207132 kb
Host smart-406e9bea-0b91-4a26-93cc-86383472da9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41078
51056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.4107851056
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.2908222785
Short name T1460
Test name
Test status
Simulation time 6315512164 ps
CPU time 206.63 seconds
Started Jul 26 05:11:16 PM PDT 24
Finished Jul 26 05:14:43 PM PDT 24
Peak memory 215636 kb
Host smart-481f305f-dd01-4dac-b44b-75fa45ba10a5
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2908222785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.2908222785
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_iso_retraction.2408712446
Short name T2620
Test name
Test status
Simulation time 11013781385 ps
CPU time 134.25 seconds
Started Jul 26 05:11:19 PM PDT 24
Finished Jul 26 05:13:33 PM PDT 24
Peak memory 207312 kb
Host smart-43989e1b-e0e6-4f2e-947b-d6b8f1737e94
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2408712446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_iso_retraction.2408712446
Directory /workspace/23.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.2216197286
Short name T2461
Test name
Test status
Simulation time 325446037 ps
CPU time 1.05 seconds
Started Jul 26 05:11:19 PM PDT 24
Finished Jul 26 05:11:20 PM PDT 24
Peak memory 206992 kb
Host smart-c415f5c7-9423-4291-b1fe-d577b033a8c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22161
97286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.2216197286
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.3744075221
Short name T705
Test name
Test status
Simulation time 23354917553 ps
CPU time 29.28 seconds
Started Jul 26 05:11:17 PM PDT 24
Finished Jul 26 05:11:47 PM PDT 24
Peak memory 207380 kb
Host smart-95dce2e0-76a9-4047-9664-43f43a72be78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37440
75221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.3744075221
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.1152863379
Short name T1811
Test name
Test status
Simulation time 3327482549 ps
CPU time 5.3 seconds
Started Jul 26 05:11:17 PM PDT 24
Finished Jul 26 05:11:22 PM PDT 24
Peak memory 207368 kb
Host smart-57531897-f3be-4a80-a2ae-0217fe992b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11528
63379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.1152863379
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.1866244311
Short name T105
Test name
Test status
Simulation time 6721915898 ps
CPU time 49.95 seconds
Started Jul 26 05:11:17 PM PDT 24
Finished Jul 26 05:12:08 PM PDT 24
Peak memory 215668 kb
Host smart-00aff26c-23d5-487e-9f94-68ded548f8c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18662
44311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.1866244311
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.3008858768
Short name T1115
Test name
Test status
Simulation time 4350752413 ps
CPU time 137.96 seconds
Started Jul 26 05:11:17 PM PDT 24
Finished Jul 26 05:13:36 PM PDT 24
Peak memory 215600 kb
Host smart-7f221e27-9d59-4bd7-9bd3-2d3c6713a2e9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3008858768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.3008858768
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.136688986
Short name T323
Test name
Test status
Simulation time 255219199 ps
CPU time 1.02 seconds
Started Jul 26 05:11:17 PM PDT 24
Finished Jul 26 05:11:18 PM PDT 24
Peak memory 207044 kb
Host smart-1e9723bd-1910-44e7-baa9-a778f5787771
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=136688986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.136688986
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.3297206565
Short name T434
Test name
Test status
Simulation time 190839017 ps
CPU time 0.99 seconds
Started Jul 26 05:11:16 PM PDT 24
Finished Jul 26 05:11:17 PM PDT 24
Peak memory 206320 kb
Host smart-caa45a3a-05ff-46aa-b183-2684e6dd7162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32972
06565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.3297206565
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.2010716178
Short name T1854
Test name
Test status
Simulation time 5850712918 ps
CPU time 48.15 seconds
Started Jul 26 05:11:19 PM PDT 24
Finished Jul 26 05:12:08 PM PDT 24
Peak memory 217220 kb
Host smart-b7160822-937b-414a-b5c7-72fab81dd7d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20107
16178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.2010716178
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.264539161
Short name T1964
Test name
Test status
Simulation time 3775964507 ps
CPU time 28.19 seconds
Started Jul 26 05:11:21 PM PDT 24
Finished Jul 26 05:11:49 PM PDT 24
Peak memory 216916 kb
Host smart-4a0726c7-1982-4742-b53f-5b39cb0bff61
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=264539161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.264539161
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.776868572
Short name T2792
Test name
Test status
Simulation time 169668844 ps
CPU time 0.95 seconds
Started Jul 26 05:11:17 PM PDT 24
Finished Jul 26 05:11:19 PM PDT 24
Peak memory 207104 kb
Host smart-04608ed7-561e-4797-9583-f7f102756b3e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=776868572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.776868572
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.3227615626
Short name T944
Test name
Test status
Simulation time 149055597 ps
CPU time 0.9 seconds
Started Jul 26 05:11:22 PM PDT 24
Finished Jul 26 05:11:23 PM PDT 24
Peak memory 207104 kb
Host smart-19e3633c-2949-4fb8-b136-ea180072c2c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32276
15626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.3227615626
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.925839915
Short name T410
Test name
Test status
Simulation time 204564390 ps
CPU time 0.93 seconds
Started Jul 26 05:11:16 PM PDT 24
Finished Jul 26 05:11:17 PM PDT 24
Peak memory 207016 kb
Host smart-775ff59c-c112-4f5e-bb2f-7b89d92ae174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92583
9915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.925839915
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.4268394814
Short name T1471
Test name
Test status
Simulation time 156987781 ps
CPU time 0.84 seconds
Started Jul 26 05:11:19 PM PDT 24
Finished Jul 26 05:11:20 PM PDT 24
Peak memory 207092 kb
Host smart-60b26a08-4fd2-42e1-97bf-bf4488498357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42683
94814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.4268394814
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.3945462728
Short name T2819
Test name
Test status
Simulation time 165643266 ps
CPU time 0.83 seconds
Started Jul 26 05:11:21 PM PDT 24
Finished Jul 26 05:11:22 PM PDT 24
Peak memory 207084 kb
Host smart-0e086b8c-5e1f-45c7-ac58-cb6f1da016e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39454
62728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.3945462728
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.2298388398
Short name T1145
Test name
Test status
Simulation time 151551787 ps
CPU time 0.9 seconds
Started Jul 26 05:11:16 PM PDT 24
Finished Jul 26 05:11:17 PM PDT 24
Peak memory 206972 kb
Host smart-d89a7f4a-8fde-4b3c-87f3-1453f21930ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22983
88398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.2298388398
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.598733308
Short name T2372
Test name
Test status
Simulation time 234346560 ps
CPU time 1.02 seconds
Started Jul 26 05:11:17 PM PDT 24
Finished Jul 26 05:11:19 PM PDT 24
Peak memory 207080 kb
Host smart-0d71452e-bc72-4c4d-9a16-13694c393fc4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=598733308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.598733308
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.3691879127
Short name T1572
Test name
Test status
Simulation time 151833987 ps
CPU time 0.81 seconds
Started Jul 26 05:11:19 PM PDT 24
Finished Jul 26 05:11:20 PM PDT 24
Peak memory 207072 kb
Host smart-7a1450d3-baec-4061-a954-ce5945f1792b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36918
79127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.3691879127
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2755737456
Short name T2724
Test name
Test status
Simulation time 43530423 ps
CPU time 0.76 seconds
Started Jul 26 05:11:18 PM PDT 24
Finished Jul 26 05:11:19 PM PDT 24
Peak memory 207024 kb
Host smart-44c57721-cfe0-459a-9e19-c15505f6e7bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27557
37456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2755737456
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.3597683965
Short name T1633
Test name
Test status
Simulation time 12696581347 ps
CPU time 35.46 seconds
Started Jul 26 05:11:18 PM PDT 24
Finished Jul 26 05:11:53 PM PDT 24
Peak memory 215572 kb
Host smart-36cd5cd2-f46c-4edf-87a3-82a84820a20d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35976
83965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.3597683965
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.850228752
Short name T2683
Test name
Test status
Simulation time 162472671 ps
CPU time 0.86 seconds
Started Jul 26 05:11:17 PM PDT 24
Finished Jul 26 05:11:18 PM PDT 24
Peak memory 206936 kb
Host smart-c7abd034-0561-468a-9833-4b1dd96f9464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85022
8752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.850228752
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.1171909226
Short name T1103
Test name
Test status
Simulation time 232569772 ps
CPU time 1.13 seconds
Started Jul 26 05:11:16 PM PDT 24
Finished Jul 26 05:11:17 PM PDT 24
Peak memory 206980 kb
Host smart-c5f95a18-7621-444e-a861-ae943de85a42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11719
09226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.1171909226
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.2279058189
Short name T364
Test name
Test status
Simulation time 158144740 ps
CPU time 0.87 seconds
Started Jul 26 05:11:17 PM PDT 24
Finished Jul 26 05:11:18 PM PDT 24
Peak memory 207056 kb
Host smart-c42a5a8c-2b49-4475-86bc-67e1c0f73224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22790
58189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.2279058189
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.1387382675
Short name T1670
Test name
Test status
Simulation time 194057936 ps
CPU time 0.96 seconds
Started Jul 26 05:11:17 PM PDT 24
Finished Jul 26 05:11:18 PM PDT 24
Peak memory 207124 kb
Host smart-bd1b379a-a17f-4f0e-bdea-b8e3b5a31d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13873
82675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.1387382675
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.495486362
Short name T1241
Test name
Test status
Simulation time 197140628 ps
CPU time 0.83 seconds
Started Jul 26 05:11:17 PM PDT 24
Finished Jul 26 05:11:18 PM PDT 24
Peak memory 207088 kb
Host smart-03f2416e-89f2-4034-976f-cd1fff9f39ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49548
6362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.495486362
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.260276190
Short name T330
Test name
Test status
Simulation time 158001283 ps
CPU time 0.89 seconds
Started Jul 26 05:11:22 PM PDT 24
Finished Jul 26 05:11:23 PM PDT 24
Peak memory 207068 kb
Host smart-e3928d73-df41-4fad-b3ca-0ca84f26b30b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26027
6190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.260276190
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.1917155192
Short name T2250
Test name
Test status
Simulation time 208056645 ps
CPU time 0.95 seconds
Started Jul 26 05:11:16 PM PDT 24
Finished Jul 26 05:11:17 PM PDT 24
Peak memory 207052 kb
Host smart-1d85d8c9-8e4c-4c47-9f68-9cb165744059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19171
55192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.1917155192
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.2336297171
Short name T1772
Test name
Test status
Simulation time 231123448 ps
CPU time 1.01 seconds
Started Jul 26 05:11:27 PM PDT 24
Finished Jul 26 05:11:28 PM PDT 24
Peak memory 207072 kb
Host smart-e9056857-6d32-40a0-b052-6235f6b69293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23362
97171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.2336297171
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.3092080591
Short name T2237
Test name
Test status
Simulation time 5483189609 ps
CPU time 42.03 seconds
Started Jul 26 05:11:26 PM PDT 24
Finished Jul 26 05:12:09 PM PDT 24
Peak memory 215492 kb
Host smart-53ae2de1-02ec-4b68-ae0e-9392b03ab500
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3092080591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.3092080591
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.694395444
Short name T1951
Test name
Test status
Simulation time 152928671 ps
CPU time 0.9 seconds
Started Jul 26 05:11:25 PM PDT 24
Finished Jul 26 05:11:26 PM PDT 24
Peak memory 206988 kb
Host smart-126cd4bd-434e-4a6f-922c-44f052cbe32c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69439
5444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.694395444
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.2995104759
Short name T2010
Test name
Test status
Simulation time 163434248 ps
CPU time 0.86 seconds
Started Jul 26 05:11:27 PM PDT 24
Finished Jul 26 05:11:28 PM PDT 24
Peak memory 207012 kb
Host smart-bcb17778-3dc1-458f-85ae-0d07b11f35c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29951
04759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.2995104759
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.1914615751
Short name T2430
Test name
Test status
Simulation time 248944035 ps
CPU time 0.98 seconds
Started Jul 26 05:11:27 PM PDT 24
Finished Jul 26 05:11:28 PM PDT 24
Peak memory 206992 kb
Host smart-cdfb10b0-bf4f-427b-b682-db8309eda623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19146
15751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.1914615751
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.465125274
Short name T448
Test name
Test status
Simulation time 5316318417 ps
CPU time 159.65 seconds
Started Jul 26 05:11:25 PM PDT 24
Finished Jul 26 05:14:05 PM PDT 24
Peak memory 215432 kb
Host smart-abd488f6-36aa-4879-a023-a099d873e488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46512
5274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.465125274
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_timeout_missing_host_handshake.1359211701
Short name T1468
Test name
Test status
Simulation time 598767104 ps
CPU time 5.08 seconds
Started Jul 26 05:11:18 PM PDT 24
Finished Jul 26 05:11:23 PM PDT 24
Peak memory 207324 kb
Host smart-5a3faca5-541c-422b-90ee-7c4a4b79c75a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359211701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_timeout_missing_hos
t_handshake.1359211701
Directory /workspace/23.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.4258542650
Short name T2104
Test name
Test status
Simulation time 42635779 ps
CPU time 0.67 seconds
Started Jul 26 05:11:37 PM PDT 24
Finished Jul 26 05:11:37 PM PDT 24
Peak memory 207096 kb
Host smart-058cd2bc-d22d-41f6-9ba6-99f04788fca9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4258542650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.4258542650
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.1943819925
Short name T2108
Test name
Test status
Simulation time 3798594250 ps
CPU time 5.77 seconds
Started Jul 26 05:11:28 PM PDT 24
Finished Jul 26 05:11:34 PM PDT 24
Peak memory 207140 kb
Host smart-0a26454c-7240-4472-9829-9cb39368654d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943819925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_a
on_wake_disconnect.1943819925
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.3183307207
Short name T216
Test name
Test status
Simulation time 13388030517 ps
CPU time 17.95 seconds
Started Jul 26 05:11:28 PM PDT 24
Finished Jul 26 05:11:46 PM PDT 24
Peak memory 207356 kb
Host smart-450741ba-a41d-4835-8b67-82ba6c3ee12d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183307207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.3183307207
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.1611309773
Short name T716
Test name
Test status
Simulation time 23487131676 ps
CPU time 28.98 seconds
Started Jul 26 05:11:26 PM PDT 24
Finished Jul 26 05:11:55 PM PDT 24
Peak memory 207308 kb
Host smart-9824d035-562d-4192-b909-a5667572db0f
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611309773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_a
on_wake_resume.1611309773
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.3940101378
Short name T1307
Test name
Test status
Simulation time 184530720 ps
CPU time 0.91 seconds
Started Jul 26 05:11:26 PM PDT 24
Finished Jul 26 05:11:27 PM PDT 24
Peak memory 207060 kb
Host smart-0d8ac7de-4ecc-459b-95e4-94a2510d0ca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39401
01378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.3940101378
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.618539663
Short name T2850
Test name
Test status
Simulation time 356450819 ps
CPU time 1.3 seconds
Started Jul 26 05:11:24 PM PDT 24
Finished Jul 26 05:11:26 PM PDT 24
Peak memory 207148 kb
Host smart-56991d8d-96cb-4775-a733-c9be02b9b206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61853
9663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.618539663
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.641500043
Short name T684
Test name
Test status
Simulation time 550385397 ps
CPU time 1.61 seconds
Started Jul 26 05:11:27 PM PDT 24
Finished Jul 26 05:11:29 PM PDT 24
Peak memory 207012 kb
Host smart-cca222fe-3e5a-4505-ad06-ac9f8a0a5b9b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=641500043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.641500043
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.3333551965
Short name T894
Test name
Test status
Simulation time 20772228436 ps
CPU time 42.92 seconds
Started Jul 26 05:11:26 PM PDT 24
Finished Jul 26 05:12:10 PM PDT 24
Peak memory 207364 kb
Host smart-1232a98e-cfb8-47da-ad11-2c25410bb32b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33335
51965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.3333551965
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_device_timeout.4005310235
Short name T2330
Test name
Test status
Simulation time 6140733536 ps
CPU time 42.66 seconds
Started Jul 26 05:11:26 PM PDT 24
Finished Jul 26 05:12:09 PM PDT 24
Peak memory 207256 kb
Host smart-93b091f0-1973-401b-856d-b4508788a6cb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005310235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_timeout.4005310235
Directory /workspace/24.usbdev_device_timeout/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.954449977
Short name T3
Test name
Test status
Simulation time 376993526 ps
CPU time 1.49 seconds
Started Jul 26 05:11:25 PM PDT 24
Finished Jul 26 05:11:27 PM PDT 24
Peak memory 206948 kb
Host smart-5936d34b-6854-42e0-a1fd-8467e9bae216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95444
9977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.954449977
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.3271811162
Short name T763
Test name
Test status
Simulation time 147896944 ps
CPU time 0.81 seconds
Started Jul 26 05:11:26 PM PDT 24
Finished Jul 26 05:11:27 PM PDT 24
Peak memory 206992 kb
Host smart-0592af6c-9f3f-4611-97bd-6b14297ee04d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32718
11162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.3271811162
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.2317563597
Short name T1784
Test name
Test status
Simulation time 45267317 ps
CPU time 0.7 seconds
Started Jul 26 05:11:27 PM PDT 24
Finished Jul 26 05:11:28 PM PDT 24
Peak memory 207068 kb
Host smart-36bf0727-994e-49ef-81b7-aa8ccb8bee39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23175
63597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.2317563597
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.906051270
Short name T2566
Test name
Test status
Simulation time 723771099 ps
CPU time 2.21 seconds
Started Jul 26 05:11:26 PM PDT 24
Finished Jul 26 05:11:28 PM PDT 24
Peak memory 207280 kb
Host smart-bea7c909-e5fc-4332-9226-5181e57a0fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90605
1270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.906051270
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.4095594456
Short name T480
Test name
Test status
Simulation time 161866329 ps
CPU time 1.47 seconds
Started Jul 26 05:11:29 PM PDT 24
Finished Jul 26 05:11:30 PM PDT 24
Peak memory 207308 kb
Host smart-d7be8ded-1e92-40b8-a228-db129b9db7e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40955
94456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.4095594456
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.2686949309
Short name T826
Test name
Test status
Simulation time 176483947 ps
CPU time 0.89 seconds
Started Jul 26 05:11:27 PM PDT 24
Finished Jul 26 05:11:28 PM PDT 24
Peak memory 207048 kb
Host smart-e6ed977d-1af5-4573-9163-5d35e4ae6249
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2686949309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.2686949309
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.1729186544
Short name T433
Test name
Test status
Simulation time 151755466 ps
CPU time 0.84 seconds
Started Jul 26 05:11:29 PM PDT 24
Finished Jul 26 05:11:30 PM PDT 24
Peak memory 207072 kb
Host smart-2e11fe9d-6b46-4154-bcac-7d8960ec15e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17291
86544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.1729186544
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.449242149
Short name T1900
Test name
Test status
Simulation time 249474843 ps
CPU time 1.01 seconds
Started Jul 26 05:11:27 PM PDT 24
Finished Jul 26 05:11:28 PM PDT 24
Peak memory 207156 kb
Host smart-a54faeed-93ae-45fe-90e6-c7b3b749935e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44924
2149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.449242149
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.621540234
Short name T5
Test name
Test status
Simulation time 7571080124 ps
CPU time 230.8 seconds
Started Jul 26 05:11:31 PM PDT 24
Finished Jul 26 05:15:22 PM PDT 24
Peak memory 215588 kb
Host smart-2700a9ce-cf00-417b-bf37-48b5dff1fc8f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=621540234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.621540234
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_iso_retraction.4041018913
Short name T1991
Test name
Test status
Simulation time 9240996311 ps
CPU time 119.78 seconds
Started Jul 26 05:11:28 PM PDT 24
Finished Jul 26 05:13:28 PM PDT 24
Peak memory 207376 kb
Host smart-5d5cce6c-1ca7-431a-8fde-f8734cffe25f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4041018913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_iso_retraction.4041018913
Directory /workspace/24.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.366035344
Short name T1901
Test name
Test status
Simulation time 217066557 ps
CPU time 0.96 seconds
Started Jul 26 05:11:26 PM PDT 24
Finished Jul 26 05:11:27 PM PDT 24
Peak memory 207064 kb
Host smart-271081d8-618f-44d9-a217-8e060458b439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36603
5344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.366035344
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.1280110270
Short name T633
Test name
Test status
Simulation time 23326526068 ps
CPU time 26.98 seconds
Started Jul 26 05:11:25 PM PDT 24
Finished Jul 26 05:11:52 PM PDT 24
Peak memory 207224 kb
Host smart-337d32ae-4162-4788-8350-81e98f94862c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12801
10270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.1280110270
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.2883605136
Short name T2863
Test name
Test status
Simulation time 3309782093 ps
CPU time 4.95 seconds
Started Jul 26 05:11:26 PM PDT 24
Finished Jul 26 05:11:31 PM PDT 24
Peak memory 207348 kb
Host smart-818497ee-14d7-41aa-8183-c8d31148ac9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28836
05136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.2883605136
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.4035859373
Short name T2083
Test name
Test status
Simulation time 6501717259 ps
CPU time 48.96 seconds
Started Jul 26 05:11:28 PM PDT 24
Finished Jul 26 05:12:17 PM PDT 24
Peak memory 217388 kb
Host smart-1d92e92a-654a-41f1-9f8e-c7009d5505b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40358
59373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.4035859373
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.4287324437
Short name T1167
Test name
Test status
Simulation time 3877097267 ps
CPU time 123.88 seconds
Started Jul 26 05:11:26 PM PDT 24
Finished Jul 26 05:13:30 PM PDT 24
Peak memory 215492 kb
Host smart-b177d76f-4f87-4b45-86ad-e2e629fe0349
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4287324437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.4287324437
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.711811448
Short name T2484
Test name
Test status
Simulation time 257332339 ps
CPU time 1.05 seconds
Started Jul 26 05:11:25 PM PDT 24
Finished Jul 26 05:11:27 PM PDT 24
Peak memory 207036 kb
Host smart-76978989-9ab8-45f3-899b-836a4e29e8c2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=711811448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.711811448
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.3030640336
Short name T1206
Test name
Test status
Simulation time 194288848 ps
CPU time 0.94 seconds
Started Jul 26 05:11:29 PM PDT 24
Finished Jul 26 05:11:31 PM PDT 24
Peak memory 207096 kb
Host smart-cd887744-e3e5-43a3-b811-2d353c0da00d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30306
40336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.3030640336
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.120303133
Short name T2310
Test name
Test status
Simulation time 6345026247 ps
CPU time 192.96 seconds
Started Jul 26 05:11:25 PM PDT 24
Finished Jul 26 05:14:38 PM PDT 24
Peak memory 215508 kb
Host smart-ca8f4f90-da7b-4e9a-affe-6d2ee43f3ef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12030
3133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.120303133
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.553442765
Short name T1963
Test name
Test status
Simulation time 5925249392 ps
CPU time 46.27 seconds
Started Jul 26 05:11:31 PM PDT 24
Finished Jul 26 05:12:17 PM PDT 24
Peak memory 207256 kb
Host smart-72735c4e-bb3c-47ea-9f6a-6ee9a3420ee0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=553442765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.553442765
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.3753647875
Short name T1164
Test name
Test status
Simulation time 195553311 ps
CPU time 0.9 seconds
Started Jul 26 05:11:40 PM PDT 24
Finished Jul 26 05:11:41 PM PDT 24
Peak memory 207140 kb
Host smart-079649c1-dc77-4974-b527-8bd8673b00b4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3753647875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.3753647875
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.535478880
Short name T1292
Test name
Test status
Simulation time 160112643 ps
CPU time 0.84 seconds
Started Jul 26 05:11:36 PM PDT 24
Finished Jul 26 05:11:37 PM PDT 24
Peak memory 207076 kb
Host smart-ac02bc38-1e0f-400c-825b-c55d73956410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53547
8880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.535478880
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.2476703576
Short name T1230
Test name
Test status
Simulation time 158467825 ps
CPU time 0.93 seconds
Started Jul 26 05:11:33 PM PDT 24
Finished Jul 26 05:11:34 PM PDT 24
Peak memory 207044 kb
Host smart-a8099465-5218-498c-8efe-ff1f539f7040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24767
03576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.2476703576
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.4023676442
Short name T2613
Test name
Test status
Simulation time 164789920 ps
CPU time 0.85 seconds
Started Jul 26 05:11:37 PM PDT 24
Finished Jul 26 05:11:38 PM PDT 24
Peak memory 207124 kb
Host smart-ec23b59e-742e-4765-80b6-d66a3be8bdd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40236
76442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.4023676442
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.217628812
Short name T2539
Test name
Test status
Simulation time 178587919 ps
CPU time 0.88 seconds
Started Jul 26 05:11:38 PM PDT 24
Finished Jul 26 05:11:39 PM PDT 24
Peak memory 207100 kb
Host smart-9980f668-9cd5-4912-82c7-ee56e5277be4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21762
8812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.217628812
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.2287722885
Short name T152
Test name
Test status
Simulation time 152114454 ps
CPU time 0.86 seconds
Started Jul 26 05:11:35 PM PDT 24
Finished Jul 26 05:11:36 PM PDT 24
Peak memory 207048 kb
Host smart-21c48cf8-e30c-4c17-9bc7-e2666ef9bc33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22877
22885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.2287722885
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.1624798725
Short name T1526
Test name
Test status
Simulation time 205250499 ps
CPU time 0.99 seconds
Started Jul 26 05:11:35 PM PDT 24
Finished Jul 26 05:11:36 PM PDT 24
Peak memory 207124 kb
Host smart-b7be6f44-b719-4307-848e-dbca3f9a6353
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1624798725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.1624798725
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.1515799566
Short name T987
Test name
Test status
Simulation time 140675213 ps
CPU time 0.84 seconds
Started Jul 26 05:11:36 PM PDT 24
Finished Jul 26 05:11:36 PM PDT 24
Peak memory 206992 kb
Host smart-fb850440-1543-4fcc-b97d-3b9f749e88b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15157
99566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.1515799566
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.951113420
Short name T388
Test name
Test status
Simulation time 72040874 ps
CPU time 0.71 seconds
Started Jul 26 05:11:38 PM PDT 24
Finished Jul 26 05:11:39 PM PDT 24
Peak memory 207012 kb
Host smart-c8c6bf4d-7f6d-4b93-9169-bd7d54992fe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95111
3420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.951113420
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.2886120079
Short name T2169
Test name
Test status
Simulation time 20808972177 ps
CPU time 50.39 seconds
Started Jul 26 05:11:38 PM PDT 24
Finished Jul 26 05:12:29 PM PDT 24
Peak memory 215564 kb
Host smart-d12176ca-0906-4fd7-8cdd-ca178102ac83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28861
20079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.2886120079
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.3420079040
Short name T764
Test name
Test status
Simulation time 183415560 ps
CPU time 0.91 seconds
Started Jul 26 05:11:36 PM PDT 24
Finished Jul 26 05:11:37 PM PDT 24
Peak memory 207100 kb
Host smart-545e0344-08fe-4363-81d5-1986c16b34af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34200
79040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.3420079040
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.3748806426
Short name T2219
Test name
Test status
Simulation time 190264932 ps
CPU time 0.98 seconds
Started Jul 26 05:11:35 PM PDT 24
Finished Jul 26 05:11:36 PM PDT 24
Peak memory 207100 kb
Host smart-d7fd722b-96cd-4730-af38-fdb8db9bb417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37488
06426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.3748806426
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.1918379274
Short name T1311
Test name
Test status
Simulation time 235237750 ps
CPU time 0.98 seconds
Started Jul 26 05:11:36 PM PDT 24
Finished Jul 26 05:11:37 PM PDT 24
Peak memory 207044 kb
Host smart-0a89950a-0f80-4381-9004-aa58cebffdf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19183
79274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.1918379274
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.2983715330
Short name T914
Test name
Test status
Simulation time 155008165 ps
CPU time 0.86 seconds
Started Jul 26 05:11:36 PM PDT 24
Finished Jul 26 05:11:37 PM PDT 24
Peak memory 207140 kb
Host smart-6e98d5c3-9178-4c9b-a3ed-134cd417f8ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29837
15330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.2983715330
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.3724836090
Short name T1373
Test name
Test status
Simulation time 187038286 ps
CPU time 0.92 seconds
Started Jul 26 05:11:37 PM PDT 24
Finished Jul 26 05:11:38 PM PDT 24
Peak memory 207088 kb
Host smart-f4155cdf-855f-4d16-bee0-cd8854bac8ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37248
36090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.3724836090
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.3678741334
Short name T1523
Test name
Test status
Simulation time 178839204 ps
CPU time 0.92 seconds
Started Jul 26 05:11:37 PM PDT 24
Finished Jul 26 05:11:38 PM PDT 24
Peak memory 206992 kb
Host smart-17701c9b-c3f7-45f4-9e96-0dc5d4fb284f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36787
41334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.3678741334
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.1902029660
Short name T1652
Test name
Test status
Simulation time 153708977 ps
CPU time 0.85 seconds
Started Jul 26 05:11:34 PM PDT 24
Finished Jul 26 05:11:36 PM PDT 24
Peak memory 206984 kb
Host smart-7617476f-5025-4d58-b1b4-b3b9c4cdc9d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19020
29660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.1902029660
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.1424572274
Short name T154
Test name
Test status
Simulation time 232220431 ps
CPU time 1.02 seconds
Started Jul 26 05:11:37 PM PDT 24
Finished Jul 26 05:11:38 PM PDT 24
Peak memory 207112 kb
Host smart-98c6659c-b39c-4c65-8693-beeb6414ec09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14245
72274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.1424572274
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.3875074022
Short name T2466
Test name
Test status
Simulation time 6606395369 ps
CPU time 75.64 seconds
Started Jul 26 05:11:38 PM PDT 24
Finished Jul 26 05:12:54 PM PDT 24
Peak memory 216728 kb
Host smart-04a14326-8cad-446e-9e04-1474712da8ab
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3875074022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.3875074022
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.3549938527
Short name T2180
Test name
Test status
Simulation time 248350259 ps
CPU time 0.95 seconds
Started Jul 26 05:11:37 PM PDT 24
Finished Jul 26 05:11:38 PM PDT 24
Peak memory 207028 kb
Host smart-7c286363-0f1f-4e63-913f-d00ba8bf5612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35499
38527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.3549938527
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.1608642113
Short name T688
Test name
Test status
Simulation time 204636737 ps
CPU time 0.96 seconds
Started Jul 26 05:11:36 PM PDT 24
Finished Jul 26 05:11:37 PM PDT 24
Peak memory 207128 kb
Host smart-957eb279-e8e9-425e-8316-97c421f8c3e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16086
42113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.1608642113
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.1102179225
Short name T471
Test name
Test status
Simulation time 383474569 ps
CPU time 1.3 seconds
Started Jul 26 05:11:36 PM PDT 24
Finished Jul 26 05:11:37 PM PDT 24
Peak memory 207100 kb
Host smart-f8429e56-7fd3-4267-86ea-41e010d425a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11021
79225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.1102179225
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.1363248932
Short name T670
Test name
Test status
Simulation time 3780762968 ps
CPU time 45.06 seconds
Started Jul 26 05:11:38 PM PDT 24
Finished Jul 26 05:12:23 PM PDT 24
Peak memory 216748 kb
Host smart-160a9dcd-23da-448f-9257-1d9da9b8eae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13632
48932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.1363248932
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_timeout_missing_host_handshake.2219285472
Short name T1505
Test name
Test status
Simulation time 1289133057 ps
CPU time 29.55 seconds
Started Jul 26 05:11:31 PM PDT 24
Finished Jul 26 05:12:00 PM PDT 24
Peak memory 207284 kb
Host smart-5599fe28-725d-4665-9a7f-20318fc666c2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219285472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_timeout_missing_hos
t_handshake.2219285472
Directory /workspace/24.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.1762932164
Short name T1414
Test name
Test status
Simulation time 44197147 ps
CPU time 0.68 seconds
Started Jul 26 05:11:56 PM PDT 24
Finished Jul 26 05:11:56 PM PDT 24
Peak memory 207124 kb
Host smart-f9f806d2-b876-49d8-bdef-621ae7528939
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1762932164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.1762932164
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.1356226396
Short name T1637
Test name
Test status
Simulation time 4243485105 ps
CPU time 5.83 seconds
Started Jul 26 05:11:39 PM PDT 24
Finished Jul 26 05:11:45 PM PDT 24
Peak memory 207408 kb
Host smart-7632b578-ae60-4c75-9f6d-55c38ea47f0a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356226396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_a
on_wake_disconnect.1356226396
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.375954030
Short name T1435
Test name
Test status
Simulation time 13412986438 ps
CPU time 14.8 seconds
Started Jul 26 05:11:36 PM PDT 24
Finished Jul 26 05:11:51 PM PDT 24
Peak memory 207400 kb
Host smart-c612a0e3-a84c-407c-9b6a-3124b579216a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=375954030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.375954030
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.2920865023
Short name T14
Test name
Test status
Simulation time 23371432701 ps
CPU time 26.43 seconds
Started Jul 26 05:11:38 PM PDT 24
Finished Jul 26 05:12:05 PM PDT 24
Peak memory 207244 kb
Host smart-5584adce-4caf-4273-9e9a-704b7c53e3fc
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920865023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_a
on_wake_resume.2920865023
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.2811931989
Short name T2325
Test name
Test status
Simulation time 150214734 ps
CPU time 0.92 seconds
Started Jul 26 05:11:37 PM PDT 24
Finished Jul 26 05:11:38 PM PDT 24
Peak memory 207092 kb
Host smart-d7a832f4-c4db-478a-9415-6432b94c2447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28119
31989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.2811931989
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.2913512299
Short name T2710
Test name
Test status
Simulation time 232906106 ps
CPU time 0.96 seconds
Started Jul 26 05:11:38 PM PDT 24
Finished Jul 26 05:11:40 PM PDT 24
Peak memory 207092 kb
Host smart-5dc6f3df-7a31-4ff7-aa6d-d15470644028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29135
12299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.2913512299
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.3457528251
Short name T345
Test name
Test status
Simulation time 307209000 ps
CPU time 1.31 seconds
Started Jul 26 05:11:38 PM PDT 24
Finished Jul 26 05:11:40 PM PDT 24
Peak memory 207096 kb
Host smart-a9323e08-84d5-49b2-8aa5-b3964f11e5dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34575
28251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.3457528251
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.3506676825
Short name T463
Test name
Test status
Simulation time 909681165 ps
CPU time 2.39 seconds
Started Jul 26 05:11:40 PM PDT 24
Finished Jul 26 05:11:43 PM PDT 24
Peak memory 207264 kb
Host smart-f48d56b4-a09b-4b9c-859b-e3ecfe1e97cb
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3506676825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.3506676825
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.2045472727
Short name T2258
Test name
Test status
Simulation time 13649641166 ps
CPU time 32.18 seconds
Started Jul 26 05:11:39 PM PDT 24
Finished Jul 26 05:12:11 PM PDT 24
Peak memory 207264 kb
Host smart-4045b894-2235-440d-ab9f-eb45e4be5507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20454
72727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.2045472727
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_device_timeout.3034639376
Short name T466
Test name
Test status
Simulation time 5662128986 ps
CPU time 48.88 seconds
Started Jul 26 05:11:35 PM PDT 24
Finished Jul 26 05:12:24 PM PDT 24
Peak memory 207344 kb
Host smart-1ef25dd6-1f98-4f26-ab64-9ad895004860
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034639376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_timeout.3034639376
Directory /workspace/25.usbdev_device_timeout/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.1959976436
Short name T2649
Test name
Test status
Simulation time 434550510 ps
CPU time 1.53 seconds
Started Jul 26 05:11:38 PM PDT 24
Finished Jul 26 05:11:40 PM PDT 24
Peak memory 206992 kb
Host smart-d8d57870-9522-46b3-be38-cf5748c23c1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19599
76436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.1959976436
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.3949249092
Short name T2827
Test name
Test status
Simulation time 145034329 ps
CPU time 0.84 seconds
Started Jul 26 05:11:36 PM PDT 24
Finished Jul 26 05:11:37 PM PDT 24
Peak memory 207096 kb
Host smart-35b5a138-e282-413c-b534-3b5289b09967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39492
49092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.3949249092
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.1461198304
Short name T2434
Test name
Test status
Simulation time 41715111 ps
CPU time 0.71 seconds
Started Jul 26 05:11:38 PM PDT 24
Finished Jul 26 05:11:39 PM PDT 24
Peak memory 206976 kb
Host smart-9c208be0-7f9b-4868-b40e-3a971f40cf6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14611
98304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.1461198304
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.2895485035
Short name T1771
Test name
Test status
Simulation time 980256044 ps
CPU time 2.45 seconds
Started Jul 26 05:11:39 PM PDT 24
Finished Jul 26 05:11:42 PM PDT 24
Peak memory 207244 kb
Host smart-b3196133-56cb-4c41-8946-1a9af55df7f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28954
85035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.2895485035
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.1880390300
Short name T2584
Test name
Test status
Simulation time 266960472 ps
CPU time 1.97 seconds
Started Jul 26 05:11:38 PM PDT 24
Finished Jul 26 05:11:41 PM PDT 24
Peak memory 207288 kb
Host smart-2acad12e-20f8-4a3d-a049-5e54b8f1e710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18803
90300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.1880390300
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.417555148
Short name T1013
Test name
Test status
Simulation time 176876631 ps
CPU time 0.97 seconds
Started Jul 26 05:11:38 PM PDT 24
Finished Jul 26 05:11:39 PM PDT 24
Peak memory 207068 kb
Host smart-35c056e6-e1cb-4c88-a2c3-9d8b78ef666b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=417555148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.417555148
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.3378176559
Short name T335
Test name
Test status
Simulation time 146522900 ps
CPU time 0.82 seconds
Started Jul 26 05:11:37 PM PDT 24
Finished Jul 26 05:11:38 PM PDT 24
Peak memory 207052 kb
Host smart-8364a034-38b2-4216-b81e-f4bd648854c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33781
76559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.3378176559
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.3578695720
Short name T693
Test name
Test status
Simulation time 199338628 ps
CPU time 0.91 seconds
Started Jul 26 05:11:38 PM PDT 24
Finished Jul 26 05:11:39 PM PDT 24
Peak memory 207020 kb
Host smart-d661c130-61e8-4d60-b26f-5c39b53b08d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35786
95720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.3578695720
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.808734479
Short name T2065
Test name
Test status
Simulation time 8290318774 ps
CPU time 61.24 seconds
Started Jul 26 05:11:36 PM PDT 24
Finished Jul 26 05:12:37 PM PDT 24
Peak memory 216824 kb
Host smart-054c341f-c2e5-46ea-b6ab-af56f8fcf4cd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=808734479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.808734479
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_iso_retraction.1142777472
Short name T104
Test name
Test status
Simulation time 8662592207 ps
CPU time 64.32 seconds
Started Jul 26 05:11:48 PM PDT 24
Finished Jul 26 05:12:52 PM PDT 24
Peak memory 207340 kb
Host smart-39a0b9c4-4341-4d29-9c36-8cabc2fdf02a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1142777472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_iso_retraction.1142777472
Directory /workspace/25.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.3795465972
Short name T1377
Test name
Test status
Simulation time 185257408 ps
CPU time 0.9 seconds
Started Jul 26 05:11:57 PM PDT 24
Finished Jul 26 05:11:58 PM PDT 24
Peak memory 207020 kb
Host smart-3b40a1db-890a-4d2d-aeea-161db8d91677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37954
65972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.3795465972
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.536961237
Short name T658
Test name
Test status
Simulation time 23328936381 ps
CPU time 33.57 seconds
Started Jul 26 05:11:46 PM PDT 24
Finished Jul 26 05:12:20 PM PDT 24
Peak memory 207240 kb
Host smart-5fa94894-af00-4806-96a2-a2912cbccfed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53696
1237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.536961237
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.1787519348
Short name T1574
Test name
Test status
Simulation time 3259150312 ps
CPU time 5.09 seconds
Started Jul 26 05:11:54 PM PDT 24
Finished Jul 26 05:12:00 PM PDT 24
Peak memory 207348 kb
Host smart-c0007be2-6690-4a2a-a527-69e2d20e7b7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17875
19348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.1787519348
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.4080202488
Short name T586
Test name
Test status
Simulation time 7175747119 ps
CPU time 53.68 seconds
Started Jul 26 05:11:50 PM PDT 24
Finished Jul 26 05:12:44 PM PDT 24
Peak memory 223768 kb
Host smart-738f3f8d-4a97-46fe-a4b9-2dda5687187b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40802
02488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.4080202488
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.22269437
Short name T1204
Test name
Test status
Simulation time 5722513898 ps
CPU time 60.5 seconds
Started Jul 26 05:11:57 PM PDT 24
Finished Jul 26 05:12:58 PM PDT 24
Peak memory 216784 kb
Host smart-ac6d87f0-b276-47d1-ac48-feacd1a26415
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=22269437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.22269437
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.1652476739
Short name T1632
Test name
Test status
Simulation time 248991275 ps
CPU time 1.08 seconds
Started Jul 26 05:11:51 PM PDT 24
Finished Jul 26 05:11:52 PM PDT 24
Peak memory 207064 kb
Host smart-18403242-4374-469b-98ad-1d41b416aa3e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1652476739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.1652476739
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.3765163760
Short name T368
Test name
Test status
Simulation time 197126891 ps
CPU time 1.02 seconds
Started Jul 26 05:11:48 PM PDT 24
Finished Jul 26 05:11:49 PM PDT 24
Peak memory 207096 kb
Host smart-14590c73-093d-4d40-b954-a8908180b681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37651
63760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.3765163760
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.3105721840
Short name T452
Test name
Test status
Simulation time 6158576394 ps
CPU time 48 seconds
Started Jul 26 05:11:49 PM PDT 24
Finished Jul 26 05:12:37 PM PDT 24
Peak memory 216932 kb
Host smart-12381ce1-a295-4020-a90d-e81712d9cf46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31057
21840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.3105721840
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.1220601157
Short name T1346
Test name
Test status
Simulation time 6364023758 ps
CPU time 52.07 seconds
Started Jul 26 05:11:57 PM PDT 24
Finished Jul 26 05:12:50 PM PDT 24
Peak memory 207360 kb
Host smart-e20583ec-2d35-404b-b37d-9040cad57c20
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1220601157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.1220601157
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.129934658
Short name T2673
Test name
Test status
Simulation time 166635889 ps
CPU time 0.89 seconds
Started Jul 26 05:11:47 PM PDT 24
Finished Jul 26 05:11:48 PM PDT 24
Peak memory 207024 kb
Host smart-447b54c3-097d-4c04-a273-30352718d923
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=129934658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.129934658
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.4223878316
Short name T860
Test name
Test status
Simulation time 150763796 ps
CPU time 0.85 seconds
Started Jul 26 05:11:49 PM PDT 24
Finished Jul 26 05:11:50 PM PDT 24
Peak memory 207008 kb
Host smart-e2e21dcd-a3d9-48ea-9d4c-5698246f87aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42238
78316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.4223878316
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.4225597260
Short name T112
Test name
Test status
Simulation time 215807814 ps
CPU time 0.96 seconds
Started Jul 26 05:11:55 PM PDT 24
Finished Jul 26 05:11:56 PM PDT 24
Peak memory 207104 kb
Host smart-16ffb78c-9e44-47fa-aeab-bb438fb04f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42255
97260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.4225597260
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.169141544
Short name T2293
Test name
Test status
Simulation time 171079512 ps
CPU time 0.9 seconds
Started Jul 26 05:11:54 PM PDT 24
Finished Jul 26 05:11:55 PM PDT 24
Peak memory 207132 kb
Host smart-c03da70c-6752-4208-b480-86b9ed3b0424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16914
1544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.169141544
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.2520189520
Short name T549
Test name
Test status
Simulation time 246790873 ps
CPU time 0.99 seconds
Started Jul 26 05:11:58 PM PDT 24
Finished Jul 26 05:11:59 PM PDT 24
Peak memory 207084 kb
Host smart-8ed8e138-a460-4a28-b059-493b6e4e8b0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25201
89520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.2520189520
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.2512428876
Short name T2355
Test name
Test status
Simulation time 205373657 ps
CPU time 0.89 seconds
Started Jul 26 05:11:47 PM PDT 24
Finished Jul 26 05:11:48 PM PDT 24
Peak memory 207136 kb
Host smart-12ccd189-c7cd-40e6-826e-63818ce66655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25124
28876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.2512428876
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.2819074281
Short name T1780
Test name
Test status
Simulation time 165840232 ps
CPU time 0.92 seconds
Started Jul 26 05:11:55 PM PDT 24
Finished Jul 26 05:11:56 PM PDT 24
Peak memory 207124 kb
Host smart-f435cca2-53d0-4215-9aa0-360b413d6047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28190
74281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.2819074281
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.4089415238
Short name T2069
Test name
Test status
Simulation time 231798250 ps
CPU time 1.06 seconds
Started Jul 26 05:11:50 PM PDT 24
Finished Jul 26 05:11:52 PM PDT 24
Peak memory 207156 kb
Host smart-74e21025-cab8-49c9-8440-6d7b97760312
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4089415238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.4089415238
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.485053304
Short name T2447
Test name
Test status
Simulation time 154824918 ps
CPU time 0.86 seconds
Started Jul 26 05:11:48 PM PDT 24
Finished Jul 26 05:11:49 PM PDT 24
Peak memory 207092 kb
Host smart-d0c553bc-6461-4027-8938-2a98b37d4661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48505
3304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.485053304
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.2137098654
Short name T1295
Test name
Test status
Simulation time 36626898 ps
CPU time 0.68 seconds
Started Jul 26 05:12:00 PM PDT 24
Finished Jul 26 05:12:01 PM PDT 24
Peak memory 206988 kb
Host smart-6c92a81a-3eb6-4ca4-b46a-02226e9036a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21370
98654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.2137098654
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.2756272237
Short name T1551
Test name
Test status
Simulation time 13371291598 ps
CPU time 33.94 seconds
Started Jul 26 05:11:51 PM PDT 24
Finished Jul 26 05:12:25 PM PDT 24
Peak memory 223740 kb
Host smart-636480e8-61cc-4e49-9ccf-9cc9ff4f4179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27562
72237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.2756272237
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.3071424521
Short name T2837
Test name
Test status
Simulation time 243823322 ps
CPU time 1.02 seconds
Started Jul 26 05:11:58 PM PDT 24
Finished Jul 26 05:11:59 PM PDT 24
Peak memory 206992 kb
Host smart-eab06e85-cbfe-43f8-aebe-2fb7c6e613a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30714
24521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.3071424521
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.3979710484
Short name T2776
Test name
Test status
Simulation time 215355422 ps
CPU time 0.97 seconds
Started Jul 26 05:11:56 PM PDT 24
Finished Jul 26 05:11:57 PM PDT 24
Peak memory 207012 kb
Host smart-a1933813-aa2e-4012-aca1-8158b1c513b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39797
10484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.3979710484
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.317776901
Short name T1891
Test name
Test status
Simulation time 148205177 ps
CPU time 0.89 seconds
Started Jul 26 05:11:48 PM PDT 24
Finished Jul 26 05:11:49 PM PDT 24
Peak memory 206936 kb
Host smart-228ba86d-eb57-4d61-b667-bf90c93a00fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31777
6901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.317776901
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.4128510958
Short name T1056
Test name
Test status
Simulation time 143407067 ps
CPU time 0.84 seconds
Started Jul 26 05:11:48 PM PDT 24
Finished Jul 26 05:11:49 PM PDT 24
Peak memory 207000 kb
Host smart-9ee25f1b-ac5f-48bf-9bd9-07389a1a2232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41285
10958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.4128510958
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.4219953642
Short name T1981
Test name
Test status
Simulation time 175429146 ps
CPU time 0.87 seconds
Started Jul 26 05:11:49 PM PDT 24
Finished Jul 26 05:11:50 PM PDT 24
Peak memory 207100 kb
Host smart-0e68092d-21a7-4c0f-84e1-0d77a2c7802c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42199
53642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.4219953642
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.3914774522
Short name T1401
Test name
Test status
Simulation time 152348896 ps
CPU time 0.87 seconds
Started Jul 26 05:11:55 PM PDT 24
Finished Jul 26 05:11:56 PM PDT 24
Peak memory 207048 kb
Host smart-b7bb7ab1-db81-489a-9fba-39adcfc3a061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39147
74522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.3914774522
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.711373333
Short name T21
Test name
Test status
Simulation time 220757615 ps
CPU time 1.04 seconds
Started Jul 26 05:11:52 PM PDT 24
Finished Jul 26 05:11:53 PM PDT 24
Peak memory 207124 kb
Host smart-cc71b0cd-80aa-4cc1-a0bd-d54751199e64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71137
3333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.711373333
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.3251520830
Short name T2727
Test name
Test status
Simulation time 4569532328 ps
CPU time 35.82 seconds
Started Jul 26 05:11:56 PM PDT 24
Finished Jul 26 05:12:32 PM PDT 24
Peak memory 216784 kb
Host smart-e49388d3-4370-4617-b1e3-dedb260fc380
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3251520830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.3251520830
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.837337358
Short name T2492
Test name
Test status
Simulation time 186352494 ps
CPU time 0.95 seconds
Started Jul 26 05:11:57 PM PDT 24
Finished Jul 26 05:11:59 PM PDT 24
Peak memory 207128 kb
Host smart-1c7bbb23-3711-41e3-a13d-9c93150ea25f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83733
7358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.837337358
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.1419438305
Short name T1848
Test name
Test status
Simulation time 157310658 ps
CPU time 0.87 seconds
Started Jul 26 05:11:55 PM PDT 24
Finished Jul 26 05:11:56 PM PDT 24
Peak memory 207100 kb
Host smart-8d9b2caa-69cb-4e16-96f4-bb786895943b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14194
38305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.1419438305
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.1769889207
Short name T1795
Test name
Test status
Simulation time 518511405 ps
CPU time 1.55 seconds
Started Jul 26 05:11:57 PM PDT 24
Finished Jul 26 05:11:59 PM PDT 24
Peak memory 206992 kb
Host smart-4a4677cf-312f-4883-b148-420543894350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17698
89207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.1769889207
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.2160416570
Short name T1962
Test name
Test status
Simulation time 4125379106 ps
CPU time 45.1 seconds
Started Jul 26 05:11:59 PM PDT 24
Finished Jul 26 05:12:44 PM PDT 24
Peak memory 215588 kb
Host smart-d0882ce7-5900-443f-832e-c23a292af302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21604
16570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.2160416570
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_timeout_missing_host_handshake.3888275155
Short name T1941
Test name
Test status
Simulation time 1106220006 ps
CPU time 9.73 seconds
Started Jul 26 05:11:36 PM PDT 24
Finished Jul 26 05:11:46 PM PDT 24
Peak memory 207200 kb
Host smart-bf6fba13-0137-4620-b314-4c11fb620793
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888275155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_timeout_missing_hos
t_handshake.3888275155
Directory /workspace/25.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.981202783
Short name T35
Test name
Test status
Simulation time 55834140 ps
CPU time 0.71 seconds
Started Jul 26 05:12:06 PM PDT 24
Finished Jul 26 05:12:07 PM PDT 24
Peak memory 207168 kb
Host smart-0d6646ea-f584-4bfd-aa44-0a75b9433806
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=981202783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.981202783
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.1537086286
Short name T13
Test name
Test status
Simulation time 4165869342 ps
CPU time 5.79 seconds
Started Jul 26 05:11:50 PM PDT 24
Finished Jul 26 05:11:56 PM PDT 24
Peak memory 207408 kb
Host smart-34416dbd-b55d-458a-80a0-83c7f8eed3e6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537086286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_a
on_wake_disconnect.1537086286
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.2656922600
Short name T1636
Test name
Test status
Simulation time 13359970701 ps
CPU time 17.04 seconds
Started Jul 26 05:11:48 PM PDT 24
Finished Jul 26 05:12:05 PM PDT 24
Peak memory 207368 kb
Host smart-303b6442-ce16-4e01-9953-b7ec545e5e1b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656922600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.2656922600
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.4059201819
Short name T1683
Test name
Test status
Simulation time 23351142742 ps
CPU time 26.04 seconds
Started Jul 26 05:11:52 PM PDT 24
Finished Jul 26 05:12:19 PM PDT 24
Peak memory 207384 kb
Host smart-5d39bfcc-d3dd-4264-b252-2f3c560205f1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059201819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_a
on_wake_resume.4059201819
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.3720366481
Short name T2678
Test name
Test status
Simulation time 189591977 ps
CPU time 0.95 seconds
Started Jul 26 05:11:58 PM PDT 24
Finished Jul 26 05:11:59 PM PDT 24
Peak memory 207080 kb
Host smart-67a9108a-2cc6-40eb-b9d7-1b2bc1329137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37203
66481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.3720366481
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.1852157914
Short name T2035
Test name
Test status
Simulation time 156861998 ps
CPU time 0.91 seconds
Started Jul 26 05:12:03 PM PDT 24
Finished Jul 26 05:12:04 PM PDT 24
Peak memory 206948 kb
Host smart-ee7b0571-405a-441a-91d6-55be38641e2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18521
57914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.1852157914
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.1906693784
Short name T1735
Test name
Test status
Simulation time 296708474 ps
CPU time 1.16 seconds
Started Jul 26 05:11:53 PM PDT 24
Finished Jul 26 05:11:55 PM PDT 24
Peak memory 207096 kb
Host smart-f8152075-d0a2-47a2-93df-48056c3a5b4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19066
93784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.1906693784
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.2180413619
Short name T2799
Test name
Test status
Simulation time 1191817664 ps
CPU time 3.27 seconds
Started Jul 26 05:11:54 PM PDT 24
Finished Jul 26 05:11:58 PM PDT 24
Peak memory 207292 kb
Host smart-46cb95a6-7270-4f5a-a942-252edf9603e1
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2180413619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.2180413619
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.2409664866
Short name T2818
Test name
Test status
Simulation time 19408105966 ps
CPU time 38.4 seconds
Started Jul 26 05:11:50 PM PDT 24
Finished Jul 26 05:12:29 PM PDT 24
Peak memory 207352 kb
Host smart-32a7e2a9-fcff-4c44-8fd8-796bb2fcad8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24096
64866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.2409664866
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_device_timeout.3340721979
Short name T2100
Test name
Test status
Simulation time 483078014 ps
CPU time 8.23 seconds
Started Jul 26 05:11:58 PM PDT 24
Finished Jul 26 05:12:07 PM PDT 24
Peak memory 207260 kb
Host smart-7716f9a4-9b9a-48b1-95d7-dd11bf28e788
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340721979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_timeout.3340721979
Directory /workspace/26.usbdev_device_timeout/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.3629608012
Short name T901
Test name
Test status
Simulation time 352416775 ps
CPU time 1.41 seconds
Started Jul 26 05:11:53 PM PDT 24
Finished Jul 26 05:11:54 PM PDT 24
Peak memory 207088 kb
Host smart-bdc3ba1e-6322-43bb-9ab0-e0b72be7816f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36296
08012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.3629608012
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.3971464747
Short name T1364
Test name
Test status
Simulation time 141765462 ps
CPU time 0.84 seconds
Started Jul 26 05:11:52 PM PDT 24
Finished Jul 26 05:11:53 PM PDT 24
Peak memory 206960 kb
Host smart-c1e07bb2-ecdc-468e-875e-ba2836b391ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39714
64747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.3971464747
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.2846669854
Short name T2567
Test name
Test status
Simulation time 41768203 ps
CPU time 0.73 seconds
Started Jul 26 05:11:57 PM PDT 24
Finished Jul 26 05:11:58 PM PDT 24
Peak memory 207008 kb
Host smart-386d5550-27de-440e-93d8-bc287d6bbd8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28466
69854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.2846669854
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.3234167894
Short name T2032
Test name
Test status
Simulation time 807064356 ps
CPU time 2.31 seconds
Started Jul 26 05:11:58 PM PDT 24
Finished Jul 26 05:12:00 PM PDT 24
Peak memory 207316 kb
Host smart-fd5db779-7ba0-49f7-aa1a-e12b42aa89ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32341
67894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.3234167894
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.966208105
Short name T1555
Test name
Test status
Simulation time 182406243 ps
CPU time 2.27 seconds
Started Jul 26 05:11:58 PM PDT 24
Finished Jul 26 05:12:01 PM PDT 24
Peak memory 207212 kb
Host smart-b0bd2c92-9f72-4e06-99cb-1cf09e9c9ef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96620
8105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.966208105
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.1401798875
Short name T1753
Test name
Test status
Simulation time 225538210 ps
CPU time 1.31 seconds
Started Jul 26 05:11:54 PM PDT 24
Finished Jul 26 05:11:56 PM PDT 24
Peak memory 215512 kb
Host smart-10a4f2b3-1cda-4a9d-a85c-acdc9e1581e3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1401798875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.1401798875
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.2030051619
Short name T2591
Test name
Test status
Simulation time 150779392 ps
CPU time 0.85 seconds
Started Jul 26 05:11:58 PM PDT 24
Finished Jul 26 05:11:59 PM PDT 24
Peak memory 206992 kb
Host smart-a46f7be4-027a-4019-bdd9-13bd5d94f10c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20300
51619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.2030051619
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.882575619
Short name T1118
Test name
Test status
Simulation time 183732599 ps
CPU time 0.96 seconds
Started Jul 26 05:11:55 PM PDT 24
Finished Jul 26 05:11:56 PM PDT 24
Peak memory 207100 kb
Host smart-45f90767-d920-4f28-9718-a7e453a393fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88257
5619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.882575619
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_invalid_sync.1546485844
Short name T818
Test name
Test status
Simulation time 7039054300 ps
CPU time 57.05 seconds
Started Jul 26 05:12:02 PM PDT 24
Finished Jul 26 05:13:00 PM PDT 24
Peak memory 216988 kb
Host smart-f92f0341-84b3-40e7-a2ca-c9b060561dd3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1546485844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.1546485844
Directory /workspace/26.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/26.usbdev_iso_retraction.231524939
Short name T2192
Test name
Test status
Simulation time 7483265283 ps
CPU time 95.98 seconds
Started Jul 26 05:11:55 PM PDT 24
Finished Jul 26 05:13:31 PM PDT 24
Peak memory 207344 kb
Host smart-c634ed85-7099-4e2d-86b6-2b64cb1c18a9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=231524939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_iso_retraction.231524939
Directory /workspace/26.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.115317462
Short name T1686
Test name
Test status
Simulation time 222821935 ps
CPU time 0.92 seconds
Started Jul 26 05:11:54 PM PDT 24
Finished Jul 26 05:11:55 PM PDT 24
Peak memory 207036 kb
Host smart-4577c31c-ae6f-4601-9fe7-ec2a01e01988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11531
7462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.115317462
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.3507718870
Short name T413
Test name
Test status
Simulation time 23336376313 ps
CPU time 28.12 seconds
Started Jul 26 05:11:54 PM PDT 24
Finished Jul 26 05:12:22 PM PDT 24
Peak memory 207284 kb
Host smart-3c41c6cd-4a64-44f9-94c9-720e4073a857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35077
18870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.3507718870
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.3682299482
Short name T2523
Test name
Test status
Simulation time 3331592817 ps
CPU time 4.7 seconds
Started Jul 26 05:11:59 PM PDT 24
Finished Jul 26 05:12:04 PM PDT 24
Peak memory 207272 kb
Host smart-d079b722-fe95-4b2c-98db-c0087b2a2af0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36822
99482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.3682299482
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.2504318378
Short name T150
Test name
Test status
Simulation time 10226615645 ps
CPU time 103.37 seconds
Started Jul 26 05:11:50 PM PDT 24
Finished Jul 26 05:13:34 PM PDT 24
Peak memory 217392 kb
Host smart-b1ef3a73-bd67-4992-bbb1-3546ddaed94d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25043
18378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.2504318378
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.2864012562
Short name T1368
Test name
Test status
Simulation time 4303848899 ps
CPU time 33.64 seconds
Started Jul 26 05:11:55 PM PDT 24
Finished Jul 26 05:12:29 PM PDT 24
Peak memory 217012 kb
Host smart-22941c7a-6ed3-4cb3-a6be-6dacd85f52d3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2864012562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.2864012562
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.3695398869
Short name T874
Test name
Test status
Simulation time 294606106 ps
CPU time 1.05 seconds
Started Jul 26 05:11:52 PM PDT 24
Finished Jul 26 05:11:53 PM PDT 24
Peak memory 207084 kb
Host smart-02faae24-c13a-450c-bba3-9153fb2c12df
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3695398869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.3695398869
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.2650487447
Short name T1861
Test name
Test status
Simulation time 209449260 ps
CPU time 0.97 seconds
Started Jul 26 05:11:53 PM PDT 24
Finished Jul 26 05:11:54 PM PDT 24
Peak memory 207040 kb
Host smart-31a03aad-4007-465f-a8af-5b0f0abbdc5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26504
87447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.2650487447
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.129118376
Short name T701
Test name
Test status
Simulation time 5159858724 ps
CPU time 162.23 seconds
Started Jul 26 05:11:59 PM PDT 24
Finished Jul 26 05:14:41 PM PDT 24
Peak memory 215592 kb
Host smart-0ad71b9e-daaf-4c6a-ad6b-1ff430d63716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12911
8376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.129118376
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.3245190802
Short name T1907
Test name
Test status
Simulation time 3736314270 ps
CPU time 30.05 seconds
Started Jul 26 05:12:02 PM PDT 24
Finished Jul 26 05:12:33 PM PDT 24
Peak memory 216892 kb
Host smart-763f5bc6-dca8-4935-9b86-a03ce1a838e0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3245190802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.3245190802
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.4247398081
Short name T1340
Test name
Test status
Simulation time 168407288 ps
CPU time 0.91 seconds
Started Jul 26 05:11:59 PM PDT 24
Finished Jul 26 05:12:00 PM PDT 24
Peak memory 207092 kb
Host smart-307052b6-c254-43db-ab4c-2d661fd4d523
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4247398081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.4247398081
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.3764842061
Short name T2828
Test name
Test status
Simulation time 136847237 ps
CPU time 0.9 seconds
Started Jul 26 05:11:53 PM PDT 24
Finished Jul 26 05:11:55 PM PDT 24
Peak memory 207120 kb
Host smart-dea3e273-6b79-4587-ad33-de98a0ac6ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37648
42061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.3764842061
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.3923859440
Short name T994
Test name
Test status
Simulation time 192356947 ps
CPU time 0.97 seconds
Started Jul 26 05:11:57 PM PDT 24
Finished Jul 26 05:11:58 PM PDT 24
Peak memory 207008 kb
Host smart-f70d3b90-350f-4926-abe1-5ac5ce0c1808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39238
59440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.3923859440
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.1279315410
Short name T614
Test name
Test status
Simulation time 172656855 ps
CPU time 0.92 seconds
Started Jul 26 05:11:58 PM PDT 24
Finished Jul 26 05:11:59 PM PDT 24
Peak memory 207148 kb
Host smart-277cc1e8-f4df-4a5c-ada5-4c0ce68a43ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12793
15410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.1279315410
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.2492168896
Short name T2436
Test name
Test status
Simulation time 187772580 ps
CPU time 0.93 seconds
Started Jul 26 05:11:58 PM PDT 24
Finished Jul 26 05:11:59 PM PDT 24
Peak memory 207088 kb
Host smart-219b9c55-2f4d-4b53-b559-2d3254d60b0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24921
68896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.2492168896
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.3716627593
Short name T2176
Test name
Test status
Simulation time 161366867 ps
CPU time 0.87 seconds
Started Jul 26 05:11:58 PM PDT 24
Finished Jul 26 05:11:59 PM PDT 24
Peak memory 207100 kb
Host smart-a2225eec-20d2-4c75-8876-897b569a502d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37166
27593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.3716627593
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.1454822129
Short name T453
Test name
Test status
Simulation time 250884858 ps
CPU time 1.14 seconds
Started Jul 26 05:12:06 PM PDT 24
Finished Jul 26 05:12:07 PM PDT 24
Peak memory 207132 kb
Host smart-78e54f49-4566-4f91-9b95-51798da513a1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1454822129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.1454822129
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.77558725
Short name T1100
Test name
Test status
Simulation time 140118302 ps
CPU time 0.83 seconds
Started Jul 26 05:11:57 PM PDT 24
Finished Jul 26 05:11:58 PM PDT 24
Peak memory 207096 kb
Host smart-f4328dd4-5e7f-4fd3-a3ce-b1938cf1acbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77558
725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.77558725
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.1235995309
Short name T1851
Test name
Test status
Simulation time 35034104 ps
CPU time 0.71 seconds
Started Jul 26 05:12:06 PM PDT 24
Finished Jul 26 05:12:06 PM PDT 24
Peak memory 207096 kb
Host smart-96921964-d33a-4575-be83-4505cdb5e7d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12359
95309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.1235995309
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.1013334442
Short name T238
Test name
Test status
Simulation time 19228804946 ps
CPU time 47.52 seconds
Started Jul 26 05:12:07 PM PDT 24
Finished Jul 26 05:12:55 PM PDT 24
Peak memory 223768 kb
Host smart-04c03a50-c247-424c-9448-6d305cddc8f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10133
34442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.1013334442
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.1267318455
Short name T1504
Test name
Test status
Simulation time 167410124 ps
CPU time 0.9 seconds
Started Jul 26 05:12:06 PM PDT 24
Finished Jul 26 05:12:07 PM PDT 24
Peak memory 207132 kb
Host smart-c5afd2e9-e05b-4e1d-950c-b07d61091a22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12673
18455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.1267318455
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.1860569429
Short name T2299
Test name
Test status
Simulation time 178838053 ps
CPU time 0.98 seconds
Started Jul 26 05:12:06 PM PDT 24
Finished Jul 26 05:12:07 PM PDT 24
Peak memory 207132 kb
Host smart-65ffff09-209d-4188-b40b-3378c7155549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18605
69429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.1860569429
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.3290178992
Short name T2786
Test name
Test status
Simulation time 245961560 ps
CPU time 0.97 seconds
Started Jul 26 05:12:01 PM PDT 24
Finished Jul 26 05:12:02 PM PDT 24
Peak memory 207028 kb
Host smart-26084c01-61d6-4e8e-a072-4ff78c4cfb41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32901
78992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.3290178992
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.2870210636
Short name T1933
Test name
Test status
Simulation time 175996767 ps
CPU time 0.91 seconds
Started Jul 26 05:12:03 PM PDT 24
Finished Jul 26 05:12:04 PM PDT 24
Peak memory 207212 kb
Host smart-a094ea24-295f-4006-9e08-a05e8949c710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28702
10636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.2870210636
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.3508878717
Short name T2517
Test name
Test status
Simulation time 145305749 ps
CPU time 0.8 seconds
Started Jul 26 05:11:58 PM PDT 24
Finished Jul 26 05:11:59 PM PDT 24
Peak memory 207140 kb
Host smart-f246fce2-0e36-47bc-9117-12018da0ab8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35088
78717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.3508878717
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.1789580836
Short name T2390
Test name
Test status
Simulation time 160948172 ps
CPU time 0.86 seconds
Started Jul 26 05:12:02 PM PDT 24
Finished Jul 26 05:12:04 PM PDT 24
Peak memory 206996 kb
Host smart-9b253d76-703f-4f9c-a20f-606c8ea427bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17895
80836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.1789580836
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.2193599039
Short name T2739
Test name
Test status
Simulation time 166402966 ps
CPU time 0.97 seconds
Started Jul 26 05:12:02 PM PDT 24
Finished Jul 26 05:12:03 PM PDT 24
Peak memory 206904 kb
Host smart-9d5faf60-1d6d-4b9f-940a-a200f83b7381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21935
99039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.2193599039
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.170251096
Short name T1793
Test name
Test status
Simulation time 218728030 ps
CPU time 0.99 seconds
Started Jul 26 05:12:02 PM PDT 24
Finished Jul 26 05:12:04 PM PDT 24
Peak memory 207124 kb
Host smart-a4d21881-feb0-4fc2-96bd-29a2accb2024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17025
1096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.170251096
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.2434560605
Short name T2413
Test name
Test status
Simulation time 6660125858 ps
CPU time 47.93 seconds
Started Jul 26 05:12:02 PM PDT 24
Finished Jul 26 05:12:50 PM PDT 24
Peak memory 215652 kb
Host smart-efca4c4b-359c-4ef4-b712-4bf7a808133b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2434560605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.2434560605
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.2205447757
Short name T2617
Test name
Test status
Simulation time 178796376 ps
CPU time 0.85 seconds
Started Jul 26 05:12:05 PM PDT 24
Finished Jul 26 05:12:06 PM PDT 24
Peak memory 207136 kb
Host smart-e22d9a8a-dab7-4ed9-aa13-5bbfdbad590c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22054
47757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.2205447757
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.1280521317
Short name T567
Test name
Test status
Simulation time 200465863 ps
CPU time 0.97 seconds
Started Jul 26 05:12:01 PM PDT 24
Finished Jul 26 05:12:02 PM PDT 24
Peak memory 207128 kb
Host smart-6d005163-a1a4-430a-994e-be707a3c01e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12805
21317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.1280521317
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.2395242171
Short name T2564
Test name
Test status
Simulation time 378233736 ps
CPU time 1.3 seconds
Started Jul 26 05:12:08 PM PDT 24
Finished Jul 26 05:12:09 PM PDT 24
Peak memory 207048 kb
Host smart-2d0472c9-c7d1-435e-ae9f-ab7ae9a5ce20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23952
42171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.2395242171
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.2389874210
Short name T2200
Test name
Test status
Simulation time 3315303601 ps
CPU time 24.6 seconds
Started Jul 26 05:12:02 PM PDT 24
Finished Jul 26 05:12:27 PM PDT 24
Peak memory 216956 kb
Host smart-8a744647-5227-458a-b59f-1e1fe2cab50b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23898
74210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.2389874210
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_timeout_missing_host_handshake.3990718379
Short name T652
Test name
Test status
Simulation time 3425900362 ps
CPU time 30.09 seconds
Started Jul 26 05:12:02 PM PDT 24
Finished Jul 26 05:12:32 PM PDT 24
Peak memory 207260 kb
Host smart-e637c3b7-76b9-43a6-b206-40ed70cb2f3d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990718379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_timeout_missing_hos
t_handshake.3990718379
Directory /workspace/26.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.16859998
Short name T1153
Test name
Test status
Simulation time 58099527 ps
CPU time 0.72 seconds
Started Jul 26 05:12:02 PM PDT 24
Finished Jul 26 05:12:03 PM PDT 24
Peak memory 207124 kb
Host smart-428ae07a-2a43-408b-a2e2-c4367c0ff6e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=16859998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.16859998
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.2717727302
Short name T1180
Test name
Test status
Simulation time 3910827025 ps
CPU time 5.59 seconds
Started Jul 26 05:11:59 PM PDT 24
Finished Jul 26 05:12:05 PM PDT 24
Peak memory 207340 kb
Host smart-bbe72ae7-361a-47cb-a2cc-57292572d7ae
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717727302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_a
on_wake_disconnect.2717727302
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.404714211
Short name T1456
Test name
Test status
Simulation time 13421634750 ps
CPU time 15.11 seconds
Started Jul 26 05:12:02 PM PDT 24
Finished Jul 26 05:12:17 PM PDT 24
Peak memory 207296 kb
Host smart-6d6c26f6-cc6f-4977-aada-f3a2b7e43ce7
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=404714211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.404714211
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.3428760814
Short name T673
Test name
Test status
Simulation time 23359887254 ps
CPU time 28.14 seconds
Started Jul 26 05:12:08 PM PDT 24
Finished Jul 26 05:12:36 PM PDT 24
Peak memory 207344 kb
Host smart-b2d29003-f7ea-473a-9ca1-2954846932d6
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428760814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_a
on_wake_resume.3428760814
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.2532625517
Short name T1080
Test name
Test status
Simulation time 176074290 ps
CPU time 0.88 seconds
Started Jul 26 05:12:01 PM PDT 24
Finished Jul 26 05:12:02 PM PDT 24
Peak memory 207152 kb
Host smart-db027919-4507-4198-afd7-e6794cdad61c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25326
25517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.2532625517
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.4099070061
Short name T1244
Test name
Test status
Simulation time 149802475 ps
CPU time 0.82 seconds
Started Jul 26 05:11:59 PM PDT 24
Finished Jul 26 05:12:00 PM PDT 24
Peak memory 207100 kb
Host smart-473d4f29-da22-41df-93e6-f40c57cf36fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40990
70061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.4099070061
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.2981410753
Short name T1609
Test name
Test status
Simulation time 286556941 ps
CPU time 1.17 seconds
Started Jul 26 05:12:04 PM PDT 24
Finished Jul 26 05:12:05 PM PDT 24
Peak memory 207044 kb
Host smart-c4a255e5-0c16-4286-93de-50cd1fc88c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29814
10753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.2981410753
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.1686078719
Short name T1786
Test name
Test status
Simulation time 367457388 ps
CPU time 1.3 seconds
Started Jul 26 05:12:08 PM PDT 24
Finished Jul 26 05:12:10 PM PDT 24
Peak memory 207096 kb
Host smart-fa20d5f4-8860-4b40-8f80-0b157ecb15b3
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1686078719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.1686078719
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.2484404402
Short name T2331
Test name
Test status
Simulation time 22936992002 ps
CPU time 57.69 seconds
Started Jul 26 05:12:09 PM PDT 24
Finished Jul 26 05:13:08 PM PDT 24
Peak memory 207224 kb
Host smart-fa0dfa62-ab04-4ff4-84fb-7cfb1d64d310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24844
04402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.2484404402
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_device_timeout.2304805231
Short name T2670
Test name
Test status
Simulation time 2922374769 ps
CPU time 25.66 seconds
Started Jul 26 05:12:08 PM PDT 24
Finished Jul 26 05:12:34 PM PDT 24
Peak memory 207396 kb
Host smart-01853b05-7d55-490d-80a4-ca78f6652d1f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304805231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_timeout.2304805231
Directory /workspace/27.usbdev_device_timeout/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.2241583982
Short name T2569
Test name
Test status
Simulation time 432271819 ps
CPU time 1.46 seconds
Started Jul 26 05:11:57 PM PDT 24
Finished Jul 26 05:11:59 PM PDT 24
Peak memory 206900 kb
Host smart-98df41a2-e6d0-4054-aedd-35e1c8abfe78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22415
83982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.2241583982
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.475255955
Short name T2399
Test name
Test status
Simulation time 148444410 ps
CPU time 0.92 seconds
Started Jul 26 05:12:09 PM PDT 24
Finished Jul 26 05:12:10 PM PDT 24
Peak memory 207284 kb
Host smart-a3641795-ce27-4401-8758-dae04c45eb62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47525
5955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.475255955
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.1529758080
Short name T1878
Test name
Test status
Simulation time 40072057 ps
CPU time 0.68 seconds
Started Jul 26 05:12:07 PM PDT 24
Finished Jul 26 05:12:08 PM PDT 24
Peak memory 207044 kb
Host smart-7bd7b0fe-3a5f-4340-a891-e4f4a93905a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15297
58080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.1529758080
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.319747473
Short name T2281
Test name
Test status
Simulation time 1113311587 ps
CPU time 3.06 seconds
Started Jul 26 05:12:10 PM PDT 24
Finished Jul 26 05:12:13 PM PDT 24
Peak memory 207332 kb
Host smart-516490b5-1170-4530-837e-836c85381ab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31974
7473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.319747473
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.2552797557
Short name T1921
Test name
Test status
Simulation time 272764463 ps
CPU time 1.59 seconds
Started Jul 26 05:11:57 PM PDT 24
Finished Jul 26 05:11:59 PM PDT 24
Peak memory 207256 kb
Host smart-03f8a6d9-df54-4c84-b708-53e36eeaade5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25527
97557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.2552797557
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.198803336
Short name T1755
Test name
Test status
Simulation time 154916761 ps
CPU time 0.95 seconds
Started Jul 26 05:12:07 PM PDT 24
Finished Jul 26 05:12:08 PM PDT 24
Peak memory 207124 kb
Host smart-6b0d36ae-9193-4235-9724-dab408958bc1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=198803336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.198803336
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.2124720034
Short name T1527
Test name
Test status
Simulation time 198591529 ps
CPU time 0.94 seconds
Started Jul 26 05:12:03 PM PDT 24
Finished Jul 26 05:12:04 PM PDT 24
Peak memory 207020 kb
Host smart-d61cbf43-1ffd-47b6-9591-a87411390915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21247
20034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.2124720034
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.4128386715
Short name T2437
Test name
Test status
Simulation time 238668475 ps
CPU time 0.96 seconds
Started Jul 26 05:12:09 PM PDT 24
Finished Jul 26 05:12:10 PM PDT 24
Peak memory 206996 kb
Host smart-7664ee4c-2f23-42bf-af6e-b22006880962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41283
86715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.4128386715
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.3702622455
Short name T149
Test name
Test status
Simulation time 9300702891 ps
CPU time 278.41 seconds
Started Jul 26 05:12:04 PM PDT 24
Finished Jul 26 05:16:43 PM PDT 24
Peak memory 215544 kb
Host smart-ae8fa8a0-b8cf-4e14-843e-82704a869421
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3702622455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.3702622455
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_iso_retraction.1544306811
Short name T236
Test name
Test status
Simulation time 7225302538 ps
CPU time 53.44 seconds
Started Jul 26 05:12:09 PM PDT 24
Finished Jul 26 05:13:03 PM PDT 24
Peak memory 207316 kb
Host smart-75dba6c1-847e-453e-8939-591b38f8f251
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1544306811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.1544306811
Directory /workspace/27.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.2098374042
Short name T1541
Test name
Test status
Simulation time 225769954 ps
CPU time 0.98 seconds
Started Jul 26 05:12:09 PM PDT 24
Finished Jul 26 05:12:11 PM PDT 24
Peak memory 207096 kb
Host smart-0608c6a0-1e95-4eb8-afa4-ced4c05b03d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20983
74042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.2098374042
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.311098496
Short name T514
Test name
Test status
Simulation time 23342628868 ps
CPU time 30.79 seconds
Started Jul 26 05:12:07 PM PDT 24
Finished Jul 26 05:12:38 PM PDT 24
Peak memory 207360 kb
Host smart-9790edc5-f7c0-4096-8080-7c2f51f04fc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31109
8496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.311098496
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.799880757
Short name T984
Test name
Test status
Simulation time 3330821392 ps
CPU time 5.53 seconds
Started Jul 26 05:12:06 PM PDT 24
Finished Jul 26 05:12:12 PM PDT 24
Peak memory 207364 kb
Host smart-8fb2e287-1ed6-47da-ac9c-0089af392978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79988
0757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.799880757
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.4181249302
Short name T1813
Test name
Test status
Simulation time 8896104062 ps
CPU time 68.37 seconds
Started Jul 26 05:12:07 PM PDT 24
Finished Jul 26 05:13:15 PM PDT 24
Peak memory 223800 kb
Host smart-7fb18e43-8eef-4ab4-a926-90d4bafd0068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41812
49302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.4181249302
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.404309023
Short name T1802
Test name
Test status
Simulation time 4689102640 ps
CPU time 35.66 seconds
Started Jul 26 05:11:59 PM PDT 24
Finished Jul 26 05:12:35 PM PDT 24
Peak memory 217004 kb
Host smart-7fbc9870-6a90-4b12-90d0-9d594b9bfabc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=404309023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.404309023
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.526325473
Short name T1610
Test name
Test status
Simulation time 243061357 ps
CPU time 1.05 seconds
Started Jul 26 05:12:08 PM PDT 24
Finished Jul 26 05:12:09 PM PDT 24
Peak memory 207124 kb
Host smart-fa7bd778-6ebe-41b0-bda3-5628cf7e6c5e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=526325473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.526325473
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.4103137113
Short name T2513
Test name
Test status
Simulation time 197805711 ps
CPU time 0.98 seconds
Started Jul 26 05:12:06 PM PDT 24
Finished Jul 26 05:12:07 PM PDT 24
Peak memory 207144 kb
Host smart-06a6904d-bed7-4716-bc93-a3d65ce030b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41031
37113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.4103137113
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.2244139208
Short name T2021
Test name
Test status
Simulation time 5049473100 ps
CPU time 42.44 seconds
Started Jul 26 05:12:05 PM PDT 24
Finished Jul 26 05:12:48 PM PDT 24
Peak memory 217056 kb
Host smart-9c3d373d-9822-40f5-861d-37115656e090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22441
39208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.2244139208
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.1322344368
Short name T1296
Test name
Test status
Simulation time 8035745923 ps
CPU time 238.72 seconds
Started Jul 26 05:12:04 PM PDT 24
Finished Jul 26 05:16:03 PM PDT 24
Peak memory 215468 kb
Host smart-c354a39e-7a00-41bc-9b8b-712704e51b5c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1322344368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.1322344368
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.4061637007
Short name T1760
Test name
Test status
Simulation time 167276356 ps
CPU time 0.86 seconds
Started Jul 26 05:12:11 PM PDT 24
Finished Jul 26 05:12:12 PM PDT 24
Peak memory 207000 kb
Host smart-be7d500c-22e9-4305-beab-844feea09a2c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4061637007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.4061637007
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.3903500567
Short name T1033
Test name
Test status
Simulation time 144596532 ps
CPU time 0.9 seconds
Started Jul 26 05:12:09 PM PDT 24
Finished Jul 26 05:12:11 PM PDT 24
Peak memory 207332 kb
Host smart-5968dc19-1abc-478e-a0f4-737c7e4a7ecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39035
00567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.3903500567
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.3201344368
Short name T120
Test name
Test status
Simulation time 217649738 ps
CPU time 0.96 seconds
Started Jul 26 05:11:57 PM PDT 24
Finished Jul 26 05:11:59 PM PDT 24
Peak memory 207020 kb
Host smart-a230fee9-971e-4118-8241-e0c6e1198966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32013
44368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.3201344368
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.1669908424
Short name T911
Test name
Test status
Simulation time 168614940 ps
CPU time 0.9 seconds
Started Jul 26 05:12:06 PM PDT 24
Finished Jul 26 05:12:07 PM PDT 24
Peak memory 207116 kb
Host smart-26028125-6ea0-4813-90d3-9a9d6d022164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16699
08424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.1669908424
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.2095879950
Short name T982
Test name
Test status
Simulation time 154609928 ps
CPU time 0.86 seconds
Started Jul 26 05:12:01 PM PDT 24
Finished Jul 26 05:12:02 PM PDT 24
Peak memory 207076 kb
Host smart-b6ae9043-03ae-4567-bcb8-e4956bb15fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20958
79950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.2095879950
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.970767606
Short name T755
Test name
Test status
Simulation time 162461518 ps
CPU time 0.89 seconds
Started Jul 26 05:12:07 PM PDT 24
Finished Jul 26 05:12:08 PM PDT 24
Peak memory 207332 kb
Host smart-02dc0df4-7be8-4b67-a50a-07a935a0f49c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97076
7606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.970767606
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.673805266
Short name T2244
Test name
Test status
Simulation time 172691230 ps
CPU time 0.89 seconds
Started Jul 26 05:12:07 PM PDT 24
Finished Jul 26 05:12:08 PM PDT 24
Peak memory 207340 kb
Host smart-a0049ca5-0ae9-4acd-8437-47c53d922392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67380
5266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.673805266
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.2241197774
Short name T2459
Test name
Test status
Simulation time 195450966 ps
CPU time 0.98 seconds
Started Jul 26 05:12:00 PM PDT 24
Finished Jul 26 05:12:01 PM PDT 24
Peak memory 207120 kb
Host smart-03dbab9c-e2a3-4356-86e3-7a3055abaa44
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2241197774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.2241197774
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.2390672435
Short name T2816
Test name
Test status
Simulation time 138861756 ps
CPU time 0.83 seconds
Started Jul 26 05:12:09 PM PDT 24
Finished Jul 26 05:12:11 PM PDT 24
Peak memory 207088 kb
Host smart-a0013f7e-b3d8-4e60-b495-535a670494b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23906
72435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.2390672435
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.3478787847
Short name T779
Test name
Test status
Simulation time 73022329 ps
CPU time 0.69 seconds
Started Jul 26 05:12:13 PM PDT 24
Finished Jul 26 05:12:14 PM PDT 24
Peak memory 207044 kb
Host smart-c6e78ba5-e70f-4f84-b974-d4f3b39c7d18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34787
87847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.3478787847
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.511930643
Short name T1846
Test name
Test status
Simulation time 10049282254 ps
CPU time 24.54 seconds
Started Jul 26 05:12:08 PM PDT 24
Finished Jul 26 05:12:33 PM PDT 24
Peak memory 215588 kb
Host smart-0a497cfd-c2d5-47f3-a41a-085f7afacdae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51193
0643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.511930643
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.2889483892
Short name T2530
Test name
Test status
Simulation time 166557728 ps
CPU time 0.89 seconds
Started Jul 26 05:12:01 PM PDT 24
Finished Jul 26 05:12:02 PM PDT 24
Peak memory 207056 kb
Host smart-0ef061b8-655c-4095-b31c-965dc0d52970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28894
83892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.2889483892
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.1732647367
Short name T1045
Test name
Test status
Simulation time 229774634 ps
CPU time 1.06 seconds
Started Jul 26 05:12:02 PM PDT 24
Finished Jul 26 05:12:03 PM PDT 24
Peak memory 206888 kb
Host smart-2559374f-4ba0-4358-b811-081a6354020f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17326
47367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.1732647367
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.3917300397
Short name T1812
Test name
Test status
Simulation time 216377764 ps
CPU time 0.93 seconds
Started Jul 26 05:12:07 PM PDT 24
Finished Jul 26 05:12:09 PM PDT 24
Peak memory 207092 kb
Host smart-00f3f55b-46f8-447b-8f4b-40f9b6f2ab78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39173
00397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.3917300397
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.3918955024
Short name T2502
Test name
Test status
Simulation time 240489732 ps
CPU time 0.98 seconds
Started Jul 26 05:12:07 PM PDT 24
Finished Jul 26 05:12:08 PM PDT 24
Peak memory 207136 kb
Host smart-6d5eb7c4-c31a-48f6-be31-829dae099ad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39189
55024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.3918955024
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.921450567
Short name T574
Test name
Test status
Simulation time 223440831 ps
CPU time 0.95 seconds
Started Jul 26 05:12:02 PM PDT 24
Finished Jul 26 05:12:03 PM PDT 24
Peak memory 207208 kb
Host smart-e87a4dcc-f560-4524-afb6-96ed6537fb42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92145
0567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.921450567
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.3367558582
Short name T2747
Test name
Test status
Simulation time 153238360 ps
CPU time 0.87 seconds
Started Jul 26 05:12:05 PM PDT 24
Finished Jul 26 05:12:06 PM PDT 24
Peak memory 207020 kb
Host smart-f65688e9-6be6-4a4b-9ac3-661c90f63108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33675
58582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.3367558582
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.1482474403
Short name T2439
Test name
Test status
Simulation time 167096591 ps
CPU time 0.84 seconds
Started Jul 26 05:12:04 PM PDT 24
Finished Jul 26 05:12:05 PM PDT 24
Peak memory 207048 kb
Host smart-95a9f1a5-02f2-4eab-8f06-7d81a862fa40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14824
74403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.1482474403
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.3397310255
Short name T2292
Test name
Test status
Simulation time 199741352 ps
CPU time 0.98 seconds
Started Jul 26 05:12:06 PM PDT 24
Finished Jul 26 05:12:08 PM PDT 24
Peak memory 207120 kb
Host smart-660741ae-0e25-4855-82a4-03f4e8cb17c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33973
10255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.3397310255
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.269652700
Short name T950
Test name
Test status
Simulation time 4706024468 ps
CPU time 48.85 seconds
Started Jul 26 05:12:01 PM PDT 24
Finished Jul 26 05:12:50 PM PDT 24
Peak memory 217184 kb
Host smart-395fcd0f-217e-4ec2-a4c6-640363bbde5a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=269652700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.269652700
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.3058114800
Short name T1617
Test name
Test status
Simulation time 147895212 ps
CPU time 0.85 seconds
Started Jul 26 05:12:11 PM PDT 24
Finished Jul 26 05:12:12 PM PDT 24
Peak memory 207012 kb
Host smart-71750ca8-0062-453d-9221-7dac3f678eb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30581
14800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.3058114800
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.3791110017
Short name T502
Test name
Test status
Simulation time 186434807 ps
CPU time 0.92 seconds
Started Jul 26 05:12:07 PM PDT 24
Finished Jul 26 05:12:08 PM PDT 24
Peak memory 207084 kb
Host smart-0b9285a7-f1a8-41ee-a126-3e030313a096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37911
10017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.3791110017
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.141617406
Short name T1926
Test name
Test status
Simulation time 1276028382 ps
CPU time 3 seconds
Started Jul 26 05:12:09 PM PDT 24
Finished Jul 26 05:12:13 PM PDT 24
Peak memory 207200 kb
Host smart-e3d40c4d-0d62-4b2e-9d46-f5167d255f6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14161
7406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.141617406
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.3649777160
Short name T831
Test name
Test status
Simulation time 4604068367 ps
CPU time 34.74 seconds
Started Jul 26 05:12:11 PM PDT 24
Finished Jul 26 05:12:46 PM PDT 24
Peak memory 216984 kb
Host smart-a1e3123f-9ac9-465f-add2-55c0acadbaae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36497
77160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.3649777160
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_timeout_missing_host_handshake.2790906938
Short name T604
Test name
Test status
Simulation time 3892810042 ps
CPU time 32.61 seconds
Started Jul 26 05:12:05 PM PDT 24
Finished Jul 26 05:12:38 PM PDT 24
Peak memory 207368 kb
Host smart-6c5bec26-b327-48f1-8f1d-a5ea49ad869a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790906938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_timeout_missing_hos
t_handshake.2790906938
Directory /workspace/27.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.258506603
Short name T806
Test name
Test status
Simulation time 38291580 ps
CPU time 0.67 seconds
Started Jul 26 05:12:19 PM PDT 24
Finished Jul 26 05:12:20 PM PDT 24
Peak memory 207132 kb
Host smart-a4b310fc-ffa0-4ff3-b84e-858fbd308686
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=258506603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.258506603
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.1964597594
Short name T1946
Test name
Test status
Simulation time 3662268933 ps
CPU time 5.72 seconds
Started Jul 26 05:12:08 PM PDT 24
Finished Jul 26 05:12:13 PM PDT 24
Peak memory 207320 kb
Host smart-4fb60939-1152-4f2b-bae6-5728d1cfac9c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964597594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_a
on_wake_disconnect.1964597594
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.186390124
Short name T908
Test name
Test status
Simulation time 13402314219 ps
CPU time 16.05 seconds
Started Jul 26 05:12:11 PM PDT 24
Finished Jul 26 05:12:28 PM PDT 24
Peak memory 207260 kb
Host smart-299b3840-df33-4df3-8bf5-5783f748e6f5
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=186390124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.186390124
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.3666243095
Short name T805
Test name
Test status
Simulation time 23352014749 ps
CPU time 32.28 seconds
Started Jul 26 05:12:09 PM PDT 24
Finished Jul 26 05:12:41 PM PDT 24
Peak memory 207320 kb
Host smart-ce417741-4bf4-42e4-8838-4aba7be0e0ea
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666243095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_a
on_wake_resume.3666243095
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.2243179332
Short name T2783
Test name
Test status
Simulation time 159610576 ps
CPU time 0.85 seconds
Started Jul 26 05:12:01 PM PDT 24
Finished Jul 26 05:12:02 PM PDT 24
Peak memory 207096 kb
Host smart-3a8ee3c3-f333-4862-909c-6351af19e75a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22431
79332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.2243179332
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.3935052370
Short name T742
Test name
Test status
Simulation time 152128320 ps
CPU time 0.86 seconds
Started Jul 26 05:12:04 PM PDT 24
Finished Jul 26 05:12:05 PM PDT 24
Peak memory 207016 kb
Host smart-8d72e5b4-8229-4865-baf6-e15ec3d8087d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39350
52370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.3935052370
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.549856367
Short name T1700
Test name
Test status
Simulation time 481503591 ps
CPU time 1.76 seconds
Started Jul 26 05:12:17 PM PDT 24
Finished Jul 26 05:12:19 PM PDT 24
Peak memory 207048 kb
Host smart-4f084e3c-3dff-4bda-aa2b-f2a2bcdf32c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54985
6367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.549856367
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.4063090417
Short name T880
Test name
Test status
Simulation time 977985946 ps
CPU time 2.57 seconds
Started Jul 26 05:12:08 PM PDT 24
Finished Jul 26 05:12:10 PM PDT 24
Peak memory 207428 kb
Host smart-03f7a588-508d-43d8-99bf-f0afc90c2fef
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4063090417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.4063090417
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_timeout.2856333874
Short name T2533
Test name
Test status
Simulation time 2538411339 ps
CPU time 19.03 seconds
Started Jul 26 05:12:11 PM PDT 24
Finished Jul 26 05:12:31 PM PDT 24
Peak memory 207372 kb
Host smart-3c90e2d0-c165-4a90-8444-7523edf69f97
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856333874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_timeout.2856333874
Directory /workspace/28.usbdev_device_timeout/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.3644064410
Short name T155
Test name
Test status
Simulation time 443553006 ps
CPU time 1.48 seconds
Started Jul 26 05:12:11 PM PDT 24
Finished Jul 26 05:12:13 PM PDT 24
Peak memory 207040 kb
Host smart-d25b20ba-5d35-4a8e-838d-180e469cdb74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36440
64410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.3644064410
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.148652008
Short name T686
Test name
Test status
Simulation time 149396302 ps
CPU time 0.81 seconds
Started Jul 26 05:12:10 PM PDT 24
Finished Jul 26 05:12:11 PM PDT 24
Peak memory 207068 kb
Host smart-13dbb0d4-53be-4af0-a64e-a523c6ab59a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14865
2008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.148652008
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.3825358837
Short name T1828
Test name
Test status
Simulation time 71863278 ps
CPU time 0.75 seconds
Started Jul 26 05:12:11 PM PDT 24
Finished Jul 26 05:12:12 PM PDT 24
Peak memory 207072 kb
Host smart-7bc81f07-9cf6-48d0-82ce-ea28c208ad1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38253
58837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.3825358837
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.1638023535
Short name T1443
Test name
Test status
Simulation time 893497698 ps
CPU time 2.32 seconds
Started Jul 26 05:12:10 PM PDT 24
Finished Jul 26 05:12:13 PM PDT 24
Peak memory 207236 kb
Host smart-5a73d1c9-0f61-41f6-9967-b13eb19e8190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16380
23535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.1638023535
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.3786126790
Short name T1278
Test name
Test status
Simulation time 182692114 ps
CPU time 1.32 seconds
Started Jul 26 05:12:21 PM PDT 24
Finished Jul 26 05:12:22 PM PDT 24
Peak memory 207256 kb
Host smart-5ec41ac5-9364-4f94-b145-ac4f3106226e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37861
26790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.3786126790
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.2931796600
Short name T2155
Test name
Test status
Simulation time 210569547 ps
CPU time 1.04 seconds
Started Jul 26 05:12:08 PM PDT 24
Finished Jul 26 05:12:10 PM PDT 24
Peak memory 207276 kb
Host smart-9ebf3db9-fa1a-42ac-b8fd-d99bd0233a63
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2931796600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.2931796600
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.430694072
Short name T1031
Test name
Test status
Simulation time 151294952 ps
CPU time 0.82 seconds
Started Jul 26 05:12:09 PM PDT 24
Finished Jul 26 05:12:10 PM PDT 24
Peak memory 206984 kb
Host smart-d006ac5e-a254-403e-9606-57d65c5c8f01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43069
4072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.430694072
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.3037475417
Short name T639
Test name
Test status
Simulation time 210836453 ps
CPU time 0.95 seconds
Started Jul 26 05:12:11 PM PDT 24
Finished Jul 26 05:12:12 PM PDT 24
Peak memory 207028 kb
Host smart-7151d16d-7e63-4c7a-8b6e-6bd26587b89c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30374
75417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.3037475417
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.2047875067
Short name T2187
Test name
Test status
Simulation time 5097736840 ps
CPU time 153.52 seconds
Started Jul 26 05:12:11 PM PDT 24
Finished Jul 26 05:14:45 PM PDT 24
Peak memory 215512 kb
Host smart-93231435-9d13-4ddb-8c2e-28bc464606bd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2047875067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.2047875067
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_iso_retraction.131168592
Short name T497
Test name
Test status
Simulation time 3974638131 ps
CPU time 27.61 seconds
Started Jul 26 05:12:10 PM PDT 24
Finished Jul 26 05:12:38 PM PDT 24
Peak memory 207304 kb
Host smart-d64d87b2-3ce2-4a6c-a249-5629dd21b9d8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=131168592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_iso_retraction.131168592
Directory /workspace/28.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.4211604310
Short name T739
Test name
Test status
Simulation time 189467551 ps
CPU time 0.92 seconds
Started Jul 26 05:12:11 PM PDT 24
Finished Jul 26 05:12:12 PM PDT 24
Peak memory 207080 kb
Host smart-e3cdf246-7990-4fd8-9ee4-9f0f9a3475e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42116
04310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.4211604310
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.2561819077
Short name T344
Test name
Test status
Simulation time 23378834982 ps
CPU time 29.89 seconds
Started Jul 26 05:12:21 PM PDT 24
Finished Jul 26 05:12:51 PM PDT 24
Peak memory 207348 kb
Host smart-dc1bb2bc-d3d9-4c99-8cd1-7e7100c7a0ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25618
19077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.2561819077
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.1272394130
Short name T2798
Test name
Test status
Simulation time 3341701630 ps
CPU time 4.79 seconds
Started Jul 26 05:12:11 PM PDT 24
Finished Jul 26 05:12:16 PM PDT 24
Peak memory 207376 kb
Host smart-2c929fc7-e069-473b-88b7-8edaab6d6821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12723
94130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.1272394130
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.60582522
Short name T2511
Test name
Test status
Simulation time 10054222271 ps
CPU time 72.24 seconds
Started Jul 26 05:12:21 PM PDT 24
Finished Jul 26 05:13:34 PM PDT 24
Peak memory 223708 kb
Host smart-7392da28-de52-41c3-8d71-fd0bb421701a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60582
522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.60582522
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.2251678250
Short name T748
Test name
Test status
Simulation time 7330496861 ps
CPU time 207.45 seconds
Started Jul 26 05:12:09 PM PDT 24
Finished Jul 26 05:15:37 PM PDT 24
Peak memory 215560 kb
Host smart-fdf33c95-ffbb-4a1d-9e51-e3f272d5f816
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2251678250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.2251678250
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.1315901184
Short name T2366
Test name
Test status
Simulation time 276765718 ps
CPU time 1.06 seconds
Started Jul 26 05:12:16 PM PDT 24
Finished Jul 26 05:12:18 PM PDT 24
Peak memory 207060 kb
Host smart-5d660615-5f11-4c58-bb35-f49d79a020b6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1315901184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.1315901184
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.1935730725
Short name T504
Test name
Test status
Simulation time 203464139 ps
CPU time 1.01 seconds
Started Jul 26 05:12:11 PM PDT 24
Finished Jul 26 05:12:12 PM PDT 24
Peak memory 207116 kb
Host smart-e83e6215-f2be-42b1-88c4-18a8aede6528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19357
30725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.1935730725
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.4149978383
Short name T2374
Test name
Test status
Simulation time 5265081178 ps
CPU time 44.62 seconds
Started Jul 26 05:12:13 PM PDT 24
Finished Jul 26 05:12:58 PM PDT 24
Peak memory 215592 kb
Host smart-c2cb3950-1d8e-403f-b7a7-1e9b6e5c0953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41499
78383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.4149978383
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.3301745426
Short name T619
Test name
Test status
Simulation time 5724859106 ps
CPU time 45.5 seconds
Started Jul 26 05:12:09 PM PDT 24
Finished Jul 26 05:12:55 PM PDT 24
Peak memory 207376 kb
Host smart-63a9bd6e-e44c-4856-82e3-679fbf13d6e1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3301745426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.3301745426
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.633227026
Short name T2126
Test name
Test status
Simulation time 164127816 ps
CPU time 0.85 seconds
Started Jul 26 05:12:10 PM PDT 24
Finished Jul 26 05:12:11 PM PDT 24
Peak memory 207108 kb
Host smart-d3067d59-1fc0-40b9-8c66-a61a1aadd2b3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=633227026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.633227026
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.2241836586
Short name T1845
Test name
Test status
Simulation time 164121543 ps
CPU time 0.86 seconds
Started Jul 26 05:12:11 PM PDT 24
Finished Jul 26 05:12:12 PM PDT 24
Peak memory 207044 kb
Host smart-34a9aa55-f561-49f6-bf76-5c2d2ede52fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22418
36586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.2241836586
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.3530910462
Short name T2598
Test name
Test status
Simulation time 202568108 ps
CPU time 0.95 seconds
Started Jul 26 05:12:08 PM PDT 24
Finished Jul 26 05:12:09 PM PDT 24
Peak memory 206980 kb
Host smart-d2274768-52b4-4d35-8f86-dd09ef51c837
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35309
10462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.3530910462
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.5211629
Short name T1750
Test name
Test status
Simulation time 203684729 ps
CPU time 0.92 seconds
Started Jul 26 05:12:12 PM PDT 24
Finished Jul 26 05:12:14 PM PDT 24
Peak memory 207100 kb
Host smart-a0a0947a-1763-4acf-8fbc-a6b4559e000c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52116
29 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.5211629
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.2925445149
Short name T2772
Test name
Test status
Simulation time 168677220 ps
CPU time 0.87 seconds
Started Jul 26 05:12:21 PM PDT 24
Finished Jul 26 05:12:22 PM PDT 24
Peak memory 206692 kb
Host smart-0d3a93b0-04ce-4a1d-9c51-da8c82ed1c9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29254
45149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.2925445149
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.2859919507
Short name T350
Test name
Test status
Simulation time 179613866 ps
CPU time 0.87 seconds
Started Jul 26 05:12:12 PM PDT 24
Finished Jul 26 05:12:13 PM PDT 24
Peak memory 207104 kb
Host smart-5bebd2a3-1c83-4dfc-8c38-325fc9806c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28599
19507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.2859919507
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.741316868
Short name T168
Test name
Test status
Simulation time 160414184 ps
CPU time 0.85 seconds
Started Jul 26 05:12:12 PM PDT 24
Finished Jul 26 05:12:13 PM PDT 24
Peak memory 207028 kb
Host smart-808ffdbe-7d00-4383-8ed6-a7aae4a6b713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74131
6868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.741316868
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.3728495015
Short name T418
Test name
Test status
Simulation time 247390878 ps
CPU time 1.02 seconds
Started Jul 26 05:12:10 PM PDT 24
Finished Jul 26 05:12:11 PM PDT 24
Peak memory 207124 kb
Host smart-9b186634-c8a7-4d36-bea4-67ea058b4874
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3728495015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.3728495015
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.3993572136
Short name T1467
Test name
Test status
Simulation time 138570395 ps
CPU time 0.81 seconds
Started Jul 26 05:12:12 PM PDT 24
Finished Jul 26 05:12:13 PM PDT 24
Peak memory 207048 kb
Host smart-2ac47194-dfde-4836-929c-56345b60ae6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39935
72136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.3993572136
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.4214806458
Short name T1496
Test name
Test status
Simulation time 37324930 ps
CPU time 0.67 seconds
Started Jul 26 05:12:21 PM PDT 24
Finished Jul 26 05:12:22 PM PDT 24
Peak memory 206656 kb
Host smart-756736c6-8b02-43c6-a1e1-4d788d6dec6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42148
06458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.4214806458
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.4007823300
Short name T2732
Test name
Test status
Simulation time 18767648735 ps
CPU time 49.32 seconds
Started Jul 26 05:12:11 PM PDT 24
Finished Jul 26 05:13:00 PM PDT 24
Peak memory 215640 kb
Host smart-0c1bb0e9-bfca-4686-aa60-00791a9f600a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40078
23300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.4007823300
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.9373225
Short name T883
Test name
Test status
Simulation time 183063505 ps
CPU time 0.97 seconds
Started Jul 26 05:12:12 PM PDT 24
Finished Jul 26 05:12:14 PM PDT 24
Peak memory 206936 kb
Host smart-2f7a0a5b-454a-4fbb-859d-eaddf4fe16b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93732
25 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.9373225
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.1080303138
Short name T1548
Test name
Test status
Simulation time 225759844 ps
CPU time 0.98 seconds
Started Jul 26 05:12:10 PM PDT 24
Finished Jul 26 05:12:12 PM PDT 24
Peak memory 207124 kb
Host smart-a81aa463-2986-4617-a551-b11be1b3a47d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10803
03138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.1080303138
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.2626649665
Short name T2082
Test name
Test status
Simulation time 308607217 ps
CPU time 1.11 seconds
Started Jul 26 05:12:21 PM PDT 24
Finished Jul 26 05:12:22 PM PDT 24
Peak memory 207120 kb
Host smart-c053c478-05f5-4008-8288-cdef916a94ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26266
49665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.2626649665
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.3659604075
Short name T1712
Test name
Test status
Simulation time 182985906 ps
CPU time 0.89 seconds
Started Jul 26 05:12:08 PM PDT 24
Finished Jul 26 05:12:09 PM PDT 24
Peak memory 206992 kb
Host smart-587a7798-0c69-46b5-9059-430b935b75f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36596
04075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.3659604075
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.1749854440
Short name T1716
Test name
Test status
Simulation time 186052953 ps
CPU time 0.89 seconds
Started Jul 26 05:12:10 PM PDT 24
Finished Jul 26 05:12:11 PM PDT 24
Peak memory 206988 kb
Host smart-f8615060-90d4-4deb-8a50-d5c7891c6c18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17498
54440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.1749854440
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.739199433
Short name T547
Test name
Test status
Simulation time 144037117 ps
CPU time 0.83 seconds
Started Jul 26 05:12:09 PM PDT 24
Finished Jul 26 05:12:10 PM PDT 24
Peak memory 207012 kb
Host smart-639eef93-252b-4026-b353-177ef9d31bf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73919
9433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.739199433
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.2493448347
Short name T358
Test name
Test status
Simulation time 185840619 ps
CPU time 0.85 seconds
Started Jul 26 05:12:11 PM PDT 24
Finished Jul 26 05:12:12 PM PDT 24
Peak memory 207140 kb
Host smart-7dc12709-ee84-4497-9ae3-9b0ff207e872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24934
48347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.2493448347
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.2084808427
Short name T2199
Test name
Test status
Simulation time 254160421 ps
CPU time 1.06 seconds
Started Jul 26 05:12:09 PM PDT 24
Finished Jul 26 05:12:11 PM PDT 24
Peak memory 207132 kb
Host smart-0498a04f-13e9-4878-b004-58b55565ca76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20848
08427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.2084808427
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.2771202323
Short name T1720
Test name
Test status
Simulation time 4154655031 ps
CPU time 35.91 seconds
Started Jul 26 05:12:10 PM PDT 24
Finished Jul 26 05:12:47 PM PDT 24
Peak memory 217240 kb
Host smart-f726c90a-db96-4c7d-9f99-7c6fc3cc0266
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2771202323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.2771202323
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.706448391
Short name T2350
Test name
Test status
Simulation time 191794012 ps
CPU time 0.94 seconds
Started Jul 26 05:12:12 PM PDT 24
Finished Jul 26 05:12:13 PM PDT 24
Peak memory 207060 kb
Host smart-35a5e963-3929-4a84-b82b-ac20a00acd44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70644
8391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.706448391
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.1808029749
Short name T1182
Test name
Test status
Simulation time 149384840 ps
CPU time 0.82 seconds
Started Jul 26 05:12:17 PM PDT 24
Finished Jul 26 05:12:18 PM PDT 24
Peak memory 207052 kb
Host smart-56f30b7a-681e-42dc-b49d-126dccf890a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18080
29749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.1808029749
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.4226829630
Short name T1451
Test name
Test status
Simulation time 969709592 ps
CPU time 2.58 seconds
Started Jul 26 05:12:10 PM PDT 24
Finished Jul 26 05:12:13 PM PDT 24
Peak memory 207236 kb
Host smart-44af39af-492f-472f-9771-eb913390c213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42268
29630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.4226829630
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.1000568904
Short name T1367
Test name
Test status
Simulation time 6534074904 ps
CPU time 198.12 seconds
Started Jul 26 05:12:19 PM PDT 24
Finished Jul 26 05:15:37 PM PDT 24
Peak memory 215520 kb
Host smart-da453dfa-faf3-498a-9d9c-b79e6089539b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10005
68904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.1000568904
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_timeout_missing_host_handshake.3909502463
Short name T1552
Test name
Test status
Simulation time 170898551 ps
CPU time 0.88 seconds
Started Jul 26 05:12:10 PM PDT 24
Finished Jul 26 05:12:11 PM PDT 24
Peak memory 207096 kb
Host smart-4605390d-569c-4af7-a856-10333e9068b7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909502463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_timeout_missing_hos
t_handshake.3909502463
Directory /workspace/28.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.2982204818
Short name T571
Test name
Test status
Simulation time 40117807 ps
CPU time 0.73 seconds
Started Jul 26 05:12:28 PM PDT 24
Finished Jul 26 05:12:29 PM PDT 24
Peak memory 207092 kb
Host smart-8f607b2f-f00e-4087-a914-5615afa327cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2982204818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.2982204818
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.2333385794
Short name T729
Test name
Test status
Simulation time 3810965617 ps
CPU time 5.52 seconds
Started Jul 26 05:12:21 PM PDT 24
Finished Jul 26 05:12:27 PM PDT 24
Peak memory 207408 kb
Host smart-855089d7-1c78-4665-b112-d8cb7aa0295c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333385794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_a
on_wake_disconnect.2333385794
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.3420764052
Short name T2373
Test name
Test status
Simulation time 13314091017 ps
CPU time 16.74 seconds
Started Jul 26 05:12:20 PM PDT 24
Finished Jul 26 05:12:37 PM PDT 24
Peak memory 207332 kb
Host smart-a85e4304-4325-4223-ac04-04d38d595b1e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420764052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.3420764052
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.670554709
Short name T568
Test name
Test status
Simulation time 23381932709 ps
CPU time 27.76 seconds
Started Jul 26 05:12:19 PM PDT 24
Finished Jul 26 05:12:46 PM PDT 24
Peak memory 207360 kb
Host smart-d6d3f3a3-9b4c-4d3f-a42e-bafc34bcb3cd
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670554709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_ao
n_wake_resume.670554709
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.1460800780
Short name T1604
Test name
Test status
Simulation time 190164500 ps
CPU time 0.93 seconds
Started Jul 26 05:12:19 PM PDT 24
Finished Jul 26 05:12:20 PM PDT 24
Peak memory 207124 kb
Host smart-36e9089c-ddc8-4c30-8108-5cf5ad5a1dcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14608
00780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.1460800780
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.228573873
Short name T2507
Test name
Test status
Simulation time 142839028 ps
CPU time 0.8 seconds
Started Jul 26 05:12:21 PM PDT 24
Finished Jul 26 05:12:22 PM PDT 24
Peak memory 207120 kb
Host smart-36d83888-c4c8-406d-b437-efb4d0cfa1bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22857
3873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.228573873
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.3467952655
Short name T417
Test name
Test status
Simulation time 166928509 ps
CPU time 0.88 seconds
Started Jul 26 05:12:20 PM PDT 24
Finished Jul 26 05:12:21 PM PDT 24
Peak memory 207008 kb
Host smart-aee2b648-7c75-4f68-a0cb-2b9bd2b75459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34679
52655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.3467952655
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.2712268231
Short name T1291
Test name
Test status
Simulation time 1038632285 ps
CPU time 2.46 seconds
Started Jul 26 05:12:19 PM PDT 24
Finished Jul 26 05:12:21 PM PDT 24
Peak memory 207312 kb
Host smart-20e52a23-4fc6-4284-a05a-02c72b7a2e7a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2712268231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.2712268231
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_timeout.1851179557
Short name T2298
Test name
Test status
Simulation time 3585940683 ps
CPU time 25.08 seconds
Started Jul 26 05:12:22 PM PDT 24
Finished Jul 26 05:12:48 PM PDT 24
Peak memory 207344 kb
Host smart-f7600ac5-46fb-4195-aea7-07bf48c9d870
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851179557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_timeout.1851179557
Directory /workspace/29.usbdev_device_timeout/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.465304127
Short name T2318
Test name
Test status
Simulation time 454564619 ps
CPU time 1.44 seconds
Started Jul 26 05:12:19 PM PDT 24
Finished Jul 26 05:12:21 PM PDT 24
Peak memory 207044 kb
Host smart-06d01a9a-5c5d-4ff2-b439-59177a7f0ad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46530
4127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.465304127
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.3365148205
Short name T1309
Test name
Test status
Simulation time 166480446 ps
CPU time 0.89 seconds
Started Jul 26 05:12:20 PM PDT 24
Finished Jul 26 05:12:21 PM PDT 24
Peak memory 207052 kb
Host smart-2f76f641-39bb-4417-9423-bc8ae2eb8552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33651
48205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.3365148205
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.1409809785
Short name T412
Test name
Test status
Simulation time 55707833 ps
CPU time 0.78 seconds
Started Jul 26 05:12:21 PM PDT 24
Finished Jul 26 05:12:23 PM PDT 24
Peak memory 207088 kb
Host smart-a75e4e53-7f70-4d7e-adab-0ff89ae9bc72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14098
09785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.1409809785
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.2980552191
Short name T301
Test name
Test status
Simulation time 834385701 ps
CPU time 2.16 seconds
Started Jul 26 05:12:22 PM PDT 24
Finished Jul 26 05:12:24 PM PDT 24
Peak memory 207168 kb
Host smart-7a2f9fd2-948a-4f83-afe8-c47c5044ec06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29805
52191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.2980552191
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.4287593234
Short name T1852
Test name
Test status
Simulation time 233659082 ps
CPU time 2.19 seconds
Started Jul 26 05:12:23 PM PDT 24
Finished Jul 26 05:12:26 PM PDT 24
Peak memory 207336 kb
Host smart-21394e81-0f7d-42fb-978f-2916d848994c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42875
93234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.4287593234
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.310113009
Short name T370
Test name
Test status
Simulation time 225276296 ps
CPU time 1.05 seconds
Started Jul 26 05:12:20 PM PDT 24
Finished Jul 26 05:12:21 PM PDT 24
Peak memory 207228 kb
Host smart-7f2bdb14-1a95-4e78-957e-85dbce4e0700
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=310113009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.310113009
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.3907932497
Short name T2588
Test name
Test status
Simulation time 193038139 ps
CPU time 0.88 seconds
Started Jul 26 05:12:19 PM PDT 24
Finished Jul 26 05:12:20 PM PDT 24
Peak memory 207052 kb
Host smart-16d7b358-6a09-4cfa-acd8-77e0b17aaef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39079
32497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.3907932497
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.2062933520
Short name T479
Test name
Test status
Simulation time 193434259 ps
CPU time 1 seconds
Started Jul 26 05:12:21 PM PDT 24
Finished Jul 26 05:12:22 PM PDT 24
Peak memory 207056 kb
Host smart-d059f050-402e-41d0-bf20-9f4e00ffe4d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20629
33520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.2062933520
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_invalid_sync.2017525839
Short name T928
Test name
Test status
Simulation time 6478805225 ps
CPU time 65.95 seconds
Started Jul 26 05:12:22 PM PDT 24
Finished Jul 26 05:13:28 PM PDT 24
Peak memory 216708 kb
Host smart-658ec488-8267-4826-af98-59f010569e8d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2017525839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.2017525839
Directory /workspace/29.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/29.usbdev_iso_retraction.1408602576
Short name T1190
Test name
Test status
Simulation time 11186129844 ps
CPU time 69.89 seconds
Started Jul 26 05:12:23 PM PDT 24
Finished Jul 26 05:13:33 PM PDT 24
Peak memory 207344 kb
Host smart-0d02c5a7-42dd-4d1c-9924-5878bef92ae0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1408602576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.1408602576
Directory /workspace/29.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.707720225
Short name T1171
Test name
Test status
Simulation time 241379498 ps
CPU time 0.99 seconds
Started Jul 26 05:12:22 PM PDT 24
Finished Jul 26 05:12:23 PM PDT 24
Peak memory 206936 kb
Host smart-54da24b3-ee8e-4e82-99cc-b4b8ffe36eb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70772
0225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.707720225
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.3464559129
Short name T583
Test name
Test status
Simulation time 23323316787 ps
CPU time 26.29 seconds
Started Jul 26 05:12:25 PM PDT 24
Finished Jul 26 05:12:52 PM PDT 24
Peak memory 207564 kb
Host smart-24a5f6ed-5bf0-4142-91a3-389dfa025cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34645
59129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.3464559129
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.2675820431
Short name T810
Test name
Test status
Simulation time 3293565827 ps
CPU time 5.26 seconds
Started Jul 26 05:12:22 PM PDT 24
Finished Jul 26 05:12:27 PM PDT 24
Peak memory 207220 kb
Host smart-7aabb261-5884-4f6d-ba14-83633270230a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26758
20431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.2675820431
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.339197342
Short name T281
Test name
Test status
Simulation time 8106586690 ps
CPU time 236.88 seconds
Started Jul 26 05:12:20 PM PDT 24
Finished Jul 26 05:16:17 PM PDT 24
Peak memory 215568 kb
Host smart-370618dd-6e12-46c1-af6c-a4d51256f55b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33919
7342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.339197342
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.1868292225
Short name T1139
Test name
Test status
Simulation time 6801478052 ps
CPU time 66.26 seconds
Started Jul 26 05:12:24 PM PDT 24
Finished Jul 26 05:13:30 PM PDT 24
Peak memory 207308 kb
Host smart-4741a388-29b5-4f98-9ea3-8f90a9592ae1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1868292225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.1868292225
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.2638053718
Short name T924
Test name
Test status
Simulation time 242173637 ps
CPU time 0.97 seconds
Started Jul 26 05:12:20 PM PDT 24
Finished Jul 26 05:12:21 PM PDT 24
Peak memory 207048 kb
Host smart-a58d28bb-9a6b-452b-a9b3-57be8457ae08
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2638053718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.2638053718
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.3268400294
Short name T2637
Test name
Test status
Simulation time 272457554 ps
CPU time 1.09 seconds
Started Jul 26 05:12:19 PM PDT 24
Finished Jul 26 05:12:21 PM PDT 24
Peak memory 207044 kb
Host smart-c63a0168-6065-482e-b40e-9278155b8206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32684
00294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.3268400294
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.274256932
Short name T1773
Test name
Test status
Simulation time 3826286398 ps
CPU time 114.87 seconds
Started Jul 26 05:12:19 PM PDT 24
Finished Jul 26 05:14:14 PM PDT 24
Peak memory 215524 kb
Host smart-0707ec2a-bab6-4bff-8e0d-042747d02a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27425
6932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.274256932
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.2250857472
Short name T884
Test name
Test status
Simulation time 4026742512 ps
CPU time 119.66 seconds
Started Jul 26 05:12:21 PM PDT 24
Finished Jul 26 05:14:21 PM PDT 24
Peak memory 215548 kb
Host smart-2fbf33c1-378d-4b66-9762-2968ac4181db
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2250857472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.2250857472
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.4108333261
Short name T2751
Test name
Test status
Simulation time 164847540 ps
CPU time 0.89 seconds
Started Jul 26 05:12:25 PM PDT 24
Finished Jul 26 05:12:26 PM PDT 24
Peak memory 207360 kb
Host smart-acb1ac1c-1699-41b1-8f58-45c8bfad3ff6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4108333261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.4108333261
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.2827354763
Short name T1814
Test name
Test status
Simulation time 145513554 ps
CPU time 0.82 seconds
Started Jul 26 05:12:19 PM PDT 24
Finished Jul 26 05:12:20 PM PDT 24
Peak memory 207104 kb
Host smart-e8f6c1c3-866e-4bdb-b4e6-0258cff05d2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28273
54763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.2827354763
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.1106755633
Short name T125
Test name
Test status
Simulation time 233217777 ps
CPU time 0.98 seconds
Started Jul 26 05:12:19 PM PDT 24
Finished Jul 26 05:12:21 PM PDT 24
Peak memory 207120 kb
Host smart-ecd9fbd2-d271-4284-9ddf-d97d1fcc409e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11067
55633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.1106755633
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.2387697193
Short name T2551
Test name
Test status
Simulation time 151295968 ps
CPU time 0.93 seconds
Started Jul 26 05:12:22 PM PDT 24
Finished Jul 26 05:12:23 PM PDT 24
Peak memory 207120 kb
Host smart-27378d09-733c-4673-81c1-0ebba483dee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23876
97193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.2387697193
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.2869572349
Short name T2329
Test name
Test status
Simulation time 206712818 ps
CPU time 0.9 seconds
Started Jul 26 05:12:20 PM PDT 24
Finished Jul 26 05:12:21 PM PDT 24
Peak memory 207024 kb
Host smart-cfbe808f-1442-4dfd-97bb-f726cb50bfc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28695
72349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.2869572349
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.3244859018
Short name T676
Test name
Test status
Simulation time 155249862 ps
CPU time 0.85 seconds
Started Jul 26 05:12:23 PM PDT 24
Finished Jul 26 05:12:24 PM PDT 24
Peak memory 207136 kb
Host smart-94fc337c-d54d-44a2-87b6-39a420abaa8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32448
59018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.3244859018
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.3355038052
Short name T1513
Test name
Test status
Simulation time 178778001 ps
CPU time 0.84 seconds
Started Jul 26 05:12:22 PM PDT 24
Finished Jul 26 05:12:23 PM PDT 24
Peak memory 207116 kb
Host smart-1a5c774c-aeef-4dad-9e42-6c8a2e03f2a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33550
38052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.3355038052
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.3087864571
Short name T401
Test name
Test status
Simulation time 282355294 ps
CPU time 1.11 seconds
Started Jul 26 05:12:23 PM PDT 24
Finished Jul 26 05:12:24 PM PDT 24
Peak memory 207120 kb
Host smart-3c33606f-8803-4a6c-b65b-880738000477
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3087864571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.3087864571
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.16839852
Short name T2822
Test name
Test status
Simulation time 190821546 ps
CPU time 0.9 seconds
Started Jul 26 05:12:20 PM PDT 24
Finished Jul 26 05:12:21 PM PDT 24
Peak memory 207020 kb
Host smart-755f618b-caad-4b1b-9fec-ddee7a46d27d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16839
852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.16839852
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.2176154510
Short name T2156
Test name
Test status
Simulation time 51029555 ps
CPU time 0.71 seconds
Started Jul 26 05:12:21 PM PDT 24
Finished Jul 26 05:12:22 PM PDT 24
Peak memory 207012 kb
Host smart-755cd2bb-76ad-4a83-aee8-1720eb0098b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21761
54510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.2176154510
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.3630380161
Short name T1844
Test name
Test status
Simulation time 18524180845 ps
CPU time 49.3 seconds
Started Jul 26 05:12:22 PM PDT 24
Finished Jul 26 05:13:12 PM PDT 24
Peak memory 215432 kb
Host smart-1f4d3e99-7c2f-42e8-b972-9bbb2587d0f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36303
80161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.3630380161
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.3651555247
Short name T926
Test name
Test status
Simulation time 162221612 ps
CPU time 0.89 seconds
Started Jul 26 05:12:20 PM PDT 24
Finished Jul 26 05:12:22 PM PDT 24
Peak memory 207048 kb
Host smart-9b3f8fb8-e749-446c-939f-14e17a79a5bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36515
55247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.3651555247
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.2951471415
Short name T1469
Test name
Test status
Simulation time 249235587 ps
CPU time 1.04 seconds
Started Jul 26 05:12:18 PM PDT 24
Finished Jul 26 05:12:19 PM PDT 24
Peak memory 207108 kb
Host smart-25c6049d-4062-4336-abe9-51b2890b51eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29514
71415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.2951471415
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.3813795681
Short name T804
Test name
Test status
Simulation time 176824461 ps
CPU time 0.88 seconds
Started Jul 26 05:12:23 PM PDT 24
Finished Jul 26 05:12:24 PM PDT 24
Peak memory 207024 kb
Host smart-99bf87ed-3009-4bb2-83ea-7380d7c5e042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38137
95681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.3813795681
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.3231784759
Short name T1956
Test name
Test status
Simulation time 198756725 ps
CPU time 0.95 seconds
Started Jul 26 05:12:22 PM PDT 24
Finished Jul 26 05:12:23 PM PDT 24
Peak memory 207108 kb
Host smart-df226ed8-ef5e-4de8-bd5c-44ca45112c43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32317
84759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.3231784759
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.2231000966
Short name T2738
Test name
Test status
Simulation time 206244137 ps
CPU time 1.01 seconds
Started Jul 26 05:12:22 PM PDT 24
Finished Jul 26 05:12:23 PM PDT 24
Peak memory 207124 kb
Host smart-97f932c1-5fe6-44d0-82fd-aa9962105be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22310
00966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.2231000966
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.2595936719
Short name T1680
Test name
Test status
Simulation time 163935624 ps
CPU time 0.83 seconds
Started Jul 26 05:12:21 PM PDT 24
Finished Jul 26 05:12:23 PM PDT 24
Peak memory 206988 kb
Host smart-04a30243-dd9b-49e0-83f9-5b746ed7cba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25959
36719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.2595936719
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.3384667451
Short name T1987
Test name
Test status
Simulation time 165534600 ps
CPU time 0.88 seconds
Started Jul 26 05:12:21 PM PDT 24
Finished Jul 26 05:12:22 PM PDT 24
Peak memory 207024 kb
Host smart-1ee51575-2b92-4734-92e1-05db888ee372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33846
67451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.3384667451
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.1137033488
Short name T1325
Test name
Test status
Simulation time 209157227 ps
CPU time 1 seconds
Started Jul 26 05:12:19 PM PDT 24
Finished Jul 26 05:12:21 PM PDT 24
Peak memory 207092 kb
Host smart-db18f674-317c-4a60-b4e4-6253ef9ad1cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11370
33488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1137033488
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.1965841637
Short name T1510
Test name
Test status
Simulation time 3246014775 ps
CPU time 99.36 seconds
Started Jul 26 05:12:21 PM PDT 24
Finished Jul 26 05:14:00 PM PDT 24
Peak memory 215536 kb
Host smart-c52e7a1f-0d8d-4994-b5a5-d5bbe7d5f011
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1965841637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.1965841637
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.3284102005
Short name T1000
Test name
Test status
Simulation time 188106733 ps
CPU time 0.95 seconds
Started Jul 26 05:12:19 PM PDT 24
Finished Jul 26 05:12:20 PM PDT 24
Peak memory 207016 kb
Host smart-977d0328-714b-4c00-becc-926e3850c9f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32841
02005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.3284102005
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.2156186745
Short name T2009
Test name
Test status
Simulation time 195509108 ps
CPU time 0.9 seconds
Started Jul 26 05:12:21 PM PDT 24
Finished Jul 26 05:12:22 PM PDT 24
Peak memory 206988 kb
Host smart-9389383c-4e8c-4ec1-9deb-b0d127cdc728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21561
86745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.2156186745
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.3144224576
Short name T1616
Test name
Test status
Simulation time 1041743736 ps
CPU time 2.62 seconds
Started Jul 26 05:12:21 PM PDT 24
Finished Jul 26 05:12:24 PM PDT 24
Peak memory 207340 kb
Host smart-f1ffedd2-8148-4b2a-a45a-b52e6136fd2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31442
24576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.3144224576
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.3185961174
Short name T381
Test name
Test status
Simulation time 5187942247 ps
CPU time 151.71 seconds
Started Jul 26 05:12:20 PM PDT 24
Finished Jul 26 05:14:52 PM PDT 24
Peak memory 215576 kb
Host smart-e086cbaf-f222-42e2-a54d-609f4bc7ecaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31859
61174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.3185961174
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_timeout_missing_host_handshake.2075725213
Short name T2537
Test name
Test status
Simulation time 3622478012 ps
CPU time 22.99 seconds
Started Jul 26 05:12:20 PM PDT 24
Finished Jul 26 05:12:43 PM PDT 24
Peak memory 207336 kb
Host smart-83b8285f-7d80-4437-add9-87b104909c2e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075725213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_timeout_missing_hos
t_handshake.2075725213
Directory /workspace/29.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.966541257
Short name T1061
Test name
Test status
Simulation time 49988767 ps
CPU time 0.68 seconds
Started Jul 26 05:07:12 PM PDT 24
Finished Jul 26 05:07:12 PM PDT 24
Peak memory 207124 kb
Host smart-bb440440-2924-4510-8766-22891971e88f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=966541257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.966541257
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.3138720531
Short name T2037
Test name
Test status
Simulation time 3778076020 ps
CPU time 5.7 seconds
Started Jul 26 05:06:52 PM PDT 24
Finished Jul 26 05:06:58 PM PDT 24
Peak memory 207336 kb
Host smart-4085f106-b5e5-44db-aeab-fae0c084130d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138720531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ao
n_wake_disconnect.3138720531
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.3871520641
Short name T2552
Test name
Test status
Simulation time 13378381796 ps
CPU time 14.95 seconds
Started Jul 26 05:06:53 PM PDT 24
Finished Jul 26 05:07:09 PM PDT 24
Peak memory 207332 kb
Host smart-68d5bf78-67c3-4b85-ad57-7c88de7c09a8
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871520641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.3871520641
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.2310070065
Short name T976
Test name
Test status
Simulation time 23376779700 ps
CPU time 25.96 seconds
Started Jul 26 05:06:52 PM PDT 24
Finished Jul 26 05:07:18 PM PDT 24
Peak memory 207308 kb
Host smart-02ebd063-58aa-428e-b20c-c69f2d1ecda3
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310070065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ao
n_wake_resume.2310070065
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.1152323399
Short name T1549
Test name
Test status
Simulation time 159000563 ps
CPU time 0.87 seconds
Started Jul 26 05:06:51 PM PDT 24
Finished Jul 26 05:06:52 PM PDT 24
Peak memory 207024 kb
Host smart-da199e19-9b66-4740-a185-3f1db207df62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11523
23399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.1152323399
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.1589057095
Short name T60
Test name
Test status
Simulation time 157503071 ps
CPU time 0.85 seconds
Started Jul 26 05:06:52 PM PDT 24
Finished Jul 26 05:06:53 PM PDT 24
Peak memory 207212 kb
Host smart-b29e638e-2d52-46af-80d3-2c9fd9b3b79b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15890
57095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.1589057095
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.3882189623
Short name T98
Test name
Test status
Simulation time 145408638 ps
CPU time 0.8 seconds
Started Jul 26 05:06:52 PM PDT 24
Finished Jul 26 05:06:53 PM PDT 24
Peak memory 207028 kb
Host smart-e5624a9b-3811-4819-bee8-8b99c9953c55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38821
89623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.3882189623
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.407663537
Short name T2085
Test name
Test status
Simulation time 146118081 ps
CPU time 0.84 seconds
Started Jul 26 05:06:49 PM PDT 24
Finished Jul 26 05:06:50 PM PDT 24
Peak memory 206988 kb
Host smart-3ecb5302-3cae-44ea-a9db-9d87ce8f79f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40766
3537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.407663537
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.3380323760
Short name T1152
Test name
Test status
Simulation time 231872884 ps
CPU time 0.89 seconds
Started Jul 26 05:06:49 PM PDT 24
Finished Jul 26 05:06:51 PM PDT 24
Peak memory 207116 kb
Host smart-8334a5f3-b917-41df-8188-cd47d5f79232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33803
23760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.3380323760
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.1458200458
Short name T1731
Test name
Test status
Simulation time 1230864447 ps
CPU time 3.28 seconds
Started Jul 26 05:06:49 PM PDT 24
Finished Jul 26 05:06:53 PM PDT 24
Peak memory 207272 kb
Host smart-3bff5c4f-f0db-44b6-858f-e03162bfbbe9
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1458200458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.1458200458
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.2681373134
Short name T2831
Test name
Test status
Simulation time 18980084666 ps
CPU time 43.2 seconds
Started Jul 26 05:06:49 PM PDT 24
Finished Jul 26 05:07:33 PM PDT 24
Peak memory 207412 kb
Host smart-f74d96b4-ab11-44ef-ad9e-d9eaf968603b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26813
73134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.2681373134
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_device_timeout.3704172918
Short name T475
Test name
Test status
Simulation time 5628801629 ps
CPU time 40.44 seconds
Started Jul 26 05:06:49 PM PDT 24
Finished Jul 26 05:07:30 PM PDT 24
Peak memory 207312 kb
Host smart-dbd9107c-58d8-4c0e-8300-e4687bd0034a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704172918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_timeout.3704172918
Directory /workspace/3.usbdev_device_timeout/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.837760231
Short name T703
Test name
Test status
Simulation time 392081605 ps
CPU time 1.33 seconds
Started Jul 26 05:06:51 PM PDT 24
Finished Jul 26 05:06:53 PM PDT 24
Peak memory 207044 kb
Host smart-8d38556a-bf7c-4d1f-ac42-8df883e3269f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83776
0231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.837760231
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.481498668
Short name T647
Test name
Test status
Simulation time 140756573 ps
CPU time 0.83 seconds
Started Jul 26 05:06:50 PM PDT 24
Finished Jul 26 05:06:51 PM PDT 24
Peak memory 207096 kb
Host smart-a33bc09b-adf6-4157-931a-316db2ee3b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48149
8668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.481498668
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.1629133474
Short name T679
Test name
Test status
Simulation time 32269006 ps
CPU time 0.7 seconds
Started Jul 26 05:06:48 PM PDT 24
Finished Jul 26 05:06:49 PM PDT 24
Peak memory 207096 kb
Host smart-6d369f08-5e96-4c5f-977f-d2089171c7ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16291
33474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.1629133474
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.1836021241
Short name T1321
Test name
Test status
Simulation time 815959319 ps
CPU time 2.42 seconds
Started Jul 26 05:06:52 PM PDT 24
Finished Jul 26 05:06:55 PM PDT 24
Peak memory 207364 kb
Host smart-a65c36c8-ecd7-4dd1-ab1b-b585ed32ffd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18360
21241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.1836021241
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.488143981
Short name T1677
Test name
Test status
Simulation time 305506569 ps
CPU time 1.84 seconds
Started Jul 26 05:06:51 PM PDT 24
Finished Jul 26 05:06:53 PM PDT 24
Peak memory 207364 kb
Host smart-d2a8be7f-0953-4845-97fb-ba29f85d5018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48814
3981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.488143981
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.2658025014
Short name T1726
Test name
Test status
Simulation time 91185602186 ps
CPU time 149.23 seconds
Started Jul 26 05:06:49 PM PDT 24
Finished Jul 26 05:09:19 PM PDT 24
Peak memory 207360 kb
Host smart-4b70a823-c4c8-45d0-93d0-e1f0a0bd495b
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2658025014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.2658025014
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.2693619967
Short name T2343
Test name
Test status
Simulation time 89183979695 ps
CPU time 128.36 seconds
Started Jul 26 05:06:55 PM PDT 24
Finished Jul 26 05:09:03 PM PDT 24
Peak memory 207272 kb
Host smart-299cd955-0757-4948-b0f3-07960fe34f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693619967 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.2693619967
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.402735066
Short name T555
Test name
Test status
Simulation time 82167697929 ps
CPU time 115.24 seconds
Started Jul 26 05:06:49 PM PDT 24
Finished Jul 26 05:08:45 PM PDT 24
Peak memory 207340 kb
Host smart-50e82a90-e7c5-4ae2-adec-f29f5938cce0
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=402735066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.402735066
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.2322470643
Short name T979
Test name
Test status
Simulation time 102913794215 ps
CPU time 148.98 seconds
Started Jul 26 05:06:51 PM PDT 24
Finished Jul 26 05:09:20 PM PDT 24
Peak memory 207264 kb
Host smart-ae89792f-3be8-4241-80e4-a9fe18116b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322470643 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.2322470643
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.2724831587
Short name T430
Test name
Test status
Simulation time 110118644899 ps
CPU time 188.64 seconds
Started Jul 26 05:06:53 PM PDT 24
Finished Jul 26 05:10:01 PM PDT 24
Peak memory 207368 kb
Host smart-aba9a923-7574-42a3-89ea-32a7222d1266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27248
31587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.2724831587
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.437546222
Short name T2770
Test name
Test status
Simulation time 170893968 ps
CPU time 0.98 seconds
Started Jul 26 05:06:51 PM PDT 24
Finished Jul 26 05:06:52 PM PDT 24
Peak memory 215272 kb
Host smart-a713fe61-17b7-49c6-a00b-f0d114ee171d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=437546222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.437546222
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.1077510267
Short name T2477
Test name
Test status
Simulation time 160052329 ps
CPU time 0.86 seconds
Started Jul 26 05:06:49 PM PDT 24
Finished Jul 26 05:06:50 PM PDT 24
Peak memory 207092 kb
Host smart-8411bc22-3d04-485d-862b-3acdb9b93596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10775
10267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.1077510267
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.4180030713
Short name T1918
Test name
Test status
Simulation time 216831501 ps
CPU time 1.03 seconds
Started Jul 26 05:06:51 PM PDT 24
Finished Jul 26 05:06:52 PM PDT 24
Peak memory 207068 kb
Host smart-936a1150-e8f9-42a9-b538-a34c54fb0a9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41800
30713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.4180030713
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_invalid_sync.2364538251
Short name T2562
Test name
Test status
Simulation time 5818057987 ps
CPU time 45.21 seconds
Started Jul 26 05:06:50 PM PDT 24
Finished Jul 26 05:07:35 PM PDT 24
Peak memory 217016 kb
Host smart-b488bd92-c5c0-4296-847b-51356fa59ea2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2364538251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.2364538251
Directory /workspace/3.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.297788476
Short name T437
Test name
Test status
Simulation time 187832268 ps
CPU time 0.92 seconds
Started Jul 26 05:06:59 PM PDT 24
Finished Jul 26 05:07:00 PM PDT 24
Peak memory 207136 kb
Host smart-9c952f1e-5eba-4901-bf46-b6ca864a83aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29778
8476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.297788476
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.1406148457
Short name T1509
Test name
Test status
Simulation time 23286770640 ps
CPU time 26.56 seconds
Started Jul 26 05:06:57 PM PDT 24
Finished Jul 26 05:07:23 PM PDT 24
Peak memory 207372 kb
Host smart-8bfee980-5e68-4b02-a421-51e8b2924df3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14061
48457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.1406148457
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.3257667245
Short name T1425
Test name
Test status
Simulation time 3338638159 ps
CPU time 5.56 seconds
Started Jul 26 05:07:00 PM PDT 24
Finished Jul 26 05:07:06 PM PDT 24
Peak memory 207324 kb
Host smart-adfcafd6-7434-47fb-b73c-d2d5569bc9b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32576
67245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.3257667245
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.876186141
Short name T1229
Test name
Test status
Simulation time 5894182736 ps
CPU time 165.4 seconds
Started Jul 26 05:07:04 PM PDT 24
Finished Jul 26 05:09:50 PM PDT 24
Peak memory 215592 kb
Host smart-60b1ceed-e076-4c5a-af8a-51ddcfa0724f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87618
6141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.876186141
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.3176052293
Short name T2838
Test name
Test status
Simulation time 6929336339 ps
CPU time 52.52 seconds
Started Jul 26 05:07:01 PM PDT 24
Finished Jul 26 05:07:54 PM PDT 24
Peak memory 207404 kb
Host smart-12464741-5945-4b84-b635-185fb44cc1e7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3176052293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.3176052293
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.102372797
Short name T1146
Test name
Test status
Simulation time 272931213 ps
CPU time 1.09 seconds
Started Jul 26 05:07:02 PM PDT 24
Finished Jul 26 05:07:03 PM PDT 24
Peak memory 207120 kb
Host smart-a864d8d7-5332-403e-810f-d906fd06666b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=102372797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.102372797
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.2433895963
Short name T2766
Test name
Test status
Simulation time 194966193 ps
CPU time 0.93 seconds
Started Jul 26 05:07:00 PM PDT 24
Finished Jul 26 05:07:01 PM PDT 24
Peak memory 207076 kb
Host smart-3461f708-4395-493c-a1d8-7bf879e191d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24338
95963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.2433895963
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.1346235178
Short name T2143
Test name
Test status
Simulation time 3626064902 ps
CPU time 111.64 seconds
Started Jul 26 05:06:58 PM PDT 24
Finished Jul 26 05:08:49 PM PDT 24
Peak memory 215508 kb
Host smart-fbf77b25-f4d8-413f-8c08-e64965eed3f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13462
35178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.1346235178
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.1355591387
Short name T2561
Test name
Test status
Simulation time 3970974427 ps
CPU time 123.66 seconds
Started Jul 26 05:06:59 PM PDT 24
Finished Jul 26 05:09:02 PM PDT 24
Peak memory 215520 kb
Host smart-4e6925cd-9e47-4c42-a669-6e1798f85433
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1355591387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.1355591387
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.299384576
Short name T2122
Test name
Test status
Simulation time 154157494 ps
CPU time 0.85 seconds
Started Jul 26 05:07:00 PM PDT 24
Finished Jul 26 05:07:01 PM PDT 24
Peak memory 207036 kb
Host smart-3481d3fb-9847-4599-b687-1ccb3a3f54cf
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=299384576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.299384576
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.3793820351
Short name T2830
Test name
Test status
Simulation time 160221331 ps
CPU time 0.91 seconds
Started Jul 26 05:07:02 PM PDT 24
Finished Jul 26 05:07:03 PM PDT 24
Peak memory 207096 kb
Host smart-b44029a1-b3f6-4944-98cc-e7ee6bab8422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37938
20351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.3793820351
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.3499562031
Short name T1685
Test name
Test status
Simulation time 174383848 ps
CPU time 0.98 seconds
Started Jul 26 05:06:58 PM PDT 24
Finished Jul 26 05:06:59 PM PDT 24
Peak memory 207044 kb
Host smart-02097b38-c3db-4ec9-aace-ddeb3e1c1271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34995
62031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.3499562031
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.407118911
Short name T1459
Test name
Test status
Simulation time 160418271 ps
CPU time 0.85 seconds
Started Jul 26 05:07:03 PM PDT 24
Finished Jul 26 05:07:04 PM PDT 24
Peak memory 207104 kb
Host smart-9fc7a95a-be48-4e15-be46-10ceb6c4897c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40711
8911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.407118911
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.4208112865
Short name T349
Test name
Test status
Simulation time 230710657 ps
CPU time 0.9 seconds
Started Jul 26 05:07:01 PM PDT 24
Finished Jul 26 05:07:02 PM PDT 24
Peak memory 207084 kb
Host smart-73a04395-6e30-43e6-b965-007343d70e32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42081
12865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.4208112865
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.947702265
Short name T172
Test name
Test status
Simulation time 152905197 ps
CPU time 0.9 seconds
Started Jul 26 05:07:00 PM PDT 24
Finished Jul 26 05:07:01 PM PDT 24
Peak memory 207112 kb
Host smart-77477d5f-4c89-477a-8ce6-6cfe4aa42ed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94770
2265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.947702265
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.3560227900
Short name T659
Test name
Test status
Simulation time 209537853 ps
CPU time 0.98 seconds
Started Jul 26 05:06:59 PM PDT 24
Finished Jul 26 05:07:00 PM PDT 24
Peak memory 207124 kb
Host smart-2a98827f-9d3c-4376-875e-8cd429d85368
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3560227900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.3560227900
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.1593646462
Short name T195
Test name
Test status
Simulation time 214708919 ps
CPU time 0.98 seconds
Started Jul 26 05:07:02 PM PDT 24
Finished Jul 26 05:07:03 PM PDT 24
Peak memory 207072 kb
Host smart-379c5fca-c5ba-48a9-b609-8b3b9536a235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15936
46462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.1593646462
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.872369468
Short name T476
Test name
Test status
Simulation time 159341684 ps
CPU time 0.85 seconds
Started Jul 26 05:07:00 PM PDT 24
Finished Jul 26 05:07:01 PM PDT 24
Peak memory 207088 kb
Host smart-af55a848-8e78-4513-a8af-1bcd57e30c39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87236
9468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.872369468
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.1905999709
Short name T2625
Test name
Test status
Simulation time 39010748 ps
CPU time 0.67 seconds
Started Jul 26 05:07:01 PM PDT 24
Finished Jul 26 05:07:02 PM PDT 24
Peak memory 207004 kb
Host smart-c6c15829-9426-44e4-9874-0a7eccba61fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19059
99709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.1905999709
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.3693654870
Short name T852
Test name
Test status
Simulation time 20849800269 ps
CPU time 51.65 seconds
Started Jul 26 05:06:58 PM PDT 24
Finished Jul 26 05:07:50 PM PDT 24
Peak memory 223596 kb
Host smart-b8e05f25-287b-4c0d-89bc-58915d11b182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36936
54870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.3693654870
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.1952770304
Short name T458
Test name
Test status
Simulation time 191888658 ps
CPU time 0.98 seconds
Started Jul 26 05:07:01 PM PDT 24
Finished Jul 26 05:07:02 PM PDT 24
Peak memory 207264 kb
Host smart-a86eba84-267a-4fcb-99f1-7fbbbbbfabc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19527
70304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.1952770304
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.1360812489
Short name T1098
Test name
Test status
Simulation time 227675066 ps
CPU time 0.96 seconds
Started Jul 26 05:07:02 PM PDT 24
Finished Jul 26 05:07:03 PM PDT 24
Peak memory 207052 kb
Host smart-04280025-9b5b-40f4-a9ed-34773b8babb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13608
12489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.1360812489
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.2517537637
Short name T2563
Test name
Test status
Simulation time 7446691164 ps
CPU time 125.78 seconds
Started Jul 26 05:07:01 PM PDT 24
Finished Jul 26 05:09:07 PM PDT 24
Peak memory 215512 kb
Host smart-425f25cb-7d6f-4ccd-ac7b-11ff0ff4a32d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2517537637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.2517537637
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.463633291
Short name T1701
Test name
Test status
Simulation time 13378752289 ps
CPU time 81.46 seconds
Started Jul 26 05:07:00 PM PDT 24
Finished Jul 26 05:08:22 PM PDT 24
Peak memory 217724 kb
Host smart-a26cbfa0-4a43-4e5f-9f7c-5455d86bd83e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=463633291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.463633291
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.3796317930
Short name T2422
Test name
Test status
Simulation time 162741963 ps
CPU time 0.92 seconds
Started Jul 26 05:07:00 PM PDT 24
Finished Jul 26 05:07:01 PM PDT 24
Peak memory 207132 kb
Host smart-b60ae5d0-eef7-461b-b371-09b3f1022fa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37963
17930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.3796317930
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.3033155694
Short name T441
Test name
Test status
Simulation time 157712839 ps
CPU time 0.89 seconds
Started Jul 26 05:07:01 PM PDT 24
Finished Jul 26 05:07:02 PM PDT 24
Peak memory 207028 kb
Host smart-36ad54f8-423f-443d-91d9-eb5b58da89f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30331
55694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.3033155694
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.3614243198
Short name T1104
Test name
Test status
Simulation time 175480039 ps
CPU time 0.97 seconds
Started Jul 26 05:07:01 PM PDT 24
Finished Jul 26 05:07:02 PM PDT 24
Peak memory 207100 kb
Host smart-05e153f8-9c47-4ba0-88e1-7f3b5a93473c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36142
43198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.3614243198
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.240584664
Short name T79
Test name
Test status
Simulation time 176092748 ps
CPU time 0.88 seconds
Started Jul 26 05:06:58 PM PDT 24
Finished Jul 26 05:07:00 PM PDT 24
Peak memory 207080 kb
Host smart-5b1e6fbd-242c-4e17-b4f9-b76aa20a3d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24058
4664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.240584664
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.2830019331
Short name T201
Test name
Test status
Simulation time 549106550 ps
CPU time 1.42 seconds
Started Jul 26 05:07:09 PM PDT 24
Finished Jul 26 05:07:11 PM PDT 24
Peak memory 223804 kb
Host smart-cd958456-a957-4ef1-95e0-e54e49bbc300
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2830019331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.2830019331
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.4274545581
Short name T2433
Test name
Test status
Simulation time 428770521 ps
CPU time 1.48 seconds
Started Jul 26 05:07:06 PM PDT 24
Finished Jul 26 05:07:07 PM PDT 24
Peak memory 207024 kb
Host smart-92313769-4258-4694-a17c-3417f1b9df75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42745
45581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.4274545581
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.2896030260
Short name T1769
Test name
Test status
Simulation time 184113281 ps
CPU time 0.92 seconds
Started Jul 26 05:07:01 PM PDT 24
Finished Jul 26 05:07:02 PM PDT 24
Peak memory 207100 kb
Host smart-6770a0bd-f1d6-445a-91ae-e2261bb365ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28960
30260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.2896030260
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.4148668502
Short name T1310
Test name
Test status
Simulation time 183932019 ps
CPU time 0.88 seconds
Started Jul 26 05:07:01 PM PDT 24
Finished Jul 26 05:07:02 PM PDT 24
Peak memory 207232 kb
Host smart-fd8e4d91-b66c-42d7-a4fc-f8bf6744d93d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41486
68502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.4148668502
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.2681485793
Short name T769
Test name
Test status
Simulation time 170914471 ps
CPU time 0.87 seconds
Started Jul 26 05:06:59 PM PDT 24
Finished Jul 26 05:07:00 PM PDT 24
Peak memory 207092 kb
Host smart-8ae9b7d1-0aad-4097-9ec9-29735675d883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26814
85793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.2681485793
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.2563964259
Short name T2651
Test name
Test status
Simulation time 243586111 ps
CPU time 1.13 seconds
Started Jul 26 05:06:58 PM PDT 24
Finished Jul 26 05:07:00 PM PDT 24
Peak memory 207132 kb
Host smart-201a4b06-5b23-4bcb-807c-6f8aa5ee9ad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25639
64259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.2563964259
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.709443602
Short name T1130
Test name
Test status
Simulation time 5656105492 ps
CPU time 45.97 seconds
Started Jul 26 05:07:01 PM PDT 24
Finished Jul 26 05:07:47 PM PDT 24
Peak memory 216728 kb
Host smart-c3eb113d-ac61-4911-9da7-adb141662d6d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=709443602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.709443602
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.3169736973
Short name T2102
Test name
Test status
Simulation time 169510765 ps
CPU time 0.91 seconds
Started Jul 26 05:07:02 PM PDT 24
Finished Jul 26 05:07:03 PM PDT 24
Peak memory 207116 kb
Host smart-ed7ccf5a-f8af-43aa-9f7e-2223545ddaf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31697
36973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.3169736973
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.3695986016
Short name T2239
Test name
Test status
Simulation time 178079653 ps
CPU time 0.88 seconds
Started Jul 26 05:07:02 PM PDT 24
Finished Jul 26 05:07:03 PM PDT 24
Peak memory 207096 kb
Host smart-068571af-d343-42f5-87fc-4f4e5f55d8b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36959
86016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.3695986016
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.2451343318
Short name T97
Test name
Test status
Simulation time 691849631 ps
CPU time 2.02 seconds
Started Jul 26 05:06:57 PM PDT 24
Finished Jul 26 05:06:59 PM PDT 24
Peak memory 207328 kb
Host smart-797254b5-917b-4d4a-8fd1-efedc655dc40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24513
43318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.2451343318
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.3851764800
Short name T2608
Test name
Test status
Simulation time 5520243666 ps
CPU time 167.67 seconds
Started Jul 26 05:07:02 PM PDT 24
Finished Jul 26 05:09:49 PM PDT 24
Peak memory 215544 kb
Host smart-b1f5b15e-23c2-48dd-af9a-e27510dcae23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38517
64800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.3851764800
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_timeout_missing_host_handshake.3563229065
Short name T1062
Test name
Test status
Simulation time 4958135670 ps
CPU time 32.96 seconds
Started Jul 26 05:06:47 PM PDT 24
Finished Jul 26 05:07:20 PM PDT 24
Peak memory 207436 kb
Host smart-bb28adb9-43e3-4217-aca7-1d93025b7e06
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563229065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_timeout_missing_host
_handshake.3563229065
Directory /workspace/3.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.1574337214
Short name T1993
Test name
Test status
Simulation time 34116345 ps
CPU time 0.71 seconds
Started Jul 26 05:12:42 PM PDT 24
Finished Jul 26 05:12:43 PM PDT 24
Peak memory 207124 kb
Host smart-744c9bf7-fa9d-4a6a-a48b-03ba8018c691
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1574337214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.1574337214
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.1835066558
Short name T2558
Test name
Test status
Simulation time 3599637496 ps
CPU time 6.53 seconds
Started Jul 26 05:12:28 PM PDT 24
Finished Jul 26 05:12:34 PM PDT 24
Peak memory 207312 kb
Host smart-d01d575e-ff5c-4f05-8bfb-4b4f54bf3ed7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835066558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_a
on_wake_disconnect.1835066558
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.727947190
Short name T1318
Test name
Test status
Simulation time 13396002302 ps
CPU time 15.85 seconds
Started Jul 26 05:12:42 PM PDT 24
Finished Jul 26 05:12:59 PM PDT 24
Peak memory 207344 kb
Host smart-60edd944-9654-4cc9-a366-2aed6de27ab3
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=727947190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.727947190
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.4126647956
Short name T1754
Test name
Test status
Simulation time 23368380393 ps
CPU time 33.34 seconds
Started Jul 26 05:12:35 PM PDT 24
Finished Jul 26 05:13:09 PM PDT 24
Peak memory 207272 kb
Host smart-855965ee-5f14-4e87-90de-ea59e308cdd1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126647956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_a
on_wake_resume.4126647956
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.3506596538
Short name T1810
Test name
Test status
Simulation time 196735185 ps
CPU time 0.93 seconds
Started Jul 26 05:12:30 PM PDT 24
Finished Jul 26 05:12:31 PM PDT 24
Peak memory 207040 kb
Host smart-e4e392c9-9d4c-480b-9367-bd217998af8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35065
96538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.3506596538
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.1554161096
Short name T2664
Test name
Test status
Simulation time 180029587 ps
CPU time 0.91 seconds
Started Jul 26 05:12:43 PM PDT 24
Finished Jul 26 05:12:44 PM PDT 24
Peak memory 207040 kb
Host smart-55ecacc5-ce90-4188-9550-08054e4d5644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15541
61096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.1554161096
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.3733293883
Short name T2147
Test name
Test status
Simulation time 457386429 ps
CPU time 1.56 seconds
Started Jul 26 05:12:28 PM PDT 24
Finished Jul 26 05:12:29 PM PDT 24
Peak memory 207044 kb
Host smart-d8b9f7c2-9f90-49af-b493-da2221bdb5fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37332
93883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.3733293883
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.791762786
Short name T427
Test name
Test status
Simulation time 1298947619 ps
CPU time 3.24 seconds
Started Jul 26 05:12:30 PM PDT 24
Finished Jul 26 05:12:34 PM PDT 24
Peak memory 207284 kb
Host smart-258f2ea1-2cef-4455-a49d-55025ae392b7
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=791762786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.791762786
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.2836761636
Short name T2756
Test name
Test status
Simulation time 18614213384 ps
CPU time 50.56 seconds
Started Jul 26 05:12:33 PM PDT 24
Finished Jul 26 05:13:23 PM PDT 24
Peak memory 207396 kb
Host smart-7153f8ad-8539-4de5-ae6f-8596367ef938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28367
61636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.2836761636
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_device_timeout.2975435104
Short name T2393
Test name
Test status
Simulation time 1704857874 ps
CPU time 39.9 seconds
Started Jul 26 05:12:42 PM PDT 24
Finished Jul 26 05:13:22 PM PDT 24
Peak memory 207296 kb
Host smart-52b8d8e6-2f95-4032-981d-a252da2fad14
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975435104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_timeout.2975435104
Directory /workspace/30.usbdev_device_timeout/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.1481140623
Short name T2425
Test name
Test status
Simulation time 376352516 ps
CPU time 1.39 seconds
Started Jul 26 05:12:52 PM PDT 24
Finished Jul 26 05:12:54 PM PDT 24
Peak memory 207016 kb
Host smart-6b7897fe-72b5-44fe-abc8-c047dfb6bcc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14811
40623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.1481140623
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.1174347301
Short name T1943
Test name
Test status
Simulation time 147749214 ps
CPU time 0.82 seconds
Started Jul 26 05:12:32 PM PDT 24
Finished Jul 26 05:12:33 PM PDT 24
Peak memory 206992 kb
Host smart-868dda99-3243-4212-a6e3-970c269db39b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11743
47301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.1174347301
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.2277358100
Short name T907
Test name
Test status
Simulation time 84012507 ps
CPU time 0.75 seconds
Started Jul 26 05:12:30 PM PDT 24
Finished Jul 26 05:12:31 PM PDT 24
Peak memory 207044 kb
Host smart-2e4a5811-4d5c-4484-85ec-c3b46b3c2ffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22773
58100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.2277358100
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.243625492
Short name T774
Test name
Test status
Simulation time 768963849 ps
CPU time 2.25 seconds
Started Jul 26 05:12:29 PM PDT 24
Finished Jul 26 05:12:32 PM PDT 24
Peak memory 207400 kb
Host smart-ef9272f6-e43c-47f0-8c03-e87bd6b50a4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24362
5492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.243625492
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.879987602
Short name T2349
Test name
Test status
Simulation time 233710973 ps
CPU time 1.57 seconds
Started Jul 26 05:12:29 PM PDT 24
Finished Jul 26 05:12:31 PM PDT 24
Peak memory 207288 kb
Host smart-5d36243f-f948-4a80-a22d-194b094192f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87998
7602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.879987602
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.3996762977
Short name T2145
Test name
Test status
Simulation time 200874927 ps
CPU time 1.01 seconds
Started Jul 26 05:12:36 PM PDT 24
Finished Jul 26 05:12:37 PM PDT 24
Peak memory 207220 kb
Host smart-7c261f96-a043-4511-bf57-457697167a08
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3996762977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.3996762977
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.1418534183
Short name T1026
Test name
Test status
Simulation time 142733389 ps
CPU time 0.79 seconds
Started Jul 26 05:12:35 PM PDT 24
Finished Jul 26 05:12:36 PM PDT 24
Peak memory 207004 kb
Host smart-c7a0a2ce-7f96-4134-8315-38cac9455207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14185
34183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.1418534183
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.2986931052
Short name T845
Test name
Test status
Simulation time 225633871 ps
CPU time 0.92 seconds
Started Jul 26 05:12:32 PM PDT 24
Finished Jul 26 05:12:33 PM PDT 24
Peak memory 206940 kb
Host smart-da3e3c6b-5392-4b90-8176-0de896390908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29869
31052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.2986931052
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_invalid_sync.1914384532
Short name T1372
Test name
Test status
Simulation time 8040359982 ps
CPU time 249.41 seconds
Started Jul 26 05:12:31 PM PDT 24
Finished Jul 26 05:16:41 PM PDT 24
Peak memory 215560 kb
Host smart-9d3c88cc-2402-4429-9b33-8375e0a11662
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1914384532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.1914384532
Directory /workspace/30.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/30.usbdev_iso_retraction.2095784778
Short name T1492
Test name
Test status
Simulation time 4184683221 ps
CPU time 51.19 seconds
Started Jul 26 05:12:35 PM PDT 24
Finished Jul 26 05:13:26 PM PDT 24
Peak memory 207252 kb
Host smart-3681d632-e34d-43dc-ad3c-6448808b6f89
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2095784778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_iso_retraction.2095784778
Directory /workspace/30.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.1396687324
Short name T2631
Test name
Test status
Simulation time 233692734 ps
CPU time 1.08 seconds
Started Jul 26 05:12:27 PM PDT 24
Finished Jul 26 05:12:28 PM PDT 24
Peak memory 207000 kb
Host smart-da293b68-4972-4306-8955-15e497f8f815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13966
87324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.1396687324
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.2551839246
Short name T1436
Test name
Test status
Simulation time 23360064424 ps
CPU time 33.19 seconds
Started Jul 26 05:12:30 PM PDT 24
Finished Jul 26 05:13:04 PM PDT 24
Peak memory 207260 kb
Host smart-64ad20fe-4d14-4036-8afa-ef6021c76fbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25518
39246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.2551839246
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.516650258
Short name T1890
Test name
Test status
Simulation time 3290692520 ps
CPU time 4.8 seconds
Started Jul 26 05:12:32 PM PDT 24
Finished Jul 26 05:12:37 PM PDT 24
Peak memory 207268 kb
Host smart-64263966-3393-44d0-8877-3ec29e885484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51665
0258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.516650258
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.1496614236
Short name T732
Test name
Test status
Simulation time 6415716902 ps
CPU time 175.35 seconds
Started Jul 26 05:12:42 PM PDT 24
Finished Jul 26 05:15:37 PM PDT 24
Peak memory 215500 kb
Host smart-b2feec16-233c-45bd-a518-8f419588fc2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14966
14236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.1496614236
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.3761205745
Short name T2236
Test name
Test status
Simulation time 7167474912 ps
CPU time 64.89 seconds
Started Jul 26 05:12:28 PM PDT 24
Finished Jul 26 05:13:33 PM PDT 24
Peak memory 207328 kb
Host smart-cda2b211-2aea-4eca-b315-ce84300a0051
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3761205745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.3761205745
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.741628244
Short name T602
Test name
Test status
Simulation time 251547662 ps
CPU time 1.03 seconds
Started Jul 26 05:12:30 PM PDT 24
Finished Jul 26 05:12:31 PM PDT 24
Peak memory 207020 kb
Host smart-83748b09-32df-4a1f-8efc-261f06425811
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=741628244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.741628244
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.3381975820
Short name T95
Test name
Test status
Simulation time 191610801 ps
CPU time 0.92 seconds
Started Jul 26 05:12:27 PM PDT 24
Finished Jul 26 05:12:28 PM PDT 24
Peak memory 207128 kb
Host smart-6cfad49a-7db6-4693-a354-8f77539384af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33819
75820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.3381975820
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.1803212719
Short name T1516
Test name
Test status
Simulation time 5173715690 ps
CPU time 40.5 seconds
Started Jul 26 05:12:43 PM PDT 24
Finished Jul 26 05:13:23 PM PDT 24
Peak memory 217124 kb
Host smart-44ea652f-96a3-4c56-8c89-3b3251ed2a5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18032
12719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.1803212719
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.1416161332
Short name T1759
Test name
Test status
Simulation time 4734734098 ps
CPU time 138.59 seconds
Started Jul 26 05:12:30 PM PDT 24
Finished Jul 26 05:14:49 PM PDT 24
Peak memory 215432 kb
Host smart-80e7be0a-b888-4012-99be-71b431c374bc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1416161332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.1416161332
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.2603211119
Short name T203
Test name
Test status
Simulation time 194302760 ps
CPU time 0.97 seconds
Started Jul 26 05:12:31 PM PDT 24
Finished Jul 26 05:12:32 PM PDT 24
Peak memory 207088 kb
Host smart-28820e52-d8a4-43fe-bcd2-f3acbc23cebf
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2603211119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.2603211119
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.1305544868
Short name T624
Test name
Test status
Simulation time 153401965 ps
CPU time 0.86 seconds
Started Jul 26 05:12:31 PM PDT 24
Finished Jul 26 05:12:32 PM PDT 24
Peak memory 206940 kb
Host smart-74c88204-dcb8-42b8-8bc6-54dac7f93529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13055
44868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.1305544868
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.313582623
Short name T132
Test name
Test status
Simulation time 199713069 ps
CPU time 0.9 seconds
Started Jul 26 05:12:43 PM PDT 24
Finished Jul 26 05:12:44 PM PDT 24
Peak memory 207072 kb
Host smart-53688305-b641-4583-a3c0-b02c7a8f5702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31358
2623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.313582623
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.733289867
Short name T730
Test name
Test status
Simulation time 176040791 ps
CPU time 0.91 seconds
Started Jul 26 05:12:36 PM PDT 24
Finished Jul 26 05:12:37 PM PDT 24
Peak memory 207032 kb
Host smart-5f42f4ae-61fb-4cf2-9601-be1d2a81c69e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73328
9867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.733289867
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.1891551973
Short name T1709
Test name
Test status
Simulation time 170177995 ps
CPU time 0.94 seconds
Started Jul 26 05:12:52 PM PDT 24
Finished Jul 26 05:12:53 PM PDT 24
Peak memory 207016 kb
Host smart-931b626b-7e5a-4db8-9e85-77f9d25d826c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18915
51973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.1891551973
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.1773039029
Short name T456
Test name
Test status
Simulation time 176440723 ps
CPU time 0.88 seconds
Started Jul 26 05:12:32 PM PDT 24
Finished Jul 26 05:12:33 PM PDT 24
Peak memory 207132 kb
Host smart-999f11b9-0b33-45b7-995e-b3424324711b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17730
39029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.1773039029
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.362578325
Short name T1737
Test name
Test status
Simulation time 159139103 ps
CPU time 0.91 seconds
Started Jul 26 05:12:41 PM PDT 24
Finished Jul 26 05:12:42 PM PDT 24
Peak memory 207108 kb
Host smart-d76bc1c7-f75c-4e8f-be2b-1df107894080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36257
8325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.362578325
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.2731738238
Short name T2116
Test name
Test status
Simulation time 170209499 ps
CPU time 0.92 seconds
Started Jul 26 05:12:42 PM PDT 24
Finished Jul 26 05:12:44 PM PDT 24
Peak memory 207104 kb
Host smart-2d04641a-e8c7-40aa-8613-33debbaa883e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2731738238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.2731738238
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.604089285
Short name T391
Test name
Test status
Simulation time 147525438 ps
CPU time 0.83 seconds
Started Jul 26 05:12:45 PM PDT 24
Finished Jul 26 05:12:46 PM PDT 24
Peak memory 207024 kb
Host smart-92d53989-0f62-4669-84c9-09cef7c10664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60408
9285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.604089285
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.1351225374
Short name T1911
Test name
Test status
Simulation time 39989747 ps
CPU time 0.72 seconds
Started Jul 26 05:12:42 PM PDT 24
Finished Jul 26 05:12:43 PM PDT 24
Peak memory 207024 kb
Host smart-6302bb5a-8ed0-4201-a38c-249df368cdaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13512
25374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.1351225374
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.532215062
Short name T1914
Test name
Test status
Simulation time 8561143229 ps
CPU time 21.95 seconds
Started Jul 26 05:12:42 PM PDT 24
Finished Jul 26 05:13:05 PM PDT 24
Peak memory 215528 kb
Host smart-53ab5547-a036-4e9d-be2f-b0b34d2859c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53221
5062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.532215062
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.343189014
Short name T655
Test name
Test status
Simulation time 176613637 ps
CPU time 0.91 seconds
Started Jul 26 05:12:41 PM PDT 24
Finished Jul 26 05:12:42 PM PDT 24
Peak memory 207100 kb
Host smart-c0e1ebea-1dc0-4b94-9c0e-820c82cab97f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34318
9014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.343189014
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.3095884543
Short name T766
Test name
Test status
Simulation time 236846504 ps
CPU time 1.1 seconds
Started Jul 26 05:12:39 PM PDT 24
Finished Jul 26 05:12:40 PM PDT 24
Peak memory 207104 kb
Host smart-c698a11e-fd7e-4a87-bd24-82325556e23c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30958
84543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.3095884543
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.1072552388
Short name T1187
Test name
Test status
Simulation time 181892401 ps
CPU time 0.92 seconds
Started Jul 26 05:12:42 PM PDT 24
Finished Jul 26 05:12:44 PM PDT 24
Peak memory 207128 kb
Host smart-fd5b7aef-735d-4e52-b50c-f33c630c0860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10725
52388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.1072552388
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.694651502
Short name T2442
Test name
Test status
Simulation time 175462725 ps
CPU time 0.91 seconds
Started Jul 26 05:12:40 PM PDT 24
Finished Jul 26 05:12:41 PM PDT 24
Peak memory 207096 kb
Host smart-d106e4bb-ce3d-4c40-ae3c-42ae9b985363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69465
1502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.694651502
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.3228309837
Short name T2559
Test name
Test status
Simulation time 141103738 ps
CPU time 0.84 seconds
Started Jul 26 05:12:40 PM PDT 24
Finished Jul 26 05:12:41 PM PDT 24
Peak memory 207048 kb
Host smart-f5dc2bb9-a067-46e3-af2d-32880e6748c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32283
09837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.3228309837
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.355934802
Short name T2851
Test name
Test status
Simulation time 154190897 ps
CPU time 0.84 seconds
Started Jul 26 05:12:41 PM PDT 24
Finished Jul 26 05:12:42 PM PDT 24
Peak memory 206984 kb
Host smart-67458b66-d79a-4267-b1e9-b902b031d2b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35593
4802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.355934802
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.3778622745
Short name T512
Test name
Test status
Simulation time 165229495 ps
CPU time 0.88 seconds
Started Jul 26 05:12:46 PM PDT 24
Finished Jul 26 05:12:48 PM PDT 24
Peak memory 206888 kb
Host smart-9b64597a-e12c-4963-bbb2-3ed628289fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37786
22745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.3778622745
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.2258276619
Short name T2407
Test name
Test status
Simulation time 216477349 ps
CPU time 1.02 seconds
Started Jul 26 05:12:42 PM PDT 24
Finished Jul 26 05:12:44 PM PDT 24
Peak memory 207056 kb
Host smart-e896c1c3-be8f-43d1-b331-0e766b330aca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22582
76619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.2258276619
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.4180451215
Short name T342
Test name
Test status
Simulation time 3966410880 ps
CPU time 30.48 seconds
Started Jul 26 05:12:39 PM PDT 24
Finished Jul 26 05:13:10 PM PDT 24
Peak memory 217120 kb
Host smart-fadb0e2a-c1cd-4e32-8edb-b964c848f871
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4180451215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.4180451215
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.360280681
Short name T1727
Test name
Test status
Simulation time 181143437 ps
CPU time 0.93 seconds
Started Jul 26 05:12:43 PM PDT 24
Finished Jul 26 05:12:44 PM PDT 24
Peak memory 207072 kb
Host smart-fdd518ab-310f-4e39-8026-387a864bf909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36028
0681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.360280681
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.170383126
Short name T1982
Test name
Test status
Simulation time 177355020 ps
CPU time 0.89 seconds
Started Jul 26 05:12:39 PM PDT 24
Finished Jul 26 05:12:41 PM PDT 24
Peak memory 207100 kb
Host smart-c974a477-0a23-45b7-8965-aa303968302a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17038
3126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.170383126
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.1949528202
Short name T362
Test name
Test status
Simulation time 507621317 ps
CPU time 1.59 seconds
Started Jul 26 05:12:41 PM PDT 24
Finished Jul 26 05:12:43 PM PDT 24
Peak memory 207092 kb
Host smart-5665ca69-2e03-4ddd-a628-a22947f93163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19495
28202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.1949528202
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.3701292495
Short name T1622
Test name
Test status
Simulation time 5134572533 ps
CPU time 56.84 seconds
Started Jul 26 05:12:41 PM PDT 24
Finished Jul 26 05:13:38 PM PDT 24
Peak memory 216776 kb
Host smart-d705a17e-06c6-48d0-9892-aa290fe22721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37012
92495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.3701292495
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/30.usbdev_timeout_missing_host_handshake.3412088815
Short name T962
Test name
Test status
Simulation time 1535201622 ps
CPU time 37.37 seconds
Started Jul 26 05:12:30 PM PDT 24
Finished Jul 26 05:13:07 PM PDT 24
Peak memory 207176 kb
Host smart-c83f8400-e44d-4c81-a876-1ead4c132047
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412088815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_timeout_missing_hos
t_handshake.3412088815
Directory /workspace/30.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.808274308
Short name T1801
Test name
Test status
Simulation time 37400720 ps
CPU time 0.61 seconds
Started Jul 26 05:12:54 PM PDT 24
Finished Jul 26 05:12:55 PM PDT 24
Peak memory 207040 kb
Host smart-55f003b6-fb41-4f06-89f4-fbc439b15c43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=808274308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.808274308
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.1366743685
Short name T968
Test name
Test status
Simulation time 3453403260 ps
CPU time 4.92 seconds
Started Jul 26 05:12:42 PM PDT 24
Finished Jul 26 05:12:47 PM PDT 24
Peak memory 207376 kb
Host smart-15f3208b-1961-4c7e-bd7c-f47e5dc9831d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366743685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_a
on_wake_disconnect.1366743685
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.3706999810
Short name T828
Test name
Test status
Simulation time 13326353146 ps
CPU time 17.41 seconds
Started Jul 26 05:12:40 PM PDT 24
Finished Jul 26 05:12:58 PM PDT 24
Peak memory 207284 kb
Host smart-fff143c3-a985-4f8a-a3ce-6bc2bccf1336
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706999810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.3706999810
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.1303308223
Short name T2728
Test name
Test status
Simulation time 23368787955 ps
CPU time 28 seconds
Started Jul 26 05:12:47 PM PDT 24
Finished Jul 26 05:13:15 PM PDT 24
Peak memory 207272 kb
Host smart-2db7e837-f5dc-4b8b-8bef-2f3114669b8b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303308223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_a
on_wake_resume.1303308223
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.4188788108
Short name T1028
Test name
Test status
Simulation time 150444479 ps
CPU time 0.85 seconds
Started Jul 26 05:12:41 PM PDT 24
Finished Jul 26 05:12:42 PM PDT 24
Peak memory 206996 kb
Host smart-568c7ace-707a-4280-b389-a08bf797d5fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41887
88108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.4188788108
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.2466855100
Short name T1301
Test name
Test status
Simulation time 139492103 ps
CPU time 0.82 seconds
Started Jul 26 05:12:43 PM PDT 24
Finished Jul 26 05:12:44 PM PDT 24
Peak memory 207068 kb
Host smart-8398a8b9-d82d-406f-b37d-90f2d0aa6949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24668
55100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.2466855100
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.1831393212
Short name T93
Test name
Test status
Simulation time 529556568 ps
CPU time 1.87 seconds
Started Jul 26 05:12:39 PM PDT 24
Finished Jul 26 05:12:41 PM PDT 24
Peak memory 207048 kb
Host smart-9ff9cfa3-25eb-47d7-850c-cac6037ac391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18313
93212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.1831393212
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.1214456658
Short name T1791
Test name
Test status
Simulation time 488114117 ps
CPU time 1.8 seconds
Started Jul 26 05:12:39 PM PDT 24
Finished Jul 26 05:12:41 PM PDT 24
Peak memory 207136 kb
Host smart-a395131d-d0b7-44a8-86b6-4cc41eb22a8e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1214456658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.1214456658
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.844804694
Short name T170
Test name
Test status
Simulation time 19928611266 ps
CPU time 40.79 seconds
Started Jul 26 05:12:41 PM PDT 24
Finished Jul 26 05:13:22 PM PDT 24
Peak memory 207404 kb
Host smart-bd3f26b8-f471-431f-80d6-fd1fd0c78491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84480
4694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.844804694
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_device_timeout.1599502842
Short name T714
Test name
Test status
Simulation time 4304530360 ps
CPU time 42.1 seconds
Started Jul 26 05:12:39 PM PDT 24
Finished Jul 26 05:13:22 PM PDT 24
Peak memory 207240 kb
Host smart-5c5f9436-002c-4427-81a9-558bfca1db94
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599502842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_timeout.1599502842
Directory /workspace/31.usbdev_device_timeout/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.1077572357
Short name T268
Test name
Test status
Simulation time 325697215 ps
CPU time 1.3 seconds
Started Jul 26 05:12:41 PM PDT 24
Finished Jul 26 05:12:42 PM PDT 24
Peak memory 207096 kb
Host smart-01fbea94-a937-44b4-b773-cfcfa7f0d648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10775
72357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.1077572357
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.2855845955
Short name T2000
Test name
Test status
Simulation time 142744658 ps
CPU time 0.84 seconds
Started Jul 26 05:12:40 PM PDT 24
Finished Jul 26 05:12:41 PM PDT 24
Peak memory 207120 kb
Host smart-5c3a53c8-8175-4c19-8988-0ac876f75956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28558
45955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.2855845955
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.320656406
Short name T525
Test name
Test status
Simulation time 87441129 ps
CPU time 0.75 seconds
Started Jul 26 05:12:45 PM PDT 24
Finished Jul 26 05:12:45 PM PDT 24
Peak memory 207044 kb
Host smart-1227cfcf-e695-4f3e-839c-dd1c159babfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32065
6406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.320656406
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.1681409074
Short name T1597
Test name
Test status
Simulation time 1024761274 ps
CPU time 2.48 seconds
Started Jul 26 05:12:42 PM PDT 24
Finished Jul 26 05:12:44 PM PDT 24
Peak memory 207192 kb
Host smart-d8dfc426-a7a0-40e4-a042-b83323c0ee7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16814
09074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.1681409074
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.3126004428
Short name T1558
Test name
Test status
Simulation time 183827412 ps
CPU time 1.87 seconds
Started Jul 26 05:12:43 PM PDT 24
Finished Jul 26 05:12:45 PM PDT 24
Peak memory 207280 kb
Host smart-e6921a32-83ec-446c-9b0c-04152cf823db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31260
04428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.3126004428
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.3491842273
Short name T371
Test name
Test status
Simulation time 174276952 ps
CPU time 0.91 seconds
Started Jul 26 05:12:46 PM PDT 24
Finished Jul 26 05:12:48 PM PDT 24
Peak memory 206920 kb
Host smart-15f44ef7-e49c-49f0-9eec-d7903eaaa5c7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3491842273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.3491842273
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.4004335271
Short name T1745
Test name
Test status
Simulation time 206595877 ps
CPU time 0.91 seconds
Started Jul 26 05:12:43 PM PDT 24
Finished Jul 26 05:12:44 PM PDT 24
Peak memory 207028 kb
Host smart-41549c95-70d1-4894-a8a7-cd55f2cc47a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40043
35271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.4004335271
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.2914928577
Short name T1449
Test name
Test status
Simulation time 294202639 ps
CPU time 1.08 seconds
Started Jul 26 05:12:41 PM PDT 24
Finished Jul 26 05:12:42 PM PDT 24
Peak memory 207064 kb
Host smart-d37c0f10-e824-47b7-95bc-d1702d027fba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29149
28577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.2914928577
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.2694989451
Short name T2076
Test name
Test status
Simulation time 7427408888 ps
CPU time 220.22 seconds
Started Jul 26 05:12:40 PM PDT 24
Finished Jul 26 05:16:21 PM PDT 24
Peak memory 215604 kb
Host smart-ab48a3bb-8170-4fa7-aad2-25df5eaf959a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2694989451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.2694989451
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.1877012627
Short name T1315
Test name
Test status
Simulation time 158709199 ps
CPU time 0.87 seconds
Started Jul 26 05:12:40 PM PDT 24
Finished Jul 26 05:12:41 PM PDT 24
Peak memory 207128 kb
Host smart-94a25f95-f450-4531-b825-9ca94d07e1c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18770
12627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.1877012627
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.1922726303
Short name T2791
Test name
Test status
Simulation time 23335404906 ps
CPU time 28.19 seconds
Started Jul 26 05:12:40 PM PDT 24
Finished Jul 26 05:13:09 PM PDT 24
Peak memory 207328 kb
Host smart-516bee02-43cb-41de-b9dc-5622649d8199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19227
26303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.1922726303
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.1075516508
Short name T1135
Test name
Test status
Simulation time 3357008136 ps
CPU time 6.07 seconds
Started Jul 26 05:12:44 PM PDT 24
Finished Jul 26 05:12:50 PM PDT 24
Peak memory 207348 kb
Host smart-76d73760-d347-41bb-af3b-42801f055b40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10755
16508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.1075516508
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.2797597409
Short name T2194
Test name
Test status
Simulation time 5961174739 ps
CPU time 170.71 seconds
Started Jul 26 05:12:47 PM PDT 24
Finished Jul 26 05:15:37 PM PDT 24
Peak memory 215524 kb
Host smart-69319bdc-e2e0-4e79-8d1c-3ba89dc1af4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27975
97409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.2797597409
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.1709081631
Short name T2074
Test name
Test status
Simulation time 5542197437 ps
CPU time 57.15 seconds
Started Jul 26 05:12:42 PM PDT 24
Finished Jul 26 05:13:39 PM PDT 24
Peak memory 207444 kb
Host smart-171beb20-158f-4ea3-878c-b584fa83cce4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1709081631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.1709081631
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.4186862068
Short name T333
Test name
Test status
Simulation time 240667536 ps
CPU time 1.04 seconds
Started Jul 26 05:12:40 PM PDT 24
Finished Jul 26 05:12:41 PM PDT 24
Peak memory 207072 kb
Host smart-e838e15f-4767-41a0-b849-41597fcb6c89
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4186862068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.4186862068
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.3168182744
Short name T1365
Test name
Test status
Simulation time 217079769 ps
CPU time 1.02 seconds
Started Jul 26 05:12:43 PM PDT 24
Finished Jul 26 05:12:44 PM PDT 24
Peak memory 207096 kb
Host smart-0d070cf4-5e1a-4ba7-a933-e7d790d524af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31681
82744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.3168182744
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.3905486765
Short name T896
Test name
Test status
Simulation time 4649527755 ps
CPU time 37.38 seconds
Started Jul 26 05:12:39 PM PDT 24
Finished Jul 26 05:13:16 PM PDT 24
Peak memory 216752 kb
Host smart-320e91f5-5661-41e2-b334-93e53975031d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39054
86765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.3905486765
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.3257217833
Short name T2417
Test name
Test status
Simulation time 7877452514 ps
CPU time 62.2 seconds
Started Jul 26 05:12:46 PM PDT 24
Finished Jul 26 05:13:49 PM PDT 24
Peak memory 207224 kb
Host smart-5406f897-dafe-4e2f-90d4-22b629622314
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3257217833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.3257217833
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.930431819
Short name T34
Test name
Test status
Simulation time 150336589 ps
CPU time 1 seconds
Started Jul 26 05:12:41 PM PDT 24
Finished Jul 26 05:12:42 PM PDT 24
Peak memory 207112 kb
Host smart-20ded8f5-53d8-460e-b9be-56c438008ad8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=930431819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.930431819
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.3887326290
Short name T1172
Test name
Test status
Simulation time 148756622 ps
CPU time 0.88 seconds
Started Jul 26 05:12:41 PM PDT 24
Finished Jul 26 05:12:42 PM PDT 24
Peak memory 207156 kb
Host smart-a9e607af-7f5d-4cf1-b6f1-548f4cf6d215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38873
26290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.3887326290
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.1831990207
Short name T138
Test name
Test status
Simulation time 202278931 ps
CPU time 0.87 seconds
Started Jul 26 05:12:38 PM PDT 24
Finished Jul 26 05:12:39 PM PDT 24
Peak memory 207012 kb
Host smart-c08d22b8-2266-4695-bce1-8ffb255895c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18319
90207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.1831990207
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.2056591635
Short name T1829
Test name
Test status
Simulation time 183529188 ps
CPU time 0.9 seconds
Started Jul 26 05:12:43 PM PDT 24
Finished Jul 26 05:12:44 PM PDT 24
Peak memory 207100 kb
Host smart-cf3f55d5-fb91-4795-9401-5bd5c9b89709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20565
91635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.2056591635
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.1083021395
Short name T2812
Test name
Test status
Simulation time 170302870 ps
CPU time 0.86 seconds
Started Jul 26 05:12:45 PM PDT 24
Finished Jul 26 05:12:46 PM PDT 24
Peak memory 207080 kb
Host smart-e3c32392-83f7-4e38-a27a-dda6dade6ec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10830
21395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.1083021395
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.1816943973
Short name T2456
Test name
Test status
Simulation time 189547163 ps
CPU time 0.88 seconds
Started Jul 26 05:12:41 PM PDT 24
Finished Jul 26 05:12:42 PM PDT 24
Peak memory 206940 kb
Host smart-c189d67f-d16d-411d-8075-01a07932f39b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18169
43973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.1816943973
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.199412306
Short name T2049
Test name
Test status
Simulation time 160886361 ps
CPU time 0.89 seconds
Started Jul 26 05:12:44 PM PDT 24
Finished Jul 26 05:12:45 PM PDT 24
Peak memory 207088 kb
Host smart-e038c169-ec4b-4497-b30a-9e5b9d26a9c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19941
2306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.199412306
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.1116531244
Short name T2213
Test name
Test status
Simulation time 247621966 ps
CPU time 1.01 seconds
Started Jul 26 05:12:51 PM PDT 24
Finished Jul 26 05:12:52 PM PDT 24
Peak memory 207048 kb
Host smart-2991ce66-3dbf-40ad-94cc-0bb42972fcda
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1116531244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.1116531244
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.225109738
Short name T721
Test name
Test status
Simulation time 148372202 ps
CPU time 0.88 seconds
Started Jul 26 05:12:53 PM PDT 24
Finished Jul 26 05:12:54 PM PDT 24
Peak memory 207012 kb
Host smart-4446f350-4772-49ee-8b5d-385fca7704ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22510
9738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.225109738
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.1171060187
Short name T1480
Test name
Test status
Simulation time 47906419 ps
CPU time 0.72 seconds
Started Jul 26 05:12:54 PM PDT 24
Finished Jul 26 05:12:55 PM PDT 24
Peak memory 207032 kb
Host smart-33a2a41e-b3b5-49f0-82f6-f5db2072c050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11710
60187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.1171060187
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.2362448937
Short name T1740
Test name
Test status
Simulation time 16248828505 ps
CPU time 38.47 seconds
Started Jul 26 05:12:56 PM PDT 24
Finished Jul 26 05:13:34 PM PDT 24
Peak memory 215504 kb
Host smart-bd65721c-7d8b-4213-8acf-47a68da5998b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23624
48937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.2362448937
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.457873151
Short name T2057
Test name
Test status
Simulation time 176880490 ps
CPU time 0.87 seconds
Started Jul 26 05:12:52 PM PDT 24
Finished Jul 26 05:12:53 PM PDT 24
Peak memory 207100 kb
Host smart-eb7d152d-78ff-4095-b865-f0144b666f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45787
3151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.457873151
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.1928051007
Short name T1329
Test name
Test status
Simulation time 227184514 ps
CPU time 1.1 seconds
Started Jul 26 05:12:51 PM PDT 24
Finished Jul 26 05:12:52 PM PDT 24
Peak memory 207072 kb
Host smart-ad0d263c-a719-48de-9415-91fd4a0da552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19280
51007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.1928051007
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.1273209127
Short name T2358
Test name
Test status
Simulation time 197587987 ps
CPU time 0.89 seconds
Started Jul 26 05:12:53 PM PDT 24
Finished Jul 26 05:12:54 PM PDT 24
Peak memory 207056 kb
Host smart-dcff86ee-9226-45a6-a9cb-ae5f492f4cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12732
09127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.1273209127
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.573929292
Short name T1965
Test name
Test status
Simulation time 161120250 ps
CPU time 0.83 seconds
Started Jul 26 05:12:51 PM PDT 24
Finished Jul 26 05:12:52 PM PDT 24
Peak memory 207152 kb
Host smart-4a06b965-c985-4251-b974-18fd2e4292d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57392
9292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.573929292
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.3775437738
Short name T49
Test name
Test status
Simulation time 137758528 ps
CPU time 0.87 seconds
Started Jul 26 05:12:51 PM PDT 24
Finished Jul 26 05:12:52 PM PDT 24
Peak memory 207100 kb
Host smart-52382e25-3391-4f60-8ccd-93f58d828c97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37754
37738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.3775437738
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.3422499251
Short name T2490
Test name
Test status
Simulation time 149692812 ps
CPU time 0.84 seconds
Started Jul 26 05:12:55 PM PDT 24
Finished Jul 26 05:12:56 PM PDT 24
Peak memory 207068 kb
Host smart-907cfe6b-ccf7-40c0-a5a8-641d48835fb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34224
99251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.3422499251
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.3461846958
Short name T2781
Test name
Test status
Simulation time 153245879 ps
CPU time 0.85 seconds
Started Jul 26 05:12:51 PM PDT 24
Finished Jul 26 05:12:52 PM PDT 24
Peak memory 207084 kb
Host smart-1d7150fe-3f6b-4048-811e-9d8a880691f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34618
46958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.3461846958
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.1606512274
Short name T1356
Test name
Test status
Simulation time 261683795 ps
CPU time 1.09 seconds
Started Jul 26 05:12:51 PM PDT 24
Finished Jul 26 05:12:52 PM PDT 24
Peak memory 206932 kb
Host smart-0b35f2aa-cb7a-4d64-aa26-2ec4da453063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16065
12274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.1606512274
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.1954585754
Short name T2073
Test name
Test status
Simulation time 4173539101 ps
CPU time 33.25 seconds
Started Jul 26 05:12:53 PM PDT 24
Finished Jul 26 05:13:26 PM PDT 24
Peak memory 217196 kb
Host smart-2f4cd6db-6c8d-4962-ab60-d1c2598c12c5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1954585754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.1954585754
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.2485321557
Short name T1037
Test name
Test status
Simulation time 184408067 ps
CPU time 0.92 seconds
Started Jul 26 05:12:55 PM PDT 24
Finished Jul 26 05:12:57 PM PDT 24
Peak memory 207100 kb
Host smart-9f768f47-27a3-451f-bf27-b5532601b8c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24853
21557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.2485321557
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.1190002685
Short name T2592
Test name
Test status
Simulation time 175615277 ps
CPU time 0.91 seconds
Started Jul 26 05:12:53 PM PDT 24
Finished Jul 26 05:12:54 PM PDT 24
Peak memory 206980 kb
Host smart-2dc14b36-8b15-43a6-8fb3-7afaf631aff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11900
02685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.1190002685
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.295676689
Short name T582
Test name
Test status
Simulation time 451212739 ps
CPU time 1.31 seconds
Started Jul 26 05:12:54 PM PDT 24
Finished Jul 26 05:12:56 PM PDT 24
Peak memory 207036 kb
Host smart-d35b4784-c085-4f2d-b24f-7aa4f21ae015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29567
6689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.295676689
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.900042622
Short name T1277
Test name
Test status
Simulation time 6030468503 ps
CPU time 182.99 seconds
Started Jul 26 05:12:54 PM PDT 24
Finished Jul 26 05:15:57 PM PDT 24
Peak memory 215592 kb
Host smart-e35dcbb0-4e62-4b57-8b08-b11bf90aad6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90004
2622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.900042622
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_timeout_missing_host_handshake.853470080
Short name T969
Test name
Test status
Simulation time 3443393700 ps
CPU time 31.09 seconds
Started Jul 26 05:12:39 PM PDT 24
Finished Jul 26 05:13:10 PM PDT 24
Peak memory 207436 kb
Host smart-e3433b2c-3ed5-43e8-9fcc-73cf75c8b688
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853470080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_timeout_missing_host
_handshake.853470080
Directory /workspace/31.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.4150611473
Short name T1077
Test name
Test status
Simulation time 48128889 ps
CPU time 0.68 seconds
Started Jul 26 05:13:03 PM PDT 24
Finished Jul 26 05:13:04 PM PDT 24
Peak memory 207132 kb
Host smart-731d6390-835a-4af3-bde0-bbd2dc5db8c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4150611473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.4150611473
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.3209276116
Short name T1621
Test name
Test status
Simulation time 4230854269 ps
CPU time 6.45 seconds
Started Jul 26 05:12:56 PM PDT 24
Finished Jul 26 05:13:02 PM PDT 24
Peak memory 207376 kb
Host smart-154b91b0-b3fe-4608-aa82-4d0683b515a8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209276116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_disconnect.3209276116
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.3145252113
Short name T777
Test name
Test status
Simulation time 13348406220 ps
CPU time 16.01 seconds
Started Jul 26 05:12:54 PM PDT 24
Finished Jul 26 05:13:10 PM PDT 24
Peak memory 207316 kb
Host smart-68ea78bb-5a55-4845-a328-cf5badacf413
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145252113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.3145252113
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.3367940968
Short name T1919
Test name
Test status
Simulation time 23359525246 ps
CPU time 27.94 seconds
Started Jul 26 05:12:54 PM PDT 24
Finished Jul 26 05:13:22 PM PDT 24
Peak memory 207360 kb
Host smart-11a1400c-0b5a-4ff1-bd11-bcb4cd09af71
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367940968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_resume.3367940968
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.1588595343
Short name T1980
Test name
Test status
Simulation time 140195085 ps
CPU time 0.83 seconds
Started Jul 26 05:12:56 PM PDT 24
Finished Jul 26 05:12:57 PM PDT 24
Peak memory 207136 kb
Host smart-786dbc61-5e99-4866-9385-49cabf96f457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15885
95343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.1588595343
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.2464257952
Short name T81
Test name
Test status
Simulation time 156822139 ps
CPU time 0.86 seconds
Started Jul 26 05:12:54 PM PDT 24
Finished Jul 26 05:12:55 PM PDT 24
Peak memory 207032 kb
Host smart-561735e9-8810-47fd-9a3a-6cb3473a52cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24642
57952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.2464257952
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.52588812
Short name T2790
Test name
Test status
Simulation time 488132082 ps
CPU time 1.59 seconds
Started Jul 26 05:12:52 PM PDT 24
Finished Jul 26 05:12:53 PM PDT 24
Peak memory 207060 kb
Host smart-364b1a5b-39a6-4e33-8826-db45baefce87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52588
812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.52588812
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.4032591418
Short name T83
Test name
Test status
Simulation time 1466523155 ps
CPU time 3.79 seconds
Started Jul 26 05:12:53 PM PDT 24
Finished Jul 26 05:12:56 PM PDT 24
Peak memory 207260 kb
Host smart-ff67f807-60ce-4b41-bc7b-29f0eab48d1d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4032591418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.4032591418
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.797698058
Short name T2516
Test name
Test status
Simulation time 7862857830 ps
CPU time 19.56 seconds
Started Jul 26 05:12:56 PM PDT 24
Finished Jul 26 05:13:16 PM PDT 24
Peak memory 207412 kb
Host smart-03be75a2-fec5-49a3-ab0f-db62471c2f09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79769
8058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.797698058
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_device_timeout.3300239621
Short name T1237
Test name
Test status
Simulation time 4765834040 ps
CPU time 43.81 seconds
Started Jul 26 05:12:54 PM PDT 24
Finished Jul 26 05:13:37 PM PDT 24
Peak memory 207320 kb
Host smart-1414bfce-ce22-4871-92ad-3588ea62b7ce
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300239621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_timeout.3300239621
Directory /workspace/32.usbdev_device_timeout/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.3875301881
Short name T1739
Test name
Test status
Simulation time 431688977 ps
CPU time 1.42 seconds
Started Jul 26 05:12:54 PM PDT 24
Finished Jul 26 05:12:56 PM PDT 24
Peak memory 207068 kb
Host smart-c7dcd1d6-5bbd-49a2-8c7c-3cb7458f5953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38753
01881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.3875301881
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.3671734283
Short name T1596
Test name
Test status
Simulation time 162755364 ps
CPU time 0.84 seconds
Started Jul 26 05:12:56 PM PDT 24
Finished Jul 26 05:12:57 PM PDT 24
Peak memory 207092 kb
Host smart-0b67d1aa-edfe-42f6-ba54-1859dfb10161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36717
34283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.3671734283
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.1208031498
Short name T2112
Test name
Test status
Simulation time 43029813 ps
CPU time 0.72 seconds
Started Jul 26 05:12:53 PM PDT 24
Finished Jul 26 05:12:53 PM PDT 24
Peak memory 207064 kb
Host smart-0514e7cf-3146-44fa-9dc3-d19f99c37414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12080
31498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.1208031498
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.3999040281
Short name T617
Test name
Test status
Simulation time 1032170794 ps
CPU time 2.62 seconds
Started Jul 26 05:12:52 PM PDT 24
Finished Jul 26 05:12:55 PM PDT 24
Peak memory 207204 kb
Host smart-7f9277d9-78d6-4a18-9ad5-f7e341212e0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39990
40281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.3999040281
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.2741494467
Short name T788
Test name
Test status
Simulation time 254116207 ps
CPU time 1.85 seconds
Started Jul 26 05:12:54 PM PDT 24
Finished Jul 26 05:12:56 PM PDT 24
Peak memory 207356 kb
Host smart-da46a45b-3d16-4d44-9711-9795ce3fe5b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27414
94467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.2741494467
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.1015738767
Short name T1306
Test name
Test status
Simulation time 147016427 ps
CPU time 0.91 seconds
Started Jul 26 05:12:54 PM PDT 24
Finished Jul 26 05:12:55 PM PDT 24
Peak memory 207076 kb
Host smart-3e75780d-22af-4d88-a63c-d27d0724bc57
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1015738767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.1015738767
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.1348858381
Short name T687
Test name
Test status
Simulation time 180875482 ps
CPU time 0.9 seconds
Started Jul 26 05:12:54 PM PDT 24
Finished Jul 26 05:12:55 PM PDT 24
Peak memory 206812 kb
Host smart-bc63dbb3-b3ef-4a4e-9fa0-25aa3fdc7d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13488
58381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.1348858381
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.369177390
Short name T1250
Test name
Test status
Simulation time 172454807 ps
CPU time 0.89 seconds
Started Jul 26 05:12:55 PM PDT 24
Finished Jul 26 05:12:56 PM PDT 24
Peak memory 207124 kb
Host smart-f68d671b-c074-42db-a083-0a13f1ff9f69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36917
7390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.369177390
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_invalid_sync.4035265118
Short name T1175
Test name
Test status
Simulation time 8753861489 ps
CPU time 88.57 seconds
Started Jul 26 05:12:53 PM PDT 24
Finished Jul 26 05:14:21 PM PDT 24
Peak memory 216688 kb
Host smart-4819d316-0369-484b-a70d-72c34496acc6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4035265118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.4035265118
Directory /workspace/32.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/32.usbdev_iso_retraction.3217332882
Short name T2443
Test name
Test status
Simulation time 11907268440 ps
CPU time 84.44 seconds
Started Jul 26 05:12:54 PM PDT 24
Finished Jul 26 05:14:19 PM PDT 24
Peak memory 206844 kb
Host smart-10a2a6af-2234-4150-a27e-f20578cf2565
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3217332882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.3217332882
Directory /workspace/32.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.4157048268
Short name T1075
Test name
Test status
Simulation time 174204859 ps
CPU time 0.94 seconds
Started Jul 26 05:12:55 PM PDT 24
Finished Jul 26 05:12:57 PM PDT 24
Peak memory 207124 kb
Host smart-dfddbf70-c8dd-4c05-a561-7be57d94e4ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41570
48268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.4157048268
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.3756085671
Short name T1650
Test name
Test status
Simulation time 23355275309 ps
CPU time 29.04 seconds
Started Jul 26 05:12:51 PM PDT 24
Finished Jul 26 05:13:20 PM PDT 24
Peak memory 207292 kb
Host smart-b41bf7c6-c53c-46ff-90ca-be5f70753889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37560
85671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.3756085671
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.2390412616
Short name T680
Test name
Test status
Simulation time 3385071951 ps
CPU time 5.94 seconds
Started Jul 26 05:12:54 PM PDT 24
Finished Jul 26 05:13:00 PM PDT 24
Peak memory 207212 kb
Host smart-61d02130-acb8-4993-bda6-8f64b42a7141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23904
12616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.2390412616
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.4233649104
Short name T588
Test name
Test status
Simulation time 7299963657 ps
CPU time 223.27 seconds
Started Jul 26 05:12:54 PM PDT 24
Finished Jul 26 05:16:38 PM PDT 24
Peak memory 215152 kb
Host smart-8ef4f8b1-23c2-4631-b099-1279d8002715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42336
49104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.4233649104
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.3705807535
Short name T1195
Test name
Test status
Simulation time 4856666855 ps
CPU time 138.41 seconds
Started Jul 26 05:12:52 PM PDT 24
Finished Jul 26 05:15:10 PM PDT 24
Peak memory 215532 kb
Host smart-cdefea4e-69d9-481d-8627-9b7904ae94a2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3705807535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.3705807535
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.1576755528
Short name T354
Test name
Test status
Simulation time 253340515 ps
CPU time 1.02 seconds
Started Jul 26 05:12:54 PM PDT 24
Finished Jul 26 05:12:55 PM PDT 24
Peak memory 206884 kb
Host smart-6cc890f9-6d19-4e87-ba97-df1616b6b86b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1576755528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.1576755528
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.2265257738
Short name T530
Test name
Test status
Simulation time 207979865 ps
CPU time 1.06 seconds
Started Jul 26 05:12:57 PM PDT 24
Finished Jul 26 05:12:58 PM PDT 24
Peak memory 207044 kb
Host smart-222e948d-ca35-44d8-bd5d-d9ce3b9813e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22652
57738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.2265257738
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.3946531395
Short name T1286
Test name
Test status
Simulation time 6220952302 ps
CPU time 69.64 seconds
Started Jul 26 05:12:52 PM PDT 24
Finished Jul 26 05:14:02 PM PDT 24
Peak memory 216684 kb
Host smart-a1ee01ce-3a8b-44af-9e79-e02a24d1e4ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39465
31395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.3946531395
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.3112344967
Short name T2808
Test name
Test status
Simulation time 6049180812 ps
CPU time 48.05 seconds
Started Jul 26 05:12:55 PM PDT 24
Finished Jul 26 05:13:43 PM PDT 24
Peak memory 207384 kb
Host smart-0dded1d1-7d77-40d7-95e6-816c5b6bc882
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3112344967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.3112344967
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.2985921170
Short name T22
Test name
Test status
Simulation time 182567799 ps
CPU time 0.87 seconds
Started Jul 26 05:12:59 PM PDT 24
Finished Jul 26 05:13:00 PM PDT 24
Peak memory 207132 kb
Host smart-06b9d9e4-e84a-46ee-bc65-b994364a0271
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2985921170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.2985921170
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.568901375
Short name T2182
Test name
Test status
Simulation time 183152655 ps
CPU time 0.91 seconds
Started Jul 26 05:12:54 PM PDT 24
Finished Jul 26 05:12:56 PM PDT 24
Peak memory 207060 kb
Host smart-5381b821-803b-40d2-b886-c5ee2b1b7125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56890
1375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.568901375
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.2816557630
Short name T113
Test name
Test status
Simulation time 190597217 ps
CPU time 0.9 seconds
Started Jul 26 05:12:54 PM PDT 24
Finished Jul 26 05:12:55 PM PDT 24
Peak memory 206988 kb
Host smart-e6375ef5-ad2f-4f82-b012-f636ca8bbbf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28165
57630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.2816557630
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.4190297117
Short name T648
Test name
Test status
Simulation time 183064925 ps
CPU time 0.91 seconds
Started Jul 26 05:12:57 PM PDT 24
Finished Jul 26 05:12:58 PM PDT 24
Peak memory 207008 kb
Host smart-ad5c18f0-4300-467f-bdcc-3ee2828fbbaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41902
97117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.4190297117
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.3513043602
Short name T365
Test name
Test status
Simulation time 184343186 ps
CPU time 0.86 seconds
Started Jul 26 05:12:57 PM PDT 24
Finished Jul 26 05:12:58 PM PDT 24
Peak memory 207084 kb
Host smart-213ff634-2643-402e-bcdc-aa3bced89d72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35130
43602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.3513043602
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.3009422114
Short name T1579
Test name
Test status
Simulation time 148624110 ps
CPU time 0.89 seconds
Started Jul 26 05:12:55 PM PDT 24
Finished Jul 26 05:12:56 PM PDT 24
Peak memory 207116 kb
Host smart-355f8911-ca4f-4593-9023-18ab32974fd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30094
22114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.3009422114
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.1876103515
Short name T2320
Test name
Test status
Simulation time 155163009 ps
CPU time 0.89 seconds
Started Jul 26 05:13:01 PM PDT 24
Finished Jul 26 05:13:02 PM PDT 24
Peak memory 207128 kb
Host smart-37eca3ee-684c-4805-87b9-bb68b3b11424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18761
03515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.1876103515
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.2589884748
Short name T1641
Test name
Test status
Simulation time 266335775 ps
CPU time 1.05 seconds
Started Jul 26 05:12:54 PM PDT 24
Finished Jul 26 05:12:56 PM PDT 24
Peak memory 207088 kb
Host smart-f3a33807-a99e-4d78-9862-f7e1036389bb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2589884748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.2589884748
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.1337528385
Short name T1210
Test name
Test status
Simulation time 150261821 ps
CPU time 0.84 seconds
Started Jul 26 05:12:58 PM PDT 24
Finished Jul 26 05:12:59 PM PDT 24
Peak memory 207040 kb
Host smart-226845a2-8718-4bc7-9289-582bd4ff0652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13375
28385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.1337528385
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.628717254
Short name T528
Test name
Test status
Simulation time 36796920 ps
CPU time 0.76 seconds
Started Jul 26 05:13:01 PM PDT 24
Finished Jul 26 05:13:02 PM PDT 24
Peak memory 207044 kb
Host smart-84031197-0cc5-4e90-8214-5626938303b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62871
7254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.628717254
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.2481036563
Short name T1215
Test name
Test status
Simulation time 19272638005 ps
CPU time 52.24 seconds
Started Jul 26 05:12:55 PM PDT 24
Finished Jul 26 05:13:48 PM PDT 24
Peak memory 215576 kb
Host smart-e7f927d1-b0bb-46e3-8e3b-5b7cc8f811b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24810
36563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.2481036563
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.203248404
Short name T713
Test name
Test status
Simulation time 171106396 ps
CPU time 0.98 seconds
Started Jul 26 05:13:01 PM PDT 24
Finished Jul 26 05:13:02 PM PDT 24
Peak memory 207132 kb
Host smart-f67fd14e-6a2f-47e2-857f-e5b2eee030cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20324
8404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.203248404
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.667949848
Short name T1470
Test name
Test status
Simulation time 228834050 ps
CPU time 0.93 seconds
Started Jul 26 05:12:55 PM PDT 24
Finished Jul 26 05:12:56 PM PDT 24
Peak memory 207052 kb
Host smart-ee0bee3e-7ca8-4b31-8658-ec9219938044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66794
9848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.667949848
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.1454698292
Short name T535
Test name
Test status
Simulation time 181123807 ps
CPU time 0.88 seconds
Started Jul 26 05:12:58 PM PDT 24
Finished Jul 26 05:12:59 PM PDT 24
Peak memory 207084 kb
Host smart-7762dcb8-4e16-4629-aa45-6fac4c3d49da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14546
98292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.1454698292
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.3602907666
Short name T1490
Test name
Test status
Simulation time 269656078 ps
CPU time 1.02 seconds
Started Jul 26 05:12:54 PM PDT 24
Finished Jul 26 05:12:55 PM PDT 24
Peak memory 207132 kb
Host smart-0b482a44-d322-445a-af2e-d47d8c23cf65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36029
07666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.3602907666
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.751138117
Short name T1375
Test name
Test status
Simulation time 156634957 ps
CPU time 0.91 seconds
Started Jul 26 05:12:57 PM PDT 24
Finished Jul 26 05:12:58 PM PDT 24
Peak memory 207068 kb
Host smart-6b8a7ca6-225c-48e1-bad8-31452ae25a45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75113
8117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.751138117
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.3458661070
Short name T1658
Test name
Test status
Simulation time 165323855 ps
CPU time 0.97 seconds
Started Jul 26 05:13:01 PM PDT 24
Finished Jul 26 05:13:02 PM PDT 24
Peak memory 207100 kb
Host smart-651b574a-6391-44c6-845b-3afb655c6106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34586
61070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.3458661070
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.3493794291
Short name T859
Test name
Test status
Simulation time 162416593 ps
CPU time 0.85 seconds
Started Jul 26 05:12:57 PM PDT 24
Finished Jul 26 05:12:58 PM PDT 24
Peak memory 207016 kb
Host smart-174be95e-b323-497c-9aad-44c4be51a7b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34937
94291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.3493794291
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.2881403664
Short name T2034
Test name
Test status
Simulation time 206536316 ps
CPU time 0.97 seconds
Started Jul 26 05:12:57 PM PDT 24
Finished Jul 26 05:12:59 PM PDT 24
Peak memory 207084 kb
Host smart-e8043f3b-7e54-4903-9083-f6f0e747bb8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28814
03664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2881403664
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.837183786
Short name T1591
Test name
Test status
Simulation time 4908465703 ps
CPU time 49.55 seconds
Started Jul 26 05:13:01 PM PDT 24
Finished Jul 26 05:13:51 PM PDT 24
Peak memory 207432 kb
Host smart-41b7cf5a-bd91-45b6-9c42-72aaad70178c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=837183786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.837183786
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.984757703
Short name T1066
Test name
Test status
Simulation time 186343395 ps
CPU time 0.88 seconds
Started Jul 26 05:12:57 PM PDT 24
Finished Jul 26 05:12:58 PM PDT 24
Peak memory 207096 kb
Host smart-b7e02c9b-deb3-48b6-9647-c6ca3a30b080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98475
7703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.984757703
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.1411495900
Short name T934
Test name
Test status
Simulation time 169053386 ps
CPU time 0.89 seconds
Started Jul 26 05:12:59 PM PDT 24
Finished Jul 26 05:13:00 PM PDT 24
Peak memory 207084 kb
Host smart-9ccf0218-0edf-42b4-aff1-7cb7c83224d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14114
95900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.1411495900
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.2223325827
Short name T277
Test name
Test status
Simulation time 911059000 ps
CPU time 2.33 seconds
Started Jul 26 05:12:55 PM PDT 24
Finished Jul 26 05:12:58 PM PDT 24
Peak memory 207264 kb
Host smart-48dd140b-2861-4a94-ac9b-c7f0f54bd4d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22233
25827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.2223325827
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.2519058391
Short name T620
Test name
Test status
Simulation time 3377903760 ps
CPU time 26.49 seconds
Started Jul 26 05:12:56 PM PDT 24
Finished Jul 26 05:13:23 PM PDT 24
Peak memory 217028 kb
Host smart-09be5479-3168-4edf-9c75-484ad9004f91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25190
58391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.2519058391
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_timeout_missing_host_handshake.3416878222
Short name T2031
Test name
Test status
Simulation time 3150152197 ps
CPU time 22.54 seconds
Started Jul 26 05:12:57 PM PDT 24
Finished Jul 26 05:13:19 PM PDT 24
Peak memory 207392 kb
Host smart-e2fadc3c-897c-4476-8d23-5eacbf4e843c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416878222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_timeout_missing_hos
t_handshake.3416878222
Directory /workspace/32.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.4219099457
Short name T178
Test name
Test status
Simulation time 79395009 ps
CPU time 0.71 seconds
Started Jul 26 05:13:09 PM PDT 24
Finished Jul 26 05:13:10 PM PDT 24
Peak memory 207156 kb
Host smart-edd12f20-922e-425b-bbe5-3c50a95dccae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4219099457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.4219099457
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.4253158127
Short name T2113
Test name
Test status
Simulation time 3396689676 ps
CPU time 5.12 seconds
Started Jul 26 05:13:05 PM PDT 24
Finished Jul 26 05:13:10 PM PDT 24
Peak memory 207260 kb
Host smart-1bdda976-298e-40ee-85d7-84d4fa9417fc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253158127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_a
on_wake_disconnect.4253158127
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.4113175927
Short name T367
Test name
Test status
Simulation time 13380248702 ps
CPU time 15.95 seconds
Started Jul 26 05:13:06 PM PDT 24
Finished Jul 26 05:13:22 PM PDT 24
Peak memory 207408 kb
Host smart-3f334048-9da9-4255-9c8c-40a6c2123971
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113175927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.4113175927
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.4075054686
Short name T2148
Test name
Test status
Simulation time 23384034492 ps
CPU time 33.93 seconds
Started Jul 26 05:13:04 PM PDT 24
Finished Jul 26 05:13:38 PM PDT 24
Peak memory 207296 kb
Host smart-4940900b-d52e-4e62-9ad1-406c7788cf0b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075054686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_a
on_wake_resume.4075054686
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.1889587597
Short name T1462
Test name
Test status
Simulation time 186224172 ps
CPU time 0.9 seconds
Started Jul 26 05:13:04 PM PDT 24
Finished Jul 26 05:13:05 PM PDT 24
Peak memory 207120 kb
Host smart-8ccfe99a-ad9c-4258-ad76-911290ea2211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18895
87597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.1889587597
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.2909125818
Short name T654
Test name
Test status
Simulation time 147722670 ps
CPU time 0.87 seconds
Started Jul 26 05:13:10 PM PDT 24
Finished Jul 26 05:13:11 PM PDT 24
Peak memory 207080 kb
Host smart-7f58232c-b39c-4e30-83c4-5940daaf2f9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29091
25818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.2909125818
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.1985333961
Short name T2548
Test name
Test status
Simulation time 190797199 ps
CPU time 0.95 seconds
Started Jul 26 05:13:16 PM PDT 24
Finished Jul 26 05:13:17 PM PDT 24
Peak memory 207208 kb
Host smart-257e0ece-0697-4355-9811-b344a3e5d4e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19853
33961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.1985333961
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.4092302323
Short name T2131
Test name
Test status
Simulation time 629991123 ps
CPU time 1.82 seconds
Started Jul 26 05:13:09 PM PDT 24
Finished Jul 26 05:13:11 PM PDT 24
Peak memory 207080 kb
Host smart-ae2f3dfe-5f3c-4f07-bd07-dbb9f6e86716
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4092302323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.4092302323
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.3294136583
Short name T2755
Test name
Test status
Simulation time 22403434142 ps
CPU time 49.45 seconds
Started Jul 26 05:13:09 PM PDT 24
Finished Jul 26 05:13:59 PM PDT 24
Peak memory 207296 kb
Host smart-ddead542-9394-4001-8758-99659f049a8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32941
36583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.3294136583
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_device_timeout.4147356472
Short name T1428
Test name
Test status
Simulation time 1084437195 ps
CPU time 9.57 seconds
Started Jul 26 05:13:05 PM PDT 24
Finished Jul 26 05:13:14 PM PDT 24
Peak memory 207260 kb
Host smart-f0867cdb-93e5-4b13-93e7-cfefa055fb58
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147356472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_timeout.4147356472
Directory /workspace/33.usbdev_device_timeout/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.515681575
Short name T1176
Test name
Test status
Simulation time 409686656 ps
CPU time 1.47 seconds
Started Jul 26 05:13:06 PM PDT 24
Finished Jul 26 05:13:08 PM PDT 24
Peak memory 207096 kb
Host smart-9dce0292-3fe8-4ad3-8b3c-8fe8ba686d0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51568
1575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.515681575
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.2579247474
Short name T878
Test name
Test status
Simulation time 136447810 ps
CPU time 0.86 seconds
Started Jul 26 05:13:13 PM PDT 24
Finished Jul 26 05:13:15 PM PDT 24
Peak memory 207088 kb
Host smart-393b3f96-8272-466c-89e5-5304fd8ad969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25792
47474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.2579247474
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.1032089715
Short name T1884
Test name
Test status
Simulation time 44792291 ps
CPU time 0.8 seconds
Started Jul 26 05:13:06 PM PDT 24
Finished Jul 26 05:13:07 PM PDT 24
Peak memory 207044 kb
Host smart-0e506b1e-667d-4eca-ba07-b39de3bb3c5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10320
89715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.1032089715
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.2186174460
Short name T1395
Test name
Test status
Simulation time 906197473 ps
CPU time 2.43 seconds
Started Jul 26 05:13:04 PM PDT 24
Finished Jul 26 05:13:07 PM PDT 24
Peak memory 207308 kb
Host smart-501c2296-4db6-4d35-8a21-1a9ce5222cf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21861
74460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.2186174460
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.4130560466
Short name T2120
Test name
Test status
Simulation time 234086068 ps
CPU time 1.44 seconds
Started Jul 26 05:13:04 PM PDT 24
Finished Jul 26 05:13:06 PM PDT 24
Peak memory 207280 kb
Host smart-d5aa57b1-e90f-4fa0-a29f-a17320904c38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41305
60466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.4130560466
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.3778140897
Short name T1542
Test name
Test status
Simulation time 224014172 ps
CPU time 1.18 seconds
Started Jul 26 05:13:04 PM PDT 24
Finished Jul 26 05:13:05 PM PDT 24
Peak memory 215476 kb
Host smart-2a3aaa7b-1662-4dea-b637-d84e9567a465
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3778140897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.3778140897
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.2450639163
Short name T1271
Test name
Test status
Simulation time 154226338 ps
CPU time 0.79 seconds
Started Jul 26 05:13:05 PM PDT 24
Finished Jul 26 05:13:06 PM PDT 24
Peak memory 207016 kb
Host smart-958417be-8d00-4722-94aa-90df42993ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24506
39163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.2450639163
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.2336580171
Short name T1838
Test name
Test status
Simulation time 241380727 ps
CPU time 0.98 seconds
Started Jul 26 05:13:03 PM PDT 24
Finished Jul 26 05:13:05 PM PDT 24
Peak memory 207024 kb
Host smart-f233d3f7-6808-4ada-aae1-1cd29a330272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23365
80171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.2336580171
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_invalid_sync.915859463
Short name T1908
Test name
Test status
Simulation time 8239434566 ps
CPU time 82.62 seconds
Started Jul 26 05:13:06 PM PDT 24
Finished Jul 26 05:14:29 PM PDT 24
Peak memory 215448 kb
Host smart-bf25d055-ad92-41fa-bb1e-92690da3661c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=915859463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.915859463
Directory /workspace/33.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/33.usbdev_iso_retraction.1596999176
Short name T1320
Test name
Test status
Simulation time 5451347614 ps
CPU time 34.74 seconds
Started Jul 26 05:13:05 PM PDT 24
Finished Jul 26 05:13:40 PM PDT 24
Peak memory 207228 kb
Host smart-ed5e5a6d-ed12-4648-8de6-8afc929693f6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1596999176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.1596999176
Directory /workspace/33.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.3176296033
Short name T1086
Test name
Test status
Simulation time 224504339 ps
CPU time 0.97 seconds
Started Jul 26 05:13:05 PM PDT 24
Finished Jul 26 05:13:06 PM PDT 24
Peak memory 207000 kb
Host smart-7ea2f3a3-5883-42df-b5e8-6a927dfe4730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31762
96033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.3176296033
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.2573982892
Short name T1675
Test name
Test status
Simulation time 23356558578 ps
CPU time 27.9 seconds
Started Jul 26 05:13:09 PM PDT 24
Finished Jul 26 05:13:37 PM PDT 24
Peak memory 207372 kb
Host smart-a29e38bb-03a9-4f30-82f7-16f5dba75acf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25739
82892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.2573982892
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.850050713
Short name T1693
Test name
Test status
Simulation time 3284495928 ps
CPU time 5.72 seconds
Started Jul 26 05:13:04 PM PDT 24
Finished Jul 26 05:13:10 PM PDT 24
Peak memory 207352 kb
Host smart-c4759e51-37d8-4310-836d-6b5f42c88a63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85005
0713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.850050713
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.2516898690
Short name T1605
Test name
Test status
Simulation time 5645252858 ps
CPU time 56.59 seconds
Started Jul 26 05:13:13 PM PDT 24
Finished Jul 26 05:14:09 PM PDT 24
Peak memory 223744 kb
Host smart-016d2e1c-2277-4535-a156-12cdc2fef121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25168
98690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.2516898690
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.1581930868
Short name T734
Test name
Test status
Simulation time 7511329837 ps
CPU time 78.78 seconds
Started Jul 26 05:13:05 PM PDT 24
Finished Jul 26 05:14:24 PM PDT 24
Peak memory 207416 kb
Host smart-1cc1a75b-97f7-4d2f-8681-239fd83b7092
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1581930868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.1581930868
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.1510537762
Short name T359
Test name
Test status
Simulation time 237829532 ps
CPU time 1 seconds
Started Jul 26 05:13:04 PM PDT 24
Finished Jul 26 05:13:05 PM PDT 24
Peak memory 207068 kb
Host smart-6886d8b7-2c16-4c9f-9220-4e69a0521530
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1510537762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.1510537762
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.459828151
Short name T2185
Test name
Test status
Simulation time 195072478 ps
CPU time 0.95 seconds
Started Jul 26 05:13:14 PM PDT 24
Finished Jul 26 05:13:15 PM PDT 24
Peak memory 207144 kb
Host smart-bec33fee-bdc6-41d3-892f-6c33c14b612c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45982
8151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.459828151
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.157523736
Short name T2677
Test name
Test status
Simulation time 4587859567 ps
CPU time 44.11 seconds
Started Jul 26 05:13:16 PM PDT 24
Finished Jul 26 05:14:01 PM PDT 24
Peak memory 215456 kb
Host smart-53594d56-3c99-4b04-85f9-dfae152f89f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15752
3736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.157523736
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.1095895278
Short name T1930
Test name
Test status
Simulation time 3894816288 ps
CPU time 39.78 seconds
Started Jul 26 05:13:08 PM PDT 24
Finished Jul 26 05:13:48 PM PDT 24
Peak memory 215568 kb
Host smart-d27a06da-0114-400d-badd-11d752100af0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1095895278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.1095895278
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.910361729
Short name T445
Test name
Test status
Simulation time 211849653 ps
CPU time 0.98 seconds
Started Jul 26 05:13:05 PM PDT 24
Finished Jul 26 05:13:06 PM PDT 24
Peak memory 207136 kb
Host smart-83e2de5d-7b43-4377-a055-2e81e4e2cf9e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=910361729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.910361729
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.599365696
Short name T1975
Test name
Test status
Simulation time 148405404 ps
CPU time 0.83 seconds
Started Jul 26 05:13:04 PM PDT 24
Finished Jul 26 05:13:05 PM PDT 24
Peak memory 207044 kb
Host smart-506b2f0d-9b3f-4d46-b35e-6fdabac6273b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59936
5696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.599365696
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.3227747255
Short name T126
Test name
Test status
Simulation time 161121878 ps
CPU time 0.86 seconds
Started Jul 26 05:13:04 PM PDT 24
Finished Jul 26 05:13:05 PM PDT 24
Peak memory 207052 kb
Host smart-b83b476e-8e94-4169-b469-218abb200186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32277
47255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3227747255
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.638609098
Short name T741
Test name
Test status
Simulation time 156983621 ps
CPU time 0.92 seconds
Started Jul 26 05:13:12 PM PDT 24
Finished Jul 26 05:13:13 PM PDT 24
Peak memory 207052 kb
Host smart-8df36e43-fd07-4281-934b-f9db1c59c8f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63860
9098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.638609098
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.282924198
Short name T2378
Test name
Test status
Simulation time 167603022 ps
CPU time 0.86 seconds
Started Jul 26 05:13:05 PM PDT 24
Finished Jul 26 05:13:06 PM PDT 24
Peak memory 206980 kb
Host smart-80d6ea00-1d41-4972-bb1d-b27b9e7c707f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28292
4198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.282924198
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.1127486999
Short name T802
Test name
Test status
Simulation time 217851353 ps
CPU time 1.06 seconds
Started Jul 26 05:13:12 PM PDT 24
Finished Jul 26 05:13:13 PM PDT 24
Peak memory 207056 kb
Host smart-86f5b20a-d7c4-4d03-9f12-9b36c4976f0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11274
86999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.1127486999
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.288022221
Short name T2512
Test name
Test status
Simulation time 153084382 ps
CPU time 0.86 seconds
Started Jul 26 05:13:08 PM PDT 24
Finished Jul 26 05:13:09 PM PDT 24
Peak memory 207096 kb
Host smart-3567ee45-280c-4453-a036-c2868979490d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28802
2221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.288022221
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.3624158223
Short name T965
Test name
Test status
Simulation time 256096820 ps
CPU time 1.04 seconds
Started Jul 26 05:13:12 PM PDT 24
Finished Jul 26 05:13:13 PM PDT 24
Peak memory 207076 kb
Host smart-980cc787-4149-48bc-b674-6d931edcbcdb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3624158223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.3624158223
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.11245600
Short name T1491
Test name
Test status
Simulation time 166867967 ps
CPU time 0.84 seconds
Started Jul 26 05:13:12 PM PDT 24
Finished Jul 26 05:13:13 PM PDT 24
Peak memory 207084 kb
Host smart-a2953ca9-bdce-4697-8c74-5a39fb911ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11245
600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.11245600
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.1754163928
Short name T1757
Test name
Test status
Simulation time 66845052 ps
CPU time 0.75 seconds
Started Jul 26 05:13:13 PM PDT 24
Finished Jul 26 05:13:15 PM PDT 24
Peak memory 207088 kb
Host smart-bc451ecf-74fc-40a7-a047-07e8892bf944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17541
63928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.1754163928
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.1159850076
Short name T2175
Test name
Test status
Simulation time 9254880166 ps
CPU time 23.62 seconds
Started Jul 26 05:13:03 PM PDT 24
Finished Jul 26 05:13:27 PM PDT 24
Peak memory 215516 kb
Host smart-c1828ba1-5800-4440-80ae-18fd5d504e1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11598
50076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.1159850076
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.870346456
Short name T290
Test name
Test status
Simulation time 211055097 ps
CPU time 1.01 seconds
Started Jul 26 05:13:05 PM PDT 24
Finished Jul 26 05:13:06 PM PDT 24
Peak memory 207128 kb
Host smart-7fe7c675-6a88-4633-a91a-234048bdb470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87034
6456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.870346456
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.2127828559
Short name T722
Test name
Test status
Simulation time 173131887 ps
CPU time 0.92 seconds
Started Jul 26 05:13:05 PM PDT 24
Finished Jul 26 05:13:06 PM PDT 24
Peak memory 207128 kb
Host smart-bde58713-05c0-49db-9edf-f8a1ade06e48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21278
28559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.2127828559
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.2928510117
Short name T2280
Test name
Test status
Simulation time 194359916 ps
CPU time 0.94 seconds
Started Jul 26 05:13:08 PM PDT 24
Finished Jul 26 05:13:09 PM PDT 24
Peak memory 207132 kb
Host smart-dc0c8c4d-0117-4afd-9d7d-ba4d6d171599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29285
10117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.2928510117
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.310061092
Short name T1733
Test name
Test status
Simulation time 197794805 ps
CPU time 0.97 seconds
Started Jul 26 05:13:04 PM PDT 24
Finished Jul 26 05:13:05 PM PDT 24
Peak memory 206936 kb
Host smart-5abcdb08-7277-49a0-8c08-c569d724cf37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31006
1092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.310061092
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.741227661
Short name T793
Test name
Test status
Simulation time 138932615 ps
CPU time 0.78 seconds
Started Jul 26 05:13:06 PM PDT 24
Finished Jul 26 05:13:07 PM PDT 24
Peak memory 206988 kb
Host smart-fa81d65e-7a84-451f-a958-6301f8061f74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74122
7661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.741227661
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.400616776
Short name T1628
Test name
Test status
Simulation time 207986346 ps
CPU time 0.91 seconds
Started Jul 26 05:13:10 PM PDT 24
Finished Jul 26 05:13:11 PM PDT 24
Peak memory 207044 kb
Host smart-77f0a361-cae2-48e7-a53e-a05c9754c940
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40061
6776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.400616776
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.186650788
Short name T2480
Test name
Test status
Simulation time 186068754 ps
CPU time 0.87 seconds
Started Jul 26 05:13:06 PM PDT 24
Finished Jul 26 05:13:07 PM PDT 24
Peak memory 207024 kb
Host smart-925342db-2cc1-46b2-9693-d32f6ea86f51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18665
0788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.186650788
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.796150391
Short name T1423
Test name
Test status
Simulation time 245460514 ps
CPU time 1.06 seconds
Started Jul 26 05:13:04 PM PDT 24
Finished Jul 26 05:13:05 PM PDT 24
Peak memory 207132 kb
Host smart-fd0f0397-7563-4b77-9b22-bbd2a63c6abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79615
0391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.796150391
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.1631625382
Short name T791
Test name
Test status
Simulation time 6722706040 ps
CPU time 205.66 seconds
Started Jul 26 05:13:08 PM PDT 24
Finished Jul 26 05:16:34 PM PDT 24
Peak memory 215540 kb
Host smart-f8def2b2-9592-4d27-95e6-4eb0a3945572
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1631625382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.1631625382
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.1826006338
Short name T1564
Test name
Test status
Simulation time 237431021 ps
CPU time 1.01 seconds
Started Jul 26 05:13:09 PM PDT 24
Finished Jul 26 05:13:10 PM PDT 24
Peak memory 207096 kb
Host smart-d1e9eb47-1d09-4d22-8a78-9f9f8715a024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18260
06338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.1826006338
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.2197171442
Short name T2474
Test name
Test status
Simulation time 155018438 ps
CPU time 0.84 seconds
Started Jul 26 05:13:12 PM PDT 24
Finished Jul 26 05:13:13 PM PDT 24
Peak memory 207120 kb
Host smart-1901055f-1714-4df6-9b59-5fb1670ebc2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21971
71442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.2197171442
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.405645624
Short name T1418
Test name
Test status
Simulation time 284995343 ps
CPU time 1.1 seconds
Started Jul 26 05:13:02 PM PDT 24
Finished Jul 26 05:13:03 PM PDT 24
Peak memory 207068 kb
Host smart-88b279ff-bd8a-41b9-826f-54903ab0c178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40564
5624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.405645624
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.840441638
Short name T1109
Test name
Test status
Simulation time 6331238111 ps
CPU time 49.43 seconds
Started Jul 26 05:13:08 PM PDT 24
Finished Jul 26 05:13:58 PM PDT 24
Peak memory 207412 kb
Host smart-876e9c79-5752-47e3-914f-06c1f2fa1f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84044
1638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.840441638
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_timeout_missing_host_handshake.2895321906
Short name T1450
Test name
Test status
Simulation time 6116599966 ps
CPU time 46.01 seconds
Started Jul 26 05:13:04 PM PDT 24
Finished Jul 26 05:13:51 PM PDT 24
Peak memory 207280 kb
Host smart-eec89e3c-7151-463f-9f8b-e790fa8a3fe7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895321906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_timeout_missing_hos
t_handshake.2895321906
Directory /workspace/33.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.3107113261
Short name T2242
Test name
Test status
Simulation time 48523098 ps
CPU time 0.68 seconds
Started Jul 26 05:13:14 PM PDT 24
Finished Jul 26 05:13:15 PM PDT 24
Peak memory 207096 kb
Host smart-c635aece-9c6c-4f76-8907-c44d280cc78a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3107113261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.3107113261
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.2297651198
Short name T2494
Test name
Test status
Simulation time 4149676718 ps
CPU time 7.09 seconds
Started Jul 26 05:13:03 PM PDT 24
Finished Jul 26 05:13:10 PM PDT 24
Peak memory 207284 kb
Host smart-2572952c-b765-4c37-9e20-400fa09d374e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297651198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_a
on_wake_disconnect.2297651198
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.3922066355
Short name T1870
Test name
Test status
Simulation time 13296175770 ps
CPU time 18.02 seconds
Started Jul 26 05:13:16 PM PDT 24
Finished Jul 26 05:13:34 PM PDT 24
Peak memory 207408 kb
Host smart-505c5df8-6006-4738-9721-bee85d7a03fa
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922066355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.3922066355
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.21027524
Short name T1783
Test name
Test status
Simulation time 23451117262 ps
CPU time 31.54 seconds
Started Jul 26 05:13:12 PM PDT 24
Finished Jul 26 05:13:44 PM PDT 24
Peak memory 207300 kb
Host smart-8d8b2d33-16af-4c1e-aa52-9b6317a68caf
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21027524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon
_wake_resume.21027524
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.4190887502
Short name T695
Test name
Test status
Simulation time 178039287 ps
CPU time 0.85 seconds
Started Jul 26 05:13:13 PM PDT 24
Finished Jul 26 05:13:14 PM PDT 24
Peak memory 207124 kb
Host smart-850e7ce9-8d5d-4f7b-8cdf-716047a223d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41908
87502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.4190887502
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.1634010767
Short name T2334
Test name
Test status
Simulation time 146298858 ps
CPU time 0.85 seconds
Started Jul 26 05:13:08 PM PDT 24
Finished Jul 26 05:13:09 PM PDT 24
Peak memory 207100 kb
Host smart-2ecc7686-f7a6-4c6f-94f3-0e4ddc551487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16340
10767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.1634010767
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.4158400152
Short name T1429
Test name
Test status
Simulation time 318693572 ps
CPU time 1.35 seconds
Started Jul 26 05:13:02 PM PDT 24
Finished Jul 26 05:13:04 PM PDT 24
Peak memory 207148 kb
Host smart-8cacbf5b-a35a-4e89-bd7e-0ce891a855db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41584
00152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.4158400152
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.130879147
Short name T1073
Test name
Test status
Simulation time 1361926899 ps
CPU time 3.21 seconds
Started Jul 26 05:13:04 PM PDT 24
Finished Jul 26 05:13:08 PM PDT 24
Peak memory 207248 kb
Host smart-56ce41ea-7d8f-4bb7-b13e-44246387b99b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=130879147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.130879147
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.1094676841
Short name T1200
Test name
Test status
Simulation time 16265418831 ps
CPU time 35.85 seconds
Started Jul 26 05:13:16 PM PDT 24
Finished Jul 26 05:13:52 PM PDT 24
Peak memory 207424 kb
Host smart-ed4e76bf-82e3-4c12-95bd-8ecde116ed38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10946
76841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.1094676841
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_device_timeout.4266862599
Short name T929
Test name
Test status
Simulation time 443611241 ps
CPU time 8.56 seconds
Started Jul 26 05:13:08 PM PDT 24
Finished Jul 26 05:13:16 PM PDT 24
Peak memory 207364 kb
Host smart-51bed7db-87ae-4db4-9bd4-b4f414cc2db2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266862599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_timeout.4266862599
Directory /workspace/34.usbdev_device_timeout/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.2508823087
Short name T2865
Test name
Test status
Simulation time 424053834 ps
CPU time 1.45 seconds
Started Jul 26 05:13:13 PM PDT 24
Finished Jul 26 05:13:15 PM PDT 24
Peak memory 207092 kb
Host smart-34284472-73c8-4ef1-b8e4-1edcfb621062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25088
23087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.2508823087
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.2165646410
Short name T1715
Test name
Test status
Simulation time 204811437 ps
CPU time 0.89 seconds
Started Jul 26 05:13:16 PM PDT 24
Finished Jul 26 05:13:17 PM PDT 24
Peak memory 207124 kb
Host smart-67c43ed0-d42c-4614-a3c5-0ac5982eca70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21656
46410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.2165646410
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.2297029936
Short name T1092
Test name
Test status
Simulation time 107880942 ps
CPU time 0.74 seconds
Started Jul 26 05:13:14 PM PDT 24
Finished Jul 26 05:13:15 PM PDT 24
Peak memory 207084 kb
Host smart-0a31039f-8c5a-4e5f-81e0-a64e14962550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22970
29936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.2297029936
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.2986830106
Short name T967
Test name
Test status
Simulation time 969704804 ps
CPU time 2.61 seconds
Started Jul 26 05:13:16 PM PDT 24
Finished Jul 26 05:13:19 PM PDT 24
Peak memory 207468 kb
Host smart-9a0c3f27-5ac9-4efb-8fc8-17ffc27cccfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29868
30106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.2986830106
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.2414755297
Short name T1820
Test name
Test status
Simulation time 191045337 ps
CPU time 2.47 seconds
Started Jul 26 05:13:09 PM PDT 24
Finished Jul 26 05:13:12 PM PDT 24
Peak memory 207308 kb
Host smart-31db76c5-44dc-4334-aac1-b35506c8c218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24147
55297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.2414755297
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.1158600267
Short name T1938
Test name
Test status
Simulation time 263498687 ps
CPU time 1.16 seconds
Started Jul 26 05:13:10 PM PDT 24
Finished Jul 26 05:13:11 PM PDT 24
Peak memory 215508 kb
Host smart-b9e210c9-9491-4db6-8f7f-0348907ecd33
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1158600267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.1158600267
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.2826715925
Short name T1322
Test name
Test status
Simulation time 148385108 ps
CPU time 0.86 seconds
Started Jul 26 05:13:14 PM PDT 24
Finished Jul 26 05:13:15 PM PDT 24
Peak memory 207088 kb
Host smart-36dc0f58-e009-46b6-b0ed-d7e9d9aac267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28267
15925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.2826715925
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.2309437476
Short name T376
Test name
Test status
Simulation time 200093994 ps
CPU time 0.97 seconds
Started Jul 26 05:13:06 PM PDT 24
Finished Jul 26 05:13:07 PM PDT 24
Peak memory 206980 kb
Host smart-b0d4defa-7798-42b5-8f15-9edf1376233d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23094
37476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.2309437476
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.3948223985
Short name T589
Test name
Test status
Simulation time 7272754624 ps
CPU time 54.11 seconds
Started Jul 26 05:13:16 PM PDT 24
Finished Jul 26 05:14:10 PM PDT 24
Peak memory 215504 kb
Host smart-cdafc086-8183-48ec-9531-8bec49307778
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3948223985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.3948223985
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/34.usbdev_iso_retraction.2515717252
Short name T1302
Test name
Test status
Simulation time 3747113653 ps
CPU time 27.18 seconds
Started Jul 26 05:13:14 PM PDT 24
Finished Jul 26 05:13:41 PM PDT 24
Peak memory 207336 kb
Host smart-fe4c380f-2f20-47dc-b52b-1afee3530336
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2515717252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_iso_retraction.2515717252
Directory /workspace/34.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.3617783240
Short name T1713
Test name
Test status
Simulation time 202232668 ps
CPU time 0.91 seconds
Started Jul 26 05:13:10 PM PDT 24
Finished Jul 26 05:13:11 PM PDT 24
Peak memory 207096 kb
Host smart-13ce09ab-842f-4094-9915-85f566e6db22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36177
83240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.3617783240
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.3817253238
Short name T2636
Test name
Test status
Simulation time 23360072216 ps
CPU time 27.22 seconds
Started Jul 26 05:13:11 PM PDT 24
Finished Jul 26 05:13:38 PM PDT 24
Peak memory 207332 kb
Host smart-0e178b76-41fe-4301-8fdb-d05040cf5a49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38172
53238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.3817253238
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.3833790799
Short name T397
Test name
Test status
Simulation time 3288651043 ps
CPU time 5 seconds
Started Jul 26 05:13:07 PM PDT 24
Finished Jul 26 05:13:12 PM PDT 24
Peak memory 207304 kb
Host smart-b5fd77c1-b6f2-442c-af64-06ec5f416ff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38337
90799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.3833790799
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.554540543
Short name T1089
Test name
Test status
Simulation time 8356208254 ps
CPU time 259.03 seconds
Started Jul 26 05:13:07 PM PDT 24
Finished Jul 26 05:17:26 PM PDT 24
Peak memory 215528 kb
Host smart-d80cb902-6eb7-42ea-ab5c-6ca60b91b88a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55454
0543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.554540543
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.1370811786
Short name T2720
Test name
Test status
Simulation time 3538835440 ps
CPU time 36.33 seconds
Started Jul 26 05:13:08 PM PDT 24
Finished Jul 26 05:13:44 PM PDT 24
Peak memory 215544 kb
Host smart-2dea7552-6bca-4ccc-880a-f16495256440
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1370811786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.1370811786
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.1070736355
Short name T1422
Test name
Test status
Simulation time 282164143 ps
CPU time 1.05 seconds
Started Jul 26 05:13:11 PM PDT 24
Finished Jul 26 05:13:12 PM PDT 24
Peak memory 207120 kb
Host smart-3545aae4-6d81-450e-8369-d1f020dc34a0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1070736355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.1070736355
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.766760398
Short name T2411
Test name
Test status
Simulation time 204899358 ps
CPU time 1 seconds
Started Jul 26 05:13:10 PM PDT 24
Finished Jul 26 05:13:11 PM PDT 24
Peak memory 207096 kb
Host smart-41abfe7e-af55-48c2-9390-fc35cc73ad68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76676
0398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.766760398
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.1442992164
Short name T1004
Test name
Test status
Simulation time 4175202810 ps
CPU time 33.43 seconds
Started Jul 26 05:13:10 PM PDT 24
Finished Jul 26 05:13:43 PM PDT 24
Peak memory 216880 kb
Host smart-e4a28489-12f3-4997-abf6-5ee7528aca6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14429
92164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.1442992164
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.4047217258
Short name T20
Test name
Test status
Simulation time 4866243007 ps
CPU time 41.43 seconds
Started Jul 26 05:13:07 PM PDT 24
Finished Jul 26 05:13:49 PM PDT 24
Peak memory 217276 kb
Host smart-3c54ce87-0f59-43e1-9404-531c01525bf6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4047217258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.4047217258
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.1306179987
Short name T324
Test name
Test status
Simulation time 213403259 ps
CPU time 0.91 seconds
Started Jul 26 05:13:10 PM PDT 24
Finished Jul 26 05:13:11 PM PDT 24
Peak memory 207120 kb
Host smart-855974d0-fc16-4666-bad9-619f13447696
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1306179987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.1306179987
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.3291414208
Short name T2114
Test name
Test status
Simulation time 160413549 ps
CPU time 0.88 seconds
Started Jul 26 05:13:16 PM PDT 24
Finished Jul 26 05:13:17 PM PDT 24
Peak memory 207156 kb
Host smart-112720e1-2682-4b71-8952-5e0a9a7238ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32914
14208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.3291414208
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.1236135284
Short name T2715
Test name
Test status
Simulation time 245876834 ps
CPU time 0.96 seconds
Started Jul 26 05:13:14 PM PDT 24
Finished Jul 26 05:13:15 PM PDT 24
Peak memory 207028 kb
Host smart-aee70717-74bb-4825-a2aa-8f214051604d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12361
35284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.1236135284
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.1233979196
Short name T2221
Test name
Test status
Simulation time 159978146 ps
CPU time 0.98 seconds
Started Jul 26 05:13:18 PM PDT 24
Finished Jul 26 05:13:19 PM PDT 24
Peak memory 207132 kb
Host smart-81f73f81-02ee-40f6-9b72-1f29c7ae9778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12339
79196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.1233979196
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.2354630264
Short name T474
Test name
Test status
Simulation time 245531629 ps
CPU time 1.02 seconds
Started Jul 26 05:13:22 PM PDT 24
Finished Jul 26 05:13:24 PM PDT 24
Peak memory 207332 kb
Host smart-5df38b18-17b5-49ff-96da-14d2195d67df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23546
30264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.2354630264
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.2631185404
Short name T696
Test name
Test status
Simulation time 204204515 ps
CPU time 0.94 seconds
Started Jul 26 05:13:14 PM PDT 24
Finished Jul 26 05:13:15 PM PDT 24
Peak memory 207048 kb
Host smart-aae826f3-9db5-447d-825c-7d7bd37177de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26311
85404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.2631185404
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.2040000157
Short name T373
Test name
Test status
Simulation time 195227215 ps
CPU time 0.91 seconds
Started Jul 26 05:13:16 PM PDT 24
Finished Jul 26 05:13:17 PM PDT 24
Peak memory 207024 kb
Host smart-a6577ab0-ce21-48a0-8a6e-d129b6cd0385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20400
00157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.2040000157
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.1345065786
Short name T402
Test name
Test status
Simulation time 212881207 ps
CPU time 1 seconds
Started Jul 26 05:13:15 PM PDT 24
Finished Jul 26 05:13:16 PM PDT 24
Peak memory 207072 kb
Host smart-f602c9b5-8cd7-4359-b557-7c5bdadcd534
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1345065786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.1345065786
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.1981551870
Short name T801
Test name
Test status
Simulation time 150103947 ps
CPU time 0.86 seconds
Started Jul 26 05:13:15 PM PDT 24
Finished Jul 26 05:13:16 PM PDT 24
Peak memory 207068 kb
Host smart-69616cbc-7c16-41bd-b895-a9fae55b044c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19815
51870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.1981551870
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.632856636
Short name T1380
Test name
Test status
Simulation time 32213821 ps
CPU time 0.68 seconds
Started Jul 26 05:13:17 PM PDT 24
Finished Jul 26 05:13:18 PM PDT 24
Peak memory 207064 kb
Host smart-24501d62-5de0-4859-a18b-881a1b967f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63285
6636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.632856636
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.1379084964
Short name T1333
Test name
Test status
Simulation time 19066259702 ps
CPU time 45.76 seconds
Started Jul 26 05:13:17 PM PDT 24
Finished Jul 26 05:14:03 PM PDT 24
Peak memory 215504 kb
Host smart-62118edb-1ab6-4d25-80e5-21305d591389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13790
84964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.1379084964
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.1954986094
Short name T1763
Test name
Test status
Simulation time 197154596 ps
CPU time 0.93 seconds
Started Jul 26 05:13:20 PM PDT 24
Finished Jul 26 05:13:21 PM PDT 24
Peak memory 207036 kb
Host smart-60424673-21cc-4c30-99e1-222d3aa6f3d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19549
86094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.1954986094
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.689373060
Short name T2015
Test name
Test status
Simulation time 217957574 ps
CPU time 0.97 seconds
Started Jul 26 05:13:17 PM PDT 24
Finished Jul 26 05:13:18 PM PDT 24
Peak memory 206908 kb
Host smart-0a4dc3e5-b76c-4e90-ab35-f218acc095cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68937
3060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.689373060
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.3338115395
Short name T2782
Test name
Test status
Simulation time 194428318 ps
CPU time 0.92 seconds
Started Jul 26 05:13:14 PM PDT 24
Finished Jul 26 05:13:15 PM PDT 24
Peak memory 207084 kb
Host smart-54387e53-eacf-41e1-8c90-9235278b43be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33381
15395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.3338115395
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.744529508
Short name T424
Test name
Test status
Simulation time 198481543 ps
CPU time 0.94 seconds
Started Jul 26 05:13:18 PM PDT 24
Finished Jul 26 05:13:19 PM PDT 24
Peak memory 207132 kb
Host smart-2c9678da-c591-44cb-bdd0-1bc71a4f0719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74452
9508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.744529508
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.2538924380
Short name T2165
Test name
Test status
Simulation time 147786438 ps
CPU time 0.81 seconds
Started Jul 26 05:13:23 PM PDT 24
Finished Jul 26 05:13:24 PM PDT 24
Peak memory 207020 kb
Host smart-3f7d76e5-57b6-4328-9503-bc2d7028559e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25389
24380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.2538924380
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.4176230584
Short name T873
Test name
Test status
Simulation time 202914270 ps
CPU time 0.87 seconds
Started Jul 26 05:13:19 PM PDT 24
Finished Jul 26 05:13:20 PM PDT 24
Peak memory 207004 kb
Host smart-4631c193-17a4-4cb7-8cbe-3d492c3fe21e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41762
30584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.4176230584
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.3982015487
Short name T2337
Test name
Test status
Simulation time 175315914 ps
CPU time 0.87 seconds
Started Jul 26 05:13:21 PM PDT 24
Finished Jul 26 05:13:22 PM PDT 24
Peak memory 207340 kb
Host smart-315e8f61-a91a-418c-a85a-7bf8f4f9be4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39820
15487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.3982015487
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.1411905000
Short name T2286
Test name
Test status
Simulation time 232088400 ps
CPU time 1.04 seconds
Started Jul 26 05:13:15 PM PDT 24
Finished Jul 26 05:13:16 PM PDT 24
Peak memory 207124 kb
Host smart-2f471989-3642-489f-ae0d-d29d03099c4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14119
05000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.1411905000
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.2516722523
Short name T469
Test name
Test status
Simulation time 2958592525 ps
CPU time 23.94 seconds
Started Jul 26 05:13:22 PM PDT 24
Finished Jul 26 05:13:46 PM PDT 24
Peak memory 217132 kb
Host smart-3688a9a3-be87-4861-9526-021fe4714fa4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2516722523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.2516722523
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.1553491509
Short name T2136
Test name
Test status
Simulation time 175687231 ps
CPU time 0.85 seconds
Started Jul 26 05:13:16 PM PDT 24
Finished Jul 26 05:13:17 PM PDT 24
Peak memory 207048 kb
Host smart-40c9a3f7-7fd1-4bb0-b579-d745e9f55e4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15534
91509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.1553491509
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.3200629664
Short name T678
Test name
Test status
Simulation time 177665520 ps
CPU time 0.87 seconds
Started Jul 26 05:13:16 PM PDT 24
Finished Jul 26 05:13:17 PM PDT 24
Peak memory 207100 kb
Host smart-d0a8814a-e525-47ce-b492-5745ab2f72bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32006
29664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.3200629664
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.1667135101
Short name T1326
Test name
Test status
Simulation time 1356576856 ps
CPU time 3.29 seconds
Started Jul 26 05:13:17 PM PDT 24
Finished Jul 26 05:13:20 PM PDT 24
Peak memory 207316 kb
Host smart-c702a393-8402-47de-81b3-ed4feb267f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16671
35101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.1667135101
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.810895631
Short name T1797
Test name
Test status
Simulation time 5064086286 ps
CPU time 55.38 seconds
Started Jul 26 05:13:17 PM PDT 24
Finished Jul 26 05:14:12 PM PDT 24
Peak memory 216748 kb
Host smart-b629e3e7-0046-4db3-9738-4e67ec8f9032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81089
5631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.810895631
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_timeout_missing_host_handshake.3225244247
Short name T645
Test name
Test status
Simulation time 2218706832 ps
CPU time 14.25 seconds
Started Jul 26 05:13:13 PM PDT 24
Finished Jul 26 05:13:28 PM PDT 24
Peak memory 207416 kb
Host smart-96056d1a-fec4-4278-ba0c-76e88b9e5ec3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225244247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_timeout_missing_hos
t_handshake.3225244247
Directory /workspace/34.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.4097771698
Short name T2017
Test name
Test status
Simulation time 39353763 ps
CPU time 0.68 seconds
Started Jul 26 05:13:24 PM PDT 24
Finished Jul 26 05:13:25 PM PDT 24
Peak memory 207172 kb
Host smart-4b5a97d8-5313-44f0-8ed0-fe7b2aedea81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4097771698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.4097771698
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.4217292923
Short name T46
Test name
Test status
Simulation time 3411059630 ps
CPU time 5.35 seconds
Started Jul 26 05:13:14 PM PDT 24
Finished Jul 26 05:13:20 PM PDT 24
Peak memory 207252 kb
Host smart-8df5d5e7-6293-4e43-937c-d9878dfcc982
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217292923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_a
on_wake_disconnect.4217292923
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.2343182245
Short name T2583
Test name
Test status
Simulation time 13401829762 ps
CPU time 15.62 seconds
Started Jul 26 05:13:15 PM PDT 24
Finished Jul 26 05:13:31 PM PDT 24
Peak memory 207200 kb
Host smart-90ed4e59-4481-4dbb-8344-7c8e2a897af4
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343182245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.2343182245
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.3927916595
Short name T15
Test name
Test status
Simulation time 23375609326 ps
CPU time 26.84 seconds
Started Jul 26 05:13:23 PM PDT 24
Finished Jul 26 05:13:50 PM PDT 24
Peak memory 207340 kb
Host smart-d58f44c6-1f01-4d44-8169-cba1df97da9f
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927916595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_a
on_wake_resume.3927916595
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.3929647241
Short name T2506
Test name
Test status
Simulation time 199189995 ps
CPU time 1.02 seconds
Started Jul 26 05:13:14 PM PDT 24
Finished Jul 26 05:13:15 PM PDT 24
Peak memory 207024 kb
Host smart-9f39fdb4-6ea4-4d29-bc6c-d7f0ad5756ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39296
47241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.3929647241
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.3756263213
Short name T1687
Test name
Test status
Simulation time 135860495 ps
CPU time 0.83 seconds
Started Jul 26 05:13:16 PM PDT 24
Finished Jul 26 05:13:17 PM PDT 24
Peak memory 207096 kb
Host smart-2ac2604b-2343-476e-8003-4da0d0f5b667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37562
63213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.3756263213
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.2789529948
Short name T932
Test name
Test status
Simulation time 581586572 ps
CPU time 1.79 seconds
Started Jul 26 05:13:23 PM PDT 24
Finished Jul 26 05:13:25 PM PDT 24
Peak memory 207080 kb
Host smart-58e296f0-d0ba-4376-b80b-1fd6eeb79796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27895
29948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.2789529948
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.1093329426
Short name T1525
Test name
Test status
Simulation time 349631636 ps
CPU time 1.23 seconds
Started Jul 26 05:13:23 PM PDT 24
Finished Jul 26 05:13:24 PM PDT 24
Peak memory 207084 kb
Host smart-00f9cc13-0e2e-42b7-9080-c3ee9bc45364
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1093329426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.1093329426
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.946450872
Short name T165
Test name
Test status
Simulation time 19793820271 ps
CPU time 44.05 seconds
Started Jul 26 05:13:15 PM PDT 24
Finished Jul 26 05:14:00 PM PDT 24
Peak memory 207240 kb
Host smart-f7dedc10-2b8f-4e19-b3d0-2a94b764b29c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94645
0872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.946450872
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_device_timeout.525689795
Short name T1497
Test name
Test status
Simulation time 743391068 ps
CPU time 15.86 seconds
Started Jul 26 05:13:18 PM PDT 24
Finished Jul 26 05:13:34 PM PDT 24
Peak memory 207292 kb
Host smart-979fe929-67e9-42c7-977d-c6dd1949b446
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525689795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_timeout.525689795
Directory /workspace/35.usbdev_device_timeout/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.4240091117
Short name T1410
Test name
Test status
Simulation time 389333889 ps
CPU time 1.37 seconds
Started Jul 26 05:13:23 PM PDT 24
Finished Jul 26 05:13:24 PM PDT 24
Peak memory 206992 kb
Host smart-8501b3cb-44e7-4e59-8b56-31b76b404376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42400
91117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.4240091117
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.1770499774
Short name T643
Test name
Test status
Simulation time 158504778 ps
CPU time 0.89 seconds
Started Jul 26 05:13:19 PM PDT 24
Finished Jul 26 05:13:20 PM PDT 24
Peak memory 207004 kb
Host smart-d5b3ac0f-4540-4f37-a365-8de4d6b0e16a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17704
99774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.1770499774
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.4021024250
Short name T2695
Test name
Test status
Simulation time 35411518 ps
CPU time 0.7 seconds
Started Jul 26 05:13:22 PM PDT 24
Finished Jul 26 05:13:23 PM PDT 24
Peak memory 207288 kb
Host smart-bafaa449-4cbe-405a-a1fa-007907390d59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40210
24250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.4021024250
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.195209507
Short name T1071
Test name
Test status
Simulation time 1047527786 ps
CPU time 2.77 seconds
Started Jul 26 05:13:19 PM PDT 24
Finished Jul 26 05:13:22 PM PDT 24
Peak memory 207316 kb
Host smart-fbdb341d-bdc2-4e14-bef0-2c945e5dc483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19520
9507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.195209507
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.776145151
Short name T2414
Test name
Test status
Simulation time 201295899 ps
CPU time 2.39 seconds
Started Jul 26 05:13:22 PM PDT 24
Finished Jul 26 05:13:25 PM PDT 24
Peak memory 207548 kb
Host smart-37e10178-3e5b-4ab5-9217-a3d5f884b060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77614
5151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.776145151
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.1602282271
Short name T668
Test name
Test status
Simulation time 236357440 ps
CPU time 1.18 seconds
Started Jul 26 05:13:17 PM PDT 24
Finished Jul 26 05:13:18 PM PDT 24
Peak memory 207264 kb
Host smart-d6fe0202-88df-4874-8b43-282dff3c2dc4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1602282271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.1602282271
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.2482629325
Short name T2364
Test name
Test status
Simulation time 168659142 ps
CPU time 0.82 seconds
Started Jul 26 05:13:17 PM PDT 24
Finished Jul 26 05:13:18 PM PDT 24
Peak memory 206944 kb
Host smart-bd4f3d5f-92a8-4924-be54-1fc980946f0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24826
29325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.2482629325
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.2052895935
Short name T2202
Test name
Test status
Simulation time 215006187 ps
CPU time 1.06 seconds
Started Jul 26 05:13:23 PM PDT 24
Finished Jul 26 05:13:24 PM PDT 24
Peak memory 207084 kb
Host smart-893e9c20-3dd5-403c-a754-ed9327bae344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20528
95935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.2052895935
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.4054727642
Short name T356
Test name
Test status
Simulation time 9372779768 ps
CPU time 277.03 seconds
Started Jul 26 05:13:23 PM PDT 24
Finished Jul 26 05:18:00 PM PDT 24
Peak memory 215452 kb
Host smart-916dcf2b-a1bf-403e-b5d9-9427718488ee
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4054727642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.4054727642
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/35.usbdev_iso_retraction.856083126
Short name T2633
Test name
Test status
Simulation time 10187381861 ps
CPU time 114.54 seconds
Started Jul 26 05:13:18 PM PDT 24
Finished Jul 26 05:15:13 PM PDT 24
Peak memory 207280 kb
Host smart-dfc74e8c-b047-4f88-8b83-c89e8957ca83
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=856083126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.856083126
Directory /workspace/35.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.854484132
Short name T2077
Test name
Test status
Simulation time 285408507 ps
CPU time 1.07 seconds
Started Jul 26 05:13:22 PM PDT 24
Finished Jul 26 05:13:23 PM PDT 24
Peak memory 207024 kb
Host smart-4ec16674-a165-4322-9d39-5577c462ff8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85448
4132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.854484132
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.1716999427
Short name T1952
Test name
Test status
Simulation time 23330654897 ps
CPU time 33.09 seconds
Started Jul 26 05:13:14 PM PDT 24
Finished Jul 26 05:13:48 PM PDT 24
Peak memory 207280 kb
Host smart-d94c8003-5861-499c-baee-81184c0f4e1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17169
99427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.1716999427
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.2561239531
Short name T1707
Test name
Test status
Simulation time 3288246925 ps
CPU time 5.14 seconds
Started Jul 26 05:13:29 PM PDT 24
Finished Jul 26 05:13:35 PM PDT 24
Peak memory 207348 kb
Host smart-025fc3c8-c4b8-44c0-9af7-eaca366cd341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25612
39531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.2561239531
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.1910488631
Short name T1853
Test name
Test status
Simulation time 7857130340 ps
CPU time 233.99 seconds
Started Jul 26 05:13:26 PM PDT 24
Finished Jul 26 05:17:20 PM PDT 24
Peak memory 215564 kb
Host smart-415da235-1487-470e-8e4d-3e60873700e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19104
88631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.1910488631
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.1510479001
Short name T2496
Test name
Test status
Simulation time 4813706159 ps
CPU time 37.85 seconds
Started Jul 26 05:13:27 PM PDT 24
Finished Jul 26 05:14:05 PM PDT 24
Peak memory 216840 kb
Host smart-ba78c150-a8cf-43a7-8f00-d02b467d967a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1510479001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.1510479001
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.2494717852
Short name T411
Test name
Test status
Simulation time 265893699 ps
CPU time 1.01 seconds
Started Jul 26 05:13:28 PM PDT 24
Finished Jul 26 05:13:29 PM PDT 24
Peak memory 207120 kb
Host smart-b4e073a1-50a7-4f65-a87a-68ad84de9e30
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2494717852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.2494717852
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.2650341849
Short name T2048
Test name
Test status
Simulation time 191375654 ps
CPU time 0.98 seconds
Started Jul 26 05:13:29 PM PDT 24
Finished Jul 26 05:13:30 PM PDT 24
Peak memory 207332 kb
Host smart-9b077acb-7d98-4d29-b784-3fc8cab1048c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26503
41849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.2650341849
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.3692227902
Short name T1996
Test name
Test status
Simulation time 4304590850 ps
CPU time 32.63 seconds
Started Jul 26 05:13:29 PM PDT 24
Finished Jul 26 05:14:02 PM PDT 24
Peak memory 215568 kb
Host smart-ff5c3d75-db4a-4986-9268-b82874fe1edd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36922
27902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.3692227902
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.2058336064
Short name T1916
Test name
Test status
Simulation time 5877768511 ps
CPU time 48.72 seconds
Started Jul 26 05:13:28 PM PDT 24
Finished Jul 26 05:14:17 PM PDT 24
Peak memory 207416 kb
Host smart-83d33d75-b56a-4495-b7a1-8ec8a5248094
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2058336064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.2058336064
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.4274599357
Short name T2395
Test name
Test status
Simulation time 157852971 ps
CPU time 0.87 seconds
Started Jul 26 05:13:29 PM PDT 24
Finished Jul 26 05:13:30 PM PDT 24
Peak memory 207064 kb
Host smart-d665427f-1eb5-4888-aa38-0c1df398d03d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4274599357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.4274599357
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.626539256
Short name T1381
Test name
Test status
Simulation time 149178649 ps
CPU time 0.82 seconds
Started Jul 26 05:13:29 PM PDT 24
Finished Jul 26 05:13:30 PM PDT 24
Peak memory 207024 kb
Host smart-8ead1e82-e1f9-4638-a09c-a600082ac99e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62653
9256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.626539256
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.1779038912
Short name T2386
Test name
Test status
Simulation time 200947464 ps
CPU time 0.97 seconds
Started Jul 26 05:13:24 PM PDT 24
Finished Jul 26 05:13:25 PM PDT 24
Peak memory 207116 kb
Host smart-4db57559-f56f-4645-99c6-bd68a1a410a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17790
38912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.1779038912
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.2778303265
Short name T1702
Test name
Test status
Simulation time 163327055 ps
CPU time 0.86 seconds
Started Jul 26 05:13:26 PM PDT 24
Finished Jul 26 05:13:27 PM PDT 24
Peak memory 207012 kb
Host smart-92c5fedd-8c46-4aab-ac34-2b165c629342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27783
03265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.2778303265
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.163322769
Short name T1664
Test name
Test status
Simulation time 146850158 ps
CPU time 0.87 seconds
Started Jul 26 05:13:35 PM PDT 24
Finished Jul 26 05:13:36 PM PDT 24
Peak memory 207132 kb
Host smart-bc440710-03ab-4b01-a94a-e866bd57550e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16332
2769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.163322769
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.3295685542
Short name T747
Test name
Test status
Simulation time 146694584 ps
CPU time 0.84 seconds
Started Jul 26 05:13:24 PM PDT 24
Finished Jul 26 05:13:25 PM PDT 24
Peak memory 207124 kb
Host smart-1174e967-6bc7-403b-a304-31e080c1f0c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32956
85542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.3295685542
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.2545201949
Short name T1576
Test name
Test status
Simulation time 184350707 ps
CPU time 0.96 seconds
Started Jul 26 05:13:25 PM PDT 24
Finished Jul 26 05:13:26 PM PDT 24
Peak memory 207112 kb
Host smart-51856eca-cbb1-440f-8536-e632cf721142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25452
01949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.2545201949
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.1787162760
Short name T1961
Test name
Test status
Simulation time 239792931 ps
CPU time 1.07 seconds
Started Jul 26 05:13:26 PM PDT 24
Finished Jul 26 05:13:27 PM PDT 24
Peak memory 207068 kb
Host smart-1fc468ef-36d5-4b58-b61f-b958a0a662df
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1787162760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.1787162760
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.3021666969
Short name T833
Test name
Test status
Simulation time 156009651 ps
CPU time 0.81 seconds
Started Jul 26 05:13:29 PM PDT 24
Finished Jul 26 05:13:30 PM PDT 24
Peak memory 207012 kb
Host smart-13708095-c287-4a0d-b7aa-99870100b741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30216
66969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.3021666969
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.4082496218
Short name T1314
Test name
Test status
Simulation time 35111335 ps
CPU time 0.69 seconds
Started Jul 26 05:13:27 PM PDT 24
Finished Jul 26 05:13:28 PM PDT 24
Peak memory 206944 kb
Host smart-b9fae33c-ade4-45c2-beb6-edd7ebfdc7f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40824
96218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.4082496218
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.4028009870
Short name T234
Test name
Test status
Simulation time 7569891207 ps
CPU time 21.16 seconds
Started Jul 26 05:13:35 PM PDT 24
Finished Jul 26 05:13:57 PM PDT 24
Peak memory 215576 kb
Host smart-aa49d198-ba8c-4e23-afec-b16b56e10230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40280
09870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.4028009870
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.1682090406
Short name T1297
Test name
Test status
Simulation time 172705088 ps
CPU time 0.88 seconds
Started Jul 26 05:13:28 PM PDT 24
Finished Jul 26 05:13:29 PM PDT 24
Peak memory 207104 kb
Host smart-cbb029ef-aeda-407e-ae5a-e077b976915e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16820
90406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.1682090406
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.3111460522
Short name T378
Test name
Test status
Simulation time 184325211 ps
CPU time 0.9 seconds
Started Jul 26 05:13:25 PM PDT 24
Finished Jul 26 05:13:26 PM PDT 24
Peak memory 207104 kb
Host smart-b7f5ccb4-b5f7-405c-b75a-01c50a4ab951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31114
60522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.3111460522
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.3347520843
Short name T960
Test name
Test status
Simulation time 246230300 ps
CPU time 0.95 seconds
Started Jul 26 05:13:28 PM PDT 24
Finished Jul 26 05:13:29 PM PDT 24
Peak memory 207036 kb
Host smart-8c304e66-a7e1-47a9-9761-c116544fde82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33475
20843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.3347520843
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.1048493280
Short name T329
Test name
Test status
Simulation time 200424093 ps
CPU time 0.95 seconds
Started Jul 26 05:13:29 PM PDT 24
Finished Jul 26 05:13:31 PM PDT 24
Peak memory 207104 kb
Host smart-74861b38-76d4-4776-a6f4-4b76be777313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10484
93280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.1048493280
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.1435698948
Short name T1078
Test name
Test status
Simulation time 190540531 ps
CPU time 0.89 seconds
Started Jul 26 05:13:27 PM PDT 24
Finished Jul 26 05:13:28 PM PDT 24
Peak memory 207044 kb
Host smart-82930795-218c-412d-ba61-1cecc15f61e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14356
98948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.1435698948
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.1494726560
Short name T1545
Test name
Test status
Simulation time 156373522 ps
CPU time 0.88 seconds
Started Jul 26 05:13:26 PM PDT 24
Finished Jul 26 05:13:28 PM PDT 24
Peak memory 207100 kb
Host smart-85ce00a8-c0c9-41cf-bb85-c53e8264d987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14947
26560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.1494726560
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.3735034619
Short name T2230
Test name
Test status
Simulation time 148032388 ps
CPU time 0.87 seconds
Started Jul 26 05:13:35 PM PDT 24
Finished Jul 26 05:13:36 PM PDT 24
Peak memory 207128 kb
Host smart-5f28c009-0677-4b5f-8626-4b58a43a87ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37350
34619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.3735034619
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.2277739642
Short name T1979
Test name
Test status
Simulation time 177180923 ps
CPU time 0.93 seconds
Started Jul 26 05:13:29 PM PDT 24
Finished Jul 26 05:13:31 PM PDT 24
Peak memory 207056 kb
Host smart-e912a212-038d-4ddd-9bc4-7fd02071f842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22777
39642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.2277739642
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.2877726751
Short name T2227
Test name
Test status
Simulation time 4054279548 ps
CPU time 124.75 seconds
Started Jul 26 05:13:25 PM PDT 24
Finished Jul 26 05:15:30 PM PDT 24
Peak memory 215444 kb
Host smart-d940ce09-d283-41f9-8370-fb3f6bca8676
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2877726751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.2877726751
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.2508415332
Short name T712
Test name
Test status
Simulation time 186667171 ps
CPU time 0.88 seconds
Started Jul 26 05:13:25 PM PDT 24
Finished Jul 26 05:13:27 PM PDT 24
Peak memory 207172 kb
Host smart-fd922d1c-9801-4ebd-ac0a-8189f48e47e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25084
15332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.2508415332
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.1340483214
Short name T832
Test name
Test status
Simulation time 182927492 ps
CPU time 0.96 seconds
Started Jul 26 05:13:30 PM PDT 24
Finished Jul 26 05:13:31 PM PDT 24
Peak memory 207084 kb
Host smart-00f8774d-20f5-40a6-975d-dfff70bde357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13404
83214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.1340483214
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.1044950504
Short name T2714
Test name
Test status
Simulation time 377340644 ps
CPU time 1.32 seconds
Started Jul 26 05:13:31 PM PDT 24
Finished Jul 26 05:13:32 PM PDT 24
Peak memory 207000 kb
Host smart-be4339d3-8f57-4171-96f8-d4d6d98c7c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10449
50504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.1044950504
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.1158648107
Short name T374
Test name
Test status
Simulation time 5716433655 ps
CPU time 175.6 seconds
Started Jul 26 05:13:26 PM PDT 24
Finished Jul 26 05:16:22 PM PDT 24
Peak memory 215484 kb
Host smart-0da25a41-b8b8-49b3-ae91-15dd6ad8143c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11586
48107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.1158648107
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_timeout_missing_host_handshake.2995438575
Short name T1570
Test name
Test status
Simulation time 272549585 ps
CPU time 4.63 seconds
Started Jul 26 05:13:15 PM PDT 24
Finished Jul 26 05:13:20 PM PDT 24
Peak memory 207212 kb
Host smart-142af777-32b8-4535-836a-57842745eb3b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995438575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_timeout_missing_hos
t_handshake.2995438575
Directory /workspace/35.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.1116098130
Short name T1344
Test name
Test status
Simulation time 43575960 ps
CPU time 0.66 seconds
Started Jul 26 05:13:37 PM PDT 24
Finished Jul 26 05:13:38 PM PDT 24
Peak memory 207128 kb
Host smart-20322a32-0edb-457a-a324-29c1d2ad436c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1116098130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.1116098130
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.4263764071
Short name T847
Test name
Test status
Simulation time 3925540427 ps
CPU time 5.69 seconds
Started Jul 26 05:13:27 PM PDT 24
Finished Jul 26 05:13:33 PM PDT 24
Peak memory 207308 kb
Host smart-47fe6279-9528-4787-908d-e899f3e7efdc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263764071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_a
on_wake_disconnect.4263764071
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.4025205153
Short name T879
Test name
Test status
Simulation time 13391902028 ps
CPU time 16.61 seconds
Started Jul 26 05:13:31 PM PDT 24
Finished Jul 26 05:13:48 PM PDT 24
Peak memory 207280 kb
Host smart-9f5b34b0-04e4-4d7d-92a2-ca33c475420e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025205153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.4025205153
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.2650914744
Short name T1140
Test name
Test status
Simulation time 23284550324 ps
CPU time 28.48 seconds
Started Jul 26 05:13:27 PM PDT 24
Finished Jul 26 05:13:55 PM PDT 24
Peak memory 207368 kb
Host smart-7730d8f9-2491-459a-a35c-99325bc2f372
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650914744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_a
on_wake_resume.2650914744
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.369552848
Short name T749
Test name
Test status
Simulation time 202262309 ps
CPU time 0.94 seconds
Started Jul 26 05:13:28 PM PDT 24
Finished Jul 26 05:13:29 PM PDT 24
Peak memory 207092 kb
Host smart-e2edf014-9ee8-4bc6-badc-dd71a0fc938a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36955
2848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.369552848
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.2759506619
Short name T72
Test name
Test status
Simulation time 184272605 ps
CPU time 0.94 seconds
Started Jul 26 05:13:36 PM PDT 24
Finished Jul 26 05:13:37 PM PDT 24
Peak memory 207016 kb
Host smart-47f08f12-ec4e-4049-9af6-375877f617c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27595
06619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.2759506619
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.2681401468
Short name T2672
Test name
Test status
Simulation time 442558003 ps
CPU time 1.58 seconds
Started Jul 26 05:13:35 PM PDT 24
Finished Jul 26 05:13:37 PM PDT 24
Peak memory 207128 kb
Host smart-b5f2ea4e-e068-45a4-8033-218905f54968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26814
01468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.2681401468
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.224723787
Short name T1474
Test name
Test status
Simulation time 348618998 ps
CPU time 1.19 seconds
Started Jul 26 05:13:27 PM PDT 24
Finished Jul 26 05:13:28 PM PDT 24
Peak memory 207016 kb
Host smart-c14e03fa-f4f5-4d24-aefe-118ec8171bac
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=224723787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.224723787
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.2929146286
Short name T2742
Test name
Test status
Simulation time 11896720644 ps
CPU time 26.87 seconds
Started Jul 26 05:13:28 PM PDT 24
Finished Jul 26 05:13:55 PM PDT 24
Peak memory 207404 kb
Host smart-5bc9cb80-49b5-4378-9b7c-b179ea9f2174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29291
46286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.2929146286
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_device_timeout.3422824148
Short name T377
Test name
Test status
Simulation time 4273417519 ps
CPU time 28.69 seconds
Started Jul 26 05:13:35 PM PDT 24
Finished Jul 26 05:14:04 PM PDT 24
Peak memory 207340 kb
Host smart-eb4e55eb-80c8-4619-b7e4-fe6808b164ef
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422824148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_timeout.3422824148
Directory /workspace/36.usbdev_device_timeout/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.2413327511
Short name T328
Test name
Test status
Simulation time 304706373 ps
CPU time 1.26 seconds
Started Jul 26 05:13:29 PM PDT 24
Finished Jul 26 05:13:30 PM PDT 24
Peak memory 207020 kb
Host smart-929f7eb1-161a-4120-8adb-b0f4ca4f3115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24133
27511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.2413327511
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.4270216350
Short name T985
Test name
Test status
Simulation time 139437060 ps
CPU time 0.8 seconds
Started Jul 26 05:13:25 PM PDT 24
Finished Jul 26 05:13:26 PM PDT 24
Peak memory 207020 kb
Host smart-ed4e463c-3f06-49ae-b101-de76420ac653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42702
16350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.4270216350
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.1703303480
Short name T2642
Test name
Test status
Simulation time 106759253 ps
CPU time 0.82 seconds
Started Jul 26 05:13:27 PM PDT 24
Finished Jul 26 05:13:29 PM PDT 24
Peak memory 206900 kb
Host smart-146b2ce7-4091-45c8-9f98-774b36390e02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17033
03480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.1703303480
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.2681130962
Short name T580
Test name
Test status
Simulation time 874418405 ps
CPU time 2.29 seconds
Started Jul 26 05:13:25 PM PDT 24
Finished Jul 26 05:13:27 PM PDT 24
Peak memory 207320 kb
Host smart-9e515e4b-d57c-42e9-80ee-be2eca0de824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26811
30962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.2681130962
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.2989119971
Short name T1507
Test name
Test status
Simulation time 200556429 ps
CPU time 1.5 seconds
Started Jul 26 05:13:26 PM PDT 24
Finished Jul 26 05:13:27 PM PDT 24
Peak memory 207308 kb
Host smart-27a7af7e-dce4-4061-a4cc-b13a98a5323f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29891
19971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.2989119971
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.3957020686
Short name T90
Test name
Test status
Simulation time 165192219 ps
CPU time 0.91 seconds
Started Jul 26 05:13:30 PM PDT 24
Finished Jul 26 05:13:31 PM PDT 24
Peak memory 207028 kb
Host smart-ebdadb54-07f3-4489-be21-2be23aaec50d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3957020686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.3957020686
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.2129970464
Short name T1165
Test name
Test status
Simulation time 152440373 ps
CPU time 0.84 seconds
Started Jul 26 05:13:27 PM PDT 24
Finished Jul 26 05:13:28 PM PDT 24
Peak memory 207104 kb
Host smart-14cddeba-eed4-4bc9-bcdf-70bb4489f51c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21299
70464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.2129970464
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.1171584104
Short name T1607
Test name
Test status
Simulation time 208306618 ps
CPU time 0.95 seconds
Started Jul 26 05:13:26 PM PDT 24
Finished Jul 26 05:13:27 PM PDT 24
Peak memory 207132 kb
Host smart-d4462222-3646-4738-8b6f-11a32175863a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11715
84104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.1171584104
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_invalid_sync.3644488006
Short name T2653
Test name
Test status
Simulation time 5102399438 ps
CPU time 53.24 seconds
Started Jul 26 05:13:22 PM PDT 24
Finished Jul 26 05:14:16 PM PDT 24
Peak memory 215556 kb
Host smart-8cb94b30-4a61-4144-8334-07e3b391182d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3644488006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.3644488006
Directory /workspace/36.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/36.usbdev_iso_retraction.3935572951
Short name T1876
Test name
Test status
Simulation time 12652975158 ps
CPU time 152.3 seconds
Started Jul 26 05:13:39 PM PDT 24
Finished Jul 26 05:16:11 PM PDT 24
Peak memory 207272 kb
Host smart-3f18edc7-b010-48d0-bf6a-634dc4cc023c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3935572951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_iso_retraction.3935572951
Directory /workspace/36.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.187180604
Short name T710
Test name
Test status
Simulation time 198627083 ps
CPU time 1.03 seconds
Started Jul 26 05:13:26 PM PDT 24
Finished Jul 26 05:13:27 PM PDT 24
Peak memory 207100 kb
Host smart-21ebce9b-8aba-4f1f-a025-4320be39adfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18718
0604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.187180604
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.2372732698
Short name T390
Test name
Test status
Simulation time 23329008069 ps
CPU time 27.61 seconds
Started Jul 26 05:13:25 PM PDT 24
Finished Jul 26 05:13:53 PM PDT 24
Peak memory 207332 kb
Host smart-1f1558f8-e05a-49d2-b7b4-d06947abb704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23727
32698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.2372732698
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.3637323257
Short name T1536
Test name
Test status
Simulation time 3294864273 ps
CPU time 5.03 seconds
Started Jul 26 05:13:31 PM PDT 24
Finished Jul 26 05:13:37 PM PDT 24
Peak memory 207276 kb
Host smart-0beb535c-04f9-42bb-8af6-b5f8ecb1384d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36373
23257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.3637323257
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.3765647685
Short name T304
Test name
Test status
Simulation time 8555572945 ps
CPU time 84.99 seconds
Started Jul 26 05:13:26 PM PDT 24
Finished Jul 26 05:14:52 PM PDT 24
Peak memory 217496 kb
Host smart-f453815c-1308-4627-a975-ab8910e93527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37656
47685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.3765647685
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.2692756308
Short name T941
Test name
Test status
Simulation time 5424823292 ps
CPU time 158.84 seconds
Started Jul 26 05:13:30 PM PDT 24
Finished Jul 26 05:16:09 PM PDT 24
Peak memory 215576 kb
Host smart-5905b88e-947c-4575-b070-23fbdb37d382
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2692756308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.2692756308
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.1101432660
Short name T467
Test name
Test status
Simulation time 256461908 ps
CPU time 0.98 seconds
Started Jul 26 05:13:25 PM PDT 24
Finished Jul 26 05:13:26 PM PDT 24
Peak memory 207108 kb
Host smart-f92119d2-7c51-4b8d-b065-a2a1b76cc190
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1101432660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.1101432660
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.1901711805
Short name T954
Test name
Test status
Simulation time 217739866 ps
CPU time 0.94 seconds
Started Jul 26 05:13:30 PM PDT 24
Finished Jul 26 05:13:31 PM PDT 24
Peak memory 207104 kb
Host smart-286dc21d-037b-473e-ac49-a70c479e3fa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19017
11805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.1901711805
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.2320336126
Short name T2137
Test name
Test status
Simulation time 6914609234 ps
CPU time 203.22 seconds
Started Jul 26 05:13:37 PM PDT 24
Finished Jul 26 05:17:01 PM PDT 24
Peak memory 215444 kb
Host smart-5b86264d-a66b-4948-b270-502c0018da02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23203
36126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.2320336126
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.1945057196
Short name T1226
Test name
Test status
Simulation time 5495910857 ps
CPU time 52.64 seconds
Started Jul 26 05:13:36 PM PDT 24
Finished Jul 26 05:14:29 PM PDT 24
Peak memory 217060 kb
Host smart-8f15080a-a0af-4fce-b012-bc80193024a3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1945057196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.1945057196
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.2747032208
Short name T2030
Test name
Test status
Simulation time 152108429 ps
CPU time 0.82 seconds
Started Jul 26 05:13:37 PM PDT 24
Finished Jul 26 05:13:39 PM PDT 24
Peak memory 207360 kb
Host smart-3811955f-c5a0-4ae2-8613-e8cfef27d7dd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2747032208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.2747032208
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.3406417853
Short name T1615
Test name
Test status
Simulation time 154941774 ps
CPU time 0.85 seconds
Started Jul 26 05:13:37 PM PDT 24
Finished Jul 26 05:13:39 PM PDT 24
Peak memory 207212 kb
Host smart-1d9d4b4d-a856-43ca-9ed4-875372ba2e67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34064
17853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.3406417853
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.3060755860
Short name T2427
Test name
Test status
Simulation time 183332011 ps
CPU time 0.97 seconds
Started Jul 26 05:13:39 PM PDT 24
Finished Jul 26 05:13:40 PM PDT 24
Peak memory 207140 kb
Host smart-1968b28d-2ed1-4d7a-a441-e35a89741434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30607
55860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.3060755860
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.1256982855
Short name T1260
Test name
Test status
Simulation time 172084048 ps
CPU time 0.9 seconds
Started Jul 26 05:13:38 PM PDT 24
Finished Jul 26 05:13:39 PM PDT 24
Peak memory 206976 kb
Host smart-7b740d26-2c9a-400a-99f9-823df83410e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12569
82855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.1256982855
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.3285144155
Short name T23
Test name
Test status
Simulation time 162829768 ps
CPU time 0.84 seconds
Started Jul 26 05:13:41 PM PDT 24
Finished Jul 26 05:13:42 PM PDT 24
Peak memory 207116 kb
Host smart-18633328-40db-4d3c-a751-48c694f5f3e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32851
44155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.3285144155
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.1351614411
Short name T1276
Test name
Test status
Simulation time 151365439 ps
CPU time 0.9 seconds
Started Jul 26 05:13:37 PM PDT 24
Finished Jul 26 05:13:38 PM PDT 24
Peak memory 207132 kb
Host smart-0b3ade00-cc6c-49c0-84a4-8a1c23c8ec68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13516
14411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.1351614411
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.1495516141
Short name T421
Test name
Test status
Simulation time 152855531 ps
CPU time 0.86 seconds
Started Jul 26 05:13:41 PM PDT 24
Finished Jul 26 05:13:42 PM PDT 24
Peak memory 207092 kb
Host smart-883798e3-a58d-4003-a1fc-13f6fec35cf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14955
16141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.1495516141
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.524624607
Short name T1777
Test name
Test status
Simulation time 231084797 ps
CPU time 1.17 seconds
Started Jul 26 05:13:36 PM PDT 24
Finished Jul 26 05:13:38 PM PDT 24
Peak memory 207076 kb
Host smart-e50b059d-c91b-4f64-a0ca-5c77fd229539
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=524624607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.524624607
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.3077822155
Short name T1125
Test name
Test status
Simulation time 149188249 ps
CPU time 0.9 seconds
Started Jul 26 05:13:36 PM PDT 24
Finished Jul 26 05:13:37 PM PDT 24
Peak memory 207096 kb
Host smart-44d7191d-14b9-4671-a019-412a7445cad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30778
22155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.3077822155
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.1082076490
Short name T813
Test name
Test status
Simulation time 99362711 ps
CPU time 0.78 seconds
Started Jul 26 05:13:38 PM PDT 24
Finished Jul 26 05:13:39 PM PDT 24
Peak memory 207024 kb
Host smart-3e42da46-cd8d-46b7-8c47-78c4df52f030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10820
76490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.1082076490
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.1108986094
Short name T1369
Test name
Test status
Simulation time 12322581612 ps
CPU time 35.98 seconds
Started Jul 26 05:13:36 PM PDT 24
Finished Jul 26 05:14:13 PM PDT 24
Peak memory 223772 kb
Host smart-b8ad019b-f1ec-435e-8ad2-7624349b550a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11089
86094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.1108986094
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.2005189178
Short name T889
Test name
Test status
Simulation time 183209186 ps
CPU time 0.96 seconds
Started Jul 26 05:13:37 PM PDT 24
Finished Jul 26 05:13:38 PM PDT 24
Peak memory 207048 kb
Host smart-1226d768-dc52-4690-8db1-3e71f96305cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20051
89178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.2005189178
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.1102251909
Short name T2610
Test name
Test status
Simulation time 223383867 ps
CPU time 1 seconds
Started Jul 26 05:13:41 PM PDT 24
Finished Jul 26 05:13:42 PM PDT 24
Peak memory 207104 kb
Host smart-25faf44c-a261-49d9-8000-574abdc2a210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11022
51909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.1102251909
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.1220985004
Short name T1696
Test name
Test status
Simulation time 264089644 ps
CPU time 1.13 seconds
Started Jul 26 05:13:42 PM PDT 24
Finished Jul 26 05:13:43 PM PDT 24
Peak memory 207064 kb
Host smart-d2282f5d-a538-4f10-8528-e5d04c490742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12209
85004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.1220985004
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.1994635519
Short name T726
Test name
Test status
Simulation time 167775631 ps
CPU time 0.87 seconds
Started Jul 26 05:13:35 PM PDT 24
Finished Jul 26 05:13:36 PM PDT 24
Peak memory 207024 kb
Host smart-cbb3e964-e140-4659-b0a4-dc5259e20d91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19946
35519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.1994635519
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.2605539438
Short name T910
Test name
Test status
Simulation time 157208902 ps
CPU time 0.84 seconds
Started Jul 26 05:13:37 PM PDT 24
Finished Jul 26 05:13:39 PM PDT 24
Peak memory 207104 kb
Host smart-7dd11a27-3841-49b5-86f0-29cc4f5587d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26055
39438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.2605539438
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.1702620655
Short name T798
Test name
Test status
Simulation time 224361693 ps
CPU time 0.94 seconds
Started Jul 26 05:13:38 PM PDT 24
Finished Jul 26 05:13:39 PM PDT 24
Peak memory 206952 kb
Host smart-8657b91b-4d62-4f97-a5d1-d564b2a98760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17026
20655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.1702620655
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.3757895816
Short name T2056
Test name
Test status
Simulation time 164925868 ps
CPU time 0.88 seconds
Started Jul 26 05:13:37 PM PDT 24
Finished Jul 26 05:13:38 PM PDT 24
Peak memory 207028 kb
Host smart-b01f752c-6f73-4506-97a2-4ffa8ec7122a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37578
95816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.3757895816
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.3821282151
Short name T2807
Test name
Test status
Simulation time 251797485 ps
CPU time 1.04 seconds
Started Jul 26 05:13:41 PM PDT 24
Finished Jul 26 05:13:42 PM PDT 24
Peak memory 207028 kb
Host smart-d6c8868a-aa96-41b0-9a92-01077a89600b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38212
82151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.3821282151
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.2812824317
Short name T1084
Test name
Test status
Simulation time 5255988384 ps
CPU time 155.22 seconds
Started Jul 26 05:13:38 PM PDT 24
Finished Jul 26 05:16:13 PM PDT 24
Peak memory 215592 kb
Host smart-e5d45c54-1937-49ff-8614-dc8fee727529
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2812824317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.2812824317
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.3458353207
Short name T1669
Test name
Test status
Simulation time 164253230 ps
CPU time 0.89 seconds
Started Jul 26 05:13:35 PM PDT 24
Finished Jul 26 05:13:36 PM PDT 24
Peak memory 206980 kb
Host smart-9c3e1fb3-a8a7-46b9-b56e-ec1d4f2d42c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34583
53207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.3458353207
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.1125932430
Short name T17
Test name
Test status
Simulation time 195551251 ps
CPU time 0.9 seconds
Started Jul 26 05:13:42 PM PDT 24
Finished Jul 26 05:13:43 PM PDT 24
Peak memory 207028 kb
Host smart-63ca4e41-84dd-4af5-811f-8a3c2c93b430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11259
32430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.1125932430
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.3346658524
Short name T817
Test name
Test status
Simulation time 1015495077 ps
CPU time 2.66 seconds
Started Jul 26 05:13:39 PM PDT 24
Finished Jul 26 05:13:42 PM PDT 24
Peak memory 207328 kb
Host smart-7ba9ac69-d6b6-406a-a56e-70025478e5bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33466
58524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.3346658524
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.926204532
Short name T897
Test name
Test status
Simulation time 5046450400 ps
CPU time 150.28 seconds
Started Jul 26 05:13:38 PM PDT 24
Finished Jul 26 05:16:08 PM PDT 24
Peak memory 215508 kb
Host smart-becf385f-050c-43c4-9dd9-80323323bd3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92620
4532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.926204532
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_timeout_missing_host_handshake.992657148
Short name T2859
Test name
Test status
Simulation time 188930040 ps
CPU time 0.98 seconds
Started Jul 26 05:13:25 PM PDT 24
Finished Jul 26 05:13:27 PM PDT 24
Peak memory 207092 kb
Host smart-1c2d8545-241b-4bf5-973b-0ac5d963e002
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992657148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_timeout_missing_host
_handshake.992657148
Directory /workspace/36.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.2493290090
Short name T1937
Test name
Test status
Simulation time 64176404 ps
CPU time 0.73 seconds
Started Jul 26 05:13:52 PM PDT 24
Finished Jul 26 05:13:53 PM PDT 24
Peak memory 207072 kb
Host smart-a0f5a37a-cf71-49ac-b067-462aa2bb3aab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2493290090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.2493290090
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.2776370324
Short name T2623
Test name
Test status
Simulation time 4351258106 ps
CPU time 6.37 seconds
Started Jul 26 05:13:40 PM PDT 24
Finished Jul 26 05:13:46 PM PDT 24
Peak memory 207220 kb
Host smart-debf5e9b-6052-479a-b2e8-631f8fe21203
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776370324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_a
on_wake_disconnect.2776370324
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.2157114683
Short name T1446
Test name
Test status
Simulation time 13399170277 ps
CPU time 19.56 seconds
Started Jul 26 05:13:37 PM PDT 24
Finished Jul 26 05:13:57 PM PDT 24
Peak memory 207408 kb
Host smart-dc1c59cf-0dca-4d1a-a8b1-ce8ec122b263
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157114683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.2157114683
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.2701824271
Short name T2012
Test name
Test status
Simulation time 23411843303 ps
CPU time 31.9 seconds
Started Jul 26 05:13:41 PM PDT 24
Finished Jul 26 05:14:13 PM PDT 24
Peak memory 207288 kb
Host smart-6b3ce17c-ed6b-40b0-bdb4-52f7488b5171
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701824271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_a
on_wake_resume.2701824271
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.14312453
Short name T2103
Test name
Test status
Simulation time 194214352 ps
CPU time 0.95 seconds
Started Jul 26 05:13:41 PM PDT 24
Finished Jul 26 05:13:42 PM PDT 24
Peak memory 207060 kb
Host smart-05ed28d0-4c86-45fd-b162-6f39b91f2a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14312
453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.14312453
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.3817950548
Short name T1120
Test name
Test status
Simulation time 218447525 ps
CPU time 0.93 seconds
Started Jul 26 05:13:39 PM PDT 24
Finished Jul 26 05:13:40 PM PDT 24
Peak memory 207044 kb
Host smart-09c0e682-8514-4240-b6e2-89cf74c3cf19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38179
50548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.3817950548
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.175144722
Short name T2457
Test name
Test status
Simulation time 196076331 ps
CPU time 0.94 seconds
Started Jul 26 05:13:38 PM PDT 24
Finished Jul 26 05:13:39 PM PDT 24
Peak memory 207112 kb
Host smart-5f0c9daa-2c41-4e04-a289-d5363ebbbbe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17514
4722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.175144722
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.2083177692
Short name T2053
Test name
Test status
Simulation time 404300417 ps
CPU time 1.43 seconds
Started Jul 26 05:13:37 PM PDT 24
Finished Jul 26 05:13:39 PM PDT 24
Peak memory 207024 kb
Host smart-b7c2867f-ac23-49be-b48d-c64b16d99f38
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2083177692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.2083177692
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_timeout.1361897112
Short name T674
Test name
Test status
Simulation time 1234706739 ps
CPU time 30.71 seconds
Started Jul 26 05:13:36 PM PDT 24
Finished Jul 26 05:14:07 PM PDT 24
Peak memory 207372 kb
Host smart-5adb957d-ff32-44cf-b4a8-f668241d195f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361897112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_timeout.1361897112
Directory /workspace/37.usbdev_device_timeout/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.4173103851
Short name T2641
Test name
Test status
Simulation time 456227094 ps
CPU time 1.46 seconds
Started Jul 26 05:13:40 PM PDT 24
Finished Jul 26 05:13:41 PM PDT 24
Peak memory 206956 kb
Host smart-e6fcf546-e769-47c6-ac8a-93792e276a1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41731
03851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.4173103851
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.3823505854
Short name T2594
Test name
Test status
Simulation time 207036932 ps
CPU time 1.01 seconds
Started Jul 26 05:13:38 PM PDT 24
Finished Jul 26 05:13:40 PM PDT 24
Peak memory 207100 kb
Host smart-c62cca6d-76d0-486b-9823-cfb91add9003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38235
05854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.3823505854
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.66316262
Short name T1166
Test name
Test status
Simulation time 121373529 ps
CPU time 0.78 seconds
Started Jul 26 05:13:42 PM PDT 24
Finished Jul 26 05:13:43 PM PDT 24
Peak memory 207028 kb
Host smart-adbe6f7c-cd69-4eba-aad2-330d5520fc9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66316
262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.66316262
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.3734647395
Short name T2432
Test name
Test status
Simulation time 876581464 ps
CPU time 2.21 seconds
Started Jul 26 05:13:37 PM PDT 24
Finished Jul 26 05:13:40 PM PDT 24
Peak memory 207392 kb
Host smart-3e2a2be8-6fd8-4a3b-9b76-075ffaec9390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37346
47395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.3734647395
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.2057969211
Short name T1575
Test name
Test status
Simulation time 164603444 ps
CPU time 1.72 seconds
Started Jul 26 05:13:40 PM PDT 24
Finished Jul 26 05:13:42 PM PDT 24
Peak memory 207220 kb
Host smart-211d428b-911d-4ba1-addc-6f563a539f9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20579
69211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.2057969211
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.3172846559
Short name T782
Test name
Test status
Simulation time 186096501 ps
CPU time 1.05 seconds
Started Jul 26 05:13:39 PM PDT 24
Finished Jul 26 05:13:41 PM PDT 24
Peak memory 215480 kb
Host smart-078bff6a-e09a-48a3-b6e0-c92c1203fa5b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3172846559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.3172846559
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.2401472952
Short name T2510
Test name
Test status
Simulation time 153193835 ps
CPU time 0.87 seconds
Started Jul 26 05:13:36 PM PDT 24
Finished Jul 26 05:13:38 PM PDT 24
Peak memory 207072 kb
Host smart-e9fb931c-6665-4eca-b87a-071f22221a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24014
72952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.2401472952
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.4152302688
Short name T2554
Test name
Test status
Simulation time 198263765 ps
CPU time 1 seconds
Started Jul 26 05:13:39 PM PDT 24
Finished Jul 26 05:13:40 PM PDT 24
Peak memory 207064 kb
Host smart-3949177a-16a3-4a63-a647-2ffadeaf0f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41523
02688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.4152302688
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.1152363522
Short name T2547
Test name
Test status
Simulation time 7098505210 ps
CPU time 81.4 seconds
Started Jul 26 05:13:38 PM PDT 24
Finished Jul 26 05:15:00 PM PDT 24
Peak memory 216712 kb
Host smart-b713630d-f594-4484-8e4d-2d120f7bfaec
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1152363522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.1152363522
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.3896013775
Short name T2847
Test name
Test status
Simulation time 196843095 ps
CPU time 0.94 seconds
Started Jul 26 05:13:41 PM PDT 24
Finished Jul 26 05:13:42 PM PDT 24
Peak memory 207064 kb
Host smart-0ecfb0a1-485c-4408-a8f7-de9a7b7c8a58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38960
13775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.3896013775
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.530275391
Short name T472
Test name
Test status
Simulation time 23320119442 ps
CPU time 29.74 seconds
Started Jul 26 05:13:40 PM PDT 24
Finished Jul 26 05:14:10 PM PDT 24
Peak memory 207220 kb
Host smart-50ce23bd-a335-4145-bcce-922a0d9c1505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53027
5391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.530275391
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.8333507
Short name T1017
Test name
Test status
Simulation time 3272333208 ps
CPU time 5.74 seconds
Started Jul 26 05:13:37 PM PDT 24
Finished Jul 26 05:13:43 PM PDT 24
Peak memory 207344 kb
Host smart-7bd3847c-4526-4022-86e3-327cbed9dd59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83335
07 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.8333507
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.2952120995
Short name T2132
Test name
Test status
Simulation time 9064254036 ps
CPU time 93.15 seconds
Started Jul 26 05:13:39 PM PDT 24
Finished Jul 26 05:15:12 PM PDT 24
Peak memory 217576 kb
Host smart-7287e607-48af-4472-8e72-703bae922d3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29521
20995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.2952120995
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.799308904
Short name T738
Test name
Test status
Simulation time 4147296538 ps
CPU time 123.44 seconds
Started Jul 26 05:13:38 PM PDT 24
Finished Jul 26 05:15:42 PM PDT 24
Peak memory 215580 kb
Host smart-da682125-6159-4d22-acb6-c6cf1ee51469
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=799308904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.799308904
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.1969234338
Short name T2365
Test name
Test status
Simulation time 236423169 ps
CPU time 1.07 seconds
Started Jul 26 05:13:37 PM PDT 24
Finished Jul 26 05:13:39 PM PDT 24
Peak memory 207104 kb
Host smart-a78ddb9a-7b85-4aa9-9f99-b9363907279c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1969234338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.1969234338
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.3211360098
Short name T597
Test name
Test status
Simulation time 202143672 ps
CPU time 1.1 seconds
Started Jul 26 05:13:36 PM PDT 24
Finished Jul 26 05:13:37 PM PDT 24
Peak memory 207048 kb
Host smart-fed3ed1c-a86f-46d2-94ea-d6aa24db81e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32113
60098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.3211360098
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.83579486
Short name T166
Test name
Test status
Simulation time 5758466432 ps
CPU time 61.6 seconds
Started Jul 26 05:13:37 PM PDT 24
Finished Jul 26 05:14:39 PM PDT 24
Peak memory 217172 kb
Host smart-9437836f-452a-402b-b966-b6044acc0c8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83579
486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.83579486
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.4206161631
Short name T431
Test name
Test status
Simulation time 7320666080 ps
CPU time 210.35 seconds
Started Jul 26 05:13:38 PM PDT 24
Finished Jul 26 05:17:09 PM PDT 24
Peak memory 215512 kb
Host smart-6285b064-d600-40fc-939c-7d18e7e501da
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4206161631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.4206161631
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.2491616646
Short name T2629
Test name
Test status
Simulation time 152785530 ps
CPU time 0.82 seconds
Started Jul 26 05:13:38 PM PDT 24
Finished Jul 26 05:13:39 PM PDT 24
Peak memory 207124 kb
Host smart-30954e9f-e575-4c24-8be3-9722c5df1937
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2491616646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.2491616646
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.3580760337
Short name T1461
Test name
Test status
Simulation time 210417481 ps
CPU time 0.95 seconds
Started Jul 26 05:13:39 PM PDT 24
Finished Jul 26 05:13:40 PM PDT 24
Peak memory 207056 kb
Host smart-a1c1ac09-661f-47f2-b039-044c6774313d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35807
60337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.3580760337
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.2192960774
Short name T117
Test name
Test status
Simulation time 183133384 ps
CPU time 0.88 seconds
Started Jul 26 05:13:51 PM PDT 24
Finished Jul 26 05:13:52 PM PDT 24
Peak memory 207084 kb
Host smart-b53b1497-9283-4037-85cd-88a91e7b8a30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21929
60774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.2192960774
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.971523610
Short name T2283
Test name
Test status
Simulation time 151102461 ps
CPU time 0.84 seconds
Started Jul 26 05:13:51 PM PDT 24
Finished Jul 26 05:13:52 PM PDT 24
Peak memory 207120 kb
Host smart-ec1c940f-478a-4b1a-b24e-b22bf41a2736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97152
3610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.971523610
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.2054973408
Short name T2171
Test name
Test status
Simulation time 163336005 ps
CPU time 0.96 seconds
Started Jul 26 05:13:52 PM PDT 24
Finished Jul 26 05:13:53 PM PDT 24
Peak memory 207136 kb
Host smart-982461ef-0368-48f9-b1dd-4a89d23455df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20549
73408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.2054973408
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.3187817572
Short name T2092
Test name
Test status
Simulation time 154552188 ps
CPU time 0.88 seconds
Started Jul 26 05:13:50 PM PDT 24
Finished Jul 26 05:13:51 PM PDT 24
Peak memory 207024 kb
Host smart-25bff53e-eb2b-4552-b90c-ad6482512c6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31878
17572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.3187817572
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.3722914933
Short name T1849
Test name
Test status
Simulation time 145152125 ps
CPU time 0.85 seconds
Started Jul 26 05:13:48 PM PDT 24
Finished Jul 26 05:13:49 PM PDT 24
Peak memory 207096 kb
Host smart-818a9a74-3209-4779-a15f-c163720ae797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37229
14933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.3722914933
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.1698606572
Short name T1272
Test name
Test status
Simulation time 205066910 ps
CPU time 0.99 seconds
Started Jul 26 05:13:50 PM PDT 24
Finished Jul 26 05:13:51 PM PDT 24
Peak memory 207156 kb
Host smart-b608fd63-f4f9-41e5-88a5-183ffcb90db2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1698606572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.1698606572
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.3176336760
Short name T2855
Test name
Test status
Simulation time 143135924 ps
CPU time 0.79 seconds
Started Jul 26 05:13:49 PM PDT 24
Finished Jul 26 05:13:50 PM PDT 24
Peak memory 207040 kb
Host smart-2331dbd8-4a81-40ec-abd9-3d8cf2216082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31763
36760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.3176336760
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.2431241931
Short name T903
Test name
Test status
Simulation time 49580091 ps
CPU time 0.74 seconds
Started Jul 26 05:13:51 PM PDT 24
Finished Jul 26 05:13:52 PM PDT 24
Peak memory 206904 kb
Host smart-d4ff3b57-3b02-4a68-9cef-a80ab5c68bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24312
41931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.2431241931
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.723270852
Short name T237
Test name
Test status
Simulation time 11014216866 ps
CPU time 27.02 seconds
Started Jul 26 05:13:55 PM PDT 24
Finished Jul 26 05:14:22 PM PDT 24
Peak memory 215528 kb
Host smart-bf3d39bc-97a0-40b9-a6b7-3bbe0e83d8ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72327
0852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.723270852
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.2883331663
Short name T820
Test name
Test status
Simulation time 147850782 ps
CPU time 0.94 seconds
Started Jul 26 05:13:49 PM PDT 24
Finished Jul 26 05:13:50 PM PDT 24
Peak memory 207096 kb
Host smart-0cfe5ae0-8386-4da8-be0c-13ddc8697b08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28833
31663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.2883331663
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.195092633
Short name T558
Test name
Test status
Simulation time 234117025 ps
CPU time 0.94 seconds
Started Jul 26 05:13:54 PM PDT 24
Finished Jul 26 05:13:55 PM PDT 24
Peak memory 207136 kb
Host smart-f54fe099-d5c3-4382-ba73-7ddd7738aa95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19509
2633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.195092633
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.26618141
Short name T2142
Test name
Test status
Simulation time 245403257 ps
CPU time 0.99 seconds
Started Jul 26 05:13:50 PM PDT 24
Finished Jul 26 05:13:51 PM PDT 24
Peak memory 207116 kb
Host smart-31afea21-4500-4913-a185-10b6c2cad119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26618
141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.26618141
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.3424841068
Short name T2669
Test name
Test status
Simulation time 243141788 ps
CPU time 0.98 seconds
Started Jul 26 05:13:50 PM PDT 24
Finished Jul 26 05:13:52 PM PDT 24
Peak memory 207068 kb
Host smart-ac41d63f-dac1-4e8c-8630-73b9e735a1b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34248
41068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.3424841068
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.2231840111
Short name T2164
Test name
Test status
Simulation time 166440670 ps
CPU time 0.86 seconds
Started Jul 26 05:13:50 PM PDT 24
Finished Jul 26 05:13:51 PM PDT 24
Peak memory 207096 kb
Host smart-7f737196-fb35-41e2-b6fe-96a9747d29b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22318
40111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.2231840111
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.145371332
Short name T1699
Test name
Test status
Simulation time 172694461 ps
CPU time 0.88 seconds
Started Jul 26 05:13:48 PM PDT 24
Finished Jul 26 05:13:49 PM PDT 24
Peak memory 206984 kb
Host smart-7d13bd11-124c-4bbd-994f-98183d59325e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14537
1332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.145371332
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.2294521091
Short name T1841
Test name
Test status
Simulation time 143702075 ps
CPU time 0.84 seconds
Started Jul 26 05:13:49 PM PDT 24
Finished Jul 26 05:13:50 PM PDT 24
Peak memory 207048 kb
Host smart-a453762a-29b9-455b-bdaf-bd52764c087d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22945
21091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.2294521091
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.3380038032
Short name T942
Test name
Test status
Simulation time 263800981 ps
CPU time 1.03 seconds
Started Jul 26 05:13:55 PM PDT 24
Finished Jul 26 05:13:56 PM PDT 24
Peak memory 207044 kb
Host smart-a46ed41f-4e31-43d7-9949-405c659bb1c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33800
38032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.3380038032
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.2395636475
Short name T2508
Test name
Test status
Simulation time 5669535037 ps
CPU time 166.17 seconds
Started Jul 26 05:13:49 PM PDT 24
Finished Jul 26 05:16:36 PM PDT 24
Peak memory 215392 kb
Host smart-d7ffc0c9-0e1b-40c2-b213-684b36345bfb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2395636475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.2395636475
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.3732911839
Short name T1024
Test name
Test status
Simulation time 159254598 ps
CPU time 0.85 seconds
Started Jul 26 05:13:49 PM PDT 24
Finished Jul 26 05:13:50 PM PDT 24
Peak memory 207084 kb
Host smart-67328290-ba0a-4278-9d5d-c989f82a86f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37329
11839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.3732911839
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.3703550122
Short name T1457
Test name
Test status
Simulation time 178448667 ps
CPU time 0.92 seconds
Started Jul 26 05:13:50 PM PDT 24
Finished Jul 26 05:13:51 PM PDT 24
Peak memory 207080 kb
Host smart-db617d39-bc70-4c3d-80e3-5062f0f7549a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37035
50122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.3703550122
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.644607282
Short name T1472
Test name
Test status
Simulation time 318517724 ps
CPU time 1.18 seconds
Started Jul 26 05:13:53 PM PDT 24
Finished Jul 26 05:13:55 PM PDT 24
Peak memory 207020 kb
Host smart-39c73099-19c9-4774-8142-b16114552d0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64460
7282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.644607282
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.3868079152
Short name T523
Test name
Test status
Simulation time 5657365289 ps
CPU time 44.06 seconds
Started Jul 26 05:13:53 PM PDT 24
Finished Jul 26 05:14:37 PM PDT 24
Peak memory 215508 kb
Host smart-2c1b1941-f56b-4ea6-b2f9-cbe48a8a7404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38680
79152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.3868079152
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_timeout_missing_host_handshake.2001336817
Short name T1035
Test name
Test status
Simulation time 170025094 ps
CPU time 0.84 seconds
Started Jul 26 05:13:39 PM PDT 24
Finished Jul 26 05:13:40 PM PDT 24
Peak memory 207056 kb
Host smart-435aa80c-d2fc-447a-9536-1f3d2186875d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001336817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_timeout_missing_hos
t_handshake.2001336817
Directory /workspace/37.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.4290136543
Short name T1023
Test name
Test status
Simulation time 41351532 ps
CPU time 0.71 seconds
Started Jul 26 05:14:13 PM PDT 24
Finished Jul 26 05:14:14 PM PDT 24
Peak memory 207128 kb
Host smart-20ecfb38-ab7d-4aa6-8a33-41760e824373
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4290136543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.4290136543
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.3757794333
Short name T916
Test name
Test status
Simulation time 4228352447 ps
CPU time 7.08 seconds
Started Jul 26 05:13:50 PM PDT 24
Finished Jul 26 05:13:57 PM PDT 24
Peak memory 207372 kb
Host smart-2a51d2a3-6ffe-4d44-9666-d3b3622fe8e4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757794333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_a
on_wake_disconnect.3757794333
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.889371554
Short name T1348
Test name
Test status
Simulation time 13362157314 ps
CPU time 16.24 seconds
Started Jul 26 05:13:50 PM PDT 24
Finished Jul 26 05:14:06 PM PDT 24
Peak memory 207316 kb
Host smart-ba5713e2-16ed-46ba-b61a-d5d3e564005a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=889371554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.889371554
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.925274627
Short name T2573
Test name
Test status
Simulation time 23451124586 ps
CPU time 28.11 seconds
Started Jul 26 05:13:50 PM PDT 24
Finished Jul 26 05:14:18 PM PDT 24
Peak memory 207336 kb
Host smart-37c821df-904f-47d5-8ef2-32667a82f938
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925274627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_ao
n_wake_resume.925274627
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.3635673762
Short name T2744
Test name
Test status
Simulation time 167611113 ps
CPU time 0.9 seconds
Started Jul 26 05:13:48 PM PDT 24
Finished Jul 26 05:13:49 PM PDT 24
Peak memory 207020 kb
Host smart-b259bd5a-bf46-48b5-9872-592592f31281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36356
73762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.3635673762
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.3211362717
Short name T109
Test name
Test status
Simulation time 195988302 ps
CPU time 0.94 seconds
Started Jul 26 05:13:50 PM PDT 24
Finished Jul 26 05:13:51 PM PDT 24
Peak memory 207068 kb
Host smart-2a5633f2-8544-49b9-b54a-144b51bb6e17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32113
62717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.3211362717
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.687499289
Short name T1790
Test name
Test status
Simulation time 548416274 ps
CPU time 2.01 seconds
Started Jul 26 05:13:53 PM PDT 24
Finished Jul 26 05:13:55 PM PDT 24
Peak memory 207128 kb
Host smart-79b1e60a-20d0-496b-8d32-2f3af8b871a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68749
9289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.687499289
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.3051425691
Short name T890
Test name
Test status
Simulation time 642893780 ps
CPU time 1.72 seconds
Started Jul 26 05:13:54 PM PDT 24
Finished Jul 26 05:13:56 PM PDT 24
Peak memory 207052 kb
Host smart-f7ba3c81-0e81-4ec3-9024-87d79dac5135
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3051425691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.3051425691
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.1884441233
Short name T300
Test name
Test status
Simulation time 13862643564 ps
CPU time 32.52 seconds
Started Jul 26 05:13:52 PM PDT 24
Finished Jul 26 05:14:25 PM PDT 24
Peak memory 207340 kb
Host smart-0691985a-9288-4dc6-b797-22b1d98756aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18844
41233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.1884441233
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_device_timeout.2750548429
Short name T2529
Test name
Test status
Simulation time 866269975 ps
CPU time 18.24 seconds
Started Jul 26 05:13:53 PM PDT 24
Finished Jul 26 05:14:11 PM PDT 24
Peak memory 207340 kb
Host smart-9740fa4c-3b85-4165-98a0-c8e31d350ad5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750548429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_timeout.2750548429
Directory /workspace/38.usbdev_device_timeout/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.3773513544
Short name T2090
Test name
Test status
Simulation time 321736915 ps
CPU time 1.24 seconds
Started Jul 26 05:13:52 PM PDT 24
Finished Jul 26 05:13:53 PM PDT 24
Peak memory 206508 kb
Host smart-ef21fe4a-8f0c-48f1-9adb-d5b36cfbd109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37735
13544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.3773513544
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.2032798989
Short name T2162
Test name
Test status
Simulation time 159660751 ps
CPU time 0.87 seconds
Started Jul 26 05:13:51 PM PDT 24
Finished Jul 26 05:13:52 PM PDT 24
Peak memory 206904 kb
Host smart-4f98e36f-3100-4bbf-95f0-bec7e884a6be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20327
98989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.2032798989
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.2940303119
Short name T1887
Test name
Test status
Simulation time 61755685 ps
CPU time 0.77 seconds
Started Jul 26 05:13:49 PM PDT 24
Finished Jul 26 05:13:50 PM PDT 24
Peak memory 206964 kb
Host smart-97a8b0c4-6ad1-472f-8ce6-6691f4443c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29403
03119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.2940303119
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.1291825346
Short name T1966
Test name
Test status
Simulation time 878594493 ps
CPU time 2.34 seconds
Started Jul 26 05:13:50 PM PDT 24
Finished Jul 26 05:13:52 PM PDT 24
Peak memory 207240 kb
Host smart-607b3831-a0e1-4a59-874a-5f22d46a91d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12918
25346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.1291825346
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.2946772234
Short name T2055
Test name
Test status
Simulation time 353916735 ps
CPU time 3.04 seconds
Started Jul 26 05:13:53 PM PDT 24
Finished Jul 26 05:13:57 PM PDT 24
Peak memory 207280 kb
Host smart-91e0882c-6ec2-4369-a4bf-9cdbb2dfda53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29467
72234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.2946772234
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.808024796
Short name T2285
Test name
Test status
Simulation time 188474447 ps
CPU time 0.93 seconds
Started Jul 26 05:13:52 PM PDT 24
Finished Jul 26 05:13:53 PM PDT 24
Peak memory 207100 kb
Host smart-982220a4-51e8-494e-bac7-098c1ee3711e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=808024796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.808024796
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.3960775143
Short name T1323
Test name
Test status
Simulation time 135144355 ps
CPU time 0.83 seconds
Started Jul 26 05:13:47 PM PDT 24
Finished Jul 26 05:13:48 PM PDT 24
Peak memory 207092 kb
Host smart-e7f78fc2-ce00-4baa-ac27-729ee2e2b9a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39607
75143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.3960775143
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.528491711
Short name T1108
Test name
Test status
Simulation time 157393536 ps
CPU time 0.95 seconds
Started Jul 26 05:13:49 PM PDT 24
Finished Jul 26 05:13:50 PM PDT 24
Peak memory 207080 kb
Host smart-166875fc-8e5a-4c51-93fc-6b2eacb729a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52849
1711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.528491711
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.491363990
Short name T1184
Test name
Test status
Simulation time 5628502085 ps
CPU time 45.64 seconds
Started Jul 26 05:13:52 PM PDT 24
Finished Jul 26 05:14:38 PM PDT 24
Peak memory 215564 kb
Host smart-4acf12a5-84b5-4856-b9bb-3fd7d3856142
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=491363990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.491363990
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_iso_retraction.492928463
Short name T399
Test name
Test status
Simulation time 7619062066 ps
CPU time 87.91 seconds
Started Jul 26 05:13:49 PM PDT 24
Finished Jul 26 05:15:17 PM PDT 24
Peak memory 207200 kb
Host smart-4d0b56eb-b093-4501-a192-46f09e7363c8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=492928463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_iso_retraction.492928463
Directory /workspace/38.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.3221124585
Short name T2379
Test name
Test status
Simulation time 185395309 ps
CPU time 0.93 seconds
Started Jul 26 05:13:51 PM PDT 24
Finished Jul 26 05:13:52 PM PDT 24
Peak memory 207132 kb
Host smart-327c044d-3245-4656-b4d8-b918ec7879ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32211
24585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.3221124585
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.1184062755
Short name T2351
Test name
Test status
Simulation time 23300426085 ps
CPU time 27.6 seconds
Started Jul 26 05:13:51 PM PDT 24
Finished Jul 26 05:14:19 PM PDT 24
Peak memory 207284 kb
Host smart-72326dd0-7d8a-4930-bdf8-3742a6a2ab7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11840
62755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.1184062755
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.1124817843
Short name T2179
Test name
Test status
Simulation time 3332831666 ps
CPU time 4.81 seconds
Started Jul 26 05:13:49 PM PDT 24
Finished Jul 26 05:13:54 PM PDT 24
Peak memory 207228 kb
Host smart-dd69f3a1-06bb-493d-b28f-46f9654d1027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11248
17843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.1124817843
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.3877412174
Short name T570
Test name
Test status
Simulation time 6482905377 ps
CPU time 189.49 seconds
Started Jul 26 05:13:54 PM PDT 24
Finished Jul 26 05:17:03 PM PDT 24
Peak memory 215544 kb
Host smart-709a4125-9a24-49df-a2f8-bb64fa8538cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38774
12174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.3877412174
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.864317874
Short name T357
Test name
Test status
Simulation time 4919719176 ps
CPU time 150.02 seconds
Started Jul 26 05:13:53 PM PDT 24
Finished Jul 26 05:16:23 PM PDT 24
Peak memory 215596 kb
Host smart-2ce2149a-e140-4117-8b85-893e6db0c8c6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=864317874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.864317874
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.2170395077
Short name T455
Test name
Test status
Simulation time 296626138 ps
CPU time 1.05 seconds
Started Jul 26 05:13:54 PM PDT 24
Finished Jul 26 05:13:56 PM PDT 24
Peak memory 207056 kb
Host smart-4924312b-d8f2-4a96-9007-97eeb2e95bfc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2170395077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.2170395077
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.3731961968
Short name T2228
Test name
Test status
Simulation time 203267635 ps
CPU time 0.98 seconds
Started Jul 26 05:13:54 PM PDT 24
Finished Jul 26 05:13:55 PM PDT 24
Peak memory 207072 kb
Host smart-ea9da256-1a8c-4cc9-8d81-ac21b57853ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37319
61968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.3731961968
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.1059699234
Short name T1294
Test name
Test status
Simulation time 5212229212 ps
CPU time 152.05 seconds
Started Jul 26 05:13:53 PM PDT 24
Finished Jul 26 05:16:25 PM PDT 24
Peak memory 215584 kb
Host smart-87f6b579-80c8-4ead-a5f5-900578f0449f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10596
99234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.1059699234
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.731067130
Short name T709
Test name
Test status
Simulation time 6530469361 ps
CPU time 70.49 seconds
Started Jul 26 05:13:48 PM PDT 24
Finished Jul 26 05:14:59 PM PDT 24
Peak memory 207372 kb
Host smart-229366d2-ffce-445d-9506-9c486a1a5255
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=731067130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.731067130
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.2762850062
Short name T2685
Test name
Test status
Simulation time 224812246 ps
CPU time 0.88 seconds
Started Jul 26 05:13:49 PM PDT 24
Finished Jul 26 05:13:50 PM PDT 24
Peak memory 207000 kb
Host smart-fc3ee987-6a29-4f29-9d1d-1a2d46eb128c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2762850062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.2762850062
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.3429199856
Short name T1265
Test name
Test status
Simulation time 204965939 ps
CPU time 0.89 seconds
Started Jul 26 05:13:50 PM PDT 24
Finished Jul 26 05:13:51 PM PDT 24
Peak memory 207156 kb
Host smart-30c6042c-f76e-4b6b-9d14-ca3a91121025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34291
99856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.3429199856
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.4262666458
Short name T127
Test name
Test status
Simulation time 234187149 ps
CPU time 0.97 seconds
Started Jul 26 05:13:51 PM PDT 24
Finished Jul 26 05:13:53 PM PDT 24
Peak memory 207024 kb
Host smart-1ee181c1-db97-4bd0-a1c2-be62a14da56e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42626
66458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.4262666458
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.2706039059
Short name T408
Test name
Test status
Simulation time 163958935 ps
CPU time 0.92 seconds
Started Jul 26 05:13:53 PM PDT 24
Finished Jul 26 05:13:54 PM PDT 24
Peak memory 207136 kb
Host smart-bb6df3ad-9a44-44c4-b1cd-db7e88fb13df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27060
39059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.2706039059
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.109491212
Short name T2370
Test name
Test status
Simulation time 224606943 ps
CPU time 0.89 seconds
Started Jul 26 05:13:48 PM PDT 24
Finished Jul 26 05:13:49 PM PDT 24
Peak memory 207156 kb
Host smart-2a90869a-89d2-4d4a-8e2e-79e35d58a028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10949
1212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.109491212
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.1510213437
Short name T343
Test name
Test status
Simulation time 194177464 ps
CPU time 0.87 seconds
Started Jul 26 05:13:53 PM PDT 24
Finished Jul 26 05:13:54 PM PDT 24
Peak memory 207048 kb
Host smart-0fbd56ec-19da-4c6b-b822-03d7389112a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15102
13437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.1510213437
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.1622368173
Short name T1895
Test name
Test status
Simulation time 154947588 ps
CPU time 0.88 seconds
Started Jul 26 05:13:51 PM PDT 24
Finished Jul 26 05:13:52 PM PDT 24
Peak memory 207132 kb
Host smart-2d164321-5a66-4a8c-9b01-893fa3219d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16223
68173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.1622368173
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.3591344194
Short name T641
Test name
Test status
Simulation time 217885257 ps
CPU time 1.02 seconds
Started Jul 26 05:13:53 PM PDT 24
Finished Jul 26 05:13:54 PM PDT 24
Peak memory 207076 kb
Host smart-3302e1c9-b580-433f-87cd-c42941fc33b2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3591344194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.3591344194
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.3344709972
Short name T2788
Test name
Test status
Simulation time 144375331 ps
CPU time 0.9 seconds
Started Jul 26 05:13:50 PM PDT 24
Finished Jul 26 05:13:51 PM PDT 24
Peak memory 207180 kb
Host smart-e8781a94-8e0c-41bd-a55c-2b4c79413b07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33447
09972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.3344709972
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.2908425907
Short name T2853
Test name
Test status
Simulation time 67384076 ps
CPU time 0.74 seconds
Started Jul 26 05:13:51 PM PDT 24
Finished Jul 26 05:13:52 PM PDT 24
Peak memory 207068 kb
Host smart-83d9ef2f-ea7a-42aa-830c-4ba2444d55b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29084
25907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.2908425907
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.456046671
Short name T807
Test name
Test status
Simulation time 14116739127 ps
CPU time 34.45 seconds
Started Jul 26 05:14:04 PM PDT 24
Finished Jul 26 05:14:39 PM PDT 24
Peak memory 215692 kb
Host smart-add18c25-ca1a-49ca-88b7-6e1123221954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45604
6671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.456046671
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.892612472
Short name T2129
Test name
Test status
Simulation time 213810397 ps
CPU time 0.91 seconds
Started Jul 26 05:13:59 PM PDT 24
Finished Jul 26 05:14:00 PM PDT 24
Peak memory 207132 kb
Host smart-d4e6452b-a1e6-42fa-9cf7-d9749d5656b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89261
2472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.892612472
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.824667907
Short name T2652
Test name
Test status
Simulation time 251147909 ps
CPU time 0.98 seconds
Started Jul 26 05:14:00 PM PDT 24
Finished Jul 26 05:14:01 PM PDT 24
Peak memory 207048 kb
Host smart-c4b2093c-f77c-4b37-a81d-12274c057e4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82466
7907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.824667907
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.986149139
Short name T394
Test name
Test status
Simulation time 295035502 ps
CPU time 1.09 seconds
Started Jul 26 05:14:03 PM PDT 24
Finished Jul 26 05:14:04 PM PDT 24
Peak memory 207132 kb
Host smart-d2353c9c-dfaf-4501-bee6-863f70b546ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98614
9139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.986149139
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.12495847
Short name T946
Test name
Test status
Simulation time 167403382 ps
CPU time 0.87 seconds
Started Jul 26 05:14:08 PM PDT 24
Finished Jul 26 05:14:09 PM PDT 24
Peak memory 207156 kb
Host smart-c402eb46-8de7-4949-99d9-65975831fdcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12495
847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.12495847
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.3125611853
Short name T2046
Test name
Test status
Simulation time 191912884 ps
CPU time 0.92 seconds
Started Jul 26 05:14:03 PM PDT 24
Finished Jul 26 05:14:04 PM PDT 24
Peak memory 207120 kb
Host smart-70a64bc3-7887-443b-ae1c-2190ce747a15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31256
11853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.3125611853
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.1232145317
Short name T672
Test name
Test status
Simulation time 159885201 ps
CPU time 0.89 seconds
Started Jul 26 05:14:06 PM PDT 24
Finished Jul 26 05:14:07 PM PDT 24
Peak memory 207088 kb
Host smart-e188ec98-8751-4ecf-965e-7229aaf77714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12321
45317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.1232145317
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.821263741
Short name T2067
Test name
Test status
Simulation time 151179456 ps
CPU time 0.88 seconds
Started Jul 26 05:14:00 PM PDT 24
Finished Jul 26 05:14:01 PM PDT 24
Peak memory 207080 kb
Host smart-2f036f34-b877-4bf9-94ef-ba07ba63b992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82126
3741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.821263741
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.482589604
Short name T2811
Test name
Test status
Simulation time 181028702 ps
CPU time 1 seconds
Started Jul 26 05:14:03 PM PDT 24
Finished Jul 26 05:14:04 PM PDT 24
Peak memory 207120 kb
Host smart-ceb8fa46-a17a-4823-9f6b-14178f3619e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48258
9604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.482589604
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.3329990454
Short name T752
Test name
Test status
Simulation time 4832494095 ps
CPU time 48.73 seconds
Started Jul 26 05:14:11 PM PDT 24
Finished Jul 26 05:15:00 PM PDT 24
Peak memory 217192 kb
Host smart-e1f4ac42-c875-46d3-a27f-341fce4a5b5a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3329990454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.3329990454
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.1268556619
Short name T2771
Test name
Test status
Simulation time 230649236 ps
CPU time 0.97 seconds
Started Jul 26 05:14:06 PM PDT 24
Finished Jul 26 05:14:07 PM PDT 24
Peak memory 207084 kb
Host smart-05b6a1c8-8985-44b8-954b-d682a9c2c530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12685
56619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.1268556619
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.1214185364
Short name T2004
Test name
Test status
Simulation time 167310846 ps
CPU time 0.88 seconds
Started Jul 26 05:14:00 PM PDT 24
Finished Jul 26 05:14:01 PM PDT 24
Peak memory 207044 kb
Host smart-fc3cbdd3-33ed-4176-a5f8-25c1026ca6ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12141
85364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.1214185364
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.3877442247
Short name T972
Test name
Test status
Simulation time 564204018 ps
CPU time 1.49 seconds
Started Jul 26 05:14:00 PM PDT 24
Finished Jul 26 05:14:01 PM PDT 24
Peak memory 207012 kb
Host smart-1920eb94-5f45-48b7-aa09-27356585445f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38774
42247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.3877442247
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.4085497904
Short name T100
Test name
Test status
Simulation time 5648856447 ps
CPU time 168.96 seconds
Started Jul 26 05:14:08 PM PDT 24
Finished Jul 26 05:16:57 PM PDT 24
Peak memory 215608 kb
Host smart-af685d00-f39c-4492-82f5-2f60bddf9876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40854
97904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.4085497904
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_timeout_missing_host_handshake.4237773392
Short name T996
Test name
Test status
Simulation time 756781974 ps
CPU time 5 seconds
Started Jul 26 05:13:52 PM PDT 24
Finished Jul 26 05:13:57 PM PDT 24
Peak memory 206592 kb
Host smart-e86ba45d-fb1e-4d4d-973f-63894b42397c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237773392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_timeout_missing_hos
t_handshake.4237773392
Directory /workspace/38.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.2610936461
Short name T1207
Test name
Test status
Simulation time 36936891 ps
CPU time 0.75 seconds
Started Jul 26 05:14:04 PM PDT 24
Finished Jul 26 05:14:05 PM PDT 24
Peak memory 207136 kb
Host smart-43d15604-db5e-4a9b-8224-692d93190896
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2610936461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.2610936461
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.3569003519
Short name T2003
Test name
Test status
Simulation time 4114172372 ps
CPU time 6.42 seconds
Started Jul 26 05:14:01 PM PDT 24
Finished Jul 26 05:14:07 PM PDT 24
Peak memory 207272 kb
Host smart-e5730581-9eea-4b39-8743-552091a478d3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569003519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_a
on_wake_disconnect.3569003519
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.4200318881
Short name T2768
Test name
Test status
Simulation time 13325073496 ps
CPU time 16.4 seconds
Started Jul 26 05:14:05 PM PDT 24
Finished Jul 26 05:14:22 PM PDT 24
Peak memory 207388 kb
Host smart-13cf9411-4fae-4bea-856e-08c88e3799ae
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200318881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.4200318881
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.2628189523
Short name T2587
Test name
Test status
Simulation time 23293519759 ps
CPU time 32.45 seconds
Started Jul 26 05:14:01 PM PDT 24
Finished Jul 26 05:14:33 PM PDT 24
Peak memory 207260 kb
Host smart-15200500-19f0-41ca-8a89-21a95c665ce4
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628189523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_a
on_wake_resume.2628189523
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.4231062940
Short name T2712
Test name
Test status
Simulation time 180499836 ps
CPU time 1.05 seconds
Started Jul 26 05:14:03 PM PDT 24
Finished Jul 26 05:14:04 PM PDT 24
Peak memory 207128 kb
Host smart-bfd0bf8e-51f9-4779-bcc7-260cab692407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42310
62940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.4231062940
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.2818926389
Short name T393
Test name
Test status
Simulation time 164776444 ps
CPU time 0.87 seconds
Started Jul 26 05:14:01 PM PDT 24
Finished Jul 26 05:14:03 PM PDT 24
Peak memory 207064 kb
Host smart-f4d78712-3874-45e9-981b-645bfc4779ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28189
26389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.2818926389
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.754344413
Short name T2787
Test name
Test status
Simulation time 239692577 ps
CPU time 1.11 seconds
Started Jul 26 05:14:05 PM PDT 24
Finished Jul 26 05:14:07 PM PDT 24
Peak memory 207036 kb
Host smart-81879997-ee54-4612-aa11-735a53da859c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75434
4413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.754344413
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.28356862
Short name T1342
Test name
Test status
Simulation time 549762248 ps
CPU time 1.63 seconds
Started Jul 26 05:14:02 PM PDT 24
Finished Jul 26 05:14:03 PM PDT 24
Peak memory 207092 kb
Host smart-f3aa939c-c708-4e11-9a12-3c00775290d9
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=28356862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.28356862
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.3376211746
Short name T2857
Test name
Test status
Simulation time 21154318746 ps
CPU time 49.47 seconds
Started Jul 26 05:14:03 PM PDT 24
Finished Jul 26 05:14:53 PM PDT 24
Peak memory 207328 kb
Host smart-bae4e859-061f-4f70-b972-ab3fd35b1671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33762
11746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.3376211746
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_device_timeout.3291427759
Short name T2196
Test name
Test status
Simulation time 3431263616 ps
CPU time 30.56 seconds
Started Jul 26 05:14:07 PM PDT 24
Finished Jul 26 05:14:37 PM PDT 24
Peak memory 207416 kb
Host smart-7388954c-7edc-4e2e-a560-6528474292ae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291427759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_timeout.3291427759
Directory /workspace/39.usbdev_device_timeout/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.2606170827
Short name T1500
Test name
Test status
Simulation time 504268287 ps
CPU time 1.72 seconds
Started Jul 26 05:14:00 PM PDT 24
Finished Jul 26 05:14:02 PM PDT 24
Peak memory 207052 kb
Host smart-d5326c59-4c8c-424d-968a-4c6d2dce0867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26061
70827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.2606170827
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.1011648593
Short name T1994
Test name
Test status
Simulation time 148263414 ps
CPU time 0.86 seconds
Started Jul 26 05:14:04 PM PDT 24
Finished Jul 26 05:14:05 PM PDT 24
Peak memory 207048 kb
Host smart-a049161f-b0b9-4acc-8259-1aa7d30f280b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10116
48593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.1011648593
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.2657157932
Short name T787
Test name
Test status
Simulation time 67560938 ps
CPU time 0.73 seconds
Started Jul 26 05:14:15 PM PDT 24
Finished Jul 26 05:14:15 PM PDT 24
Peak memory 206996 kb
Host smart-2497a6a5-c67f-4e7d-952b-ea350fb08eaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26571
57932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.2657157932
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.81444355
Short name T756
Test name
Test status
Simulation time 921194516 ps
CPU time 2.8 seconds
Started Jul 26 05:14:11 PM PDT 24
Finished Jul 26 05:14:14 PM PDT 24
Peak memory 207284 kb
Host smart-c564f17a-a07d-4ce1-a166-de59c35b7ba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81444
355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.81444355
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.1723092070
Short name T1129
Test name
Test status
Simulation time 195817841 ps
CPU time 2.71 seconds
Started Jul 26 05:14:02 PM PDT 24
Finished Jul 26 05:14:05 PM PDT 24
Peak memory 207220 kb
Host smart-d9084f5c-0753-4a9e-88c8-50062e2babc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17230
92070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.1723092070
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.668802211
Short name T1897
Test name
Test status
Simulation time 261769255 ps
CPU time 1.25 seconds
Started Jul 26 05:14:01 PM PDT 24
Finished Jul 26 05:14:02 PM PDT 24
Peak memory 215520 kb
Host smart-e99125e2-90a2-4218-ad7c-f4e40721972b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=668802211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.668802211
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.2570808592
Short name T1154
Test name
Test status
Simulation time 139944987 ps
CPU time 0.87 seconds
Started Jul 26 05:14:01 PM PDT 24
Finished Jul 26 05:14:02 PM PDT 24
Peak memory 206988 kb
Host smart-cd408d54-14ae-4c4b-90fe-665c026931a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25708
08592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.2570808592
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.2439138911
Short name T2572
Test name
Test status
Simulation time 203989595 ps
CPU time 1.04 seconds
Started Jul 26 05:14:03 PM PDT 24
Finished Jul 26 05:14:04 PM PDT 24
Peak memory 207020 kb
Host smart-ea0a5ff6-d86c-4b7c-9a2a-c43899920387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24391
38911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.2439138911
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_invalid_sync.4057031325
Short name T1710
Test name
Test status
Simulation time 5762227061 ps
CPU time 43.11 seconds
Started Jul 26 05:14:02 PM PDT 24
Finished Jul 26 05:14:46 PM PDT 24
Peak memory 215488 kb
Host smart-4bc0c114-a0af-4e23-a7f7-ecd0db64a811
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4057031325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.4057031325
Directory /workspace/39.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/39.usbdev_iso_retraction.4145652825
Short name T2072
Test name
Test status
Simulation time 4547125718 ps
CPU time 33.62 seconds
Started Jul 26 05:14:06 PM PDT 24
Finished Jul 26 05:14:39 PM PDT 24
Peak memory 207364 kb
Host smart-d20463b6-d37f-4923-ac86-f09e978c0bde
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4145652825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_iso_retraction.4145652825
Directory /workspace/39.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.376162013
Short name T2815
Test name
Test status
Simulation time 216921628 ps
CPU time 0.92 seconds
Started Jul 26 05:13:59 PM PDT 24
Finished Jul 26 05:14:00 PM PDT 24
Peak memory 206976 kb
Host smart-8e046850-6e39-4a3b-a9bb-cf0bf3dc196c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37616
2013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.376162013
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.450949534
Short name T552
Test name
Test status
Simulation time 23289064860 ps
CPU time 28.72 seconds
Started Jul 26 05:14:03 PM PDT 24
Finished Jul 26 05:14:31 PM PDT 24
Peak memory 207376 kb
Host smart-f46026bd-a75a-475f-88a2-2cf5db480463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45094
9534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.450949534
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.4154366079
Short name T1251
Test name
Test status
Simulation time 3270312243 ps
CPU time 5.98 seconds
Started Jul 26 05:14:13 PM PDT 24
Finished Jul 26 05:14:19 PM PDT 24
Peak memory 207320 kb
Host smart-f02e7552-4486-4e5e-b86e-8d9a55266d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41543
66079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.4154366079
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.2676433620
Short name T2826
Test name
Test status
Simulation time 8997336320 ps
CPU time 63.79 seconds
Started Jul 26 05:14:05 PM PDT 24
Finished Jul 26 05:15:09 PM PDT 24
Peak memory 223696 kb
Host smart-4e6e9226-cbd5-4f05-94a7-c39d7bad6625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26764
33620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.2676433620
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.3180219233
Short name T1475
Test name
Test status
Simulation time 4949893424 ps
CPU time 36.78 seconds
Started Jul 26 05:14:05 PM PDT 24
Finished Jul 26 05:14:42 PM PDT 24
Peak memory 207356 kb
Host smart-80f21be0-52ed-438c-b774-a7e5b7b9ff23
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3180219233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.3180219233
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.2230310138
Short name T1303
Test name
Test status
Simulation time 249722540 ps
CPU time 1.04 seconds
Started Jul 26 05:14:01 PM PDT 24
Finished Jul 26 05:14:03 PM PDT 24
Peak memory 207052 kb
Host smart-3ffeabcb-57cf-420e-beda-e1a25ab4773e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2230310138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.2230310138
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.2836454562
Short name T414
Test name
Test status
Simulation time 263294716 ps
CPU time 1.02 seconds
Started Jul 26 05:14:01 PM PDT 24
Finished Jul 26 05:14:02 PM PDT 24
Peak memory 207096 kb
Host smart-5bd1c910-d53b-476f-b632-ae034c9d5054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28364
54562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.2836454562
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.1446237276
Short name T2029
Test name
Test status
Simulation time 3324475317 ps
CPU time 98.57 seconds
Started Jul 26 05:14:08 PM PDT 24
Finished Jul 26 05:15:47 PM PDT 24
Peak memory 215424 kb
Host smart-6761dd23-ce1c-4cca-848d-edf30bf2929d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14462
37276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.1446237276
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.3938639020
Short name T1690
Test name
Test status
Simulation time 5591829440 ps
CPU time 168.55 seconds
Started Jul 26 05:14:04 PM PDT 24
Finished Jul 26 05:16:53 PM PDT 24
Peak memory 215500 kb
Host smart-5253edb8-754b-41d9-91b9-0d499378340e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3938639020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.3938639020
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.3199464374
Short name T649
Test name
Test status
Simulation time 156993509 ps
CPU time 0.86 seconds
Started Jul 26 05:14:06 PM PDT 24
Finished Jul 26 05:14:07 PM PDT 24
Peak memory 207204 kb
Host smart-d18ae033-7d10-488b-888b-1adde3b2ee58
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3199464374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.3199464374
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.3966346812
Short name T1397
Test name
Test status
Simulation time 149010321 ps
CPU time 0.92 seconds
Started Jul 26 05:14:01 PM PDT 24
Finished Jul 26 05:14:03 PM PDT 24
Peak memory 207128 kb
Host smart-67843891-bf00-452a-8abd-1a99d4d3aea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39663
46812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.3966346812
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.1519589618
Short name T141
Test name
Test status
Simulation time 189005696 ps
CPU time 0.88 seconds
Started Jul 26 05:14:01 PM PDT 24
Finished Jul 26 05:14:02 PM PDT 24
Peak memory 206980 kb
Host smart-3175f2c3-27e8-405a-9f3b-52b694792839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15195
89618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.1519589618
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.3857564204
Short name T2277
Test name
Test status
Simulation time 139804863 ps
CPU time 0.81 seconds
Started Jul 26 05:14:01 PM PDT 24
Finished Jul 26 05:14:02 PM PDT 24
Peak memory 207020 kb
Host smart-96230a07-392e-4427-924b-644bedca9299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38575
64204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.3857564204
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.2253114265
Short name T731
Test name
Test status
Simulation time 152052306 ps
CPU time 0.83 seconds
Started Jul 26 05:14:06 PM PDT 24
Finished Jul 26 05:14:07 PM PDT 24
Peak memory 207140 kb
Host smart-fe219608-d62e-41da-9b11-ae0a1d6ff63b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22531
14265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.2253114265
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.556993385
Short name T646
Test name
Test status
Simulation time 178264468 ps
CPU time 0.87 seconds
Started Jul 26 05:14:05 PM PDT 24
Finished Jul 26 05:14:05 PM PDT 24
Peak memory 207036 kb
Host smart-78ee4262-55de-41e7-9e85-75a7dfe91c66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55699
3385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.556993385
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.2893671258
Short name T1584
Test name
Test status
Simulation time 155997801 ps
CPU time 0.84 seconds
Started Jul 26 05:14:08 PM PDT 24
Finished Jul 26 05:14:09 PM PDT 24
Peak memory 206972 kb
Host smart-5e6c2f70-743d-4210-b896-8cff1e033dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28936
71258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.2893671258
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.1465448787
Short name T1043
Test name
Test status
Simulation time 219739410 ps
CPU time 0.96 seconds
Started Jul 26 05:14:00 PM PDT 24
Finished Jul 26 05:14:01 PM PDT 24
Peak memory 207124 kb
Host smart-6ca8c624-18b5-408e-bffa-f981118e547f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1465448787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.1465448787
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.2375379443
Short name T2134
Test name
Test status
Simulation time 146983758 ps
CPU time 0.84 seconds
Started Jul 26 05:14:01 PM PDT 24
Finished Jul 26 05:14:02 PM PDT 24
Peak memory 206984 kb
Host smart-9fd4855f-7fec-43b5-9bc9-353b968f9cf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23753
79443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.2375379443
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.556464301
Short name T1261
Test name
Test status
Simulation time 37989148 ps
CPU time 0.75 seconds
Started Jul 26 05:14:02 PM PDT 24
Finished Jul 26 05:14:03 PM PDT 24
Peak memory 206988 kb
Host smart-0edcea6e-c9f0-4df1-97a5-c9338127987f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55646
4301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.556464301
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.2962159460
Short name T2725
Test name
Test status
Simulation time 8786798578 ps
CPU time 22.09 seconds
Started Jul 26 05:14:05 PM PDT 24
Finished Jul 26 05:14:27 PM PDT 24
Peak memory 215544 kb
Host smart-fcbe9f34-3916-41c7-b9d1-96c7be6a1f4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29621
59460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.2962159460
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.4226304373
Short name T1665
Test name
Test status
Simulation time 144484170 ps
CPU time 0.84 seconds
Started Jul 26 05:14:05 PM PDT 24
Finished Jul 26 05:14:06 PM PDT 24
Peak memory 207052 kb
Host smart-a57cfed7-c775-47aa-8677-643f1006cda1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42263
04373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.4226304373
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.1646607652
Short name T785
Test name
Test status
Simulation time 242656030 ps
CPU time 1.01 seconds
Started Jul 26 05:14:13 PM PDT 24
Finished Jul 26 05:14:14 PM PDT 24
Peak memory 207076 kb
Host smart-ab29d71d-86a6-4855-8000-9a66908a1846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16466
07652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.1646607652
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.2710587685
Short name T899
Test name
Test status
Simulation time 198559968 ps
CPU time 0.96 seconds
Started Jul 26 05:14:05 PM PDT 24
Finished Jul 26 05:14:06 PM PDT 24
Peak memory 207128 kb
Host smart-4f5c299f-069d-40e0-9554-4cbf29a344d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27105
87685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.2710587685
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.3892205395
Short name T1160
Test name
Test status
Simulation time 249897207 ps
CPU time 0.97 seconds
Started Jul 26 05:14:00 PM PDT 24
Finished Jul 26 05:14:01 PM PDT 24
Peak memory 207080 kb
Host smart-1be7c41b-456a-472c-9805-ad165a5fc1c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38922
05395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.3892205395
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.3846919066
Short name T1955
Test name
Test status
Simulation time 198391005 ps
CPU time 0.92 seconds
Started Jul 26 05:14:03 PM PDT 24
Finished Jul 26 05:14:04 PM PDT 24
Peak memory 207264 kb
Host smart-5faa3777-3235-4b25-8cab-5bf94a701e3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38469
19066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.3846919066
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.2849030885
Short name T2707
Test name
Test status
Simulation time 164059552 ps
CPU time 0.88 seconds
Started Jul 26 05:14:02 PM PDT 24
Finished Jul 26 05:14:03 PM PDT 24
Peak memory 207100 kb
Host smart-f0579de5-d3cd-4ae5-b651-5bf5a06363e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28490
30885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.2849030885
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.1952495342
Short name T1593
Test name
Test status
Simulation time 159526110 ps
CPU time 0.85 seconds
Started Jul 26 05:14:03 PM PDT 24
Finished Jul 26 05:14:04 PM PDT 24
Peak memory 207260 kb
Host smart-332f0457-19c7-4595-8d3a-ce599f47482a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19524
95342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.1952495342
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.1542820348
Short name T438
Test name
Test status
Simulation time 209180408 ps
CPU time 1.02 seconds
Started Jul 26 05:14:04 PM PDT 24
Finished Jul 26 05:14:05 PM PDT 24
Peak memory 207120 kb
Host smart-38d3c247-1b6c-4939-9062-37bae75f17e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15428
20348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.1542820348
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.479786466
Short name T2619
Test name
Test status
Simulation time 5307230019 ps
CPU time 42.18 seconds
Started Jul 26 05:14:04 PM PDT 24
Finished Jul 26 05:14:46 PM PDT 24
Peak memory 215560 kb
Host smart-b9a1fe53-2741-4f9d-9973-c8897613f6bb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=479786466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.479786466
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.1954468067
Short name T1393
Test name
Test status
Simulation time 204276116 ps
CPU time 0.98 seconds
Started Jul 26 05:14:02 PM PDT 24
Finished Jul 26 05:14:04 PM PDT 24
Peak memory 207028 kb
Host smart-99a0076f-ee70-4a7b-b4ac-475e459197da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19544
68067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.1954468067
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.1082080165
Short name T2690
Test name
Test status
Simulation time 219383684 ps
CPU time 0.91 seconds
Started Jul 26 05:14:12 PM PDT 24
Finished Jul 26 05:14:13 PM PDT 24
Peak memory 207100 kb
Host smart-5ea05d5d-d725-4c89-bbdb-dbe571a61c6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10820
80165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.1082080165
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.1167043540
Short name T569
Test name
Test status
Simulation time 460984039 ps
CPU time 1.53 seconds
Started Jul 26 05:14:04 PM PDT 24
Finished Jul 26 05:14:05 PM PDT 24
Peak memory 207216 kb
Host smart-af386b7d-4f7d-4c71-91ce-d41d428e34a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11670
43540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.1167043540
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.131446637
Short name T754
Test name
Test status
Simulation time 6169974041 ps
CPU time 188.68 seconds
Started Jul 26 05:14:12 PM PDT 24
Finished Jul 26 05:17:21 PM PDT 24
Peak memory 215596 kb
Host smart-70cadf83-b520-4165-acac-8d2f3cd211c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13144
6637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.131446637
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_timeout_missing_host_handshake.3655800705
Short name T2731
Test name
Test status
Simulation time 3635815944 ps
CPU time 23.84 seconds
Started Jul 26 05:14:02 PM PDT 24
Finished Jul 26 05:14:26 PM PDT 24
Peak memory 207176 kb
Host smart-b96665d5-a9ae-4a5f-bf40-87d5e8f76827
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655800705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_timeout_missing_hos
t_handshake.3655800705
Directory /workspace/39.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.3866210147
Short name T1830
Test name
Test status
Simulation time 38814237 ps
CPU time 0.65 seconds
Started Jul 26 05:07:27 PM PDT 24
Finished Jul 26 05:07:28 PM PDT 24
Peak memory 207064 kb
Host smart-010f6600-e645-439f-9ea1-869200017487
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3866210147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.3866210147
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.624382179
Short name T1508
Test name
Test status
Simulation time 3946595203 ps
CPU time 6.47 seconds
Started Jul 26 05:07:10 PM PDT 24
Finished Jul 26 05:07:16 PM PDT 24
Peak memory 207324 kb
Host smart-4db19393-1170-40fc-81a7-82bf132814d6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624382179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon
_wake_disconnect.624382179
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.2743989178
Short name T2645
Test name
Test status
Simulation time 23409463317 ps
CPU time 31.24 seconds
Started Jul 26 05:07:09 PM PDT 24
Finished Jul 26 05:07:40 PM PDT 24
Peak memory 207408 kb
Host smart-e7c08959-cb03-4b27-a15d-833ea82f2b15
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743989178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ao
n_wake_resume.2743989178
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.2346589357
Short name T423
Test name
Test status
Simulation time 178381226 ps
CPU time 0.88 seconds
Started Jul 26 05:07:09 PM PDT 24
Finished Jul 26 05:07:10 PM PDT 24
Peak memory 207060 kb
Host smart-86a72654-e1c9-4167-8c6e-8ff6a69faaad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23465
89357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.2346589357
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.518432389
Short name T2371
Test name
Test status
Simulation time 166055811 ps
CPU time 0.91 seconds
Started Jul 26 05:07:09 PM PDT 24
Finished Jul 26 05:07:10 PM PDT 24
Peak memory 207032 kb
Host smart-77729c7d-8f96-4307-82d3-00511e2adff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51843
2389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.518432389
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.46530003
Short name T66
Test name
Test status
Simulation time 158264645 ps
CPU time 0.86 seconds
Started Jul 26 05:07:21 PM PDT 24
Finished Jul 26 05:07:22 PM PDT 24
Peak memory 207024 kb
Host smart-9aa8692f-6b20-4987-8012-8769a01ed7d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46530
003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.46530003
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.3963096331
Short name T2438
Test name
Test status
Simulation time 166947660 ps
CPU time 0.88 seconds
Started Jul 26 05:07:23 PM PDT 24
Finished Jul 26 05:07:24 PM PDT 24
Peak memory 206992 kb
Host smart-4ee9bd6c-3899-4577-901f-73d746a2638e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39630
96331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.3963096331
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.1677114242
Short name T498
Test name
Test status
Simulation time 295978352 ps
CPU time 1.19 seconds
Started Jul 26 05:07:23 PM PDT 24
Finished Jul 26 05:07:24 PM PDT 24
Peak memory 207072 kb
Host smart-1b2f24ab-70a4-4a27-9668-b1a2923383ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16771
14242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.1677114242
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.935453180
Short name T728
Test name
Test status
Simulation time 410979337 ps
CPU time 1.26 seconds
Started Jul 26 05:07:20 PM PDT 24
Finished Jul 26 05:07:21 PM PDT 24
Peak memory 207060 kb
Host smart-4eaf22bd-6ad9-428c-8969-a9b80e81eac9
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=935453180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.935453180
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.2278960063
Short name T1444
Test name
Test status
Simulation time 11260432611 ps
CPU time 25.88 seconds
Started Jul 26 05:07:20 PM PDT 24
Finished Jul 26 05:07:46 PM PDT 24
Peak memory 207428 kb
Host smart-7c05a8f4-998a-4dd5-abc1-f5f49ccf8567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22789
60063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.2278960063
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_device_timeout.2714587831
Short name T351
Test name
Test status
Simulation time 628563531 ps
CPU time 5.24 seconds
Started Jul 26 05:07:20 PM PDT 24
Finished Jul 26 05:07:25 PM PDT 24
Peak memory 207296 kb
Host smart-3d07cd68-cc31-4710-878f-9fab1796022e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714587831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_timeout.2714587831
Directory /workspace/4.usbdev_device_timeout/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.4216581218
Short name T584
Test name
Test status
Simulation time 344189033 ps
CPU time 1.29 seconds
Started Jul 26 05:07:20 PM PDT 24
Finished Jul 26 05:07:22 PM PDT 24
Peak memory 207052 kb
Host smart-2dfda83c-3c7b-4e81-aa37-87323a7e609f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42165
81218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.4216581218
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.1814561425
Short name T1050
Test name
Test status
Simulation time 132166453 ps
CPU time 0.82 seconds
Started Jul 26 05:07:19 PM PDT 24
Finished Jul 26 05:07:20 PM PDT 24
Peak memory 207100 kb
Host smart-81fa3096-5262-40d7-8a66-dcdbfc5489c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18145
61425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.1814561425
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.446808325
Short name T2296
Test name
Test status
Simulation time 41536946 ps
CPU time 0.72 seconds
Started Jul 26 05:07:19 PM PDT 24
Finished Jul 26 05:07:20 PM PDT 24
Peak memory 207064 kb
Host smart-085057ec-8b7b-42cc-844c-ac2f026a02b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44680
8325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.446808325
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.2801971079
Short name T986
Test name
Test status
Simulation time 911897219 ps
CPU time 2.58 seconds
Started Jul 26 05:07:27 PM PDT 24
Finished Jul 26 05:07:29 PM PDT 24
Peak memory 207392 kb
Host smart-e94535eb-8da1-4f2e-a0cc-71d4a8c10631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28019
71079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.2801971079
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.1084957905
Short name T877
Test name
Test status
Simulation time 380722614 ps
CPU time 2.7 seconds
Started Jul 26 05:07:20 PM PDT 24
Finished Jul 26 05:07:23 PM PDT 24
Peak memory 207332 kb
Host smart-f71540f9-7d1f-4b44-ad44-036fcabdf7ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10849
57905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.1084957905
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.401611432
Short name T2088
Test name
Test status
Simulation time 118201371910 ps
CPU time 180.35 seconds
Started Jul 26 05:07:21 PM PDT 24
Finished Jul 26 05:10:21 PM PDT 24
Peak memory 207248 kb
Host smart-d332bd44-ca6c-4093-9b4d-dbcf3917bafb
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=401611432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.401611432
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.2044306525
Short name T851
Test name
Test status
Simulation time 119014056924 ps
CPU time 187.94 seconds
Started Jul 26 05:07:21 PM PDT 24
Finished Jul 26 05:10:29 PM PDT 24
Peak memory 207268 kb
Host smart-67a1d75a-3323-4626-ac81-64624e50ab2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044306525 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.2044306525
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.3181143341
Short name T2440
Test name
Test status
Simulation time 120135303125 ps
CPU time 194.5 seconds
Started Jul 26 05:07:20 PM PDT 24
Finished Jul 26 05:10:35 PM PDT 24
Peak memory 207256 kb
Host smart-e85fef80-89ca-4ef0-8065-1b805dbf6115
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3181143341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.3181143341
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.4073024559
Short name T307
Test name
Test status
Simulation time 121150302740 ps
CPU time 199.02 seconds
Started Jul 26 05:07:19 PM PDT 24
Finished Jul 26 05:10:38 PM PDT 24
Peak memory 207328 kb
Host smart-5091f481-e843-4a98-b784-faab79b168f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073024559 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.4073024559
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.1304900064
Short name T2360
Test name
Test status
Simulation time 102135855991 ps
CPU time 166.31 seconds
Started Jul 26 05:07:21 PM PDT 24
Finished Jul 26 05:10:07 PM PDT 24
Peak memory 207364 kb
Host smart-2226802a-e146-4537-9c5c-a80b371fa4dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13049
00064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.1304900064
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.2560831475
Short name T886
Test name
Test status
Simulation time 178512993 ps
CPU time 0.99 seconds
Started Jul 26 05:07:25 PM PDT 24
Finished Jul 26 05:07:26 PM PDT 24
Peak memory 207544 kb
Host smart-78e0c7d4-5c76-494f-84e6-a36f91ee9e50
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2560831475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.2560831475
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.2238649955
Short name T2800
Test name
Test status
Simulation time 143242940 ps
CPU time 0.87 seconds
Started Jul 26 05:07:25 PM PDT 24
Finished Jul 26 05:07:26 PM PDT 24
Peak memory 207292 kb
Host smart-138ccd3f-75aa-4a9f-a529-0f83a9c095b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22386
49955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.2238649955
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.459449250
Short name T823
Test name
Test status
Simulation time 226953778 ps
CPU time 1.01 seconds
Started Jul 26 05:07:20 PM PDT 24
Finished Jul 26 05:07:21 PM PDT 24
Peak memory 207084 kb
Host smart-1d944a31-cafc-41f0-b59c-05730b64903a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45944
9250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.459449250
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_invalid_sync.1101296043
Short name T2405
Test name
Test status
Simulation time 5714095602 ps
CPU time 55.3 seconds
Started Jul 26 05:07:22 PM PDT 24
Finished Jul 26 05:08:17 PM PDT 24
Peak memory 216804 kb
Host smart-ce63b427-fba5-4259-878b-34577f2cb48b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1101296043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.1101296043
Directory /workspace/4.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.3197995942
Short name T790
Test name
Test status
Simulation time 231331023 ps
CPU time 1.09 seconds
Started Jul 26 05:07:19 PM PDT 24
Finished Jul 26 05:07:21 PM PDT 24
Peak memory 207016 kb
Host smart-8543f93b-677e-4cec-acee-a05b488ac485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31979
95942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.3197995942
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.2181758976
Short name T322
Test name
Test status
Simulation time 23314177045 ps
CPU time 30.73 seconds
Started Jul 26 05:07:24 PM PDT 24
Finished Jul 26 05:07:55 PM PDT 24
Peak memory 207356 kb
Host smart-fb206196-db3d-4c55-b870-a31edd07c747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21817
58976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.2181758976
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.3400400131
Short name T542
Test name
Test status
Simulation time 3305872837 ps
CPU time 5.11 seconds
Started Jul 26 05:07:19 PM PDT 24
Finished Jul 26 05:07:24 PM PDT 24
Peak memory 207312 kb
Host smart-e1fb9b0a-9fff-4452-8ef1-3f946d6b2771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34004
00131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.3400400131
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.1102867599
Short name T1902
Test name
Test status
Simulation time 7020503472 ps
CPU time 223.24 seconds
Started Jul 26 05:07:20 PM PDT 24
Finished Jul 26 05:11:04 PM PDT 24
Peak memory 215600 kb
Host smart-552f2713-401e-4d6a-bb4c-7780d3572f1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11028
67599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.1102867599
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.3182056865
Short name T811
Test name
Test status
Simulation time 4168700476 ps
CPU time 46.14 seconds
Started Jul 26 05:07:23 PM PDT 24
Finished Jul 26 05:08:09 PM PDT 24
Peak memory 215464 kb
Host smart-ecccc9de-7be2-4ad2-b7ef-7221440b33b1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3182056865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.3182056865
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.2121524116
Short name T508
Test name
Test status
Simulation time 239622737 ps
CPU time 1.05 seconds
Started Jul 26 05:07:19 PM PDT 24
Finished Jul 26 05:07:20 PM PDT 24
Peak memory 207036 kb
Host smart-5b9d6597-6b78-4976-98b2-548c6d5e640e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2121524116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.2121524116
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.145995288
Short name T2639
Test name
Test status
Simulation time 188439163 ps
CPU time 0.96 seconds
Started Jul 26 05:07:23 PM PDT 24
Finished Jul 26 05:07:24 PM PDT 24
Peak memory 207020 kb
Host smart-4acc4534-9730-4193-a5d5-32575c9517c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14599
5288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.145995288
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.3148230230
Short name T1197
Test name
Test status
Simulation time 3624623368 ps
CPU time 117.23 seconds
Started Jul 26 05:07:19 PM PDT 24
Finished Jul 26 05:09:16 PM PDT 24
Peak memory 215396 kb
Host smart-0f889248-d5a3-421c-bee6-5065f7e09eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31482
30230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.3148230230
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.4193518171
Short name T454
Test name
Test status
Simulation time 4192979356 ps
CPU time 42.11 seconds
Started Jul 26 05:07:20 PM PDT 24
Finished Jul 26 05:08:02 PM PDT 24
Peak memory 207372 kb
Host smart-89d11cb0-a702-48a7-abcf-7dd92f080a69
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4193518171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.4193518171
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.110116009
Short name T1721
Test name
Test status
Simulation time 187628791 ps
CPU time 0.84 seconds
Started Jul 26 05:07:21 PM PDT 24
Finished Jul 26 05:07:22 PM PDT 24
Peak memory 206980 kb
Host smart-629c7676-7f89-42b3-9bea-8e25f0d8d0f8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=110116009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.110116009
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.1908564317
Short name T2836
Test name
Test status
Simulation time 217685864 ps
CPU time 0.93 seconds
Started Jul 26 05:07:18 PM PDT 24
Finished Jul 26 05:07:19 PM PDT 24
Peak memory 207148 kb
Host smart-4c7f443d-9a3a-480d-8717-d11310e3cf51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19085
64317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.1908564317
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.629314152
Short name T140
Test name
Test status
Simulation time 175758573 ps
CPU time 0.94 seconds
Started Jul 26 05:07:20 PM PDT 24
Finished Jul 26 05:07:21 PM PDT 24
Peak memory 207060 kb
Host smart-8b12efa1-c414-401f-a692-f84f06a04f90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62931
4152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.629314152
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.3942154790
Short name T1894
Test name
Test status
Simulation time 167105534 ps
CPU time 0.87 seconds
Started Jul 26 05:07:19 PM PDT 24
Finished Jul 26 05:07:20 PM PDT 24
Peak memory 207124 kb
Host smart-843f4ea5-8ff6-4fe2-a2ee-620a5c0674fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39421
54790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.3942154790
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.397263364
Short name T682
Test name
Test status
Simulation time 225109456 ps
CPU time 0.98 seconds
Started Jul 26 05:07:27 PM PDT 24
Finished Jul 26 05:07:28 PM PDT 24
Peak memory 207140 kb
Host smart-e63d0719-f4de-4c01-9cfd-e8a7e4a41a51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39726
3364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.397263364
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.495163203
Short name T1141
Test name
Test status
Simulation time 145840490 ps
CPU time 0.85 seconds
Started Jul 26 05:07:20 PM PDT 24
Finished Jul 26 05:07:21 PM PDT 24
Peak memory 207136 kb
Host smart-1cb38b0e-7a7a-47d5-a5b7-79db308874da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49516
3203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.495163203
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.1091226931
Short name T1142
Test name
Test status
Simulation time 176171380 ps
CPU time 0.83 seconds
Started Jul 26 05:07:19 PM PDT 24
Finished Jul 26 05:07:20 PM PDT 24
Peak memory 207088 kb
Host smart-55c362cb-16a1-4f6c-ac3d-577bf88a5d67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10912
26931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.1091226931
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.2929167433
Short name T1379
Test name
Test status
Simulation time 200225673 ps
CPU time 0.97 seconds
Started Jul 26 05:07:18 PM PDT 24
Finished Jul 26 05:07:19 PM PDT 24
Peak memory 207156 kb
Host smart-26c2ea56-ffab-47f5-8c7b-7c9f9ee1782e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2929167433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.2929167433
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.2266620653
Short name T196
Test name
Test status
Simulation time 223513631 ps
CPU time 1.06 seconds
Started Jul 26 05:07:25 PM PDT 24
Finished Jul 26 05:07:26 PM PDT 24
Peak memory 207336 kb
Host smart-2d93cb5e-78ef-45cd-be29-51fd9678ae0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22666
20653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.2266620653
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.3351438189
Short name T1732
Test name
Test status
Simulation time 159372655 ps
CPU time 0.84 seconds
Started Jul 26 05:07:19 PM PDT 24
Finished Jul 26 05:07:20 PM PDT 24
Peak memory 207064 kb
Host smart-65247170-49f6-44e5-a99a-0b7252ef3e78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33514
38189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.3351438189
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.1920612829
Short name T725
Test name
Test status
Simulation time 34356363 ps
CPU time 0.67 seconds
Started Jul 26 05:07:22 PM PDT 24
Finished Jul 26 05:07:23 PM PDT 24
Peak memory 206988 kb
Host smart-3f484e0b-1434-4782-b09b-ebe8607277aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19206
12829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.1920612829
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.780003216
Short name T2545
Test name
Test status
Simulation time 9155963226 ps
CPU time 26.06 seconds
Started Jul 26 05:07:21 PM PDT 24
Finished Jul 26 05:07:47 PM PDT 24
Peak memory 215572 kb
Host smart-54ee7409-7786-49e2-95c5-a4f9a699103e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78000
3216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.780003216
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.4006117887
Short name T1655
Test name
Test status
Simulation time 157946340 ps
CPU time 0.91 seconds
Started Jul 26 05:07:19 PM PDT 24
Finished Jul 26 05:07:20 PM PDT 24
Peak memory 207100 kb
Host smart-886f58df-73ff-4689-bd13-1a5d2818e5e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40061
17887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.4006117887
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.3893260011
Short name T1285
Test name
Test status
Simulation time 176131560 ps
CPU time 0.91 seconds
Started Jul 26 05:07:22 PM PDT 24
Finished Jul 26 05:07:23 PM PDT 24
Peak memory 207020 kb
Host smart-b11a5e85-4d77-446b-8462-a09a93ae6732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38932
60011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.3893260011
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.1599206723
Short name T157
Test name
Test status
Simulation time 5497193128 ps
CPU time 146.65 seconds
Started Jul 26 05:07:23 PM PDT 24
Finished Jul 26 05:09:50 PM PDT 24
Peak memory 215500 kb
Host smart-5d708bf5-d828-4da0-9c4a-707716aa1ddf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599206723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.1599206723
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.2676100695
Short name T2206
Test name
Test status
Simulation time 12371789673 ps
CPU time 241.58 seconds
Started Jul 26 05:07:32 PM PDT 24
Finished Jul 26 05:11:34 PM PDT 24
Peak memory 215660 kb
Host smart-0ba01d89-90bf-49ca-89f9-aaf482878bf0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676100695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.2676100695
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.2025811119
Short name T1927
Test name
Test status
Simulation time 288574006 ps
CPU time 1.04 seconds
Started Jul 26 05:07:25 PM PDT 24
Finished Jul 26 05:07:26 PM PDT 24
Peak memory 207324 kb
Host smart-6362020a-ff01-416b-a8b4-85b74c341aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20258
11119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.2025811119
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.3704681751
Short name T2191
Test name
Test status
Simulation time 163924399 ps
CPU time 0.86 seconds
Started Jul 26 05:07:21 PM PDT 24
Finished Jul 26 05:07:22 PM PDT 24
Peak memory 207000 kb
Host smart-a10033d3-7e4d-496a-a8ab-e91bde6791b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37046
81751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.3704681751
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.3478557454
Short name T644
Test name
Test status
Simulation time 152028870 ps
CPU time 0.9 seconds
Started Jul 26 05:07:31 PM PDT 24
Finished Jul 26 05:07:32 PM PDT 24
Peak memory 207116 kb
Host smart-c3931902-6b0b-4551-b50e-541485a01572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34785
57454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.3478557454
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.2958597309
Short name T2064
Test name
Test status
Simulation time 194327398 ps
CPU time 0.96 seconds
Started Jul 26 05:07:27 PM PDT 24
Finished Jul 26 05:07:28 PM PDT 24
Peak memory 207024 kb
Host smart-af628832-6256-420a-bf5d-3e8d7abba4fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29585
97309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.2958597309
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.3016974180
Short name T185
Test name
Test status
Simulation time 290330872 ps
CPU time 1.12 seconds
Started Jul 26 05:07:30 PM PDT 24
Finished Jul 26 05:07:31 PM PDT 24
Peak memory 222880 kb
Host smart-9ba63a73-6b61-4a0e-8da9-ce04310cc6c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3016974180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.3016974180
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.791835383
Short name T57
Test name
Test status
Simulation time 418531574 ps
CPU time 1.48 seconds
Started Jul 26 05:07:30 PM PDT 24
Finished Jul 26 05:07:32 PM PDT 24
Peak memory 207080 kb
Host smart-78138240-c031-4a73-8544-a6059132eeb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79183
5383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.791835383
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.1276704416
Short name T1382
Test name
Test status
Simulation time 221863744 ps
CPU time 1.02 seconds
Started Jul 26 05:07:28 PM PDT 24
Finished Jul 26 05:07:29 PM PDT 24
Peak memory 207124 kb
Host smart-edf99f23-d4ff-4574-989c-2e2305c6efb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12767
04416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.1276704416
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.3948551270
Short name T2133
Test name
Test status
Simulation time 152985960 ps
CPU time 0.83 seconds
Started Jul 26 05:07:31 PM PDT 24
Finished Jul 26 05:07:32 PM PDT 24
Peak memory 207180 kb
Host smart-5eff5952-798a-4e33-a23c-2bf134be0049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39485
51270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.3948551270
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.1045391294
Short name T1238
Test name
Test status
Simulation time 158006121 ps
CPU time 0.87 seconds
Started Jul 26 05:07:31 PM PDT 24
Finished Jul 26 05:07:32 PM PDT 24
Peak memory 207136 kb
Host smart-c15fe3e0-c7ad-4445-a6a7-40e6878a893a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10453
91294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.1045391294
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.2484561612
Short name T1255
Test name
Test status
Simulation time 223531782 ps
CPU time 0.98 seconds
Started Jul 26 05:07:34 PM PDT 24
Finished Jul 26 05:07:35 PM PDT 24
Peak memory 207108 kb
Host smart-1155b020-3ea0-4343-baf6-3b7c1c9d314a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24845
61612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.2484561612
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.2772154804
Short name T634
Test name
Test status
Simulation time 5534920627 ps
CPU time 163.2 seconds
Started Jul 26 05:07:29 PM PDT 24
Finished Jul 26 05:10:13 PM PDT 24
Peak memory 215512 kb
Host smart-b94cf799-d20b-433d-b653-664da7a63992
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2772154804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.2772154804
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.3863888918
Short name T2080
Test name
Test status
Simulation time 177864354 ps
CPU time 0.95 seconds
Started Jul 26 05:07:29 PM PDT 24
Finished Jul 26 05:07:31 PM PDT 24
Peak memory 207092 kb
Host smart-a60b13c8-9c58-4bc8-b638-7c071e558acb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38638
88918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.3863888918
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.2725712455
Short name T1729
Test name
Test status
Simulation time 159031012 ps
CPU time 0.83 seconds
Started Jul 26 05:07:29 PM PDT 24
Finished Jul 26 05:07:30 PM PDT 24
Peak memory 207096 kb
Host smart-bab0223f-816f-4663-be21-413f3f5b1bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27257
12455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.2725712455
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.2502289419
Short name T664
Test name
Test status
Simulation time 888226743 ps
CPU time 2.32 seconds
Started Jul 26 05:07:27 PM PDT 24
Finished Jul 26 05:07:30 PM PDT 24
Peak memory 207304 kb
Host smart-109137d9-618d-4466-987a-568f70befd36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25022
89419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.2502289419
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.2583176730
Short name T1415
Test name
Test status
Simulation time 5502811544 ps
CPU time 56.15 seconds
Started Jul 26 05:07:29 PM PDT 24
Finished Jul 26 05:08:26 PM PDT 24
Peak memory 207300 kb
Host smart-790abcff-16ee-499f-b581-012fd7c06f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25831
76730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.2583176730
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_timeout_missing_host_handshake.331172355
Short name T1360
Test name
Test status
Simulation time 3872682586 ps
CPU time 32.92 seconds
Started Jul 26 05:07:21 PM PDT 24
Finished Jul 26 05:07:54 PM PDT 24
Peak memory 207324 kb
Host smart-96f355df-3bf8-49ea-a3c8-9ae083d21bed
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331172355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_timeout_missing_host_
handshake.331172355
Directory /workspace/4.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.3161314719
Short name T518
Test name
Test status
Simulation time 52015360 ps
CPU time 0.69 seconds
Started Jul 26 05:14:13 PM PDT 24
Finished Jul 26 05:14:13 PM PDT 24
Peak memory 207064 kb
Host smart-d7b448c4-beb0-474d-bac7-ec1f8a99a552
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3161314719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.3161314719
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.1511790667
Short name T2693
Test name
Test status
Simulation time 3581481067 ps
CPU time 6.27 seconds
Started Jul 26 05:14:01 PM PDT 24
Finished Jul 26 05:14:07 PM PDT 24
Peak memory 207364 kb
Host smart-196969c4-af44-4701-9db4-4db2c49f2743
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511790667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_a
on_wake_disconnect.1511790667
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.2990143096
Short name T2650
Test name
Test status
Simulation time 13420297613 ps
CPU time 16.89 seconds
Started Jul 26 05:14:02 PM PDT 24
Finished Jul 26 05:14:19 PM PDT 24
Peak memory 207396 kb
Host smart-41c4300f-f6ee-457d-8eea-acd60ef878d6
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990143096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.2990143096
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.3307140039
Short name T2284
Test name
Test status
Simulation time 23470553123 ps
CPU time 27.99 seconds
Started Jul 26 05:14:04 PM PDT 24
Finished Jul 26 05:14:32 PM PDT 24
Peak memory 207352 kb
Host smart-583a9439-e6b9-4d49-90a6-095fe6864a50
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307140039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_a
on_wake_resume.3307140039
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.4088511469
Short name T1705
Test name
Test status
Simulation time 171353492 ps
CPU time 0.93 seconds
Started Jul 26 05:14:01 PM PDT 24
Finished Jul 26 05:14:03 PM PDT 24
Peak memory 207120 kb
Host smart-9b46c1c7-c5d4-452b-8ee8-d553891ec6ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40885
11469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.4088511469
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.2788291801
Short name T1774
Test name
Test status
Simulation time 225203180 ps
CPU time 0.96 seconds
Started Jul 26 05:14:11 PM PDT 24
Finished Jul 26 05:14:12 PM PDT 24
Peak memory 207028 kb
Host smart-6b0a0080-e628-4b91-9f90-f4ff9c2e4bc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27882
91801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.2788291801
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.2174520615
Short name T2380
Test name
Test status
Simulation time 438447601 ps
CPU time 1.56 seconds
Started Jul 26 05:14:12 PM PDT 24
Finished Jul 26 05:14:14 PM PDT 24
Peak memory 207120 kb
Host smart-cf24a06c-bd92-4af2-a438-df8932f6a731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21745
20615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.2174520615
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.666437483
Short name T1805
Test name
Test status
Simulation time 1324665141 ps
CPU time 3.38 seconds
Started Jul 26 05:14:13 PM PDT 24
Finished Jul 26 05:14:17 PM PDT 24
Peak memory 207192 kb
Host smart-1ac68e8d-0616-4d04-8c49-122769a817ae
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=666437483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.666437483
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.2114533100
Short name T1221
Test name
Test status
Simulation time 14612510265 ps
CPU time 29.53 seconds
Started Jul 26 05:14:13 PM PDT 24
Finished Jul 26 05:14:43 PM PDT 24
Peak memory 207288 kb
Host smart-8560c7c6-94d9-4f40-85ca-52a6bbeef9f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21145
33100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.2114533100
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_device_timeout.881617675
Short name T1618
Test name
Test status
Simulation time 1653130346 ps
CPU time 41.29 seconds
Started Jul 26 05:14:11 PM PDT 24
Finished Jul 26 05:14:52 PM PDT 24
Peak memory 207208 kb
Host smart-08af3934-7c4b-4fc1-ad44-fda16a58571e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881617675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_timeout.881617675
Directory /workspace/40.usbdev_device_timeout/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.3382076057
Short name T2543
Test name
Test status
Simulation time 441641272 ps
CPU time 1.49 seconds
Started Jul 26 05:14:14 PM PDT 24
Finished Jul 26 05:14:16 PM PDT 24
Peak memory 206992 kb
Host smart-a6878892-4542-4ff2-9ec3-a7b69d5e4a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33820
76057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.3382076057
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.180253937
Short name T861
Test name
Test status
Simulation time 204356963 ps
CPU time 0.89 seconds
Started Jul 26 05:14:11 PM PDT 24
Finished Jul 26 05:14:12 PM PDT 24
Peak memory 207052 kb
Host smart-fd9c6887-1a7f-461a-a6cf-ba2f3cdcb1cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18025
3937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.180253937
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.3183893279
Short name T2125
Test name
Test status
Simulation time 124411309 ps
CPU time 0.77 seconds
Started Jul 26 05:14:13 PM PDT 24
Finished Jul 26 05:14:14 PM PDT 24
Peak memory 207000 kb
Host smart-e105c996-1e2c-4e1d-8b09-05ab59ac9200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31838
93279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.3183893279
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.3538943204
Short name T470
Test name
Test status
Simulation time 873056909 ps
CPU time 2.39 seconds
Started Jul 26 05:14:13 PM PDT 24
Finished Jul 26 05:14:15 PM PDT 24
Peak memory 207396 kb
Host smart-9e585fe6-19e8-454c-94e8-5ba72635d826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35389
43204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.3538943204
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.3721509843
Short name T2158
Test name
Test status
Simulation time 231919660 ps
CPU time 2.41 seconds
Started Jul 26 05:14:12 PM PDT 24
Finished Jul 26 05:14:14 PM PDT 24
Peak memory 207348 kb
Host smart-d73a76aa-1e74-4dae-a04a-aee710ea7828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37215
09843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.3721509843
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.1999469836
Short name T2597
Test name
Test status
Simulation time 144401300 ps
CPU time 0.86 seconds
Started Jul 26 05:14:10 PM PDT 24
Finished Jul 26 05:14:11 PM PDT 24
Peak memory 207016 kb
Host smart-9b889918-f178-4e35-8101-6e06ac36e226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19994
69836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.1999469836
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.4131070386
Short name T1211
Test name
Test status
Simulation time 232795098 ps
CPU time 1 seconds
Started Jul 26 05:14:12 PM PDT 24
Finished Jul 26 05:14:13 PM PDT 24
Peak memory 206980 kb
Host smart-6cc56740-e2a4-4f80-bc07-9957e25d1543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41310
70386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.4131070386
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.774151933
Short name T1088
Test name
Test status
Simulation time 8351861852 ps
CPU time 66.1 seconds
Started Jul 26 05:14:11 PM PDT 24
Finished Jul 26 05:15:18 PM PDT 24
Peak memory 207392 kb
Host smart-47ad012d-5622-4b9e-892f-e3457f271f8f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=774151933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.774151933
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.2294964552
Short name T2743
Test name
Test status
Simulation time 237670712 ps
CPU time 0.95 seconds
Started Jul 26 05:14:13 PM PDT 24
Finished Jul 26 05:14:14 PM PDT 24
Peak memory 207120 kb
Host smart-46351702-5d3b-4e5f-877c-ab45467d295b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22949
64552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.2294964552
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.3307244103
Short name T1638
Test name
Test status
Simulation time 23330019553 ps
CPU time 32.2 seconds
Started Jul 26 05:14:15 PM PDT 24
Finished Jul 26 05:14:47 PM PDT 24
Peak memory 207348 kb
Host smart-278da3d7-a86f-4b5a-b72b-fdcc4ba764b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33072
44103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.3307244103
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.2234482633
Short name T1623
Test name
Test status
Simulation time 3338951845 ps
CPU time 4.84 seconds
Started Jul 26 05:14:13 PM PDT 24
Finished Jul 26 05:14:19 PM PDT 24
Peak memory 207276 kb
Host smart-59bb3e7a-3ef7-429f-a659-06d3ef537342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22344
82633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.2234482633
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.2977509120
Short name T500
Test name
Test status
Simulation time 7695500760 ps
CPU time 79.35 seconds
Started Jul 26 05:14:12 PM PDT 24
Finished Jul 26 05:15:31 PM PDT 24
Peak memory 217080 kb
Host smart-208e5c00-56dd-4ddd-9b27-1def9d183458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29775
09120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.2977509120
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.485760641
Short name T1613
Test name
Test status
Simulation time 4594363996 ps
CPU time 36.17 seconds
Started Jul 26 05:14:13 PM PDT 24
Finished Jul 26 05:14:49 PM PDT 24
Peak memory 217004 kb
Host smart-cf05e4ab-8a83-4467-910b-844f7ac8a6aa
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=485760641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.485760641
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.2853471518
Short name T2166
Test name
Test status
Simulation time 250733510 ps
CPU time 1.02 seconds
Started Jul 26 05:14:19 PM PDT 24
Finished Jul 26 05:14:20 PM PDT 24
Peak memory 207120 kb
Host smart-b520ba01-7526-4b28-93cb-c142b7a0ef02
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2853471518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.2853471518
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.2630940548
Short name T2549
Test name
Test status
Simulation time 196747188 ps
CPU time 0.96 seconds
Started Jul 26 05:14:15 PM PDT 24
Finished Jul 26 05:14:16 PM PDT 24
Peak memory 207056 kb
Host smart-7bf1fd26-56ca-42b0-886d-b0226d87d3d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26309
40548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.2630940548
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.908598620
Short name T1174
Test name
Test status
Simulation time 6503875357 ps
CPU time 51.72 seconds
Started Jul 26 05:14:11 PM PDT 24
Finished Jul 26 05:15:03 PM PDT 24
Peak memory 215612 kb
Host smart-ad600262-158b-4055-803f-8107d5a193be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90859
8620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.908598620
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.272707280
Short name T1989
Test name
Test status
Simulation time 3186384093 ps
CPU time 24.34 seconds
Started Jul 26 05:14:12 PM PDT 24
Finished Jul 26 05:14:36 PM PDT 24
Peak memory 216808 kb
Host smart-5e046764-997a-44a7-9a9a-31af94dac3f8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=272707280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.272707280
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.408589126
Short name T737
Test name
Test status
Simulation time 170209547 ps
CPU time 0.9 seconds
Started Jul 26 05:14:19 PM PDT 24
Finished Jul 26 05:14:20 PM PDT 24
Peak memory 207120 kb
Host smart-2f99d2e8-98bb-4ec6-a2e5-893049bcbecd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=408589126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.408589126
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.1887674046
Short name T490
Test name
Test status
Simulation time 153077660 ps
CPU time 0.87 seconds
Started Jul 26 05:14:15 PM PDT 24
Finished Jul 26 05:14:16 PM PDT 24
Peak memory 207044 kb
Host smart-b22d64bd-1975-42ef-b36e-d6690d317800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18876
74046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.1887674046
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.1847869670
Short name T2763
Test name
Test status
Simulation time 210111389 ps
CPU time 0.93 seconds
Started Jul 26 05:14:12 PM PDT 24
Finished Jul 26 05:14:13 PM PDT 24
Peak memory 206952 kb
Host smart-44b06c58-2552-4dbb-87d2-3b2eace971d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18478
69670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.1847869670
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.2514799769
Short name T838
Test name
Test status
Simulation time 176579642 ps
CPU time 0.86 seconds
Started Jul 26 05:14:11 PM PDT 24
Finished Jul 26 05:14:12 PM PDT 24
Peak memory 207012 kb
Host smart-45bcc590-7e77-4178-be6b-29ee95b925ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25147
99769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.2514799769
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.2385399975
Short name T919
Test name
Test status
Simulation time 185199712 ps
CPU time 0.87 seconds
Started Jul 26 05:14:11 PM PDT 24
Finished Jul 26 05:14:12 PM PDT 24
Peak memory 207068 kb
Host smart-c4e04ca9-7ee3-43f8-99fe-b35f1d134699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23853
99975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.2385399975
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.2014235072
Short name T1439
Test name
Test status
Simulation time 188788899 ps
CPU time 0.91 seconds
Started Jul 26 05:14:19 PM PDT 24
Finished Jul 26 05:14:20 PM PDT 24
Peak memory 207100 kb
Host smart-029925e8-e066-477e-8c3c-a3df18899362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20142
35072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.2014235072
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.825939289
Short name T1179
Test name
Test status
Simulation time 164111251 ps
CPU time 0.88 seconds
Started Jul 26 05:14:18 PM PDT 24
Finished Jul 26 05:14:20 PM PDT 24
Peak memory 207096 kb
Host smart-c1d80c3e-fefd-4203-8bdf-320d291c0101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82593
9289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.825939289
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.3400649441
Short name T439
Test name
Test status
Simulation time 256081800 ps
CPU time 1.13 seconds
Started Jul 26 05:14:14 PM PDT 24
Finished Jul 26 05:14:16 PM PDT 24
Peak memory 207004 kb
Host smart-41342616-29a5-4b8d-af38-78ef969d2e48
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3400649441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.3400649441
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.1814836420
Short name T1002
Test name
Test status
Simulation time 140435920 ps
CPU time 0.84 seconds
Started Jul 26 05:14:13 PM PDT 24
Finished Jul 26 05:14:15 PM PDT 24
Peak memory 207064 kb
Host smart-35afb375-bb4b-4ff0-929a-a6c61a938460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18148
36420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.1814836420
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.51906760
Short name T38
Test name
Test status
Simulation time 59449879 ps
CPU time 0.73 seconds
Started Jul 26 05:14:10 PM PDT 24
Finished Jul 26 05:14:11 PM PDT 24
Peak memory 207116 kb
Host smart-3e62cb46-3ea4-49c5-8808-c483319166c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51906
760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.51906760
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.1423952287
Short name T923
Test name
Test status
Simulation time 15117079154 ps
CPU time 40 seconds
Started Jul 26 05:14:10 PM PDT 24
Finished Jul 26 05:14:50 PM PDT 24
Peak memory 215616 kb
Host smart-de61d82b-4bae-401f-9b90-ddf3000d7e32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14239
52287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.1423952287
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.597073026
Short name T1072
Test name
Test status
Simulation time 189671595 ps
CPU time 0.96 seconds
Started Jul 26 05:14:13 PM PDT 24
Finished Jul 26 05:14:14 PM PDT 24
Peak memory 207100 kb
Host smart-b5c94883-e0e4-43f3-b9ba-c191b490fdf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59707
3026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.597073026
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.3542621712
Short name T2589
Test name
Test status
Simulation time 183584815 ps
CPU time 0.88 seconds
Started Jul 26 05:14:18 PM PDT 24
Finished Jul 26 05:14:19 PM PDT 24
Peak memory 206912 kb
Host smart-d3262483-8624-40f0-ae84-ed75f8b35f86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35426
21712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.3542621712
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.3256803845
Short name T1117
Test name
Test status
Simulation time 206013458 ps
CPU time 0.95 seconds
Started Jul 26 05:14:19 PM PDT 24
Finished Jul 26 05:14:20 PM PDT 24
Peak memory 207100 kb
Host smart-606b407c-9ba6-4904-bd72-d9675dccefb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32568
03845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.3256803845
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.3622460793
Short name T363
Test name
Test status
Simulation time 163284601 ps
CPU time 0.86 seconds
Started Jul 26 05:14:12 PM PDT 24
Finished Jul 26 05:14:13 PM PDT 24
Peak memory 207104 kb
Host smart-9f02603a-e915-4a15-8946-32cc46b16c60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36224
60793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.3622460793
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.2007322458
Short name T612
Test name
Test status
Simulation time 146154187 ps
CPU time 0.81 seconds
Started Jul 26 05:14:19 PM PDT 24
Finished Jul 26 05:14:20 PM PDT 24
Peak memory 207060 kb
Host smart-c707e3c3-5268-4e86-9984-60ef5f35fa25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20073
22458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.2007322458
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.2039048939
Short name T1455
Test name
Test status
Simulation time 150783947 ps
CPU time 0.83 seconds
Started Jul 26 05:14:13 PM PDT 24
Finished Jul 26 05:14:14 PM PDT 24
Peak memory 206904 kb
Host smart-28094c62-ed52-4aef-b54b-d2e765a9cd16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20390
48939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.2039048939
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.1334668555
Short name T1626
Test name
Test status
Simulation time 160064982 ps
CPU time 0.9 seconds
Started Jul 26 05:14:19 PM PDT 24
Finished Jul 26 05:14:20 PM PDT 24
Peak memory 207052 kb
Host smart-48f50f27-74f1-4dc8-8992-f4143a712e23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13346
68555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.1334668555
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.660075558
Short name T1243
Test name
Test status
Simulation time 243286820 ps
CPU time 1.06 seconds
Started Jul 26 05:14:14 PM PDT 24
Finished Jul 26 05:14:16 PM PDT 24
Peak memory 207032 kb
Host smart-d79d53ca-3e43-487d-9c8d-5262ef08bc07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66007
5558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.660075558
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.2339344105
Short name T101
Test name
Test status
Simulation time 4066156920 ps
CPU time 43.33 seconds
Started Jul 26 05:14:14 PM PDT 24
Finished Jul 26 05:14:58 PM PDT 24
Peak memory 216748 kb
Host smart-dab98071-cb18-4332-8f83-90f575c76805
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2339344105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.2339344105
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.127131773
Short name T1022
Test name
Test status
Simulation time 180710840 ps
CPU time 0.87 seconds
Started Jul 26 05:14:13 PM PDT 24
Finished Jul 26 05:14:14 PM PDT 24
Peak memory 207084 kb
Host smart-8501016d-30e3-4421-b2b3-ec17185b4490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12713
1773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.127131773
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.4208876703
Short name T2304
Test name
Test status
Simulation time 232217070 ps
CPU time 0.89 seconds
Started Jul 26 05:14:11 PM PDT 24
Finished Jul 26 05:14:12 PM PDT 24
Peak memory 207024 kb
Host smart-daf2ae73-0ff5-4505-8673-2a489b3f249a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42088
76703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.4208876703
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.3541534807
Short name T2687
Test name
Test status
Simulation time 341764920 ps
CPU time 1.15 seconds
Started Jul 26 05:14:18 PM PDT 24
Finished Jul 26 05:14:19 PM PDT 24
Peak memory 206980 kb
Host smart-e275188a-2f9a-4e4e-a535-45e5a013efef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35415
34807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.3541534807
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.1667141117
Short name T2170
Test name
Test status
Simulation time 3799746970 ps
CPU time 28.33 seconds
Started Jul 26 05:14:20 PM PDT 24
Finished Jul 26 05:14:48 PM PDT 24
Peak memory 216824 kb
Host smart-cfda7fd3-75d2-4028-8bee-dcfccf07b4b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16671
41117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.1667141117
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/40.usbdev_timeout_missing_host_handshake.388271784
Short name T2602
Test name
Test status
Simulation time 3806016882 ps
CPU time 26.78 seconds
Started Jul 26 05:14:14 PM PDT 24
Finished Jul 26 05:14:41 PM PDT 24
Peak memory 207260 kb
Host smart-ebc3b78a-ac9e-4a63-aba6-5b6ca62f61f6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388271784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_timeout_missing_host
_handshake.388271784
Directory /workspace/40.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.3798429019
Short name T2646
Test name
Test status
Simulation time 40063399 ps
CPU time 0.66 seconds
Started Jul 26 05:14:23 PM PDT 24
Finished Jul 26 05:14:24 PM PDT 24
Peak memory 207060 kb
Host smart-90e1f2bd-eb67-48e2-ae3e-4e828c71b340
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3798429019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.3798429019
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.633907741
Short name T2234
Test name
Test status
Simulation time 4078440630 ps
CPU time 5.87 seconds
Started Jul 26 05:14:13 PM PDT 24
Finished Jul 26 05:14:20 PM PDT 24
Peak memory 207336 kb
Host smart-81306d0a-7e64-45b1-852d-81b2e5cd9db8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633907741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_ao
n_wake_disconnect.633907741
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.3986263043
Short name T1051
Test name
Test status
Simulation time 13288912046 ps
CPU time 17.22 seconds
Started Jul 26 05:14:13 PM PDT 24
Finished Jul 26 05:14:31 PM PDT 24
Peak memory 207320 kb
Host smart-c9fbd65c-b9fd-445a-89da-be235a2b531a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986263043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.3986263043
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.3471727984
Short name T1406
Test name
Test status
Simulation time 23386291528 ps
CPU time 33.74 seconds
Started Jul 26 05:14:13 PM PDT 24
Finished Jul 26 05:14:47 PM PDT 24
Peak memory 207388 kb
Host smart-b8ddc85c-b4cb-47db-88b5-08ae912dabf8
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471727984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_a
on_wake_resume.3471727984
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.2804164640
Short name T206
Test name
Test status
Simulation time 178417326 ps
CPU time 0.88 seconds
Started Jul 26 05:14:19 PM PDT 24
Finished Jul 26 05:14:20 PM PDT 24
Peak memory 206996 kb
Host smart-cafa29ce-d7e9-491d-adfc-a9849c23f309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28041
64640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.2804164640
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.1510193736
Short name T1728
Test name
Test status
Simulation time 146228764 ps
CPU time 0.83 seconds
Started Jul 26 05:14:18 PM PDT 24
Finished Jul 26 05:14:19 PM PDT 24
Peak memory 206900 kb
Host smart-17560f69-68c4-4a46-a5be-2df44df3ee49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15101
93736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.1510193736
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.1210668229
Short name T1501
Test name
Test status
Simulation time 520025589 ps
CPU time 1.65 seconds
Started Jul 26 05:14:15 PM PDT 24
Finished Jul 26 05:14:16 PM PDT 24
Peak memory 207096 kb
Host smart-04cc294c-d6f9-4839-be17-e10c0d61e8d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12106
68229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.1210668229
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.86122711
Short name T1967
Test name
Test status
Simulation time 1190420895 ps
CPU time 3.06 seconds
Started Jul 26 05:14:15 PM PDT 24
Finished Jul 26 05:14:18 PM PDT 24
Peak memory 207288 kb
Host smart-4c5bc2a6-2dfe-427a-ab69-51a1d71f19d9
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=86122711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.86122711
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.2171893385
Short name T1159
Test name
Test status
Simulation time 17603241410 ps
CPU time 39.54 seconds
Started Jul 26 05:14:12 PM PDT 24
Finished Jul 26 05:14:52 PM PDT 24
Peak memory 207352 kb
Host smart-59e99c53-f539-46fd-ae9a-e40fdefc1897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21718
93385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.2171893385
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_device_timeout.3235873724
Short name T1822
Test name
Test status
Simulation time 2072624160 ps
CPU time 51.87 seconds
Started Jul 26 05:14:13 PM PDT 24
Finished Jul 26 05:15:06 PM PDT 24
Peak memory 207320 kb
Host smart-ff7904d4-b23d-44c5-8904-e706ccd34d04
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235873724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_timeout.3235873724
Directory /workspace/41.usbdev_device_timeout/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.4071850566
Short name T2864
Test name
Test status
Simulation time 382297316 ps
CPU time 1.36 seconds
Started Jul 26 05:14:18 PM PDT 24
Finished Jul 26 05:14:19 PM PDT 24
Peak memory 206980 kb
Host smart-daaa0528-91d6-4545-9723-a3a569789d31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40718
50566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.4071850566
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.577822831
Short name T2070
Test name
Test status
Simulation time 143535865 ps
CPU time 0.84 seconds
Started Jul 26 05:14:13 PM PDT 24
Finished Jul 26 05:14:14 PM PDT 24
Peak memory 206980 kb
Host smart-9a792b8e-3443-4f8d-a004-16b214aa8e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57782
2831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.577822831
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.3131314473
Short name T864
Test name
Test status
Simulation time 129091649 ps
CPU time 0.81 seconds
Started Jul 26 05:14:14 PM PDT 24
Finished Jul 26 05:14:15 PM PDT 24
Peak memory 207020 kb
Host smart-812ca8f8-1396-4e8f-8571-f3826ff2dd01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31313
14473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.3131314473
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.751493303
Short name T775
Test name
Test status
Simulation time 662258204 ps
CPU time 2.12 seconds
Started Jul 26 05:14:16 PM PDT 24
Finished Jul 26 05:14:18 PM PDT 24
Peak memory 207268 kb
Host smart-cad410bc-0c72-41c8-bd09-65f5448af2da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75149
3303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.751493303
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.1767533298
Short name T1748
Test name
Test status
Simulation time 194972849 ps
CPU time 2.5 seconds
Started Jul 26 05:14:15 PM PDT 24
Finished Jul 26 05:14:17 PM PDT 24
Peak memory 207332 kb
Host smart-af279514-04ca-41c5-bc53-63e0e545f38b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17675
33298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.1767533298
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.4232201788
Short name T2779
Test name
Test status
Simulation time 220603605 ps
CPU time 1.08 seconds
Started Jul 26 05:14:13 PM PDT 24
Finished Jul 26 05:14:15 PM PDT 24
Peak memory 207240 kb
Host smart-a3e8c47d-6b3c-47c1-be16-dad35fb38fec
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4232201788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.4232201788
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.2159927176
Short name T902
Test name
Test status
Simulation time 169943800 ps
CPU time 0.9 seconds
Started Jul 26 05:14:13 PM PDT 24
Finished Jul 26 05:14:14 PM PDT 24
Peak memory 206948 kb
Host smart-76a7b5a7-c181-4c9b-8cdb-a364bf75b648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21599
27176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.2159927176
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.3354719745
Short name T2241
Test name
Test status
Simulation time 219600089 ps
CPU time 0.96 seconds
Started Jul 26 05:14:11 PM PDT 24
Finished Jul 26 05:14:12 PM PDT 24
Peak memory 207128 kb
Host smart-664c75c4-30fa-4ef3-99ed-3225f608b357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33547
19745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.3354719745
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_invalid_sync.2660739945
Short name T2144
Test name
Test status
Simulation time 5519870240 ps
CPU time 42.92 seconds
Started Jul 26 05:14:08 PM PDT 24
Finished Jul 26 05:14:51 PM PDT 24
Peak memory 215616 kb
Host smart-012e929e-38dd-4ba8-820a-95b8897d6cb5
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2660739945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.2660739945
Directory /workspace/41.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/41.usbdev_iso_retraction.514569755
Short name T1136
Test name
Test status
Simulation time 3425633586 ps
CPU time 39.25 seconds
Started Jul 26 05:14:14 PM PDT 24
Finished Jul 26 05:14:54 PM PDT 24
Peak memory 207480 kb
Host smart-6564fbc2-2c9f-4386-8500-147d6544c13e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=514569755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.514569755
Directory /workspace/41.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.2759746086
Short name T759
Test name
Test status
Simulation time 151601858 ps
CPU time 0.85 seconds
Started Jul 26 05:14:13 PM PDT 24
Finished Jul 26 05:14:14 PM PDT 24
Peak memory 207124 kb
Host smart-71c6963a-84c2-451a-88ef-3f2c6e5c5719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27597
46086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.2759746086
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.3557957288
Short name T2577
Test name
Test status
Simulation time 23316573694 ps
CPU time 27.16 seconds
Started Jul 26 05:14:14 PM PDT 24
Finished Jul 26 05:14:41 PM PDT 24
Peak memory 207368 kb
Host smart-b875365e-3db8-4a7f-b637-1687483ce408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35579
57288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.3557957288
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.2240028782
Short name T2734
Test name
Test status
Simulation time 3265357154 ps
CPU time 4.77 seconds
Started Jul 26 05:14:27 PM PDT 24
Finished Jul 26 05:14:32 PM PDT 24
Peak memory 207312 kb
Host smart-3c03d07d-0612-4877-97c3-f90536b23bb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22400
28782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.2240028782
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.3644106603
Short name T1198
Test name
Test status
Simulation time 8429376964 ps
CPU time 245.53 seconds
Started Jul 26 05:14:21 PM PDT 24
Finished Jul 26 05:18:27 PM PDT 24
Peak memory 215444 kb
Host smart-c3b27b28-d854-4fae-9587-c2f9e38df8b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36441
06603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.3644106603
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.216932010
Short name T2571
Test name
Test status
Simulation time 3375032062 ps
CPU time 34.65 seconds
Started Jul 26 05:14:21 PM PDT 24
Finished Jul 26 05:14:56 PM PDT 24
Peak memory 215632 kb
Host smart-30547031-168f-4d4c-8722-7776ee5b6aed
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=216932010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.216932010
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.1537955550
Short name T1370
Test name
Test status
Simulation time 264586223 ps
CPU time 1.06 seconds
Started Jul 26 05:14:22 PM PDT 24
Finished Jul 26 05:14:23 PM PDT 24
Peak memory 207104 kb
Host smart-8e171130-caf0-4b95-81ea-455ee0c6c2d5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1537955550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.1537955550
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.1853346365
Short name T2824
Test name
Test status
Simulation time 194043672 ps
CPU time 0.99 seconds
Started Jul 26 05:14:21 PM PDT 24
Finished Jul 26 05:14:23 PM PDT 24
Peak memory 207040 kb
Host smart-3d1ff1da-7cf0-497f-a140-6707628e6c39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18533
46365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.1853346365
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.2203004468
Short name T159
Test name
Test status
Simulation time 6387319231 ps
CPU time 203.69 seconds
Started Jul 26 05:14:21 PM PDT 24
Finished Jul 26 05:17:45 PM PDT 24
Peak memory 215400 kb
Host smart-e5780c26-698d-4d2c-b68f-8e2b2f6666c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22030
04468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.2203004468
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.111234035
Short name T2541
Test name
Test status
Simulation time 3355081854 ps
CPU time 102.77 seconds
Started Jul 26 05:14:20 PM PDT 24
Finished Jul 26 05:16:03 PM PDT 24
Peak memory 215612 kb
Host smart-4a40593b-90c2-40ee-8e0b-0be8110ddc21
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=111234035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.111234035
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.357383782
Short name T2600
Test name
Test status
Simulation time 149157432 ps
CPU time 0.85 seconds
Started Jul 26 05:14:20 PM PDT 24
Finished Jul 26 05:14:21 PM PDT 24
Peak memory 207024 kb
Host smart-dd86e806-ada7-4551-9e54-4b007097be94
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=357383782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.357383782
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.4069119806
Short name T2071
Test name
Test status
Simulation time 170541507 ps
CPU time 0.88 seconds
Started Jul 26 05:14:27 PM PDT 24
Finished Jul 26 05:14:28 PM PDT 24
Peak memory 207060 kb
Host smart-b4de6b97-f28d-4992-9ea5-401847bb1eb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40691
19806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.4069119806
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.1953672231
Short name T702
Test name
Test status
Simulation time 170002960 ps
CPU time 0.88 seconds
Started Jul 26 05:14:22 PM PDT 24
Finished Jul 26 05:14:23 PM PDT 24
Peak memory 207124 kb
Host smart-4e7beaa5-e49d-4dd0-b17a-b860d4ba8275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19536
72231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.1953672231
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.41980808
Short name T650
Test name
Test status
Simulation time 175854345 ps
CPU time 0.9 seconds
Started Jul 26 05:14:28 PM PDT 24
Finished Jul 26 05:14:29 PM PDT 24
Peak memory 207068 kb
Host smart-522f2a1d-6d79-4144-8349-0bb1b0c4c0b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41980
808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.41980808
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.2841992618
Short name T1924
Test name
Test status
Simulation time 194728254 ps
CPU time 0.88 seconds
Started Jul 26 05:14:24 PM PDT 24
Finished Jul 26 05:14:25 PM PDT 24
Peak memory 207136 kb
Host smart-9d1fdf09-6ab6-409d-94fe-ed714d0f144e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28419
92618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.2841992618
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.4278887675
Short name T2694
Test name
Test status
Simulation time 154012563 ps
CPU time 0.83 seconds
Started Jul 26 05:14:23 PM PDT 24
Finished Jul 26 05:14:24 PM PDT 24
Peak memory 207120 kb
Host smart-cfbc1457-7d5d-4a47-a450-b8381c3aef37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42788
87675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.4278887675
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.1027191272
Short name T2674
Test name
Test status
Simulation time 228403752 ps
CPU time 1.04 seconds
Started Jul 26 05:14:25 PM PDT 24
Finished Jul 26 05:14:27 PM PDT 24
Peak memory 207156 kb
Host smart-0031dba8-60e8-4f67-824d-284f367fa8c2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1027191272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.1027191272
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.1088479399
Short name T562
Test name
Test status
Simulation time 175498901 ps
CPU time 0.88 seconds
Started Jul 26 05:14:33 PM PDT 24
Finished Jul 26 05:14:34 PM PDT 24
Peak memory 207072 kb
Host smart-b6e2043a-1eaf-443f-b885-60473bef38f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10884
79399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.1088479399
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.2913941487
Short name T2063
Test name
Test status
Simulation time 85359160 ps
CPU time 0.76 seconds
Started Jul 26 05:14:22 PM PDT 24
Finished Jul 26 05:14:23 PM PDT 24
Peak memory 206988 kb
Host smart-d706a3c4-1312-44b4-9ea7-cc2b983c2bde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29139
41487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.2913941487
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.1893339977
Short name T1157
Test name
Test status
Simulation time 12150439793 ps
CPU time 30.95 seconds
Started Jul 26 05:14:23 PM PDT 24
Finished Jul 26 05:14:54 PM PDT 24
Peak memory 215508 kb
Host smart-823abc99-cf6c-4aeb-816f-e7fe1f36aaef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18933
39977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.1893339977
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.572185885
Short name T2328
Test name
Test status
Simulation time 178928926 ps
CPU time 0.87 seconds
Started Jul 26 05:14:21 PM PDT 24
Finished Jul 26 05:14:22 PM PDT 24
Peak memory 207052 kb
Host smart-3aa350cb-d017-4d25-9368-cfe5bd7e14b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57218
5885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.572185885
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.4093801151
Short name T321
Test name
Test status
Simulation time 216603820 ps
CPU time 1.08 seconds
Started Jul 26 05:14:29 PM PDT 24
Finished Jul 26 05:14:30 PM PDT 24
Peak memory 207124 kb
Host smart-9ee58c15-88ea-4068-94fd-ff61cf006693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40938
01151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.4093801151
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.3589115296
Short name T2001
Test name
Test status
Simulation time 173982898 ps
CPU time 0.88 seconds
Started Jul 26 05:14:24 PM PDT 24
Finished Jul 26 05:14:25 PM PDT 24
Peak memory 207028 kb
Host smart-92a3cfa0-df0a-437d-b4e2-c2469d4e0ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35891
15296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.3589115296
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.4238084899
Short name T2661
Test name
Test status
Simulation time 197592425 ps
CPU time 0.93 seconds
Started Jul 26 05:14:29 PM PDT 24
Finished Jul 26 05:14:30 PM PDT 24
Peak memory 207124 kb
Host smart-0395b912-e4b3-4e62-86c4-162d6a1dd171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42380
84899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.4238084899
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.4114464667
Short name T677
Test name
Test status
Simulation time 130670310 ps
CPU time 0.77 seconds
Started Jul 26 05:14:25 PM PDT 24
Finished Jul 26 05:14:25 PM PDT 24
Peak memory 207096 kb
Host smart-1adad39d-1a78-4597-b074-8c8ec90f5cd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41144
64667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.4114464667
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.1225977667
Short name T760
Test name
Test status
Simulation time 188125015 ps
CPU time 0.84 seconds
Started Jul 26 05:14:25 PM PDT 24
Finished Jul 26 05:14:26 PM PDT 24
Peak memory 207180 kb
Host smart-e4ff11ea-58f1-45df-b15e-63913f950cce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12259
77667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.1225977667
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.2167685400
Short name T2750
Test name
Test status
Simulation time 182652952 ps
CPU time 0.93 seconds
Started Jul 26 05:14:19 PM PDT 24
Finished Jul 26 05:14:20 PM PDT 24
Peak memory 207092 kb
Host smart-a89ceff8-3f98-49d6-a6ed-2129f6d173d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21676
85400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.2167685400
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.3018956309
Short name T1568
Test name
Test status
Simulation time 187587496 ps
CPU time 0.99 seconds
Started Jul 26 05:14:22 PM PDT 24
Finished Jul 26 05:14:23 PM PDT 24
Peak memory 207020 kb
Host smart-5a563bf1-66cb-46db-a1bd-b0148c56f894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30189
56309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.3018956309
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.759194301
Short name T573
Test name
Test status
Simulation time 3237573061 ps
CPU time 100.3 seconds
Started Jul 26 05:14:23 PM PDT 24
Finished Jul 26 05:16:04 PM PDT 24
Peak memory 215528 kb
Host smart-c556c5c1-a306-4cbb-80d1-3c6ae3a0dc73
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=759194301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.759194301
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.1245684371
Short name T2676
Test name
Test status
Simulation time 152027595 ps
CPU time 0.81 seconds
Started Jul 26 05:14:22 PM PDT 24
Finished Jul 26 05:14:22 PM PDT 24
Peak memory 207076 kb
Host smart-849bf128-25c9-4c8b-bce4-51328ad47a47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12456
84371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.1245684371
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.1103513472
Short name T1711
Test name
Test status
Simulation time 185390847 ps
CPU time 0.91 seconds
Started Jul 26 05:14:29 PM PDT 24
Finished Jul 26 05:14:31 PM PDT 24
Peak memory 207124 kb
Host smart-0cdf8366-5d19-42b7-a97c-c016acd74536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11035
13472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.1103513472
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.2008126056
Short name T318
Test name
Test status
Simulation time 1082595676 ps
CPU time 2.71 seconds
Started Jul 26 05:14:28 PM PDT 24
Finished Jul 26 05:14:31 PM PDT 24
Peak memory 207244 kb
Host smart-49877cef-3db3-425b-8062-0d5c46359766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20081
26056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.2008126056
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.1834754857
Short name T2248
Test name
Test status
Simulation time 6961345014 ps
CPU time 210 seconds
Started Jul 26 05:14:23 PM PDT 24
Finished Jul 26 05:17:53 PM PDT 24
Peak memory 215488 kb
Host smart-dabce650-b8de-4ade-87f7-e6d6fbd7f0df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18347
54857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.1834754857
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_timeout_missing_host_handshake.1592319265
Short name T665
Test name
Test status
Simulation time 762425313 ps
CPU time 5.1 seconds
Started Jul 26 05:14:17 PM PDT 24
Finished Jul 26 05:14:22 PM PDT 24
Peak memory 207188 kb
Host smart-064ec7a2-c6d8-44ee-8309-06f7f245ed5a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592319265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_timeout_missing_hos
t_handshake.1592319265
Directory /workspace/41.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.1632262856
Short name T1209
Test name
Test status
Simulation time 52812947 ps
CPU time 0.7 seconds
Started Jul 26 05:14:29 PM PDT 24
Finished Jul 26 05:14:30 PM PDT 24
Peak memory 207072 kb
Host smart-092fe78b-77b9-40d6-867f-a643f3706c21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1632262856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.1632262856
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.724732597
Short name T1815
Test name
Test status
Simulation time 3485805081 ps
CPU time 5.28 seconds
Started Jul 26 05:14:28 PM PDT 24
Finished Jul 26 05:14:33 PM PDT 24
Peak memory 207356 kb
Host smart-7b8e129f-2d16-4f82-8095-2b8aaea87bb2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724732597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_ao
n_wake_disconnect.724732597
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.3461662149
Short name T808
Test name
Test status
Simulation time 13367168736 ps
CPU time 17.37 seconds
Started Jul 26 05:14:26 PM PDT 24
Finished Jul 26 05:14:43 PM PDT 24
Peak memory 207448 kb
Host smart-84a12dcc-90c7-4ceb-8bbe-626f13ab9603
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461662149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.3461662149
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.601042632
Short name T2404
Test name
Test status
Simulation time 23314384891 ps
CPU time 30.33 seconds
Started Jul 26 05:14:23 PM PDT 24
Finished Jul 26 05:14:54 PM PDT 24
Peak memory 207304 kb
Host smart-97df69e1-9b1e-414c-9b5a-992cd5d34301
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601042632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_ao
n_wake_resume.601042632
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.1161288129
Short name T812
Test name
Test status
Simulation time 178428096 ps
CPU time 0.89 seconds
Started Jul 26 05:14:33 PM PDT 24
Finished Jul 26 05:14:34 PM PDT 24
Peak memory 207084 kb
Host smart-afa8358f-a183-4a74-b729-0a08404ab17f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11612
88129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.1161288129
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.1954276367
Short name T821
Test name
Test status
Simulation time 136867707 ps
CPU time 0.83 seconds
Started Jul 26 05:14:20 PM PDT 24
Finished Jul 26 05:14:21 PM PDT 24
Peak memory 207092 kb
Host smart-596d7df7-bb34-4023-9fb1-a10b46d532b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19542
76367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.1954276367
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.1881554876
Short name T2066
Test name
Test status
Simulation time 202908995 ps
CPU time 1.13 seconds
Started Jul 26 05:14:32 PM PDT 24
Finished Jul 26 05:14:34 PM PDT 24
Peak memory 206904 kb
Host smart-a807d2da-a995-4b1a-b4ff-c073c86b3b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18815
54876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.1881554876
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.725533260
Short name T207
Test name
Test status
Simulation time 490813278 ps
CPU time 1.42 seconds
Started Jul 26 05:14:25 PM PDT 24
Finished Jul 26 05:14:26 PM PDT 24
Peak memory 207204 kb
Host smart-3955c494-c54d-49f0-b023-0487dfa4018a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=725533260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.725533260
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.3032678037
Short name T2387
Test name
Test status
Simulation time 16821615444 ps
CPU time 35.4 seconds
Started Jul 26 05:14:28 PM PDT 24
Finished Jul 26 05:15:04 PM PDT 24
Peak memory 207396 kb
Host smart-61f66ed2-478d-4d31-aa8b-4d5bb6c6ceb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30326
78037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.3032678037
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_device_timeout.1487377060
Short name T405
Test name
Test status
Simulation time 583826153 ps
CPU time 12.21 seconds
Started Jul 26 05:14:21 PM PDT 24
Finished Jul 26 05:14:33 PM PDT 24
Peak memory 207252 kb
Host smart-1465f940-7e4b-45fe-b753-1f404011caa3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487377060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_timeout.1487377060
Directory /workspace/42.usbdev_device_timeout/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.1650402246
Short name T1413
Test name
Test status
Simulation time 398213582 ps
CPU time 1.45 seconds
Started Jul 26 05:14:30 PM PDT 24
Finished Jul 26 05:14:32 PM PDT 24
Peak memory 207092 kb
Host smart-914a7d7b-b192-4010-9147-96a3954c64fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16504
02246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.1650402246
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.3749383275
Short name T442
Test name
Test status
Simulation time 155059872 ps
CPU time 0.85 seconds
Started Jul 26 05:14:22 PM PDT 24
Finished Jul 26 05:14:23 PM PDT 24
Peak memory 207092 kb
Host smart-20cb69ed-fcd3-4356-8d02-ce50f48c405c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37493
83275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.3749383275
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.1977809683
Short name T2775
Test name
Test status
Simulation time 89157369 ps
CPU time 0.77 seconds
Started Jul 26 05:14:21 PM PDT 24
Finished Jul 26 05:14:22 PM PDT 24
Peak memory 207092 kb
Host smart-474c8a92-3446-49f8-8aab-0d6be95cb934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19778
09683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.1977809683
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.2429652106
Short name T1203
Test name
Test status
Simulation time 871009655 ps
CPU time 2.27 seconds
Started Jul 26 05:14:22 PM PDT 24
Finished Jul 26 05:14:24 PM PDT 24
Peak memory 207168 kb
Host smart-f4d041e8-9e4c-4411-aab5-4c06dbeac0d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24296
52106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.2429652106
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.850275627
Short name T869
Test name
Test status
Simulation time 315617019 ps
CPU time 2.48 seconds
Started Jul 26 05:14:20 PM PDT 24
Finished Jul 26 05:14:23 PM PDT 24
Peak memory 207260 kb
Host smart-3e0f55e6-053b-4d05-812b-e6aadfc1ff6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85027
5627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.850275627
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.825984492
Short name T1602
Test name
Test status
Simulation time 225352235 ps
CPU time 1.12 seconds
Started Jul 26 05:14:21 PM PDT 24
Finished Jul 26 05:14:23 PM PDT 24
Peak memory 207304 kb
Host smart-4ff097fb-1fb7-4a6b-bfd0-adf4acbeebd6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=825984492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.825984492
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.2900686788
Short name T971
Test name
Test status
Simulation time 147905042 ps
CPU time 0.95 seconds
Started Jul 26 05:14:29 PM PDT 24
Finished Jul 26 05:14:30 PM PDT 24
Peak memory 207092 kb
Host smart-ed13c3de-370e-48b5-9476-4631e977dc36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29006
86788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.2900686788
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.4285191776
Short name T2287
Test name
Test status
Simulation time 203335794 ps
CPU time 0.97 seconds
Started Jul 26 05:14:21 PM PDT 24
Finished Jul 26 05:14:22 PM PDT 24
Peak memory 207152 kb
Host smart-9e932e49-904f-402c-9121-7cdf4cfa946d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42851
91776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.4285191776
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.1321826867
Short name T2445
Test name
Test status
Simulation time 5226837752 ps
CPU time 145.02 seconds
Started Jul 26 05:14:22 PM PDT 24
Finished Jul 26 05:16:47 PM PDT 24
Peak memory 215604 kb
Host smart-9fecbf04-1de8-40ae-9941-473c3f4317cc
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1321826867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.1321826867
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_iso_retraction.1039413221
Short name T746
Test name
Test status
Simulation time 8382325945 ps
CPU time 54.46 seconds
Started Jul 26 05:14:21 PM PDT 24
Finished Jul 26 05:15:16 PM PDT 24
Peak memory 207308 kb
Host smart-f0fda64d-0771-4d86-9148-8da9cd1f4f3f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1039413221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_iso_retraction.1039413221
Directory /workspace/42.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.695441598
Short name T882
Test name
Test status
Simulation time 233414110 ps
CPU time 1.03 seconds
Started Jul 26 05:14:33 PM PDT 24
Finished Jul 26 05:14:34 PM PDT 24
Peak memory 206944 kb
Host smart-c3119cee-3eef-47cf-9a96-2e70ee64fe5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69544
1598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.695441598
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.3212862419
Short name T784
Test name
Test status
Simulation time 23384295268 ps
CPU time 28.09 seconds
Started Jul 26 05:14:23 PM PDT 24
Finished Jul 26 05:14:51 PM PDT 24
Peak memory 207176 kb
Host smart-b0ec8477-50b0-40be-8311-c6661d7abccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32128
62419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.3212862419
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.2092361774
Short name T745
Test name
Test status
Simulation time 3316030083 ps
CPU time 5.12 seconds
Started Jul 26 05:14:33 PM PDT 24
Finished Jul 26 05:14:38 PM PDT 24
Peak memory 207188 kb
Host smart-c210de4e-9290-4d0e-99ea-93655e9d6e4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20923
61774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.2092361774
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.1172491244
Short name T651
Test name
Test status
Simulation time 8530377138 ps
CPU time 233.89 seconds
Started Jul 26 05:14:33 PM PDT 24
Finished Jul 26 05:18:27 PM PDT 24
Peak memory 215536 kb
Host smart-5256be14-690a-49a1-bb96-09c4a0a7d8d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11724
91244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.1172491244
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.4045921440
Short name T2324
Test name
Test status
Simulation time 5612208115 ps
CPU time 171.17 seconds
Started Jul 26 05:14:22 PM PDT 24
Finished Jul 26 05:17:14 PM PDT 24
Peak memory 215412 kb
Host smart-d963c6e8-a7e3-45b3-bd55-5b780e5b5685
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4045921440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.4045921440
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.894013604
Short name T2527
Test name
Test status
Simulation time 241911785 ps
CPU time 1.13 seconds
Started Jul 26 05:14:28 PM PDT 24
Finished Jul 26 05:14:29 PM PDT 24
Peak memory 207108 kb
Host smart-4e6d6595-107b-4a2c-a59e-e496741e2f25
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=894013604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.894013604
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.2805677156
Short name T2546
Test name
Test status
Simulation time 241539994 ps
CPU time 0.99 seconds
Started Jul 26 05:14:31 PM PDT 24
Finished Jul 26 05:14:32 PM PDT 24
Peak memory 206904 kb
Host smart-aa55fc3c-62a6-4e8c-8898-4fca80a84287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28056
77156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.2805677156
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.45122204
Short name T2692
Test name
Test status
Simulation time 3761247321 ps
CPU time 29.66 seconds
Started Jul 26 05:14:27 PM PDT 24
Finished Jul 26 05:14:57 PM PDT 24
Peak memory 215536 kb
Host smart-bfab6588-8fad-4180-bb43-30a40f5b62bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45122
204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.45122204
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.2204675273
Short name T426
Test name
Test status
Simulation time 2997878167 ps
CPU time 88.52 seconds
Started Jul 26 05:14:21 PM PDT 24
Finished Jul 26 05:15:49 PM PDT 24
Peak memory 215536 kb
Host smart-b20c614b-af3e-420d-9563-21247392838c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2204675273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.2204675273
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.23313631
Short name T529
Test name
Test status
Simulation time 154257980 ps
CPU time 0.87 seconds
Started Jul 26 05:14:22 PM PDT 24
Finished Jul 26 05:14:23 PM PDT 24
Peak memory 207104 kb
Host smart-537a7da1-2b62-4a00-94d5-c717aa536406
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=23313631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.23313631
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.282204705
Short name T1281
Test name
Test status
Simulation time 157972305 ps
CPU time 0.85 seconds
Started Jul 26 05:14:21 PM PDT 24
Finished Jul 26 05:14:22 PM PDT 24
Peak memory 207152 kb
Host smart-52d583d5-1a1b-4a77-b20b-05cfb25acd24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28220
4705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.282204705
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.4147974908
Short name T142
Test name
Test status
Simulation time 210790494 ps
CPU time 0.99 seconds
Started Jul 26 05:14:23 PM PDT 24
Finished Jul 26 05:14:24 PM PDT 24
Peak memory 207068 kb
Host smart-f14db72a-5197-47e3-89a7-891720e11595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41479
74908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.4147974908
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.2246099367
Short name T2388
Test name
Test status
Simulation time 197084250 ps
CPU time 0.9 seconds
Started Jul 26 05:14:27 PM PDT 24
Finished Jul 26 05:14:28 PM PDT 24
Peak memory 207100 kb
Host smart-017d69fa-369c-48bc-9168-17a8c28ff867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22460
99367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.2246099367
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.1420920310
Short name T2289
Test name
Test status
Simulation time 174440060 ps
CPU time 0.89 seconds
Started Jul 26 05:14:33 PM PDT 24
Finished Jul 26 05:14:34 PM PDT 24
Peak memory 207084 kb
Host smart-5a9689af-7e42-4ee1-820a-bc12ba0b2606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14209
20310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.1420920310
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.3610861102
Short name T2406
Test name
Test status
Simulation time 231598376 ps
CPU time 0.94 seconds
Started Jul 26 05:14:22 PM PDT 24
Finished Jul 26 05:14:23 PM PDT 24
Peak memory 207080 kb
Host smart-6693aca8-8df7-4c88-8b4b-f8141cedacbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36108
61102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.3610861102
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.146851589
Short name T1747
Test name
Test status
Simulation time 174579191 ps
CPU time 0.88 seconds
Started Jul 26 05:14:23 PM PDT 24
Finished Jul 26 05:14:24 PM PDT 24
Peak memory 207116 kb
Host smart-64255d0d-6ac1-479a-a395-b55d8285cc86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14685
1589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.146851589
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.954646132
Short name T2025
Test name
Test status
Simulation time 228846890 ps
CPU time 1.03 seconds
Started Jul 26 05:14:33 PM PDT 24
Finished Jul 26 05:14:35 PM PDT 24
Peak memory 206932 kb
Host smart-3458bbc6-50c4-475a-bf46-01be5349565d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=954646132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.954646132
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.1543254839
Short name T1985
Test name
Test status
Simulation time 150568802 ps
CPU time 0.82 seconds
Started Jul 26 05:14:39 PM PDT 24
Finished Jul 26 05:14:40 PM PDT 24
Peak memory 206880 kb
Host smart-7b8f5639-22a6-400f-868d-c175e50c191b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15432
54839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.1543254839
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.1033177445
Short name T618
Test name
Test status
Simulation time 53181414 ps
CPU time 0.72 seconds
Started Jul 26 05:14:32 PM PDT 24
Finished Jul 26 05:14:33 PM PDT 24
Peak memory 207068 kb
Host smart-1315b2bf-7784-494d-900c-c6d6175241e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10331
77445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.1033177445
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.3660984303
Short name T1430
Test name
Test status
Simulation time 9224305503 ps
CPU time 25.11 seconds
Started Jul 26 05:14:34 PM PDT 24
Finished Jul 26 05:15:00 PM PDT 24
Peak memory 215652 kb
Host smart-c183b95b-cfd2-40d7-a28c-758188f82388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36609
84303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.3660984303
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.3570903297
Short name T1359
Test name
Test status
Simulation time 205212041 ps
CPU time 0.87 seconds
Started Jul 26 05:14:27 PM PDT 24
Finished Jul 26 05:14:28 PM PDT 24
Peak memory 207100 kb
Host smart-deca17a8-0945-4118-b9b8-5af211c2a909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35709
03297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.3570903297
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.1770263430
Short name T2141
Test name
Test status
Simulation time 249274046 ps
CPU time 0.97 seconds
Started Jul 26 05:14:29 PM PDT 24
Finished Jul 26 05:14:30 PM PDT 24
Peak memory 206952 kb
Host smart-0411a49e-8f50-4467-8cac-4d546ccb4ae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17702
63430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.1770263430
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.2092244774
Short name T2489
Test name
Test status
Simulation time 293922023 ps
CPU time 1.09 seconds
Started Jul 26 05:14:30 PM PDT 24
Finished Jul 26 05:14:31 PM PDT 24
Peak memory 207100 kb
Host smart-3584c5f2-4dbb-4b47-8972-a7a2a99f0c98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20922
44774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.2092244774
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.1250791269
Short name T338
Test name
Test status
Simulation time 171113610 ps
CPU time 0.93 seconds
Started Jul 26 05:14:30 PM PDT 24
Finished Jul 26 05:14:31 PM PDT 24
Peak memory 207092 kb
Host smart-6318b9d9-cd1e-4103-b41e-8e0adf16e317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12507
91269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.1250791269
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.2426572579
Short name T106
Test name
Test status
Simulation time 166419069 ps
CPU time 0.84 seconds
Started Jul 26 05:14:30 PM PDT 24
Finished Jul 26 05:14:31 PM PDT 24
Peak memory 206988 kb
Host smart-cc3982a4-daa5-4167-9ca7-11f5bb0d6345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24265
72579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.2426572579
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.4001860353
Short name T931
Test name
Test status
Simulation time 142642430 ps
CPU time 0.83 seconds
Started Jul 26 05:14:30 PM PDT 24
Finished Jul 26 05:14:31 PM PDT 24
Peak memory 206996 kb
Host smart-474d9117-d7b3-493a-9915-c86fbb819414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40018
60353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.4001860353
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.3721074452
Short name T517
Test name
Test status
Simulation time 151708983 ps
CPU time 0.85 seconds
Started Jul 26 05:14:28 PM PDT 24
Finished Jul 26 05:14:29 PM PDT 24
Peak memory 207056 kb
Host smart-a3450b6a-c12c-4a4b-b87e-3a53301a70c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37210
74452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.3721074452
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.3649946311
Short name T1627
Test name
Test status
Simulation time 245097313 ps
CPU time 1.04 seconds
Started Jul 26 05:14:30 PM PDT 24
Finished Jul 26 05:14:31 PM PDT 24
Peak memory 207152 kb
Host smart-80a17643-617c-406a-afeb-44f097a31c81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36499
46311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.3649946311
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.1807869302
Short name T1442
Test name
Test status
Simulation time 6213117339 ps
CPU time 48.85 seconds
Started Jul 26 05:14:30 PM PDT 24
Finished Jul 26 05:15:19 PM PDT 24
Peak memory 216744 kb
Host smart-61f9f95d-0294-43c2-babf-c48f4a20c062
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1807869302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.1807869302
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.441206373
Short name T1730
Test name
Test status
Simulation time 185284282 ps
CPU time 0.86 seconds
Started Jul 26 05:14:29 PM PDT 24
Finished Jul 26 05:14:29 PM PDT 24
Peak memory 207056 kb
Host smart-715209d9-0f67-4bdf-81f3-e1efa5096f40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44120
6373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.441206373
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.48083926
Short name T2047
Test name
Test status
Simulation time 204467065 ps
CPU time 0.91 seconds
Started Jul 26 05:14:40 PM PDT 24
Finished Jul 26 05:14:41 PM PDT 24
Peak memory 206928 kb
Host smart-22eed8c7-fbb1-4450-995f-5555fd00390b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48083
926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.48083926
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.575939489
Short name T920
Test name
Test status
Simulation time 627681678 ps
CPU time 1.81 seconds
Started Jul 26 05:14:31 PM PDT 24
Finished Jul 26 05:14:33 PM PDT 24
Peak memory 206912 kb
Host smart-89a783c4-40ee-4a20-9cf3-b14707a18fc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57593
9489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.575939489
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.1815190281
Short name T1804
Test name
Test status
Simulation time 4492600050 ps
CPU time 44.09 seconds
Started Jul 26 05:14:30 PM PDT 24
Finished Jul 26 05:15:14 PM PDT 24
Peak memory 216780 kb
Host smart-b7144895-81ea-44c3-b202-671e07ca9810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18151
90281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.1815190281
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_timeout_missing_host_handshake.2284235467
Short name T2254
Test name
Test status
Simulation time 722013422 ps
CPU time 15.59 seconds
Started Jul 26 05:14:19 PM PDT 24
Finished Jul 26 05:14:35 PM PDT 24
Peak memory 207152 kb
Host smart-790b3fd7-6e62-4469-ad7d-a61cb563d786
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284235467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_timeout_missing_hos
t_handshake.2284235467
Directory /workspace/42.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.536048565
Short name T783
Test name
Test status
Simulation time 66089327 ps
CPU time 0.73 seconds
Started Jul 26 05:14:43 PM PDT 24
Finished Jul 26 05:14:44 PM PDT 24
Peak memory 207176 kb
Host smart-0ab71f5c-20d6-45a5-be40-e871e8a30521
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=536048565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.536048565
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.1604354960
Short name T2403
Test name
Test status
Simulation time 4304062595 ps
CPU time 6.43 seconds
Started Jul 26 05:14:40 PM PDT 24
Finished Jul 26 05:14:47 PM PDT 24
Peak memory 207180 kb
Host smart-818abb62-bf7d-426f-b884-9c67227d01be
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604354960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_a
on_wake_disconnect.1604354960
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.3719020845
Short name T1403
Test name
Test status
Simulation time 13412218631 ps
CPU time 15.58 seconds
Started Jul 26 05:14:29 PM PDT 24
Finished Jul 26 05:14:45 PM PDT 24
Peak memory 207396 kb
Host smart-2752f02f-aeab-4975-8922-33308a42b48f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719020845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.3719020845
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.3944929033
Short name T1649
Test name
Test status
Simulation time 23361080286 ps
CPU time 28.44 seconds
Started Jul 26 05:14:31 PM PDT 24
Finished Jul 26 05:15:00 PM PDT 24
Peak memory 207360 kb
Host smart-0769f532-d73e-4c85-8acc-415a4f157bab
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944929033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_a
on_wake_resume.3944929033
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.2204394797
Short name T1678
Test name
Test status
Simulation time 159401820 ps
CPU time 0.92 seconds
Started Jul 26 05:14:30 PM PDT 24
Finished Jul 26 05:14:31 PM PDT 24
Peak memory 207096 kb
Host smart-94ee337b-8af5-471f-a0d2-d6dc7f705645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22043
94797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.2204394797
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.3263541783
Short name T1866
Test name
Test status
Simulation time 150434116 ps
CPU time 0.89 seconds
Started Jul 26 05:14:29 PM PDT 24
Finished Jul 26 05:14:30 PM PDT 24
Peak memory 206968 kb
Host smart-373fc01a-5692-455c-a376-89fbddb6e582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32635
41783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.3263541783
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.2151790948
Short name T2007
Test name
Test status
Simulation time 343941581 ps
CPU time 1.35 seconds
Started Jul 26 05:14:35 PM PDT 24
Finished Jul 26 05:14:36 PM PDT 24
Peak memory 207208 kb
Host smart-def3a44d-115b-4249-9026-99dca9d0a19d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21517
90948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.2151790948
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.3621209315
Short name T557
Test name
Test status
Simulation time 706013307 ps
CPU time 2.07 seconds
Started Jul 26 05:14:31 PM PDT 24
Finished Jul 26 05:14:33 PM PDT 24
Peak memory 207352 kb
Host smart-3bdf706d-2cc5-476c-a3f5-bbd5112ecf8a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3621209315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.3621209315
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.4051775003
Short name T773
Test name
Test status
Simulation time 19008781039 ps
CPU time 40.17 seconds
Started Jul 26 05:14:29 PM PDT 24
Finished Jul 26 05:15:09 PM PDT 24
Peak memory 207332 kb
Host smart-a7c3cb15-98e2-4d5b-bba7-f588b2c4ad33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40517
75003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.4051775003
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_device_timeout.2981889029
Short name T1105
Test name
Test status
Simulation time 1086093533 ps
CPU time 9.24 seconds
Started Jul 26 05:14:30 PM PDT 24
Finished Jul 26 05:14:40 PM PDT 24
Peak memory 207376 kb
Host smart-1767836d-85e6-47ce-be05-cd54c22e360a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981889029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_timeout.2981889029
Directory /workspace/43.usbdev_device_timeout/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.1593179785
Short name T2054
Test name
Test status
Simulation time 321356481 ps
CPU time 1.17 seconds
Started Jul 26 05:14:32 PM PDT 24
Finished Jul 26 05:14:33 PM PDT 24
Peak memory 207092 kb
Host smart-d69fbf66-c17b-4d8f-b27e-41893242176c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15931
79785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.1593179785
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.1866876081
Short name T854
Test name
Test status
Simulation time 140608545 ps
CPU time 0.9 seconds
Started Jul 26 05:14:30 PM PDT 24
Finished Jul 26 05:14:31 PM PDT 24
Peak memory 207048 kb
Host smart-f8490244-42dc-4e10-af6a-64b50052561e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18668
76081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.1866876081
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.611789773
Short name T326
Test name
Test status
Simulation time 59208169 ps
CPU time 0.69 seconds
Started Jul 26 05:14:34 PM PDT 24
Finished Jul 26 05:14:35 PM PDT 24
Peak memory 207056 kb
Host smart-62225dc4-4c4e-46f4-b52d-a3abdb04acaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61178
9773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.611789773
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.1297520513
Short name T1535
Test name
Test status
Simulation time 905140278 ps
CPU time 2.74 seconds
Started Jul 26 05:14:30 PM PDT 24
Finished Jul 26 05:14:33 PM PDT 24
Peak memory 207364 kb
Host smart-78842860-16ea-4e22-8182-1c1b61f40be0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12975
20513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.1297520513
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.2622184365
Short name T2542
Test name
Test status
Simulation time 188501408 ps
CPU time 2.25 seconds
Started Jul 26 05:14:33 PM PDT 24
Finished Jul 26 05:14:36 PM PDT 24
Peak memory 207220 kb
Host smart-75f85fa6-7bcd-4671-aa08-09dbb53f2ec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26221
84365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.2622184365
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.2978628053
Short name T566
Test name
Test status
Simulation time 294209817 ps
CPU time 1.34 seconds
Started Jul 26 05:14:28 PM PDT 24
Finished Jul 26 05:14:30 PM PDT 24
Peak memory 215428 kb
Host smart-ee962f5b-3439-432e-838b-d8fdd76db4b7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2978628053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.2978628053
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.2809566667
Short name T1758
Test name
Test status
Simulation time 188213086 ps
CPU time 0.87 seconds
Started Jul 26 05:14:30 PM PDT 24
Finished Jul 26 05:14:31 PM PDT 24
Peak memory 206992 kb
Host smart-095e0be0-3e3c-40f3-8452-20fc4a6b1ea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28095
66667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.2809566667
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.1705174009
Short name T2448
Test name
Test status
Simulation time 165660809 ps
CPU time 0.92 seconds
Started Jul 26 05:14:29 PM PDT 24
Finished Jul 26 05:14:30 PM PDT 24
Peak memory 207020 kb
Host smart-6937aaa1-1910-406e-baef-5bd65d37aeba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17051
74009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.1705174009
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.4138682040
Short name T2146
Test name
Test status
Simulation time 9762151010 ps
CPU time 303.26 seconds
Started Jul 26 05:14:30 PM PDT 24
Finished Jul 26 05:19:34 PM PDT 24
Peak memory 215408 kb
Host smart-db9ec40e-17b6-46cf-98d2-7fc1be0c9c9b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4138682040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.4138682040
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_iso_retraction.574048392
Short name T380
Test name
Test status
Simulation time 11088061256 ps
CPU time 76.29 seconds
Started Jul 26 05:14:30 PM PDT 24
Finished Jul 26 05:15:46 PM PDT 24
Peak memory 207240 kb
Host smart-6401c577-75fb-4701-a994-340d3925687e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=574048392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_iso_retraction.574048392
Directory /workspace/43.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.984868826
Short name T62
Test name
Test status
Simulation time 172320837 ps
CPU time 0.88 seconds
Started Jul 26 05:14:31 PM PDT 24
Finished Jul 26 05:14:32 PM PDT 24
Peak memory 207132 kb
Host smart-1d922bc0-bd56-4e30-9ccb-6b23f5cffcc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98486
8826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.984868826
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.1519603178
Short name T2149
Test name
Test status
Simulation time 23334544414 ps
CPU time 26.16 seconds
Started Jul 26 05:14:30 PM PDT 24
Finished Jul 26 05:14:57 PM PDT 24
Peak memory 207284 kb
Host smart-3f2bb0ae-4c39-4945-b94a-4269c50291bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15196
03178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.1519603178
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.4054041569
Short name T316
Test name
Test status
Simulation time 3277543788 ps
CPU time 4.98 seconds
Started Jul 26 05:14:28 PM PDT 24
Finished Jul 26 05:14:33 PM PDT 24
Peak memory 207480 kb
Host smart-484f7b10-5ae5-4526-a2b3-1e54a528ee13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40540
41569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.4054041569
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.2313995316
Short name T613
Test name
Test status
Simulation time 7063449354 ps
CPU time 57.71 seconds
Started Jul 26 05:14:31 PM PDT 24
Finished Jul 26 05:15:29 PM PDT 24
Peak memory 217432 kb
Host smart-6adc3265-83f5-4815-b97c-b29b801ca396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23139
95316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.2313995316
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.970319249
Short name T866
Test name
Test status
Simulation time 3145946959 ps
CPU time 32.02 seconds
Started Jul 26 05:14:29 PM PDT 24
Finished Jul 26 05:15:01 PM PDT 24
Peak memory 215476 kb
Host smart-83f53b21-2629-4052-9c99-4557402315f5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=970319249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.970319249
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.2606550964
Short name T2657
Test name
Test status
Simulation time 242445682 ps
CPU time 1 seconds
Started Jul 26 05:14:40 PM PDT 24
Finished Jul 26 05:14:41 PM PDT 24
Peak memory 206916 kb
Host smart-ec4f6839-0bd3-4247-ba2b-df3364402100
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2606550964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.2606550964
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.547621776
Short name T2615
Test name
Test status
Simulation time 188562069 ps
CPU time 0.98 seconds
Started Jul 26 05:14:30 PM PDT 24
Finished Jul 26 05:14:31 PM PDT 24
Peak memory 207148 kb
Host smart-9ce8348a-19be-42b1-90d1-4993cd9dfd9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54762
1776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.547621776
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.501746498
Short name T561
Test name
Test status
Simulation time 7015558161 ps
CPU time 76.7 seconds
Started Jul 26 05:14:43 PM PDT 24
Finished Jul 26 05:16:00 PM PDT 24
Peak memory 217044 kb
Host smart-5df2dd06-a9b4-4b80-bf3c-3160cab7c229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50174
6498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.501746498
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.1038309611
Short name T1960
Test name
Test status
Simulation time 4438689965 ps
CPU time 38.14 seconds
Started Jul 26 05:14:39 PM PDT 24
Finished Jul 26 05:15:18 PM PDT 24
Peak memory 215596 kb
Host smart-aedfe4e5-6bfa-4514-99ef-0b0d518a1040
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1038309611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.1038309611
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.94001110
Short name T1376
Test name
Test status
Simulation time 174379133 ps
CPU time 0.91 seconds
Started Jul 26 05:14:57 PM PDT 24
Finished Jul 26 05:14:58 PM PDT 24
Peak memory 207108 kb
Host smart-a79c0240-9f30-4739-8d9b-25fdf75dde95
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=94001110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.94001110
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.2007204288
Short name T2095
Test name
Test status
Simulation time 151601507 ps
CPU time 0.88 seconds
Started Jul 26 05:14:40 PM PDT 24
Finished Jul 26 05:14:41 PM PDT 24
Peak memory 207040 kb
Host smart-e4ba3815-ddb2-4596-83d5-09330b8d380c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20072
04288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.2007204288
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.1601184392
Short name T2483
Test name
Test status
Simulation time 266456702 ps
CPU time 1.01 seconds
Started Jul 26 05:14:40 PM PDT 24
Finished Jul 26 05:14:42 PM PDT 24
Peak memory 206976 kb
Host smart-5a88b8ca-cc48-4d0a-a807-1766d362d92c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16011
84392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.1601184392
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.906141086
Short name T2716
Test name
Test status
Simulation time 198316014 ps
CPU time 0.95 seconds
Started Jul 26 05:14:40 PM PDT 24
Finished Jul 26 05:14:41 PM PDT 24
Peak memory 207064 kb
Host smart-95458fda-ca33-4d97-83d1-e73caa90b359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90614
1086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.906141086
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.2774360681
Short name T1433
Test name
Test status
Simulation time 181145913 ps
CPU time 0.95 seconds
Started Jul 26 05:14:40 PM PDT 24
Finished Jul 26 05:14:41 PM PDT 24
Peak memory 207152 kb
Host smart-49f6a4c8-20dc-461d-92cf-729f0cd4ecd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27743
60681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.2774360681
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.3483612453
Short name T1440
Test name
Test status
Simulation time 242143530 ps
CPU time 1.01 seconds
Started Jul 26 05:14:41 PM PDT 24
Finished Jul 26 05:14:42 PM PDT 24
Peak memory 206940 kb
Host smart-c911a040-6979-49d2-a508-09f29c07fef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34836
12453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.3483612453
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.630477366
Short name T2263
Test name
Test status
Simulation time 197141017 ps
CPU time 0.98 seconds
Started Jul 26 05:14:40 PM PDT 24
Finished Jul 26 05:14:41 PM PDT 24
Peak memory 207008 kb
Host smart-eeb2ce14-736f-45d6-8811-ffc86074131f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63047
7366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.630477366
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.815863816
Short name T1006
Test name
Test status
Simulation time 219915243 ps
CPU time 1.01 seconds
Started Jul 26 05:14:43 PM PDT 24
Finished Jul 26 05:14:44 PM PDT 24
Peak memory 207132 kb
Host smart-2d84e1bd-ab60-46ea-baa3-aeaf9b101d09
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=815863816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.815863816
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.1759459423
Short name T1756
Test name
Test status
Simulation time 148635969 ps
CPU time 0.87 seconds
Started Jul 26 05:14:39 PM PDT 24
Finished Jul 26 05:14:40 PM PDT 24
Peak memory 207032 kb
Host smart-d3b36145-526a-4c30-8558-c4ecf2cdce19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17594
59423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.1759459423
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.1758451246
Short name T1121
Test name
Test status
Simulation time 39228645 ps
CPU time 0.72 seconds
Started Jul 26 05:14:39 PM PDT 24
Finished Jul 26 05:14:40 PM PDT 24
Peak memory 207064 kb
Host smart-1d3e39cb-917b-40d7-93d3-be7ae2fe12d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17584
51246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.1758451246
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.1895034041
Short name T1893
Test name
Test status
Simulation time 6586440272 ps
CPU time 16.6 seconds
Started Jul 26 05:14:44 PM PDT 24
Finished Jul 26 05:15:01 PM PDT 24
Peak memory 215524 kb
Host smart-4363c182-3732-4a35-83fd-2ede675c0e50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18950
34041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.1895034041
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.1712423074
Short name T1247
Test name
Test status
Simulation time 169289830 ps
CPU time 0.87 seconds
Started Jul 26 05:14:42 PM PDT 24
Finished Jul 26 05:14:43 PM PDT 24
Peak memory 207024 kb
Host smart-9ac4526c-45d6-473e-897f-9466632409b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17124
23074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.1712423074
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.955060503
Short name T1506
Test name
Test status
Simulation time 191955825 ps
CPU time 0.92 seconds
Started Jul 26 05:14:41 PM PDT 24
Finished Jul 26 05:14:42 PM PDT 24
Peak memory 206988 kb
Host smart-2492910f-169b-4f79-9b68-f9b767b7e228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95506
0503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.955060503
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.1931490708
Short name T2476
Test name
Test status
Simulation time 269067595 ps
CPU time 1.02 seconds
Started Jul 26 05:14:43 PM PDT 24
Finished Jul 26 05:14:44 PM PDT 24
Peak memory 207100 kb
Host smart-f94e0ec8-dc2a-47f9-8768-f77457780be9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19314
90708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.1931490708
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.3503159974
Short name T1667
Test name
Test status
Simulation time 183659375 ps
CPU time 0.9 seconds
Started Jul 26 05:14:46 PM PDT 24
Finished Jul 26 05:14:47 PM PDT 24
Peak memory 207136 kb
Host smart-20f1a64c-f6a1-4cd8-bd49-4f0c6be41fc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35031
59974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.3503159974
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.1652813653
Short name T2504
Test name
Test status
Simulation time 175100153 ps
CPU time 1 seconds
Started Jul 26 05:14:43 PM PDT 24
Finished Jul 26 05:14:44 PM PDT 24
Peak memory 207332 kb
Host smart-83797f4b-bccd-4898-83be-a6059a522582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16528
13653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.1652813653
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.3831472126
Short name T382
Test name
Test status
Simulation time 188217139 ps
CPU time 0.94 seconds
Started Jul 26 05:14:40 PM PDT 24
Finished Jul 26 05:14:42 PM PDT 24
Peak memory 207012 kb
Host smart-a591c17e-a262-43f5-b1ac-25649422ac08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38314
72126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.3831472126
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.2690762138
Short name T491
Test name
Test status
Simulation time 170571497 ps
CPU time 0.93 seconds
Started Jul 26 05:14:43 PM PDT 24
Finished Jul 26 05:14:44 PM PDT 24
Peak memory 207096 kb
Host smart-f303b247-8f0e-4380-b7d2-dc6a94017ea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26907
62138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.2690762138
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.750070659
Short name T1407
Test name
Test status
Simulation time 245338682 ps
CPU time 1.13 seconds
Started Jul 26 05:14:42 PM PDT 24
Finished Jul 26 05:14:44 PM PDT 24
Peak memory 207072 kb
Host smart-2024614b-a1d5-429e-b854-923d960e4554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75007
0659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.750070659
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.2435967630
Short name T279
Test name
Test status
Simulation time 5960256296 ps
CPU time 60.03 seconds
Started Jul 26 05:14:42 PM PDT 24
Finished Jul 26 05:15:42 PM PDT 24
Peak memory 215432 kb
Host smart-54f9a269-fdac-4f8e-b6b7-57df5dd0823f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2435967630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.2435967630
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.3382628978
Short name T753
Test name
Test status
Simulation time 227848762 ps
CPU time 1.02 seconds
Started Jul 26 05:14:42 PM PDT 24
Finished Jul 26 05:14:43 PM PDT 24
Peak memory 207120 kb
Host smart-4a3ffcdd-105c-4eea-8bc9-7f002d55c758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33826
28978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.3382628978
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.2108972130
Short name T1419
Test name
Test status
Simulation time 162720066 ps
CPU time 0.89 seconds
Started Jul 26 05:14:41 PM PDT 24
Finished Jul 26 05:14:42 PM PDT 24
Peak memory 207080 kb
Host smart-738e2cb5-706a-4063-a66b-57f6eed0beeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21089
72130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.2108972130
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.1882053409
Short name T1643
Test name
Test status
Simulation time 617534900 ps
CPU time 1.73 seconds
Started Jul 26 05:14:41 PM PDT 24
Finished Jul 26 05:14:43 PM PDT 24
Peak memory 206992 kb
Host smart-e88ae092-7a15-42da-af47-5df9c24e1dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18820
53409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.1882053409
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.3730031097
Short name T606
Test name
Test status
Simulation time 6000470342 ps
CPU time 174.31 seconds
Started Jul 26 05:14:42 PM PDT 24
Finished Jul 26 05:17:37 PM PDT 24
Peak memory 215556 kb
Host smart-81ae6df7-0add-4bad-8a15-e1523ac0d12b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37300
31097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.3730031097
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_timeout_missing_host_handshake.1047783013
Short name T1538
Test name
Test status
Simulation time 1295009338 ps
CPU time 29.77 seconds
Started Jul 26 05:14:39 PM PDT 24
Finished Jul 26 05:15:09 PM PDT 24
Peak memory 207112 kb
Host smart-99559e02-3707-47b8-8a4b-40239360b66e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047783013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_timeout_missing_hos
t_handshake.1047783013
Directory /workspace/43.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.1177115877
Short name T789
Test name
Test status
Simulation time 38445808 ps
CPU time 0.67 seconds
Started Jul 26 05:14:58 PM PDT 24
Finished Jul 26 05:14:59 PM PDT 24
Peak memory 207228 kb
Host smart-b88b0b9f-9544-4dbc-86f5-bef700687ce8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1177115877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.1177115877
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.856044653
Short name T816
Test name
Test status
Simulation time 3939479881 ps
CPU time 6.42 seconds
Started Jul 26 05:14:42 PM PDT 24
Finished Jul 26 05:14:48 PM PDT 24
Peak memory 207252 kb
Host smart-3eb13576-4e80-4e45-908c-7ee9ebbf0b11
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856044653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_ao
n_wake_disconnect.856044653
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.1007365928
Short name T966
Test name
Test status
Simulation time 13366700988 ps
CPU time 17.89 seconds
Started Jul 26 05:14:40 PM PDT 24
Finished Jul 26 05:14:58 PM PDT 24
Peak memory 207296 kb
Host smart-100ce00c-3105-44e7-973a-d9405dc42e6e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007365928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.1007365928
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.2503269710
Short name T1532
Test name
Test status
Simulation time 23431749211 ps
CPU time 28.27 seconds
Started Jul 26 05:14:42 PM PDT 24
Finished Jul 26 05:15:10 PM PDT 24
Peak memory 207216 kb
Host smart-c412aeda-6ab0-4e4d-b341-7cab3362abd5
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503269710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_a
on_wake_resume.2503269710
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.3049324533
Short name T1361
Test name
Test status
Simulation time 151141583 ps
CPU time 0.87 seconds
Started Jul 26 05:14:42 PM PDT 24
Finished Jul 26 05:14:43 PM PDT 24
Peak memory 207128 kb
Host smart-8c770927-33c4-4e1b-aa3b-5a87fa59f226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30493
24533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.3049324533
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.1024223569
Short name T744
Test name
Test status
Simulation time 143313956 ps
CPU time 0.84 seconds
Started Jul 26 05:14:41 PM PDT 24
Finished Jul 26 05:14:42 PM PDT 24
Peak memory 206992 kb
Host smart-66a487a0-889e-4e36-bb00-bbe39fa81fe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10242
23569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.1024223569
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.1907508182
Short name T1138
Test name
Test status
Simulation time 495239005 ps
CPU time 1.76 seconds
Started Jul 26 05:14:43 PM PDT 24
Finished Jul 26 05:14:45 PM PDT 24
Peak memory 207096 kb
Host smart-26b6d8da-89aa-4174-b86f-cfcef7e58252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19075
08182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.1907508182
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.2104609699
Short name T1047
Test name
Test status
Simulation time 931199501 ps
CPU time 2.43 seconds
Started Jul 26 05:14:47 PM PDT 24
Finished Jul 26 05:14:50 PM PDT 24
Peak memory 207304 kb
Host smart-ec5a6763-ab7f-4477-ba46-324ad2030c7e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2104609699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.2104609699
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.3187837265
Short name T1990
Test name
Test status
Simulation time 21772103921 ps
CPU time 44.72 seconds
Started Jul 26 05:14:39 PM PDT 24
Finished Jul 26 05:15:24 PM PDT 24
Peak memory 207312 kb
Host smart-4a2ef031-7cff-43a8-b55c-a63fcd80e683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31878
37265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.3187837265
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_device_timeout.41350411
Short name T1524
Test name
Test status
Simulation time 2530305676 ps
CPU time 22.56 seconds
Started Jul 26 05:14:40 PM PDT 24
Finished Jul 26 05:15:03 PM PDT 24
Peak memory 207348 kb
Host smart-a9467969-763a-4d6e-9496-1650fefc2895
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41350411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_timeout.41350411
Directory /workspace/44.usbdev_device_timeout/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.2089502063
Short name T2028
Test name
Test status
Simulation time 480050550 ps
CPU time 1.72 seconds
Started Jul 26 05:14:43 PM PDT 24
Finished Jul 26 05:14:45 PM PDT 24
Peak memory 207028 kb
Host smart-7db20a55-7ee8-4c3d-9abc-546966795a82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20895
02063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.2089502063
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.2889287249
Short name T2381
Test name
Test status
Simulation time 140610300 ps
CPU time 0.86 seconds
Started Jul 26 05:14:43 PM PDT 24
Finished Jul 26 05:14:44 PM PDT 24
Peak memory 207180 kb
Host smart-fc055eae-c8be-4cbc-9303-ce0aefb92a1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28892
87249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.2889287249
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.13325723
Short name T1540
Test name
Test status
Simulation time 53665608 ps
CPU time 0.78 seconds
Started Jul 26 05:14:43 PM PDT 24
Finished Jul 26 05:14:44 PM PDT 24
Peak memory 207324 kb
Host smart-11c044e7-0581-475d-8a09-db9dbb465df2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13325
723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.13325723
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.503030275
Short name T2565
Test name
Test status
Simulation time 1076726707 ps
CPU time 2.86 seconds
Started Jul 26 05:14:42 PM PDT 24
Finished Jul 26 05:14:46 PM PDT 24
Peak memory 207324 kb
Host smart-ed82158e-8741-41b9-8d13-136eaf30caad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50303
0275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.503030275
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.3803803882
Short name T2498
Test name
Test status
Simulation time 361268030 ps
CPU time 2.61 seconds
Started Jul 26 05:14:41 PM PDT 24
Finished Jul 26 05:14:44 PM PDT 24
Peak memory 207272 kb
Host smart-14a67500-3d41-478f-a539-5e56db0df7b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38038
03882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.3803803882
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.895063546
Short name T1904
Test name
Test status
Simulation time 210161169 ps
CPU time 1.04 seconds
Started Jul 26 05:14:43 PM PDT 24
Finished Jul 26 05:14:44 PM PDT 24
Peak memory 215368 kb
Host smart-6b212c94-d6c2-45be-9eb2-d2d16c060a6c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=895063546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.895063546
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.2434083294
Short name T2208
Test name
Test status
Simulation time 138967980 ps
CPU time 0.85 seconds
Started Jul 26 05:14:59 PM PDT 24
Finished Jul 26 05:15:00 PM PDT 24
Peak memory 207064 kb
Host smart-3a7309cc-692a-42a9-b688-4c619aa4814d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24340
83294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.2434083294
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.615412317
Short name T1274
Test name
Test status
Simulation time 225796172 ps
CPU time 0.99 seconds
Started Jul 26 05:14:55 PM PDT 24
Finished Jul 26 05:14:56 PM PDT 24
Peak memory 207080 kb
Host smart-a5260bf1-1b18-4a4d-9135-ceda5a684669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61541
2317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.615412317
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.202662871
Short name T2321
Test name
Test status
Simulation time 5104244848 ps
CPU time 157.52 seconds
Started Jul 26 05:14:43 PM PDT 24
Finished Jul 26 05:17:21 PM PDT 24
Peak memory 217288 kb
Host smart-f36b9d7e-a903-47e3-8953-c783ccc03ffb
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=202662871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.202662871
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_iso_retraction.2394733382
Short name T661
Test name
Test status
Simulation time 4067061593 ps
CPU time 30.52 seconds
Started Jul 26 05:14:58 PM PDT 24
Finished Jul 26 05:15:28 PM PDT 24
Peak memory 207356 kb
Host smart-e06bf299-4ab5-40c6-a798-60256cc7c692
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2394733382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_iso_retraction.2394733382
Directory /workspace/44.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.1791306916
Short name T1909
Test name
Test status
Simulation time 199650357 ps
CPU time 0.94 seconds
Started Jul 26 05:14:59 PM PDT 24
Finished Jul 26 05:15:00 PM PDT 24
Peak memory 207100 kb
Host smart-8d41c49f-bb2a-4c95-9ced-de4a4691cc58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17913
06916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.1791306916
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.2209391724
Short name T1998
Test name
Test status
Simulation time 23348192408 ps
CPU time 29.15 seconds
Started Jul 26 05:14:55 PM PDT 24
Finished Jul 26 05:15:24 PM PDT 24
Peak memory 207200 kb
Host smart-6d7008bc-0ed4-4412-98d9-b1fe962db7d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22093
91724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.2209391724
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.2398423829
Short name T1225
Test name
Test status
Simulation time 3327475071 ps
CPU time 5.24 seconds
Started Jul 26 05:15:01 PM PDT 24
Finished Jul 26 05:15:06 PM PDT 24
Peak memory 207128 kb
Host smart-83f45398-d2a3-4401-b9b7-42f54ea5c3b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23984
23829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.2398423829
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.3388867998
Short name T1027
Test name
Test status
Simulation time 4958175361 ps
CPU time 39.29 seconds
Started Jul 26 05:14:58 PM PDT 24
Finished Jul 26 05:15:37 PM PDT 24
Peak memory 217668 kb
Host smart-2465b1ca-0ab7-4ec8-ba41-21d7e06993c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33888
67998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.3388867998
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.383402414
Short name T1942
Test name
Test status
Simulation time 5551564651 ps
CPU time 58.75 seconds
Started Jul 26 05:14:54 PM PDT 24
Finished Jul 26 05:15:52 PM PDT 24
Peak memory 215516 kb
Host smart-2cd67274-b92d-4c8b-b40d-c747c9f89181
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=383402414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.383402414
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.3885296214
Short name T2718
Test name
Test status
Simulation time 330456481 ps
CPU time 1.15 seconds
Started Jul 26 05:14:57 PM PDT 24
Finished Jul 26 05:14:58 PM PDT 24
Peak memory 207044 kb
Host smart-7ebc1f1f-7784-4768-824a-817525bc6e38
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3885296214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.3885296214
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.604403791
Short name T2832
Test name
Test status
Simulation time 242320673 ps
CPU time 1.11 seconds
Started Jul 26 05:14:56 PM PDT 24
Finished Jul 26 05:14:57 PM PDT 24
Peak memory 207048 kb
Host smart-464f7782-f1e5-4c1d-9f25-8e525a090110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60440
3791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.604403791
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.3249945028
Short name T2757
Test name
Test status
Simulation time 5265389243 ps
CPU time 39.95 seconds
Started Jul 26 05:14:55 PM PDT 24
Finished Jul 26 05:15:36 PM PDT 24
Peak memory 217020 kb
Host smart-09c78158-fea0-4529-9bc2-09a89ec48a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32499
45028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.3249945028
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.887869572
Short name T1959
Test name
Test status
Simulation time 5262794476 ps
CPU time 52.55 seconds
Started Jul 26 05:14:57 PM PDT 24
Finished Jul 26 05:15:49 PM PDT 24
Peak memory 207236 kb
Host smart-fa16bfad-ab47-40b4-93f3-e83adb59ffb8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=887869572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.887869572
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.3815476520
Short name T2590
Test name
Test status
Simulation time 158708499 ps
CPU time 0.87 seconds
Started Jul 26 05:14:56 PM PDT 24
Finished Jul 26 05:14:57 PM PDT 24
Peak memory 207100 kb
Host smart-5707e98c-7d61-4020-94a9-19ded4275655
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3815476520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.3815476520
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.3141049990
Short name T1018
Test name
Test status
Simulation time 143891103 ps
CPU time 0.91 seconds
Started Jul 26 05:14:53 PM PDT 24
Finished Jul 26 05:14:54 PM PDT 24
Peak memory 207124 kb
Host smart-2e36a1a7-511f-4b5c-89c9-1d8598e895c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31410
49990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.3141049990
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.3875335707
Short name T110
Test name
Test status
Simulation time 189884788 ps
CPU time 0.91 seconds
Started Jul 26 05:14:57 PM PDT 24
Finished Jul 26 05:14:58 PM PDT 24
Peak memory 207128 kb
Host smart-ac22a6aa-cc06-4e43-86d9-f6ab5e0aa7e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38753
35707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.3875335707
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.2833287593
Short name T1432
Test name
Test status
Simulation time 159819909 ps
CPU time 0.93 seconds
Started Jul 26 05:14:56 PM PDT 24
Finished Jul 26 05:14:58 PM PDT 24
Peak memory 207008 kb
Host smart-fc101d6f-864d-4413-bf54-4de78569ea29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28332
87593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.2833287593
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.3860761055
Short name T1578
Test name
Test status
Simulation time 166010994 ps
CPU time 0.88 seconds
Started Jul 26 05:14:55 PM PDT 24
Finished Jul 26 05:14:56 PM PDT 24
Peak memory 207172 kb
Host smart-25eb8ee9-9865-48e6-8927-9e477c5085e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38607
61055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.3860761055
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.597638174
Short name T1787
Test name
Test status
Simulation time 206306220 ps
CPU time 0.92 seconds
Started Jul 26 05:14:55 PM PDT 24
Finished Jul 26 05:14:56 PM PDT 24
Peak memory 207100 kb
Host smart-2d53ad80-ff57-4042-983a-419497da4e3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59763
8174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.597638174
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.379127627
Short name T2418
Test name
Test status
Simulation time 180212183 ps
CPU time 0.88 seconds
Started Jul 26 05:14:52 PM PDT 24
Finished Jul 26 05:14:53 PM PDT 24
Peak memory 207064 kb
Host smart-dcf6040b-5ff5-4563-931b-edaf694a0681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37912
7627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.379127627
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.1093710081
Short name T1883
Test name
Test status
Simulation time 231782900 ps
CPU time 1.14 seconds
Started Jul 26 05:14:54 PM PDT 24
Finished Jul 26 05:14:56 PM PDT 24
Peak memory 207048 kb
Host smart-f225256c-b1f8-449a-8a64-cd10d1a4aa33
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1093710081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.1093710081
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.3445463063
Short name T2684
Test name
Test status
Simulation time 155177250 ps
CPU time 0.91 seconds
Started Jul 26 05:14:56 PM PDT 24
Finished Jul 26 05:14:57 PM PDT 24
Peak memory 207064 kb
Host smart-9dc3f573-5c9d-4741-afcf-4adf5731b832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34454
63063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.3445463063
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.557375906
Short name T1888
Test name
Test status
Simulation time 49631358 ps
CPU time 0.76 seconds
Started Jul 26 05:14:59 PM PDT 24
Finished Jul 26 05:15:00 PM PDT 24
Peak memory 207068 kb
Host smart-87884752-9041-4b97-8e48-d8a76e42c9fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55737
5906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.557375906
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.2709200836
Short name T809
Test name
Test status
Simulation time 11787520082 ps
CPU time 30.06 seconds
Started Jul 26 05:14:54 PM PDT 24
Finished Jul 26 05:15:24 PM PDT 24
Peak memory 215512 kb
Host smart-ce454820-bd3d-4957-a05e-fd42f593139f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27092
00836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.2709200836
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.1790827276
Short name T1644
Test name
Test status
Simulation time 148472855 ps
CPU time 0.85 seconds
Started Jul 26 05:14:56 PM PDT 24
Finished Jul 26 05:14:58 PM PDT 24
Peak memory 207044 kb
Host smart-5b78de6c-4eaf-4f4e-9686-f894779a5ff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17908
27276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.1790827276
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.60843419
Short name T592
Test name
Test status
Simulation time 200721396 ps
CPU time 0.95 seconds
Started Jul 26 05:14:58 PM PDT 24
Finished Jul 26 05:14:59 PM PDT 24
Peak memory 207120 kb
Host smart-47ed7430-c1be-40fc-a47d-f9685c4b1cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60843
419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.60843419
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.2293751838
Short name T2273
Test name
Test status
Simulation time 183288463 ps
CPU time 0.9 seconds
Started Jul 26 05:14:54 PM PDT 24
Finished Jul 26 05:14:55 PM PDT 24
Peak memory 206988 kb
Host smart-24a120c9-ccee-4d5d-b0d6-33ce1b308e2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22937
51838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.2293751838
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.3369010012
Short name T2689
Test name
Test status
Simulation time 179107801 ps
CPU time 0.89 seconds
Started Jul 26 05:14:57 PM PDT 24
Finished Jul 26 05:14:59 PM PDT 24
Peak memory 207128 kb
Host smart-3f3356c3-befc-4865-b337-bf3c200d7df6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33690
10012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.3369010012
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.647304060
Short name T2123
Test name
Test status
Simulation time 139445714 ps
CPU time 0.84 seconds
Started Jul 26 05:14:56 PM PDT 24
Finished Jul 26 05:14:57 PM PDT 24
Peak memory 207092 kb
Host smart-75efe2d8-68da-4360-85bc-eac331cc4c20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64730
4060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.647304060
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.1989289607
Short name T1614
Test name
Test status
Simulation time 183235476 ps
CPU time 0.92 seconds
Started Jul 26 05:14:55 PM PDT 24
Finished Jul 26 05:14:57 PM PDT 24
Peak memory 206992 kb
Host smart-1cf0e4cc-0ba0-4654-8dc9-17f99048e126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19892
89607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.1989289607
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.3147366554
Short name T1746
Test name
Test status
Simulation time 159593939 ps
CPU time 0.83 seconds
Started Jul 26 05:14:54 PM PDT 24
Finished Jul 26 05:14:55 PM PDT 24
Peak memory 207128 kb
Host smart-9783bb9a-ca0a-41dd-a9ab-6b0b3f72d5dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31473
66554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.3147366554
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.4018940970
Short name T348
Test name
Test status
Simulation time 265895228 ps
CPU time 1.11 seconds
Started Jul 26 05:14:56 PM PDT 24
Finished Jul 26 05:14:57 PM PDT 24
Peak memory 207116 kb
Host smart-4adbf5b1-476f-4358-a12d-bf0d13d3bb0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40189
40970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.4018940970
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.2270483690
Short name T2005
Test name
Test status
Simulation time 4115303033 ps
CPU time 41.24 seconds
Started Jul 26 05:15:03 PM PDT 24
Finished Jul 26 05:15:45 PM PDT 24
Peak memory 215580 kb
Host smart-dc82c364-e96d-420c-8547-234515e44b25
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2270483690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.2270483690
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.2973215589
Short name T2181
Test name
Test status
Simulation time 197550492 ps
CPU time 0.95 seconds
Started Jul 26 05:14:56 PM PDT 24
Finished Jul 26 05:14:58 PM PDT 24
Peak memory 207120 kb
Host smart-6a962f4c-cb2b-43ba-8ca4-a8d19a13151f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29732
15589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.2973215589
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.431968989
Short name T857
Test name
Test status
Simulation time 179240266 ps
CPU time 0.87 seconds
Started Jul 26 05:14:55 PM PDT 24
Finished Jul 26 05:14:56 PM PDT 24
Peak memory 207136 kb
Host smart-27e05b7e-944f-421a-8a19-4323aab6a693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43196
8989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.431968989
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.964199188
Short name T319
Test name
Test status
Simulation time 1025422493 ps
CPU time 2.59 seconds
Started Jul 26 05:14:55 PM PDT 24
Finished Jul 26 05:14:58 PM PDT 24
Peak memory 207260 kb
Host smart-a1454513-fc80-4785-8d8c-3d5c6dec7816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96419
9188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.964199188
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.4061565563
Short name T2335
Test name
Test status
Simulation time 5372882334 ps
CPU time 158.37 seconds
Started Jul 26 05:14:59 PM PDT 24
Finished Jul 26 05:17:37 PM PDT 24
Peak memory 215556 kb
Host smart-1c1e60bb-b9e6-475d-9a3c-e220e39ecee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40615
65563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.4061565563
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_timeout_missing_host_handshake.1539275934
Short name T572
Test name
Test status
Simulation time 3862842331 ps
CPU time 33.84 seconds
Started Jul 26 05:14:42 PM PDT 24
Finished Jul 26 05:15:16 PM PDT 24
Peak memory 207260 kb
Host smart-677c0591-e772-49f6-999a-e9143091efbb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539275934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_timeout_missing_hos
t_handshake.1539275934
Directory /workspace/44.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.1260389441
Short name T1256
Test name
Test status
Simulation time 38127762 ps
CPU time 0.67 seconds
Started Jul 26 05:15:09 PM PDT 24
Finished Jul 26 05:15:09 PM PDT 24
Peak memory 207088 kb
Host smart-951bf08b-aadd-47f5-8bfc-dd2cab2fd4c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1260389441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.1260389441
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.4177362122
Short name T596
Test name
Test status
Simulation time 3940743767 ps
CPU time 6.49 seconds
Started Jul 26 05:14:55 PM PDT 24
Finished Jul 26 05:15:02 PM PDT 24
Peak memory 207284 kb
Host smart-ba65405c-ad65-4edb-a76e-04dbb4fa0447
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177362122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_a
on_wake_disconnect.4177362122
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.3125146112
Short name T961
Test name
Test status
Simulation time 13382652027 ps
CPU time 14.46 seconds
Started Jul 26 05:14:55 PM PDT 24
Finished Jul 26 05:15:10 PM PDT 24
Peak memory 207396 kb
Host smart-adbce325-0926-4f08-a6c5-01c6fc35376c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125146112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.3125146112
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.2844195536
Short name T2579
Test name
Test status
Simulation time 23467684799 ps
CPU time 28.5 seconds
Started Jul 26 05:14:56 PM PDT 24
Finished Jul 26 05:15:25 PM PDT 24
Peak memory 207272 kb
Host smart-24336a69-7053-4aa1-9faf-d0b9ed842711
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844195536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_a
on_wake_resume.2844195536
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.3193924082
Short name T422
Test name
Test status
Simulation time 155129096 ps
CPU time 0.86 seconds
Started Jul 26 05:14:55 PM PDT 24
Finished Jul 26 05:14:56 PM PDT 24
Peak memory 206856 kb
Host smart-20c74db1-971c-427d-88a0-db5b21861f5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31939
24082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.3193924082
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.2990282709
Short name T560
Test name
Test status
Simulation time 156319932 ps
CPU time 0.83 seconds
Started Jul 26 05:14:55 PM PDT 24
Finished Jul 26 05:14:56 PM PDT 24
Peak memory 206860 kb
Host smart-ccf7a2d2-3b56-42dd-b466-ac7092a410ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29902
82709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.2990282709
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.3215799907
Short name T1595
Test name
Test status
Simulation time 513973028 ps
CPU time 1.72 seconds
Started Jul 26 05:14:53 PM PDT 24
Finished Jul 26 05:14:55 PM PDT 24
Peak memory 207068 kb
Host smart-ea45f425-e155-4ed2-88a6-0d9a07b4d589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32157
99907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.3215799907
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.1880903864
Short name T819
Test name
Test status
Simulation time 1380568554 ps
CPU time 3.67 seconds
Started Jul 26 05:14:59 PM PDT 24
Finished Jul 26 05:15:03 PM PDT 24
Peak memory 207268 kb
Host smart-d5929813-1716-431f-aa12-e7f49d65959f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1880903864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.1880903864
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.977334496
Short name T1837
Test name
Test status
Simulation time 16969772954 ps
CPU time 40.75 seconds
Started Jul 26 05:14:54 PM PDT 24
Finished Jul 26 05:15:35 PM PDT 24
Peak memory 207404 kb
Host smart-3b2f0307-82ed-4e77-9266-7bd9269b9681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97733
4496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.977334496
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_device_timeout.588400699
Short name T2300
Test name
Test status
Simulation time 3404155450 ps
CPU time 32.09 seconds
Started Jul 26 05:14:56 PM PDT 24
Finished Jul 26 05:15:28 PM PDT 24
Peak memory 207304 kb
Host smart-409c044f-f995-4269-b11c-b1098b7b3e7b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588400699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_timeout.588400699
Directory /workspace/45.usbdev_device_timeout/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.5847047
Short name T1217
Test name
Test status
Simulation time 333095016 ps
CPU time 1.21 seconds
Started Jul 26 05:14:59 PM PDT 24
Finished Jul 26 05:15:00 PM PDT 24
Peak memory 207068 kb
Host smart-1a3e570d-7bd7-456f-91d0-fd3e3d4cf3a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58470
47 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.5847047
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.564550462
Short name T2488
Test name
Test status
Simulation time 155818495 ps
CPU time 0.94 seconds
Started Jul 26 05:14:56 PM PDT 24
Finished Jul 26 05:14:57 PM PDT 24
Peak memory 207088 kb
Host smart-c2e2cafe-18bd-4e43-a0a1-5627cbf6436d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56455
0462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.564550462
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.3067070393
Short name T361
Test name
Test status
Simulation time 45023350 ps
CPU time 0.7 seconds
Started Jul 26 05:14:56 PM PDT 24
Finished Jul 26 05:14:57 PM PDT 24
Peak memory 207000 kb
Host smart-1072aea0-24f4-4f3f-82db-bccf78752c89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30670
70393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.3067070393
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.110308307
Short name T1958
Test name
Test status
Simulation time 842782302 ps
CPU time 2.26 seconds
Started Jul 26 05:14:59 PM PDT 24
Finished Jul 26 05:15:01 PM PDT 24
Peak memory 207384 kb
Host smart-ec7f1cad-7856-475d-a471-93925dbe14e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11030
8307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.110308307
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.1430500719
Short name T2027
Test name
Test status
Simulation time 261191852 ps
CPU time 1.78 seconds
Started Jul 26 05:14:55 PM PDT 24
Finished Jul 26 05:14:57 PM PDT 24
Peak memory 207220 kb
Host smart-0b77a9d6-fe83-4e36-a64e-8633009cd2c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14305
00719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.1430500719
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.3345208680
Short name T416
Test name
Test status
Simulation time 197696601 ps
CPU time 1.12 seconds
Started Jul 26 05:14:59 PM PDT 24
Finished Jul 26 05:15:00 PM PDT 24
Peak memory 215484 kb
Host smart-dab779e9-00ac-4cb6-832f-6d38df8a80f1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3345208680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.3345208680
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.3097996208
Short name T1662
Test name
Test status
Simulation time 152692310 ps
CPU time 0.87 seconds
Started Jul 26 05:14:55 PM PDT 24
Finished Jul 26 05:14:56 PM PDT 24
Peak memory 207092 kb
Host smart-7b9fe05b-300f-43db-9cda-deb469d20e9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30979
96208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.3097996208
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.956367673
Short name T548
Test name
Test status
Simulation time 196648762 ps
CPU time 0.95 seconds
Started Jul 26 05:15:02 PM PDT 24
Finished Jul 26 05:15:03 PM PDT 24
Peak memory 206912 kb
Host smart-38193e12-fbb2-44aa-898e-5b66c09e302a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95636
7673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.956367673
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.1449116857
Short name T2363
Test name
Test status
Simulation time 7782273208 ps
CPU time 244.3 seconds
Started Jul 26 05:14:54 PM PDT 24
Finished Jul 26 05:18:58 PM PDT 24
Peak memory 215564 kb
Host smart-a686877a-21e2-480d-8759-752a88baa096
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1449116857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.1449116857
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_iso_retraction.1057149201
Short name T921
Test name
Test status
Simulation time 7052322282 ps
CPU time 86.73 seconds
Started Jul 26 05:14:59 PM PDT 24
Finished Jul 26 05:16:25 PM PDT 24
Peak memory 207348 kb
Host smart-9228eb47-8d86-4685-8ff5-7bc0e2e5cd04
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1057149201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_iso_retraction.1057149201
Directory /workspace/45.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.441241947
Short name T2322
Test name
Test status
Simulation time 289429705 ps
CPU time 1.04 seconds
Started Jul 26 05:14:57 PM PDT 24
Finished Jul 26 05:14:58 PM PDT 24
Peak memory 207080 kb
Host smart-10ab66e5-bcb3-427f-b937-4428e9b5943a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44124
1947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.441241947
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.4283057111
Short name T892
Test name
Test status
Simulation time 23350905718 ps
CPU time 29.47 seconds
Started Jul 26 05:15:03 PM PDT 24
Finished Jul 26 05:15:33 PM PDT 24
Peak memory 207384 kb
Host smart-016b8213-dd17-4872-b26e-668c9d2cb2e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42830
57111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.4283057111
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.3131908008
Short name T1954
Test name
Test status
Simulation time 3329228809 ps
CPU time 4.7 seconds
Started Jul 26 05:14:55 PM PDT 24
Finished Jul 26 05:15:00 PM PDT 24
Peak memory 207376 kb
Host smart-fb3d5bf8-39ff-4543-b181-bde4bd74fbc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31319
08008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.3131908008
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.2018273792
Short name T2820
Test name
Test status
Simulation time 4868669991 ps
CPU time 149.17 seconds
Started Jul 26 05:14:57 PM PDT 24
Finished Jul 26 05:17:27 PM PDT 24
Peak memory 215648 kb
Host smart-470a7e67-4f7c-4699-93c5-788b9e649862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20182
73792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.2018273792
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.3120100358
Short name T2309
Test name
Test status
Simulation time 6939021816 ps
CPU time 204.4 seconds
Started Jul 26 05:14:59 PM PDT 24
Finished Jul 26 05:18:24 PM PDT 24
Peak memory 215532 kb
Host smart-f45f3ccc-d128-409f-a4b5-526c7472c6aa
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3120100358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.3120100358
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.333548473
Short name T2706
Test name
Test status
Simulation time 244861479 ps
CPU time 0.97 seconds
Started Jul 26 05:15:07 PM PDT 24
Finished Jul 26 05:15:08 PM PDT 24
Peak memory 207048 kb
Host smart-8338d6d8-db60-4bec-b2d1-de09f63c1fcf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=333548473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.333548473
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.3222451532
Short name T519
Test name
Test status
Simulation time 204187848 ps
CPU time 0.98 seconds
Started Jul 26 05:15:14 PM PDT 24
Finished Jul 26 05:15:15 PM PDT 24
Peak memory 207048 kb
Host smart-4bdec219-c53f-4bc8-8067-fcff4bfbdd1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32224
51532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.3222451532
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.2912379346
Short name T871
Test name
Test status
Simulation time 3300538681 ps
CPU time 25.13 seconds
Started Jul 26 05:15:09 PM PDT 24
Finished Jul 26 05:15:34 PM PDT 24
Peak memory 215436 kb
Host smart-6ae82bd4-5a7e-4ec0-8a42-1a14aeb5a2c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29123
79346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.2912379346
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.1951527915
Short name T640
Test name
Test status
Simulation time 5289674483 ps
CPU time 42.94 seconds
Started Jul 26 05:15:13 PM PDT 24
Finished Jul 26 05:15:56 PM PDT 24
Peak memory 217088 kb
Host smart-8941a644-97eb-4226-82c2-d97d5f5b1895
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1951527915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.1951527915
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.1808595124
Short name T1409
Test name
Test status
Simulation time 169912119 ps
CPU time 0.89 seconds
Started Jul 26 05:15:10 PM PDT 24
Finished Jul 26 05:15:11 PM PDT 24
Peak memory 207160 kb
Host smart-3f67a793-ed49-48ec-ae8b-dd0c2989f495
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1808595124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.1808595124
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.2012767262
Short name T1181
Test name
Test status
Simulation time 151280186 ps
CPU time 0.85 seconds
Started Jul 26 05:15:14 PM PDT 24
Finished Jul 26 05:15:15 PM PDT 24
Peak memory 207072 kb
Host smart-fc3b244e-8fec-4e3f-82ee-94c1049aaf7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20127
67262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.2012767262
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.3272620305
Short name T2044
Test name
Test status
Simulation time 244324269 ps
CPU time 0.96 seconds
Started Jul 26 05:15:09 PM PDT 24
Finished Jul 26 05:15:11 PM PDT 24
Peak memory 207020 kb
Host smart-6682473f-97c8-4176-ac9c-1982edfcb942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32726
20305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.3272620305
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.405504090
Short name T400
Test name
Test status
Simulation time 171344522 ps
CPU time 0.95 seconds
Started Jul 26 05:15:16 PM PDT 24
Finished Jul 26 05:15:17 PM PDT 24
Peak memory 207320 kb
Host smart-85a3f69e-c031-4653-8c8a-92789dfc2192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40550
4090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.405504090
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.3134577464
Short name T637
Test name
Test status
Simulation time 193444905 ps
CPU time 0.94 seconds
Started Jul 26 05:15:10 PM PDT 24
Finished Jul 26 05:15:11 PM PDT 24
Peak memory 207120 kb
Host smart-c66b965e-ab05-4d84-ab67-540faf6ca78a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31345
77464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.3134577464
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.2209437014
Short name T1057
Test name
Test status
Simulation time 145126556 ps
CPU time 0.86 seconds
Started Jul 26 05:15:06 PM PDT 24
Finished Jul 26 05:15:07 PM PDT 24
Peak memory 207116 kb
Host smart-b4abae14-efab-492a-8147-f229343f1e72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22094
37014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.2209437014
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.2881579644
Short name T836
Test name
Test status
Simulation time 179207438 ps
CPU time 0.88 seconds
Started Jul 26 05:15:14 PM PDT 24
Finished Jul 26 05:15:15 PM PDT 24
Peak memory 207052 kb
Host smart-dfbfd3c2-2e5b-4262-85a4-ab135658728e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28815
79644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.2881579644
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.3916545740
Short name T2385
Test name
Test status
Simulation time 262747308 ps
CPU time 1.06 seconds
Started Jul 26 05:15:07 PM PDT 24
Finished Jul 26 05:15:08 PM PDT 24
Peak memory 207156 kb
Host smart-37899406-a3b5-45d7-ae5c-05f5393dcd28
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3916545740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.3916545740
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.124020145
Short name T1054
Test name
Test status
Simulation time 177204017 ps
CPU time 0.87 seconds
Started Jul 26 05:15:07 PM PDT 24
Finished Jul 26 05:15:08 PM PDT 24
Peak memory 207040 kb
Host smart-3bf46791-4645-46fd-9f73-5f73c9e20442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12402
0145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.124020145
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.3261102257
Short name T2042
Test name
Test status
Simulation time 49824554 ps
CPU time 0.72 seconds
Started Jul 26 05:15:06 PM PDT 24
Finished Jul 26 05:15:07 PM PDT 24
Peak memory 206968 kb
Host smart-f795c11d-ba51-4300-8ad3-e1afc14905d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32611
02257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.3261102257
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.847841394
Short name T974
Test name
Test status
Simulation time 16748823688 ps
CPU time 47.3 seconds
Started Jul 26 05:15:09 PM PDT 24
Finished Jul 26 05:15:56 PM PDT 24
Peak memory 223732 kb
Host smart-d01be341-0793-4ef3-be3f-bbf7f27f1f59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84784
1394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.847841394
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.1145932922
Short name T556
Test name
Test status
Simulation time 163034322 ps
CPU time 0.87 seconds
Started Jul 26 05:15:09 PM PDT 24
Finished Jul 26 05:15:10 PM PDT 24
Peak memory 207128 kb
Host smart-1002fdad-4192-4aa2-a57f-94d591120b41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11459
32922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.1145932922
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.2172165756
Short name T2834
Test name
Test status
Simulation time 183886559 ps
CPU time 0.97 seconds
Started Jul 26 05:15:07 PM PDT 24
Finished Jul 26 05:15:08 PM PDT 24
Peak memory 207024 kb
Host smart-89aa0d5a-1933-46bb-b0e4-b12da73daf49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21721
65756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.2172165756
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.4083780721
Short name T1520
Test name
Test status
Simulation time 162975858 ps
CPU time 0.96 seconds
Started Jul 26 05:15:12 PM PDT 24
Finished Jul 26 05:15:13 PM PDT 24
Peak memory 207124 kb
Host smart-2b819272-3b09-4b48-8ac5-b8d2ad2b1fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40837
80721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.4083780721
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.1663884710
Short name T685
Test name
Test status
Simulation time 165760056 ps
CPU time 0.9 seconds
Started Jul 26 05:15:10 PM PDT 24
Finished Jul 26 05:15:11 PM PDT 24
Peak memory 207156 kb
Host smart-1e95d401-41a6-4c4e-9b92-bbff17c6c71e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16638
84710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.1663884710
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.3357639492
Short name T2362
Test name
Test status
Simulation time 211809295 ps
CPU time 0.9 seconds
Started Jul 26 05:15:11 PM PDT 24
Finished Jul 26 05:15:12 PM PDT 24
Peak memory 207088 kb
Host smart-3481234d-2c79-460e-b7a8-fc5387d6d8ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33576
39492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.3357639492
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.1148979694
Short name T2121
Test name
Test status
Simulation time 154220950 ps
CPU time 0.91 seconds
Started Jul 26 05:15:12 PM PDT 24
Finished Jul 26 05:15:14 PM PDT 24
Peak memory 207092 kb
Host smart-5d23246a-826d-4ebc-b15d-3b4c7e94416c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11489
79694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.1148979694
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.1755043193
Short name T1529
Test name
Test status
Simulation time 154551645 ps
CPU time 0.89 seconds
Started Jul 26 05:15:06 PM PDT 24
Finished Jul 26 05:15:07 PM PDT 24
Peak memory 207084 kb
Host smart-c3e8d4cf-efeb-4464-a016-738d250c58c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17550
43193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.1755043193
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.3387193670
Short name T551
Test name
Test status
Simulation time 211033444 ps
CPU time 1.02 seconds
Started Jul 26 05:15:07 PM PDT 24
Finished Jul 26 05:15:08 PM PDT 24
Peak memory 207024 kb
Host smart-4469b908-e424-49ca-8122-6b37406080c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33871
93670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.3387193670
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.1244362409
Short name T837
Test name
Test status
Simulation time 3896646468 ps
CPU time 113.44 seconds
Started Jul 26 05:15:11 PM PDT 24
Finished Jul 26 05:17:05 PM PDT 24
Peak memory 215568 kb
Host smart-460bc1b9-e3a8-4244-ace7-aa4e3325dcb3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1244362409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.1244362409
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.647801323
Short name T2829
Test name
Test status
Simulation time 213314005 ps
CPU time 0.95 seconds
Started Jul 26 05:15:07 PM PDT 24
Finished Jul 26 05:15:08 PM PDT 24
Peak memory 207088 kb
Host smart-59066e08-f9ec-4588-9e26-450486ef4ee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64780
1323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.647801323
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.306363558
Short name T1386
Test name
Test status
Simulation time 160321717 ps
CPU time 0.86 seconds
Started Jul 26 05:15:12 PM PDT 24
Finished Jul 26 05:15:13 PM PDT 24
Peak memory 206976 kb
Host smart-82b684cd-2b94-43ee-94d5-f79770040a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30636
3558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.306363558
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.210434323
Short name T2560
Test name
Test status
Simulation time 665237232 ps
CPU time 1.95 seconds
Started Jul 26 05:15:10 PM PDT 24
Finished Jul 26 05:15:12 PM PDT 24
Peak memory 207072 kb
Host smart-5d7fc06c-5a4b-4884-b7b7-4cc0c956ba49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21043
4323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.210434323
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.1033437076
Short name T2105
Test name
Test status
Simulation time 7622877966 ps
CPU time 213.38 seconds
Started Jul 26 05:15:15 PM PDT 24
Finished Jul 26 05:18:48 PM PDT 24
Peak memory 215508 kb
Host smart-da6e579d-3a6a-4f73-9fa7-26da67c83f7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10334
37076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.1033437076
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_timeout_missing_host_handshake.2731670453
Short name T1479
Test name
Test status
Simulation time 721802320 ps
CPU time 15.1 seconds
Started Jul 26 05:14:56 PM PDT 24
Finished Jul 26 05:15:12 PM PDT 24
Peak memory 207308 kb
Host smart-591f7437-f2ed-446a-821a-b703ab14414e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731670453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_timeout_missing_hos
t_handshake.2731670453
Directory /workspace/45.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.3662972659
Short name T2353
Test name
Test status
Simulation time 44601003 ps
CPU time 0.71 seconds
Started Jul 26 05:15:17 PM PDT 24
Finished Jul 26 05:15:18 PM PDT 24
Peak memory 206936 kb
Host smart-bef94ff0-58fe-4d27-a727-de2136a08ca9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3662972659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.3662972659
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.3810187403
Short name T607
Test name
Test status
Simulation time 3422417592 ps
CPU time 5.74 seconds
Started Jul 26 05:15:08 PM PDT 24
Finished Jul 26 05:15:13 PM PDT 24
Peak memory 207220 kb
Host smart-adf87fbc-f412-454f-a9bb-516e48a8695d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810187403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_a
on_wake_disconnect.3810187403
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.1550574135
Short name T822
Test name
Test status
Simulation time 13347934853 ps
CPU time 16.2 seconds
Started Jul 26 05:15:16 PM PDT 24
Finished Jul 26 05:15:32 PM PDT 24
Peak memory 207596 kb
Host smart-9e4ddb79-2601-4df4-b227-4756a45646ec
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550574135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.1550574135
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.3664601127
Short name T2813
Test name
Test status
Simulation time 23475666178 ps
CPU time 27.88 seconds
Started Jul 26 05:15:12 PM PDT 24
Finished Jul 26 05:15:40 PM PDT 24
Peak memory 207364 kb
Host smart-783ef773-740b-4b80-83fd-1c3a7e522b37
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664601127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_a
on_wake_resume.3664601127
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.588131365
Short name T1936
Test name
Test status
Simulation time 206765283 ps
CPU time 0.92 seconds
Started Jul 26 05:15:11 PM PDT 24
Finished Jul 26 05:15:12 PM PDT 24
Peak memory 207208 kb
Host smart-476802ce-67be-4366-8fca-68a62ac20e22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58813
1365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.588131365
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.3418199072
Short name T815
Test name
Test status
Simulation time 157449391 ps
CPU time 0.86 seconds
Started Jul 26 05:15:14 PM PDT 24
Finished Jul 26 05:15:15 PM PDT 24
Peak memory 207092 kb
Host smart-666f6768-c963-48ce-9846-d3e5ad80641c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34181
99072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.3418199072
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.735094703
Short name T1259
Test name
Test status
Simulation time 300363859 ps
CPU time 1.14 seconds
Started Jul 26 05:15:07 PM PDT 24
Finished Jul 26 05:15:08 PM PDT 24
Peak memory 207092 kb
Host smart-26aa05d9-d695-48e7-ac75-e7be6b709c56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73509
4703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.735094703
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.1966182520
Short name T765
Test name
Test status
Simulation time 406916245 ps
CPU time 1.29 seconds
Started Jul 26 05:15:09 PM PDT 24
Finished Jul 26 05:15:11 PM PDT 24
Peak memory 207132 kb
Host smart-fc64940a-c3cf-4834-990a-efdd8ec555d0
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1966182520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.1966182520
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.3404298190
Short name T1058
Test name
Test status
Simulation time 10876782359 ps
CPU time 25.57 seconds
Started Jul 26 05:15:08 PM PDT 24
Finished Jul 26 05:15:34 PM PDT 24
Peak memory 207296 kb
Host smart-d70ab02e-3390-412b-beb8-42034fc1f59e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34042
98190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.3404298190
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_device_timeout.382013868
Short name T842
Test name
Test status
Simulation time 3367717887 ps
CPU time 29.66 seconds
Started Jul 26 05:15:09 PM PDT 24
Finished Jul 26 05:15:39 PM PDT 24
Peak memory 207412 kb
Host smart-51b74f31-f22b-4d46-8e9d-2b3cab9df6aa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382013868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_timeout.382013868
Directory /workspace/46.usbdev_device_timeout/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.229103820
Short name T594
Test name
Test status
Simulation time 406986327 ps
CPU time 1.55 seconds
Started Jul 26 05:15:11 PM PDT 24
Finished Jul 26 05:15:13 PM PDT 24
Peak memory 207096 kb
Host smart-7e6e9053-00d6-42b8-b0c2-05443031bc6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22910
3820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.229103820
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.3763263580
Short name T42
Test name
Test status
Simulation time 138798709 ps
CPU time 0.81 seconds
Started Jul 26 05:15:11 PM PDT 24
Finished Jul 26 05:15:12 PM PDT 24
Peak memory 207100 kb
Host smart-3ee4fb93-33a3-467c-a987-ee678a7f1269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37632
63580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.3763263580
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.2569048804
Short name T1833
Test name
Test status
Simulation time 40432478 ps
CPU time 0.68 seconds
Started Jul 26 05:15:06 PM PDT 24
Finished Jul 26 05:15:07 PM PDT 24
Peak memory 207024 kb
Host smart-a156a97f-45a2-4d67-9244-6532c0c8192e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25690
48804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.2569048804
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.2752696784
Short name T2839
Test name
Test status
Simulation time 939015725 ps
CPU time 2.65 seconds
Started Jul 26 05:15:10 PM PDT 24
Finished Jul 26 05:15:13 PM PDT 24
Peak memory 207156 kb
Host smart-50a6d812-e234-414b-adce-076127a608d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27526
96784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.2752696784
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.4227481443
Short name T2737
Test name
Test status
Simulation time 291755671 ps
CPU time 2.03 seconds
Started Jul 26 05:15:12 PM PDT 24
Finished Jul 26 05:15:14 PM PDT 24
Peak memory 207176 kb
Host smart-414bb4ed-737f-4d79-acb9-eb7cd2c5a35a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42274
81443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.4227481443
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.3118835276
Short name T1972
Test name
Test status
Simulation time 200830432 ps
CPU time 1.09 seconds
Started Jul 26 05:15:10 PM PDT 24
Finished Jul 26 05:15:12 PM PDT 24
Peak memory 215436 kb
Host smart-7c2b6e20-02e8-486e-b0c3-ae5d202dea72
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3118835276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.3118835276
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.3490846954
Short name T91
Test name
Test status
Simulation time 205263132 ps
CPU time 0.9 seconds
Started Jul 26 05:15:08 PM PDT 24
Finished Jul 26 05:15:09 PM PDT 24
Peak memory 207064 kb
Host smart-54fa60ac-afcc-4b47-976e-c362b43057dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34908
46954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.3490846954
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.4209987688
Short name T2238
Test name
Test status
Simulation time 171792989 ps
CPU time 0.89 seconds
Started Jul 26 05:15:09 PM PDT 24
Finished Jul 26 05:15:10 PM PDT 24
Peak memory 206976 kb
Host smart-e472ca6a-6ef0-4c01-a65e-8095c894027a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42099
87688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.4209987688
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_invalid_sync.3152054057
Short name T2075
Test name
Test status
Simulation time 6858680787 ps
CPU time 57.28 seconds
Started Jul 26 05:15:08 PM PDT 24
Finished Jul 26 05:16:06 PM PDT 24
Peak memory 216724 kb
Host smart-657d7687-594b-4519-aa73-8875c9af5b29
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3152054057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.3152054057
Directory /workspace/46.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/46.usbdev_iso_retraction.1796632576
Short name T1405
Test name
Test status
Simulation time 4158617343 ps
CPU time 54.78 seconds
Started Jul 26 05:15:11 PM PDT 24
Finished Jul 26 05:16:06 PM PDT 24
Peak memory 207420 kb
Host smart-dbbc2e8b-a49f-4867-bdf2-d787ce1aa0b5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1796632576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.1796632576
Directory /workspace/46.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.3288114123
Short name T1387
Test name
Test status
Simulation time 229585212 ps
CPU time 0.99 seconds
Started Jul 26 05:15:09 PM PDT 24
Finished Jul 26 05:15:10 PM PDT 24
Peak memory 207044 kb
Host smart-48d74540-fbe3-47db-bf6c-d0895be7a285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32881
14123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.3288114123
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.640474785
Short name T2848
Test name
Test status
Simulation time 23325811643 ps
CPU time 28.44 seconds
Started Jul 26 05:15:12 PM PDT 24
Finished Jul 26 05:15:41 PM PDT 24
Peak memory 207340 kb
Host smart-62540a6f-b7e7-47b2-bf6d-a5840decded4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64047
4785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.640474785
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.1480167772
Short name T2719
Test name
Test status
Simulation time 3281917940 ps
CPU time 4.89 seconds
Started Jul 26 05:15:06 PM PDT 24
Finished Jul 26 05:15:11 PM PDT 24
Peak memory 207180 kb
Host smart-f3b62df5-6d39-482a-9952-364d3bce4675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14801
67772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.1480167772
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.297113076
Short name T2455
Test name
Test status
Simulation time 5731738392 ps
CPU time 171.49 seconds
Started Jul 26 05:15:10 PM PDT 24
Finished Jul 26 05:18:02 PM PDT 24
Peak memory 215496 kb
Host smart-eafb286b-f947-4aa7-a550-ce77d8d066b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29711
3076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.297113076
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.135141593
Short name T825
Test name
Test status
Simulation time 4984926393 ps
CPU time 53.1 seconds
Started Jul 26 05:15:13 PM PDT 24
Finished Jul 26 05:16:07 PM PDT 24
Peak memory 216800 kb
Host smart-0dbfdb9a-4447-4944-9aed-34a84f1f44f8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=135141593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.135141593
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.228818898
Short name T958
Test name
Test status
Simulation time 246037638 ps
CPU time 1.09 seconds
Started Jul 26 05:15:14 PM PDT 24
Finished Jul 26 05:15:15 PM PDT 24
Peak memory 207088 kb
Host smart-56bed0b2-01e7-4808-a73a-d36ca4c37727
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=228818898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.228818898
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.2882198474
Short name T1932
Test name
Test status
Simulation time 252665217 ps
CPU time 1.12 seconds
Started Jul 26 05:15:13 PM PDT 24
Finished Jul 26 05:15:15 PM PDT 24
Peak memory 207104 kb
Host smart-d1ac42f3-cd7a-4c08-9167-36f07a63997d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28821
98474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.2882198474
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.1850185066
Short name T545
Test name
Test status
Simulation time 4202126085 ps
CPU time 121.53 seconds
Started Jul 26 05:15:09 PM PDT 24
Finished Jul 26 05:17:11 PM PDT 24
Peak memory 215564 kb
Host smart-7ed069a8-355a-4014-a96e-712770a3dfee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18501
85066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.1850185066
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.2376909518
Short name T2481
Test name
Test status
Simulation time 4898442961 ps
CPU time 144.92 seconds
Started Jul 26 05:15:16 PM PDT 24
Finished Jul 26 05:17:41 PM PDT 24
Peak memory 215824 kb
Host smart-2db75d17-0523-4137-bf54-66880fe304c7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2376909518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.2376909518
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.2909108477
Short name T707
Test name
Test status
Simulation time 210252283 ps
CPU time 0.94 seconds
Started Jul 26 05:15:10 PM PDT 24
Finished Jul 26 05:15:11 PM PDT 24
Peak memory 206984 kb
Host smart-b90da3d2-5111-4fc4-bdb2-f57ab7da44e5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2909108477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.2909108477
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.2824730604
Short name T2471
Test name
Test status
Simulation time 148209285 ps
CPU time 0.91 seconds
Started Jul 26 05:15:13 PM PDT 24
Finished Jul 26 05:15:15 PM PDT 24
Peak memory 206972 kb
Host smart-a0738b60-edd5-4f40-a8a1-3e24614f2c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28247
30604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.2824730604
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.1893025163
Short name T2844
Test name
Test status
Simulation time 219679586 ps
CPU time 0.93 seconds
Started Jul 26 05:15:12 PM PDT 24
Finished Jul 26 05:15:14 PM PDT 24
Peak memory 207076 kb
Host smart-78e4995c-0056-4604-b7b7-dd6a6f674905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18930
25163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.1893025163
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.3328053676
Short name T1898
Test name
Test status
Simulation time 186143203 ps
CPU time 0.94 seconds
Started Jul 26 05:15:09 PM PDT 24
Finished Jul 26 05:15:10 PM PDT 24
Peak memory 207020 kb
Host smart-f0796569-29ba-4bf5-8a16-5001decee268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33280
53676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.3328053676
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.3980629553
Short name T2207
Test name
Test status
Simulation time 164685728 ps
CPU time 0.87 seconds
Started Jul 26 05:15:10 PM PDT 24
Finished Jul 26 05:15:11 PM PDT 24
Peak memory 207048 kb
Host smart-59039af6-9952-42da-83ab-e73aac57cfd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39806
29553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.3980629553
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.1507143620
Short name T1860
Test name
Test status
Simulation time 207342572 ps
CPU time 0.96 seconds
Started Jul 26 05:15:16 PM PDT 24
Finished Jul 26 05:15:17 PM PDT 24
Peak memory 207332 kb
Host smart-bb35fe7a-1e81-413c-8882-d391978b9f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15071
43620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.1507143620
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.1032422555
Short name T1782
Test name
Test status
Simulation time 150515328 ps
CPU time 0.87 seconds
Started Jul 26 05:15:08 PM PDT 24
Finished Jul 26 05:15:09 PM PDT 24
Peak memory 207080 kb
Host smart-0217bc97-336f-4649-b184-a95eb9876ad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10324
22555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.1032422555
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.1019924700
Short name T2039
Test name
Test status
Simulation time 222641142 ps
CPU time 0.97 seconds
Started Jul 26 05:15:13 PM PDT 24
Finished Jul 26 05:15:14 PM PDT 24
Peak memory 207100 kb
Host smart-b6524979-5848-4651-a720-c16b0f4acb06
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1019924700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.1019924700
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.1197929625
Short name T2317
Test name
Test status
Simulation time 145107162 ps
CPU time 0.81 seconds
Started Jul 26 05:15:13 PM PDT 24
Finished Jul 26 05:15:14 PM PDT 24
Peak memory 207028 kb
Host smart-4efe9cec-cec1-408a-9ae1-9de85bfc3509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11979
29625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.1197929625
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.872174244
Short name T39
Test name
Test status
Simulation time 32313758 ps
CPU time 0.7 seconds
Started Jul 26 05:15:13 PM PDT 24
Finished Jul 26 05:15:14 PM PDT 24
Peak memory 207088 kb
Host smart-eda1c078-bd9b-4f60-8e90-81dfd9c0082e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87217
4244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.872174244
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.1397469404
Short name T610
Test name
Test status
Simulation time 20855392867 ps
CPU time 54.46 seconds
Started Jul 26 05:15:13 PM PDT 24
Finished Jul 26 05:16:07 PM PDT 24
Peak memory 223692 kb
Host smart-11a5db7f-277e-416a-9306-d40c1b9f639d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13974
69404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.1397469404
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.3766428327
Short name T2216
Test name
Test status
Simulation time 187555191 ps
CPU time 1.06 seconds
Started Jul 26 05:15:11 PM PDT 24
Finished Jul 26 05:15:12 PM PDT 24
Peak memory 207084 kb
Host smart-1158dc52-ac33-447a-8842-e0334638b471
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37664
28327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.3766428327
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.1204090160
Short name T2460
Test name
Test status
Simulation time 235531623 ps
CPU time 0.99 seconds
Started Jul 26 05:15:09 PM PDT 24
Finished Jul 26 05:15:10 PM PDT 24
Peak memory 206916 kb
Host smart-1ec770c9-ae09-4abb-95ed-d6c19adfc1c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12040
90160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.1204090160
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.1255306440
Short name T1069
Test name
Test status
Simulation time 239378230 ps
CPU time 0.98 seconds
Started Jul 26 05:15:13 PM PDT 24
Finished Jul 26 05:15:14 PM PDT 24
Peak memory 207076 kb
Host smart-ab9bb14d-6e63-4379-bf33-687e898c9f31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12553
06440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.1255306440
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.1481169256
Short name T1694
Test name
Test status
Simulation time 191999688 ps
CPU time 1.03 seconds
Started Jul 26 05:15:13 PM PDT 24
Finished Jul 26 05:15:14 PM PDT 24
Peak memory 207060 kb
Host smart-d312cbd4-2e5f-48fe-a236-d66404c1e999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14811
69256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.1481169256
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.2609187721
Short name T1487
Test name
Test status
Simulation time 186578974 ps
CPU time 0.9 seconds
Started Jul 26 05:15:12 PM PDT 24
Finished Jul 26 05:15:13 PM PDT 24
Peak memory 207020 kb
Host smart-508927d6-7acc-4d21-a151-103f702c8755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26091
87721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.2609187721
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.3366317235
Short name T1034
Test name
Test status
Simulation time 149941276 ps
CPU time 0.86 seconds
Started Jul 26 05:15:13 PM PDT 24
Finished Jul 26 05:15:14 PM PDT 24
Peak memory 207032 kb
Host smart-ab8b35d8-0242-42aa-8049-ba272ac776b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33663
17235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.3366317235
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.2504447699
Short name T89
Test name
Test status
Simulation time 147237796 ps
CPU time 0.86 seconds
Started Jul 26 05:15:10 PM PDT 24
Finished Jul 26 05:15:11 PM PDT 24
Peak memory 206992 kb
Host smart-2829ca61-9672-482d-94c0-94e0a4745390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25044
47699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.2504447699
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.850779620
Short name T1014
Test name
Test status
Simulation time 237910906 ps
CPU time 1 seconds
Started Jul 26 05:15:13 PM PDT 24
Finished Jul 26 05:15:15 PM PDT 24
Peak memory 207048 kb
Host smart-6ab78a31-1a4a-4c06-bc5e-c0751400c0fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85077
9620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.850779620
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.2150979571
Short name T516
Test name
Test status
Simulation time 4330124978 ps
CPU time 130.52 seconds
Started Jul 26 05:15:13 PM PDT 24
Finished Jul 26 05:17:24 PM PDT 24
Peak memory 215512 kb
Host smart-0c8f567f-ae0e-405e-9c63-a46ebe656738
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2150979571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.2150979571
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.203092906
Short name T690
Test name
Test status
Simulation time 155300166 ps
CPU time 0.86 seconds
Started Jul 26 05:15:11 PM PDT 24
Finished Jul 26 05:15:12 PM PDT 24
Peak memory 207128 kb
Host smart-65fc0df5-bc27-4b17-8c42-c462e5e35cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20309
2906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.203092906
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.1424859059
Short name T2840
Test name
Test status
Simulation time 166254757 ps
CPU time 0.87 seconds
Started Jul 26 05:15:13 PM PDT 24
Finished Jul 26 05:15:15 PM PDT 24
Peak memory 206976 kb
Host smart-1d872693-36d2-4267-a3e7-d55e66baf22c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14248
59059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.1424859059
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.3213670609
Short name T1903
Test name
Test status
Simulation time 1053157358 ps
CPU time 2.66 seconds
Started Jul 26 05:15:17 PM PDT 24
Finished Jul 26 05:15:20 PM PDT 24
Peak memory 207032 kb
Host smart-6bdb9dbc-a388-479f-bdea-dd7cc2462d18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32136
70609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.3213670609
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.507084990
Short name T1832
Test name
Test status
Simulation time 5222494854 ps
CPU time 152.7 seconds
Started Jul 26 05:15:17 PM PDT 24
Finished Jul 26 05:17:50 PM PDT 24
Peak memory 215532 kb
Host smart-fa5494eb-0ca2-47ca-9735-dbf2d7bc67c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50708
4990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.507084990
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_timeout_missing_host_handshake.4213846304
Short name T1398
Test name
Test status
Simulation time 2208293735 ps
CPU time 15.12 seconds
Started Jul 26 05:15:10 PM PDT 24
Finished Jul 26 05:15:25 PM PDT 24
Peak memory 207284 kb
Host smart-5e05d474-85c9-4bee-ae5f-90a931c9c763
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213846304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_timeout_missing_hos
t_handshake.4213846304
Directory /workspace/46.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.3076718198
Short name T1577
Test name
Test status
Simulation time 34354900 ps
CPU time 0.66 seconds
Started Jul 26 05:15:20 PM PDT 24
Finished Jul 26 05:15:21 PM PDT 24
Peak memory 207116 kb
Host smart-54628761-3ea2-40ae-b223-d7e61daa3186
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3076718198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.3076718198
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.124203418
Short name T1495
Test name
Test status
Simulation time 4435909119 ps
CPU time 7.19 seconds
Started Jul 26 05:15:13 PM PDT 24
Finished Jul 26 05:15:20 PM PDT 24
Peak memory 207360 kb
Host smart-5717e0c2-0ae5-40aa-b18a-3d18a30bce1b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124203418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_ao
n_wake_disconnect.124203418
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.87043759
Short name T7
Test name
Test status
Simulation time 13402345124 ps
CPU time 16.89 seconds
Started Jul 26 05:15:14 PM PDT 24
Finished Jul 26 05:15:31 PM PDT 24
Peak memory 207368 kb
Host smart-58a1dfd1-8d82-4c50-b739-e7388bfbb4d4
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=87043759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.87043759
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.3331133805
Short name T462
Test name
Test status
Simulation time 23314183253 ps
CPU time 30.49 seconds
Started Jul 26 05:15:17 PM PDT 24
Finished Jul 26 05:15:48 PM PDT 24
Peak memory 207388 kb
Host smart-bfb35b41-3c20-40d8-8f2b-afee0a4f6abb
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331133805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_a
on_wake_resume.3331133805
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.1382742392
Short name T1681
Test name
Test status
Simulation time 157529153 ps
CPU time 0.85 seconds
Started Jul 26 05:15:13 PM PDT 24
Finished Jul 26 05:15:15 PM PDT 24
Peak memory 206976 kb
Host smart-f9ae5638-951c-4f59-8c66-765096c23508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13827
42392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.1382742392
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.3032169047
Short name T2622
Test name
Test status
Simulation time 163977316 ps
CPU time 0.87 seconds
Started Jul 26 05:15:13 PM PDT 24
Finished Jul 26 05:15:14 PM PDT 24
Peak memory 207032 kb
Host smart-0392caf9-52b2-45e3-8892-fca0215e5751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30321
69047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.3032169047
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.785086201
Short name T1220
Test name
Test status
Simulation time 267599668 ps
CPU time 1.15 seconds
Started Jul 26 05:15:17 PM PDT 24
Finished Jul 26 05:15:19 PM PDT 24
Peak memory 207128 kb
Host smart-08796715-c45d-4974-87ac-b36d8fa78873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78508
6201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.785086201
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.3137026283
Short name T1317
Test name
Test status
Simulation time 334138242 ps
CPU time 1.19 seconds
Started Jul 26 05:15:12 PM PDT 24
Finished Jul 26 05:15:14 PM PDT 24
Peak memory 207024 kb
Host smart-4de61018-94a7-406a-8c66-73cdaa0a08ac
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3137026283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.3137026283
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.921786729
Short name T2635
Test name
Test status
Simulation time 6161380814 ps
CPU time 12.88 seconds
Started Jul 26 05:15:12 PM PDT 24
Finished Jul 26 05:15:25 PM PDT 24
Peak memory 207316 kb
Host smart-10bd12df-d1da-456a-a124-1b286ac8e8b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92178
6729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.921786729
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_device_timeout.68418737
Short name T977
Test name
Test status
Simulation time 878988900 ps
CPU time 19.37 seconds
Started Jul 26 05:15:17 PM PDT 24
Finished Jul 26 05:15:37 PM PDT 24
Peak memory 207352 kb
Host smart-c126cbcf-c735-48a8-b387-fc75e4e003d8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68418737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_timeout.68418737
Directory /workspace/47.usbdev_device_timeout/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.4053643613
Short name T891
Test name
Test status
Simulation time 391686566 ps
CPU time 1.35 seconds
Started Jul 26 05:15:19 PM PDT 24
Finished Jul 26 05:15:20 PM PDT 24
Peak memory 207016 kb
Host smart-54ef5ace-cfea-43d8-a877-fa2174548c99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40536
43613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.4053643613
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.1328265556
Short name T1515
Test name
Test status
Simulation time 182930472 ps
CPU time 0.83 seconds
Started Jul 26 05:15:12 PM PDT 24
Finished Jul 26 05:15:13 PM PDT 24
Peak memory 207100 kb
Host smart-a1d726af-74ae-4c36-ba2e-f9c475ba755e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13282
65556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.1328265556
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.3861264923
Short name T2450
Test name
Test status
Simulation time 54333508 ps
CPU time 0.7 seconds
Started Jul 26 05:15:17 PM PDT 24
Finished Jul 26 05:15:18 PM PDT 24
Peak memory 207064 kb
Host smart-4a5f1cb8-58d8-4935-a4d1-5cd9cbc213ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38612
64923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.3861264923
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.22491114
Short name T980
Test name
Test status
Simulation time 739605569 ps
CPU time 2.21 seconds
Started Jul 26 05:15:18 PM PDT 24
Finished Jul 26 05:15:20 PM PDT 24
Peak memory 207332 kb
Host smart-840a6fc4-9fcb-4c2a-a02e-184aefe3c4fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22491
114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.22491114
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.3115370446
Short name T176
Test name
Test status
Simulation time 196756145 ps
CPU time 1.5 seconds
Started Jul 26 05:15:17 PM PDT 24
Finished Jul 26 05:15:18 PM PDT 24
Peak memory 207060 kb
Host smart-cf763ba2-9013-4607-97d7-715e5fb9ed76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31153
70446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.3115370446
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.2538465973
Short name T1453
Test name
Test status
Simulation time 172018470 ps
CPU time 0.92 seconds
Started Jul 26 05:15:18 PM PDT 24
Finished Jul 26 05:15:19 PM PDT 24
Peak memory 207120 kb
Host smart-21d0a2a4-e4c0-4c5c-b54a-9fbd64ad0008
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2538465973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.2538465973
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.2679669792
Short name T2061
Test name
Test status
Simulation time 148152849 ps
CPU time 0.89 seconds
Started Jul 26 05:15:17 PM PDT 24
Finished Jul 26 05:15:18 PM PDT 24
Peak memory 206840 kb
Host smart-98db941f-fdb3-48f5-a32a-fc0b96a9fb68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26796
69792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.2679669792
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.2375582758
Short name T429
Test name
Test status
Simulation time 164544048 ps
CPU time 0.89 seconds
Started Jul 26 05:15:15 PM PDT 24
Finished Jul 26 05:15:16 PM PDT 24
Peak memory 207212 kb
Host smart-260a1fdb-17d1-4252-a178-5fa9ac18df08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23755
82758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.2375582758
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.2054469667
Short name T2852
Test name
Test status
Simulation time 7059412423 ps
CPU time 53.85 seconds
Started Jul 26 05:15:16 PM PDT 24
Finished Jul 26 05:16:10 PM PDT 24
Peak memory 217180 kb
Host smart-02f1252f-fb5c-45ea-a7a3-b507ed65c3f3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2054469667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.2054469667
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_iso_retraction.2256449098
Short name T2294
Test name
Test status
Simulation time 4398600467 ps
CPU time 52.01 seconds
Started Jul 26 05:15:17 PM PDT 24
Finished Jul 26 05:16:09 PM PDT 24
Peak memory 207344 kb
Host smart-0b9ab366-efac-48cd-b1ea-353879a80f95
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2256449098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.2256449098
Directory /workspace/47.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.3288216643
Short name T675
Test name
Test status
Simulation time 230669727 ps
CPU time 0.97 seconds
Started Jul 26 05:15:19 PM PDT 24
Finished Jul 26 05:15:20 PM PDT 24
Peak memory 207024 kb
Host smart-a6fb1511-ffc3-4082-a208-fdb73dcff787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32882
16643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.3288216643
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.4279751100
Short name T1096
Test name
Test status
Simulation time 23341548560 ps
CPU time 28.14 seconds
Started Jul 26 05:15:19 PM PDT 24
Finished Jul 26 05:15:47 PM PDT 24
Peak memory 207376 kb
Host smart-9ac09ef4-53c5-4aaa-8c95-64f31077ef45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42797
51100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.4279751100
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.583586565
Short name T2173
Test name
Test status
Simulation time 3372572771 ps
CPU time 4.9 seconds
Started Jul 26 05:15:28 PM PDT 24
Finished Jul 26 05:15:33 PM PDT 24
Peak memory 207320 kb
Host smart-ce2c48d8-4cea-4d5d-937c-ddb260dbff49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58358
6565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.583586565
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.2204001476
Short name T1185
Test name
Test status
Simulation time 5425275650 ps
CPU time 40.7 seconds
Started Jul 26 05:15:28 PM PDT 24
Finished Jul 26 05:16:09 PM PDT 24
Peak memory 223648 kb
Host smart-3dc080ec-0779-4578-a076-2d21de71d985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22040
01476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.2204001476
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.2930341667
Short name T1070
Test name
Test status
Simulation time 4547788621 ps
CPU time 35.9 seconds
Started Jul 26 05:15:23 PM PDT 24
Finished Jul 26 05:15:59 PM PDT 24
Peak memory 217024 kb
Host smart-4ee82acd-c3e2-4942-852d-caa6b02fbf85
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2930341667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.2930341667
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.3469002125
Short name T1269
Test name
Test status
Simulation time 251176705 ps
CPU time 1.08 seconds
Started Jul 26 05:15:32 PM PDT 24
Finished Jul 26 05:15:34 PM PDT 24
Peak memory 207128 kb
Host smart-885537b8-0676-4988-be91-f83ddcb020ef
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3469002125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.3469002125
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.997081889
Short name T2581
Test name
Test status
Simulation time 192733582 ps
CPU time 0.93 seconds
Started Jul 26 05:15:27 PM PDT 24
Finished Jul 26 05:15:28 PM PDT 24
Peak memory 207100 kb
Host smart-591a31a5-ae5e-47ff-85cc-f013a23c38e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99708
1889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.997081889
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.691898783
Short name T2726
Test name
Test status
Simulation time 4358765779 ps
CPU time 122.39 seconds
Started Jul 26 05:15:26 PM PDT 24
Finished Jul 26 05:17:28 PM PDT 24
Peak memory 215496 kb
Host smart-2a4f7e4e-ac37-4e77-81d4-9c096611f506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69189
8783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.691898783
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.3588860605
Short name T2312
Test name
Test status
Simulation time 4746521303 ps
CPU time 50.48 seconds
Started Jul 26 05:15:21 PM PDT 24
Finished Jul 26 05:16:12 PM PDT 24
Peak memory 207260 kb
Host smart-9f634ae2-4154-4e71-bfb3-9baaf433997f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3588860605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.3588860605
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.3853375836
Short name T1502
Test name
Test status
Simulation time 181457991 ps
CPU time 0.9 seconds
Started Jul 26 05:15:23 PM PDT 24
Finished Jul 26 05:15:25 PM PDT 24
Peak memory 207108 kb
Host smart-1546828d-0025-4b0d-8a07-7b6fd8879099
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3853375836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.3853375836
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.557902789
Short name T2245
Test name
Test status
Simulation time 147443555 ps
CPU time 0.85 seconds
Started Jul 26 05:15:20 PM PDT 24
Finished Jul 26 05:15:21 PM PDT 24
Peak memory 207124 kb
Host smart-7aaf8aba-a796-43ac-902d-4103127ec6fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55790
2789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.557902789
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.1586439684
Short name T2550
Test name
Test status
Simulation time 211860215 ps
CPU time 0.99 seconds
Started Jul 26 05:15:25 PM PDT 24
Finished Jul 26 05:15:26 PM PDT 24
Peak memory 207012 kb
Host smart-0c100ad8-e21f-4ef7-b39c-d55c8f88ca08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15864
39684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.1586439684
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.3250944533
Short name T1212
Test name
Test status
Simulation time 160867990 ps
CPU time 0.89 seconds
Started Jul 26 05:15:28 PM PDT 24
Finished Jul 26 05:15:29 PM PDT 24
Peak memory 207052 kb
Host smart-4775b380-7260-48fe-a974-a9320e291eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32509
44533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.3250944533
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.4046105806
Short name T917
Test name
Test status
Simulation time 202488524 ps
CPU time 0.94 seconds
Started Jul 26 05:15:23 PM PDT 24
Finished Jul 26 05:15:24 PM PDT 24
Peak memory 207120 kb
Host smart-ecf21136-c870-46fb-8c96-ea8b15d1f352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40461
05806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.4046105806
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.143729811
Short name T771
Test name
Test status
Simulation time 179728048 ps
CPU time 0.84 seconds
Started Jul 26 05:15:17 PM PDT 24
Finished Jul 26 05:15:18 PM PDT 24
Peak memory 207132 kb
Host smart-ffa0d59f-96ea-41a4-9da3-4b7e2c5dd867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14372
9811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.143729811
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.2178423954
Short name T171
Test name
Test status
Simulation time 145916842 ps
CPU time 0.87 seconds
Started Jul 26 05:15:19 PM PDT 24
Finished Jul 26 05:15:20 PM PDT 24
Peak memory 207208 kb
Host smart-94c3550c-465d-4a5c-ac79-516fb55fe2d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21784
23954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.2178423954
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.3741379755
Short name T577
Test name
Test status
Simulation time 267609237 ps
CPU time 1.13 seconds
Started Jul 26 05:15:18 PM PDT 24
Finished Jul 26 05:15:19 PM PDT 24
Peak memory 207156 kb
Host smart-a8010044-c1ad-4f13-81f7-13f1555d6a70
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3741379755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.3741379755
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.2624243582
Short name T2253
Test name
Test status
Simulation time 140679019 ps
CPU time 0.89 seconds
Started Jul 26 05:15:28 PM PDT 24
Finished Jul 26 05:15:29 PM PDT 24
Peak memory 207012 kb
Host smart-db4dbcec-c929-4ed5-ab44-04beeae3505e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26242
43582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.2624243582
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.1813091376
Short name T1093
Test name
Test status
Simulation time 45894677 ps
CPU time 0.69 seconds
Started Jul 26 05:15:25 PM PDT 24
Finished Jul 26 05:15:26 PM PDT 24
Peak memory 207048 kb
Host smart-a3ef04eb-7375-4b50-b55b-6a94fe70e8b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18130
91376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.1813091376
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.3569019402
Short name T2501
Test name
Test status
Simulation time 19552161878 ps
CPU time 53.07 seconds
Started Jul 26 05:15:26 PM PDT 24
Finished Jul 26 05:16:20 PM PDT 24
Peak memory 215524 kb
Host smart-9127d9c2-f4ce-4ddf-a14f-9e7a0a9a9c48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35690
19402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.3569019402
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.3266298483
Short name T585
Test name
Test status
Simulation time 157855055 ps
CPU time 0.82 seconds
Started Jul 26 05:15:21 PM PDT 24
Finished Jul 26 05:15:21 PM PDT 24
Peak memory 206908 kb
Host smart-af98f7bb-6f73-4ecf-9846-8e72f99221b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32662
98483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.3266298483
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.1301038749
Short name T1778
Test name
Test status
Simulation time 180546315 ps
CPU time 0.9 seconds
Started Jul 26 05:15:21 PM PDT 24
Finished Jul 26 05:15:22 PM PDT 24
Peak memory 207012 kb
Host smart-b0a20945-7fba-45e5-801b-2dee16f5d846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13010
38749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.1301038749
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.938965813
Short name T1825
Test name
Test status
Simulation time 198000554 ps
CPU time 0.93 seconds
Started Jul 26 05:15:20 PM PDT 24
Finished Jul 26 05:15:21 PM PDT 24
Peak memory 207212 kb
Host smart-350cf159-7cdb-431c-ac75-7c35711635e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93896
5813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.938965813
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.582634098
Short name T2341
Test name
Test status
Simulation time 159396683 ps
CPU time 0.83 seconds
Started Jul 26 05:15:28 PM PDT 24
Finished Jul 26 05:15:29 PM PDT 24
Peak memory 207100 kb
Host smart-9d54b5d3-89a3-42bd-8048-0260dcf60acd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58263
4098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.582634098
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.3769407260
Short name T1582
Test name
Test status
Simulation time 166517541 ps
CPU time 0.85 seconds
Started Jul 26 05:15:26 PM PDT 24
Finished Jul 26 05:15:27 PM PDT 24
Peak memory 207096 kb
Host smart-c1c46e84-19e0-42e3-98eb-0f5038522dc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37694
07260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.3769407260
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.3488268816
Short name T1363
Test name
Test status
Simulation time 149738371 ps
CPU time 0.81 seconds
Started Jul 26 05:15:22 PM PDT 24
Finished Jul 26 05:15:22 PM PDT 24
Peak memory 207068 kb
Host smart-b571d45b-6148-4e4d-a1fc-e4737805231d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34882
68816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.3488268816
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.1717922524
Short name T625
Test name
Test status
Simulation time 155625286 ps
CPU time 0.87 seconds
Started Jul 26 05:15:28 PM PDT 24
Finished Jul 26 05:15:29 PM PDT 24
Peak memory 207096 kb
Host smart-b89e1d9c-adeb-495d-852b-27e847ccffd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17179
22524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.1717922524
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.2147100327
Short name T1896
Test name
Test status
Simulation time 224737099 ps
CPU time 1.01 seconds
Started Jul 26 05:15:20 PM PDT 24
Finished Jul 26 05:15:21 PM PDT 24
Peak memory 207024 kb
Host smart-ed867b04-8ca1-471b-8fd6-9210f8a39c91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21471
00327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.2147100327
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.3231682144
Short name T443
Test name
Test status
Simulation time 6695948742 ps
CPU time 70.09 seconds
Started Jul 26 05:15:20 PM PDT 24
Finished Jul 26 05:16:30 PM PDT 24
Peak memory 217056 kb
Host smart-a0aef994-3d03-4d04-886b-bc0b537411bc
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3231682144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.3231682144
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.4170008850
Short name T2059
Test name
Test status
Simulation time 165748129 ps
CPU time 0.92 seconds
Started Jul 26 05:15:21 PM PDT 24
Finished Jul 26 05:15:22 PM PDT 24
Peak memory 207064 kb
Host smart-d2c7c885-8c98-4fb5-8928-24f5d83b2e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41700
08850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.4170008850
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.3382640526
Short name T1411
Test name
Test status
Simulation time 228990732 ps
CPU time 0.94 seconds
Started Jul 26 05:15:17 PM PDT 24
Finished Jul 26 05:15:19 PM PDT 24
Peak memory 207132 kb
Host smart-1ed4d636-69ef-4a56-9b85-580b82ccb724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33826
40526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.3382640526
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.1136794920
Short name T2585
Test name
Test status
Simulation time 635297215 ps
CPU time 1.75 seconds
Started Jul 26 05:15:27 PM PDT 24
Finished Jul 26 05:15:29 PM PDT 24
Peak memory 207060 kb
Host smart-d4a26830-bb15-4393-9cf0-92901468871d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11367
94920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.1136794920
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.2255976936
Short name T2315
Test name
Test status
Simulation time 5801706312 ps
CPU time 155.76 seconds
Started Jul 26 05:15:18 PM PDT 24
Finished Jul 26 05:17:54 PM PDT 24
Peak memory 215560 kb
Host smart-301768c5-2d95-4364-bfbf-35e6e067bad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22559
76936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.2255976936
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_timeout_missing_host_handshake.2650040685
Short name T757
Test name
Test status
Simulation time 1063897874 ps
CPU time 23.78 seconds
Started Jul 26 05:15:14 PM PDT 24
Finished Jul 26 05:15:38 PM PDT 24
Peak memory 207324 kb
Host smart-a4f31026-317b-4bb1-b120-4de9a06b1e21
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650040685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_timeout_missing_hos
t_handshake.2650040685
Directory /workspace/47.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.3954032085
Short name T2079
Test name
Test status
Simulation time 33911267 ps
CPU time 0.64 seconds
Started Jul 26 05:15:36 PM PDT 24
Finished Jul 26 05:15:37 PM PDT 24
Peak memory 207156 kb
Host smart-67a28457-e0b0-4898-a72d-5df758b174aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3954032085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.3954032085
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.2471050610
Short name T1123
Test name
Test status
Simulation time 4389984178 ps
CPU time 6.18 seconds
Started Jul 26 05:15:27 PM PDT 24
Finished Jul 26 05:15:33 PM PDT 24
Peak memory 207324 kb
Host smart-763cbeab-dfa3-4b79-b91b-67584979b78e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471050610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_a
on_wake_disconnect.2471050610
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.646072353
Short name T9
Test name
Test status
Simulation time 13331579118 ps
CPU time 15.48 seconds
Started Jul 26 05:15:28 PM PDT 24
Finished Jul 26 05:15:44 PM PDT 24
Peak memory 207316 kb
Host smart-08b25b20-7a55-490d-b79d-0d59f68534eb
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=646072353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.646072353
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.145475425
Short name T2019
Test name
Test status
Simulation time 23338812160 ps
CPU time 31.23 seconds
Started Jul 26 05:15:24 PM PDT 24
Finished Jul 26 05:15:55 PM PDT 24
Peak memory 207364 kb
Host smart-08dbe221-ec7b-40ca-9a23-f963cd3c5da0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145475425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_ao
n_wake_resume.145475425
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.1697385390
Short name T1544
Test name
Test status
Simulation time 181112156 ps
CPU time 0.94 seconds
Started Jul 26 05:15:21 PM PDT 24
Finished Jul 26 05:15:22 PM PDT 24
Peak memory 207104 kb
Host smart-ccf82433-8b27-40a3-b4f2-6dfdbbd27507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16973
85390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.1697385390
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.73717152
Short name T492
Test name
Test status
Simulation time 156386527 ps
CPU time 0.87 seconds
Started Jul 26 05:15:22 PM PDT 24
Finished Jul 26 05:15:23 PM PDT 24
Peak memory 207084 kb
Host smart-6f25bac2-97f2-47bb-9f27-80c71bf77acd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73717
152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.73717152
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.1237485926
Short name T1030
Test name
Test status
Simulation time 242460870 ps
CPU time 1.15 seconds
Started Jul 26 05:15:28 PM PDT 24
Finished Jul 26 05:15:29 PM PDT 24
Peak memory 207108 kb
Host smart-0a13a70f-e4a2-4fdb-8fa0-ea558a8481f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12374
85926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.1237485926
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.2224628001
Short name T1879
Test name
Test status
Simulation time 334316480 ps
CPU time 1.13 seconds
Started Jul 26 05:15:28 PM PDT 24
Finished Jul 26 05:15:29 PM PDT 24
Peak memory 207104 kb
Host smart-aaa54f2f-d784-4247-86dd-c35bbb3d3b8e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2224628001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.2224628001
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.1225950857
Short name T158
Test name
Test status
Simulation time 7331191009 ps
CPU time 16.31 seconds
Started Jul 26 05:15:22 PM PDT 24
Finished Jul 26 05:15:38 PM PDT 24
Peak memory 207376 kb
Host smart-d8e34ec0-03bb-4614-9147-c20aaa32a89f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12259
50857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.1225950857
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_device_timeout.2715383122
Short name T2235
Test name
Test status
Simulation time 152934847 ps
CPU time 0.82 seconds
Started Jul 26 05:15:19 PM PDT 24
Finished Jul 26 05:15:20 PM PDT 24
Peak memory 207068 kb
Host smart-05f334c0-dfe3-4f2b-ace7-a9f96afdded6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715383122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_timeout.2715383122
Directory /workspace/48.usbdev_device_timeout/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.2683128564
Short name T867
Test name
Test status
Simulation time 401184373 ps
CPU time 1.34 seconds
Started Jul 26 05:15:26 PM PDT 24
Finished Jul 26 05:15:27 PM PDT 24
Peak memory 207048 kb
Host smart-48a0b999-83d8-436a-b0e4-d8755f9438ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26831
28564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.2683128564
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.676297994
Short name T2290
Test name
Test status
Simulation time 147535458 ps
CPU time 0.84 seconds
Started Jul 26 05:15:26 PM PDT 24
Finished Jul 26 05:15:27 PM PDT 24
Peak memory 206996 kb
Host smart-cb576216-229e-4e51-9b75-fdbb2b320556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67629
7994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.676297994
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.3365594051
Short name T2503
Test name
Test status
Simulation time 31240832 ps
CPU time 0.7 seconds
Started Jul 26 05:15:22 PM PDT 24
Finished Jul 26 05:15:23 PM PDT 24
Peak memory 207064 kb
Host smart-92fb1cd3-477d-4048-a88d-42fbfde4ac39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33655
94051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.3365594051
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.1146918678
Short name T2419
Test name
Test status
Simulation time 911094145 ps
CPU time 2.42 seconds
Started Jul 26 05:15:24 PM PDT 24
Finished Jul 26 05:15:26 PM PDT 24
Peak memory 207240 kb
Host smart-021f6de5-35f1-44eb-aad5-9730dbed2689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11469
18678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.1146918678
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.1572623810
Short name T550
Test name
Test status
Simulation time 162623101 ps
CPU time 1.89 seconds
Started Jul 26 05:15:21 PM PDT 24
Finished Jul 26 05:15:23 PM PDT 24
Peak memory 207192 kb
Host smart-67955783-9cab-4ebf-a625-96fd1b852942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15726
23810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.1572623810
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.3878365282
Short name T937
Test name
Test status
Simulation time 188051230 ps
CPU time 1.02 seconds
Started Jul 26 05:15:21 PM PDT 24
Finished Jul 26 05:15:22 PM PDT 24
Peak memory 207292 kb
Host smart-17d32180-7d1d-42f7-b188-3088a3249e1a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3878365282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.3878365282
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.848295077
Short name T2301
Test name
Test status
Simulation time 143332388 ps
CPU time 0.88 seconds
Started Jul 26 05:15:28 PM PDT 24
Finished Jul 26 05:15:29 PM PDT 24
Peak memory 207016 kb
Host smart-2888016c-b74a-466f-a49d-0086fb3e216c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84829
5077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.848295077
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.2302906037
Short name T1177
Test name
Test status
Simulation time 246754731 ps
CPU time 1.16 seconds
Started Jul 26 05:15:24 PM PDT 24
Finished Jul 26 05:15:25 PM PDT 24
Peak memory 207124 kb
Host smart-6d533bcc-e914-4265-a457-1c14cc2260b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23029
06037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.2302906037
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.2645448924
Short name T2186
Test name
Test status
Simulation time 6841512549 ps
CPU time 200.75 seconds
Started Jul 26 05:15:20 PM PDT 24
Finished Jul 26 05:18:41 PM PDT 24
Peak memory 215556 kb
Host smart-36023d64-6e8c-4572-86d6-be4cb05cb00b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2645448924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.2645448924
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_iso_retraction.1553713364
Short name T938
Test name
Test status
Simulation time 10335041291 ps
CPU time 79.74 seconds
Started Jul 26 05:15:19 PM PDT 24
Finished Jul 26 05:16:39 PM PDT 24
Peak memory 207192 kb
Host smart-5f9f53cb-e517-4f47-af12-c82d0e08b4ba
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1553713364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_iso_retraction.1553713364
Directory /workspace/48.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.1010933928
Short name T544
Test name
Test status
Simulation time 178751095 ps
CPU time 0.89 seconds
Started Jul 26 05:15:24 PM PDT 24
Finished Jul 26 05:15:25 PM PDT 24
Peak memory 207124 kb
Host smart-a792110d-f6b4-4530-bea6-ffb9b14e7a8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10109
33928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.1010933928
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.3656254564
Short name T2576
Test name
Test status
Simulation time 23322124684 ps
CPU time 30.03 seconds
Started Jul 26 05:15:17 PM PDT 24
Finished Jul 26 05:15:48 PM PDT 24
Peak memory 207268 kb
Host smart-3b0577e8-06e7-4484-9fa8-446c77defc53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36562
54564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.3656254564
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.4204666488
Short name T1133
Test name
Test status
Simulation time 3353841931 ps
CPU time 5.03 seconds
Started Jul 26 05:15:30 PM PDT 24
Finished Jul 26 05:15:36 PM PDT 24
Peak memory 207368 kb
Host smart-38e546a2-bfa1-4159-ac42-dc6544ace36b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42046
66488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.4204666488
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.2053112535
Short name T218
Test name
Test status
Simulation time 10335474985 ps
CPU time 73.96 seconds
Started Jul 26 05:15:24 PM PDT 24
Finished Jul 26 05:16:38 PM PDT 24
Peak memory 223752 kb
Host smart-764b775d-36d0-4c20-bb91-7bf14e5b17b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20531
12535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.2053112535
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.4243463912
Short name T499
Test name
Test status
Simulation time 5405560495 ps
CPU time 53.74 seconds
Started Jul 26 05:15:30 PM PDT 24
Finished Jul 26 05:16:23 PM PDT 24
Peak memory 207252 kb
Host smart-49daea3d-5b11-4bda-98fe-7e1c33558b07
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4243463912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.4243463912
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.240139980
Short name T483
Test name
Test status
Simulation time 242962969 ps
CPU time 1.01 seconds
Started Jul 26 05:15:26 PM PDT 24
Finished Jul 26 05:15:28 PM PDT 24
Peak memory 207036 kb
Host smart-f70b297f-ae9c-455e-b980-f72d68ea3cd0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=240139980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.240139980
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.4277384138
Short name T2257
Test name
Test status
Simulation time 181942253 ps
CPU time 0.92 seconds
Started Jul 26 05:15:29 PM PDT 24
Finished Jul 26 05:15:30 PM PDT 24
Peak memory 207024 kb
Host smart-e23628f0-2358-4642-94a6-d7b1d0dff2d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42773
84138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.4277384138
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.3343225385
Short name T521
Test name
Test status
Simulation time 3825921672 ps
CPU time 30.15 seconds
Started Jul 26 05:15:25 PM PDT 24
Finished Jul 26 05:15:55 PM PDT 24
Peak memory 217092 kb
Host smart-98cd39aa-9b74-4387-8bd3-ae2aabdff3aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33432
25385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.3343225385
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.3327810853
Short name T1404
Test name
Test status
Simulation time 3880513976 ps
CPU time 113.3 seconds
Started Jul 26 05:15:30 PM PDT 24
Finished Jul 26 05:17:24 PM PDT 24
Peak memory 215588 kb
Host smart-b19ad4d3-c3a8-43a7-aac0-444f6ae72c86
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3327810853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.3327810853
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.636836627
Short name T468
Test name
Test status
Simulation time 180980702 ps
CPU time 0.93 seconds
Started Jul 26 05:15:21 PM PDT 24
Finished Jul 26 05:15:22 PM PDT 24
Peak memory 207020 kb
Host smart-e0278e89-f283-4f55-83c0-2305c418852d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=636836627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.636836627
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.4195371976
Short name T2306
Test name
Test status
Simulation time 166907097 ps
CPU time 0.85 seconds
Started Jul 26 05:15:25 PM PDT 24
Finished Jul 26 05:15:26 PM PDT 24
Peak memory 207024 kb
Host smart-e0da25fe-1e2b-48f8-8b1b-5cafcda2f2b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41953
71976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.4195371976
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.1475982898
Short name T129
Test name
Test status
Simulation time 242729860 ps
CPU time 1.07 seconds
Started Jul 26 05:15:24 PM PDT 24
Finished Jul 26 05:15:25 PM PDT 24
Peak memory 207088 kb
Host smart-caf72e51-c303-41a7-bec0-8e2c5e51866e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14759
82898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.1475982898
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.4266737830
Short name T2089
Test name
Test status
Simulation time 186124954 ps
CPU time 1.01 seconds
Started Jul 26 05:15:21 PM PDT 24
Finished Jul 26 05:15:22 PM PDT 24
Peak memory 207072 kb
Host smart-d374e8a3-171a-4153-8dd8-154a295df440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42667
37830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.4266737830
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.1362623984
Short name T2086
Test name
Test status
Simulation time 172055937 ps
CPU time 0.87 seconds
Started Jul 26 05:15:26 PM PDT 24
Finished Jul 26 05:15:27 PM PDT 24
Peak memory 207080 kb
Host smart-df4adffe-0211-409f-8886-703e5e65410a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13626
23984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.1362623984
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.1372487212
Short name T1708
Test name
Test status
Simulation time 149793788 ps
CPU time 0.82 seconds
Started Jul 26 05:15:23 PM PDT 24
Finished Jul 26 05:15:24 PM PDT 24
Peak memory 207024 kb
Host smart-6edb990c-3e91-4f55-90e3-035ed6504394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13724
87212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.1372487212
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.4261153517
Short name T2339
Test name
Test status
Simulation time 171313286 ps
CPU time 0.9 seconds
Started Jul 26 05:15:28 PM PDT 24
Finished Jul 26 05:15:29 PM PDT 24
Peak memory 207100 kb
Host smart-c2adf7aa-5470-421b-908f-94d3efd383d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42611
53517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.4261153517
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.3368393048
Short name T1095
Test name
Test status
Simulation time 238441962 ps
CPU time 0.96 seconds
Started Jul 26 05:15:25 PM PDT 24
Finished Jul 26 05:15:27 PM PDT 24
Peak memory 206960 kb
Host smart-4b688a19-dee5-40e4-9b7f-27dfe6fc2e43
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3368393048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.3368393048
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.2641748886
Short name T419
Test name
Test status
Simulation time 146252213 ps
CPU time 0.84 seconds
Started Jul 26 05:15:29 PM PDT 24
Finished Jul 26 05:15:30 PM PDT 24
Peak memory 207064 kb
Host smart-0f65b9bc-3c9a-40d4-b1c4-1b1551d28705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26417
48886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.2641748886
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.1455128725
Short name T2011
Test name
Test status
Simulation time 71965375 ps
CPU time 0.71 seconds
Started Jul 26 05:15:29 PM PDT 24
Finished Jul 26 05:15:30 PM PDT 24
Peak memory 206988 kb
Host smart-d0b235e3-55cb-4a0f-8696-27e4ffe363b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14551
28725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.1455128725
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.2157041788
Short name T2168
Test name
Test status
Simulation time 10417154534 ps
CPU time 28.57 seconds
Started Jul 26 05:15:42 PM PDT 24
Finished Jul 26 05:16:11 PM PDT 24
Peak memory 215500 kb
Host smart-7b68946d-7c6a-47bd-b670-2532c8259dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21570
41788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.2157041788
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.2981752509
Short name T2762
Test name
Test status
Simulation time 166655578 ps
CPU time 0.91 seconds
Started Jul 26 05:15:38 PM PDT 24
Finished Jul 26 05:15:39 PM PDT 24
Peak memory 207124 kb
Host smart-4e8fdc31-1db1-443d-bc53-fad2d03c81f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29817
52509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.2981752509
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.4173916343
Short name T1447
Test name
Test status
Simulation time 254356933 ps
CPU time 1.01 seconds
Started Jul 26 05:15:27 PM PDT 24
Finished Jul 26 05:15:28 PM PDT 24
Peak memory 206996 kb
Host smart-543fa31d-90dc-4648-8b80-4248e01f0a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41739
16343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.4173916343
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.3733000242
Short name T2217
Test name
Test status
Simulation time 168878621 ps
CPU time 0.9 seconds
Started Jul 26 05:15:42 PM PDT 24
Finished Jul 26 05:15:44 PM PDT 24
Peak memory 206996 kb
Host smart-4bf48f77-8b0e-4da2-ae12-f855fbcddb02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37330
00242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.3733000242
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.273704753
Short name T628
Test name
Test status
Simulation time 175459359 ps
CPU time 0.88 seconds
Started Jul 26 05:15:26 PM PDT 24
Finished Jul 26 05:15:27 PM PDT 24
Peak memory 207136 kb
Host smart-dabf9269-28a0-4d41-8dac-236464a27893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27370
4753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.273704753
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.3484797088
Short name T706
Test name
Test status
Simulation time 178640866 ps
CPU time 0.86 seconds
Started Jul 26 05:15:26 PM PDT 24
Finished Jul 26 05:15:27 PM PDT 24
Peak memory 207084 kb
Host smart-86414e9b-29b4-410b-a7ba-513d05c41366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34847
97088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.3484797088
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.3096488268
Short name T1723
Test name
Test status
Simulation time 155237770 ps
CPU time 0.9 seconds
Started Jul 26 05:15:37 PM PDT 24
Finished Jul 26 05:15:38 PM PDT 24
Peak memory 207004 kb
Host smart-e630fd3c-51e7-4043-90cd-49ecbec22dd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30964
88268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.3096488268
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.2213791349
Short name T1232
Test name
Test status
Simulation time 191098205 ps
CPU time 0.87 seconds
Started Jul 26 05:15:26 PM PDT 24
Finished Jul 26 05:15:27 PM PDT 24
Peak memory 207028 kb
Host smart-6e42c72a-84cf-4170-ac93-3d43c55d9457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22137
91349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.2213791349
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.1133941506
Short name T1224
Test name
Test status
Simulation time 306207858 ps
CPU time 1.08 seconds
Started Jul 26 05:15:29 PM PDT 24
Finished Jul 26 05:15:30 PM PDT 24
Peak memory 207052 kb
Host smart-0afdc60d-99de-4243-8f59-3c4b6ff2ee8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11339
41506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1133941506
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.595887895
Short name T1794
Test name
Test status
Simulation time 5476060416 ps
CPU time 167.2 seconds
Started Jul 26 05:15:31 PM PDT 24
Finished Jul 26 05:18:18 PM PDT 24
Peak memory 215808 kb
Host smart-f80f81c1-3c0e-4691-b88c-357a09294ef3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=595887895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.595887895
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.87884985
Short name T1350
Test name
Test status
Simulation time 217872622 ps
CPU time 0.88 seconds
Started Jul 26 05:15:37 PM PDT 24
Finished Jul 26 05:15:39 PM PDT 24
Peak memory 207016 kb
Host smart-d4468c34-f50e-4d88-89ee-dab89a085d7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87884
985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.87884985
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.3551427349
Short name T2556
Test name
Test status
Simulation time 210634622 ps
CPU time 0.91 seconds
Started Jul 26 05:15:26 PM PDT 24
Finished Jul 26 05:15:28 PM PDT 24
Peak memory 207132 kb
Host smart-57d81834-7c04-4973-81ab-667cb917afb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35514
27349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.3551427349
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.467105221
Short name T1606
Test name
Test status
Simulation time 507681888 ps
CPU time 1.6 seconds
Started Jul 26 05:15:31 PM PDT 24
Finished Jul 26 05:15:33 PM PDT 24
Peak memory 207328 kb
Host smart-b01827cd-fe98-4569-95d8-61b51ee6195e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46710
5221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.467105221
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.503213187
Short name T1530
Test name
Test status
Simulation time 4644618393 ps
CPU time 144.15 seconds
Started Jul 26 05:15:28 PM PDT 24
Finished Jul 26 05:17:52 PM PDT 24
Peak memory 215592 kb
Host smart-b6de4de3-0b6e-49a0-b4fe-8346f341b679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50321
3187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.503213187
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_timeout_missing_host_handshake.3701309776
Short name T1458
Test name
Test status
Simulation time 620515490 ps
CPU time 5.21 seconds
Started Jul 26 05:15:23 PM PDT 24
Finished Jul 26 05:15:29 PM PDT 24
Peak memory 207188 kb
Host smart-f452d4eb-7e1a-4788-9c07-9d85dcfd7f90
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701309776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_timeout_missing_hos
t_handshake.3701309776
Directory /workspace/48.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.1117644125
Short name T1764
Test name
Test status
Simulation time 45674671 ps
CPU time 0.65 seconds
Started Jul 26 05:15:36 PM PDT 24
Finished Jul 26 05:15:37 PM PDT 24
Peak memory 207136 kb
Host smart-1553d47d-9c38-4ef3-83a5-eeb301c8a46c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1117644125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.1117644125
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.1358820189
Short name T2596
Test name
Test status
Simulation time 4230858897 ps
CPU time 5.88 seconds
Started Jul 26 05:15:37 PM PDT 24
Finished Jul 26 05:15:44 PM PDT 24
Peak memory 207212 kb
Host smart-3b359449-4b68-4951-b30f-8778f17b38bb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358820189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_a
on_wake_disconnect.1358820189
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.31527308
Short name T2522
Test name
Test status
Simulation time 13328891241 ps
CPU time 16.08 seconds
Started Jul 26 05:15:32 PM PDT 24
Finished Jul 26 05:15:49 PM PDT 24
Peak memory 207384 kb
Host smart-745df487-57e5-4229-bf71-f89cc9f32828
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=31527308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.31527308
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.3473023849
Short name T6
Test name
Test status
Simulation time 23365283004 ps
CPU time 26.89 seconds
Started Jul 26 05:15:36 PM PDT 24
Finished Jul 26 05:16:03 PM PDT 24
Peak memory 207272 kb
Host smart-d890cfd6-0531-4411-a1cb-934e914fb49b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473023849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_a
on_wake_resume.3473023849
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.956147062
Short name T835
Test name
Test status
Simulation time 171781352 ps
CPU time 0.85 seconds
Started Jul 26 05:15:27 PM PDT 24
Finished Jul 26 05:15:28 PM PDT 24
Peak memory 206520 kb
Host smart-f1c752f8-3b3a-4760-bbde-2691f5a1b594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95614
7062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.956147062
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.2400961248
Short name T1973
Test name
Test status
Simulation time 180229474 ps
CPU time 0.92 seconds
Started Jul 26 05:15:27 PM PDT 24
Finished Jul 26 05:15:28 PM PDT 24
Peak memory 206436 kb
Host smart-ca052734-037a-4f81-a250-d2357508eb7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24009
61248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.2400961248
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.527060477
Short name T575
Test name
Test status
Simulation time 217174608 ps
CPU time 1.03 seconds
Started Jul 26 05:15:38 PM PDT 24
Finished Jul 26 05:15:40 PM PDT 24
Peak memory 206984 kb
Host smart-8cf90ff0-1808-43b4-bc5b-5f89343af526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52706
0477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.527060477
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.8830515
Short name T1656
Test name
Test status
Simulation time 1494961782 ps
CPU time 3.45 seconds
Started Jul 26 05:15:30 PM PDT 24
Finished Jul 26 05:15:33 PM PDT 24
Peak memory 207116 kb
Host smart-953e4ca4-5fec-4eeb-9ace-5c99f77032e7
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=8830515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.8830515
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_timeout.3200028191
Short name T2297
Test name
Test status
Simulation time 921240527 ps
CPU time 19.11 seconds
Started Jul 26 05:15:37 PM PDT 24
Finished Jul 26 05:15:56 PM PDT 24
Peak memory 207260 kb
Host smart-31a3c927-2712-4fba-957a-8eabb0469256
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200028191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_timeout.3200028191
Directory /workspace/49.usbdev_device_timeout/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.632733943
Short name T271
Test name
Test status
Simulation time 330541609 ps
CPU time 1.35 seconds
Started Jul 26 05:15:30 PM PDT 24
Finished Jul 26 05:15:31 PM PDT 24
Peak memory 207068 kb
Host smart-f448f61e-5fa4-4a2e-9136-a1f5902927c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63273
3943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.632733943
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.3069404704
Short name T2177
Test name
Test status
Simulation time 148510442 ps
CPU time 0.85 seconds
Started Jul 26 05:15:29 PM PDT 24
Finished Jul 26 05:15:30 PM PDT 24
Peak memory 207068 kb
Host smart-f3716f3f-9d8a-4895-836b-5376d5e182d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30694
04704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.3069404704
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.2757326343
Short name T2861
Test name
Test status
Simulation time 32100309 ps
CPU time 0.7 seconds
Started Jul 26 05:15:31 PM PDT 24
Finished Jul 26 05:15:32 PM PDT 24
Peak memory 206976 kb
Host smart-9b5709ab-ea8a-4b32-8e0b-073c04cd5f4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27573
26343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.2757326343
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.3335775938
Short name T2212
Test name
Test status
Simulation time 857940613 ps
CPU time 2.12 seconds
Started Jul 26 05:15:31 PM PDT 24
Finished Jul 26 05:15:33 PM PDT 24
Peak memory 207084 kb
Host smart-10785d6c-65ef-486d-b9dd-e61726851cb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33357
75938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.3335775938
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.3379230101
Short name T1085
Test name
Test status
Simulation time 159390225 ps
CPU time 1.49 seconds
Started Jul 26 05:15:29 PM PDT 24
Finished Jul 26 05:15:31 PM PDT 24
Peak memory 207264 kb
Host smart-6a00606f-fe5a-46a4-9310-d40f2c191787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33792
30101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.3379230101
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.2121444923
Short name T794
Test name
Test status
Simulation time 207891863 ps
CPU time 0.96 seconds
Started Jul 26 05:15:32 PM PDT 24
Finished Jul 26 05:15:34 PM PDT 24
Peak memory 207144 kb
Host smart-a9b7eccf-3712-429f-8452-e35ce40c87d8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2121444923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.2121444923
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.46112963
Short name T2754
Test name
Test status
Simulation time 152473501 ps
CPU time 0.84 seconds
Started Jul 26 05:15:29 PM PDT 24
Finished Jul 26 05:15:30 PM PDT 24
Peak memory 207068 kb
Host smart-554e93c4-9847-49b7-b54a-66c877e19bf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46112
963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.46112963
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.2328619838
Short name T2352
Test name
Test status
Simulation time 202319259 ps
CPU time 0.97 seconds
Started Jul 26 05:15:39 PM PDT 24
Finished Jul 26 05:15:40 PM PDT 24
Peak memory 207096 kb
Host smart-4ed89c28-9dc1-493a-bb14-72b1155e1b49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23286
19838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.2328619838
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_iso_retraction.2162553027
Short name T102
Test name
Test status
Simulation time 14911368822 ps
CPU time 95.26 seconds
Started Jul 26 05:15:37 PM PDT 24
Finished Jul 26 05:17:13 PM PDT 24
Peak memory 207316 kb
Host smart-426a5fe8-fec2-4571-b279-80bdb95d36c1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2162553027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_iso_retraction.2162553027
Directory /workspace/49.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.1547957348
Short name T697
Test name
Test status
Simulation time 309562216 ps
CPU time 1.07 seconds
Started Jul 26 05:15:32 PM PDT 24
Finished Jul 26 05:15:34 PM PDT 24
Peak memory 207120 kb
Host smart-03f14874-c336-436a-96e8-06662dee2b86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15479
57348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.1547957348
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.543542704
Short name T1163
Test name
Test status
Simulation time 23378840662 ps
CPU time 35.05 seconds
Started Jul 26 05:15:38 PM PDT 24
Finished Jul 26 05:16:14 PM PDT 24
Peak memory 207260 kb
Host smart-a230bb13-1e65-4893-93df-a636f3b4e91e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54354
2704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.543542704
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.1428042108
Short name T2203
Test name
Test status
Simulation time 3280999142 ps
CPU time 5.82 seconds
Started Jul 26 05:15:37 PM PDT 24
Finished Jul 26 05:15:43 PM PDT 24
Peak memory 207372 kb
Host smart-8ae78c69-5fb1-4df3-9d3d-a9e7a6bbe1b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14280
42108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.1428042108
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.2555774358
Short name T964
Test name
Test status
Simulation time 5002690843 ps
CPU time 38.35 seconds
Started Jul 26 05:15:28 PM PDT 24
Finished Jul 26 05:16:07 PM PDT 24
Peak memory 223644 kb
Host smart-a510be73-4bcb-47e0-9390-ecf725dc385f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25557
74358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.2555774358
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.777706848
Short name T2226
Test name
Test status
Simulation time 5164120168 ps
CPU time 50.07 seconds
Started Jul 26 05:15:26 PM PDT 24
Finished Jul 26 05:16:16 PM PDT 24
Peak memory 217116 kb
Host smart-e5e9a96b-48ba-43d4-8049-b2048935ad7c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=777706848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.777706848
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.1899881429
Short name T1836
Test name
Test status
Simulation time 315032959 ps
CPU time 1.15 seconds
Started Jul 26 05:15:31 PM PDT 24
Finished Jul 26 05:15:33 PM PDT 24
Peak memory 207108 kb
Host smart-b54760e1-9703-4266-879c-58a7a5a85f79
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1899881429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.1899881429
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.1977246247
Short name T1134
Test name
Test status
Simulation time 243941094 ps
CPU time 1 seconds
Started Jul 26 05:15:37 PM PDT 24
Finished Jul 26 05:15:38 PM PDT 24
Peak memory 207120 kb
Host smart-ae73f639-7aaf-49f2-b4ba-b70a3062a0f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19772
46247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.1977246247
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.2931044472
Short name T340
Test name
Test status
Simulation time 6337473235 ps
CPU time 45.9 seconds
Started Jul 26 05:15:31 PM PDT 24
Finished Jul 26 05:16:17 PM PDT 24
Peak memory 216456 kb
Host smart-b189d923-d829-4cb0-a052-33aba2292685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29310
44472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.2931044472
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.3517149614
Short name T981
Test name
Test status
Simulation time 5568679905 ps
CPU time 42.46 seconds
Started Jul 26 05:15:36 PM PDT 24
Finished Jul 26 05:16:18 PM PDT 24
Peak memory 215516 kb
Host smart-fb8ca02d-14d2-48af-8a6e-5bdb24c0666a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3517149614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.3517149614
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.286757077
Short name T2804
Test name
Test status
Simulation time 188526357 ps
CPU time 0.87 seconds
Started Jul 26 05:15:30 PM PDT 24
Finished Jul 26 05:15:31 PM PDT 24
Peak memory 207140 kb
Host smart-5232eefe-5733-4413-99ba-ceddbbe371ee
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=286757077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.286757077
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.3565332272
Short name T2612
Test name
Test status
Simulation time 186789134 ps
CPU time 0.85 seconds
Started Jul 26 05:15:27 PM PDT 24
Finished Jul 26 05:15:28 PM PDT 24
Peak memory 207156 kb
Host smart-49a8153f-d3b8-4454-9865-0dc336fadbff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35653
32272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.3565332272
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.2723531631
Short name T123
Test name
Test status
Simulation time 194808591 ps
CPU time 0.92 seconds
Started Jul 26 05:15:30 PM PDT 24
Finished Jul 26 05:15:31 PM PDT 24
Peak memory 207124 kb
Host smart-fa4a5110-d02e-46b4-bbb3-3cdf3a775928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27235
31631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.2723531631
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.2164467304
Short name T501
Test name
Test status
Simulation time 168015886 ps
CPU time 0.94 seconds
Started Jul 26 05:15:36 PM PDT 24
Finished Jul 26 05:15:37 PM PDT 24
Peak memory 207032 kb
Host smart-c8f3112d-aaee-4e1d-a3d0-40016bf79b08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21644
67304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.2164467304
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.1253006826
Short name T2400
Test name
Test status
Simulation time 192196223 ps
CPU time 0.91 seconds
Started Jul 26 05:15:30 PM PDT 24
Finished Jul 26 05:15:31 PM PDT 24
Peak memory 207104 kb
Host smart-e71ffbb2-53b7-441c-8740-646695ad55b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12530
06826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.1253006826
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.817469267
Short name T2740
Test name
Test status
Simulation time 179261184 ps
CPU time 0.89 seconds
Started Jul 26 05:15:37 PM PDT 24
Finished Jul 26 05:15:39 PM PDT 24
Peak memory 206992 kb
Host smart-5d9dc8c3-5bee-42d7-97c3-323ceddd0be8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81746
9267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.817469267
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.2422232725
Short name T2814
Test name
Test status
Simulation time 155812052 ps
CPU time 0.87 seconds
Started Jul 26 05:15:36 PM PDT 24
Finished Jul 26 05:15:37 PM PDT 24
Peak memory 207120 kb
Host smart-6b9f9806-75d0-4b2d-aeea-2fefb6c05823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24222
32725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.2422232725
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.1513821021
Short name T506
Test name
Test status
Simulation time 213164326 ps
CPU time 0.98 seconds
Started Jul 26 05:15:39 PM PDT 24
Finished Jul 26 05:15:40 PM PDT 24
Peak memory 207148 kb
Host smart-bc64a41c-bea6-40e2-bd83-91a15a6f1085
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1513821021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.1513821021
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.1977855415
Short name T2722
Test name
Test status
Simulation time 157614600 ps
CPU time 0.94 seconds
Started Jul 26 05:15:32 PM PDT 24
Finished Jul 26 05:15:33 PM PDT 24
Peak memory 207300 kb
Host smart-390e1abb-a611-417e-b435-6a959d59bd79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19778
55415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.1977855415
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.1524923290
Short name T1385
Test name
Test status
Simulation time 61339800 ps
CPU time 0.7 seconds
Started Jul 26 05:15:31 PM PDT 24
Finished Jul 26 05:15:32 PM PDT 24
Peak memory 206976 kb
Host smart-fad8b091-c998-47dc-adf7-99bfdb1e015d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15249
23290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.1524923290
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.405543144
Short name T1094
Test name
Test status
Simulation time 18571226335 ps
CPU time 46.72 seconds
Started Jul 26 05:15:36 PM PDT 24
Finished Jul 26 05:16:23 PM PDT 24
Peak memory 215540 kb
Host smart-4de4934c-551e-456c-817e-39e7973c1f15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40554
3144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.405543144
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.1131294501
Short name T1550
Test name
Test status
Simulation time 235747579 ps
CPU time 1.04 seconds
Started Jul 26 05:15:35 PM PDT 24
Finished Jul 26 05:15:37 PM PDT 24
Peak memory 207056 kb
Host smart-bfbb4697-f78d-4c07-ab2c-63450adcd79a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11312
94501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.1131294501
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.1972228565
Short name T1337
Test name
Test status
Simulation time 233254401 ps
CPU time 0.96 seconds
Started Jul 26 05:15:37 PM PDT 24
Finished Jul 26 05:15:38 PM PDT 24
Peak memory 207044 kb
Host smart-cbb78404-ba78-49ce-813e-bb65e7b95300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19722
28565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.1972228565
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.776695024
Short name T1275
Test name
Test status
Simulation time 214057196 ps
CPU time 0.92 seconds
Started Jul 26 05:15:38 PM PDT 24
Finished Jul 26 05:15:39 PM PDT 24
Peak memory 207104 kb
Host smart-9b0a3b39-1ed6-401a-91be-6401c75c51ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77669
5024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.776695024
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.1734792308
Short name T1543
Test name
Test status
Simulation time 166250321 ps
CPU time 0.87 seconds
Started Jul 26 05:15:39 PM PDT 24
Finished Jul 26 05:15:40 PM PDT 24
Peak memory 207048 kb
Host smart-0c9f43ad-4465-43e9-b83b-bb832c42a553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17347
92308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.1734792308
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.2730981251
Short name T2482
Test name
Test status
Simulation time 171648503 ps
CPU time 0.9 seconds
Started Jul 26 05:15:37 PM PDT 24
Finished Jul 26 05:15:38 PM PDT 24
Peak memory 207120 kb
Host smart-7c48b243-57f5-442f-b591-c08e7bc2cd0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27309
81251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.2730981251
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.1267138698
Short name T532
Test name
Test status
Simulation time 197255487 ps
CPU time 0.92 seconds
Started Jul 26 05:15:37 PM PDT 24
Finished Jul 26 05:15:38 PM PDT 24
Peak memory 207068 kb
Host smart-ddb39bfa-a220-4f58-b762-c29e42a4a528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12671
38698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.1267138698
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.1636517050
Short name T511
Test name
Test status
Simulation time 160188861 ps
CPU time 0.85 seconds
Started Jul 26 05:15:41 PM PDT 24
Finished Jul 26 05:15:42 PM PDT 24
Peak memory 207096 kb
Host smart-6473adca-3fb1-4e96-9263-97109473f67f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16365
17050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.1636517050
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.3102489793
Short name T1657
Test name
Test status
Simulation time 277569282 ps
CPU time 1.08 seconds
Started Jul 26 05:15:39 PM PDT 24
Finished Jul 26 05:15:40 PM PDT 24
Peak memory 207096 kb
Host smart-9b37d1c6-f8d0-4a0b-8e4d-d194bf289cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31024
89793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.3102489793
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.3889264213
Short name T2243
Test name
Test status
Simulation time 4386079596 ps
CPU time 32.81 seconds
Started Jul 26 05:15:37 PM PDT 24
Finished Jul 26 05:16:10 PM PDT 24
Peak memory 216948 kb
Host smart-a65f36d2-83ca-4840-b6c5-17e905b82261
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3889264213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.3889264213
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.977988972
Short name T1464
Test name
Test status
Simulation time 170305402 ps
CPU time 0.95 seconds
Started Jul 26 05:15:37 PM PDT 24
Finished Jul 26 05:15:38 PM PDT 24
Peak memory 207124 kb
Host smart-11b09df9-aa47-4d5b-8d12-74a004e19ff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97798
8972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.977988972
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.3647189297
Short name T436
Test name
Test status
Simulation time 258388950 ps
CPU time 0.93 seconds
Started Jul 26 05:15:39 PM PDT 24
Finished Jul 26 05:15:40 PM PDT 24
Peak memory 207100 kb
Host smart-e0037c80-7b3e-41ec-b94a-38fdadef0b84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36471
89297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.3647189297
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.2070171433
Short name T1465
Test name
Test status
Simulation time 1114149265 ps
CPU time 3.27 seconds
Started Jul 26 05:15:39 PM PDT 24
Finished Jul 26 05:15:43 PM PDT 24
Peak memory 207200 kb
Host smart-bcecf4ae-de75-4e9e-a4bc-0baf605c6eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20701
71433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.2070171433
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.2751442019
Short name T2849
Test name
Test status
Simulation time 5790541750 ps
CPU time 43.41 seconds
Started Jul 26 05:15:38 PM PDT 24
Finished Jul 26 05:16:21 PM PDT 24
Peak memory 215556 kb
Host smart-0cc2c24c-da52-4ced-94d8-20dc9cba2ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27514
42019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.2751442019
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_timeout_missing_host_handshake.959488348
Short name T2319
Test name
Test status
Simulation time 1567751644 ps
CPU time 13.57 seconds
Started Jul 26 05:15:26 PM PDT 24
Finished Jul 26 05:15:40 PM PDT 24
Peak memory 207320 kb
Host smart-03175784-9de0-4ab8-bd95-6d5a2be6e0a8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959488348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_timeout_missing_host
_handshake.959488348
Directory /workspace/49.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.1256887860
Short name T1366
Test name
Test status
Simulation time 49374158 ps
CPU time 0.73 seconds
Started Jul 26 05:07:39 PM PDT 24
Finished Jul 26 05:07:40 PM PDT 24
Peak memory 207156 kb
Host smart-e0c5da90-a9e9-480f-aa42-f3fb45cc0e4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1256887860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.1256887860
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.3184155388
Short name T2265
Test name
Test status
Simulation time 3905269154 ps
CPU time 5.87 seconds
Started Jul 26 05:07:31 PM PDT 24
Finished Jul 26 05:07:37 PM PDT 24
Peak memory 207360 kb
Host smart-58174679-a000-4ba9-abda-5180d1e07889
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184155388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_disconnect.3184155388
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.2751320551
Short name T180
Test name
Test status
Simulation time 13360116986 ps
CPU time 16.7 seconds
Started Jul 26 05:07:30 PM PDT 24
Finished Jul 26 05:07:47 PM PDT 24
Peak memory 207368 kb
Host smart-2394c78b-612c-441b-96db-eb25c75bc2dc
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751320551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.2751320551
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.2064018477
Short name T2624
Test name
Test status
Simulation time 23345167508 ps
CPU time 30.77 seconds
Started Jul 26 05:07:28 PM PDT 24
Finished Jul 26 05:07:59 PM PDT 24
Peak memory 207376 kb
Host smart-13759c2c-e052-4c9a-baf3-e63562461434
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064018477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_resume.2064018477
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.1426759400
Short name T2700
Test name
Test status
Simulation time 184274281 ps
CPU time 0.91 seconds
Started Jul 26 05:07:29 PM PDT 24
Finished Jul 26 05:07:30 PM PDT 24
Peak memory 207128 kb
Host smart-bbc6dd14-eadc-41ba-ba90-51d00f91de7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14267
59400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.1426759400
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.4209906797
Short name T1692
Test name
Test status
Simulation time 140759677 ps
CPU time 0.81 seconds
Started Jul 26 05:07:29 PM PDT 24
Finished Jul 26 05:07:30 PM PDT 24
Peak memory 207092 kb
Host smart-cc97ce86-cf4e-459a-b52b-66bbb2149cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42099
06797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.4209906797
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.416367669
Short name T2499
Test name
Test status
Simulation time 256723153 ps
CPU time 1.04 seconds
Started Jul 26 05:07:31 PM PDT 24
Finished Jul 26 05:07:33 PM PDT 24
Peak memory 207208 kb
Host smart-f8d11dd9-6a4c-4032-a7d8-a5f1afe5878b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41636
7669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.416367669
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.2155596781
Short name T2295
Test name
Test status
Simulation time 524397175 ps
CPU time 1.76 seconds
Started Jul 26 05:07:29 PM PDT 24
Finished Jul 26 05:07:31 PM PDT 24
Peak memory 207108 kb
Host smart-2da2a855-e423-489e-8657-c3269c558f23
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2155596781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.2155596781
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.2673529916
Short name T1245
Test name
Test status
Simulation time 20975493397 ps
CPU time 45.34 seconds
Started Jul 26 05:07:29 PM PDT 24
Finished Jul 26 05:08:14 PM PDT 24
Peak memory 207400 kb
Host smart-22652025-25e0-4072-865a-ad2c37c8f526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26735
29916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.2673529916
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_device_timeout.395314707
Short name T2376
Test name
Test status
Simulation time 2050609691 ps
CPU time 17.31 seconds
Started Jul 26 05:07:30 PM PDT 24
Finished Jul 26 05:07:48 PM PDT 24
Peak memory 207324 kb
Host smart-7772fe87-c5a0-41f8-a9ef-a82eb594da86
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395314707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_timeout.395314707
Directory /workspace/5.usbdev_device_timeout/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.3602181884
Short name T1188
Test name
Test status
Simulation time 324623114 ps
CPU time 1.22 seconds
Started Jul 26 05:07:26 PM PDT 24
Finished Jul 26 05:07:28 PM PDT 24
Peak memory 206976 kb
Host smart-e3707cc0-1e50-4a62-b044-d8997af96852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36021
81884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.3602181884
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.1610139510
Short name T2452
Test name
Test status
Simulation time 141890234 ps
CPU time 0.86 seconds
Started Jul 26 05:07:31 PM PDT 24
Finished Jul 26 05:07:32 PM PDT 24
Peak memory 207068 kb
Host smart-0bd6406b-6c63-480a-8121-d9c426fb5e7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16101
39510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.1610139510
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.2823032080
Short name T2680
Test name
Test status
Simulation time 49799620 ps
CPU time 0.7 seconds
Started Jul 26 05:07:29 PM PDT 24
Finished Jul 26 05:07:29 PM PDT 24
Peak memory 206976 kb
Host smart-12dc6e89-4197-4c31-8d14-beee2cbfc49b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28230
32080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.2823032080
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.3591115069
Short name T1589
Test name
Test status
Simulation time 838074142 ps
CPU time 2.43 seconds
Started Jul 26 05:07:30 PM PDT 24
Finished Jul 26 05:07:33 PM PDT 24
Peak memory 207336 kb
Host smart-d21d7b65-f5fc-4013-9bb3-6bd0c897710c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35911
15069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.3591115069
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.4065707596
Short name T1601
Test name
Test status
Simulation time 201940162 ps
CPU time 2.26 seconds
Started Jul 26 05:07:29 PM PDT 24
Finished Jul 26 05:07:31 PM PDT 24
Peak memory 207088 kb
Host smart-e59db9a1-976d-41ce-a935-cab432a20b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40657
07596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.4065707596
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.1004327065
Short name T510
Test name
Test status
Simulation time 164224365 ps
CPU time 0.91 seconds
Started Jul 26 05:07:27 PM PDT 24
Finished Jul 26 05:07:28 PM PDT 24
Peak memory 207104 kb
Host smart-a8d45f6b-8c29-47a6-860b-9e6f8f621534
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1004327065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.1004327065
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.2642723385
Short name T2152
Test name
Test status
Simulation time 144151574 ps
CPU time 0.86 seconds
Started Jul 26 05:07:30 PM PDT 24
Finished Jul 26 05:07:31 PM PDT 24
Peak memory 207096 kb
Host smart-994f17ec-0385-4111-bd3a-cc2bc3070038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26427
23385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.2642723385
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.4166712545
Short name T905
Test name
Test status
Simulation time 238778393 ps
CPU time 1.04 seconds
Started Jul 26 05:07:31 PM PDT 24
Finished Jul 26 05:07:33 PM PDT 24
Peak memory 207076 kb
Host smart-c469d5b1-5a56-4edd-a1cd-61f29ba3ea03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41667
12545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.4166712545
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.2211126984
Short name T841
Test name
Test status
Simulation time 8824823599 ps
CPU time 252 seconds
Started Jul 26 05:07:29 PM PDT 24
Finished Jul 26 05:11:41 PM PDT 24
Peak memory 215532 kb
Host smart-1fe1baf5-f2f7-427e-960c-91571f6d49a4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2211126984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.2211126984
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_iso_retraction.2639411930
Short name T1654
Test name
Test status
Simulation time 10875090357 ps
CPU time 67.77 seconds
Started Jul 26 05:07:30 PM PDT 24
Finished Jul 26 05:08:38 PM PDT 24
Peak memory 207292 kb
Host smart-9e3ca963-5a0b-4a0a-9b88-abb0c79d1c08
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2639411930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.2639411930
Directory /workspace/5.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.2349147283
Short name T1947
Test name
Test status
Simulation time 256050261 ps
CPU time 0.98 seconds
Started Jul 26 05:07:30 PM PDT 24
Finished Jul 26 05:07:32 PM PDT 24
Peak memory 207048 kb
Host smart-78f82a44-d36a-4adc-bd65-9f1df4b7d565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23491
47283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.2349147283
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.245517015
Short name T2497
Test name
Test status
Simulation time 23298610086 ps
CPU time 28.51 seconds
Started Jul 26 05:07:28 PM PDT 24
Finished Jul 26 05:07:57 PM PDT 24
Peak memory 207184 kb
Host smart-0f755127-e1dc-428b-88ae-2bf4f6cf693c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24551
7015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.245517015
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.604676831
Short name T1912
Test name
Test status
Simulation time 3377116922 ps
CPU time 5.02 seconds
Started Jul 26 05:07:30 PM PDT 24
Finished Jul 26 05:07:35 PM PDT 24
Peak memory 207376 kb
Host smart-81600344-f860-439c-8d24-cef45ae5e02f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60467
6831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.604676831
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.3078324295
Short name T1042
Test name
Test status
Simulation time 9415472188 ps
CPU time 95.95 seconds
Started Jul 26 05:07:28 PM PDT 24
Finished Jul 26 05:09:05 PM PDT 24
Peak memory 217576 kb
Host smart-2721cc2d-595b-4e6b-ad3d-b3de1bc20f0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30783
24295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.3078324295
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.2149228477
Short name T280
Test name
Test status
Simulation time 7236474049 ps
CPU time 58.6 seconds
Started Jul 26 05:07:36 PM PDT 24
Finished Jul 26 05:08:35 PM PDT 24
Peak memory 207312 kb
Host smart-1cc33e55-bd51-4741-8eeb-dcafc14f26e8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2149228477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.2149228477
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.174606635
Short name T865
Test name
Test status
Simulation time 289699600 ps
CPU time 1.11 seconds
Started Jul 26 05:07:36 PM PDT 24
Finished Jul 26 05:07:37 PM PDT 24
Peak memory 207012 kb
Host smart-a6574dca-8921-4c65-ac84-a4a1a49186d4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=174606635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.174606635
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.431966270
Short name T2340
Test name
Test status
Simulation time 193357325 ps
CPU time 0.99 seconds
Started Jul 26 05:07:37 PM PDT 24
Finished Jul 26 05:07:38 PM PDT 24
Peak memory 207084 kb
Host smart-120699df-c73d-4e99-9175-88610fee1f60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43196
6270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.431966270
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.4221235439
Short name T2174
Test name
Test status
Simulation time 5935389213 ps
CPU time 47.55 seconds
Started Jul 26 05:07:36 PM PDT 24
Finished Jul 26 05:08:24 PM PDT 24
Peak memory 217088 kb
Host smart-bb4669dc-c910-4334-b6b0-16eac65f49d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42212
35439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.4221235439
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.88461069
Short name T993
Test name
Test status
Simulation time 4683531920 ps
CPU time 37.54 seconds
Started Jul 26 05:07:36 PM PDT 24
Finished Jul 26 05:08:14 PM PDT 24
Peak memory 207432 kb
Host smart-7ddefd0c-ebe2-43f7-b943-dfa90e2e0da0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=88461069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.88461069
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.3488580266
Short name T232
Test name
Test status
Simulation time 153239883 ps
CPU time 0.85 seconds
Started Jul 26 05:07:35 PM PDT 24
Finished Jul 26 05:07:36 PM PDT 24
Peak memory 207136 kb
Host smart-45e1b3ea-662c-4b8e-80d6-f2867ba1f7dc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3488580266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.3488580266
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.553713389
Short name T2686
Test name
Test status
Simulation time 161172136 ps
CPU time 0.88 seconds
Started Jul 26 05:07:39 PM PDT 24
Finished Jul 26 05:07:40 PM PDT 24
Peak memory 207336 kb
Host smart-fc4a9785-8313-4123-8616-4a663639eeee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55371
3389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.553713389
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.1962383789
Short name T133
Test name
Test status
Simulation time 263176198 ps
CPU time 1.01 seconds
Started Jul 26 05:07:38 PM PDT 24
Finished Jul 26 05:07:39 PM PDT 24
Peak memory 207208 kb
Host smart-3ec8ca07-366e-41da-a2f8-564dc8c8a063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19623
83789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.1962383789
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.828439217
Short name T2553
Test name
Test status
Simulation time 208204056 ps
CPU time 0.92 seconds
Started Jul 26 05:07:42 PM PDT 24
Finished Jul 26 05:07:44 PM PDT 24
Peak memory 207048 kb
Host smart-45e39105-57d4-4368-8721-cc85ac88e983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82843
9217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.828439217
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.473293794
Short name T1194
Test name
Test status
Simulation time 202528523 ps
CPU time 0.9 seconds
Started Jul 26 05:07:34 PM PDT 24
Finished Jul 26 05:07:35 PM PDT 24
Peak memory 207056 kb
Host smart-dd6f6f7f-4c14-4646-a9b3-6cd4b5c46520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47329
3794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.473293794
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.2267958770
Short name T1691
Test name
Test status
Simulation time 208005976 ps
CPU time 0.91 seconds
Started Jul 26 05:07:36 PM PDT 24
Finished Jul 26 05:07:37 PM PDT 24
Peak memory 207132 kb
Host smart-c105de46-4481-4fe1-a060-08df0783f656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22679
58770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.2267958770
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.3233658046
Short name T2211
Test name
Test status
Simulation time 168197033 ps
CPU time 0.89 seconds
Started Jul 26 05:07:40 PM PDT 24
Finished Jul 26 05:07:41 PM PDT 24
Peak memory 207084 kb
Host smart-dabcf252-8ee3-4b19-afbe-161b9b2a1b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32336
58046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.3233658046
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.2831844311
Short name T1059
Test name
Test status
Simulation time 233816814 ps
CPU time 1.03 seconds
Started Jul 26 05:07:36 PM PDT 24
Finished Jul 26 05:07:37 PM PDT 24
Peak memory 207152 kb
Host smart-9fff1bc8-e38e-4156-ab6e-50b6bf683f66
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2831844311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.2831844311
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.4056081627
Short name T2841
Test name
Test status
Simulation time 149924220 ps
CPU time 0.83 seconds
Started Jul 26 05:07:45 PM PDT 24
Finished Jul 26 05:07:47 PM PDT 24
Peak memory 207040 kb
Host smart-f4fc82dc-83c8-4036-adae-63551a475c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40560
81627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.4056081627
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.1520540574
Short name T662
Test name
Test status
Simulation time 38724814 ps
CPU time 0.74 seconds
Started Jul 26 05:07:40 PM PDT 24
Finished Jul 26 05:07:41 PM PDT 24
Peak memory 207048 kb
Host smart-965a920e-4f44-4c10-b418-6bfd399940aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15205
40574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.1520540574
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.672845127
Short name T228
Test name
Test status
Simulation time 21305093837 ps
CPU time 58.8 seconds
Started Jul 26 05:07:39 PM PDT 24
Finished Jul 26 05:08:38 PM PDT 24
Peak memory 215584 kb
Host smart-66cd8acf-75d0-4418-a9c0-9a598de863c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67284
5127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.672845127
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.2202923548
Short name T868
Test name
Test status
Simulation time 202768621 ps
CPU time 0.97 seconds
Started Jul 26 05:07:42 PM PDT 24
Finished Jul 26 05:07:44 PM PDT 24
Peak memory 207052 kb
Host smart-06d18307-0864-45d5-ac2f-9071fc91d6e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22029
23548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.2202923548
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.1512441852
Short name T2704
Test name
Test status
Simulation time 240205826 ps
CPU time 1.01 seconds
Started Jul 26 05:07:55 PM PDT 24
Finished Jul 26 05:07:56 PM PDT 24
Peak memory 207060 kb
Host smart-0d3bcd52-9196-455a-93ba-11cdc8857935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15124
41852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.1512441852
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.3259181683
Short name T711
Test name
Test status
Simulation time 7692732666 ps
CPU time 224.8 seconds
Started Jul 26 05:07:36 PM PDT 24
Finished Jul 26 05:11:21 PM PDT 24
Peak memory 215568 kb
Host smart-5bc025ec-eb7f-4d25-b7e4-18edcd53e459
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259181683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.3259181683
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.1797058810
Short name T2601
Test name
Test status
Simulation time 5288182785 ps
CPU time 49.39 seconds
Started Jul 26 05:07:37 PM PDT 24
Finished Jul 26 05:08:27 PM PDT 24
Peak memory 215508 kb
Host smart-0cebf3d9-1008-4822-8139-b10011f753bf
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1797058810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.1797058810
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.3497939018
Short name T1150
Test name
Test status
Simulation time 12001469935 ps
CPU time 86.73 seconds
Started Jul 26 05:07:45 PM PDT 24
Finished Jul 26 05:09:12 PM PDT 24
Peak memory 217432 kb
Host smart-cf6a4568-39d9-4644-9c9b-e98e5211cc48
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497939018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.3497939018
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.605511177
Short name T2252
Test name
Test status
Simulation time 183721661 ps
CPU time 0.87 seconds
Started Jul 26 05:07:37 PM PDT 24
Finished Jul 26 05:07:38 PM PDT 24
Peak memory 207120 kb
Host smart-b18f651b-edd7-44e1-9552-d7b80b3d722e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60551
1177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.605511177
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.1652656323
Short name T1590
Test name
Test status
Simulation time 185596701 ps
CPU time 1 seconds
Started Jul 26 05:07:41 PM PDT 24
Finished Jul 26 05:07:42 PM PDT 24
Peak memory 207052 kb
Host smart-212ca5d7-6366-4811-851d-8c66d7a82606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16526
56323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.1652656323
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.1029205021
Short name T799
Test name
Test status
Simulation time 188875737 ps
CPU time 0.9 seconds
Started Jul 26 05:07:43 PM PDT 24
Finished Jul 26 05:07:44 PM PDT 24
Peak memory 207072 kb
Host smart-226ebd1d-e3a7-4819-9c4d-4c5e7c9f7642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10292
05021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.1029205021
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.3106886144
Short name T933
Test name
Test status
Simulation time 178259449 ps
CPU time 0.9 seconds
Started Jul 26 05:07:38 PM PDT 24
Finished Jul 26 05:07:39 PM PDT 24
Peak memory 207040 kb
Host smart-b761aa31-194e-4ad7-9993-c773dce59551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31068
86144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.3106886144
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.4272503208
Short name T895
Test name
Test status
Simulation time 191201040 ps
CPU time 0.89 seconds
Started Jul 26 05:07:39 PM PDT 24
Finished Jul 26 05:07:40 PM PDT 24
Peak memory 207080 kb
Host smart-a721f479-4dcc-45bb-9855-2b9c8b1ce3da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42725
03208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.4272503208
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.1697208217
Short name T1831
Test name
Test status
Simulation time 195187047 ps
CPU time 0.97 seconds
Started Jul 26 05:07:40 PM PDT 24
Finished Jul 26 05:07:41 PM PDT 24
Peak memory 207076 kb
Host smart-03d68d85-7b19-40b2-8cf7-249fcf9a07a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16972
08217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.1697208217
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.2714858479
Short name T1546
Test name
Test status
Simulation time 6138792715 ps
CPU time 46.7 seconds
Started Jul 26 05:07:43 PM PDT 24
Finished Jul 26 05:08:30 PM PDT 24
Peak memory 215544 kb
Host smart-3cd2209c-a371-46c5-a307-5d66ee8cf585
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2714858479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.2714858479
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.2208287390
Short name T1799
Test name
Test status
Simulation time 224407498 ps
CPU time 0.98 seconds
Started Jul 26 05:07:36 PM PDT 24
Finished Jul 26 05:07:37 PM PDT 24
Peak memory 207100 kb
Host smart-0431a0da-c0e8-4f83-adcf-22e863f7a574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22082
87390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.2208287390
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.83567925
Short name T1518
Test name
Test status
Simulation time 181752779 ps
CPU time 0.99 seconds
Started Jul 26 05:07:38 PM PDT 24
Finished Jul 26 05:07:39 PM PDT 24
Peak memory 207072 kb
Host smart-e1f6b094-da30-4f73-93f0-14a4ee4a1ff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83567
925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.83567925
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.1199586975
Short name T1396
Test name
Test status
Simulation time 597347603 ps
CPU time 1.87 seconds
Started Jul 26 05:07:37 PM PDT 24
Finished Jul 26 05:07:39 PM PDT 24
Peak memory 207036 kb
Host smart-9ad92c0f-3e69-4b6d-b50c-30ba0e40f1da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11995
86975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.1199586975
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.2038296303
Short name T949
Test name
Test status
Simulation time 5503649616 ps
CPU time 44.3 seconds
Started Jul 26 05:07:38 PM PDT 24
Finished Jul 26 05:08:22 PM PDT 24
Peak memory 217040 kb
Host smart-0fe3d7f7-5e4c-4b1a-9c4f-07df0fbbeaf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20382
96303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.2038296303
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_timeout_missing_host_handshake.1903098189
Short name T1817
Test name
Test status
Simulation time 1565807688 ps
CPU time 9.91 seconds
Started Jul 26 05:07:29 PM PDT 24
Finished Jul 26 05:07:39 PM PDT 24
Peak memory 207304 kb
Host smart-f6e93325-a9ee-48d4-9fce-391b59b5294f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903098189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_timeout_missing_host
_handshake.1903098189
Directory /workspace/5.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.966169085
Short name T451
Test name
Test status
Simulation time 38407633 ps
CPU time 0.69 seconds
Started Jul 26 05:07:56 PM PDT 24
Finished Jul 26 05:07:57 PM PDT 24
Peak memory 207112 kb
Host smart-41533702-24ce-4c26-a49e-b3cb50a5d971
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=966169085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.966169085
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.445576785
Short name T2759
Test name
Test status
Simulation time 13422473512 ps
CPU time 16.44 seconds
Started Jul 26 05:07:37 PM PDT 24
Finished Jul 26 05:07:53 PM PDT 24
Peak memory 207344 kb
Host smart-db25f94a-3e91-4d4f-8816-eee898e2cc7d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=445576785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.445576785
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.471521422
Short name T2408
Test name
Test status
Simulation time 23446411881 ps
CPU time 28.31 seconds
Started Jul 26 05:07:45 PM PDT 24
Finished Jul 26 05:08:14 PM PDT 24
Peak memory 207356 kb
Host smart-33895b68-bace-413a-a9fc-b99ed867beee
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471521422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon
_wake_resume.471521422
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.1319181718
Short name T366
Test name
Test status
Simulation time 174977915 ps
CPU time 0.87 seconds
Started Jul 26 05:07:45 PM PDT 24
Finished Jul 26 05:07:47 PM PDT 24
Peak memory 207100 kb
Host smart-ad2b3eea-8869-49b6-a7fa-5b245515162d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13191
81718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.1319181718
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.2677525851
Short name T1448
Test name
Test status
Simulation time 201204371 ps
CPU time 0.89 seconds
Started Jul 26 05:07:38 PM PDT 24
Finished Jul 26 05:07:39 PM PDT 24
Peak memory 207180 kb
Host smart-9b0af6e8-1890-4d9d-8976-9af731c89b0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26775
25851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.2677525851
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.2007009316
Short name T379
Test name
Test status
Simulation time 490344542 ps
CPU time 1.7 seconds
Started Jul 26 05:07:44 PM PDT 24
Finished Jul 26 05:07:46 PM PDT 24
Peak memory 207140 kb
Host smart-6687f480-396b-4730-9daa-5ea7f526c528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20070
09316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.2007009316
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.2814434276
Short name T1354
Test name
Test status
Simulation time 661124629 ps
CPU time 1.88 seconds
Started Jul 26 05:07:44 PM PDT 24
Finished Jul 26 05:07:47 PM PDT 24
Peak memory 207020 kb
Host smart-73012ba3-8512-4050-b983-c29630d57b9d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2814434276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.2814434276
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.2614332305
Short name T2368
Test name
Test status
Simulation time 10826116407 ps
CPU time 22.61 seconds
Started Jul 26 05:07:44 PM PDT 24
Finished Jul 26 05:08:07 PM PDT 24
Peak memory 207436 kb
Host smart-109b884b-5272-41a9-9562-11a5edcfffa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26143
32305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.2614332305
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_device_timeout.3425577809
Short name T733
Test name
Test status
Simulation time 1369985186 ps
CPU time 8.85 seconds
Started Jul 26 05:07:43 PM PDT 24
Finished Jul 26 05:07:52 PM PDT 24
Peak memory 207272 kb
Host smart-7574362d-0085-4853-8989-7bfe8553c73b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425577809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_timeout.3425577809
Directory /workspace/6.usbdev_device_timeout/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.778885741
Short name T269
Test name
Test status
Simulation time 332779189 ps
CPU time 1.28 seconds
Started Jul 26 05:07:43 PM PDT 24
Finished Jul 26 05:07:45 PM PDT 24
Peak memory 207096 kb
Host smart-0a021764-966c-4d91-ac7b-6fe5cb987a35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77888
5741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.778885741
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.3749488800
Short name T44
Test name
Test status
Simulation time 143006231 ps
CPU time 0.88 seconds
Started Jul 26 05:07:44 PM PDT 24
Finished Jul 26 05:07:45 PM PDT 24
Peak memory 207092 kb
Host smart-f3a52061-46fc-4b4d-8dd3-c7616e278a3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37494
88800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.3749488800
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.1380841212
Short name T227
Test name
Test status
Simulation time 36172177 ps
CPU time 0.72 seconds
Started Jul 26 05:07:46 PM PDT 24
Finished Jul 26 05:07:47 PM PDT 24
Peak memory 207044 kb
Host smart-e3f4cfc0-fc0f-430b-a0af-22be04f1865c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13808
41212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.1380841212
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.4211327533
Short name T147
Test name
Test status
Simulation time 753684745 ps
CPU time 2.27 seconds
Started Jul 26 05:07:44 PM PDT 24
Finished Jul 26 05:07:46 PM PDT 24
Peak memory 207232 kb
Host smart-27ba3e80-2603-4307-b747-56f82f79d6af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42113
27533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.4211327533
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.3632509915
Short name T175
Test name
Test status
Simulation time 182647503 ps
CPU time 2 seconds
Started Jul 26 05:07:49 PM PDT 24
Finished Jul 26 05:07:52 PM PDT 24
Peak memory 207256 kb
Host smart-0f388fe8-9269-427c-b448-8bb6ff2b31d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36325
09915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.3632509915
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.3788319368
Short name T444
Test name
Test status
Simulation time 191176031 ps
CPU time 1.01 seconds
Started Jul 26 05:07:43 PM PDT 24
Finished Jul 26 05:07:44 PM PDT 24
Peak memory 207240 kb
Host smart-8aa064a9-1144-4ea6-a286-937734960038
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3788319368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.3788319368
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.1011661630
Short name T656
Test name
Test status
Simulation time 141162429 ps
CPU time 0.83 seconds
Started Jul 26 05:07:43 PM PDT 24
Finished Jul 26 05:07:44 PM PDT 24
Peak memory 207000 kb
Host smart-678b2a99-b876-48a4-bcba-2972d15c35f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10116
61630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.1011661630
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.2133309966
Short name T2662
Test name
Test status
Simulation time 245345175 ps
CPU time 1 seconds
Started Jul 26 05:07:46 PM PDT 24
Finished Jul 26 05:07:47 PM PDT 24
Peak memory 207048 kb
Host smart-634b7bba-a76f-49ee-b3c6-92fe5c44c279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21333
09966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.2133309966
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.3874656871
Short name T2107
Test name
Test status
Simulation time 4795177095 ps
CPU time 137.84 seconds
Started Jul 26 05:07:46 PM PDT 24
Finished Jul 26 05:10:04 PM PDT 24
Peak memory 215720 kb
Host smart-5535dee6-c77c-4af8-847d-61d485916529
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3874656871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.3874656871
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_iso_retraction.936265947
Short name T18
Test name
Test status
Simulation time 5371097424 ps
CPU time 34.31 seconds
Started Jul 26 05:07:45 PM PDT 24
Finished Jul 26 05:08:20 PM PDT 24
Peak memory 207304 kb
Host smart-376140ad-bced-402c-9d89-98a553c35f5d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=936265947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_iso_retraction.936265947
Directory /workspace/6.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.1766727029
Short name T2774
Test name
Test status
Simulation time 179885860 ps
CPU time 0.91 seconds
Started Jul 26 05:07:43 PM PDT 24
Finished Jul 26 05:07:45 PM PDT 24
Peak memory 207072 kb
Host smart-a581a0ef-daca-4e24-ab70-b65703bbbbb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17667
27029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.1766727029
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.2575345487
Short name T181
Test name
Test status
Simulation time 23266238584 ps
CPU time 27.7 seconds
Started Jul 26 05:07:43 PM PDT 24
Finished Jul 26 05:08:12 PM PDT 24
Peak memory 207272 kb
Host smart-eac844c4-4acb-4748-a46f-32a09e06cc38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25753
45487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.2575345487
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.991605975
Short name T1039
Test name
Test status
Simulation time 3354841666 ps
CPU time 4.88 seconds
Started Jul 26 05:07:43 PM PDT 24
Finished Jul 26 05:07:49 PM PDT 24
Peak memory 207260 kb
Host smart-908fa1f3-b82c-4063-b799-f860e9196d50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99160
5975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.991605975
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.4137318226
Short name T724
Test name
Test status
Simulation time 6412897676 ps
CPU time 66.8 seconds
Started Jul 26 05:07:44 PM PDT 24
Finished Jul 26 05:08:51 PM PDT 24
Peak memory 223744 kb
Host smart-73efb348-a730-4a35-abb0-e1bac6c50e2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41373
18226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.4137318226
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.2126344060
Short name T2382
Test name
Test status
Simulation time 3778527412 ps
CPU time 39.31 seconds
Started Jul 26 05:07:43 PM PDT 24
Finished Jul 26 05:08:23 PM PDT 24
Peak memory 216960 kb
Host smart-65e45cda-1ebe-4cf3-a312-bf8a28090a20
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2126344060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.2126344060
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.2682018270
Short name T2193
Test name
Test status
Simulation time 239513736 ps
CPU time 0.99 seconds
Started Jul 26 05:07:46 PM PDT 24
Finished Jul 26 05:07:47 PM PDT 24
Peak memory 207264 kb
Host smart-4d53995c-4033-43a6-9216-6a7617f90877
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2682018270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.2682018270
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.1180736282
Short name T1581
Test name
Test status
Simulation time 253206004 ps
CPU time 0.97 seconds
Started Jul 26 05:07:46 PM PDT 24
Finished Jul 26 05:07:47 PM PDT 24
Peak memory 207100 kb
Host smart-b318a474-6e72-4f31-b1e7-faf7f96c4009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11807
36282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.1180736282
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.1879364404
Short name T2157
Test name
Test status
Simulation time 3497340833 ps
CPU time 103.01 seconds
Started Jul 26 05:07:45 PM PDT 24
Finished Jul 26 05:09:29 PM PDT 24
Peak memory 215596 kb
Host smart-217dc805-b762-41f3-959d-8fb6a71ca82e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18793
64404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.1879364404
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.2461901932
Short name T2008
Test name
Test status
Simulation time 3567923139 ps
CPU time 109.19 seconds
Started Jul 26 05:07:47 PM PDT 24
Finished Jul 26 05:09:36 PM PDT 24
Peak memory 215516 kb
Host smart-35b38920-aed2-4efb-8a9c-9e34d7514f1f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2461901932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.2461901932
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.991153964
Short name T1503
Test name
Test status
Simulation time 210902730 ps
CPU time 0.91 seconds
Started Jul 26 05:07:46 PM PDT 24
Finished Jul 26 05:07:47 PM PDT 24
Peak memory 207136 kb
Host smart-6266d304-b28f-48fa-a900-bf4fedd8bc5c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=991153964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.991153964
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.1015357746
Short name T2514
Test name
Test status
Simulation time 148195982 ps
CPU time 0.81 seconds
Started Jul 26 05:07:44 PM PDT 24
Finished Jul 26 05:07:45 PM PDT 24
Peak memory 207124 kb
Host smart-9c9b2c23-179e-42a7-81da-f15b2e3537c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10153
57746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.1015357746
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.2596851208
Short name T111
Test name
Test status
Simulation time 199990193 ps
CPU time 0.93 seconds
Started Jul 26 05:07:43 PM PDT 24
Finished Jul 26 05:07:44 PM PDT 24
Peak memory 207100 kb
Host smart-966f8bdd-3ca3-4e07-ab85-185dd7eac8a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25968
51208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.2596851208
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.675528918
Short name T386
Test name
Test status
Simulation time 249603540 ps
CPU time 0.98 seconds
Started Jul 26 05:07:49 PM PDT 24
Finished Jul 26 05:07:51 PM PDT 24
Peak memory 207100 kb
Host smart-da95eee8-541a-4b77-87f0-5e9b562c17ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67552
8918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.675528918
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.3526706802
Short name T31
Test name
Test status
Simulation time 190516675 ps
CPU time 0.92 seconds
Started Jul 26 05:07:46 PM PDT 24
Finished Jul 26 05:07:47 PM PDT 24
Peak memory 207264 kb
Host smart-86d9db1e-ee3c-40c7-a59b-e11ce543e9c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35267
06802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.3526706802
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.3916577810
Short name T272
Test name
Test status
Simulation time 214751666 ps
CPU time 0.96 seconds
Started Jul 26 05:07:43 PM PDT 24
Finished Jul 26 05:07:45 PM PDT 24
Peak memory 206976 kb
Host smart-d6a440df-5e8e-4bdf-9a9e-899678fe8250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39165
77810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.3916577810
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.872652584
Short name T2773
Test name
Test status
Simulation time 160321479 ps
CPU time 0.86 seconds
Started Jul 26 05:07:45 PM PDT 24
Finished Jul 26 05:07:46 PM PDT 24
Peak memory 207104 kb
Host smart-ba8e1927-1c8a-4c5d-891b-12de6ec0b7b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87265
2584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.872652584
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.4186979416
Short name T2825
Test name
Test status
Simulation time 259234681 ps
CPU time 1.07 seconds
Started Jul 26 05:07:45 PM PDT 24
Finished Jul 26 05:07:46 PM PDT 24
Peak memory 207108 kb
Host smart-8d7725f6-c84b-4acf-b1ef-c1e3cd9f7559
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4186979416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.4186979416
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.2647023156
Short name T578
Test name
Test status
Simulation time 148006873 ps
CPU time 0.86 seconds
Started Jul 26 05:07:46 PM PDT 24
Finished Jul 26 05:07:47 PM PDT 24
Peak memory 207008 kb
Host smart-fe3a9e70-8f1a-4857-bbbb-7d5339673adc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26470
23156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.2647023156
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.1946716453
Short name T1065
Test name
Test status
Simulation time 40728517 ps
CPU time 0.71 seconds
Started Jul 26 05:07:43 PM PDT 24
Finished Jul 26 05:07:44 PM PDT 24
Peak memory 207084 kb
Host smart-2ab6663c-1297-4e57-b208-fc07577095ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19467
16453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.1946716453
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.4081159358
Short name T2421
Test name
Test status
Simulation time 10607933668 ps
CPU time 28.91 seconds
Started Jul 26 05:07:46 PM PDT 24
Finished Jul 26 05:08:15 PM PDT 24
Peak memory 215540 kb
Host smart-45863c2a-4839-46c5-acb1-0c9504d79901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40811
59358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.4081159358
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.2500469122
Short name T2249
Test name
Test status
Simulation time 183557629 ps
CPU time 0.87 seconds
Started Jul 26 05:07:45 PM PDT 24
Finished Jul 26 05:07:47 PM PDT 24
Peak memory 207080 kb
Host smart-b8c2506a-e032-4b65-bb77-9a04f00b9938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25004
69122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.2500469122
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.1575617089
Short name T2780
Test name
Test status
Simulation time 247755431 ps
CPU time 1.06 seconds
Started Jul 26 05:07:44 PM PDT 24
Finished Jul 26 05:07:45 PM PDT 24
Peak memory 207000 kb
Host smart-d74d996d-dab5-4a10-9093-9a0e6f900d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15756
17089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.1575617089
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.2119681588
Short name T1580
Test name
Test status
Simulation time 11904186432 ps
CPU time 66.38 seconds
Started Jul 26 05:07:45 PM PDT 24
Finished Jul 26 05:08:52 PM PDT 24
Peak memory 217604 kb
Host smart-b5e1557f-0104-4192-9c34-e5ea8915b952
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119681588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.2119681588
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.3636101804
Short name T160
Test name
Test status
Simulation time 12189268285 ps
CPU time 93.89 seconds
Started Jul 26 05:07:49 PM PDT 24
Finished Jul 26 05:09:24 PM PDT 24
Peak memory 218052 kb
Host smart-53681d99-a493-49ac-85cb-0c2dcc372030
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3636101804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.3636101804
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.1952867927
Short name T1112
Test name
Test status
Simulation time 15068135942 ps
CPU time 325.82 seconds
Started Jul 26 05:07:58 PM PDT 24
Finished Jul 26 05:13:24 PM PDT 24
Peak memory 215632 kb
Host smart-7c000431-c398-4edc-826d-13466c1a9ead
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952867927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.1952867927
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.3518391744
Short name T1149
Test name
Test status
Simulation time 229628508 ps
CPU time 0.95 seconds
Started Jul 26 05:07:46 PM PDT 24
Finished Jul 26 05:07:47 PM PDT 24
Peak memory 207100 kb
Host smart-8e8e3760-17ce-4758-9232-11c23c42e912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35183
91744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.3518391744
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.3218021892
Short name T723
Test name
Test status
Simulation time 168185189 ps
CPU time 0.89 seconds
Started Jul 26 05:07:44 PM PDT 24
Finished Jul 26 05:07:45 PM PDT 24
Peak memory 207332 kb
Host smart-c592a83b-9bd9-4311-92cb-184152ef5fdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32180
21892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.3218021892
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.250634988
Short name T2595
Test name
Test status
Simulation time 139516941 ps
CPU time 0.84 seconds
Started Jul 26 05:08:03 PM PDT 24
Finished Jul 26 05:08:04 PM PDT 24
Peak memory 206980 kb
Host smart-6fe3e49b-473a-4933-a08b-9fe79f4e2ef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25063
4988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.250634988
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.304455138
Short name T626
Test name
Test status
Simulation time 162416611 ps
CPU time 0.91 seconds
Started Jul 26 05:07:55 PM PDT 24
Finished Jul 26 05:07:56 PM PDT 24
Peak memory 207136 kb
Host smart-1d896589-babd-4445-b20d-150b4d6933a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30445
5138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.304455138
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.4281254727
Short name T2397
Test name
Test status
Simulation time 154262524 ps
CPU time 0.86 seconds
Started Jul 26 05:07:57 PM PDT 24
Finished Jul 26 05:07:58 PM PDT 24
Peak memory 207124 kb
Host smart-b96ee285-230a-47e5-80a9-8450096771f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42812
54727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.4281254727
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.1850810022
Short name T1454
Test name
Test status
Simulation time 211225553 ps
CPU time 0.97 seconds
Started Jul 26 05:07:54 PM PDT 24
Finished Jul 26 05:07:55 PM PDT 24
Peak memory 207040 kb
Host smart-36551075-0b54-4e82-95f4-173a938d9c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18508
10022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.1850810022
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.1267720497
Short name T2097
Test name
Test status
Simulation time 4364366548 ps
CPU time 34.13 seconds
Started Jul 26 05:07:56 PM PDT 24
Finished Jul 26 05:08:30 PM PDT 24
Peak memory 215564 kb
Host smart-ce33295a-bc22-4de0-8537-e52e4cf00180
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1267720497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.1267720497
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.3700784662
Short name T487
Test name
Test status
Simulation time 185596743 ps
CPU time 0.95 seconds
Started Jul 26 05:07:56 PM PDT 24
Finished Jul 26 05:07:57 PM PDT 24
Peak memory 207148 kb
Host smart-d9dfc70d-4623-4d8d-be9d-08587817069d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37007
84662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.3700784662
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.2243782967
Short name T1424
Test name
Test status
Simulation time 165688612 ps
CPU time 0.87 seconds
Started Jul 26 05:07:56 PM PDT 24
Finished Jul 26 05:07:57 PM PDT 24
Peak memory 207132 kb
Host smart-75c7197e-d84f-4525-b8a7-9d680a72ad2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22437
82967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.2243782967
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.2021128681
Short name T1647
Test name
Test status
Simulation time 794376181 ps
CPU time 1.93 seconds
Started Jul 26 05:07:56 PM PDT 24
Finished Jul 26 05:07:58 PM PDT 24
Peak memory 207100 kb
Host smart-d401560f-e44e-42a2-8f26-524fe773c986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20211
28681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.2021128681
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.1852397470
Short name T700
Test name
Test status
Simulation time 4806394352 ps
CPU time 146.86 seconds
Started Jul 26 05:07:56 PM PDT 24
Finished Jul 26 05:10:23 PM PDT 24
Peak memory 215484 kb
Host smart-6bdeaedd-692a-426e-ac5f-6e02a7d18c3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18523
97470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.1852397470
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_timeout_missing_host_handshake.1482838960
Short name T459
Test name
Test status
Simulation time 3436017939 ps
CPU time 27.96 seconds
Started Jul 26 05:07:45 PM PDT 24
Finished Jul 26 05:08:14 PM PDT 24
Peak memory 207424 kb
Host smart-ea8afa65-5cc8-41f0-97bd-f132340bebf0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482838960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_timeout_missing_host
_handshake.1482838960
Directory /workspace/6.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.2577609312
Short name T1463
Test name
Test status
Simulation time 64493753 ps
CPU time 0.69 seconds
Started Jul 26 05:08:25 PM PDT 24
Finished Jul 26 05:08:26 PM PDT 24
Peak memory 207016 kb
Host smart-404b93b9-71c1-4e9f-832e-041f47432799
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2577609312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.2577609312
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.3267190278
Short name T885
Test name
Test status
Simulation time 4124461168 ps
CPU time 6.04 seconds
Started Jul 26 05:18:21 PM PDT 24
Finished Jul 26 05:18:28 PM PDT 24
Peak memory 207360 kb
Host smart-f33b5cd4-60b2-42a8-a56a-59b9ddbcb43a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267190278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ao
n_wake_disconnect.3267190278
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.815722696
Short name T2473
Test name
Test status
Simulation time 13355802484 ps
CPU time 16 seconds
Started Jul 26 05:38:54 PM PDT 24
Finished Jul 26 05:39:10 PM PDT 24
Peak memory 207332 kb
Host smart-4445a703-0feb-45c3-bd38-c5108d732662
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=815722696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.815722696
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.3761629009
Short name T1808
Test name
Test status
Simulation time 23423552974 ps
CPU time 28.26 seconds
Started Jul 26 05:16:13 PM PDT 24
Finished Jul 26 05:16:42 PM PDT 24
Peak memory 207304 kb
Host smart-f5eb0084-6a0d-4725-bced-2b385b725cd5
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761629009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ao
n_wake_resume.3761629009
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.2466853187
Short name T671
Test name
Test status
Simulation time 191445901 ps
CPU time 0.95 seconds
Started Jul 26 05:08:39 PM PDT 24
Finished Jul 26 05:08:40 PM PDT 24
Peak memory 207100 kb
Host smart-328019e8-6708-4ee3-8f68-f3745b3874e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24668
53187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2466853187
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.2036911778
Short name T2052
Test name
Test status
Simulation time 152469361 ps
CPU time 0.91 seconds
Started Jul 26 05:46:32 PM PDT 24
Finished Jul 26 05:46:33 PM PDT 24
Peak memory 207040 kb
Host smart-58fd7427-ac29-4c0c-91e2-f90a5ae9e841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20369
11778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.2036911778
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.3711892234
Short name T1199
Test name
Test status
Simulation time 614330952 ps
CPU time 1.93 seconds
Started Jul 26 05:39:53 PM PDT 24
Finished Jul 26 05:39:55 PM PDT 24
Peak memory 207084 kb
Host smart-b26a3328-65a2-4bff-afec-6c12a267a453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37118
92234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.3711892234
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_device_address.2059190689
Short name T1486
Test name
Test status
Simulation time 13765664704 ps
CPU time 28.65 seconds
Started Jul 26 05:07:55 PM PDT 24
Finished Jul 26 05:08:24 PM PDT 24
Peak memory 207288 kb
Host smart-5db2f765-dde5-43b7-ad10-f84f053fd09c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20591
90689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.2059190689
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_device_timeout.1566513682
Short name T1044
Test name
Test status
Simulation time 2546912619 ps
CPU time 20.53 seconds
Started Jul 26 05:34:14 PM PDT 24
Finished Jul 26 05:34:34 PM PDT 24
Peak memory 207296 kb
Host smart-7296c219-c566-4393-9404-91824fe5b13b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566513682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_timeout.1566513682
Directory /workspace/7.usbdev_device_timeout/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.898954142
Short name T495
Test name
Test status
Simulation time 495460902 ps
CPU time 1.7 seconds
Started Jul 26 05:07:58 PM PDT 24
Finished Jul 26 05:08:00 PM PDT 24
Peak memory 207084 kb
Host smart-a7044204-bfc9-41ff-88b2-984cf826cb8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89895
4142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.898954142
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.3168837808
Short name T776
Test name
Test status
Simulation time 153101837 ps
CPU time 0.86 seconds
Started Jul 26 05:18:44 PM PDT 24
Finished Jul 26 05:18:45 PM PDT 24
Peak memory 207068 kb
Host smart-9dc25f5c-7571-4eb0-9c67-74d5bad8e776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31688
37808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.3168837808
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.2649166297
Short name T1594
Test name
Test status
Simulation time 55004658 ps
CPU time 0.73 seconds
Started Jul 26 05:15:52 PM PDT 24
Finished Jul 26 05:15:53 PM PDT 24
Peak memory 207064 kb
Host smart-cbe61540-f80a-4d9b-8246-7d83c3fb695d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26491
66297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.2649166297
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.724592171
Short name T601
Test name
Test status
Simulation time 1021038682 ps
CPU time 2.8 seconds
Started Jul 26 05:07:55 PM PDT 24
Finished Jul 26 05:07:58 PM PDT 24
Peak memory 207324 kb
Host smart-9cad65ff-e981-4e1d-891c-dd9be45cae7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72459
2171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.724592171
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.2503944599
Short name T1498
Test name
Test status
Simulation time 163596089 ps
CPU time 1.74 seconds
Started Jul 26 05:07:55 PM PDT 24
Finished Jul 26 05:07:57 PM PDT 24
Peak memory 207256 kb
Host smart-c6d46d10-88ea-4d22-95f4-78a3ab59fc62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25039
44599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.2503944599
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.901773809
Short name T1695
Test name
Test status
Simulation time 179611670 ps
CPU time 1.01 seconds
Started Jul 26 05:08:03 PM PDT 24
Finished Jul 26 05:08:04 PM PDT 24
Peak memory 207084 kb
Host smart-c98af5a1-dbc0-43b3-91b1-4eb0447ede04
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=901773809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.901773809
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.1639568676
Short name T1598
Test name
Test status
Simulation time 153140166 ps
CPU time 0.83 seconds
Started Jul 26 05:08:04 PM PDT 24
Finished Jul 26 05:08:05 PM PDT 24
Peak memory 207072 kb
Host smart-0fca6020-61a1-435d-bfbf-542ce6f87b99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16395
68676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.1639568676
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.4250045927
Short name T2215
Test name
Test status
Simulation time 174255513 ps
CPU time 0.99 seconds
Started Jul 26 05:08:03 PM PDT 24
Finished Jul 26 05:08:05 PM PDT 24
Peak memory 207100 kb
Host smart-137a49fd-bd19-49c0-b029-9015972fb137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42500
45927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.4250045927
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_invalid_sync.1294436365
Short name T888
Test name
Test status
Simulation time 10458452831 ps
CPU time 309.64 seconds
Started Jul 26 05:08:03 PM PDT 24
Finished Jul 26 05:13:13 PM PDT 24
Peak memory 215612 kb
Host smart-fe9ea56d-0346-4b6a-974a-6c02709ce399
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1294436365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.1294436365
Directory /workspace/7.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/7.usbdev_iso_retraction.729268726
Short name T1371
Test name
Test status
Simulation time 14621899559 ps
CPU time 100.15 seconds
Started Jul 26 05:08:06 PM PDT 24
Finished Jul 26 05:09:46 PM PDT 24
Peak memory 207356 kb
Host smart-f7dcce0f-0b27-487c-aab3-b09d65e5e304
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=729268726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.729268726
Directory /workspace/7.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.1119592138
Short name T761
Test name
Test status
Simulation time 239890798 ps
CPU time 1.03 seconds
Started Jul 26 05:08:03 PM PDT 24
Finished Jul 26 05:08:05 PM PDT 24
Peak memory 206984 kb
Host smart-0cd23e84-4137-4540-b9d0-0e427fccebd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11195
92138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.1119592138
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.1532305708
Short name T2544
Test name
Test status
Simulation time 23335825848 ps
CPU time 30.02 seconds
Started Jul 26 05:08:06 PM PDT 24
Finished Jul 26 05:08:36 PM PDT 24
Peak memory 207284 kb
Host smart-cf896fa0-717e-4e61-b909-9eb693c0c6a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15323
05708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.1532305708
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.3970279019
Short name T1394
Test name
Test status
Simulation time 3296263154 ps
CPU time 4.66 seconds
Started Jul 26 05:08:05 PM PDT 24
Finished Jul 26 05:08:10 PM PDT 24
Peak memory 207268 kb
Host smart-7ccf4e35-b04b-4c75-bb3c-286e062add2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39702
79019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.3970279019
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.840312649
Short name T298
Test name
Test status
Simulation time 6395075272 ps
CPU time 46.48 seconds
Started Jul 26 05:08:03 PM PDT 24
Finished Jul 26 05:08:50 PM PDT 24
Peak memory 223580 kb
Host smart-b4e8d879-a432-423f-bc14-c7255f58a2d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84031
2649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.840312649
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.4056880896
Short name T2736
Test name
Test status
Simulation time 4953937112 ps
CPU time 59.06 seconds
Started Jul 26 05:08:03 PM PDT 24
Finished Jul 26 05:09:03 PM PDT 24
Peak memory 207280 kb
Host smart-776fbcf1-a045-46cf-836e-23ab08d85d2a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4056880896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.4056880896
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.2663967702
Short name T2153
Test name
Test status
Simulation time 283987647 ps
CPU time 1.07 seconds
Started Jul 26 05:08:04 PM PDT 24
Finished Jul 26 05:08:05 PM PDT 24
Peak memory 207060 kb
Host smart-e687a215-ecc5-42b5-8782-87a0cd772337
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2663967702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.2663967702
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.3396017637
Short name T2467
Test name
Test status
Simulation time 229756788 ps
CPU time 1 seconds
Started Jul 26 05:08:03 PM PDT 24
Finished Jul 26 05:08:05 PM PDT 24
Peak memory 207000 kb
Host smart-54ad4fa0-2b9d-44dc-a5ea-d9731db97a60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33960
17637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.3396017637
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.2856560614
Short name T1484
Test name
Test status
Simulation time 6451011209 ps
CPU time 197.41 seconds
Started Jul 26 05:08:02 PM PDT 24
Finished Jul 26 05:11:20 PM PDT 24
Peak memory 215500 kb
Host smart-3e157b76-c9bb-47f1-b5c8-d6817126da76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28565
60614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.2856560614
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.41137848
Short name T870
Test name
Test status
Simulation time 5252845369 ps
CPU time 161.17 seconds
Started Jul 26 05:08:04 PM PDT 24
Finished Jul 26 05:10:46 PM PDT 24
Peak memory 215580 kb
Host smart-6133c5b9-b855-4b0b-a5cd-9c2808b6ce0d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=41137848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.41137848
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.38731412
Short name T1313
Test name
Test status
Simulation time 151561244 ps
CPU time 0.89 seconds
Started Jul 26 05:08:03 PM PDT 24
Finished Jul 26 05:08:05 PM PDT 24
Peak memory 207072 kb
Host smart-52cbcad4-a0fd-4baf-bd4a-6e5075c04145
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=38731412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.38731412
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.4170842496
Short name T948
Test name
Test status
Simulation time 205485630 ps
CPU time 0.92 seconds
Started Jul 26 05:08:05 PM PDT 24
Finished Jul 26 05:08:06 PM PDT 24
Peak memory 207148 kb
Host smart-c4950eab-59d6-4b04-84b3-8d3259ffa6dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41708
42496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.4170842496
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.3170139818
Short name T131
Test name
Test status
Simulation time 189511419 ps
CPU time 0.91 seconds
Started Jul 26 05:08:09 PM PDT 24
Finished Jul 26 05:08:10 PM PDT 24
Peak memory 207040 kb
Host smart-37826dd9-b2e8-4a3e-a858-c0538276017b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31701
39818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.3170139818
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.2663646088
Short name T1289
Test name
Test status
Simulation time 179220005 ps
CPU time 0.84 seconds
Started Jul 26 05:08:05 PM PDT 24
Finished Jul 26 05:08:06 PM PDT 24
Peak memory 207048 kb
Host smart-31891b6d-070b-43cb-89b9-42ad1d001739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26636
46088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.2663646088
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.614388623
Short name T1399
Test name
Test status
Simulation time 169079404 ps
CPU time 0.93 seconds
Started Jul 26 05:08:08 PM PDT 24
Finished Jul 26 05:08:09 PM PDT 24
Peak memory 207104 kb
Host smart-f5548240-57a1-4e1e-af57-7126352b91cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61438
8623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.614388623
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.1360158028
Short name T1734
Test name
Test status
Simulation time 232854979 ps
CPU time 1.02 seconds
Started Jul 26 05:08:03 PM PDT 24
Finished Jul 26 05:08:05 PM PDT 24
Peak memory 207096 kb
Host smart-43502934-6784-4757-877d-8a2df7b13d43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13601
58028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.1360158028
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.552016474
Short name T1676
Test name
Test status
Simulation time 147576596 ps
CPU time 0.87 seconds
Started Jul 26 05:08:03 PM PDT 24
Finished Jul 26 05:08:04 PM PDT 24
Peak memory 207088 kb
Host smart-f7e000b7-6697-4eaf-9a45-7de0a8c8c1e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55201
6474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.552016474
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.3045941573
Short name T1818
Test name
Test status
Simulation time 198284018 ps
CPU time 1.03 seconds
Started Jul 26 05:08:03 PM PDT 24
Finished Jul 26 05:08:04 PM PDT 24
Peak memory 207140 kb
Host smart-0171ccd2-23a7-4d1d-b3b7-2c607ba995b7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3045941573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.3045941573
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.3305902262
Short name T1128
Test name
Test status
Simulation time 142888767 ps
CPU time 0.86 seconds
Started Jul 26 05:08:09 PM PDT 24
Finished Jul 26 05:08:10 PM PDT 24
Peak memory 207060 kb
Host smart-35926eb1-a240-4904-8b38-96d752dbfbf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33059
02262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.3305902262
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.816568283
Short name T25
Test name
Test status
Simulation time 45371695 ps
CPU time 0.68 seconds
Started Jul 26 05:08:04 PM PDT 24
Finished Jul 26 05:08:05 PM PDT 24
Peak memory 207100 kb
Host smart-c8cb1a2e-4da4-4dd7-9b8a-e00b069a1e1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81656
8283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.816568283
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.2278741424
Short name T2392
Test name
Test status
Simulation time 7136966180 ps
CPU time 18.02 seconds
Started Jul 26 05:08:06 PM PDT 24
Finished Jul 26 05:08:24 PM PDT 24
Peak memory 215508 kb
Host smart-f3a9f550-e26e-41e6-a0bb-d304e14f3664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22787
41424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.2278741424
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.2114001205
Short name T2311
Test name
Test status
Simulation time 191211454 ps
CPU time 0.9 seconds
Started Jul 26 05:08:03 PM PDT 24
Finished Jul 26 05:08:04 PM PDT 24
Peak memory 207024 kb
Host smart-d0b823b2-97cf-4f48-8d6b-ab89e1c11d29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21140
01205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.2114001205
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.441049182
Short name T559
Test name
Test status
Simulation time 242495651 ps
CPU time 0.98 seconds
Started Jul 26 05:08:03 PM PDT 24
Finished Jul 26 05:08:04 PM PDT 24
Peak memory 207036 kb
Host smart-45463e97-2ee4-49ee-9dd1-d56f3bcad0ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44104
9182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.441049182
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.3651473915
Short name T161
Test name
Test status
Simulation time 8402092494 ps
CPU time 49.15 seconds
Started Jul 26 05:08:04 PM PDT 24
Finished Jul 26 05:08:53 PM PDT 24
Peak memory 218880 kb
Host smart-44c954fa-dedc-4a4c-a0f6-1f2d3409e12e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651473915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.3651473915
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.2883260127
Short name T1672
Test name
Test status
Simulation time 13377904689 ps
CPU time 80.71 seconds
Started Jul 26 05:08:05 PM PDT 24
Finished Jul 26 05:09:26 PM PDT 24
Peak memory 218860 kb
Host smart-55d86ada-8197-41f8-b3ac-705aea997d44
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2883260127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.2883260127
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.2534841572
Short name T1868
Test name
Test status
Simulation time 19834520355 ps
CPU time 495.58 seconds
Started Jul 26 05:08:03 PM PDT 24
Finished Jul 26 05:16:19 PM PDT 24
Peak memory 215580 kb
Host smart-6fd5bc53-a69d-48bf-8b80-048e69f48ca1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534841572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.2534841572
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.3687787833
Short name T2578
Test name
Test status
Simulation time 228999892 ps
CPU time 1.02 seconds
Started Jul 26 05:08:05 PM PDT 24
Finished Jul 26 05:08:06 PM PDT 24
Peak memory 207124 kb
Host smart-1f1a3133-57e6-49b7-b150-98d630011826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36877
87833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.3687787833
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.493131041
Short name T1999
Test name
Test status
Simulation time 172008375 ps
CPU time 0.87 seconds
Started Jul 26 05:08:08 PM PDT 24
Finished Jul 26 05:08:09 PM PDT 24
Peak memory 207100 kb
Host smart-63991ba6-15e8-40ec-ab7d-47178b6bfe84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49313
1041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.493131041
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.3027772405
Short name T2764
Test name
Test status
Simulation time 145069630 ps
CPU time 0.88 seconds
Started Jul 26 05:08:00 PM PDT 24
Finished Jul 26 05:08:01 PM PDT 24
Peak memory 207116 kb
Host smart-dab55463-a7ad-4fec-9b88-f1946dec305c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30277
72405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.3027772405
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.1877132771
Short name T1640
Test name
Test status
Simulation time 209056080 ps
CPU time 0.88 seconds
Started Jul 26 05:08:05 PM PDT 24
Finished Jul 26 05:08:06 PM PDT 24
Peak memory 206988 kb
Host smart-34a68fda-8fd5-4a75-9daf-7678ff854ebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18771
32771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.1877132771
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.1500905082
Short name T276
Test name
Test status
Simulation time 148008375 ps
CPU time 0.85 seconds
Started Jul 26 05:08:03 PM PDT 24
Finished Jul 26 05:08:04 PM PDT 24
Peak memory 206976 kb
Host smart-52874e3a-13b1-4443-aa4c-bb7427955875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15009
05082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.1500905082
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.1070229079
Short name T963
Test name
Test status
Simulation time 220158638 ps
CPU time 0.97 seconds
Started Jul 26 05:08:07 PM PDT 24
Finished Jul 26 05:08:08 PM PDT 24
Peak memory 207044 kb
Host smart-abe7d806-2426-4238-a25a-307b9959eb43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10702
29079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.1070229079
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.1358749038
Short name T383
Test name
Test status
Simulation time 7044228022 ps
CPU time 54.41 seconds
Started Jul 26 05:08:03 PM PDT 24
Finished Jul 26 05:08:58 PM PDT 24
Peak memory 207376 kb
Host smart-581ee41b-34b2-4c13-8735-332aaf385ab7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1358749038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.1358749038
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.940826021
Short name T1441
Test name
Test status
Simulation time 188304308 ps
CPU time 1.05 seconds
Started Jul 26 05:08:02 PM PDT 24
Finished Jul 26 05:08:03 PM PDT 24
Peak memory 207052 kb
Host smart-b4c5c3b8-2e66-4c89-8dde-c92e282d2063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94082
6021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.940826021
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.223361645
Short name T1910
Test name
Test status
Simulation time 172629807 ps
CPU time 0.87 seconds
Started Jul 26 05:08:04 PM PDT 24
Finished Jul 26 05:08:05 PM PDT 24
Peak memory 207028 kb
Host smart-0fbc5ca6-f7bf-4ca2-ba87-9ff64007d565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22336
1645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.223361645
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.2647256618
Short name T2279
Test name
Test status
Simulation time 512127715 ps
CPU time 1.62 seconds
Started Jul 26 05:08:10 PM PDT 24
Finished Jul 26 05:08:12 PM PDT 24
Peak memory 206964 kb
Host smart-e453e0f4-f5e8-42f5-8110-adb471d37589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26472
56618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.2647256618
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.4051701556
Short name T554
Test name
Test status
Simulation time 3337341331 ps
CPU time 24.75 seconds
Started Jul 26 05:08:10 PM PDT 24
Finished Jul 26 05:08:35 PM PDT 24
Peak memory 216648 kb
Host smart-0d0fc2bd-1b80-48f1-8520-9bd9a1fb8678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40517
01556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.4051701556
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_timeout_missing_host_handshake.4013280222
Short name T2697
Test name
Test status
Simulation time 752035847 ps
CPU time 5.33 seconds
Started Jul 26 05:16:44 PM PDT 24
Finished Jul 26 05:16:50 PM PDT 24
Peak memory 207228 kb
Host smart-d8e99dcd-02eb-4b2b-8f58-2e6f402a77f6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013280222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_timeout_missing_host
_handshake.4013280222
Directory /workspace/7.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.3484882088
Short name T1137
Test name
Test status
Simulation time 69133010 ps
CPU time 0.72 seconds
Started Jul 26 05:08:29 PM PDT 24
Finished Jul 26 05:08:30 PM PDT 24
Peak memory 207168 kb
Host smart-b67f4462-3532-4099-b0da-982e4855ed61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3484882088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.3484882088
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.1990868500
Short name T524
Test name
Test status
Simulation time 3506060604 ps
CPU time 5.47 seconds
Started Jul 26 05:08:15 PM PDT 24
Finished Jul 26 05:08:21 PM PDT 24
Peak memory 207452 kb
Host smart-543dcbff-ce13-4e21-98f9-c389a522526c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990868500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ao
n_wake_disconnect.1990868500
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.1690962469
Short name T1412
Test name
Test status
Simulation time 13491414426 ps
CPU time 17.41 seconds
Started Jul 26 05:08:30 PM PDT 24
Finished Jul 26 05:08:47 PM PDT 24
Peak memory 207444 kb
Host smart-21cf1e6c-5082-4e1e-a203-324b70e9d1ca
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690962469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.1690962469
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.1587474149
Short name T11
Test name
Test status
Simulation time 23535310258 ps
CPU time 29.82 seconds
Started Jul 26 05:08:14 PM PDT 24
Finished Jul 26 05:08:44 PM PDT 24
Peak memory 207332 kb
Host smart-950a2981-ecca-46bd-8728-27139455d893
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587474149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ao
n_wake_resume.1587474149
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.2963294165
Short name T2582
Test name
Test status
Simulation time 152327713 ps
CPU time 0.88 seconds
Started Jul 26 05:08:13 PM PDT 24
Finished Jul 26 05:08:14 PM PDT 24
Peak memory 207100 kb
Host smart-090d30a7-0e8a-4453-9107-6cf45518b498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29632
94165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.2963294165
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.3567569774
Short name T1517
Test name
Test status
Simulation time 181653841 ps
CPU time 0.89 seconds
Started Jul 26 05:08:12 PM PDT 24
Finished Jul 26 05:08:13 PM PDT 24
Peak memory 207016 kb
Host smart-8e4f16ba-9d7d-4f87-8317-f8ad2a016551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35675
69774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.3567569774
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.2887011075
Short name T2671
Test name
Test status
Simulation time 464954799 ps
CPU time 1.57 seconds
Started Jul 26 05:08:14 PM PDT 24
Finished Jul 26 05:08:15 PM PDT 24
Peak memory 207024 kb
Host smart-21bec075-39a1-40e7-91b9-6f8d1cd6eac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28870
11075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.2887011075
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.4137840670
Short name T1431
Test name
Test status
Simulation time 1511847134 ps
CPU time 3.95 seconds
Started Jul 26 05:08:25 PM PDT 24
Finished Jul 26 05:08:29 PM PDT 24
Peak memory 207232 kb
Host smart-fae3783c-29bf-493e-b185-3d08e583e357
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4137840670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.4137840670
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.3154097180
Short name T1843
Test name
Test status
Simulation time 12755052521 ps
CPU time 27.26 seconds
Started Jul 26 05:08:17 PM PDT 24
Finished Jul 26 05:08:44 PM PDT 24
Peak memory 207240 kb
Host smart-e51d92b7-6bfb-4299-baaa-76a947b0be35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31540
97180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.3154097180
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_device_timeout.235423195
Short name T1969
Test name
Test status
Simulation time 6368491006 ps
CPU time 42.27 seconds
Started Jul 26 05:08:15 PM PDT 24
Finished Jul 26 05:08:57 PM PDT 24
Peak memory 207444 kb
Host smart-684e29a3-f4a4-40b7-a2f3-9ead4c93abfd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235423195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_timeout.235423195
Directory /workspace/8.usbdev_device_timeout/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.2208019441
Short name T2761
Test name
Test status
Simulation time 360051481 ps
CPU time 1.32 seconds
Started Jul 26 05:08:15 PM PDT 24
Finished Jul 26 05:08:17 PM PDT 24
Peak memory 207176 kb
Host smart-512cc711-9ded-4839-97df-75cd25c91766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22080
19441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.2208019441
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.1541436508
Short name T936
Test name
Test status
Simulation time 167264498 ps
CPU time 0.84 seconds
Started Jul 26 05:08:13 PM PDT 24
Finished Jul 26 05:08:14 PM PDT 24
Peak memory 207128 kb
Host smart-56018d30-ab41-4f40-9e7d-c7b34e4f0873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15414
36508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.1541436508
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.2190572654
Short name T2458
Test name
Test status
Simulation time 38476683 ps
CPU time 0.73 seconds
Started Jul 26 05:08:25 PM PDT 24
Finished Jul 26 05:08:25 PM PDT 24
Peak memory 206952 kb
Host smart-dc787966-b262-4344-882e-c019c4497577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21905
72654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.2190572654
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.279054223
Short name T1648
Test name
Test status
Simulation time 959192198 ps
CPU time 2.5 seconds
Started Jul 26 05:08:25 PM PDT 24
Finished Jul 26 05:08:28 PM PDT 24
Peak memory 207232 kb
Host smart-bb9d9c0a-3252-4768-a68e-f8077aee7e67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27905
4223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.279054223
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.2418811854
Short name T814
Test name
Test status
Simulation time 163375303 ps
CPU time 1.71 seconds
Started Jul 26 05:08:14 PM PDT 24
Finished Jul 26 05:08:16 PM PDT 24
Peak memory 207284 kb
Host smart-cdcba865-eebe-4b05-9859-0a5d27ed7054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24188
11854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.2418811854
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.2442492400
Short name T1651
Test name
Test status
Simulation time 159917769 ps
CPU time 0.9 seconds
Started Jul 26 05:08:14 PM PDT 24
Finished Jul 26 05:08:15 PM PDT 24
Peak memory 207148 kb
Host smart-5041b45c-7493-4a5d-838d-59834e68c54f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2442492400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.2442492400
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.3657980912
Short name T1005
Test name
Test status
Simulation time 163420292 ps
CPU time 0.86 seconds
Started Jul 26 05:08:12 PM PDT 24
Finished Jul 26 05:08:13 PM PDT 24
Peak memory 207048 kb
Host smart-78e7a9f5-19c3-4d62-9224-3736ef39469a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36579
80912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.3657980912
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.3974548815
Short name T579
Test name
Test status
Simulation time 195701908 ps
CPU time 0.96 seconds
Started Jul 26 05:08:15 PM PDT 24
Finished Jul 26 05:08:16 PM PDT 24
Peak memory 207020 kb
Host smart-b279f40a-41c9-4070-a53e-9e6a357bace2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39745
48815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.3974548815
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_invalid_sync.1380115512
Short name T2423
Test name
Test status
Simulation time 6570779220 ps
CPU time 68.83 seconds
Started Jul 26 05:08:13 PM PDT 24
Finished Jul 26 05:09:22 PM PDT 24
Peak memory 217048 kb
Host smart-eb42e8db-f108-4a17-9bd6-80ae9fc1c859
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1380115512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.1380115512
Directory /workspace/8.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/8.usbdev_iso_retraction.1145333577
Short name T1288
Test name
Test status
Simulation time 11018957811 ps
CPU time 72.59 seconds
Started Jul 26 05:08:14 PM PDT 24
Finished Jul 26 05:09:27 PM PDT 24
Peak memory 207356 kb
Host smart-98243a42-1701-499a-bfc6-e8a711a3d302
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1145333577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_iso_retraction.1145333577
Directory /workspace/8.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.3610911869
Short name T1341
Test name
Test status
Simulation time 211907231 ps
CPU time 0.96 seconds
Started Jul 26 05:08:15 PM PDT 24
Finished Jul 26 05:08:16 PM PDT 24
Peak memory 207064 kb
Host smart-ca5e3d03-f881-4140-bb56-65d1b44b4279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36109
11869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.3610911869
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.2932859183
Short name T278
Test name
Test status
Simulation time 23343052984 ps
CPU time 35.17 seconds
Started Jul 26 05:08:12 PM PDT 24
Finished Jul 26 05:08:48 PM PDT 24
Peak memory 207176 kb
Host smart-7e01b296-821f-49ae-9e10-cd1428475cbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29328
59183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.2932859183
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.1922900018
Short name T2220
Test name
Test status
Simulation time 3332359432 ps
CPU time 5.13 seconds
Started Jul 26 05:08:13 PM PDT 24
Finished Jul 26 05:08:19 PM PDT 24
Peak memory 207376 kb
Host smart-0e377ca6-8e52-498b-a00c-cc934666063d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19229
00018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.1922900018
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.1731254910
Short name T1642
Test name
Test status
Simulation time 7641063896 ps
CPU time 60.75 seconds
Started Jul 26 05:08:15 PM PDT 24
Finished Jul 26 05:09:16 PM PDT 24
Peak memory 217592 kb
Host smart-513e6432-5b53-4704-abc8-8c953c6f7a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17312
54910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.1731254910
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.2324586973
Short name T2538
Test name
Test status
Simulation time 4820479037 ps
CPU time 130.89 seconds
Started Jul 26 05:08:24 PM PDT 24
Finished Jul 26 05:10:35 PM PDT 24
Peak memory 215412 kb
Host smart-b8c7c177-4e56-4ac6-a1d9-5764a406fea9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2324586973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.2324586973
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.2363147274
Short name T2784
Test name
Test status
Simulation time 241087326 ps
CPU time 1.09 seconds
Started Jul 26 05:08:15 PM PDT 24
Finished Jul 26 05:08:16 PM PDT 24
Peak memory 207108 kb
Host smart-b70090a0-88b2-4956-ba8d-6a64de2446ed
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2363147274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.2363147274
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.1934479495
Short name T2384
Test name
Test status
Simulation time 242094712 ps
CPU time 1.02 seconds
Started Jul 26 05:08:24 PM PDT 24
Finished Jul 26 05:08:25 PM PDT 24
Peak memory 206988 kb
Host smart-9628be6c-2db6-4217-ad64-92c5fc756d97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19344
79495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.1934479495
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.2202888040
Short name T1886
Test name
Test status
Simulation time 5265140526 ps
CPU time 54.2 seconds
Started Jul 26 05:08:17 PM PDT 24
Finished Jul 26 05:09:12 PM PDT 24
Peak memory 215536 kb
Host smart-bb56ccd4-3ff1-4b61-bac0-b35f5ea52c8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22028
88040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.2202888040
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.1623163030
Short name T1562
Test name
Test status
Simulation time 6536161088 ps
CPU time 195.06 seconds
Started Jul 26 05:08:13 PM PDT 24
Finished Jul 26 05:11:28 PM PDT 24
Peak memory 215480 kb
Host smart-ac5b90d8-92d8-40aa-bf0e-91f5eaa1e4bd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1623163030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.1623163030
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.1511503807
Short name T2058
Test name
Test status
Simulation time 163012121 ps
CPU time 0.88 seconds
Started Jul 26 05:08:25 PM PDT 24
Finished Jul 26 05:08:26 PM PDT 24
Peak memory 207000 kb
Host smart-9b05abb4-357d-49cc-999d-c24ef2fcb9b1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1511503807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.1511503807
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.1284836307
Short name T1273
Test name
Test status
Simulation time 144422197 ps
CPU time 0.82 seconds
Started Jul 26 05:08:14 PM PDT 24
Finished Jul 26 05:08:15 PM PDT 24
Peak memory 207152 kb
Host smart-b2b9d05a-fc21-480f-a7de-f6712e9c26a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12848
36307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.1284836307
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.285693518
Short name T956
Test name
Test status
Simulation time 285438472 ps
CPU time 1.04 seconds
Started Jul 26 05:08:14 PM PDT 24
Finished Jul 26 05:08:16 PM PDT 24
Peak memory 207100 kb
Host smart-d73f583b-642a-484b-bcb2-463a261cb02a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28569
3518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.285693518
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.4174284647
Short name T1806
Test name
Test status
Simulation time 158863756 ps
CPU time 0.89 seconds
Started Jul 26 05:08:14 PM PDT 24
Finished Jul 26 05:08:15 PM PDT 24
Peak memory 207132 kb
Host smart-714007fe-0844-419f-ad3d-4dcc00ba1fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41742
84647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.4174284647
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.507876684
Short name T1193
Test name
Test status
Simulation time 144039203 ps
CPU time 0.83 seconds
Started Jul 26 05:08:14 PM PDT 24
Finished Jul 26 05:08:15 PM PDT 24
Peak memory 207100 kb
Host smart-7db5070b-356e-4c46-acd8-be7bba1e0efb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50787
6684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.507876684
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.2811002822
Short name T2291
Test name
Test status
Simulation time 186975051 ps
CPU time 0.94 seconds
Started Jul 26 05:08:18 PM PDT 24
Finished Jul 26 05:08:19 PM PDT 24
Peak memory 207120 kb
Host smart-70a0cc3b-7887-46c5-b5e9-0ef2c56eec42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28110
02822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.2811002822
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.3306493431
Short name T1235
Test name
Test status
Simulation time 151145437 ps
CPU time 0.85 seconds
Started Jul 26 05:08:13 PM PDT 24
Finished Jul 26 05:08:13 PM PDT 24
Peak memory 207128 kb
Host smart-4d93741f-492a-41f8-a754-eea54e4e5bd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33064
93431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.3306493431
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.1518295878
Short name T1646
Test name
Test status
Simulation time 213628041 ps
CPU time 1.05 seconds
Started Jul 26 05:08:14 PM PDT 24
Finished Jul 26 05:08:15 PM PDT 24
Peak memory 207120 kb
Host smart-fb300131-73a2-47a2-b016-2755cf966614
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1518295878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.1518295878
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.3930205886
Short name T2416
Test name
Test status
Simulation time 164196435 ps
CPU time 0.85 seconds
Started Jul 26 05:08:15 PM PDT 24
Finished Jul 26 05:08:16 PM PDT 24
Peak memory 207064 kb
Host smart-2eeb6e8b-0d3d-4367-abfa-99d1a3d4f93a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39302
05886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.3930205886
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.2109491647
Short name T2313
Test name
Test status
Simulation time 31559394 ps
CPU time 0.69 seconds
Started Jul 26 05:08:17 PM PDT 24
Finished Jul 26 05:08:18 PM PDT 24
Peak memory 207088 kb
Host smart-4fa4dd9a-f817-41e2-bbdc-0ab3a2c399d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21094
91647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.2109491647
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.3174502665
Short name T1003
Test name
Test status
Simulation time 15382549599 ps
CPU time 34.71 seconds
Started Jul 26 05:08:17 PM PDT 24
Finished Jul 26 05:08:52 PM PDT 24
Peak memory 215428 kb
Host smart-e6e580b0-8f79-4452-ab6f-67f8639d0abf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31745
02665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.3174502665
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.328274353
Short name T2648
Test name
Test status
Simulation time 175467605 ps
CPU time 0.88 seconds
Started Jul 26 05:08:15 PM PDT 24
Finished Jul 26 05:08:16 PM PDT 24
Peak memory 207100 kb
Host smart-26526184-a967-4d08-b7a5-a907e7077506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32827
4353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.328274353
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.2808389468
Short name T1353
Test name
Test status
Simulation time 193119757 ps
CPU time 0.88 seconds
Started Jul 26 05:08:17 PM PDT 24
Finished Jul 26 05:08:18 PM PDT 24
Peak memory 206940 kb
Host smart-165e383f-3c85-4578-966b-72c23af81bf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28083
89468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.2808389468
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.1073276201
Short name T2091
Test name
Test status
Simulation time 8194642382 ps
CPU time 39.35 seconds
Started Jul 26 05:08:28 PM PDT 24
Finished Jul 26 05:09:07 PM PDT 24
Peak memory 218280 kb
Host smart-e58c505b-2e01-4c0e-b4d3-b6e9bb474754
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073276201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.1073276201
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.2439429168
Short name T1408
Test name
Test status
Simulation time 13323709359 ps
CPU time 273.41 seconds
Started Jul 26 05:08:29 PM PDT 24
Finished Jul 26 05:13:02 PM PDT 24
Peak memory 215556 kb
Host smart-12feb28f-ef47-44ec-af41-18e162bdb257
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2439429168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.2439429168
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.2795131380
Short name T1239
Test name
Test status
Simulation time 18110713332 ps
CPU time 447.22 seconds
Started Jul 26 05:08:26 PM PDT 24
Finished Jul 26 05:15:53 PM PDT 24
Peak memory 215608 kb
Host smart-42925726-4073-4441-9757-08ad8a1b7080
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795131380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.2795131380
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.2523323432
Short name T447
Test name
Test status
Simulation time 259645471 ps
CPU time 1.04 seconds
Started Jul 26 05:08:17 PM PDT 24
Finished Jul 26 05:08:18 PM PDT 24
Peak memory 206964 kb
Host smart-b92625f3-94e3-42c4-8f61-c819371ce661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25233
23432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.2523323432
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.1777773993
Short name T2308
Test name
Test status
Simulation time 175643497 ps
CPU time 0.88 seconds
Started Jul 26 05:08:26 PM PDT 24
Finished Jul 26 05:08:27 PM PDT 24
Peak memory 207064 kb
Host smart-16236c0c-9723-4ed6-8bd2-d25fa39600c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17777
73993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.1777773993
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.2240738940
Short name T1923
Test name
Test status
Simulation time 217522558 ps
CPU time 0.92 seconds
Started Jul 26 05:08:28 PM PDT 24
Finished Jul 26 05:08:29 PM PDT 24
Peak memory 207068 kb
Host smart-00d770a7-7960-4f01-b9af-215882145d0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22407
38940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.2240738940
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.4289402310
Short name T2409
Test name
Test status
Simulation time 152000638 ps
CPU time 0.87 seconds
Started Jul 26 05:08:26 PM PDT 24
Finished Jul 26 05:08:27 PM PDT 24
Peak memory 206980 kb
Host smart-e39fbb31-c1a6-48a0-8374-fb2885942433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42894
02310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.4289402310
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.656489328
Short name T853
Test name
Test status
Simulation time 212452448 ps
CPU time 0.92 seconds
Started Jul 26 05:08:26 PM PDT 24
Finished Jul 26 05:08:27 PM PDT 24
Peak memory 207088 kb
Host smart-96a8ce3b-c2c7-4af7-b84c-2fcbcff43cac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65648
9328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.656489328
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.2585972963
Short name T1189
Test name
Test status
Simulation time 297000875 ps
CPU time 1.19 seconds
Started Jul 26 05:08:27 PM PDT 24
Finished Jul 26 05:08:28 PM PDT 24
Peak memory 207036 kb
Host smart-5e6896bc-8b98-4c5f-b6ed-0e889ccac569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25859
72963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.2585972963
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.1074715931
Short name T1600
Test name
Test status
Simulation time 3748166801 ps
CPU time 39.54 seconds
Started Jul 26 05:08:26 PM PDT 24
Finished Jul 26 05:09:06 PM PDT 24
Peak memory 216816 kb
Host smart-a5fc06f5-9c54-47b3-8f74-374466e3c620
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1074715931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.1074715931
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.472885803
Short name T274
Test name
Test status
Simulation time 167902938 ps
CPU time 0.88 seconds
Started Jul 26 05:08:30 PM PDT 24
Finished Jul 26 05:08:31 PM PDT 24
Peak memory 207136 kb
Host smart-2eb4b1a6-4ed9-4807-95f6-7bc9c1d1817a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47288
5803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.472885803
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.1608741796
Short name T2810
Test name
Test status
Simulation time 154958684 ps
CPU time 0.84 seconds
Started Jul 26 05:08:25 PM PDT 24
Finished Jul 26 05:08:26 PM PDT 24
Peak memory 207104 kb
Host smart-91186684-efef-41ca-a4d0-7bf49ffb031d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16087
41796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.1608741796
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.3544554602
Short name T538
Test name
Test status
Simulation time 1036105388 ps
CPU time 2.58 seconds
Started Jul 26 05:08:26 PM PDT 24
Finished Jul 26 05:08:29 PM PDT 24
Peak memory 207232 kb
Host smart-96ae844a-326e-42bb-9c58-b47b8a78059a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35445
54602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.3544554602
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.469579730
Short name T978
Test name
Test status
Simulation time 5847590993 ps
CPU time 168.84 seconds
Started Jul 26 05:08:28 PM PDT 24
Finished Jul 26 05:11:17 PM PDT 24
Peak memory 215532 kb
Host smart-e2f66e0c-79e0-4839-a3b1-f438ced2f63e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46957
9730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.469579730
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_timeout_missing_host_handshake.2339970074
Short name T2462
Test name
Test status
Simulation time 3755864261 ps
CPU time 25.62 seconds
Started Jul 26 05:08:17 PM PDT 24
Finished Jul 26 05:08:42 PM PDT 24
Peak memory 207364 kb
Host smart-a339e147-cd7d-401c-b8a2-448c1ef2bbd3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339970074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_timeout_missing_host
_handshake.2339970074
Directory /workspace/8.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.705324516
Short name T2
Test name
Test status
Simulation time 33755104 ps
CPU time 0.67 seconds
Started Jul 26 05:08:40 PM PDT 24
Finished Jul 26 05:08:41 PM PDT 24
Peak memory 207136 kb
Host smart-1c2ebc06-c652-444d-bf29-8329c9c3bc76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=705324516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.705324516
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.3853959632
Short name T2183
Test name
Test status
Simulation time 3644775721 ps
CPU time 5.96 seconds
Started Jul 26 05:08:28 PM PDT 24
Finished Jul 26 05:08:34 PM PDT 24
Peak memory 207296 kb
Host smart-12789c7c-e1b6-491a-93ec-7aa916f5e832
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853959632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_ao
n_wake_disconnect.3853959632
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.1949315467
Short name T12
Test name
Test status
Simulation time 13348884840 ps
CPU time 14.37 seconds
Started Jul 26 05:08:24 PM PDT 24
Finished Jul 26 05:08:39 PM PDT 24
Peak memory 207400 kb
Host smart-7040854f-c462-464b-a1dd-ec037ad0d7b6
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949315467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.1949315467
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.3727959707
Short name T1834
Test name
Test status
Simulation time 23371998722 ps
CPU time 29.47 seconds
Started Jul 26 05:08:28 PM PDT 24
Finished Jul 26 05:08:57 PM PDT 24
Peak memory 207384 kb
Host smart-1ca49f86-3404-4d35-8441-fcbafccba966
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727959707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_ao
n_wake_resume.3727959707
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.1849425122
Short name T153
Test name
Test status
Simulation time 157768410 ps
CPU time 0.93 seconds
Started Jul 26 05:08:26 PM PDT 24
Finished Jul 26 05:08:27 PM PDT 24
Peak memory 207096 kb
Host smart-da65f3c8-bd78-4aee-a8ef-2218d80e5065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18494
25122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.1849425122
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.3592578374
Short name T553
Test name
Test status
Simulation time 148031140 ps
CPU time 0.83 seconds
Started Jul 26 05:08:25 PM PDT 24
Finished Jul 26 05:08:26 PM PDT 24
Peak memory 207048 kb
Host smart-5762c4c0-7f38-4c38-a8e2-7447eedbed1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35925
78374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.3592578374
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.2749445849
Short name T2167
Test name
Test status
Simulation time 307468417 ps
CPU time 1.23 seconds
Started Jul 26 05:08:27 PM PDT 24
Finished Jul 26 05:08:28 PM PDT 24
Peak memory 207120 kb
Host smart-cd996c19-83c5-4eae-b737-194fa4b934ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27494
45849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.2749445849
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.2983238371
Short name T663
Test name
Test status
Simulation time 979077675 ps
CPU time 2.65 seconds
Started Jul 26 05:08:27 PM PDT 24
Finished Jul 26 05:08:30 PM PDT 24
Peak memory 207288 kb
Host smart-a501f287-dee5-45e5-ae5f-94ae2435e284
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2983238371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.2983238371
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.2412969732
Short name T2161
Test name
Test status
Simulation time 7549746465 ps
CPU time 18.71 seconds
Started Jul 26 05:08:26 PM PDT 24
Finished Jul 26 05:08:44 PM PDT 24
Peak memory 207456 kb
Host smart-900d5a5e-5bde-437d-b252-ee49a60d3b10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24129
69732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.2412969732
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_device_timeout.2560464299
Short name T1521
Test name
Test status
Simulation time 4957568037 ps
CPU time 33.03 seconds
Started Jul 26 05:08:28 PM PDT 24
Finished Jul 26 05:09:01 PM PDT 24
Peak memory 207304 kb
Host smart-ab62b5ee-030a-4994-a15b-10c3b6cec986
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560464299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_timeout.2560464299
Directory /workspace/9.usbdev_device_timeout/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.1169826746
Short name T997
Test name
Test status
Simulation time 354287984 ps
CPU time 1.35 seconds
Started Jul 26 05:08:26 PM PDT 24
Finished Jul 26 05:08:28 PM PDT 24
Peak memory 207064 kb
Host smart-f4b3e413-9b2d-494e-8f5d-12e7bd916f18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11698
26746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.1169826746
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.1785011167
Short name T1485
Test name
Test status
Simulation time 144819635 ps
CPU time 0.82 seconds
Started Jul 26 05:08:25 PM PDT 24
Finished Jul 26 05:08:26 PM PDT 24
Peak memory 207096 kb
Host smart-eacc8221-e8b0-463e-8d89-71015c6fd411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17850
11167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.1785011167
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.590955852
Short name T446
Test name
Test status
Simulation time 78148229 ps
CPU time 0.75 seconds
Started Jul 26 05:08:26 PM PDT 24
Finished Jul 26 05:08:27 PM PDT 24
Peak memory 207096 kb
Host smart-d62d4316-43d5-4222-930e-d73976e3c2f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59095
5852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.590955852
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.4154587646
Short name T477
Test name
Test status
Simulation time 841218708 ps
CPU time 2.28 seconds
Started Jul 26 05:08:26 PM PDT 24
Finished Jul 26 05:08:29 PM PDT 24
Peak memory 207320 kb
Host smart-ef1050c6-7f8a-4d8c-bfbc-dd92ce05509f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41545
87646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.4154587646
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.4212440409
Short name T177
Test name
Test status
Simulation time 183991415 ps
CPU time 2.15 seconds
Started Jul 26 05:08:28 PM PDT 24
Finished Jul 26 05:08:31 PM PDT 24
Peak memory 207220 kb
Host smart-c47eefe3-c777-4258-b9ce-d914224ea132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42124
40409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.4212440409
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.705052935
Short name T778
Test name
Test status
Simulation time 266179125 ps
CPU time 1.27 seconds
Started Jul 26 05:08:29 PM PDT 24
Finished Jul 26 05:08:30 PM PDT 24
Peak memory 215464 kb
Host smart-60592a96-a270-4cb2-a04d-453f99dc3129
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=705052935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.705052935
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.4099205314
Short name T2753
Test name
Test status
Simulation time 140685940 ps
CPU time 0.83 seconds
Started Jul 26 05:08:28 PM PDT 24
Finished Jul 26 05:08:29 PM PDT 24
Peak memory 207048 kb
Host smart-eb837919-0dc2-472b-87dd-10474857e995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40992
05314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.4099205314
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.51856767
Short name T1144
Test name
Test status
Simulation time 247822891 ps
CPU time 1 seconds
Started Jul 26 05:08:29 PM PDT 24
Finished Jul 26 05:08:30 PM PDT 24
Peak memory 207124 kb
Host smart-5d2fbbfb-c3ca-4d8f-81fa-ae26011226bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51856
767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.51856767
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_invalid_sync.555973999
Short name T1704
Test name
Test status
Simulation time 5490085670 ps
CPU time 172.89 seconds
Started Jul 26 05:08:26 PM PDT 24
Finished Jul 26 05:11:19 PM PDT 24
Peak memory 215616 kb
Host smart-4fa6c1f6-c169-4bc4-b4f1-ad738a1103f7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=555973999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.555973999
Directory /workspace/9.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/9.usbdev_iso_retraction.374851495
Short name T1001
Test name
Test status
Simulation time 14264381345 ps
CPU time 105.6 seconds
Started Jul 26 05:08:26 PM PDT 24
Finished Jul 26 05:10:12 PM PDT 24
Peak memory 207328 kb
Host smart-c717185c-b5a0-47ab-be82-8bce39c722bb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=374851495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.374851495
Directory /workspace/9.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.571502406
Short name T1874
Test name
Test status
Simulation time 249855984 ps
CPU time 1.12 seconds
Started Jul 26 05:08:28 PM PDT 24
Finished Jul 26 05:08:29 PM PDT 24
Peak memory 207092 kb
Host smart-c7584f9a-4714-46d9-8062-5dab17251f8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57150
2406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.571502406
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.1079921076
Short name T2519
Test name
Test status
Simulation time 23377961862 ps
CPU time 30.1 seconds
Started Jul 26 05:08:27 PM PDT 24
Finished Jul 26 05:08:57 PM PDT 24
Peak memory 207272 kb
Host smart-6dc3b02e-dac3-4284-8ee2-bb5a08caf54e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10799
21076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.1079921076
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.2576282475
Short name T1749
Test name
Test status
Simulation time 3317071517 ps
CPU time 5.45 seconds
Started Jul 26 05:08:30 PM PDT 24
Finished Jul 26 05:08:35 PM PDT 24
Peak memory 207456 kb
Host smart-cb10e45e-85c0-41bb-b8a6-d96c0681f25f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25762
82475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.2576282475
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.990986855
Short name T2860
Test name
Test status
Simulation time 5082746993 ps
CPU time 38.97 seconds
Started Jul 26 05:08:28 PM PDT 24
Finished Jul 26 05:09:07 PM PDT 24
Peak memory 217552 kb
Host smart-8abb9f52-3456-4ced-91b7-564bc0b10439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99098
6855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.990986855
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.3795525147
Short name T2665
Test name
Test status
Simulation time 7719822298 ps
CPU time 59.63 seconds
Started Jul 26 05:08:29 PM PDT 24
Finished Jul 26 05:09:28 PM PDT 24
Peak memory 207384 kb
Host smart-1b7e1ec8-bd8c-42e7-aa1d-5588cf4e314c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3795525147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.3795525147
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.4220145294
Short name T616
Test name
Test status
Simulation time 246020323 ps
CPU time 1.02 seconds
Started Jul 26 05:08:28 PM PDT 24
Finished Jul 26 05:08:29 PM PDT 24
Peak memory 207044 kb
Host smart-5c3a8e13-53c0-4ea5-ad81-670ef6c38af4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4220145294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.4220145294
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.1457647056
Short name T1872
Test name
Test status
Simulation time 249661432 ps
CPU time 1.03 seconds
Started Jul 26 05:08:27 PM PDT 24
Finished Jul 26 05:08:29 PM PDT 24
Peak memory 207096 kb
Host smart-201c7feb-1a50-4ed4-a73b-02f78010a9b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14576
47056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.1457647056
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.3509287645
Short name T409
Test name
Test status
Simulation time 5803481892 ps
CPU time 61.27 seconds
Started Jul 26 05:08:27 PM PDT 24
Finished Jul 26 05:09:28 PM PDT 24
Peak memory 216972 kb
Host smart-8ebe703b-09f6-4bf7-a384-f186a57ca008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35092
87645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.3509287645
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.426151982
Short name T1977
Test name
Test status
Simulation time 5017970948 ps
CPU time 144.57 seconds
Started Jul 26 05:08:27 PM PDT 24
Finished Jul 26 05:10:52 PM PDT 24
Peak memory 215448 kb
Host smart-2080945b-cbbf-4d88-8e51-303776b60a34
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=426151982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.426151982
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.380935849
Short name T1566
Test name
Test status
Simulation time 152669072 ps
CPU time 0.86 seconds
Started Jul 26 05:08:27 PM PDT 24
Finished Jul 26 05:08:28 PM PDT 24
Peak memory 207064 kb
Host smart-e4322465-dbac-44f7-bbf8-d01be0b6099c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=380935849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.380935849
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.3866424989
Short name T1214
Test name
Test status
Simulation time 165093794 ps
CPU time 0.86 seconds
Started Jul 26 05:08:29 PM PDT 24
Finished Jul 26 05:08:30 PM PDT 24
Peak memory 207104 kb
Host smart-63410780-735f-47e9-9e08-60590078992a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38664
24989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.3866424989
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.2673274770
Short name T143
Test name
Test status
Simulation time 184970228 ps
CPU time 0.89 seconds
Started Jul 26 05:08:27 PM PDT 24
Finished Jul 26 05:08:28 PM PDT 24
Peak memory 207104 kb
Host smart-13bf1972-f5ff-472e-b638-b742b99bc875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26732
74770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.2673274770
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.89949637
Short name T622
Test name
Test status
Simulation time 206641114 ps
CPU time 1.03 seconds
Started Jul 26 05:08:30 PM PDT 24
Finished Jul 26 05:08:31 PM PDT 24
Peak memory 207136 kb
Host smart-d1ac7be6-b298-4560-8a6d-586c4ea90238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89949
637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.89949637
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.3929809249
Short name T1725
Test name
Test status
Simulation time 184947497 ps
CPU time 0.95 seconds
Started Jul 26 05:08:26 PM PDT 24
Finished Jul 26 05:08:27 PM PDT 24
Peak memory 207060 kb
Host smart-3fab99c3-e442-46b3-ad05-8a8aeae732c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39298
09249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.3929809249
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.2513760398
Short name T420
Test name
Test status
Simulation time 164375192 ps
CPU time 0.87 seconds
Started Jul 26 05:08:42 PM PDT 24
Finished Jul 26 05:08:43 PM PDT 24
Peak memory 207036 kb
Host smart-e906e785-e884-411e-b8b9-00b6d16a111a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25137
60398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.2513760398
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.3645927794
Short name T526
Test name
Test status
Simulation time 147387167 ps
CPU time 0.87 seconds
Started Jul 26 05:08:43 PM PDT 24
Finished Jul 26 05:08:44 PM PDT 24
Peak memory 207024 kb
Host smart-2786c1d1-4e6e-4548-8463-c608708ca6d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36459
27794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.3645927794
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.834828238
Short name T2682
Test name
Test status
Simulation time 263992223 ps
CPU time 1.17 seconds
Started Jul 26 05:08:40 PM PDT 24
Finished Jul 26 05:08:41 PM PDT 24
Peak memory 207156 kb
Host smart-079480a4-469c-4469-96fb-4dc6daa6c7e2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=834828238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.834828238
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.3651066031
Short name T2272
Test name
Test status
Simulation time 146644470 ps
CPU time 0.86 seconds
Started Jul 26 05:08:41 PM PDT 24
Finished Jul 26 05:08:42 PM PDT 24
Peak memory 207084 kb
Host smart-97d29bd8-9972-4b76-8b88-aadd3fb8c99d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36510
66031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.3651066031
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.3070983835
Short name T1099
Test name
Test status
Simulation time 58891301 ps
CPU time 0.66 seconds
Started Jul 26 05:08:42 PM PDT 24
Finished Jul 26 05:08:43 PM PDT 24
Peak memory 206988 kb
Host smart-57b7d351-9e16-44ad-9119-5f2c6682833a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30709
83835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.3070983835
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.159059307
Short name T235
Test name
Test status
Simulation time 16106005908 ps
CPU time 42.14 seconds
Started Jul 26 05:08:41 PM PDT 24
Finished Jul 26 05:09:23 PM PDT 24
Peak memory 215620 kb
Host smart-39a2ef16-1d41-45d9-a837-872723804780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15905
9307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.159059307
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.3231638908
Short name T1986
Test name
Test status
Simulation time 157403477 ps
CPU time 0.82 seconds
Started Jul 26 05:08:39 PM PDT 24
Finished Jul 26 05:08:40 PM PDT 24
Peak memory 207064 kb
Host smart-f4046683-52fb-47ef-840b-4b6a84ee485c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32316
38908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.3231638908
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.156186981
Short name T1789
Test name
Test status
Simulation time 235237063 ps
CPU time 1 seconds
Started Jul 26 05:08:40 PM PDT 24
Finished Jul 26 05:08:41 PM PDT 24
Peak memory 207092 kb
Host smart-142d376d-ab48-46d9-81a5-19f37ddaed9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15618
6981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.156186981
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.3105316941
Short name T2570
Test name
Test status
Simulation time 5551442082 ps
CPU time 39.03 seconds
Started Jul 26 05:08:40 PM PDT 24
Finished Jul 26 05:09:19 PM PDT 24
Peak memory 223680 kb
Host smart-0d9d95d3-4ce3-4674-b135-5624e5695cf8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105316941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.3105316941
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.3594998308
Short name T164
Test name
Test status
Simulation time 10923883494 ps
CPU time 214.72 seconds
Started Jul 26 05:08:40 PM PDT 24
Finished Jul 26 05:12:15 PM PDT 24
Peak memory 215536 kb
Host smart-e3c417cd-63ca-42bf-8489-388e7bc8225c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3594998308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.3594998308
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.3251296375
Short name T2568
Test name
Test status
Simulation time 12404205287 ps
CPU time 74.87 seconds
Started Jul 26 05:08:40 PM PDT 24
Finished Jul 26 05:09:55 PM PDT 24
Peak memory 223632 kb
Host smart-7987e047-2614-4152-ab77-3ab582cdeded
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251296375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.3251296375
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.3127978873
Short name T2359
Test name
Test status
Simulation time 235138795 ps
CPU time 0.95 seconds
Started Jul 26 05:08:42 PM PDT 24
Finished Jul 26 05:08:43 PM PDT 24
Peak memory 206976 kb
Host smart-f25104f1-fccd-4011-ae3d-130d9e3db434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31279
78873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.3127978873
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.390705529
Short name T1308
Test name
Test status
Simulation time 183499768 ps
CPU time 0.9 seconds
Started Jul 26 05:08:40 PM PDT 24
Finished Jul 26 05:08:41 PM PDT 24
Peak memory 207076 kb
Host smart-39c721b2-995d-4a42-9702-5796fa1423cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39070
5529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.390705529
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.138128401
Short name T205
Test name
Test status
Simulation time 178091033 ps
CPU time 0.93 seconds
Started Jul 26 05:08:39 PM PDT 24
Finished Jul 26 05:08:40 PM PDT 24
Peak memory 207168 kb
Host smart-8027f334-be4f-4dfb-af7e-36f93a98a337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13812
8401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.138128401
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.3501616418
Short name T1567
Test name
Test status
Simulation time 176620056 ps
CPU time 0.98 seconds
Started Jul 26 05:08:38 PM PDT 24
Finished Jul 26 05:08:39 PM PDT 24
Peak memory 207100 kb
Host smart-5b5cb4ac-d0fb-4cbe-85f9-5165ee01a139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35016
16418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.3501616418
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.746290517
Short name T2528
Test name
Test status
Simulation time 156679610 ps
CPU time 0.81 seconds
Started Jul 26 05:08:41 PM PDT 24
Finished Jul 26 05:08:42 PM PDT 24
Peak memory 207136 kb
Host smart-c9c75046-c260-4334-813a-97d12ac3ca34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74629
0517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.746290517
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.643271006
Short name T346
Test name
Test status
Simulation time 242796995 ps
CPU time 1.06 seconds
Started Jul 26 05:08:43 PM PDT 24
Finished Jul 26 05:08:45 PM PDT 24
Peak memory 207076 kb
Host smart-910fa8ff-ded9-4e66-8471-02c71cafa83d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64327
1006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.643271006
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.2624064446
Short name T1240
Test name
Test status
Simulation time 6027462845 ps
CPU time 184.98 seconds
Started Jul 26 05:08:43 PM PDT 24
Finished Jul 26 05:11:48 PM PDT 24
Peak memory 215484 kb
Host smart-6f5542dd-f104-4a69-ba75-255d313ac40f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2624064446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.2624064446
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.2892999549
Short name T2111
Test name
Test status
Simulation time 149800184 ps
CPU time 0.83 seconds
Started Jul 26 05:08:41 PM PDT 24
Finished Jul 26 05:08:42 PM PDT 24
Peak memory 207044 kb
Host smart-26950777-657d-4f1c-8857-9aebcebf5ca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28929
99549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.2892999549
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.1429013843
Short name T1236
Test name
Test status
Simulation time 146330377 ps
CPU time 0.83 seconds
Started Jul 26 05:08:38 PM PDT 24
Finished Jul 26 05:08:39 PM PDT 24
Peak memory 206932 kb
Host smart-0f57348e-286d-4afb-ba98-9576aa76075e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14290
13843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.1429013843
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.142195825
Short name T2268
Test name
Test status
Simulation time 703888571 ps
CPU time 1.92 seconds
Started Jul 26 05:08:42 PM PDT 24
Finished Jul 26 05:08:44 PM PDT 24
Peak memory 206944 kb
Host smart-7c262fef-9046-4d91-89f4-2d929760d6b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14219
5825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.142195825
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.2667940869
Short name T642
Test name
Test status
Simulation time 4257069431 ps
CPU time 43.61 seconds
Started Jul 26 05:08:40 PM PDT 24
Finished Jul 26 05:09:24 PM PDT 24
Peak memory 215500 kb
Host smart-979d3e8a-acb1-4af1-a4ef-d2ec48281a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26679
40869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.2667940869
Directory /workspace/9.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_timeout_missing_host_handshake.1957455257
Short name T1473
Test name
Test status
Simulation time 593684765 ps
CPU time 11.42 seconds
Started Jul 26 05:08:29 PM PDT 24
Finished Jul 26 05:08:41 PM PDT 24
Peak memory 207368 kb
Host smart-32c9d8f2-7219-4d1f-86dc-8a9bed9ce993
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957455257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_timeout_missing_host
_handshake.1957455257
Directory /workspace/9.usbdev_timeout_missing_host_handshake/latest
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