Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	80460	1		T1	2		T2	4		T3	2
all_values[1]	80460	1		T1	2		T2	4		T3	2
all_values[2]	80460	1		T1	2		T2	4		T3	2
all_values[3]	80460	1		T1	2		T2	4		T3	2
all_values[4]	80460	1		T1	2		T2	4		T3	2
all_values[5]	80460	1		T1	2		T2	4		T3	2
all_values[6]	80460	1		T1	2		T2	4		T3	2
all_values[7]	80460	1		T1	2		T2	4		T3	2
all_values[8]	80460	1		T1	2		T2	4		T3	2
all_values[9]	80460	1		T1	2		T2	4		T3	2
all_values[10]	80460	1		T1	2		T2	4		T3	2
all_values[11]	80460	1		T1	2		T2	4		T3	2
all_values[12]	80460	1		T1	2		T2	4		T3	2
all_values[13]	80460	1		T1	2		T2	4		T3	2
all_values[14]	80460	1		T1	2		T2	4		T3	2
all_values[15]	80460	1		T1	2		T2	4		T3	2
all_values[16]	80460	1		T1	2		T2	4		T3	2
all_values[17]	80460	1		T1	2		T2	4		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2567707	1		T1	64		T2	126		T3	64
auto[1]	7013	1		T2	2		T16	3		T21	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2138013	1		T1	58		T2	111		T3	58
auto[1]	436707	1		T1	6		T2	17		T3	6

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	55225	1		T1	2		T2	4		T3	2
all_values[0]	auto[0]	auto[1]	24398	1		T20	13		T29	11		T90	2
all_values[0]	auto[1]	auto[0]	731	1		T21	3		T28	3		T40	3
all_values[0]	auto[1]	auto[1]	106	1		T41	1		T316	1		T317	1
all_values[1]	auto[0]	auto[0]	77175	1		T1	2		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	1623	1		T28	1		T6	2		T30	2
all_values[1]	auto[1]	auto[0]	648	1		T2	1		T16	2		T35	1
all_values[1]	auto[1]	auto[1]	1014	1		T2	1		T16	1		T35	1
all_values[2]	auto[0]	auto[0]	2943	1		T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	77230	1		T1	1		T2	3		T3	1
all_values[2]	auto[1]	auto[0]	149	1		T36	1		T37	1		T38	1
all_values[2]	auto[1]	auto[1]	138	1		T36	1		T37	1		T38	1
all_values[3]	auto[0]	auto[0]	78324	1		T1	2		T2	4		T3	2
all_values[3]	auto[0]	auto[1]	532	1		T4	1		T5	1		T6	1
all_values[3]	auto[1]	auto[0]	1538	1		T58	1428		T213	3		T214	2
all_values[3]	auto[1]	auto[1]	66	1		T58	1		T213	1		T214	3
all_values[4]	auto[0]	auto[0]	2941	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	77370	1		T1	1		T2	3		T3	1
all_values[4]	auto[1]	auto[0]	89	1		T59	1		T214	2		T215	1
all_values[4]	auto[1]	auto[1]	60	1		T59	1		T214	2		T215	1
all_values[5]	auto[0]	auto[0]	79936	1		T1	2		T2	3		T3	2
all_values[5]	auto[0]	auto[1]	346	1		T2	1		T35	1		T7	1
all_values[5]	auto[1]	auto[0]	100	1		T213	4		T214	2		T308	2
all_values[5]	auto[1]	auto[1]	78	1		T213	1		T214	3		T215	1
all_values[6]	auto[0]	auto[0]	80007	1		T1	2		T2	4		T3	2
all_values[6]	auto[0]	auto[1]	270	1		T35	2		T7	1		T8	1
all_values[6]	auto[1]	auto[0]	94	1		T213	1		T214	2		T215	2
all_values[6]	auto[1]	auto[1]	89	1		T213	3		T214	3		T215	3
all_values[7]	auto[0]	auto[0]	27460	1		T1	2		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	52849	1		T2	2		T16	3		T17	2
all_values[7]	auto[1]	auto[0]	96	1		T43	1		T44	1		T45	1
all_values[7]	auto[1]	auto[1]	55	1		T43	1		T44	1		T45	1
all_values[8]	auto[0]	auto[0]	80223	1		T1	2		T2	4		T3	2
all_values[8]	auto[0]	auto[1]	54	1		T213	1		T215	4		T308	3
all_values[8]	auto[1]	auto[0]	120	1		T48	10		T213	3		T214	3
all_values[8]	auto[1]	auto[1]	63	1		T48	1		T213	1		T214	3
all_values[9]	auto[0]	auto[0]	80204	1		T1	2		T2	4		T3	2
all_values[9]	auto[0]	auto[1]	59	1		T213	2		T214	2		T308	3
all_values[9]	auto[1]	auto[0]	131	1		T55	3		T56	3		T57	3
all_values[9]	auto[1]	auto[1]	66	1		T55	2		T56	2		T57	2
all_values[10]	auto[0]	auto[0]	79993	1		T1	2		T2	4		T3	2
all_values[10]	auto[0]	auto[1]	306	1		T52	1		T53	1		T54	2
all_values[10]	auto[1]	auto[0]	94	1		T213	2		T214	2		T215	1
all_values[10]	auto[1]	auto[1]	67	1		T214	1		T215	4		T309	1
all_values[11]	auto[0]	auto[0]	80067	1		T1	2		T2	4		T3	2
all_values[11]	auto[0]	auto[1]	127	1		T63	1		T64	1		T68	1
all_values[11]	auto[1]	auto[0]	164	1		T65	1		T66	1		T67	1
all_values[11]	auto[1]	auto[1]	102	1		T65	1		T66	1		T67	1
all_values[12]	auto[0]	auto[0]	80217	1		T1	2		T2	4		T3	2
all_values[12]	auto[0]	auto[1]	81	1		T68	1		T69	1		T73	1
all_values[12]	auto[1]	auto[0]	93	1		T70	2		T71	2		T72	2
all_values[12]	auto[1]	auto[1]	69	1		T70	1		T71	1		T72	1
all_values[13]	auto[0]	auto[0]	80123	1		T1	2		T2	4		T3	2
all_values[13]	auto[0]	auto[1]	71	1		T68	1		T69	1		T73	1
all_values[13]	auto[1]	auto[0]	139	1		T63	1		T64	1		T74	1
all_values[13]	auto[1]	auto[1]	127	1		T63	1		T64	1		T74	1
all_values[14]	auto[0]	auto[0]	13006	1		T1	2		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	67307	1		T2	2		T4	1		T19	1
all_values[14]	auto[1]	auto[0]	92	1		T213	4		T214	1		T215	2
all_values[14]	auto[1]	auto[1]	55	1		T214	3		T215	3		T308	2
all_values[15]	auto[0]	auto[0]	2961	1		T1	1		T2	1		T3	1
all_values[15]	auto[0]	auto[1]	77296	1		T1	1		T2	3		T3	1
all_values[15]	auto[1]	auto[0]	111	1		T213	1		T214	4		T215	3
all_values[15]	auto[1]	auto[1]	92	1		T213	3		T214	2		T215	3
all_values[16]	auto[0]	auto[0]	79855	1		T1	1		T2	4		T3	1
all_values[16]	auto[0]	auto[1]	417	1		T1	1		T3	1		T22	1
all_values[16]	auto[1]	auto[0]	115	1		T60	4		T61	4		T62	4
all_values[16]	auto[1]	auto[1]	73	1		T60	4		T61	4		T62	4
all_values[17]	auto[0]	auto[0]	26288	1		T2	2		T18	2		T6	2
all_values[17]	auto[0]	auto[1]	53983	1		T1	2		T2	2		T3	2
all_values[17]	auto[1]	auto[0]	121	1		T50	1		T51	1		T213	1
all_values[17]	auto[1]	auto[1]	68	1		T50	1		T51	1		T215	3