Group : usbdev_env_pkg::usbdev_env_cov::crc16_cg
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Group : usbdev_env_pkg::usbdev_env_cov::crc16_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv



Summary for Group usbdev_env_pkg::usbdev_env_cov::crc16_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group usbdev_env_pkg::usbdev_env_cov::crc16_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_crc16 2 0 2 100.00 100 1 1 0
cp_dir 2 0 2 100.00 100 1 1 2


Crosses for Group usbdev_env_pkg::usbdev_env_cov::crc16_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_crc16_X_dir 4 0 4 100.00 100 1 1 0


Summary for Variable cp_crc16

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_crc16

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
six_ones 27 1 T252 1 T339 1 T340 2
all_ones 9 1 T341 1 T342 1 T343 1



Summary for Variable cp_dir

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_dir

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 132896 1 T1 1 T2 1 T3 2
auto[1] 60978 1 T2 1 T16 1 T4 175



Summary for Cross cr_crc16_X_dir

Samples crossed: cp_crc16 cp_dir
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cr_crc16_X_dir

Bins
cp_crc16cp_dirCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
six_ones auto[0] 19 1 T252 1 T339 1 T340 1
six_ones auto[1] 8 1 T340 1 T344 1 T345 1
all_ones auto[0] 6 1 T341 1 T342 1 T346 1
all_ones auto[1] 3 1 T343 1 T347 1 T115 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%