Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	132896	1		T1	1		T2	1		T3	2
auto[1]	60978	1		T2	1		T16	1		T4	175

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
sixty_four	28734	1		T4	172		T20	13		T5	56
sixty_three	1235	1		T6	6		T30	6		T83	11
sixty_two	1108	1		T83	7		T333	2		T163	2
sixty_one	1180	1		T6	2		T30	6		T94	2
five	1555	1		T6	4		T30	2		T94	2
four	1576	1		T30	4		T94	2		T83	7
three	1592	1		T6	6		T30	2		T83	7
one	1736	1		T6	1		T30	6		T94	2
zero	11436	1		T4	3		T5	4		T6	5

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
sixty_four	auto[0]	23914	1		T20	13		T29	11		T30	6
sixty_four	auto[1]	4820	1		T4	172		T5	56		T30	6
sixty_three	auto[0]	782	1		T6	3		T30	3		T83	6
sixty_three	auto[1]	453	1		T6	3		T30	3		T83	5
sixty_two	auto[0]	705	1		T83	5		T333	1		T163	1
sixty_two	auto[1]	403	1		T83	2		T333	1		T163	1
sixty_one	auto[0]	740	1		T6	1		T30	3		T94	1
sixty_one	auto[1]	440	1		T6	1		T30	3		T94	1
five	auto[0]	826	1		T6	2		T30	1		T94	1
five	auto[1]	729	1		T6	2		T30	1		T94	1
four	auto[0]	833	1		T30	2		T94	1		T83	5
four	auto[1]	743	1		T30	2		T94	1		T83	2
three	auto[0]	829	1		T6	4		T30	1		T83	5
three	auto[1]	763	1		T6	2		T30	1		T83	2
one	auto[0]	847	1		T6	1		T30	3		T94	1
one	auto[1]	889	1		T30	3		T94	1		T349	1
zero	auto[0]	1001	1		T6	3		T30	3		T94	3
zero	auto[1]	10435	1		T4	3		T5	4		T6	2