Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg
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Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
42.67 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv



Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 22 6 16 72.73
Crosses 128 80 48 37.50


Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_dir 2 0 2 100.00 100 1 1 2
cp_endp 16 4 12 75.00 100 1 1 16
cp_pid 4 2 2 50.00 100 1 1 0


Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_pid_X_dir_X_endp 128 80 48 37.50 100 1 1 0


Summary for Variable cp_dir

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_dir

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 86826 1 T1 1 T2 1 T3 2
auto[1] 56421 1 T2 1 T16 1 T28 1



Summary for Variable cp_endp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 16 4 12 75.00


Automatically Generated Bins for cp_endp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[12] - auto[15]] -- -- 4


Covered bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 10427 1 T6 24 T35 2 T83 32
auto[1] 11309 1 T27 1 T30 42 T40 1
auto[2] 9886 1 T6 24 T64 1 T294 1
auto[3] 12544 1 T1 1 T297 1 T91 1
auto[4] 10321 1 T16 2 T6 24 T98 18
auto[5] 13803 1 T3 2 T22 1 T29 11
auto[6] 13238 1 T6 24 T30 42 T154 2
auto[7] 9595 1 T103 1 T83 32 T106 1
auto[8] 12642 1 T6 24 T30 42 T83 32
auto[9] 10428 1 T20 13 T21 1 T30 42
auto[10] 14861 1 T2 2 T28 3 T30 42
auto[11] 14193 1 T6 24 T97 1 T94 164



Summary for Variable cp_pid

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 2 2 50.00


User Defined Bins for cp_pid

Uncovered bins
NAME   COUNT   AT LEAST   NUMBER   
nak 0 1 1
ack 0 1 1


Covered bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
data1 67313 1 T3 1 T20 6 T28 2
data0 75920 1 T1 1 T2 2 T3 1



Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 80 48 37.50 80


Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Element holes
cp_pid   cp_dir   cp_endp   COUNT   AT LEAST   NUMBER   
[nak , ack] * * -- -- 64
[data1 , data0] * [auto[12] - auto[15]] -- -- 16


Covered bins
cp_pid   cp_dir   cp_endp   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
data1 auto[0] auto[0] 2564 1 T6 5 T83 8 T150 21
data1 auto[0] auto[1] 2893 1 T30 10 T83 8 T150 17
data1 auto[0] auto[2] 2295 1 T6 6 T150 18 T151 5
data1 auto[0] auto[3] 3157 1 T150 16 T151 4 T152 5
data1 auto[0] auto[4] 2447 1 T6 4 T98 9 T116 1
data1 auto[0] auto[5] 3599 1 T3 1 T29 5 T83 8
data1 auto[0] auto[6] 3556 1 T6 3 T30 10 T161 24
data1 auto[0] auto[7] 1979 1 T83 5 T150 21 T151 7
data1 auto[0] auto[8] 3342 1 T6 6 T30 10 T83 8
data1 auto[0] auto[9] 2462 1 T20 6 T30 7 T155 30
data1 auto[0] auto[10] 4373 1 T28 1 T30 10 T83 8
data1 auto[0] auto[11] 4235 1 T6 2 T94 41 T83 8
data1 auto[1] auto[0] 2313 1 T6 7 T83 8 T150 18
data1 auto[1] auto[1] 2439 1 T30 10 T83 8 T150 22
data1 auto[1] auto[2] 2276 1 T6 6 T150 16 T151 8
data1 auto[1] auto[3] 2678 1 T150 15 T151 10 T152 5
data1 auto[1] auto[4] 2388 1 T6 7 T150 19 T151 7
data1 auto[1] auto[5] 3036 1 T83 8 T42 1 T150 16
data1 auto[1] auto[6] 2646 1 T6 9 T30 10 T161 48
data1 auto[1] auto[7] 2420 1 T83 10 T52 7 T150 16
data1 auto[1] auto[8] 2626 1 T6 6 T30 10 T83 8
data1 auto[1] auto[9] 2432 1 T30 14 T155 59 T163 49
data1 auto[1] auto[10] 2675 1 T28 1 T30 10 T83 8
data1 auto[1] auto[11] 2482 1 T6 9 T94 41 T83 8
data0 auto[0] auto[0] 3448 1 T6 7 T35 1 T83 8
data0 auto[0] auto[1] 3972 1 T27 1 T30 11 T40 1
data0 auto[0] auto[2] 3323 1 T6 6 T64 1 T294 1
data0 auto[0] auto[3] 4497 1 T1 1 T297 1 T91 1
data0 auto[0] auto[4] 3419 1 T16 1 T6 8 T98 9
data0 auto[0] auto[5] 4579 1 T3 1 T22 1 T29 6
data0 auto[0] auto[6] 4755 1 T6 9 T30 11 T154 1
data0 auto[0] auto[7] 3082 1 T103 1 T83 11 T106 1
data0 auto[0] auto[8] 4417 1 T6 6 T30 11 T83 8
data0 auto[0] auto[9] 3563 1 T20 7 T21 1 T30 14
data0 auto[0] auto[10] 5503 1 T2 1 T28 1 T30 11
data0 auto[0] auto[11] 5352 1 T6 10 T97 1 T94 41
data0 auto[1] auto[0] 2099 1 T6 5 T35 1 T83 8
data0 auto[1] auto[1] 2002 1 T30 11 T83 8 T298 1
data0 auto[1] auto[2] 1992 1 T6 6 T12 1 T150 17
data0 auto[1] auto[3] 2211 1 T150 15 T151 4 T152 5
data0 auto[1] auto[4] 2066 1 T16 1 T6 5 T153 1
data0 auto[1] auto[5] 2589 1 T83 8 T150 17 T152 5
data0 auto[1] auto[6] 2281 1 T6 3 T30 11 T154 1
data0 auto[1] auto[7] 2113 1 T83 6 T8 1 T52 12
data0 auto[1] auto[8] 2256 1 T6 6 T30 11 T83 8
data0 auto[1] auto[9] 1969 1 T30 7 T155 30 T163 17
data0 auto[1] auto[10] 2310 1 T2 1 T30 11 T83 8
data0 auto[1] auto[11] 2122 1 T6 3 T94 41 T83 8