Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	1	7	87.50
Crosses	16	11	5	31.25

Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_in_enable	2	0	2	100.00	100	1	1	2
cp_in_iso	2	0	2	100.00	100	1	1	2
cp_in_stall	2	0	2	100.00	100	1	1	2
cp_pid	2	1	1	50.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_x_epconfig	16	11	5	31.25	100	1	1	0

Summary for Variable cp_in_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_enable

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	6229	1		T6	7		T165	4		T166	2
auto[1]	67542	1		T2	1		T16	1		T17	1

---

Summary for Variable cp_in_iso

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_iso

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	69214	1		T2	1		T16	1		T17	1
auto[1]	4557	1		T4	175		T5	60		T91	1

---

Summary for Variable cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_stall

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	68776	1		T2	1		T16	1		T4	175
auto[1]	4995	1		T17	1		T165	5		T166	8

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for cp_pid

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
ignore_pre[PidTypePre]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeInToken]	73771	1		T2	1		T16	1		T17	1

---

Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	11	5	31.25	11

Automatically Generated Cross Bins for cr_pid_x_epconfig

Element holes

cp_pid	cp_in_enable	cp_in_iso	cp_in_stall	COUNT	AT LEAST	NUMBER
[ignore_pre[PidTypePre]]	*	*	*	--	--	8
[pkt_types[PidTypeInToken]]	[auto[0]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_pid	cp_in_enable	cp_in_iso	cp_in_stall	COUNT	AT LEAST	NUMBER
[pkt_types[PidTypeInToken]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_pid

cp_in_enable

cp_in_iso

cp_in_stall

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[0]

3980

1

T6

7

T165

1

T166

1

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[1]

2249

1

T165

3

T166

1

T287

1

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[0]

60239

1

T2

1

T16

1

T28

1

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[1]

2746

1

T17

1

T165

2

T166

7

pkt_types[PidTypeInToken]

auto[1]

auto[1]

auto[0]

4557

1

T4

175

T5

60

T91

1