Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

Group : usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
24.15	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	1	14	93.33
Crosses	192	156	36	18.75

Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_out_enable	2	0	2	100.00	100	1	1	2
cp_out_iso	2	0	2	100.00	100	1	1	2
cp_out_stall	2	0	2	100.00	100	1	1	2
cp_pid	3	1	2	66.67	100	1	1	0
cp_rxenable_out	2	0	2	100.00	100	1	1	2
cp_rxenable_setup	2	0	2	100.00	100	1	1	2
cp_set_nak_out	2	0	2	100.00	100	1	1	2

Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_x_epconfig	192	156	36	18.75	100	1	1	0

Summary for Variable cp_out_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_out_enable

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	19643	1		T6	6		T165	16		T63	1
auto[1]	96793	1		T1	1		T2	1		T3	2

---

Summary for Variable cp_out_iso

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_out_iso

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	116386	1		T1	1		T2	1		T3	2
auto[1]	50	1		T112	1		T113	1		T114	1

---

Summary for Variable cp_out_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_out_stall

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	103193	1		T2	1		T3	2		T16	1
auto[1]	13243	1		T1	1		T27	1		T28	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	1	2	66.67

User Defined Bins for cp_pid

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
ignore_pre[PidTypePre]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	22216	1		T21	1		T28	1		T6	34
pkt_types[PidTypeOutToken]	94167	1		T1	1		T2	1		T3	2

---

Summary for Variable cp_rxenable_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rxenable_out

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	20162	1		T3	1		T21	1		T22	1
auto[1]	96274	1		T1	1		T2	1		T3	1

---

Summary for Variable cp_rxenable_setup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rxenable_setup

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	79524	1		T1	1		T2	1		T3	2
auto[1]	36912	1		T28	2		T6	73		T90	1

---

Summary for Variable cp_set_nak_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_set_nak_out

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	116286	1		T2	1		T16	1		T20	13
auto[1]	150	1		T1	1		T3	2		T116	2

---

Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_out_enable cp_rxenable_setup cp_rxenable_out cp_set_nak_out cp_out_iso cp_out_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	192	156	36	18.75	156

Automatically Generated Cross Bins for cr_pid_x_epconfig

Element holes

cp_pid	cp_out_enable	cp_rxenable_setup	cp_rxenable_out	cp_set_nak_out	cp_out_iso	cp_out_stall	COUNT	AT LEAST	NUMBER
[ignore_pre[PidTypePre]]	*	*	*	*	*	*	--	--	64
[pkt_types[PidTypeSetupToken]]	*	*	*	[auto[0]]	[auto[1]]	*	--	--	16
[pkt_types[PidTypeSetupToken]]	*	*	*	[auto[1]]	*	*	--	--	32
[pkt_types[PidTypeOutToken]]	[auto[0]]	*	*	[auto[0]]	[auto[1]]	*	--	--	8
[pkt_types[PidTypeOutToken]]	[auto[0]]	*	*	[auto[1]]	*	*	--	--	16
[pkt_types[PidTypeOutToken]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	*	--	--	2
[pkt_types[PidTypeOutToken]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	*	--	--	2
[pkt_types[PidTypeOutToken]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	*	--	--	2
[pkt_types[PidTypeOutToken]]	[auto[1]]	[auto[1]]	*	[auto[0]]	[auto[1]]	*	--	--	4
[pkt_types[PidTypeOutToken]]	[auto[1]]	[auto[1]]	*	[auto[1]]	*	*	--	--	8

Uncovered bins

cp_pid	cp_out_enable	cp_rxenable_setup	cp_rxenable_out	cp_set_nak_out	cp_out_iso	cp_out_stall	COUNT	AT LEAST	NUMBER
[pkt_types[PidTypeOutToken]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[pkt_types[PidTypeOutToken]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_pid

cp_out_enable

cp_rxenable_setup

cp_rxenable_out

cp_set_nak_out

cp_out_iso

cp_out_stall

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1022

1

T6

2

T165

2

T158

3

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

905

1

T287

1

T288

2

T289

2

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

763

1

T165

1

T287

3

T290

5

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

778

1

T165

1

T166

1

T291

2

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

871

1

T6

2

T68

3

T158

2

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

678

1

T166

1

T290

2

T289

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

722

1

T165

1

T287

2

T288

2

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

687

1

T287

2

T86

15

T87

37

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

935

1

T21

1

T40

1

T111

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

629

1

T87

31

T292

23

T189

8

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1169

1

T6

1

T68

1

T233

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

553

1

T86

30

T87

26

T189

18

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1666

1

T90

1

T106

1

T108

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

39

1

T86

4

T88

2

T189

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

10660

1

T6

29

T30

9

T83

8

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

139

1

T28

1

T42

1

T99

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

2201

1

T165

1

T63

1

T68

9

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

1791

1

T166

2

T287

5

T288

4

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1638

1

T165

6

T166

1

T287

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1623

1

T165

1

T166

5

T291

8

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1768

1

T6

2

T68

8

T158

3

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

1384

1

T165

1

T166

3

T287

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1363

1

T165

2

T287

2

T288

5

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

1421

1

T287

4

T86

24

T87

68

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1872

1

T22

1

T293

1

T237

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

1198

1

T87

54

T292

48

T189

27

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

50

1

T3

1

T116

1

T144

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

60969

1

T2

1

T16

1

T20

13

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1245

1

T27

1

T103

1

T109

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

50

1

T112

1

T113

1

T114

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

50

1

T3

1

T116

1

T144

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

50

1

T1

1

T294

1

T295

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

3058

1

T86

77

T87

55

T88

169

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

67

1

T86

5

T88

2

T296

5

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

12313

1

T28

1

T6

40

T30

12

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

56

1

T169

1

T86

1

T184

1