Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

Group : usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
33.85	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	1	10	90.91
Crosses	54	42	12	22.22

Variables for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_avout	3	0	3	100.00	100	1	1	0
cp_avsetup	3	0	3	100.00	100	1	1	0
cp_pid	2	0	2	100.00	100	1	1	0
cp_rx	3	1	2	66.67	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_fifo_X_pid	54	42	12	22.22	100	1	1	0

Summary for Variable cp_avout

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_avout

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	41840	1		T6	88		T30	105		T94	82
solo	89267	1		T1	1		T2	1		T3	2
empty	1690	1		T21	1		T28	1		T90	1

---

Summary for Variable cp_avsetup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_avsetup

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	41835	1		T6	88		T30	105		T94	82
solo	46326	1		T28	1		T90	1		T106	1
empty	44690	1		T1	1		T2	1		T3	2

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
out	106619	1		T1	1		T2	1		T3	2
setup	26240	1		T21	1		T28	1		T6	34

---

Summary for Variable cp_rx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	1	2	66.67

User Defined Bins for cp_rx

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
full	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
solo	14	1		T46	2		T60	1		T61	1
empty	108909	1		T1	1		T2	1		T3	2

---

Summary for Cross cr_fifo_X_pid

Samples crossed: cp_avsetup cp_avout cp_rx cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	54	42	12	22.22	42

Automatically Generated Cross Bins for cr_fifo_X_pid

Element holes

cp_avsetup	cp_avout	cp_rx	cp_pid	COUNT	AT LEAST	NUMBER
[full]	[full]	[full , solo]	*	--	--	4
[full]	[solo , empty]	*	*	--	--	12
[solo]	[full]	[full , solo]	*	--	--	4
[solo]	[solo]	[full]	*	--	--	2
[solo]	[empty]	[full]	*	--	--	2
[empty]	[full]	*	*	--	--	6
[empty]	[solo]	[full , solo]	*	--	--	4
[empty]	[empty]	[full , solo]	*	--	--	4

Uncovered bins

cp_avsetup	cp_avout	cp_rx	cp_pid	COUNT	AT LEAST	NUMBER
[solo]	[full]	[empty]	[setup]	0	1	1
[solo]	[empty]	[solo , empty]	[out]	--	--	2
[empty]	[solo]	[empty]	[setup]	0	1	1

Covered bins

cp_avsetup

cp_avout

cp_rx

cp_pid

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

full

full

empty

out

32257

1

T6

54

T30

96

T94

82

full

full

empty

setup

9578

1

T6

34

T30

9

T83

8

solo

full

empty

out

5

1

T46

1

T47

1

T49

1

solo

solo

solo

out

5

1

T46

1

T47

1

T49

1

solo

solo

solo

setup

5

1

T46

1

T47

1

T49

1

solo

solo

empty

out

16876

1

T165

8

T166

8

T169

1

solo

solo

empty

setup

8338

1

T165

5

T166

2

T169

1

solo

empty

solo

setup

1

1

T48

1

-

-

-

-

solo

empty

empty

setup

318

1

T28

1

T90

1

T106

1

empty

solo

empty

out

41334

1

T1

1

T2

1

T3

2

empty

empty

empty

out

142

1

T58

139

T60

1

T61

1

empty

empty

empty

setup

50

1

T21

1

T40

1

T111

1