Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	80460	1		T1	2		T2	4		T3	2
all_pins[1]	80460	1		T1	2		T2	4		T3	2
all_pins[2]	80460	1		T1	2		T2	4		T3	2
all_pins[3]	80460	1		T1	2		T2	4		T3	2
all_pins[4]	80460	1		T1	2		T2	4		T3	2
all_pins[5]	80460	1		T1	2		T2	4		T3	2
all_pins[6]	80460	1		T1	2		T2	4		T3	2
all_pins[7]	80460	1		T1	2		T2	4		T3	2
all_pins[8]	80460	1		T1	2		T2	4		T3	2
all_pins[9]	80460	1		T1	2		T2	4		T3	2
all_pins[10]	80460	1		T1	2		T2	4		T3	2
all_pins[11]	80460	1		T1	2		T2	4		T3	2
all_pins[12]	80460	1		T1	2		T2	4		T3	2
all_pins[13]	80460	1		T1	2		T2	4		T3	2
all_pins[14]	80460	1		T1	2		T2	4		T3	2
all_pins[15]	80460	1		T1	2		T2	4		T3	2
all_pins[16]	80460	1		T1	2		T2	4		T3	2
all_pins[17]	80460	1		T1	2		T2	4		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2572332	1		T1	64		T2	127		T3	64
values[0x1]	2388	1		T2	1		T16	1		T35	1
transitions[0x0=>0x1]	2076	1		T2	1		T16	1		T35	1
transitions[0x1=>0x0]	2076	1		T2	1		T16	1		T35	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	80354	1		T1	2		T2	4		T3	2
all_pins[0]	values[0x1]	106	1		T41	1		T316	1		T317	1
all_pins[0]	transitions[0x0=>0x1]	94	1		T41	1		T316	1		T317	1
all_pins[0]	transitions[0x1=>0x0]	1002	1		T2	1		T16	1		T35	1
all_pins[1]	values[0x0]	79446	1		T1	2		T2	3		T3	2
all_pins[1]	values[0x1]	1014	1		T2	1		T16	1		T35	1
all_pins[1]	transitions[0x0=>0x1]	994	1		T2	1		T16	1		T35	1
all_pins[1]	transitions[0x1=>0x0]	118	1		T36	1		T37	1		T38	1
all_pins[2]	values[0x0]	80322	1		T1	2		T2	4		T3	2
all_pins[2]	values[0x1]	138	1		T36	1		T37	1		T38	1
all_pins[2]	transitions[0x0=>0x1]	115	1		T36	1		T37	1		T38	1
all_pins[2]	transitions[0x1=>0x0]	43	1		T58	1		T214	1		T308	2
all_pins[3]	values[0x0]	80394	1		T1	2		T2	4		T3	2
all_pins[3]	values[0x1]	66	1		T58	1		T213	1		T214	3
all_pins[3]	transitions[0x0=>0x1]	51	1		T58	1		T213	1		T214	1
all_pins[3]	transitions[0x1=>0x0]	45	1		T59	1		T215	1		T285	1
all_pins[4]	values[0x0]	80400	1		T1	2		T2	4		T3	2
all_pins[4]	values[0x1]	60	1		T59	1		T214	2		T215	1
all_pins[4]	transitions[0x0=>0x1]	38	1		T59	1		T310	1		T285	1
all_pins[4]	transitions[0x1=>0x0]	56	1		T213	1		T214	1		T308	4
all_pins[5]	values[0x0]	80382	1		T1	2		T2	4		T3	2
all_pins[5]	values[0x1]	78	1		T213	1		T214	3		T215	1
all_pins[5]	transitions[0x0=>0x1]	39	1		T214	1		T308	1		T309	1
all_pins[5]	transitions[0x1=>0x0]	50	1		T213	2		T214	1		T215	2
all_pins[6]	values[0x0]	80371	1		T1	2		T2	4		T3	2
all_pins[6]	values[0x1]	89	1		T213	3		T214	3		T215	3
all_pins[6]	transitions[0x0=>0x1]	77	1		T213	3		T214	3		T215	3
all_pins[6]	transitions[0x1=>0x0]	43	1		T43	1		T44	1		T45	1
all_pins[7]	values[0x0]	80405	1		T1	2		T2	4		T3	2
all_pins[7]	values[0x1]	55	1		T43	1		T44	1		T45	1
all_pins[7]	transitions[0x0=>0x1]	39	1		T43	1		T44	1		T45	1
all_pins[7]	transitions[0x1=>0x0]	47	1		T48	1		T213	1		T214	3
all_pins[8]	values[0x0]	80397	1		T1	2		T2	4		T3	2
all_pins[8]	values[0x1]	63	1		T48	1		T213	1		T214	3
all_pins[8]	transitions[0x0=>0x1]	52	1		T48	1		T213	1		T214	2
all_pins[8]	transitions[0x1=>0x0]	55	1		T55	2		T56	2		T57	2
all_pins[9]	values[0x0]	80394	1		T1	2		T2	4		T3	2
all_pins[9]	values[0x1]	66	1		T55	2		T56	2		T57	2
all_pins[9]	transitions[0x0=>0x1]	46	1		T55	2		T56	2		T57	2
all_pins[9]	transitions[0x1=>0x0]	47	1		T214	1		T215	4		T309	1
all_pins[10]	values[0x0]	80393	1		T1	2		T2	4		T3	2
all_pins[10]	values[0x1]	67	1		T214	1		T215	4		T309	1
all_pins[10]	transitions[0x0=>0x1]	56	1		T214	1		T215	4		T309	1
all_pins[10]	transitions[0x1=>0x0]	91	1		T65	1		T66	1		T67	1
all_pins[11]	values[0x0]	80358	1		T1	2		T2	4		T3	2
all_pins[11]	values[0x1]	102	1		T65	1		T66	1		T67	1
all_pins[11]	transitions[0x0=>0x1]	80	1		T65	1		T66	1		T67	1
all_pins[11]	transitions[0x1=>0x0]	47	1		T70	1		T71	1		T72	1
all_pins[12]	values[0x0]	80391	1		T1	2		T2	4		T3	2
all_pins[12]	values[0x1]	69	1		T70	1		T71	1		T72	1
all_pins[12]	transitions[0x0=>0x1]	55	1		T70	1		T71	1		T72	1
all_pins[12]	transitions[0x1=>0x0]	113	1		T63	1		T64	1		T74	1
all_pins[13]	values[0x0]	80333	1		T1	2		T2	4		T3	2
all_pins[13]	values[0x1]	127	1		T63	1		T64	1		T74	1
all_pins[13]	transitions[0x0=>0x1]	113	1		T63	1		T64	1		T74	1
all_pins[13]	transitions[0x1=>0x0]	41	1		T214	2		T215	3		T308	2
all_pins[14]	values[0x0]	80405	1		T1	2		T2	4		T3	2
all_pins[14]	values[0x1]	55	1		T214	3		T215	3		T308	2
all_pins[14]	transitions[0x0=>0x1]	30	1		T214	3		T310	1		T313	1
all_pins[14]	transitions[0x1=>0x0]	67	1		T213	3		T214	2		T308	5
all_pins[15]	values[0x0]	80368	1		T1	2		T2	4		T3	2
all_pins[15]	values[0x1]	92	1		T213	3		T214	2		T215	3
all_pins[15]	transitions[0x0=>0x1]	72	1		T213	2		T214	2		T308	5
all_pins[15]	transitions[0x1=>0x0]	53	1		T60	4		T61	4		T62	4
all_pins[16]	values[0x0]	80387	1		T1	2		T2	4		T3	2
all_pins[16]	values[0x1]	73	1		T60	4		T61	4		T62	4
all_pins[16]	transitions[0x0=>0x1]	57	1		T60	4		T61	4		T62	4
all_pins[16]	transitions[0x1=>0x0]	52	1		T50	1		T51	1		T215	1
all_pins[17]	values[0x0]	80392	1		T1	2		T2	4		T3	2
all_pins[17]	values[0x1]	68	1		T50	1		T51	1		T215	3
all_pins[17]	transitions[0x0=>0x1]	68	1		T50	1		T51	1		T215	3