Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[12]	5030	1		T83	19		T84	20		T68	3
invalid_ep[13]	5093	1		T83	31		T84	12		T68	4
invalid_ep[14]	5184	1		T83	35		T84	14		T68	2
invalid_ep[15]	5165	1		T83	26		T84	19		T68	5
endpoints[0]	14245	1		T6	29		T35	2		T83	33
endpoints[1]	15790	1		T4	175		T27	1		T6	3
endpoints[2]	13291	1		T6	28		T165	1		T64	1
endpoints[3]	16416	1		T1	1		T6	3		T297	1
endpoints[4]	14531	1		T16	2		T6	26		T98	18
endpoints[5]	18177	1		T3	2		T22	1		T6	1
endpoints[6]	17195	1		T6	27		T30	43		T154	2
endpoints[7]	13155	1		T103	1		T6	2		T83	33
endpoints[8]	16477	1		T5	60		T6	26		T30	43
endpoints[9]	14456	1		T20	13		T21	1		T6	2
endpoints[10]	18516	1		T2	2		T28	3		T6	2
endpoints[11]	17958	1		T17	1		T6	26		T97	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	26240	1		T21	1		T28	1		T6	34
pkt_types[PidTypeOutToken]	106619	1		T1	1		T2	1		T3	2
pkt_types[PidTypeInToken]	77767	1		T2	1		T16	1		T17	1

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[12]	982	1		T86	12		T87	19		T88	33
pkt_types[PidTypeSetupToken]	invalid_ep[13]	1035	1		T86	15		T87	28		T88	29
pkt_types[PidTypeSetupToken]	invalid_ep[14]	1010	1		T86	11		T87	37		T88	34
pkt_types[PidTypeSetupToken]	invalid_ep[15]	997	1		T86	9		T87	28		T88	33
pkt_types[PidTypeSetupToken]	endpoints[0]	1668	1		T6	6		T165	1		T111	1
pkt_types[PidTypeSetupToken]	endpoints[1]	1898	1		T6	2		T40	1		T156	28
pkt_types[PidTypeSetupToken]	endpoints[2]	1673	1		T6	3		T165	1		T101	1
pkt_types[PidTypeSetupToken]	endpoints[3]	2046	1		T6	1		T165	1		T166	1
pkt_types[PidTypeSetupToken]	endpoints[4]	1875	1		T6	4		T68	9		T159	7
pkt_types[PidTypeSetupToken]	endpoints[5]	1941	1		T90	1		T42	1		T160	1
pkt_types[PidTypeSetupToken]	endpoints[6]	1845	1		T6	8		T161	34		T152	6
pkt_types[PidTypeSetupToken]	endpoints[7]	1731	1		T83	8		T106	1		T165	1
pkt_types[PidTypeSetupToken]	endpoints[8]	1868	1		T6	1		T162	1		T99	1
pkt_types[PidTypeSetupToken]	endpoints[9]	2034	1		T21	1		T30	9		T155	46
pkt_types[PidTypeSetupToken]	endpoints[10]	1795	1		T28	1		T6	1		T165	1
pkt_types[PidTypeSetupToken]	endpoints[11]	1842	1		T6	8		T108	1		T100	1
pkt_types[PidTypeOutToken]	invalid_ep[12]	3080	1		T83	19		T84	20		T68	3
pkt_types[PidTypeOutToken]	invalid_ep[13]	3049	1		T83	31		T84	12		T68	4
pkt_types[PidTypeOutToken]	invalid_ep[14]	3168	1		T83	35		T84	14		T68	2
pkt_types[PidTypeOutToken]	invalid_ep[15]	3155	1		T83	26		T84	19		T68	5
pkt_types[PidTypeOutToken]	endpoints[0]	6967	1		T6	10		T35	1		T83	16
pkt_types[PidTypeOutToken]	endpoints[1]	7600	1		T27	1		T6	1		T30	21
pkt_types[PidTypeOutToken]	endpoints[2]	6201	1		T6	11		T64	1		T294	1
pkt_types[PidTypeOutToken]	endpoints[3]	7867	1		T1	1		T297	1		T91	1
pkt_types[PidTypeOutToken]	endpoints[4]	6677	1		T16	1		T6	9		T98	18
pkt_types[PidTypeOutToken]	endpoints[5]	8854	1		T3	2		T22	1		T6	1
pkt_types[PidTypeOutToken]	endpoints[6]	8798	1		T6	6		T30	21		T154	1
pkt_types[PidTypeOutToken]	endpoints[7]	5754	1		T103	1		T83	8		T8	1
pkt_types[PidTypeOutToken]	endpoints[8]	8385	1		T6	12		T30	21		T83	16
pkt_types[PidTypeOutToken]	endpoints[9]	6556	1		T20	13		T30	12		T109	1
pkt_types[PidTypeOutToken]	endpoints[10]	10439	1		T2	1		T28	1		T30	21
pkt_types[PidTypeOutToken]	endpoints[11]	10069	1		T6	4		T97	1		T94	82
pkt_types[PidTypeInToken]	invalid_ep[12]	968	1		T86	17		T87	21		T88	41
pkt_types[PidTypeInToken]	invalid_ep[13]	1009	1		T86	15		T87	33		T88	37
pkt_types[PidTypeInToken]	invalid_ep[14]	1006	1		T86	14		T87	34		T88	37
pkt_types[PidTypeInToken]	invalid_ep[15]	1013	1		T86	8		T87	24		T88	26
pkt_types[PidTypeInToken]	endpoints[0]	5607	1		T6	13		T35	1		T83	17
pkt_types[PidTypeInToken]	endpoints[1]	6285	1		T4	175		T30	22		T83	17
pkt_types[PidTypeInToken]	endpoints[2]	5413	1		T6	14		T12	1		T150	33
pkt_types[PidTypeInToken]	endpoints[3]	6497	1		T6	2		T91	1		T165	1
pkt_types[PidTypeInToken]	endpoints[4]	5975	1		T16	1		T6	13		T153	1
pkt_types[PidTypeInToken]	endpoints[5]	7381	1		T83	17		T42	1		T166	1
pkt_types[PidTypeInToken]	endpoints[6]	6547	1		T6	13		T30	22		T154	1
pkt_types[PidTypeInToken]	endpoints[7]	5664	1		T6	2		T83	17		T8	1
pkt_types[PidTypeInToken]	endpoints[8]	6218	1		T5	60		T6	13		T30	22
pkt_types[PidTypeInToken]	endpoints[9]	5863	1		T6	2		T30	22		T85	53
pkt_types[PidTypeInToken]	endpoints[10]	6275	1		T2	1		T28	1		T6	1
pkt_types[PidTypeInToken]	endpoints[11]	6046	1		T17	1		T6	14		T94	83