Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	275	1		T213	4		T214	7		T215	7
all_values[1]	275	1		T213	4		T214	7		T215	7
all_values[2]	275	1		T213	4		T214	7		T215	7
all_values[3]	275	1		T213	4		T214	7		T215	7
all_values[4]	275	1		T213	4		T214	7		T215	7
all_values[5]	275	1		T213	4		T214	7		T215	7
all_values[6]	275	1		T213	4		T214	7		T215	7
all_values[7]	275	1		T213	4		T214	7		T215	7
all_values[8]	275	1		T213	4		T214	7		T215	7
all_values[9]	275	1		T213	4		T214	7		T215	7
all_values[10]	275	1		T213	4		T214	7		T215	7
all_values[11]	275	1		T213	4		T214	7		T215	7
all_values[12]	275	1		T213	4		T214	7		T215	7
all_values[13]	275	1		T213	4		T214	7		T215	7
all_values[14]	275	1		T213	4		T214	7		T215	7
all_values[15]	275	1		T213	4		T214	7		T215	7
all_values[16]	275	1		T213	4		T214	7		T215	7
all_values[17]	275	1		T213	4		T214	7		T215	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	6450	1		T213	86		T214	169		T215	164
auto[1]	2350	1		T213	42		T214	55		T215	60

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5985	1		T213	90		T214	145		T215	148
auto[1]	2815	1		T213	38		T214	79		T215	76

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5065	1		T213	81		T214	123		T215	116
auto[1]	3735	1		T213	47		T214	101		T215	108

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	76	1		T213	1		T215	2		T308	2
all_values[0]	auto[0]	auto[1]	auto[0]	81	1		T213	1		T214	4		T215	1
all_values[0]	auto[1]	auto[0]	auto[1]	71	1		T213	1		T214	2		T215	4
all_values[0]	auto[1]	auto[1]	auto[1]	47	1		T213	1		T214	1		T309	1
all_values[1]	auto[0]	auto[0]	auto[0]	88	1		T213	1		T214	4		T215	3
all_values[1]	auto[0]	auto[1]	auto[0]	66	1		T213	1		T215	2		T309	2
all_values[1]	auto[1]	auto[0]	auto[1]	63	1		T213	1		T214	3		T215	1
all_values[1]	auto[1]	auto[1]	auto[1]	58	1		T213	1		T215	1		T308	1
all_values[2]	auto[0]	auto[0]	auto[0]	35	1		T308	3		T310	1		T285	1
all_values[2]	auto[0]	auto[0]	auto[1]	41	1		T214	2		T309	3		T310	1
all_values[2]	auto[0]	auto[1]	auto[0]	44	1		T215	4		T308	1		T285	2
all_values[2]	auto[0]	auto[1]	auto[1]	37	1		T213	2		T214	1		T215	1
all_values[2]	auto[1]	auto[0]	auto[1]	53	1		T214	2		T215	1		T308	1
all_values[2]	auto[1]	auto[1]	auto[1]	65	1		T213	2		T214	2		T215	1
all_values[3]	auto[0]	auto[0]	auto[0]	53	1		T213	1		T214	1		T215	4
all_values[3]	auto[0]	auto[0]	auto[1]	23	1		T215	1		T308	1		T285	1
all_values[3]	auto[0]	auto[1]	auto[0]	55	1		T213	2		T214	1		T308	1
all_values[3]	auto[0]	auto[1]	auto[1]	25	1		T214	2		T308	2		T309	1
all_values[3]	auto[1]	auto[0]	auto[1]	70	1		T213	1		T214	1		T215	1
all_values[3]	auto[1]	auto[1]	auto[1]	49	1		T214	2		T215	1		T309	3
all_values[4]	auto[0]	auto[0]	auto[0]	62	1		T213	4		T214	1		T215	1
all_values[4]	auto[0]	auto[0]	auto[1]	29	1		T215	1		T309	1		T285	1
all_values[4]	auto[0]	auto[1]	auto[0]	40	1		T214	2		T215	1		T308	1
all_values[4]	auto[0]	auto[1]	auto[1]	24	1		T214	1		T215	1		T308	1
all_values[4]	auto[1]	auto[0]	auto[1]	65	1		T214	2		T215	1		T308	2
all_values[4]	auto[1]	auto[1]	auto[1]	55	1		T214	1		T215	2		T308	1
all_values[5]	auto[0]	auto[0]	auto[0]	61	1		T214	3		T309	1		T310	2
all_values[5]	auto[0]	auto[0]	auto[1]	24	1		T215	1		T309	1		T286	1
all_values[5]	auto[0]	auto[1]	auto[0]	42	1		T213	3		T308	1		T310	1
all_values[5]	auto[0]	auto[1]	auto[1]	31	1		T214	2		T215	1		T308	1
all_values[5]	auto[1]	auto[0]	auto[1]	55	1		T214	1		T215	4		T308	3
all_values[5]	auto[1]	auto[1]	auto[1]	62	1		T213	1		T214	1		T215	1
all_values[6]	auto[0]	auto[0]	auto[0]	49	1		T215	2		T308	1		T309	3
all_values[6]	auto[0]	auto[0]	auto[1]	22	1		T214	1		T310	2		T285	1
all_values[6]	auto[0]	auto[1]	auto[0]	42	1		T214	1		T286	1		T311	2
all_values[6]	auto[0]	auto[1]	auto[1]	43	1		T213	2		T214	1		T215	2
all_values[6]	auto[1]	auto[0]	auto[1]	57	1		T213	2		T214	3		T215	1
all_values[6]	auto[1]	auto[1]	auto[1]	62	1		T214	1		T215	2		T308	1
all_values[7]	auto[0]	auto[0]	auto[0]	105	1		T213	2		T214	5		T215	3
all_values[7]	auto[0]	auto[1]	auto[0]	59	1		T213	1		T215	1		T308	3
all_values[7]	auto[1]	auto[0]	auto[1]	59	1		T214	2		T215	2		T308	1
all_values[7]	auto[1]	auto[1]	auto[1]	52	1		T213	1		T215	1		T308	2
all_values[8]	auto[0]	auto[0]	auto[0]	83	1		T213	1		T214	2		T215	3
all_values[8]	auto[0]	auto[1]	auto[0]	76	1		T213	1		T214	2		T308	2
all_values[8]	auto[1]	auto[0]	auto[1]	60	1		T213	1		T214	1		T215	4
all_values[8]	auto[1]	auto[1]	auto[1]	56	1		T213	1		T214	2		T308	1
all_values[9]	auto[0]	auto[0]	auto[0]	62	1		T213	2		T214	1		T215	3
all_values[9]	auto[0]	auto[0]	auto[1]	30	1		T214	1		T308	2		T309	1
all_values[9]	auto[0]	auto[1]	auto[0]	61	1		T215	3		T308	1		T309	1
all_values[9]	auto[0]	auto[1]	auto[1]	21	1		T308	1		T309	1		T310	2
all_values[9]	auto[1]	auto[0]	auto[1]	51	1		T213	2		T214	2		T215	1
all_values[9]	auto[1]	auto[1]	auto[1]	50	1		T214	3		T308	1		T310	2
all_values[10]	auto[0]	auto[0]	auto[0]	49	1		T214	1		T215	2		T308	1
all_values[10]	auto[0]	auto[0]	auto[1]	28	1		T213	1		T214	1		T308	1
all_values[10]	auto[0]	auto[1]	auto[0]	40	1		T213	2		T214	1		T309	1
all_values[10]	auto[0]	auto[1]	auto[1]	25	1		T214	1		T215	1		T312	1
all_values[10]	auto[1]	auto[0]	auto[1]	79	1		T213	1		T214	3		T308	3
all_values[10]	auto[1]	auto[1]	auto[1]	54	1		T215	4		T308	2		T309	1
all_values[11]	auto[0]	auto[0]	auto[0]	59	1		T214	1		T308	2		T310	3
all_values[11]	auto[0]	auto[0]	auto[1]	25	1		T214	1		T215	1		T308	1
all_values[11]	auto[0]	auto[1]	auto[0]	67	1		T213	3		T214	3		T215	3
all_values[11]	auto[0]	auto[1]	auto[1]	23	1		T286	1		T311	1		T313	2
all_values[11]	auto[1]	auto[0]	auto[1]	59	1		T214	2		T215	2		T310	1
all_values[11]	auto[1]	auto[1]	auto[1]	42	1		T213	1		T215	1		T308	1
all_values[12]	auto[0]	auto[0]	auto[0]	60	1		T214	1		T215	2		T309	2
all_values[12]	auto[0]	auto[0]	auto[1]	26	1		T214	1		T308	1		T314	2
all_values[12]	auto[0]	auto[1]	auto[0]	36	1		T310	2		T285	5		T286	1
all_values[12]	auto[0]	auto[1]	auto[1]	29	1		T213	2		T286	1		T313	1
all_values[12]	auto[1]	auto[0]	auto[1]	73	1		T213	2		T214	1		T215	5
all_values[12]	auto[1]	auto[1]	auto[1]	51	1		T214	4		T308	3		T310	1
all_values[13]	auto[0]	auto[0]	auto[0]	55	1		T215	2		T308	4		T310	3
all_values[13]	auto[0]	auto[0]	auto[1]	26	1		T214	1		T285	3		T286	2
all_values[13]	auto[0]	auto[1]	auto[0]	38	1		T213	3		T215	1		T308	1
all_values[13]	auto[0]	auto[1]	auto[1]	37	1		T215	1		T312	2		T314	1
all_values[13]	auto[1]	auto[0]	auto[1]	68	1		T214	4		T215	1		T308	1
all_values[13]	auto[1]	auto[1]	auto[1]	51	1		T213	1		T214	2		T215	2
all_values[14]	auto[0]	auto[0]	auto[0]	57	1		T214	2		T215	2		T308	1
all_values[14]	auto[0]	auto[0]	auto[1]	35	1		T308	1		T310	1		T286	1
all_values[14]	auto[0]	auto[1]	auto[0]	46	1		T213	2		T215	1		T308	1
all_values[14]	auto[0]	auto[1]	auto[1]	29	1		T214	3		T215	1		T308	1
all_values[14]	auto[1]	auto[0]	auto[1]	66	1		T214	2		T308	2		T309	2
all_values[14]	auto[1]	auto[1]	auto[1]	42	1		T213	2		T215	3		T308	1
all_values[15]	auto[0]	auto[0]	auto[0]	49	1		T215	2		T310	1		T286	2
all_values[15]	auto[0]	auto[0]	auto[1]	17	1		T309	1		T311	1		T315	1
all_values[15]	auto[0]	auto[1]	auto[0]	53	1		T214	2		T215	1		T310	2
all_values[15]	auto[0]	auto[1]	auto[1]	37	1		T213	1		T215	1		T308	6
all_values[15]	auto[1]	auto[0]	auto[1]	49	1		T214	3		T309	1		T285	1
all_values[15]	auto[1]	auto[1]	auto[1]	70	1		T213	3		T214	2		T215	3
all_values[16]	auto[0]	auto[0]	auto[0]	71	1		T214	3		T308	3		T309	1
all_values[16]	auto[0]	auto[0]	auto[1]	20	1		T213	2		T214	1		T286	1
all_values[16]	auto[0]	auto[1]	auto[0]	51	1		T308	1		T309	1		T285	1
all_values[16]	auto[0]	auto[1]	auto[1]	28	1		T213	1		T214	1		T215	2
all_values[16]	auto[1]	auto[0]	auto[1]	51	1		T214	1		T215	2		T308	1
all_values[16]	auto[1]	auto[1]	auto[1]	54	1		T213	1		T214	1		T215	3
all_values[17]	auto[0]	auto[0]	auto[0]	83	1		T213	3		T214	2		T308	3
all_values[17]	auto[0]	auto[1]	auto[0]	81	1		T214	4		T215	1		T308	2
all_values[17]	auto[1]	auto[0]	auto[1]	48	1		T213	1		T215	1		T308	1
all_values[17]	auto[1]	auto[1]	auto[1]	63	1		T214	1		T215	5		T308	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal